Series comparison

-[PULL 00/12] target-arm queue
+[PULL 00/30] target-arm queue
-Almost nothing in here is arm-related, but the target-arm
+The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:
 queue was convenient for these last minute bits and pieces
 for 5.0...
-thanks
+  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)
 -- PMM
 The following changes since commit 14e5526b51910efd62cd31cd95b49baca975c83f:
   Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-04-13 15:42:51 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200414
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216
-for you to fetch changes up to 84f82ddcbb4ac4ed04c8675e85155329f23184f0:
+for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:
-  Deprecate KVM support for AArch32 (2020-04-14 17:20:22 +0100)
+  tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)
 ----------------------------------------------------------------
-patch queue:
+target-arm queue:
- * Fix some problems that trip up Coverity's scanner
+ * Some mostly M-profile-related code cleanups
- * run-coverity-scan: New script automating the scan-and-upload process
+ * avocado: Retire the boot_linux.py AArch64 TCG tests
- * docs: Improve our gdbstub documentation
+ * hw/arm/smmuv3: Add GBPA register
- * configure: Honour --disable-werror for Sphinx
+ * arm/virt: don't try to spell out the accelerator
- * docs: Fix errors produced when building with Sphinx 3.0
+ * hw/arm: Attach PSPI module to NPCM7XX SoC
- * docs: Require Sphinx 1.6 or better
+ * Some cleanup/refactoring patches aiming towards
- * Add deprecation notice for KVM support on AArch32 hosts
+   allowing building Arm targets without CONFIG_TCG
 ----------------------------------------------------------------
-Peter Maydell (12):
+Alex Bennée (1):
-      osdep.h: Drop no-longer-needed Coverity workarounds
+      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
       thread.h: Fix Coverity version of qemu_cond_timedwait()
       thread.h: Remove trailing semicolons from Coverity qemu_mutex_lock() etc
       linux-user/flatload.c: Use "" for include of QEMU header target_flat.h
       scripts/run-coverity-scan: Script to run Coverity Scan build
       scripts/coverity-scan: Add Docker support
       docs: Improve our gdbstub documentation
       configure: Honour --disable-werror for Sphinx
       scripts/kernel-doc: Add missing close-paren in c:function directives
       kernel-doc: Use c:struct for Sphinx 3.0 and later
       docs: Require Sphinx 1.6 or better
       Deprecate KVM support for AArch32
- configure                                  |   9 +-
+Claudio Fontana (3):
- Makefile                                   |   2 +-
+      target/arm: rename handle_semihosting to tcg_handle_semihosting
- include/qemu/osdep.h                       |  14 -
+      target/arm: wrap psci call with tcg_enabled
- include/qemu/thread.h                      |  12 +-
+      target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
  linux-user/flatload.c                      |   2 +-
  MAINTAINERS                                |   5 +
  docs/conf.py                               |   6 +-
  docs/sphinx/kerneldoc.py                   |   1 +
  docs/system/deprecated.rst                 |   8 +
  docs/system/gdb.rst                        |  22 +-
  qemu-options.hx                            |  24 +-
  scripts/coverity-scan/coverity-scan.docker | 131 ++++++++++
  scripts/coverity-scan/run-coverity-scan    | 401 +++++++++++++++++++++++++++++
  scripts/kernel-doc                         |  18 +-
 files changed, 615 insertions(+), 40 deletions(-)
  create mode 100644 scripts/coverity-scan/coverity-scan.docker
  create mode 100755 scripts/coverity-scan/run-coverity-scan
+Cornelia Huck (1):
+      arm/virt: don't try to spell out the accelerator
+Fabiano Rosas (7):
+      target/arm: Move PC alignment check
+      target/arm: Move cpregs code out of cpu.h
+      tests/avocado: Skip tests that require a missing accelerator
+      tests/avocado: Tag TCG tests with accel:tcg
+      target/arm: Use "max" as default cpu for the virt machine with KVM
+      tests/qtest: arm-cpu-features: Match tests to required accelerators
+      tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
+Hao Wu (3):
+      MAINTAINERS: Add myself to maintainers and remove Havard
+      hw/ssi: Add Nuvoton PSPI Module
+      hw/arm: Attach PSPI module to NPCM7XX SoC
+Jean-Philippe Brucker (2):
+      hw/arm/smmu-common: Support 64-bit addresses
+      hw/arm/smmu-common: Fix TTB1 handling
+Mostafa Saleh (1):
+      hw/arm/smmuv3: Add GBPA register
+Philippe Mathieu-Daudé (12):
+      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
+      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
+      target/arm: Constify ID_PFR1 on user emulation
+      target/arm: Convert CPUARMState::eabi to boolean
+      target/arm: Avoid resetting CPUARMState::eabi field
+      target/arm: Restrict CPUARMState::gicv3state to sysemu
+      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
+      target/arm: Restrict CPUARMState::nvic to sysemu
+      target/arm: Store CPUARMState::nvic as NVICState*
+      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+ MAINTAINERS                            |   8 +-
+ docs/system/arm/nuvoton.rst            |   2 +-
+ hw/arm/smmuv3-internal.h               |   7 +
+ include/hw/arm/npcm7xx.h               |   2 +
+ include/hw/arm/smmu-common.h           |   2 -
+ include/hw/arm/smmuv3.h                |   1 +
+ include/hw/intc/armv7m_nvic.h          | 128 +++++++++++++++++-
+ include/hw/ssi/npcm_pspi.h             |  53 ++++++++
+ linux-user/user-internals.h            |   2 +-
+ target/arm/cpregs.h                    |  98 ++++++++++++++
+ target/arm/cpu.h                       | 228 ++-------------------------------
+ target/arm/internals.h                 |  14 --
+ hw/arm/npcm7xx.c                       |  25 +++-
+ hw/arm/smmu-common.c                   |   4 +-
+ hw/arm/smmuv3.c                        |  43 ++++++-
+ hw/arm/virt.c                          |  10 +-
+ hw/intc/armv7m_nvic.c                  |  38 ++----
+ hw/ssi/npcm_pspi.c                     | 221 ++++++++++++++++++++++++++++++++
+ linux-user/arm/cpu_loop.c              |   4 +-
+ target/arm/cpu.c                       |   5 +-
+ target/arm/cpu_tcg.c                   |   3 +
+ target/arm/helper.c                    |  31 +++--
+ target/arm/m_helper.c                  |  86 +++++++------
+ target/arm/machine.c                   |  18 +--
+ tests/qtest/arm-cpu-features.c         |  28 ++--
+ hw/arm/Kconfig                         |   1 +
+ hw/ssi/meson.build                     |   2 +-
+ hw/ssi/trace-events                    |   5 +
+ tests/avocado/avocado_qemu/__init__.py |   4 +
+ tests/avocado/boot_linux.py            |  48 ++-----
+ tests/avocado/boot_linux_console.py    |   1 +
+ tests/avocado/machine_aarch64_virt.py  |  63 ++++++++-
+ tests/avocado/reverse_debugging.py     |   8 ++
+ tests/qtest/meson.build                |   4 +-
+files changed, 798 insertions(+), 399 deletions(-)
+ create mode 100644 include/hw/ssi/npcm_pspi.h
+ create mode 100644 hw/ssi/npcm_pspi.c

-[PULL 09/12] scripts/kernel-doc: Add missing close-paren in c:function directives
+[PULL 01/30] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
-When kernel-doc generates a 'c:function' directive for a function
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 one of whose arguments is a function pointer, it fails to print
 the close-paren after the argument list of the function pointer
 argument, for instance in the memory API documentation:
   .. c:function:: void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp)
-which should have a ')' after the 'void *host' which is the
+Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
-last argument to 'resized'.
+similarly to automatic conversion from commit 8063396bf3
 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
-Older versions of Sphinx don't try to parse the argumnet
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-to c:function, but Sphinx 3.0 does do this and will complain:
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230206223502.25122-2-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/intc/armv7m_nvic.h | 5 +----
 file changed, 1 insertion(+), 4 deletions(-)
-  /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:834: WARNING: Error in declarator or parameters
+diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
-  Invalid C declaration: Expecting "," or ")" in parameters, got "EOF". [error at 208]
+index XXXXXXX..XXXXXXX 100644
-    void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp)
+--- a/include/hw/intc/armv7m_nvic.h
-    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------^
++++ b/include/hw/intc/armv7m_nvic.h
+@@ -XXX,XX +XXX,XX @@
-Add the missing close-paren.
+ #include "qom/object.h"
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+ #define TYPE_NVIC "armv7m_nvic"
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+-
-Message-id: 20200411182934.28678-3-peter.maydell@linaro.org
+-typedef struct NVICState NVICState;
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
----
+-                         TYPE_NVIC)
- scripts/kernel-doc | 2 +-
++OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
-file changed, 1 insertion(+), 1 deletion(-)
+ /* Highest permitted number of exceptions (architectural limit) */
-diff --git a/scripts/kernel-doc b/scripts/kernel-doc
+ #define NVIC_MAX_VECTORS 512
 index XXXXXXX..XXXXXXX 100755
 --- a/scripts/kernel-doc
 +++ b/scripts/kernel-doc
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
      if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
          # pointer-to-function
 -        print $1 . $parameter . ") (" . $2;
 +        print $1 . $parameter . ") (" . $2 . ")";
      } else {
          print $type . " " . $parameter;
      }
 --
-.20.1
+.34.1

-New patch
+[PULL 02/30] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-3-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/m_helper.c | 11 ++++++++---
+file changed, 8 insertions(+), 3 deletions(-)
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return 0;
+ }
+-#else
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    return ARMMMUIdx_MUser;
++}
++
++#else /* !CONFIG_USER_ONLY */
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-#endif /* !CONFIG_USER_ONLY */
+-
+ ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                               bool secstate, bool priv, bool negpri)
+ {
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+ }
++
++#endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 03/30] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
+are only used for system emulation in m_helper.c.
+Move the definitions to avoid prototype forward declarations.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-4-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h | 14 --------
+ target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
+files changed, 37 insertions(+), 51 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
+ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
+-/*
+- * Return the MMU index for a v7M CPU with all relevant information
+- * manually specified.
+- */
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+-                              bool secstate, bool priv, bool negpri);
+-
+-/*
+- * Return the MMU index for a v7M CPU in the specified security and
+- * privilege state.
+- */
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+-                                                bool secstate, bool priv);
+-
+ /* Return the MMU index for a v7M CPU in the specified security state */
+ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+ #else /* !CONFIG_USER_ONLY */
++static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
++                                     bool secstate, bool priv, bool negpri)
++{
++    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
++
++    if (priv) {
++        mmu_idx |= ARM_MMU_IDX_M_PRIV;
++    }
++
++    if (negpri) {
++        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
++    }
++
++    if (secstate) {
++        mmu_idx |= ARM_MMU_IDX_M_S;
++    }
++
++    return mmu_idx;
++}
++
++static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
++                                                       bool secstate, bool priv)
++{
++    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
++
++    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
++}
++
++/* Return the MMU index for a v7M CPU in the specified security state */
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    bool priv = arm_v7m_is_handler_mode(env) ||
++        !(env->v7m.control[secstate] & 1);
++
++    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
++}
++
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+  * generated during the stacking are treated.
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+-                              bool secstate, bool priv, bool negpri)
+-{
+-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+-
+-    if (priv) {
+-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+-    }
+-
+-    if (negpri) {
+-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+-    }
+-
+-    if (secstate) {
+-        mmu_idx |= ARM_MMU_IDX_M_S;
+-    }
+-
+-    return mmu_idx;
+-}
+-
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+-                                                bool secstate, bool priv)
+-{
+-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+-
+-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+-}
+-
+-/* Return the MMU index for a v7M CPU in the specified security state */
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+-{
+-    bool priv = arm_v7m_is_handler_mode(env) ||
+-        !(env->v7m.control[secstate] & 1);
+-
+-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+-}
+-
+ #endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-[PULL 08/12] configure: Honour --disable-werror for Sphinx
+[PULL 04/30] target/arm: Constify ID_PFR1 on user emulation
-If we are not making warnings fatal for compilation, make them
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 non-fatal when building the Sphinx documentation also.  (For instance
 Sphinx 3.0 warns about some constructs that older versions were happy
 with, which is a build failure if we use the warnings-as-errors
 flag.)
-This provides a workaround at least for LP:1872113.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230206223502.25122-5-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 12 ++++++++++--
 file changed, 10 insertions(+), 2 deletions(-)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/target/arm/helper.c b/target/arm/helper.c
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+index XXXXXXX..XXXXXXX 100644
-Message-id: 20200411182934.28678-2-peter.maydell@linaro.org
+--- a/target/arm/helper.c
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
++++ b/target/arm/helper.c
----
+@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
- configure | 9 ++++++++-
+     }
  Makefile  | 2 +-
 files changed, 9 insertions(+), 2 deletions(-)
 diff --git a/configure b/configure
 index XXXXXXX..XXXXXXX 100755
 --- a/configure
 +++ b/configure
@@ -XXX,XX +XXX,XX @@ if check_include sys/kcov.h ; then
      kcov=yes
  fi
 +# If we're making warnings fatal, apply this to Sphinx runs as well
 +sphinx_werror=""
 +if test "$werror" = "yes"; then
 +    sphinx_werror="-W"
 +fi
 +
  # Check we have a new enough version of sphinx-build
  has_sphinx_build() {
      # This is a bit awkward but works: create a trivial document and
@@ -XXX,XX +XXX,XX @@ has_sphinx_build() {
      # sphinx-build doesn't exist at all or if it is too old.
      mkdir -p "$TMPDIR1/sphinx"
      touch "$TMPDIR1/sphinx/index.rst"
 -    "$sphinx_build" -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1
 +    "$sphinx_build" $sphinx_werror -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1
  }
- # Check if tools are available to build documentation.
++#ifndef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ echo "INSTALL_PROG=$install -c -m 0755" >> $config_host_mak
+ /*
- echo "INSTALL_LIB=$install -c -m 0644" >> $config_host_mak
+  * We don't know until after realize whether there's a GICv3
- echo "PYTHON=$python" >> $config_host_mak
+  * attached, and that is what registers the gicv3 sysregs.
- echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak
+@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
-+echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak
+     return pfr1;
- echo "GENISOIMAGE=$genisoimage" >> $config_host_mak
+ }
- echo "CC=$cc" >> $config_host_mak
- if $iasl -h > /dev/null 2>&1; then
+-#ifndef CONFIG_USER_ONLY
-diff --git a/Makefile b/Makefile
+ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/Makefile
+     ARMCPU *cpu = env_archcpu(env);
-+++ b/Makefile
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ sphinxdocs: $(MANUAL_BUILDDIR)/devel/index.html \
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
- # Note the use of different doctree for each (manual, builder) tuple;
+               .access = PL1_R, .type = ARM_CP_NO_RAW,
- # this works around Sphinx not handling parallel invocation on
+               .accessfn = access_aa32_tid3,
- # a single doctree: https://github.com/sphinx-doc/sphinx/issues/2946
++#ifdef CONFIG_USER_ONLY
--build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) -W -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1")
++              .type = ARM_CP_CONST,
-+build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) $(SPHINX_WERROR) -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1")
++              .resetvalue = cpu->isar.id_pfr1,
- # We assume all RST files in the manual's directory are used in it
++#else
- manual-deps = $(wildcard $(SRC_PATH)/docs/$1/*.rst $(SRC_PATH)/docs/$1/*/*.rst) \
++              .type = ARM_CP_NO_RAW,
-               $(SRC_PATH)/docs/defs.rst.inc \
++              .accessfn = access_aa32_tid3,
                .readfn = id_pfr1_read,
 -              .writefn = arm_cp_write_ignore },
 +              .writefn = arm_cp_write_ignore
 +#endif
 +            },
              { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
                .access = PL1_R, .type = ARM_CP_CONST,
 --
-.20.1
+.34.1

-[PULL 12/12] Deprecate KVM support for AArch32
+[PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean
-The Linux kernel has dropped support for allowing 32-bit Arm systems
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 to host KVM guests (kernel commit 541ad0150ca4aa663a2, which just
 landed upstream in the 5.7 merge window).  Mark QEMU's support for
 this configuration as deprecated, so that we can delete that support
 code in 5.2.
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-6-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Jones <drjones@redhat.com>
 ---
- docs/system/deprecated.rst | 8 ++++++++
+ linux-user/user-internals.h | 2 +-
-file changed, 8 insertions(+)
+ target/arm/cpu.h            | 2 +-
  linux-user/arm/cpu_loop.c   | 4 ++--
 files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
+diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/deprecated.rst
+--- a/linux-user/user-internals.h
-+++ b/docs/system/deprecated.rst
++++ b/linux-user/user-internals.h
-@@ -XXX,XX +XXX,XX @@ The ``compat`` property used to set backwards compatibility modes for
+@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
- the processor has been deprecated. The ``max-cpu-compat`` property of
+ #ifdef TARGET_ARM
- the ``pseries`` machine type should be used instead.
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
+ {
-+KVM guest support on 32-bit Arm hosts (since 5.0)
+-    return cpu_env->eabi == 1;
-+'''''''''''''''''''''''''''''''''''''''''''''''''
++    return cpu_env->eabi;
-+
+ }
-+The Linux kernel has dropped support for allowing 32-bit Arm systems
+ #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
-+to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
-+its support for this configuration and will remove it in a future version.
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-+Running 32-bit guests on a 64-bit Arm host remains supported.
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/target/arm/cpu.h
- System emulator devices
++++ b/target/arm/cpu.h
- -----------------------
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
  #if defined(CONFIG_USER_ONLY)
      /* For usermode syscall translation.  */
 -    int eabi;
 +    bool eabi;
  #endif
      struct CPUBreakpoint *cpu_breakpoint[16];
 diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/arm/cpu_loop.c
 +++ b/linux-user/arm/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
              break;
          case EXCP_SWI:
              {
 -                env->eabi = 1;
 +                env->eabi = true;
                  /* system call */
                  if (env->thumb) {
                      /* Thumb is always EABI style with syscall number in r7 */
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
                           * > 0xfffff and are handled below as out-of-range.
                           */
                          n ^= ARM_SYSCALL_BASE;
 -                        env->eabi = 0;
 +                        env->eabi = false;
                      }
                  }
 --
-.20.1
+.34.1

-New patch
+[PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Although the 'eabi' field is only used in user emulation where
+CPU reset doesn't occur, it doesn't belong to the area to reset.
+Move it after the 'end_reset_fields' for consistency.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-7-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 9 ++++-----
+file changed, 4 insertions(+), 5 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     ARMVectorReg zarray[ARM_MAX_VQ * 16];
+ #endif
+-#if defined(CONFIG_USER_ONLY)
+-    /* For usermode syscall translation.  */
+-    bool eabi;
+-#endif
+-
+     struct CPUBreakpoint *cpu_breakpoint[16];
+     struct CPUWatchpoint *cpu_watchpoint[16];
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
++#if defined(CONFIG_USER_ONLY)
++    /* For usermode syscall translation.  */
++    bool eabi;
++#endif /* CONFIG_USER_ONLY */
+ #ifdef TARGET_TAGGED_ADDRESSES
+     /* Linux syscall tagged address support */
+--
+.34.1

-New patch
+[PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-8-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     void *nvic;
+     const struct arm_boot_info *boot_info;
++#if !defined(CONFIG_USER_ONLY)
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+-#if defined(CONFIG_USER_ONLY)
++#else /* CONFIG_USER_ONLY */
+     /* For usermode syscall translation.  */
+     bool eabi;
+ #endif /* CONFIG_USER_ONLY */
+--
+.34.1

-[PULL 04/12] linux-user/flatload.c: Use "" for include of QEMU header target_flat.h
+[PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu
-The target_flat.h file is a QEMU header, so we should include it using
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 quotes, not angle brackets.
-Coverity otherwise is unable to find the header:
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-"../linux-user/flatload.c", line 40: error #1712: cannot open source file
+Message-id: 20230206223502.25122-9-philmd@linaro.org
           "target_flat.h"
   #include <target_flat.h>
                           ^
 because the relevant directory is only on the -iquote path, not the -I path.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200319193323.2038-5-peter.maydell@linaro.org
 ---
- linux-user/flatload.c | 2 +-
+ target/arm/cpu.h | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/linux-user/flatload.c b/linux-user/flatload.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/flatload.c
+--- a/target/arm/cpu.h
-+++ b/linux-user/flatload.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     } sau;
- #include "qemu.h"
- #include "flat.h"
+     void *nvic;
--#include <target_flat.h>
+-    const struct arm_boot_info *boot_info;
-+#include "target_flat.h"
+ #if !defined(CONFIG_USER_ONLY)
++    const struct arm_boot_info *boot_info;
- //#define DEBUG
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
  #else /* CONFIG_USER_ONLY */
 --
-.20.1
+.34.1

-[PULL 02/12] thread.h: Fix Coverity version of qemu_cond_timedwait()
+[PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu
-For Coverity's benefit, we provide simpler versions of functions like
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 qemu_mutex_lock(), qemu_cond_wait() and qemu_cond_timedwait().  When
 we added qemu_cond_timedwait() in commit 3dcc9c6ec4ea, a cut and
 paste error meant that the Coverity version of qemu_cond_timedwait()
 was using the wrong _impl function, which makes the Coverity parser
 complain:
-"/qemu/include/qemu/thread.h", line 159: warning #140: too many arguments in
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-          function call
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-      return qemu_cond_timedwait(cond, mutex, ms);
+Message-id: 20230206223502.25122-10-philmd@linaro.org
              ^
 "/qemu/include/qemu/thread.h", line 159: warning #120: return value type does
           not match the function type
       return qemu_cond_timedwait(cond, mutex, ms);
              ^
 "/qemu/include/qemu/thread.h", line 156: warning #1563: function
           "qemu_cond_timedwait" not emitted, consider modeling it or review
           parse diagnostics to improve fidelity
   static inline bool (qemu_cond_timedwait)(QemuCond *cond, QemuMutex *mutex,
                       ^
 These aren't fatal, but reduce the scope of the analysis. Fix the error.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200319193323.2038-3-peter.maydell@linaro.org
 ---
- include/qemu/thread.h | 2 +-
+ target/arm/cpu.h | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/include/qemu/thread.h b/include/qemu/thread.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/qemu/thread.h
+--- a/target/arm/cpu.h
-+++ b/include/qemu/thread.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func;
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
- #define qemu_cond_wait(c, m)                                            \
+         uint32_t ctrl;
-             qemu_cond_wait_impl(c, m, __FILE__, __LINE__);
+     } sau;
- #define qemu_cond_timedwait(c, m, ms)                                   \
--            qemu_cond_wait_impl(c, m, ms, __FILE__, __LINE__);
+-    void *nvic;
-+            qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__);
+ #if !defined(CONFIG_USER_ONLY)
- #else
++    void *nvic;
- #define qemu_mutex_lock(m) ({                                           \
+     const struct arm_boot_info *boot_info;
-             QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func);  \
+     /* Store GICv3CPUState to access from this struct */
      void *gicv3state;
 --
-.20.1
+.34.1

-New patch
+[PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 There is no point in using a void pointer to access the NVIC.
 Use the real type to avoid casting it while debugging.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230206223502.25122-11-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
  hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
  target/arm/cpu.c      |  1 +
  target/arm/m_helper.c |  2 +-
 files changed, 39 insertions(+), 48 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
  typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 +typedef struct NVICState NVICState;
 +
  typedef struct CPUArchState {
      /* Regs for current mode.  */
      uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
      } sau;
  #if !defined(CONFIG_USER_ONLY)
 -    void *nvic;
 +    NVICState *nvic;
      const struct arm_boot_info *boot_info;
      /* Store GICv3CPUState to access from this struct */
      void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
  /* Interface between CPU and Interrupt controller.  */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(void *opaque);
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
  #else
 -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
      return true;
  }
  #endif
  /**
   * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
   * exceptions (exceptions generated in the course of trying to take
   * a different exception).
   */
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
   * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
   * generated in the course of lazy stacking of FP registers.
   */
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_pending_irq_info: return highest priority pending
   *    exception, and whether it targets Secure state
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @pirq: set to pending exception number
   * @ptargets_secure: set to whether pending exception targets Secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
   * to true if the current highest priority pending exception should
   * be taken to Secure state, false for NS.
   */
 -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                        bool *ptargets_secure);
  /**
   * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Move the current highest priority pending exception from the pending
   * state to the active state, and update v7m.exception to indicate that
   * it is the exception currently being handled.
   */
 -void armv7m_nvic_acknowledge_irq(void *opaque);
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
  /**
   * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to complete
   * @secure: true if this exception was secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
   *           0 if there is still an irq active after this one was completed
   * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
   */
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
   * interrupt the current execution priority. This controls whether the
   * RDY bit for it in the FPCCR is set.
   */
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Returns: the raw execution priority as defined by the v8M architecture.
   * This is the execution priority minus the effects of AIRCR.PRIS,
   * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
   * (v8M ARM ARM I_PKLD.)
   */
 -int armv7m_nvic_raw_execution_priority(void *opaque);
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
  /**
   * armv7m_nvic_neg_prio_requested: return true if the requested execution
   * priority is negative for the specified security state.
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @secure: the security state to test
   * This corresponds to the pseudocode IsReqExecPriNeg().
   */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
  #else
 -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      return false;
  }
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
      return MIN(running, s->exception_prio);
  }
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      /* Return true if the requested execution priority is negative
       * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
       * mean we don't allow FAULTMASK_NS to actually make the execution
       * priority negative). Compare pseudocode IsReqExcPriNeg().
       */
 -    NVICState *s = opaque;
 -
      if (s->cpu->env.v7m.faultmask[secure]) {
          return true;
      }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      return false;
  }
 -bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return nvic_exec_prio(s) > nvic_pending_prio(s);
  }
 -int armv7m_nvic_raw_execution_priority(void *opaque)
 +int armv7m_nvic_raw_execution_priority(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return s->exception_prio;
  }
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
 +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec;
      assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
      }
  }
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
 +    do_armv7m_nvic_set_pending(s, irq, secure, false);
  }
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
 +    do_armv7m_nvic_set_pending(s, irq, secure, true);
  }
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
  {
      /*
       * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
       * whether we should escalate depends on the saved context
       * in the FPCCR register, not on the current state of the CPU/NVIC.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
  }
  /* Make pending IRQ active.  */
 -void armv7m_nvic_acknowledge_irq(void *opaque)
 +void armv7m_nvic_acknowledge_irq(NVICState *s)
  {
 -    NVICState *s = (NVICState *)opaque;
      CPUARMState *env = &s->cpu->env;
      const int pending = s->vectpending;
      const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
          exc_targets_secure(s, s->vectpending);
  }
 -void armv7m_nvic_get_pending_irq_info(void *opaque,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                        int *pirq, bool *ptargets_secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      const int pending = s->vectpending;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
      *pirq = pending;
  }
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec = NULL;
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
      return ret;
  }
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
  {
      /*
       * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
       * for non-banked exceptions secure is always false; for banked exceptions
       * it indicates which of the exceptions is required.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      int running = nvic_exec_prio(s);
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#include "hw/intc/armv7m_nvic.h"
  #endif
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
       * that we will need later in order to do lazy FP reg stacking.
       */
      bool is_secure = env->v7m.secure;
 -    void *nvic = env->nvic;
 +    NVICState *nvic = env->nvic;
      /*
       * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
       * are banked and we want to update the bit in the bank for the
 --
 .34.1

-New patch
+[PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 While dozens of files include "cpu.h", only 3 files require
 these NVIC helper declarations.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230206223502.25122-12-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
  target/arm/cpu.h              | 123 ----------------------------------
  target/arm/cpu.c              |   4 +-
  target/arm/cpu_tcg.c          |   3 +
  target/arm/m_helper.c         |   3 +
 files changed, 132 insertions(+), 124 deletions(-)
 diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/intc/armv7m_nvic.h
 +++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
      qemu_irq sysresetreq;
  };
 +/* Interface between CPU and Interrupt controller.  */
 +/**
 + * armv7m_nvic_set_pending: mark the specified exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Marks the specified exception as pending. Note that we will assert()
 + * if @secure is true and @irq does not specify one of the fixed set
 + * of architecturally banked exceptions.
 + */
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for derived
 + * exceptions (exceptions generated in the course of trying to take
 + * a different exception).
 + */
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 + * generated in the course of lazy stacking of FP registers.
 + */
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_pending_irq_info: return highest priority pending
 + *    exception, and whether it targets Secure state
 + * @s: the NVIC
 + * @pirq: set to pending exception number
 + * @ptargets_secure: set to whether pending exception targets Secure
 + *
 + * This function writes the number of the highest priority pending
 + * exception (the one which would be made active by
 + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 + * to true if the current highest priority pending exception should
 + * be taken to Secure state, false for NS.
 + */
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 +                                      bool *ptargets_secure);
 +/**
 + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 + * @s: the NVIC
 + *
 + * Move the current highest priority pending exception from the pending
 + * state to the active state, and update v7m.exception to indicate that
 + * it is the exception currently being handled.
 + */
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
 +/**
 + * armv7m_nvic_complete_irq: complete specified interrupt or exception
 + * @s: the NVIC
 + * @irq: the exception number to complete
 + * @secure: true if this exception was secure
 + *
 + * Returns: -1 if the irq was not active
 + *           1 if completing this irq brought us back to base (no active irqs)
 + *           0 if there is still an irq active after this one was completed
 + * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 + */
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Return whether an exception is "ready", i.e. whether the exception is
 + * enabled and is configured at a priority which would allow it to
 + * interrupt the current execution priority. This controls whether the
 + * RDY bit for it in the FPCCR is set.
 + */
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_raw_execution_priority: return the raw execution priority
 + * @s: the NVIC
 + *
 + * Returns: the raw execution priority as defined by the v8M architecture.
 + * This is the execution priority minus the effects of AIRCR.PRIS,
 + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 + * (v8M ARM ARM I_PKLD.)
 + */
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
 +/**
 + * armv7m_nvic_neg_prio_requested: return true if the requested execution
 + * priority is negative for the specified security state.
 + * @s: the NVIC
 + * @secure: the security state to test
 + * This corresponds to the pseudocode IsReqExecPriNeg().
 + */
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 +#else
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 +{
 +    return false;
 +}
 +#endif
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 +#else
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 +{
 +    return true;
 +}
 +#endif
 +
  #endif
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface between CPU and Interrupt controller.  */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 -#else
 -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 -{
 -    return true;
 -}
 -#endif
 -/**
 - * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Marks the specified exception as pending. Note that we will assert()
 - * if @secure is true and @irq does not specify one of the fixed set
 - * of architecturally banked exceptions.
 - */
 -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for derived
 - * exceptions (exceptions generated in the course of trying to take
 - * a different exception).
 - */
 -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 - * generated in the course of lazy stacking of FP registers.
 - */
 -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_pending_irq_info: return highest priority pending
 - *    exception, and whether it targets Secure state
 - * @s: the NVIC
 - * @pirq: set to pending exception number
 - * @ptargets_secure: set to whether pending exception targets Secure
 - *
 - * This function writes the number of the highest priority pending
 - * exception (the one which would be made active by
 - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 - * to true if the current highest priority pending exception should
 - * be taken to Secure state, false for NS.
 - */
 -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 -                                      bool *ptargets_secure);
 -/**
 - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @s: the NVIC
 - *
 - * Move the current highest priority pending exception from the pending
 - * state to the active state, and update v7m.exception to indicate that
 - * it is the exception currently being handled.
 - */
 -void armv7m_nvic_acknowledge_irq(NVICState *s);
 -/**
 - * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @s: the NVIC
 - * @irq: the exception number to complete
 - * @secure: true if this exception was secure
 - *
 - * Returns: -1 if the irq was not active
 - *           1 if completing this irq brought us back to base (no active irqs)
 - *           0 if there is still an irq active after this one was completed
 - * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 - */
 -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Return whether an exception is "ready", i.e. whether the exception is
 - * enabled and is configured at a priority which would allow it to
 - * interrupt the current execution priority. This controls whether the
 - * RDY bit for it in the FPCCR is set.
 - */
 -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @s: the NVIC
 - *
 - * Returns: the raw execution priority as defined by the v8M architecture.
 - * This is the execution priority minus the effects of AIRCR.PRIS,
 - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 - * (v8M ARM ARM I_PKLD.)
 - */
 -int armv7m_nvic_raw_execution_priority(NVICState *s);
 -/**
 - * armv7m_nvic_neg_prio_requested: return true if the requested execution
 - * priority is negative for the specified security state.
 - * @s: the NVIC
 - * @secure: the security state to test
 - * This corresponds to the pseudocode IsReqExecPriNeg().
 - */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 -#else
 -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 -{
 -    return false;
 -}
 -#endif
 -
  /* Interface for defining coprocessor registers.
   * Registers are defined in tables of arm_cp_reginfo structs
   * which are passed to define_arm_cp_regs().
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#ifdef CONFIG_TCG
  #include "hw/intc/armv7m_nvic.h"
 -#endif
 +#endif /* CONFIG_TCG */
 +#endif /* !CONFIG_USER_ONLY */
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
  #include "sysemu/hw_accel.h"
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/boards.h"
  #endif
  #include "cpregs.h"
 +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  /* Share AArch32 -cpu max features with AArch64. */
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
 +#if !defined(CONFIG_USER_ONLY)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                           uint32_t reg, uint32_t val)
 --
 .34.1

-New patch
+[PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
+From: Alex Bennée <alex.bennee@linaro.org>
 The two TCG tests for GICv2 and GICv3 are very heavy weight distros
 that take a long time to boot up, especially for an --enable-debug
 build. The total code coverage they give is:
   Overall coverage rate:
     lines......: 11.2% (59584 of 530123 lines)
     functions..: 15.0% (7436 of 49443 functions)
     branches...: 6.3% (19273 of 303933 branches)
 We already get pretty close to that with the machine_aarch64_virt
 tests which only does one full boot (~120s vs ~600s) of alpine. We
 expand the kernel+initrd boot (~8s) to test both GICs and also add an
 RNG device and a block device to generate a few IRQs and exercise the
 storage layer. With that we get to a coverage of:
   Overall coverage rate:
     lines......: 11.0% (58121 of 530123 lines)
     functions..: 14.9% (7343 of 49443 functions)
     branches...: 6.0% (18269 of 303933 branches)
 which I feel is close enough given the massive time saving. If we want
 to target any more sub-systems we can use lighter weight more directed
 tests.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Acked-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/avocado/boot_linux.py           | 48 ++++----------------
  tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 files changed, 65 insertions(+), 46 deletions(-)
 diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/boot_linux.py
 +++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
          self.launch_and_wait(set_up_ssh_connection=False)
 -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
 -# heavyweight. There are lighter weight distros which we use in the
 -# machine_aarch64_virt.py tests.
 +# For Aarch64 we only boot KVM tests in CI as booting the current
 +# Fedora OS in TCG tests is very heavyweight. There are lighter weight
 +# distros which we use in the machine_aarch64_virt.py tests.
  class BootLinuxAarch64(LinuxTest):
      """
      :avocado: tags=arch:aarch64
      :avocado: tags=machine:virt
 -    :avocado: tags=machine:gic-version=2
      """
      timeout = 720
 -    def add_common_args(self):
 -        self.vm.add_args('-bios',
 -                         os.path.join(BUILD_DIR, 'pc-bios',
 -                                      'edk2-aarch64-code.fd'))
 -        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 -        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv2(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv2
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=2")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv3(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv3
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=3")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
      def test_virt_kvm(self):
          """
          :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
          self.require_accelerator("kvm")
          self.vm.add_args("-accel", "kvm")
          self.vm.add_args("-machine", "virt,gic-version=host")
 -        self.add_common_args()
 +        self.vm.add_args('-bios',
 +                         os.path.join(BUILD_DIR, 'pc-bios',
 +                                      'edk2-aarch64-code.fd'))
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
          self.launch_and_wait(set_up_ssh_connection=False)
 diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/machine_aarch64_virt.py
 +++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
  import time
  import os
 +import logging
  from avocado_qemu import QemuSystemTest
  from avocado_qemu import wait_for_console_pattern
  from avocado_qemu import exec_command
  from avocado_qemu import BUILD_DIR
 +from avocado.utils import process
 +from avocado.utils.path import find_command
  class Aarch64VirtMachine(QemuSystemTest):
      KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
          self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 -    def test_aarch64_virt(self):
 +    def common_aarch64_virt(self, machine):
          """
 -        :avocado: tags=arch:aarch64
 -        :avocado: tags=machine:virt
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 +        Common code to launch basic virt machine with kernel+initrd
 +        and a scratch disk.
          """
 +        logger = logging.getLogger('aarch64_virt')
 +
          kernel_url = ('https://fileserver.linaro.org/s/'
                        'z6B2ARM7DQT3HWN/download')
 -
          kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
          kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                 'console=ttyAMA0')
          self.require_accelerator("tcg")
          self.vm.add_args('-cpu', 'max,pauth-impdef=on',
 +                         '-machine', machine,
                           '-accel', 'tcg',
                           '-kernel', kernel_path,
                           '-append', kernel_command_line)
 +
 +        # A RNG offers an easy way to generate a few IRQs
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object',
 +                         'rng-random,id=rng0,filename=/dev/urandom')
 +
 +        # Also add a scratch block device
 +        logger.info('creating scratch qcow2 image')
 +        image_path = os.path.join(self.workdir, 'scratch.qcow2')
 +        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
 +        if not os.path.exists(qemu_img):
 +            qemu_img = find_command('qemu-img', False)
 +        if qemu_img is False:
 +            self.cancel('Could not find "qemu-img", which is required to '
 +                        'create the temporary qcow2 image')
 +        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
 +        process.run(cmd)
 +
 +        # Add the device
 +        self.vm.add_args('-blockdev',
 +                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
 +        self.vm.add_args('-device',
 +                         'virtio-blk-device,drive=scratch')
 +
          self.vm.launch()
          self.wait_for_console_pattern('Welcome to Buildroot')
          time.sleep(0.1)
          exec_command(self, 'root')
          time.sleep(0.1)
 +        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
 +        time.sleep(0.1)
 +        exec_command(self, 'md5sum /dev/vda')
 +        time.sleep(0.1)
 +        exec_command(self, 'cat /proc/interrupts')
 +        time.sleep(0.1)
          exec_command(self, 'cat /proc/self/maps')
          time.sleep(0.1)
 +
 +    def test_aarch64_virt_gicv3(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic_version=3")
 +
 +    def test_aarch64_virt_gicv2(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic-version=2")
 --
 .34.1

-New patch
+[PULL 13/30] hw/arm/smmuv3: Add GBPA register
+From: Mostafa Saleh <smostafa@google.com>
+GBPA register can be used to globally abort all
+transactions.
+It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
+ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
+be zero(Do not abort incoming transactions).
+Other fields have default values of Use Incoming.
+If UPDATE is not set, the write is ignored. This is the only permitted
+behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
+As this patch adds a new state to the SMMU (GBPA), it is added
+in a new subsection for forward migration compatibility.
+GBPA is only migrated if its value is different from the reset value.
+It does this to be backward migration compatible if SW didn't write
+the register.
+Signed-off-by: Mostafa Saleh <smostafa@google.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230214094009.2445653-1-smostafa@google.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/smmuv3-internal.h |  7 +++++++
+ include/hw/arm/smmuv3.h  |  1 +
+ hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
+files changed, 50 insertions(+), 1 deletion(-)
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3-internal.h
++++ b/hw/arm/smmuv3-internal.h
+@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
+ REG32(CR1,                 0x28)
+ REG32(CR2,                 0x2c)
+ REG32(STATUSR,             0x40)
++REG32(GBPA,                0x44)
++    FIELD(GBPA, ABORT,        20, 1)
++    FIELD(GBPA, UPDATE,       31, 1)
++
++/* Use incoming. */
++#define SMMU_GBPA_RESET_VAL 0x1000
++
+ REG32(IRQ_CTRL,            0x50)
+     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
+     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
+diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmuv3.h
++++ b/include/hw/arm/smmuv3.h
+@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
+     uint32_t cr[3];
+     uint32_t cr0ack;
+     uint32_t statusr;
++    uint32_t gbpa;
+     uint32_t irq_ctrl;
+     uint32_t gerror;
+     uint32_t gerrorn;
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3.c
++++ b/hw/arm/smmuv3.c
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
+     s->gerror = 0;
+     s->gerrorn = 0;
+     s->statusr = 0;
++    s->gbpa = SMMU_GBPA_RESET_VAL;
+ }
+ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
+     qemu_mutex_lock(&s->mutex);
+     if (!smmu_enabled(s)) {
+-        status = SMMU_TRANS_DISABLE;
++        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
++            status = SMMU_TRANS_ABORT;
++        } else {
++            status = SMMU_TRANS_DISABLE;
++        }
+         goto epilogue;
+     }
+@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
+     case A_GERROR_IRQ_CFG2:
+         s->gerror_irq_cfg2 = data;
+         return MEMTX_OK;
++    case A_GBPA:
++        /*
++         * If UPDATE is not set, the write is ignored. This is the only
++         * permitted behavior in SMMUv3.2 and later.
++         */
++        if (data & R_GBPA_UPDATE_MASK) {
++            /* Ignore update bit as write is synchronous. */
++            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
++        }
++        return MEMTX_OK;
+     case A_STRTAB_BASE: /* 64b */
+         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
+         return MEMTX_OK;
+@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
+     case A_STATUSR:
+         *data = s->statusr;
+         return MEMTX_OK;
++    case A_GBPA:
++        *data = s->gbpa;
++        return MEMTX_OK;
+     case A_IRQ_CTRL:
+     case A_IRQ_CTRL_ACK:
+         *data = s->irq_ctrl;
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
+     },
+ };
++static bool smmuv3_gbpa_needed(void *opaque)
++{
++    SMMUv3State *s = opaque;
++
++    /* Only migrate GBPA if it has different reset value. */
++    return s->gbpa != SMMU_GBPA_RESET_VAL;
++}
++
++static const VMStateDescription vmstate_gbpa = {
++    .name = "smmuv3/gbpa",
++    .version_id = 1,
++    .minimum_version_id = 1,
++    .needed = smmuv3_gbpa_needed,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINT32(gbpa, SMMUv3State),
++        VMSTATE_END_OF_LIST()
++    }
++};
++
+ static const VMStateDescription vmstate_smmuv3 = {
+     .name = "smmuv3",
+     .version_id = 1,
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
+         VMSTATE_END_OF_LIST(),
+     },
++    .subsections = (const VMStateDescription * []) {
++        &vmstate_gbpa,
++        NULL
++    }
+ };
+ static void smmuv3_instance_init(Object *obj)
+--
+.34.1

-New patch
+[PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since commit acc0b8b05a when running the ZynqMP ZCU102 board with
+a QEMU configured using --without-default-devices, we get:
+  $ qemu-system-aarch64 -M xlnx-zcu102
+  qemu-system-aarch64: missing object type 'usb_dwc3'
+  Abort trap: 6
+Fix by adding the missing Kconfig dependency.
+Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230216092327.2203-1-philmd@linaro.org
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/Kconfig | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
+     select XLNX_CSU_DMA
+     select XLNX_ZYNQMP
+     select XLNX_ZDMA
++    select USB_DWC3
+ config XLNX_VERSAL
+     bool
+--
+.34.1

-New patch
+[PULL 15/30] arm/virt: don't try to spell out the accelerator
+From: Cornelia Huck <cohuck@redhat.com>
+Just use current_accel_name() directly.
+Signed-off-by: Cornelia Huck <cohuck@redhat.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/virt.c | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Security extensions (TrustZone) to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Virtualization extensions to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "MTE to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+--
+.34.1

-New patch
+[PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard
+From: Hao Wu <wuhaotsh@google.com>
+Havard is no longer working on the Nuvoton systems for a while
+and won't be able to do any work on it in the future. So I'll
+take over maintaining the Nuvoton system from him.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Acked-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-2-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h
+ F: docs/system/arm/musicpal.rst
+ Nuvoton NPCM7xx
+-M: Havard Skinnemoen <hskinnemoen@google.com>
+ M: Tyrone Ting <kfting@nuvoton.com>
++M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+ F: hw/*/npcm7xx*
+--
+.34.1

-[PULL 05/12] scripts/run-coverity-scan: Script to run Coverity Scan build
+[PULL 17/30] hw/ssi: Add Nuvoton PSPI Module
-Add a new script to automate the process of running the Coverity
+From: Hao Wu <wuhaotsh@google.com>
 Scan build tools and uploading the resulting tarball to the
 website.
-This is intended eventually to be driven from Travis,
+Nuvoton's PSPI is a general purpose SPI module which enables
-but it can be run locally, if you are a maintainer of the
+connections to SPI-based peripheral devices.
 QEMU project on the Coverity Scan website and have the secret
 upload token.
-The script must be run on a Fedora 30 system.  Support for using a
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-Docker container is added in a following commit.
+Reviewed-by: Chris Rauer <crauer@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20200319193323.2038-6-peter.maydell@linaro.org
 ---
- MAINTAINERS                             |   5 +
+ MAINTAINERS                |   6 +-
- scripts/coverity-scan/run-coverity-scan | 311 ++++++++++++++++++++++++
+ include/hw/ssi/npcm_pspi.h |  53 +++++++++
-files changed, 316 insertions(+)
+ hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
- create mode 100755 scripts/coverity-scan/run-coverity-scan
+ hw/ssi/meson.build         |   2 +-
  hw/ssi/trace-events        |   5 +
 files changed, 283 insertions(+), 4 deletions(-)
  create mode 100644 include/hw/ssi/npcm_pspi.h
  create mode 100644 hw/ssi/npcm_pspi.c
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ M: Markus Armbruster <armbru@redhat.com>
+@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
  M: Hao Wu <wuhaotsh@google.com>
  L: qemu-arm@nongnu.org
  S: Supported
- F: scripts/coverity-model.c
+-F: hw/*/npcm7xx*
+-F: include/hw/*/npcm7xx*
-+Coverity Scan integration
+-F: tests/qtest/npcm7xx*
-+M: Peter Maydell <peter.maydell@linaro.org>
++F: hw/*/npcm*
-+S: Maintained
++F: include/hw/*/npcm*
-+F: scripts/coverity-scan/
++F: tests/qtest/npcm*
-+
+ F: pc-bios/npcm7xx_bootrom.bin
- Device Tree
+ F: roms/vbootrom
- M: Alistair Francis <alistair.francis@wdc.com>
+ F: docs/system/arm/nuvoton.rst
- R: David Gibson <david@gibson.dropbear.id.au>
+diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
-diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan
+new file mode 100644
 new file mode 100755
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/scripts/coverity-scan/run-coverity-scan
++++ b/include/hw/ssi/npcm_pspi.h
 @@ -XXX,XX +XXX,XX @@
-+#!/bin/sh -e
++/*
-+
++ * Nuvoton Peripheral SPI Module
-+# Upload a created tarball to Coverity Scan, as per
++ *
-+# https://scan.coverity.com/projects/qemu/builds/new
++ * Copyright 2023 Google LLC
-+
++ *
-+# This work is licensed under the terms of the GNU GPL version 2,
++ * This program is free software; you can redistribute it and/or modify it
-+# or (at your option) any later version.
++ * under the terms of the GNU General Public License as published by the
-+# See the COPYING file in the top-level directory.
++ * Free Software Foundation; either version 2 of the License, or
-+#
++ * (at your option) any later version.
-+# Copyright (c) 2017-2020 Linaro Limited
++ *
-+# Written by Peter Maydell
++ * This program is distributed in the hope that it will be useful, but WITHOUT
-+
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+# Note that this script will automatically download and
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+# run the (closed-source) coverity build tools, so don't
++ * for more details.
-+# use it if you don't trust them!
++ */
-+
++#ifndef NPCM_PSPI_H
-+# This script assumes that you're running it from a QEMU source
++#define NPCM_PSPI_H
-+# tree, and that tree is a fresh clean one, because we do an in-tree
++
-+# build. (This is necessary so that the filenames that the Coverity
++#include "hw/ssi/ssi.h"
-+# Scan server sees are relative paths that match up with the component
++#include "hw/sysbus.h"
-+# regular expressions it uses; an out-of-tree build won't work for this.)
++
-+# The host machine should have as many of QEMU's dependencies
++/*
-+# installed as possible, for maximum coverity coverage.
++ * Number of registers in our device state structure. Don't change this without
-+
++ * incrementing the version_id in the vmstate.
-+# To do an upload you need to be a maintainer in the Coverity online
++ */
-+# service, and you will need to know the "Coverity token", which is a
++#define NPCM_PSPI_NR_REGS 3
-+# secret 8 digit hex string. You can find that from the web UI in the
++
-+# project settings, if you have maintainer access there.
++/**
-+
++ * NPCMPSPIState - Device state for one Flash Interface Unit.
-+# Command line options:
++ * @parent: System bus device.
-+#   --dry-run : run the tools, but don't actually do the upload
++ * @mmio: Memory region for register access.
-+#   --update-tools-only : update the cached copy of the tools, but don't run them
++ * @spi: The SPI bus mastered by this controller.
-+#   --tokenfile : file to read Coverity token from
++ * @regs: Register contents.
-+#   --version ver : specify version being analyzed (default: ask git)
++ * @irq: The interrupt request queue for this module.
-+#   --description desc : specify description of this version (default: ask git)
++ *
-+#   --srcdir : QEMU source tree to analyze (default: current working dir)
++ * Each PSPI has a shared bank of registers, and controls up to four chip
-+#   --results-tarball : path to copy the results tarball to (default: don't
++ * selects. Each chip select has a dedicated memory region which may be used to
-+#                       copy it anywhere, just upload it)
++ * read and write the flash connected to that chip select as if it were memory.
-+#
++ */
-+# User-specifiable environment variables:
++typedef struct NPCMPSPIState {
-+#  COVERITY_TOKEN -- Coverity token
++    SysBusDevice parent;
-+#  COVERITY_EMAIL -- the email address to use for uploads (default:
++
-+#                    looks at your git user.email config)
++    MemoryRegion mmio;
-+#  COVERITY_BUILD_CMD -- make command (default: 'make -jN' where N is
++
-+#                    number of CPUs as determined by 'nproc')
++    SSIBus *spi;
-+#  COVERITY_TOOL_BASE -- set to directory to put coverity tools
++    uint16_t regs[NPCM_PSPI_NR_REGS];
-+#                        (default: /tmp/coverity-tools)
++    qemu_irq irq;
-+#
++} NPCMPSPIState;
-+# You must specify the token, either by environment variable or by
++
-+# putting it in a file and using --tokenfile. Everything else has
++#define TYPE_NPCM_PSPI "npcm-pspi"
-+# a reasonable default if this is run from a git tree.
++OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
 +
-+check_upload_permissions() {
++#endif /* NPCM_PSPI_H */
-+    # Check whether we can do an upload to the server; will exit the script
+diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
-+    # with status 1 if the check failed (usually a bad token);
+new file mode 100644
-+    # will exit the script with status 0 if the check indicated that we
+index XXXXXXX..XXXXXXX
-+    # can't upload yet (ie we are at quota)
+--- /dev/null
-+    # Assumes that PROJTOKEN, PROJNAME and DRYRUN have been initialized.
++++ b/hw/ssi/npcm_pspi.c
-+
+@@ -XXX,XX +XXX,XX @@
-+    echo "Checking upload permissions..."
++/*
-+
++ * Nuvoton NPCM Peripheral SPI Module (PSPI)
-+    if ! up_perm="$(wget https://scan.coverity.com/api/upload_permitted --post-data "token=$PROJTOKEN&project=$PROJNAME" -q -O -)"; then
++ *
-+        echo "Coverity Scan API access denied: bad token?"
++ * Copyright 2023 Google LLC
-+        exit 1
++ *
-+    fi
++ * This program is free software; you can redistribute it and/or modify it
-+
++ * under the terms of the GNU General Public License as published by the
-+    # Really up_perm is a JSON response with either
++ * Free Software Foundation; either version 2 of the License, or
-+    # {upload_permitted:true} or {next_upload_permitted_at:<date>}
++ * (at your option) any later version.
-+    # We do some hacky string parsing instead of properly parsing it.
++ *
-+    case "$up_perm" in
++ * This program is distributed in the hope that it will be useful, but WITHOUT
-+        *upload_permitted*true*)
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+            echo "Coverity Scan: upload permitted"
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+            ;;
++ * for more details.
-+        *next_upload_permitted_at*)
++ */
-+            if [ "$DRYRUN" = yes ]; then
++
-+                echo "Coverity Scan: upload quota reached, continuing dry run"
++#include "qemu/osdep.h"
-+            else
++
-+                echo "Coverity Scan: upload quota reached; stopping here"
++#include "hw/irq.h"
-+                # Exit success as this isn't a build error.
++#include "hw/registerfields.h"
-+                exit 0
++#include "hw/ssi/npcm_pspi.h"
-+            fi
++#include "migration/vmstate.h"
-+            ;;
++#include "qapi/error.h"
-+        *)
++#include "qemu/error-report.h"
-+            echo "Coverity Scan upload check: unexpected result $up_perm"
++#include "qemu/log.h"
-+            exit 1
++#include "qemu/module.h"
-+            ;;
++#include "qemu/units.h"
-+    esac
++
-+}
++#include "trace.h"
 +
-+
++REG16(PSPI_DATA, 0x0)
-+update_coverity_tools () {
++REG16(PSPI_CTL1, 0x2)
-+    # Check for whether we need to download the Coverity tools
++    FIELD(PSPI_CTL1, SPIEN, 0,  1)
-+    # (either because we don't have a copy, or because it's out of date)
++    FIELD(PSPI_CTL1, MOD,   2,  1)
-+    # Assumes that COVERITY_TOOL_BASE, PROJTOKEN and PROJNAME are set.
++    FIELD(PSPI_CTL1, EIR,   5,  1)
-+
++    FIELD(PSPI_CTL1, EIW,   6,  1)
-+    mkdir -p "$COVERITY_TOOL_BASE"
++    FIELD(PSPI_CTL1, SCM,   7,  1)
-+    cd "$COVERITY_TOOL_BASE"
++    FIELD(PSPI_CTL1, SCIDL, 8,  1)
-+
++    FIELD(PSPI_CTL1, SCDV,  9,  7)
-+    echo "Checking for new version of coverity build tools..."
++REG16(PSPI_STAT, 0x4)
-+    wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME&md5=1" -O coverity_tool.md5.new
++    FIELD(PSPI_STAT, BSY,  0,  1)
-+
++    FIELD(PSPI_STAT, RBF,  1,  1)
-+    if ! cmp -s coverity_tool.md5 coverity_tool.md5.new; then
++
-+        # out of date md5 or no md5: download new build tool
++static void npcm_pspi_update_irq(NPCMPSPIState *s)
-+        # blow away the old build tool
++{
-+        echo "Downloading coverity build tools..."
++    int level = 0;
-+        rm -rf coverity_tool coverity_tool.tgz
++
-+        wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME" -O coverity_tool.tgz
++    /* Only fire IRQ when the module is enabled. */
-+        if ! (cat coverity_tool.md5.new; echo "  coverity_tool.tgz") | md5sum -c --status; then
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
-+            echo "Downloaded tarball didn't match md5sum!"
++        /* Update interrupt as BSY is cleared. */
-+            exit 1
++        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
-+        fi
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
-+        # extract the new one, keeping it corralled in a 'coverity_tool' directory
++            level = 1;
-+        echo "Unpacking coverity build tools..."
++        }
-+        mkdir -p coverity_tool
++
-+        cd coverity_tool
++        /* Update interrupt as RBF is set. */
-+        tar xf ../coverity_tool.tgz
++        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
-+        cd ..
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
-+        mv coverity_tool.md5.new coverity_tool.md5
++            level = 1;
-+    fi
++        }
-+
++    }
-+    rm -f coverity_tool.md5.new
++    qemu_set_irq(s->irq, level);
 +}
 +
-+
++static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
-+# Check user-provided environment variables and arguments
++{
-+DRYRUN=no
++    uint16_t value = s->regs[R_PSPI_DATA];
-+UPDATE_ONLY=no
++
-+
++    /* Clear stat bits as the value are read out. */
-+while [ "$#" -ge 1 ]; do
++    s->regs[R_PSPI_STAT] = 0;
-+    case "$1" in
++
-+        --dry-run)
++    return value;
-+            shift
++}
-+            DRYRUN=yes
++
-+            ;;
++static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
-+        --update-tools-only)
++{
-+            shift
++    uint16_t value = 0;
-+            UPDATE_ONLY=yes
++
-+            ;;
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
-+        --version)
++        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
-+            shift
++    }
-+            if [ $# -eq 0 ]; then
++    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
-+                echo "--version needs an argument"
++    s->regs[R_PSPI_DATA] = value;
-+                exit 1
++
-+            fi
++    /* Mark data as available */
-+            VERSION="$1"
++    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
-+            shift
++}
-+            ;;
++
-+        --description)
++/* Control register read handler. */
-+            shift
++static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
-+            if [ $# -eq 0 ]; then
++                                    unsigned int size)
-+                echo "--description needs an argument"
++{
-+                exit 1
++    NPCMPSPIState *s = opaque;
-+            fi
++    uint16_t value;
-+            DESCRIPTION="$1"
++
-+            shift
++    switch (addr) {
-+            ;;
++    case A_PSPI_DATA:
-+        --tokenfile)
++        value = npcm_pspi_read_data(s);
-+            shift
++        break;
-+            if [ $# -eq 0 ]; then
++
-+                echo "--tokenfile needs an argument"
++    case A_PSPI_CTL1:
-+                exit 1
++        value = s->regs[R_PSPI_CTL1];
-+            fi
++        break;
-+            COVERITY_TOKEN="$(cat "$1")"
++
-+            shift
++    case A_PSPI_STAT:
-+            ;;
++        value = s->regs[R_PSPI_STAT];
-+        --srcdir)
++        break;
-+            shift
++
-+            if [ $# -eq 0 ]; then
++    default:
-+                echo "--srcdir needs an argument"
++        qemu_log_mask(LOG_GUEST_ERROR,
-+                exit 1
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
-+            fi
++                      DEVICE(s)->canonical_path, addr);
-+            SRCDIR="$1"
++        return 0;
-+            shift
++    }
-+            ;;
++    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
-+        --results-tarball)
++    npcm_pspi_update_irq(s);
-+            shift
++
-+            if [ $# -eq 0 ]; then
++    return value;
-+                echo "--results-tarball needs an argument"
++}
-+                exit 1
++
-+            fi
++/* Control register write handler. */
-+            RESULTSTARBALL="$1"
++static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
-+            shift
++                                 unsigned int size)
-+            ;;
++{
-+        *)
++    NPCMPSPIState *s = opaque;
-+            echo "Unexpected argument '$1'"
++    uint16_t value = v;
-+            exit 1
++
-+            ;;
++    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
-+    esac
++
-+done
++    switch (addr) {
-+
++    case A_PSPI_DATA:
-+if [ -z "$COVERITY_TOKEN" ]; then
++        npcm_pspi_write_data(s, value);
-+    echo "COVERITY_TOKEN environment variable not set"
++        break;
-+    exit 1
++
-+fi
++    case A_PSPI_CTL1:
-+
++        s->regs[R_PSPI_CTL1] = value;
-+if [ -z "$COVERITY_BUILD_CMD" ]; then
++        break;
-+    NPROC=$(nproc)
++
-+    COVERITY_BUILD_CMD="make -j$NPROC"
++    case A_PSPI_STAT:
-+    echo "COVERITY_BUILD_CMD: using default '$COVERITY_BUILD_CMD'"
++        qemu_log_mask(LOG_GUEST_ERROR,
-+fi
++                      "%s: write to read-only register PSPI_STAT: 0x%08"
-+
++                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
-+if [ -z "$COVERITY_TOOL_BASE" ]; then
++        break;
-+    echo "COVERITY_TOOL_BASE: using default /tmp/coverity-tools"
++
-+    COVERITY_TOOL_BASE=/tmp/coverity-tools
++    default:
-+fi
++        qemu_log_mask(LOG_GUEST_ERROR,
-+
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
-+if [ -z "$SRCDIR" ]; then
++                      DEVICE(s)->canonical_path, addr);
-+    SRCDIR="$PWD"
++        return;
-+fi
++    }
-+
++    npcm_pspi_update_irq(s);
-+PROJTOKEN="$COVERITY_TOKEN"
++}
-+PROJNAME=QEMU
++
-+TARBALL=cov-int.tar.xz
++static const MemoryRegionOps npcm_pspi_ctrl_ops = {
-+
++    .read = npcm_pspi_ctrl_read,
-+
++    .write = npcm_pspi_ctrl_write,
-+if [ "$UPDATE_ONLY" = yes ]; then
++    .endianness = DEVICE_LITTLE_ENDIAN,
-+    # Just do the tools update; we don't need to check whether
++    .valid = {
-+    # we are in a source tree or have upload rights for this,
++        .min_access_size = 1,
-+    # so do it before some of the command line and source tree checks.
++        .max_access_size = 2,
-+    update_coverity_tools
++        .unaligned = false,
-+    exit 0
++    },
-+fi
++    .impl = {
-+
++        .min_access_size = 2,
-+cd "$SRCDIR"
++        .max_access_size = 2,
-+
++        .unaligned = false,
-+echo "Checking this is a QEMU source tree..."
++    },
-+if ! [ -e "$SRCDIR/VERSION" ]; then
++};
-+    echo "Not in a QEMU source tree?"
++
-+    exit 1
++static void npcm_pspi_enter_reset(Object *obj, ResetType type)
-+fi
++{
-+
++    NPCMPSPIState *s = NPCM_PSPI(obj);
-+# Fill in defaults used by the non-update-only process
++
-+if [ -z "$VERSION" ]; then
++    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
-+    VERSION="$(git describe --always HEAD)"
++    memset(s->regs, 0, sizeof(s->regs));
-+fi
++}
 +
-+if [ -z "$DESCRIPTION" ]; then
++static void npcm_pspi_realize(DeviceState *dev, Error **errp)
-+    DESCRIPTION="$(git rev-parse HEAD)"
++{
-+fi
++    NPCMPSPIState *s = NPCM_PSPI(dev);
-+
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-+if [ -z "$COVERITY_EMAIL" ]; then
++    Object *obj = OBJECT(dev);
-+    COVERITY_EMAIL="$(git config user.email)"
++
-+fi
++    s->spi = ssi_create_bus(dev, "pspi");
-+
++    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
-+check_upload_permissions
++                          "mmio", 4 * KiB);
-+
++    sysbus_init_mmio(sbd, &s->mmio);
-+update_coverity_tools
++    sysbus_init_irq(sbd, &s->irq);
-+
++}
-+TOOLBIN="$(cd "$COVERITY_TOOL_BASE" && echo $PWD/coverity_tool/cov-analysis-*/bin)"
++
-+
++static const VMStateDescription vmstate_npcm_pspi = {
-+if ! test -x "$TOOLBIN/cov-build"; then
++    .name = "npcm-pspi",
-+    echo "Couldn't find cov-build in the coverity build-tool directory??"
++    .version_id = 0,
-+    exit 1
++    .minimum_version_id = 0,
-+fi
++    .fields = (VMStateField[]) {
-+
++        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
-+export PATH="$TOOLBIN:$PATH"
++        VMSTATE_END_OF_LIST(),
-+
++    },
-+cd "$SRCDIR"
++};
 +
-+echo "Doing make distclean..."
++
-+make distclean
++static void npcm_pspi_class_init(ObjectClass *klass, void *data)
-+
++{
-+echo "Configuring..."
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+# We configure with a fixed set of enables here to ensure that we don't
++    DeviceClass *dc = DEVICE_CLASS(klass);
-+# accidentally reduce the scope of the analysis by doing the build on
++
-+# the system that's missing a dependency that we need to build part of
++    dc->desc = "NPCM Peripheral SPI Module";
-+# the codebase.
++    dc->realize = npcm_pspi_realize;
-+./configure --disable-modules --enable-sdl --enable-gtk \
++    dc->vmsd = &vmstate_npcm_pspi;
-+    --enable-opengl --enable-vte --enable-gnutls \
++    rc->phases.enter = npcm_pspi_enter_reset;
-+    --enable-nettle --enable-curses --enable-curl \
++}
-+    --audio-drv-list=oss,alsa,sdl,pa --enable-virtfs \
++
-+    --enable-vnc --enable-vnc-sasl --enable-vnc-jpeg --enable-vnc-png \
++static const TypeInfo npcm_pspi_types[] = {
-+    --enable-xen --enable-brlapi \
++    {
-+    --enable-linux-aio --enable-attr \
++        .name = TYPE_NPCM_PSPI,
-+    --enable-cap-ng --enable-trace-backends=log --enable-spice --enable-rbd \
++        .parent = TYPE_SYS_BUS_DEVICE,
-+    --enable-xfsctl --enable-libusb --enable-usb-redir \
++        .instance_size = sizeof(NPCMPSPIState),
-+    --enable-libiscsi --enable-libnfs --enable-seccomp \
++        .class_init = npcm_pspi_class_init,
-+    --enable-tpm --enable-libssh --enable-lzo --enable-snappy --enable-bzip2 \
++    },
-+    --enable-numa --enable-rdma --enable-smartcard --enable-virglrenderer \
++};
-+    --enable-mpath --enable-libxml2 --enable-glusterfs \
++DEFINE_TYPES(npcm_pspi_types);
-+    --enable-virtfs --enable-zstd
+diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
-+
+index XXXXXXX..XXXXXXX 100644
-+echo "Making libqemustub.a..."
+--- a/hw/ssi/meson.build
-+make libqemustub.a
++++ b/hw/ssi/meson.build
-+
+@@ -XXX,XX +XXX,XX @@
-+echo "Running cov-build..."
+ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
-+rm -rf cov-int
+ softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
-+mkdir cov-int
+-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
-+cov-build --dir cov-int $COVERITY_BUILD_CMD
++softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
-+
+ softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
-+echo "Creating results tarball..."
+ softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
-+tar cvf - cov-int | xz > "$TARBALL"
+ softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
-+
+diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
-+if [ ! -z "$RESULTSTARBALL" ]; then
+index XXXXXXX..XXXXXXX 100644
-+    echo "Copying results tarball to $RESULTSTARBALL..."
+--- a/hw/ssi/trace-events
-+    cp "$TARBALL" "$RESULTSTARBALL"
++++ b/hw/ssi/trace-events
-+fi
+@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
-+
+ npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
-+echo "Uploading results tarball..."
+ npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
-+
-+if [ "$DRYRUN" = yes ]; then
++# npcm_pspi.c
-+    echo "Dry run only, not uploading $TARBALL"
++npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
-+    exit 0
++npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
-+fi
++npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
 +
-+curl --form token="$PROJTOKEN" --form email="$COVERITY_EMAIL" \
+ # ibex_spi_host.c
-+     --form file=@"$TARBALL" --form version="$VERSION" \
-+     --form description="$DESCRIPTION" \
+ ibex_spi_host_reset(const char *msg) "%s"
 +     https://scan.coverity.com/builds?project="$PROJNAME"
 +
 +echo "Done."
 --
-.20.1
+.34.1

-New patch
+[PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC
+From: Hao Wu <wuhaotsh@google.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Titus Rwantare <titusr@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/nuvoton.rst |  2 +-
+ include/hw/arm/npcm7xx.h    |  2 ++
+ hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
+files changed, 26 insertions(+), 3 deletions(-)
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/nuvoton.rst
++++ b/docs/system/arm/nuvoton.rst
+@@ -XXX,XX +XXX,XX @@ Supported devices
+  * SMBus controller (SMBF)
+  * Ethernet controller (EMC)
+  * Tachometer
++ * Peripheral SPI controller (PSPI)
+ Missing devices
+ ---------------
+@@ -XXX,XX +XXX,XX @@ Missing devices
+  * Ethernet controller (GMAC)
+  * USB device (USBD)
+- * Peripheral SPI controller (PSPI)
+  * SD/MMC host
+  * PECI interface
+  * PCI and PCIe root complex and bridges
+diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/npcm7xx.h
++++ b/include/hw/arm/npcm7xx.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/nvram/npcm7xx_otp.h"
+ #include "hw/timer/npcm7xx_timer.h"
+ #include "hw/ssi/npcm7xx_fiu.h"
++#include "hw/ssi/npcm_pspi.h"
+ #include "hw/usb/hcd-ehci.h"
+ #include "hw/usb/hcd-ohci.h"
+ #include "target/arm/cpu.h"
+@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
+     NPCM7xxFIUState     fiu[2];
+     NPCM7xxEMCState     emc[2];
+     NPCM7xxSDHCIState   mmc;
++    NPCMPSPIState       pspi[2];
+ };
+ #define TYPE_NPCM7XX    "npcm7xx"
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/npcm7xx.c
++++ b/hw/arm/npcm7xx.c
+@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
+     NPCM7XX_EMC1RX_IRQ          = 15,
+     NPCM7XX_EMC1TX_IRQ,
+     NPCM7XX_MMC_IRQ             = 26,
++    NPCM7XX_PSPI2_IRQ           = 28,
++    NPCM7XX_PSPI1_IRQ           = 31,
+     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
+     NPCM7XX_TIMER1_IRQ,
+     NPCM7XX_TIMER2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
+xf0826000,
+ };
++/* Register base address for each PSPI Module */
++static const hwaddr npcm7xx_pspi_addr[] = {
++    0xf0200000,
++    0xf0201000,
++};
++
+ static const struct {
+     hwaddr regs_addr;
+     uint32_t unconnected_pins;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
+         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
+     }
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
++    }
++
+     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
+ }
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
+             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
++    /* PSPI */
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
++        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
++
++        sysbus_realize(sbd, &error_abort);
++        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
++        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
++    }
++
+     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
+     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
+     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
+--
+.34.1

-New patch
+[PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Addresses targeting the second translation table (TTB1) in the SMMU have
+all upper bits set. Ensure the IOMMU region covers all 64 bits.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/smmu-common.h | 2 --
+ hw/arm/smmu-common.c         | 2 +-
+files changed, 1 insertion(+), 3 deletions(-)
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmu-common.h
++++ b/include/hw/arm/smmu-common.h
+@@ -XXX,XX +XXX,XX @@
+ #define SMMU_PCI_DEVFN_MAX    256
+ #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
+-#define SMMU_MAX_VA_BITS      48
+-
+ /*
+  * Page table walk error types
+  */
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
+         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
+                                  s->mrtypename,
+-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
++                                 OBJECT(s), name, UINT64_MAX);
+         address_space_init(&sdev->as,
+                            MEMORY_REGION(&sdev->iommu), name);
+         trace_smmu_add_mr(name);
+--
+.34.1

-New patch
+[PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Addresses targeting the second translation table (TTB1) in the SMMU have
+all upper bits set (except for the top byte when TBI is enabled). Fix
+the TTB1 check.
+Reported-by: Ola Hugosson <ola.hugosson@arm.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/smmu-common.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
+         /* there is a ttbr0 region and we are in it (high bits all zero) */
+         return &cfg->tt[0];
+     } else if (cfg->tt[1].tsz &&
+-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
++        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
+         /* there is a ttbr1 region and we are in it (high bits all one) */
+         return &cfg->tt[1];
+     } else if (!cfg->tt[0].tsz) {
+--
+.34.1

-[PULL 11/12] docs: Require Sphinx 1.6 or better
+[PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting
-Versions of Sphinx older than 1.6 can't build all of our documentation,
+From: Claudio Fontana <cfontana@suse.de>
 because they are too picky about the syntax of the argument to the
 option:: directive; see Sphinx bugs #646, #3366:
-  https://github.com/sphinx-doc/sphinx/issues/646
+make it clearer from the name that this is a tcg-only function.
   https://github.com/sphinx-doc/sphinx/issues/3366
-Trying to build with a 1.4.x Sphinx fails with
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
- docs/system/images.rst:4: SEVERE: Duplicate ID: "cmdoption-qcow2-arg-encrypt"
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
-and a 1.5.x Sphinx fails with
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- docs/system/invocation.rst:544: WARNING: Malformed option description '[enable=]PATTERN', should look like "opt", "-opt
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-args", "--opt args", "/opt args" or "+opt args"
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-Update our needs_sphinx setting to indicate that we require at least
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 .6.  This will allow configure to fall back to "don't build the
 docs" rather than causing the build to fail entirely, which is
 probably what most users building on a host old enough to have such
 an old Sphinx would want; if they do want the docs then they'll have
 a useful indication of what they need to do (upgrade Sphinx!) rather
 than a confusing error message.
 In theory our distro support policy would suggest that we should
 support building on the Sphinx shipped in those distros, but:
  * EPEL7 has Sphinx 1.2.3 (which we've never supported!)
  * Debian Stretch has Sphinx 1.4.8
 Trying to get our docs to work with Sphinx 1.4 is not tractable
 for the 5.0 release and I'm not sure it's worthwhile effort anyway;
 at least with this change the build as a whole now succeeds.
 Thanks to John Snow for doing the investigation and testing to
 confirm what Sphinx versions fail in what ways and what distros
 shipped what.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
  docs/conf.py | 6 ++++--
 file changed, 4 insertions(+), 2 deletions(-)
 diff --git a/docs/conf.py b/docs/conf.py
 index XXXXXXX..XXXXXXX 100644
---- a/docs/conf.py
+--- a/target/arm/helper.c
-+++ b/docs/conf.py
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ sys.path.insert(0, os.path.join(qemu_docdir, "sphinx"))
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
+  * trapped to the hypervisor in KVM.
- # If your documentation needs a minimal Sphinx version, state it here.
+  */
- #
+ #ifdef CONFIG_TCG
--# 1.3 is where the 'alabaster' theme was shipped with Sphinx.
+-static void handle_semihosting(CPUState *cs)
--needs_sphinx = '1.3'
++static void tcg_handle_semihosting(CPUState *cs)
-+# Sphinx 1.5 and earlier can't build our docs because they are too
+ {
-+# picky about the syntax of the argument to the option:: directive
+     ARMCPU *cpu = ARM_CPU(cs);
-+# (see Sphinx bugs #646, #3366).
+     CPUARMState *env = &cpu->env;
-+needs_sphinx = '1.6'
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
+      */
- # Add any Sphinx extension module names here, as strings. They can be
+ #ifdef CONFIG_TCG
- # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+     if (cs->exception_index == EXCP_SEMIHOST) {
 -        handle_semihosting(cs);
 +        tcg_handle_semihosting(cs);
          return;
      }
  #endif
 --
-.20.1
+.34.1

-[PULL 10/12] kernel-doc: Use c:struct for Sphinx 3.0 and later
+[PULL 22/30] target/arm: wrap psci call with tcg_enabled
-The kernel-doc Sphinx plugin and associated script currently emit
+From: Claudio Fontana <cfontana@suse.de>
 'c:type' directives for "struct foo" documentation.
-Sphinx 3.0 warns about this:
+for "all" builds (tcg + kvm), we want to avoid doing
-  /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:3: WARNING: Type must be either just a name or a typedef-like declaration.
+the psci check if tcg is built-in, but not enabled.
   If just a name:
     Error in declarator or parameters
     Invalid C declaration: Expected identifier in nested name, got keyword: struct [error at 6]
       struct MemoryListener
       ------^
   If typedef-like declaration:
     Error in declarator or parameters
     Invalid C declaration: Expected identifier in nested name. [error at 21]
       struct MemoryListener
       ---------------------^
-because it wants us to use the new-in-3.0 'c:struct' instead.
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 3 ++-
 file changed, 2 insertions(+), 1 deletion(-)
-Plumb the Sphinx version through to the kernel-doc script
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 and use it to select 'c:struct' for newer versions than 3.0.
 Fixes: LP:1872113
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 ---
  docs/sphinx/kerneldoc.py |  1 +
  scripts/kernel-doc       | 16 +++++++++++++++-
 files changed, 16 insertions(+), 1 deletion(-)
 diff --git a/docs/sphinx/kerneldoc.py b/docs/sphinx/kerneldoc.py
 index XXXXXXX..XXXXXXX 100644
---- a/docs/sphinx/kerneldoc.py
+--- a/target/arm/helper.c
-+++ b/docs/sphinx/kerneldoc.py
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ class KernelDocDirective(Directive):
+@@ -XXX,XX +XXX,XX @@
-                 env.note_dependency(os.path.abspath(f))
+ #include "hw/irq.h"
-                 cmd += ['-export-file', f]
+ #include "sysemu/cpu-timers.h"
+ #include "sysemu/kvm.h"
-+        cmd += ['-sphinx-version', sphinx.__version__]
++#include "sysemu/tcg.h"
-         cmd += [filename]
+ #include "qapi/qapi-commands-machine-target.h"
+ #include "qapi/error.h"
-         try:
+ #include "qemu/guest-random.h"
-diff --git a/scripts/kernel-doc b/scripts/kernel-doc
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
-index XXXXXXX..XXXXXXX 100755
+                       env->exception.syndrome);
---- a/scripts/kernel-doc
+     }
-+++ b/scripts/kernel-doc
-@@ -XXX,XX +XXX,XX @@ Output selection (mutually exclusive):
+-    if (arm_is_psci_call(cpu, cs->exception_index)) {
-             DOC: sections. May be specified multiple times.
++    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
+         arm_handle_psci_call(cpu);
- Output selection modifiers:
+         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
-+  -sphinx-version VER   Generate rST syntax for the specified Sphinx version.
+         return;
 +                        Only works with reStructuredTextFormat.
    -no-doc-sections    Do not output DOC: sections.
    -enable-lineno        Enable output of #define LINENO lines. Only works with
                          reStructuredText format.
@@ -XXX,XX +XXX,XX @@ use constant {
  };
  my $output_selection = OUTPUT_ALL;
  my $show_not_found = 0;    # No longer used
 +my $sphinx_version = "0.0"; # if not specified, assume old
  my @export_file_list;
@@ -XXX,XX +XXX,XX @@ while ($ARGV[0] =~ m/^--?(.*)/) {
          $enable_lineno = 1;
      } elsif ($cmd eq 'show-not-found') {
      $show_not_found = 1;  # A no-op but don't fail
 +    } elsif ($cmd eq 'sphinx-version') {
 +        $sphinx_version = shift @ARGV;
      } else {
      # Unknown argument
          usage();
@@ -XXX,XX +XXX,XX @@ sub output_struct_rst(%) {
      my $oldprefix = $lineprefix;
      my $name = $args{'type'} . " " . $args{'struct'};
 -    print "\n\n.. c:type:: " . $name . "\n\n";
 +    # Sphinx 3.0 and up will emit warnings for "c:type:: struct Foo".
 +    # It wants to see "c:struct:: Foo" (and will add the word 'struct' in
 +    # the rendered output).
 +    if ((split(/\./, $sphinx_version))[0] >= 3) {
 +        my $sname = $name;
 +        $sname =~ s/^struct //;
 +        print "\n\n.. c:struct:: " . $sname . "\n\n";
 +    } else {
 +        print "\n\n.. c:type:: " . $name . "\n\n";
 +    }
      print_lineno($declaration_start_line);
      $lineprefix = "   ";
      output_highlight_rst($args{'purpose'});
 --
-.20.1
+.34.1

-[PULL 07/12] docs: Improve our gdbstub documentation
+[PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
-The documentation of our -s and -gdb options is quite old; in
+From: Claudio Fontana <cfontana@suse.de>
 particular it still claims that it will cause QEMU to stop and wait
 for the gdb connection, when this has not been true for some time:
 you also need to pass -S if you want to make QEMU not launch the
 guest on startup.
-Improve the documentation to mention this requirement in the
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
-executable's --help output, the documentation of the -gdb option in
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-the manual, and in the "GDB usage" chapter.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 12 +++++++-----
 file changed, 7 insertions(+), 5 deletions(-)
-Includes some minor tweaks to these paragraphs of documentation
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 since I was editing them anyway (such as dropping the description
 of our gdb support as "primitive").
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20200403094014.9589-1-peter.maydell@linaro.org
 ---
  docs/system/gdb.rst | 22 +++++++++++++++-------
  qemu-options.hx     | 24 ++++++++++++++++++------
 files changed, 33 insertions(+), 13 deletions(-)
 diff --git a/docs/system/gdb.rst b/docs/system/gdb.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/gdb.rst
+--- a/target/arm/helper.c
-+++ b/docs/system/gdb.rst
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
- GDB usage
+     unsigned int cur_el = arm_current_el(env);
- ---------
+     int rt;
--QEMU has a primitive support to work with gdb, so that you can do
+-    /*
--'Ctrl-C' while the virtual machine is running and inspect its state.
+-     * Note that new_el can never be 0.  If cur_el is 0, then
-+QEMU supports working with gdb via gdb's remote-connection facility
+-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-+(the "gdbstub"). This allows you to debug guest code in the same
+-     */
-+way that you might with a low-level debug facility like JTAG
+-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
-+on real hardware. You can stop and start the virtual machine,
++    if (tcg_enabled()) {
-+examine state like registers and memory, and set breakpoints and
++        /*
-+watchpoints.
++         * Note that new_el can never be 0.  If cur_el is 0, then
++         * el0_a64 is is_a64(), else el0_a64 is ignored.
--In order to use gdb, launch QEMU with the '-s' option. It will wait for
++         */
--a gdb connection:
++        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
-+In order to use gdb, launch QEMU with the ``-s`` and ``-S`` options.
++    }
-+The ``-s`` option will make QEMU listen for an incoming connection
-+from gdb on TCP port 1234, and ``-S`` will make QEMU not start the
+     if (cur_el < new_el) {
-+guest until you tell it to from gdb. (If you want to specify which
+         /*
 +TCP port to use or to use something other than TCP for the gdbstub
 +connection, use the ``-gdb dev`` option instead of ``-s``.)
  .. parsed-literal::
 -   |qemu_system| -s -kernel bzImage -hda rootdisk.img -append "root=/dev/hda"
 -   Connected to host network interface: tun0
 -   Waiting gdb connection on port 1234
 +   |qemu_system| -s -S -kernel bzImage -hda rootdisk.img -append "root=/dev/hda"
 +
 +QEMU will launch but will silently wait for gdb to connect.
  Then launch gdb on the 'vmlinux' executable::
 diff --git a/qemu-options.hx b/qemu-options.hx
 index XXXXXXX..XXXXXXX 100644
 --- a/qemu-options.hx
 +++ b/qemu-options.hx
@@ -XXX,XX +XXX,XX @@ SRST
  ERST
  DEF("gdb", HAS_ARG, QEMU_OPTION_gdb, \
 -    "-gdb dev        wait for gdb connection on 'dev'\n", QEMU_ARCH_ALL)
 +    "-gdb dev        accept gdb connection on 'dev'. (QEMU defaults to starting\n"
 +    "                the guest without waiting for gdb to connect; use -S too\n"
 +    "                if you want it to not start execution.)\n",
 +    QEMU_ARCH_ALL)
  SRST
  ``-gdb dev``
 -    Wait for gdb connection on device dev (see
 -    :ref:`gdb_005fusage`). Typical connections will likely be
 -    TCP-based, but also UDP, pseudo TTY, or even stdio are reasonable
 -    use case. The latter is allowing to start QEMU from within gdb and
 -    establish the connection via a pipe:
 +    Accept a gdb connection on device dev (see
 +    :ref:`gdb_005fusage`). Note that this option does not pause QEMU
 +    execution -- if you want QEMU to not start the guest until you
 +    connect with gdb and issue a ``continue`` command, you will need to
 +    also pass the ``-S`` option to QEMU.
 +
 +    The most usual configuration is to listen on a local TCP socket::
 +
 +        -gdb tcp::3117
 +
 +    but you can specify other backends; UDP, pseudo TTY, or even stdio
 +    are all reasonable use cases. For example, a stdio connection
 +    allows you to start QEMU from within gdb and establish the
 +    connection via a pipe:
      .. parsed-literal::
 --
-.20.1
+.34.1

-[PULL 06/12] scripts/coverity-scan: Add Docker support
+[PULL 24/30] target/arm: Move PC alignment check
-Add support for running the Coverity Scan tools inside a Docker
+From: Fabiano Rosas <farosas@suse.de>
 container rather than directly on the host system.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Move this earlier to make the next patch diff cleaner. While here
 update the comment slightly to not give the impression that the
 misalignment affects only TCG.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20200319193323.2038-7-peter.maydell@linaro.org
 ---
- scripts/coverity-scan/coverity-scan.docker | 131 +++++++++++++++++++++
+ target/arm/machine.c | 18 +++++++++---------
- scripts/coverity-scan/run-coverity-scan    |  90 ++++++++++++++
+file changed, 9 insertions(+), 9 deletions(-)
 files changed, 221 insertions(+)
  create mode 100644 scripts/coverity-scan/coverity-scan.docker
-diff --git a/scripts/coverity-scan/coverity-scan.docker b/scripts/coverity-scan/coverity-scan.docker
+diff --git a/target/arm/machine.c b/target/arm/machine.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/arm/machine.c
---- /dev/null
++++ b/target/arm/machine.c
-+++ b/scripts/coverity-scan/coverity-scan.docker
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
-@@ -XXX,XX +XXX,XX @@
+         }
-+# syntax=docker/dockerfile:1.0.0-experimental
+     }
-+#
-+# Docker setup for running the "Coverity Scan" tools over the source
++    /*
-+# tree and uploading them to the website, as per
++     * Misaligned thumb pc is architecturally impossible. Fail the
-+# https://scan.coverity.com/projects/qemu/builds/new
++     * incoming migration. For TCG it would trigger the assert in
-+# We do this on a fixed config (currently Fedora 30 with a known
++     * thumb_tr_translate_insn().
-+# set of dependencies and a configure command that enables a specific
++     */
-+# set of options) so that random changes don't result in our accidentally
++    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-+# dropping some files from the scan.
++        return -1;
-+#
++    }
 +# We don't build on top of the fedora.docker file because we don't
 +# want to accidentally change or break the scan config when that
 +# is updated.
 +
-+# The work of actually doing the build is handled by the
+     hw_breakpoint_update_all(cpu);
-+# run-coverity-scan script.
+     hw_watchpoint_update_all(cpu);
-+
-+FROM fedora:30
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
-+ENV PACKAGES \
+         }
-+    alsa-lib-devel \
+     }
-+    bc \
-+    bison \
+-    /*
-+    brlapi-devel \
+-     * Misaligned thumb pc is architecturally impossible.
-+    bzip2 \
+-     * We have an assert in thumb_tr_translate_insn to verify this.
-+    bzip2-devel \
+-     * Fail an incoming migrate to avoid this assert.
-+    ccache \
+-     */
-+    clang \
+-    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-+    curl \
+-        return -1;
-+    cyrus-sasl-devel \
+-    }
-+    dbus-daemon \
+-
-+    device-mapper-multipath-devel \
+     if (!kvm_enabled()) {
-+    findutils \
+         pmu_op_finish(&cpu->env);
-+    flex \
+     }
 +    gcc \
 +    gcc-c++ \
 +    gettext \
 +    git \
 +    glib2-devel \
 +    glusterfs-api-devel \
 +    gnutls-devel \
 +    gtk3-devel \
 +    hostname \
 +    libaio-devel \
 +    libasan \
 +    libattr-devel \
 +    libblockdev-mpath-devel \
 +    libcap-devel \
 +    libcap-ng-devel \
 +    libcurl-devel \
 +    libepoxy-devel \
 +    libfdt-devel \
 +    libgbm-devel \
 +    libiscsi-devel \
 +    libjpeg-devel \
 +    libpmem-devel \
 +    libnfs-devel \
 +    libpng-devel \
 +    librbd-devel \
 +    libseccomp-devel \
 +    libssh-devel \
 +    libubsan \
 +    libudev-devel \
 +    libusbx-devel \
 +    libxml2-devel \
 +    libzstd-devel \
 +    llvm \
 +    lzo-devel \
 +    make \
 +    mingw32-bzip2 \
 +    mingw32-curl \
 +    mingw32-glib2 \
 +    mingw32-gmp \
 +    mingw32-gnutls \
 +    mingw32-gtk3 \
 +    mingw32-libjpeg-turbo \
 +    mingw32-libpng \
 +    mingw32-libtasn1 \
 +    mingw32-nettle \
 +    mingw32-nsis \
 +    mingw32-pixman \
 +    mingw32-pkg-config \
 +    mingw32-SDL2 \
 +    mingw64-bzip2 \
 +    mingw64-curl \
 +    mingw64-glib2 \
 +    mingw64-gmp \
 +    mingw64-gnutls \
 +    mingw64-gtk3 \
 +    mingw64-libjpeg-turbo \
 +    mingw64-libpng \
 +    mingw64-libtasn1 \
 +    mingw64-nettle \
 +    mingw64-pixman \
 +    mingw64-pkg-config \
 +    mingw64-SDL2 \
 +    ncurses-devel \
 +    nettle-devel \
 +    nss-devel \
 +    numactl-devel \
 +    perl \
 +    perl-Test-Harness \
 +    pixman-devel \
 +    pulseaudio-libs-devel \
 +    python3 \
 +    python3-sphinx \
 +    PyYAML \
 +    rdma-core-devel \
 +    SDL2-devel \
 +    snappy-devel \
 +    sparse \
 +    spice-server-devel \
 +    systemd-devel \
 +    systemtap-sdt-devel \
 +    tar \
 +    texinfo \
 +    usbredir-devel \
 +    virglrenderer-devel \
 +    vte291-devel \
 +    wget \
 +    which \
 +    xen-devel \
 +    xfsprogs-devel \
 +    zlib-devel
 +ENV QEMU_CONFIGURE_OPTS --python=/usr/bin/python3
 +
 +RUN dnf install -y $PACKAGES
 +RUN rpm -q $PACKAGES | sort > /packages.txt
 +ENV PATH $PATH:/usr/libexec/python3-sphinx/
 +ENV COVERITY_TOOL_BASE=/coverity-tools
 +COPY run-coverity-scan run-coverity-scan
 +RUN --mount=type=secret,id=coverity.token,required ./run-coverity-scan --update-tools-only --tokenfile /run/secrets/coverity.token
 diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan
 index XXXXXXX..XXXXXXX 100755
 --- a/scripts/coverity-scan/run-coverity-scan
 +++ b/scripts/coverity-scan/run-coverity-scan
@@ -XXX,XX +XXX,XX @@
  # Command line options:
  #   --dry-run : run the tools, but don't actually do the upload
 +#   --docker : create and work inside a docker container
  #   --update-tools-only : update the cached copy of the tools, but don't run them
  #   --tokenfile : file to read Coverity token from
  #   --version ver : specify version being analyzed (default: ask git)
@@ -XXX,XX +XXX,XX @@
  #   --srcdir : QEMU source tree to analyze (default: current working dir)
  #   --results-tarball : path to copy the results tarball to (default: don't
  #                       copy it anywhere, just upload it)
 +#   --src-tarball : tarball to untar into src dir (default: none); this
 +#                   is intended mainly for internal use by the Docker support
  #
  # User-specifiable environment variables:
  #  COVERITY_TOKEN -- Coverity token
@@ -XXX,XX +XXX,XX @@ update_coverity_tools () {
  # Check user-provided environment variables and arguments
  DRYRUN=no
  UPDATE_ONLY=no
 +DOCKER=no
  while [ "$#" -ge 1 ]; do
      case "$1" in
@@ -XXX,XX +XXX,XX @@ while [ "$#" -ge 1 ]; do
              RESULTSTARBALL="$1"
              shift
              ;;
 +        --src-tarball)
 +            shift
 +            if [ $# -eq 0 ]; then
 +                echo "--src-tarball needs an argument"
 +                exit 1
 +            fi
 +            SRCTARBALL="$1"
 +            shift
 +            ;;
 +        --docker)
 +            DOCKER=yes
 +            shift
 +            ;;
          *)
              echo "Unexpected argument '$1'"
              exit 1
@@ -XXX,XX +XXX,XX @@ PROJTOKEN="$COVERITY_TOKEN"
  PROJNAME=QEMU
  TARBALL=cov-int.tar.xz
 +if [ "$UPDATE_ONLY" = yes ] && [ "$DOCKER" = yes ]; then
 +    echo "Combining --docker and --update-only is not supported"
 +    exit 1
 +fi
  if [ "$UPDATE_ONLY" = yes ]; then
      # Just do the tools update; we don't need to check whether
@@ -XXX,XX +XXX,XX @@ if [ "$UPDATE_ONLY" = yes ]; then
      exit 0
  fi
 +if [ ! -e "$SRCDIR" ]; then
 +    mkdir "$SRCDIR"
 +fi
 +
  cd "$SRCDIR"
 +if [ ! -z "$SRCTARBALL" ]; then
 +    echo "Untarring source tarball into $SRCDIR..."
 +    tar xvf "$SRCTARBALL"
 +fi
 +
  echo "Checking this is a QEMU source tree..."
  if ! [ -e "$SRCDIR/VERSION" ]; then
      echo "Not in a QEMU source tree?"
@@ -XXX,XX +XXX,XX @@ if [ -z "$COVERITY_EMAIL" ]; then
      COVERITY_EMAIL="$(git config user.email)"
  fi
 +# Run ourselves inside docker if that's what the user wants
 +if [ "$DOCKER" = yes ]; then
 +    # build docker container including the coverity-scan tools
 +    # Put the Coverity token into a temporary file that only
 +    # we have read access to, and then pass it to docker build
 +    # using --secret. This requires at least Docker 18.09.
 +    # Mostly what we are trying to do here is ensure we don't leak
 +    # the token into the Docker image.
 +    umask 077
 +    SECRETDIR=$(mktemp -d)
 +    if [ -z "$SECRETDIR" ]; then
 +        echo "Failed to create temporary directory"
 +        exit 1
 +    fi
 +    trap 'rm -rf "$SECRETDIR"' INT TERM EXIT
 +    echo "Created temporary directory $SECRETDIR"
 +    SECRET="$SECRETDIR/token"
 +    echo "$COVERITY_TOKEN" > "$SECRET"
 +    echo "Building docker container..."
 +    # TODO: This re-downloads the tools every time, rather than
 +    # caching and reusing the image produced with the downloaded tools.
 +    # Not sure why.
 +    # TODO: how do you get 'docker build' to print the output of the
 +    # commands it is running to its stdout? This would be useful for debug.
 +    DOCKER_BUILDKIT=1 docker build -t coverity-scanner \
 +                   --secret id=coverity.token,src="$SECRET" \
 +                   -f scripts/coverity-scan/coverity-scan.docker \
 +                   scripts/coverity-scan
 +    echo "Archiving sources to be analyzed..."
 +    ./scripts/archive-source.sh "$SECRETDIR/qemu-sources.tgz"
 +    if [ "$DRYRUN" = yes ]; then
 +        DRYRUNARG=--dry-run
 +    fi
 +    echo "Running scanner..."
 +    # If we need to capture the output tarball, get the inner run to
 +    # save it to the secrets directory so we can copy it out before the
 +    # directory is cleaned up.
 +    if [ ! -z "$RESULTSTARBALL" ]; then
 +        RTARGS="--results-tarball /work/cov-int.tar.xz"
 +    else
 +        RTARGS=""
 +    fi
 +    # Arrange for this docker run to get access to the sources with -v.
 +    # We pass through all the configuration from the outer script to the inner.
 +    export COVERITY_EMAIL COVERITY_BUILD_CMD
 +    docker run -it --env COVERITY_EMAIL --env COVERITY_BUILD_CMD \
 +           -v "$SECRETDIR:/work" coverity-scanner \
 +           ./run-coverity-scan --version "$VERSION" \
 +           --description "$DESCRIPTION" $DRYRUNARG --tokenfile /work/token \
 +           --srcdir /qemu --src-tarball /work/qemu-sources.tgz $RTARGS
 +    if [ ! -z "$RESULTSTARBALL" ]; then
 +        echo "Copying results tarball to $RESULTSTARBALL..."
 +        cp "$SECRETDIR/cov-int.tar.xz" "$RESULTSTARBALL"
 +    fi
 +    echo "Docker work complete."
 +    exit 0
 +fi
 +
 +# Otherwise, continue with the full build and upload process.
 +
  check_upload_permissions
  update_coverity_tools
 --
-.20.1
+.34.1

-New patch
+[PULL 25/30] target/arm: Move cpregs code out of cpu.h
+From: Fabiano Rosas <farosas@suse.de>
 Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
 a cpregs.h header which is more suitable for this code.
 Code moved verbatim.
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
  target/arm/cpu.h    | 91 -----------------------------------------
 files changed, 98 insertions(+), 91 deletions(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpregs.h
 +++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
      ARM_CP_SME                   = 1 << 19,
  };
 +/*
 + * Interface for defining coprocessor registers.
 + * Registers are defined in tables of arm_cp_reginfo structs
 + * which are passed to define_arm_cp_regs().
 + */
 +
 +/*
 + * When looking up a coprocessor register we look for it
 + * via an integer which encodes all of:
 + *  coprocessor number
 + *  Crn, Crm, opc1, opc2 fields
 + *  32 or 64 bit register (ie is it accessed via MRC/MCR
 + *    or via MRRC/MCRR?)
 + *  non-secure/secure bank (AArch32 only)
 + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 + * (In this case crn and opc2 should be zero.)
 + * For AArch64, there is no 32/64 bit size distinction;
 + * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 + * and 4 bit CRn and CRm. The encoding patterns are chosen
 + * to be easy to convert to and from the KVM encodings, and also
 + * so that the hashtable can contain both AArch32 and AArch64
 + * registers (to allow for interprocessing where we might run
 + * 32 bit code on a 64 bit core).
 + */
 +/*
 + * This bit is private to our hashtable cpreg; in KVM register
 + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 + * in the upper bits of the 64 bit ID.
 + */
 +#define CP_REG_AA64_SHIFT 28
 +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 +
 +/*
 + * To enable banking of coprocessor registers depending on ns-bit we
 + * add a bit to distinguish between secure and non-secure cpregs in the
 + * hashtable.
 + */
 +#define CP_REG_NS_SHIFT 29
 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 +
 +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 +    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 +     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 +
 +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 +    (CP_REG_AA64_MASK |                                 \
 +     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 +     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 +     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 +     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 +     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 +     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 +
 +/*
 + * Convert a full 64 bit KVM register ID to the truncated 32 bit
 + * version used as a key for the coprocessor register hashtable
 + */
 +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 +{
 +    uint32_t cpregid = kvmid;
 +    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 +        cpregid |= CP_REG_AA64_MASK;
 +    } else {
 +        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 +            cpregid |= (1 << 15);
 +        }
 +
 +        /*
 +         * KVM is always non-secure so add the NS flag on AArch32 register
 +         * entries.
 +         */
 +         cpregid |= 1 << CP_REG_NS_SHIFT;
 +    }
 +    return cpregid;
 +}
 +
 +/*
 + * Convert a truncated 32 bit hashtable key into the full
 + * 64 bit KVM register ID.
 + */
 +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 +{
 +    uint64_t kvmid;
 +
 +    if (cpregid & CP_REG_AA64_MASK) {
 +        kvmid = cpregid & ~CP_REG_AA64_MASK;
 +        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 +    } else {
 +        kvmid = cpregid & ~(1 << 15);
 +        if (cpregid & (1 << 15)) {
 +            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 +        } else {
 +            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 +        }
 +    }
 +    return kvmid;
 +}
 +
  /*
   * Valid values for ARMCPRegInfo state field, indicating which of
   * the AArch32 and AArch64 execution states this register is visible in.
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface for defining coprocessor registers.
 - * Registers are defined in tables of arm_cp_reginfo structs
 - * which are passed to define_arm_cp_regs().
 - */
 -
 -/* When looking up a coprocessor register we look for it
 - * via an integer which encodes all of:
 - *  coprocessor number
 - *  Crn, Crm, opc1, opc2 fields
 - *  32 or 64 bit register (ie is it accessed via MRC/MCR
 - *    or via MRRC/MCRR?)
 - *  non-secure/secure bank (AArch32 only)
 - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 - * (In this case crn and opc2 should be zero.)
 - * For AArch64, there is no 32/64 bit size distinction;
 - * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 - * and 4 bit CRn and CRm. The encoding patterns are chosen
 - * to be easy to convert to and from the KVM encodings, and also
 - * so that the hashtable can contain both AArch32 and AArch64
 - * registers (to allow for interprocessing where we might run
 - * 32 bit code on a 64 bit core).
 - */
 -/* This bit is private to our hashtable cpreg; in KVM register
 - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 - * in the upper bits of the 64 bit ID.
 - */
 -#define CP_REG_AA64_SHIFT 28
 -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 -
 -/* To enable banking of coprocessor registers depending on ns-bit we
 - * add a bit to distinguish between secure and non-secure cpregs in the
 - * hashtable.
 - */
 -#define CP_REG_NS_SHIFT 29
 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 -
 -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 -    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 -     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 -
 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 -    (CP_REG_AA64_MASK |                                 \
 -     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 -     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 -     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 -     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 -     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 -     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 -
 -/* Convert a full 64 bit KVM register ID to the truncated 32 bit
 - * version used as a key for the coprocessor register hashtable
 - */
 -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 -{
 -    uint32_t cpregid = kvmid;
 -    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 -        cpregid |= CP_REG_AA64_MASK;
 -    } else {
 -        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 -            cpregid |= (1 << 15);
 -        }
 -
 -        /* KVM is always non-secure so add the NS flag on AArch32 register
 -         * entries.
 -         */
 -         cpregid |= 1 << CP_REG_NS_SHIFT;
 -    }
 -    return cpregid;
 -}
 -
 -/* Convert a truncated 32 bit hashtable key into the full
 - * 64 bit KVM register ID.
 - */
 -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 -{
 -    uint64_t kvmid;
 -
 -    if (cpregid & CP_REG_AA64_MASK) {
 -        kvmid = cpregid & ~CP_REG_AA64_MASK;
 -        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 -    } else {
 -        kvmid = cpregid & ~(1 << 15);
 -        if (cpregid & (1 << 15)) {
 -            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 -        } else {
 -            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 -        }
 -    }
 -    return kvmid;
 -}
 -
  /* Return the highest implemented Exception Level */
  static inline int arm_highest_el(CPUARMState *env)
  {
 --
 .34.1

-[PULL 01/12] osdep.h: Drop no-longer-needed Coverity workarounds
+[PULL 26/30] tests/avocado: Skip tests that require a missing accelerator
-In commit a1a98357e3fd in 2018 we added some workarounds for Coverity
+From: Fabiano Rosas <farosas@suse.de>
 not being able to handle the _Float* types introduced by recent
 glibc.  Newer versions of the Coverity scan tools have support for
 these types, and will fail with errors about duplicate typedefs if we
 have our workaround.  Remove our copy of the typedefs.
+If a test was tagged with the "accel" tag and the specified
+accelerator it not present in the qemu binary, cancel the test.
+We can now write tests without explicit calls to require_accelerator,
+just the tag is enough.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200319193323.2038-2-peter.maydell@linaro.org
 ---
- include/qemu/osdep.h | 14 --------------
+ tests/avocado/avocado_qemu/__init__.py | 4 ++++
-file changed, 14 deletions(-)
+file changed, 4 insertions(+)
-diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
+diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
 index XXXXXXX..XXXXXXX 100644
---- a/include/qemu/osdep.h
+--- a/tests/avocado/avocado_qemu/__init__.py
-+++ b/include/qemu/osdep.h
++++ b/tests/avocado/avocado_qemu/__init__.py
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ def setUp(self):
- #else
- #include "exec/poison.h"
+         super().setUp('qemu-system-')
- #endif
--#ifdef __COVERITY__
++        accel_required = self._get_unique_tag_val('accel')
--/* Coverity does not like the new _Float* types that are used by
++        if accel_required:
-- * recent glibc, and croaks on every single file that includes
++            self.require_accelerator(accel_required)
-- * stdlib.h.  These typedefs are enough to please it.
++
-- *
+         self.machine = self.params.get('machine',
-- * Note that these fix parse errors so they cannot be placed in
+                                        default=self._get_unique_tag_val('machine'))
 - * scripts/coverity-model.c.
 - */
 -typedef float _Float32;
 -typedef double _Float32x;
 -typedef double _Float64;
 -typedef __float80 _Float64x;
 -typedef __float128 _Float128;
 -#endif
  #include "qemu/compiler.h"
 --
-.20.1
+.34.1

-[PULL 03/12] thread.h: Remove trailing semicolons from Coverity qemu_mutex_lock() etc
+[PULL 27/30] tests/avocado: Tag TCG tests with accel:tcg
-All the Coverity-specific definitions of qemu_mutex_lock() and friends
+From: Fabiano Rosas <farosas@suse.de>
 have a trailing semicolon. This works fine almost everywhere because
 of QEMU's mandatory-braces coding style and because most callsites are
 simple, but target/s390x/sigp.c has a use of qemu_mutex_trylock() as
 an if() statement, which makes the ';' a syntax error:
 "../target/s390x/sigp.c", line 461: warning #18: expected a ")"
       if (qemu_mutex_trylock(&qemu_sigp_mutex)) {
           ^
-Remove the bogus semicolons from the macro definitions.
+This allows the test to be skipped when TCG is not present in the QEMU
 binary.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200319193323.2038-4-peter.maydell@linaro.org
 ---
- include/qemu/thread.h | 12 ++++++------
+ tests/avocado/boot_linux_console.py | 1 +
-file changed, 6 insertions(+), 6 deletions(-)
+ tests/avocado/reverse_debugging.py  | 8 ++++++++
 files changed, 9 insertions(+)
-diff --git a/include/qemu/thread.h b/include/qemu/thread.h
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/include/qemu/thread.h
+--- a/tests/avocado/boot_linux_console.py
-+++ b/include/qemu/thread.h
++++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func;
+@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
-  * hide them.
-  */
+     def test_aarch64_raspi3_atf(self):
- #define qemu_mutex_lock(m)                                              \
+         """
--            qemu_mutex_lock_impl(m, __FILE__, __LINE__);
++        :avocado: tags=accel:tcg
-+            qemu_mutex_lock_impl(m, __FILE__, __LINE__)
+         :avocado: tags=arch:aarch64
- #define qemu_mutex_trylock(m)                                           \
+         :avocado: tags=machine:raspi3b
--            qemu_mutex_trylock_impl(m, __FILE__, __LINE__);
+         :avocado: tags=cpu:cortex-a53
-+            qemu_mutex_trylock_impl(m, __FILE__, __LINE__)
+diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
- #define qemu_rec_mutex_lock(m)                                          \
+index XXXXXXX..XXXXXXX 100644
--            qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__);
+--- a/tests/avocado/reverse_debugging.py
-+            qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__)
++++ b/tests/avocado/reverse_debugging.py
- #define qemu_rec_mutex_trylock(m)                                       \
+@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
--            qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__);
+         vm.shutdown()
-+            qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__)
- #define qemu_cond_wait(c, m)                                            \
+ class ReverseDebugging_X86_64(ReverseDebugging):
--            qemu_cond_wait_impl(c, m, __FILE__, __LINE__);
++    """
-+            qemu_cond_wait_impl(c, m, __FILE__, __LINE__)
++    :avocado: tags=accel:tcg
- #define qemu_cond_timedwait(c, m, ms)                                   \
++    """
--            qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__);
++
-+            qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__)
+     REG_PC = 0x10
- #else
+     REG_CS = 0x12
- #define qemu_mutex_lock(m) ({                                           \
+     def get_pc(self, g):
-             QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func);  \
+@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
          self.reverse_debugging()
  class ReverseDebugging_AArch64(ReverseDebugging):
 +    """
 +    :avocado: tags=accel:tcg
 +    """
 +
      REG_PC = 32
      # unidentified gitlab timeout problem
 --
-.20.1
+.34.1

-New patch
+[PULL 28/30] target/arm: Use "max" as default cpu for the virt machine with KVM
+From: Fabiano Rosas <farosas@suse.de>
+Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
+KVM-only build the 'max' cpu.
+Note that we cannot use 'host' here because the qtests can run without
+any other accelerator (than qtest) and 'host' depends on KVM being
+enabled.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/virt.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+     mc->minimum_page_bits = 12;
+     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
+     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
++#ifdef CONFIG_TCG
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
++#else
++    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
++#endif
+     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
+     mc->kvm_type = virt_kvm_type;
+     assert(!mc->get_hotplug_handler);
+--
+.34.1

-New patch
+[PULL 29/30] tests/qtest: arm-cpu-features: Match tests to required accelerators
+From: Fabiano Rosas <farosas@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
+file changed, 18 insertions(+), 10 deletions(-)
+diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/arm-cpu-features.c
++++ b/tests/qtest/arm-cpu-features.c
+@@ -XXX,XX +XXX,XX @@
+ #define SVE_MAX_VQ 16
+ #define MACHINE     "-machine virt,gic-version=max -accel tcg "
+-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
++#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
+ #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+                     "  'arguments': { 'type': 'full', "
+ #define QUERY_TAIL  "}}"
+@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
+ {
+     g_test_init(&argc, &argv, NULL);
+-    qtest_add_data_func("/arm/query-cpu-model-expansion",
+-                        NULL, test_query_cpu_model_expansion);
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/query-cpu-model-expansion",
++                            NULL, test_query_cpu_model_expansion);
++    }
++
++    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
++        goto out;
++    }
+     /*
+      * For now we only run KVM specific tests with AArch64 QEMU in
+      * order avoid attempting to run an AArch32 QEMU with KVM on
+      * AArch64 hosts. That won't work and isn't easy to detect.
+      */
+-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
++    if (qtest_has_accel("kvm")) {
+         /*
+          * This tests target the 'host' CPU type, so register it only if
+          * KVM is available.
+          */
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                             NULL, test_query_cpu_model_expansion_kvm);
+-    }
+-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+-                            NULL, sve_tests_sve_max_vq_8);
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+-                            NULL, sve_tests_sve_off);
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+                             NULL, sve_tests_sve_off_kvm);
+     }
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
++                            NULL, sve_tests_sve_max_vq_8);
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
++                            NULL, sve_tests_sve_off);
++    }
++
++out:
+     return g_test_run();
+ }
+--
+.34.1

-New patch
+[PULL 30/30] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
+From: Fabiano Rosas <farosas@suse.de>
+These tests set -accel tcg, so restrict them to when TCG is present.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/meson.build | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/meson.build
++++ b/tests/qtest/meson.build
+@@ -XXX,XX +XXX,XX @@ qtests_arm = \
+ # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
+ qtests_aarch64 = \
+   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
++  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
++    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
+   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
+   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
+   ['arm-cpu-features',
+--
+.34.1

Almost nothing in here is arm-related, but the target-arm
queue was convenient for these last minute bits and pieces
for 5.0...

thanks
-- PMM

The following changes since commit 14e5526b51910efd62cd31cd95b49baca975c83f:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-04-13 15:42:51 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200414

for you to fetch changes up to 84f82ddcbb4ac4ed04c8675e85155329f23184f0:

Deprecate KVM support for AArch32 (2020-04-14 17:20:22 +0100)

----------------------------------------------------------------
patch queue:
 * Fix some problems that trip up Coverity's scanner
 * run-coverity-scan: New script automating the scan-and-upload process
 * docs: Improve our gdbstub documentation
 * configure: Honour --disable-werror for Sphinx
 * docs: Fix errors produced when building with Sphinx 3.0
 * docs: Require Sphinx 1.6 or better
 * Add deprecation notice for KVM support on AArch32 hosts

----------------------------------------------------------------
Peter Maydell (12):
      osdep.h: Drop no-longer-needed Coverity workarounds
      thread.h: Fix Coverity version of qemu_cond_timedwait()
      thread.h: Remove trailing semicolons from Coverity qemu_mutex_lock() etc
      linux-user/flatload.c: Use "" for include of QEMU header target_flat.h
      scripts/run-coverity-scan: Script to run Coverity Scan build
      scripts/coverity-scan: Add Docker support
      docs: Improve our gdbstub documentation
      configure: Honour --disable-werror for Sphinx
      scripts/kernel-doc: Add missing close-paren in c:function directives
      kernel-doc: Use c:struct for Sphinx 3.0 and later
      docs: Require Sphinx 1.6 or better
      Deprecate KVM support for AArch32

In commit a1a98357e3fd in 2018 we added some workarounds for Coverity
not being able to handle the _Float* types introduced by recent
glibc.  Newer versions of the Coverity scan tools have support for
these types, and will fail with errors about duplicate typedefs if we
have our workaround.  Remove our copy of the typedefs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200319193323.2038-2-peter.maydell@linaro.org
---
 include/qemu/osdep.h | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -XXX,XX +XXX,XX @@
 #else
 #include "exec/poison.h"
 #endif
-#ifdef __COVERITY__
-/* Coverity does not like the new _Float* types that are used by
- * recent glibc, and croaks on every single file that includes
- * stdlib.h.  These typedefs are enough to please it.
- *
- * Note that these fix parse errors so they cannot be placed in
- * scripts/coverity-model.c.
- */
-typedef float _Float32;
-typedef double _Float32x;
-typedef double _Float64;
-typedef __float80 _Float64x;
-typedef __float128 _Float128;
-#endif
 
 #include "qemu/compiler.h"
 
-- 
2.20.1

For Coverity's benefit, we provide simpler versions of functions like
qemu_mutex_lock(), qemu_cond_wait() and qemu_cond_timedwait().  When
we added qemu_cond_timedwait() in commit 3dcc9c6ec4ea, a cut and
paste error meant that the Coverity version of qemu_cond_timedwait()
was using the wrong _impl function, which makes the Coverity parser
complain:

"/qemu/include/qemu/thread.h", line 159: warning #140: too many arguments in
          function call
      return qemu_cond_timedwait(cond, mutex, ms);
             ^

"/qemu/include/qemu/thread.h", line 159: warning #120: return value type does
          not match the function type
      return qemu_cond_timedwait(cond, mutex, ms);
             ^

"/qemu/include/qemu/thread.h", line 156: warning #1563: function
          "qemu_cond_timedwait" not emitted, consider modeling it or review
          parse diagnostics to improve fidelity
  static inline bool (qemu_cond_timedwait)(QemuCond *cond, QemuMutex *mutex,
                      ^

These aren't fatal, but reduce the scope of the analysis. Fix the error.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200319193323.2038-3-peter.maydell@linaro.org
---
 include/qemu/thread.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

All the Coverity-specific definitions of qemu_mutex_lock() and friends
have a trailing semicolon. This works fine almost everywhere because
of QEMU's mandatory-braces coding style and because most callsites are
simple, but target/s390x/sigp.c has a use of qemu_mutex_trylock() as
an if() statement, which makes the ';' a syntax error:
"../target/s390x/sigp.c", line 461: warning #18: expected a ")"
      if (qemu_mutex_trylock(&qemu_sigp_mutex)) {
          ^

Remove the bogus semicolons from the macro definitions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200319193323.2038-4-peter.maydell@linaro.org
---
 include/qemu/thread.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/qemu/thread.h b/include/qemu/thread.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/thread.h
+++ b/include/qemu/thread.h
@@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func;
  * hide them.
  */
 #define qemu_mutex_lock(m)                                              \
-            qemu_mutex_lock_impl(m, __FILE__, __LINE__);
+            qemu_mutex_lock_impl(m, __FILE__, __LINE__)
 #define qemu_mutex_trylock(m)                                           \
-            qemu_mutex_trylock_impl(m, __FILE__, __LINE__);
+            qemu_mutex_trylock_impl(m, __FILE__, __LINE__)
 #define qemu_rec_mutex_lock(m)                                          \
-            qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__);
+            qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__)
 #define qemu_rec_mutex_trylock(m)                                       \
-            qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__);
+            qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__)
 #define qemu_cond_wait(c, m)                                            \
-            qemu_cond_wait_impl(c, m, __FILE__, __LINE__);
+            qemu_cond_wait_impl(c, m, __FILE__, __LINE__)
 #define qemu_cond_timedwait(c, m, ms)                                   \
-            qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__);
+            qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__)
 #else
 #define qemu_mutex_lock(m) ({                                           \
             QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func);  \
-- 
2.20.1

Add a new script to automate the process of running the Coverity
Scan build tools and uploading the resulting tarball to the
website.

This is intended eventually to be driven from Travis,
but it can be run locally, if you are a maintainer of the
QEMU project on the Coverity Scan website and have the secret
upload token.

The script must be run on a Fedora 30 system.  Support for using a
Docker container is added in a following commit.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200319193323.2038-6-peter.maydell@linaro.org
---
 MAINTAINERS                             |   5 +
 scripts/coverity-scan/run-coverity-scan | 311 ++++++++++++++++++++++++
 2 files changed, 316 insertions(+)
 create mode 100755 scripts/coverity-scan/run-coverity-scan

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Markus Armbruster <armbru@redhat.com>
 S: Supported
 F: scripts/coverity-model.c
 
+Coverity Scan integration
+M: Peter Maydell <peter.maydell@linaro.org>
+S: Maintained
+F: scripts/coverity-scan/
+
 Device Tree
 M: Alistair Francis <alistair.francis@wdc.com>
 R: David Gibson <david@gibson.dropbear.id.au>
diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan
new file mode 100755
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/scripts/coverity-scan/run-coverity-scan
@@ -XXX,XX +XXX,XX @@
+#!/bin/sh -e
+
+# Upload a created tarball to Coverity Scan, as per
+# https://scan.coverity.com/projects/qemu/builds/new
+
+# This work is licensed under the terms of the GNU GPL version 2,
+# or (at your option) any later version.
+# See the COPYING file in the top-level directory.
+#
+# Copyright (c) 2017-2020 Linaro Limited
+# Written by Peter Maydell
+
+# Note that this script will automatically download and
+# run the (closed-source) coverity build tools, so don't
+# use it if you don't trust them!
+
+# This script assumes that you're running it from a QEMU source
+# tree, and that tree is a fresh clean one, because we do an in-tree
+# build. (This is necessary so that the filenames that the Coverity
+# Scan server sees are relative paths that match up with the component
+# regular expressions it uses; an out-of-tree build won't work for this.)
+# The host machine should have as many of QEMU's dependencies
+# installed as possible, for maximum coverity coverage.
+
+# To do an upload you need to be a maintainer in the Coverity online
+# service, and you will need to know the "Coverity token", which is a
+# secret 8 digit hex string. You can find that from the web UI in the
+# project settings, if you have maintainer access there.
+
+# Command line options:
+#   --dry-run : run the tools, but don't actually do the upload
+#   --update-tools-only : update the cached copy of the tools, but don't run them
+#   --tokenfile : file to read Coverity token from
+#   --version ver : specify version being analyzed (default: ask git)
+#   --description desc : specify description of this version (default: ask git)
+#   --srcdir : QEMU source tree to analyze (default: current working dir)
+#   --results-tarball : path to copy the results tarball to (default: don't
+#                       copy it anywhere, just upload it)
+#
+# User-specifiable environment variables:
+#  COVERITY_TOKEN -- Coverity token
+#  COVERITY_EMAIL -- the email address to use for uploads (default:
+#                    looks at your git user.email config)
+#  COVERITY_BUILD_CMD -- make command (default: 'make -jN' where N is
+#                    number of CPUs as determined by 'nproc')
+#  COVERITY_TOOL_BASE -- set to directory to put coverity tools
+#                        (default: /tmp/coverity-tools)
+#
+# You must specify the token, either by environment variable or by
+# putting it in a file and using --tokenfile. Everything else has
+# a reasonable default if this is run from a git tree.
+
+check_upload_permissions() {
+    # Check whether we can do an upload to the server; will exit the script
+    # with status 1 if the check failed (usually a bad token);
+    # will exit the script with status 0 if the check indicated that we
+    # can't upload yet (ie we are at quota)
+    # Assumes that PROJTOKEN, PROJNAME and DRYRUN have been initialized.
+
+    echo "Checking upload permissions..."
+
+    if ! up_perm="$(wget https://scan.coverity.com/api/upload_permitted --post-data "token=$PROJTOKEN&project=$PROJNAME" -q -O -)"; then
+        echo "Coverity Scan API access denied: bad token?"
+        exit 1
+    fi
+
+    # Really up_perm is a JSON response with either
+    # {upload_permitted:true} or {next_upload_permitted_at:<date>}
+    # We do some hacky string parsing instead of properly parsing it.
+    case "$up_perm" in
+        *upload_permitted*true*)
+            echo "Coverity Scan: upload permitted"
+            ;;
+        *next_upload_permitted_at*)
+            if [ "$DRYRUN" = yes ]; then
+                echo "Coverity Scan: upload quota reached, continuing dry run"
+            else
+                echo "Coverity Scan: upload quota reached; stopping here"
+                # Exit success as this isn't a build error.
+                exit 0
+            fi
+            ;;
+        *)
+            echo "Coverity Scan upload check: unexpected result $up_perm"
+            exit 1
+            ;;
+    esac
+}
+
+
+update_coverity_tools () {
+    # Check for whether we need to download the Coverity tools
+    # (either because we don't have a copy, or because it's out of date)
+    # Assumes that COVERITY_TOOL_BASE, PROJTOKEN and PROJNAME are set.
+
+    mkdir -p "$COVERITY_TOOL_BASE"
+    cd "$COVERITY_TOOL_BASE"
+
+    echo "Checking for new version of coverity build tools..."
+    wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME&md5=1" -O coverity_tool.md5.new
+
+    if ! cmp -s coverity_tool.md5 coverity_tool.md5.new; then
+        # out of date md5 or no md5: download new build tool
+        # blow away the old build tool
+        echo "Downloading coverity build tools..."
+        rm -rf coverity_tool coverity_tool.tgz
+        wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME" -O coverity_tool.tgz
+        if ! (cat coverity_tool.md5.new; echo "  coverity_tool.tgz") | md5sum -c --status; then
+            echo "Downloaded tarball didn't match md5sum!"
+            exit 1
+        fi
+        # extract the new one, keeping it corralled in a 'coverity_tool' directory
+        echo "Unpacking coverity build tools..."
+        mkdir -p coverity_tool
+        cd coverity_tool
+        tar xf ../coverity_tool.tgz
+        cd ..
+        mv coverity_tool.md5.new coverity_tool.md5
+    fi
+
+    rm -f coverity_tool.md5.new
+}
+
+
+# Check user-provided environment variables and arguments
+DRYRUN=no
+UPDATE_ONLY=no
+
+while [ "$#" -ge 1 ]; do
+    case "$1" in
+        --dry-run)
+            shift
+            DRYRUN=yes
+            ;;
+        --update-tools-only)
+            shift
+            UPDATE_ONLY=yes
+            ;;
+        --version)
+            shift
+            if [ $# -eq 0 ]; then
+                echo "--version needs an argument"
+                exit 1
+            fi
+            VERSION="$1"
+            shift
+            ;;
+        --description)
+            shift
+            if [ $# -eq 0 ]; then
+                echo "--description needs an argument"
+                exit 1
+            fi
+            DESCRIPTION="$1"
+            shift
+            ;;
+        --tokenfile)
+            shift
+            if [ $# -eq 0 ]; then
+                echo "--tokenfile needs an argument"
+                exit 1
+            fi
+            COVERITY_TOKEN="$(cat "$1")"
+            shift
+            ;;
+        --srcdir)
+            shift
+            if [ $# -eq 0 ]; then
+                echo "--srcdir needs an argument"
+                exit 1
+            fi
+            SRCDIR="$1"
+            shift
+            ;;
+        --results-tarball)
+            shift
+            if [ $# -eq 0 ]; then
+                echo "--results-tarball needs an argument"
+                exit 1
+            fi
+            RESULTSTARBALL="$1"
+            shift
+            ;;
+        *)
+            echo "Unexpected argument '$1'"
+            exit 1
+            ;;
+    esac
+done
+
+if [ -z "$COVERITY_TOKEN" ]; then
+    echo "COVERITY_TOKEN environment variable not set"
+    exit 1
+fi
+
+if [ -z "$COVERITY_BUILD_CMD" ]; then
+    NPROC=$(nproc)
+    COVERITY_BUILD_CMD="make -j$NPROC"
+    echo "COVERITY_BUILD_CMD: using default '$COVERITY_BUILD_CMD'"
+fi
+
+if [ -z "$COVERITY_TOOL_BASE" ]; then
+    echo "COVERITY_TOOL_BASE: using default /tmp/coverity-tools"
+    COVERITY_TOOL_BASE=/tmp/coverity-tools
+fi
+
+if [ -z "$SRCDIR" ]; then
+    SRCDIR="$PWD"
+fi
+
+PROJTOKEN="$COVERITY_TOKEN"
+PROJNAME=QEMU
+TARBALL=cov-int.tar.xz
+
+
+if [ "$UPDATE_ONLY" = yes ]; then
+    # Just do the tools update; we don't need to check whether
+    # we are in a source tree or have upload rights for this,
+    # so do it before some of the command line and source tree checks.
+    update_coverity_tools
+    exit 0
+fi
+
+cd "$SRCDIR"
+
+echo "Checking this is a QEMU source tree..."
+if ! [ -e "$SRCDIR/VERSION" ]; then
+    echo "Not in a QEMU source tree?"
+    exit 1
+fi
+
+# Fill in defaults used by the non-update-only process
+if [ -z "$VERSION" ]; then
+    VERSION="$(git describe --always HEAD)"
+fi
+
+if [ -z "$DESCRIPTION" ]; then
+    DESCRIPTION="$(git rev-parse HEAD)"
+fi
+
+if [ -z "$COVERITY_EMAIL" ]; then
+    COVERITY_EMAIL="$(git config user.email)"
+fi
+
+check_upload_permissions
+
+update_coverity_tools
+
+TOOLBIN="$(cd "$COVERITY_TOOL_BASE" && echo $PWD/coverity_tool/cov-analysis-*/bin)"
+
+if ! test -x "$TOOLBIN/cov-build"; then
+    echo "Couldn't find cov-build in the coverity build-tool directory??"
+    exit 1
+fi
+
+export PATH="$TOOLBIN:$PATH"
+
+cd "$SRCDIR"
+
+echo "Doing make distclean..."
+make distclean
+
+echo "Configuring..."
+# We configure with a fixed set of enables here to ensure that we don't
+# accidentally reduce the scope of the analysis by doing the build on
+# the system that's missing a dependency that we need to build part of
+# the codebase.
+./configure --disable-modules --enable-sdl --enable-gtk \
+    --enable-opengl --enable-vte --enable-gnutls \
+    --enable-nettle --enable-curses --enable-curl \
+    --audio-drv-list=oss,alsa,sdl,pa --enable-virtfs \
+    --enable-vnc --enable-vnc-sasl --enable-vnc-jpeg --enable-vnc-png \
+    --enable-xen --enable-brlapi \
+    --enable-linux-aio --enable-attr \
+    --enable-cap-ng --enable-trace-backends=log --enable-spice --enable-rbd \
+    --enable-xfsctl --enable-libusb --enable-usb-redir \
+    --enable-libiscsi --enable-libnfs --enable-seccomp \
+    --enable-tpm --enable-libssh --enable-lzo --enable-snappy --enable-bzip2 \
+    --enable-numa --enable-rdma --enable-smartcard --enable-virglrenderer \
+    --enable-mpath --enable-libxml2 --enable-glusterfs \
+    --enable-virtfs --enable-zstd
+
+echo "Making libqemustub.a..."
+make libqemustub.a
+
+echo "Running cov-build..."
+rm -rf cov-int
+mkdir cov-int
+cov-build --dir cov-int $COVERITY_BUILD_CMD
+
+echo "Creating results tarball..."
+tar cvf - cov-int | xz > "$TARBALL"
+
+if [ ! -z "$RESULTSTARBALL" ]; then
+    echo "Copying results tarball to $RESULTSTARBALL..."
+    cp "$TARBALL" "$RESULTSTARBALL"
+fi
+
+echo "Uploading results tarball..."
+
+if [ "$DRYRUN" = yes ]; then
+    echo "Dry run only, not uploading $TARBALL"
+    exit 0
+fi
+
+curl --form token="$PROJTOKEN" --form email="$COVERITY_EMAIL" \
+     --form file=@"$TARBALL" --form version="$VERSION" \
+     --form description="$DESCRIPTION" \
+     https://scan.coverity.com/builds?project="$PROJNAME"
+
+echo "Done."
-- 
2.20.1

Add support for running the Coverity Scan tools inside a Docker
container rather than directly on the host system.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200319193323.2038-7-peter.maydell@linaro.org
---
 scripts/coverity-scan/coverity-scan.docker | 131 +++++++++++++++++++++
 scripts/coverity-scan/run-coverity-scan    |  90 ++++++++++++++
 2 files changed, 221 insertions(+)
 create mode 100644 scripts/coverity-scan/coverity-scan.docker

diff --git a/scripts/coverity-scan/coverity-scan.docker b/scripts/coverity-scan/coverity-scan.docker
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/scripts/coverity-scan/coverity-scan.docker
@@ -XXX,XX +XXX,XX @@
+# syntax=docker/dockerfile:1.0.0-experimental
+#
+# Docker setup for running the "Coverity Scan" tools over the source
+# tree and uploading them to the website, as per
+# https://scan.coverity.com/projects/qemu/builds/new
+# We do this on a fixed config (currently Fedora 30 with a known
+# set of dependencies and a configure command that enables a specific
+# set of options) so that random changes don't result in our accidentally
+# dropping some files from the scan.
+#
+# We don't build on top of the fedora.docker file because we don't
+# want to accidentally change or break the scan config when that
+# is updated.
+
+# The work of actually doing the build is handled by the
+# run-coverity-scan script.
+
+FROM fedora:30
+ENV PACKAGES \
+    alsa-lib-devel \
+    bc \
+    bison \
+    brlapi-devel \
+    bzip2 \
+    bzip2-devel \
+    ccache \
+    clang \
+    curl \
+    cyrus-sasl-devel \
+    dbus-daemon \
+    device-mapper-multipath-devel \
+    findutils \
+    flex \
+    gcc \
+    gcc-c++ \
+    gettext \
+    git \
+    glib2-devel \
+    glusterfs-api-devel \
+    gnutls-devel \
+    gtk3-devel \
+    hostname \
+    libaio-devel \
+    libasan \
+    libattr-devel \
+    libblockdev-mpath-devel \
+    libcap-devel \
+    libcap-ng-devel \
+    libcurl-devel \
+    libepoxy-devel \
+    libfdt-devel \
+    libgbm-devel \
+    libiscsi-devel \
+    libjpeg-devel \
+    libpmem-devel \
+    libnfs-devel \
+    libpng-devel \
+    librbd-devel \
+    libseccomp-devel \
+    libssh-devel \
+    libubsan \
+    libudev-devel \
+    libusbx-devel \
+    libxml2-devel \
+    libzstd-devel \
+    llvm \
+    lzo-devel \
+    make \
+    mingw32-bzip2 \
+    mingw32-curl \
+    mingw32-glib2 \
+    mingw32-gmp \
+    mingw32-gnutls \
+    mingw32-gtk3 \
+    mingw32-libjpeg-turbo \
+    mingw32-libpng \
+    mingw32-libtasn1 \
+    mingw32-nettle \
+    mingw32-nsis \
+    mingw32-pixman \
+    mingw32-pkg-config \
+    mingw32-SDL2 \
+    mingw64-bzip2 \
+    mingw64-curl \
+    mingw64-glib2 \
+    mingw64-gmp \
+    mingw64-gnutls \
+    mingw64-gtk3 \
+    mingw64-libjpeg-turbo \
+    mingw64-libpng \
+    mingw64-libtasn1 \
+    mingw64-nettle \
+    mingw64-pixman \
+    mingw64-pkg-config \
+    mingw64-SDL2 \
+    ncurses-devel \
+    nettle-devel \
+    nss-devel \
+    numactl-devel \
+    perl \
+    perl-Test-Harness \
+    pixman-devel \
+    pulseaudio-libs-devel \
+    python3 \
+    python3-sphinx \
+    PyYAML \
+    rdma-core-devel \
+    SDL2-devel \
+    snappy-devel \
+    sparse \
+    spice-server-devel \
+    systemd-devel \
+    systemtap-sdt-devel \
+    tar \
+    texinfo \
+    usbredir-devel \
+    virglrenderer-devel \
+    vte291-devel \
+    wget \
+    which \
+    xen-devel \
+    xfsprogs-devel \
+    zlib-devel
+ENV QEMU_CONFIGURE_OPTS --python=/usr/bin/python3
+
+RUN dnf install -y $PACKAGES
+RUN rpm -q $PACKAGES | sort > /packages.txt
+ENV PATH $PATH:/usr/libexec/python3-sphinx/
+ENV COVERITY_TOOL_BASE=/coverity-tools
+COPY run-coverity-scan run-coverity-scan
+RUN --mount=type=secret,id=coverity.token,required ./run-coverity-scan --update-tools-only --tokenfile /run/secrets/coverity.token
diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan
index XXXXXXX..XXXXXXX 100755
--- a/scripts/coverity-scan/run-coverity-scan
+++ b/scripts/coverity-scan/run-coverity-scan
@@ -XXX,XX +XXX,XX @@
 
 # Command line options:
 #   --dry-run : run the tools, but don't actually do the upload
+#   --docker : create and work inside a docker container
 #   --update-tools-only : update the cached copy of the tools, but don't run them
 #   --tokenfile : file to read Coverity token from
 #   --version ver : specify version being analyzed (default: ask git)
@@ -XXX,XX +XXX,XX @@
 #   --srcdir : QEMU source tree to analyze (default: current working dir)
 #   --results-tarball : path to copy the results tarball to (default: don't
 #                       copy it anywhere, just upload it)
+#   --src-tarball : tarball to untar into src dir (default: none); this
+#                   is intended mainly for internal use by the Docker support
 #
 # User-specifiable environment variables:
 #  COVERITY_TOKEN -- Coverity token
@@ -XXX,XX +XXX,XX @@ update_coverity_tools () {
 # Check user-provided environment variables and arguments
 DRYRUN=no
 UPDATE_ONLY=no
+DOCKER=no
 
 while [ "$#" -ge 1 ]; do
     case "$1" in
@@ -XXX,XX +XXX,XX @@ while [ "$#" -ge 1 ]; do
             RESULTSTARBALL="$1"
             shift
             ;;
+        --src-tarball)
+            shift
+            if [ $# -eq 0 ]; then
+                echo "--src-tarball needs an argument"
+                exit 1
+            fi
+            SRCTARBALL="$1"
+            shift
+            ;;
+        --docker)
+            DOCKER=yes
+            shift
+            ;;
         *)
             echo "Unexpected argument '$1'"
             exit 1
@@ -XXX,XX +XXX,XX @@ PROJTOKEN="$COVERITY_TOKEN"
 PROJNAME=QEMU
 TARBALL=cov-int.tar.xz
 
+if [ "$UPDATE_ONLY" = yes ] && [ "$DOCKER" = yes ]; then
+    echo "Combining --docker and --update-only is not supported"
+    exit 1
+fi
 
 if [ "$UPDATE_ONLY" = yes ]; then
     # Just do the tools update; we don't need to check whether
@@ -XXX,XX +XXX,XX @@ if [ "$UPDATE_ONLY" = yes ]; then
     exit 0
 fi
 
+if [ ! -e "$SRCDIR" ]; then
+    mkdir "$SRCDIR"
+fi
+
 cd "$SRCDIR"
 
+if [ ! -z "$SRCTARBALL" ]; then
+    echo "Untarring source tarball into $SRCDIR..."
+    tar xvf "$SRCTARBALL"
+fi
+
 echo "Checking this is a QEMU source tree..."
 if ! [ -e "$SRCDIR/VERSION" ]; then
     echo "Not in a QEMU source tree?"
@@ -XXX,XX +XXX,XX @@ if [ -z "$COVERITY_EMAIL" ]; then
     COVERITY_EMAIL="$(git config user.email)"
 fi
 
+# Run ourselves inside docker if that's what the user wants
+if [ "$DOCKER" = yes ]; then
+    # build docker container including the coverity-scan tools
+    # Put the Coverity token into a temporary file that only
+    # we have read access to, and then pass it to docker build
+    # using --secret. This requires at least Docker 18.09.
+    # Mostly what we are trying to do here is ensure we don't leak
+    # the token into the Docker image.
+    umask 077
+    SECRETDIR=$(mktemp -d)
+    if [ -z "$SECRETDIR" ]; then
+        echo "Failed to create temporary directory"
+        exit 1
+    fi
+    trap 'rm -rf "$SECRETDIR"' INT TERM EXIT
+    echo "Created temporary directory $SECRETDIR"
+    SECRET="$SECRETDIR/token"
+    echo "$COVERITY_TOKEN" > "$SECRET"
+    echo "Building docker container..."
+    # TODO: This re-downloads the tools every time, rather than
+    # caching and reusing the image produced with the downloaded tools.
+    # Not sure why.
+    # TODO: how do you get 'docker build' to print the output of the
+    # commands it is running to its stdout? This would be useful for debug.
+    DOCKER_BUILDKIT=1 docker build -t coverity-scanner \
+                   --secret id=coverity.token,src="$SECRET" \
+                   -f scripts/coverity-scan/coverity-scan.docker \
+                   scripts/coverity-scan
+    echo "Archiving sources to be analyzed..."
+    ./scripts/archive-source.sh "$SECRETDIR/qemu-sources.tgz"
+    if [ "$DRYRUN" = yes ]; then
+        DRYRUNARG=--dry-run
+    fi
+    echo "Running scanner..."
+    # If we need to capture the output tarball, get the inner run to
+    # save it to the secrets directory so we can copy it out before the
+    # directory is cleaned up.
+    if [ ! -z "$RESULTSTARBALL" ]; then
+        RTARGS="--results-tarball /work/cov-int.tar.xz"
+    else
+        RTARGS=""
+    fi
+    # Arrange for this docker run to get access to the sources with -v.
+    # We pass through all the configuration from the outer script to the inner.
+    export COVERITY_EMAIL COVERITY_BUILD_CMD
+    docker run -it --env COVERITY_EMAIL --env COVERITY_BUILD_CMD \
+           -v "$SECRETDIR:/work" coverity-scanner \
+           ./run-coverity-scan --version "$VERSION" \
+           --description "$DESCRIPTION" $DRYRUNARG --tokenfile /work/token \
+           --srcdir /qemu --src-tarball /work/qemu-sources.tgz $RTARGS
+    if [ ! -z "$RESULTSTARBALL" ]; then
+        echo "Copying results tarball to $RESULTSTARBALL..."
+        cp "$SECRETDIR/cov-int.tar.xz" "$RESULTSTARBALL"
+    fi
+    echo "Docker work complete."
+    exit 0
+fi
+
+# Otherwise, continue with the full build and upload process.
+
 check_upload_permissions
 
 update_coverity_tools
-- 
2.20.1

The documentation of our -s and -gdb options is quite old; in
particular it still claims that it will cause QEMU to stop and wait
for the gdb connection, when this has not been true for some time:
you also need to pass -S if you want to make QEMU not launch the
guest on startup.

Improve the documentation to mention this requirement in the
executable's --help output, the documentation of the -gdb option in
the manual, and in the "GDB usage" chapter.

Includes some minor tweaks to these paragraphs of documentation
since I was editing them anyway (such as dropping the description
of our gdb support as "primitive").

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200403094014.9589-1-peter.maydell@linaro.org
---
 docs/system/gdb.rst | 22 +++++++++++++++-------
 qemu-options.hx     | 24 ++++++++++++++++++------
 2 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/docs/system/gdb.rst b/docs/system/gdb.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/gdb.rst
+++ b/docs/system/gdb.rst
@@ -XXX,XX +XXX,XX @@
 GDB usage
 ---------
 
-QEMU has a primitive support to work with gdb, so that you can do
-'Ctrl-C' while the virtual machine is running and inspect its state.
+QEMU supports working with gdb via gdb's remote-connection facility
+(the "gdbstub"). This allows you to debug guest code in the same
+way that you might with a low-level debug facility like JTAG
+on real hardware. You can stop and start the virtual machine,
+examine state like registers and memory, and set breakpoints and
+watchpoints.
 
-In order to use gdb, launch QEMU with the '-s' option. It will wait for
-a gdb connection:
+In order to use gdb, launch QEMU with the ``-s`` and ``-S`` options.
+The ``-s`` option will make QEMU listen for an incoming connection
+from gdb on TCP port 1234, and ``-S`` will make QEMU not start the
+guest until you tell it to from gdb. (If you want to specify which
+TCP port to use or to use something other than TCP for the gdbstub
+connection, use the ``-gdb dev`` option instead of ``-s``.)
 
 .. parsed-literal::
 
-   |qemu_system| -s -kernel bzImage -hda rootdisk.img -append "root=/dev/hda"
-   Connected to host network interface: tun0
-   Waiting gdb connection on port 1234
+   |qemu_system| -s -S -kernel bzImage -hda rootdisk.img -append "root=/dev/hda"
+
+QEMU will launch but will silently wait for gdb to connect.
 
 Then launch gdb on the 'vmlinux' executable::
 
diff --git a/qemu-options.hx b/qemu-options.hx
index XXXXXXX..XXXXXXX 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -XXX,XX +XXX,XX @@ SRST
 ERST
 
 DEF("gdb", HAS_ARG, QEMU_OPTION_gdb, \
-    "-gdb dev        wait for gdb connection on 'dev'\n", QEMU_ARCH_ALL)
+    "-gdb dev        accept gdb connection on 'dev'. (QEMU defaults to starting\n"
+    "                the guest without waiting for gdb to connect; use -S too\n"
+    "                if you want it to not start execution.)\n",
+    QEMU_ARCH_ALL)
 SRST
 ``-gdb dev``
-    Wait for gdb connection on device dev (see
-    :ref:`gdb_005fusage`). Typical connections will likely be
-    TCP-based, but also UDP, pseudo TTY, or even stdio are reasonable
-    use case. The latter is allowing to start QEMU from within gdb and
-    establish the connection via a pipe:
+    Accept a gdb connection on device dev (see
+    :ref:`gdb_005fusage`). Note that this option does not pause QEMU
+    execution -- if you want QEMU to not start the guest until you
+    connect with gdb and issue a ``continue`` command, you will need to
+    also pass the ``-S`` option to QEMU.
+
+    The most usual configuration is to listen on a local TCP socket::
+
+        -gdb tcp::3117
+
+    but you can specify other backends; UDP, pseudo TTY, or even stdio
+    are all reasonable use cases. For example, a stdio connection
+    allows you to start QEMU from within gdb and establish the
+    connection via a pipe:
 
     .. parsed-literal::
 
-- 
2.20.1

If we are not making warnings fatal for compilation, make them
non-fatal when building the Sphinx documentation also.  (For instance
Sphinx 3.0 warns about some constructs that older versions were happy
with, which is a build failure if we use the warnings-as-errors
flag.)

This provides a workaround at least for LP:1872113.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200411182934.28678-2-peter.maydell@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 configure | 9 ++++++++-
 Makefile  | 2 +-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/configure b/configure
index XXXXXXX..XXXXXXX 100755
--- a/configure
+++ b/configure
@@ -XXX,XX +XXX,XX @@ if check_include sys/kcov.h ; then
     kcov=yes
 fi
 
+# If we're making warnings fatal, apply this to Sphinx runs as well
+sphinx_werror=""
+if test "$werror" = "yes"; then
+    sphinx_werror="-W"
+fi
+
 # Check we have a new enough version of sphinx-build
 has_sphinx_build() {
     # This is a bit awkward but works: create a trivial document and
@@ -XXX,XX +XXX,XX @@ has_sphinx_build() {
     # sphinx-build doesn't exist at all or if it is too old.
     mkdir -p "$TMPDIR1/sphinx"
     touch "$TMPDIR1/sphinx/index.rst"
-    "$sphinx_build" -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1
+    "$sphinx_build" $sphinx_werror -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1
 }
 
 # Check if tools are available to build documentation.
@@ -XXX,XX +XXX,XX @@ echo "INSTALL_PROG=$install -c -m 0755" >> $config_host_mak
 echo "INSTALL_LIB=$install -c -m 0644" >> $config_host_mak
 echo "PYTHON=$python" >> $config_host_mak
 echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak
+echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak
 echo "GENISOIMAGE=$genisoimage" >> $config_host_mak
 echo "CC=$cc" >> $config_host_mak
 if $iasl -h > /dev/null 2>&1; then
diff --git a/Makefile b/Makefile
index XXXXXXX..XXXXXXX 100644
--- a/Makefile
+++ b/Makefile
@@ -XXX,XX +XXX,XX @@ sphinxdocs: $(MANUAL_BUILDDIR)/devel/index.html \
 # Note the use of different doctree for each (manual, builder) tuple;
 # this works around Sphinx not handling parallel invocation on
 # a single doctree: https://github.com/sphinx-doc/sphinx/issues/2946
-build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) -W -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1")
+build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) $(SPHINX_WERROR) -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1")
 # We assume all RST files in the manual's directory are used in it
 manual-deps = $(wildcard $(SRC_PATH)/docs/$1/*.rst $(SRC_PATH)/docs/$1/*/*.rst) \
               $(SRC_PATH)/docs/defs.rst.inc \
-- 
2.20.1

When kernel-doc generates a 'c:function' directive for a function
one of whose arguments is a function pointer, it fails to print
the close-paren after the argument list of the function pointer
argument, for instance in the memory API documentation:
  .. c:function:: void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp)

which should have a ')' after the 'void *host' which is the
last argument to 'resized'.

Older versions of Sphinx don't try to parse the argumnet
to c:function, but Sphinx 3.0 does do this and will complain:

/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:834: WARNING: Error in declarator or parameters
  Invalid C declaration: Expecting "," or ")" in parameters, got "EOF". [error at 208]
    void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp)
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------^

Add the missing close-paren.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200411182934.28678-3-peter.maydell@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 scripts/kernel-doc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/kernel-doc b/scripts/kernel-doc
index XXXXXXX..XXXXXXX 100755
--- a/scripts/kernel-doc
+++ b/scripts/kernel-doc
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
 
 	if ($type =~ m/([^$]*\(\*)\s*$\s*$([^$]*)\)/) {
 	    # pointer-to-function
-	    print $1 . $parameter . ") (" . $2;
+	    print $1 . $parameter . ") (" . $2 . ")";
 	} else {
 	    print $type . " " . $parameter;
 	}
-- 
2.20.1

The kernel-doc Sphinx plugin and associated script currently emit
'c:type' directives for "struct foo" documentation.

Sphinx 3.0 warns about this:
  /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:3: WARNING: Type must be either just a name or a typedef-like declaration.
  If just a name:
    Error in declarator or parameters
    Invalid C declaration: Expected identifier in nested name, got keyword: struct [error at 6]
      struct MemoryListener
      ------^
  If typedef-like declaration:
    Error in declarator or parameters
    Invalid C declaration: Expected identifier in nested name. [error at 21]
      struct MemoryListener
      ---------------------^

because it wants us to use the new-in-3.0 'c:struct' instead.

Plumb the Sphinx version through to the kernel-doc script
and use it to select 'c:struct' for newer versions than 3.0.

Fixes: LP:1872113
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 docs/sphinx/kerneldoc.py |  1 +
 scripts/kernel-doc       | 16 +++++++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/docs/sphinx/kerneldoc.py b/docs/sphinx/kerneldoc.py
index XXXXXXX..XXXXXXX 100644
--- a/docs/sphinx/kerneldoc.py
+++ b/docs/sphinx/kerneldoc.py
@@ -XXX,XX +XXX,XX @@ class KernelDocDirective(Directive):
                 env.note_dependency(os.path.abspath(f))
                 cmd += ['-export-file', f]
 
+        cmd += ['-sphinx-version', sphinx.__version__]
         cmd += [filename]
 
         try:
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
index XXXXXXX..XXXXXXX 100755
--- a/scripts/kernel-doc
+++ b/scripts/kernel-doc
@@ -XXX,XX +XXX,XX @@ Output selection (mutually exclusive):
 			DOC: sections. May be specified multiple times.
 
 Output selection modifiers:
+  -sphinx-version VER   Generate rST syntax for the specified Sphinx version.
+                        Only works with reStructuredTextFormat.
   -no-doc-sections	Do not output DOC: sections.
   -enable-lineno        Enable output of #define LINENO lines. Only works with
                         reStructuredText format.
@@ -XXX,XX +XXX,XX @@ use constant {
 };
 my $output_selection = OUTPUT_ALL;
 my $show_not_found = 0;	# No longer used
+my $sphinx_version = "0.0"; # if not specified, assume old
 
 my @export_file_list;
 
@@ -XXX,XX +XXX,XX @@ while ($ARGV[0] =~ m/^--?(.*)/) {
 	    $enable_lineno = 1;
     } elsif ($cmd eq 'show-not-found') {
 	$show_not_found = 1;  # A no-op but don't fail
+    } elsif ($cmd eq 'sphinx-version') {
+        $sphinx_version = shift @ARGV;
     } else {
 	# Unknown argument
         usage();
@@ -XXX,XX +XXX,XX @@ sub output_struct_rst(%) {
     my $oldprefix = $lineprefix;
     my $name = $args{'type'} . " " . $args{'struct'};
 
-    print "\n\n.. c:type:: " . $name . "\n\n";
+    # Sphinx 3.0 and up will emit warnings for "c:type:: struct Foo".
+    # It wants to see "c:struct:: Foo" (and will add the word 'struct' in
+    # the rendered output).
+    if ((split(/\./, $sphinx_version))[0] >= 3) {
+        my $sname = $name;
+        $sname =~ s/^struct //;
+        print "\n\n.. c:struct:: " . $sname . "\n\n";
+    } else {
+        print "\n\n.. c:type:: " . $name . "\n\n";
+    }
     print_lineno($declaration_start_line);
     $lineprefix = "   ";
     output_highlight_rst($args{'purpose'});
-- 
2.20.1

Versions of Sphinx older than 1.6 can't build all of our documentation,
because they are too picky about the syntax of the argument to the
option:: directive; see Sphinx bugs #646, #3366:

https://github.com/sphinx-doc/sphinx/issues/646
  https://github.com/sphinx-doc/sphinx/issues/3366

Trying to build with a 1.4.x Sphinx fails with
 docs/system/images.rst:4: SEVERE: Duplicate ID: "cmdoption-qcow2-arg-encrypt"
and a 1.5.x Sphinx fails with
 docs/system/invocation.rst:544: WARNING: Malformed option description '[enable=]PATTERN', should look like "opt", "-opt
args", "--opt args", "/opt args" or "+opt args"

Update our needs_sphinx setting to indicate that we require at least
1.6.  This will allow configure to fall back to "don't build the
docs" rather than causing the build to fail entirely, which is
probably what most users building on a host old enough to have such
an old Sphinx would want; if they do want the docs then they'll have
a useful indication of what they need to do (upgrade Sphinx!) rather
than a confusing error message.

In theory our distro support policy would suggest that we should
support building on the Sphinx shipped in those distros, but:
 * EPEL7 has Sphinx 1.2.3 (which we've never supported!)
 * Debian Stretch has Sphinx 1.4.8

Trying to get our docs to work with Sphinx 1.4 is not tractable
for the 5.0 release and I'm not sure it's worthwhile effort anyway;
at least with this change the build as a whole now succeeds.

Thanks to John Snow for doing the investigation and testing to
confirm what Sphinx versions fail in what ways and what distros
shipped what.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 docs/conf.py | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/docs/conf.py b/docs/conf.py
index XXXXXXX..XXXXXXX 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ sys.path.insert(0, os.path.join(qemu_docdir, "sphinx"))
 
 # If your documentation needs a minimal Sphinx version, state it here.
 #
-# 1.3 is where the 'alabaster' theme was shipped with Sphinx.
-needs_sphinx = '1.3'
+# Sphinx 1.5 and earlier can't build our docs because they are too
+# picky about the syntax of the argument to the option:: directive
+# (see Sphinx bugs #646, #3366).
+needs_sphinx = '1.6'
 
 # Add any Sphinx extension module names here, as strings. They can be
 # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
-- 
2.20.1

The Linux kernel has dropped support for allowing 32-bit Arm systems
to host KVM guests (kernel commit 541ad0150ca4aa663a2, which just
landed upstream in the 5.7 merge window).  Mark QEMU's support for
this configuration as deprecated, so that we can delete that support
code in 5.2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
 docs/system/deprecated.rst | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ The ``compat`` property used to set backwards compatibility modes for
 the processor has been deprecated. The ``max-cpu-compat`` property of
 the ``pseries`` machine type should be used instead.
 
+KVM guest support on 32-bit Arm hosts (since 5.0)
+'''''''''''''''''''''''''''''''''''''''''''''''''
+
+The Linux kernel has dropped support for allowing 32-bit Arm systems
+to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
+its support for this configuration and will remove it in a future version.
+Running 32-bit guests on a 64-bit Arm host remains supported.
+
 System emulator devices
 -----------------------
 
-- 
2.20.1

The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216

for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:

tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * Some mostly M-profile-related code cleanups
 * avocado: Retire the boot_linux.py AArch64 TCG tests
 * hw/arm/smmuv3: Add GBPA register
 * arm/virt: don't try to spell out the accelerator
 * hw/arm: Attach PSPI module to NPCM7XX SoC
 * Some cleanup/refactoring patches aiming towards
   allowing building Arm targets without CONFIG_TCG

----------------------------------------------------------------
Alex Bennée (1):
      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py

Claudio Fontana (3):
      target/arm: rename handle_semihosting to tcg_handle_semihosting
      target/arm: wrap psci call with tcg_enabled
      target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()

Cornelia Huck (1):
      arm/virt: don't try to spell out the accelerator

Fabiano Rosas (7):
      target/arm: Move PC alignment check
      target/arm: Move cpregs code out of cpu.h
      tests/avocado: Skip tests that require a missing accelerator
      tests/avocado: Tag TCG tests with accel:tcg
      target/arm: Use "max" as default cpu for the virt machine with KVM
      tests/qtest: arm-cpu-features: Match tests to required accelerators
      tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG

Hao Wu (3):
      MAINTAINERS: Add myself to maintainers and remove Havard
      hw/ssi: Add Nuvoton PSPI Module
      hw/arm: Attach PSPI module to NPCM7XX SoC

Jean-Philippe Brucker (2):
      hw/arm/smmu-common: Support 64-bit addresses
      hw/arm/smmu-common: Fix TTB1 handling

Mostafa Saleh (1):
      hw/arm/smmuv3: Add GBPA register

Philippe Mathieu-Daudé (12):
      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
      target/arm: Constify ID_PFR1 on user emulation
      target/arm: Convert CPUARMState::eabi to boolean
      target/arm: Avoid resetting CPUARMState::eabi field
      target/arm: Restrict CPUARMState::gicv3state to sysemu
      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
      target/arm: Restrict CPUARMState::nvic to sysemu
      target/arm: Store CPUARMState::nvic as NVICState*
      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
similarly to automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_NVIC "armv7m_nvic"
-
-typedef struct NVICState NVICState;
-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
-                         TYPE_NVIC)
+OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
 
 /* Highest permitted number of exceptions (architectural limit) */
 #define NVIC_MAX_VECTORS 512
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return 0;
 }
 
-#else
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    return ARMMMUIdx_MUser;
+}
+
+#else /* !CONFIG_USER_ONLY */
 
 /*
  * What kind of stack write are we doing? This affects how exceptions
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
                               bool secstate, bool priv, bool negpri)
 {
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 }
+
+#endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
are only used for system emulation in m_helper.c.
Move the definitions to avoid prototype forward declarations.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 14 --------
 target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
 2 files changed, 37 insertions(+), 51 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
 
 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
 
-/*
- * Return the MMU index for a v7M CPU with all relevant information
- * manually specified.
- */
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri);
-
-/*
- * Return the MMU index for a v7M CPU in the specified security and
- * privilege state.
- */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv);
-
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
 
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
 #else /* !CONFIG_USER_ONLY */
 
+static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                                     bool secstate, bool priv, bool negpri)
+{
+    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+
+    if (priv) {
+        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+    }
+
+    if (negpri) {
+        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+    }
+
+    if (secstate) {
+        mmu_idx |= ARM_MMU_IDX_M_S;
+    }
+
+    return mmu_idx;
+}
+
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+                                                       bool secstate, bool priv)
+{
+    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
+/* Return the MMU index for a v7M CPU in the specified security state */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    bool priv = arm_v7m_is_handler_mode(env) ||
+        !(env->v7m.control[secstate] & 1);
+
+    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
 /*
  * What kind of stack write are we doing? This affects how exceptions
  * generated during the stacking are treated.
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri)
-{
-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
-
-    if (priv) {
-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
-    }
-
-    if (negpri) {
-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
-    }
-
-    if (secstate) {
-        mmu_idx |= ARM_MMU_IDX_M_S;
-    }
-
-    return mmu_idx;
-}
-
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv)
-{
-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
-
-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
-}
-
-/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
-    bool priv = arm_v7m_is_handler_mode(env) ||
-        !(env->v7m.control[secstate] & 1);
-
-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
-}
-
 #endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     }
 }
 
+#ifndef CONFIG_USER_ONLY
 /*
  * We don't know until after realize whether there's a GICv3
  * attached, and that is what registers the gicv3 sysregs.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
     return pfr1;
 }
 
-#ifndef CONFIG_USER_ONLY
 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_NO_RAW,
               .accessfn = access_aa32_tid3,
+#ifdef CONFIG_USER_ONLY
+              .type = ARM_CP_CONST,
+              .resetvalue = cpu->isar.id_pfr1,
+#else
+              .type = ARM_CP_NO_RAW,
+              .accessfn = access_aa32_tid3,
               .readfn = id_pfr1_read,
-              .writefn = arm_cp_write_ignore },
+              .writefn = arm_cp_write_ignore
+#endif
+            },
             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/user-internals.h | 2 +-
 target/arm/cpu.h            | 2 +-
 linux-user/arm/cpu_loop.c   | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/user-internals.h
+++ b/linux-user/user-internals.h
@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
 #ifdef TARGET_ARM
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
 {
-    return cpu_env->eabi == 1;
+    return cpu_env->eabi;
 }
 #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
 
 #if defined(CONFIG_USER_ONLY)
     /* For usermode syscall translation.  */
-    int eabi;
+    bool eabi;
 #endif
 
     struct CPUBreakpoint *cpu_breakpoint[16];
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
             break;
         case EXCP_SWI:
             {
-                env->eabi = 1;
+                env->eabi = true;
                 /* system call */
                 if (env->thumb) {
                     /* Thumb is always EABI style with syscall number in r7 */
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
                          * > 0xfffff and are handled below as out-of-range.
                          */
                         n ^= ARM_SYSCALL_BASE;
-                        env->eabi = 0;
+                        env->eabi = false;
                     }
                 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Although the 'eabi' field is only used in user emulation where
CPU reset doesn't occur, it doesn't belong to the area to reset.
Move it after the 'end_reset_fields' for consistency.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     ARMVectorReg zarray[ARM_MAX_VQ * 16];
 #endif
 
-#if defined(CONFIG_USER_ONLY)
-    /* For usermode syscall translation.  */
-    bool eabi;
-#endif
-
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
+#if defined(CONFIG_USER_ONLY)
+    /* For usermode syscall translation.  */
+    bool eabi;
+#endif /* CONFIG_USER_ONLY */
 
 #ifdef TARGET_TAGGED_ADDRESSES
     /* Linux syscall tagged address support */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

There is no point in using a void pointer to access the NVIC.
Use the real type to avoid casting it while debugging.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
 hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
 target/arm/cpu.c      |  1 +
 target/arm/m_helper.c |  2 +-
 4 files changed, 39 insertions(+), 48 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
 
 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 
+typedef struct NVICState NVICState;
+
 typedef struct CPUArchState {
     /* Regs for current mode.  */
     uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     } sau;
 
 #if !defined(CONFIG_USER_ONLY)
-    void *nvic;
+    NVICState *nvic;
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
 
 /* Interface between CPU and Interrupt controller.  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(void *opaque);
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 #else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
     return true;
 }
 #endif
 /**
  * armv7m_nvic_set_pending: mark the specified exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
  * exceptions (exceptions generated in the course of trying to take
  * a different exception).
  */
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
  * generated in the course of lazy stacking of FP registers.
  */
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_pending_irq_info: return highest priority pending
  *    exception, and whether it targets Secure state
- * @opaque: the NVIC
+ * @s: the NVIC
  * @pirq: set to pending exception number
  * @ptargets_secure: set to whether pending exception targets Secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
  * to true if the current highest priority pending exception should
  * be taken to Secure state, false for NS.
  */
-void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                       bool *ptargets_secure);
 /**
  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Move the current highest priority pending exception from the pending
  * state to the active state, and update v7m.exception to indicate that
  * it is the exception currently being handled.
  */
-void armv7m_nvic_acknowledge_irq(void *opaque);
+void armv7m_nvic_acknowledge_irq(NVICState *s);
 /**
  * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to complete
  * @secure: true if this exception was secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
  *           0 if there is still an irq active after this one was completed
  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
  */
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
  * interrupt the current execution priority. This controls whether the
  * RDY bit for it in the FPCCR is set.
  */
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Returns: the raw execution priority as defined by the v8M architecture.
  * This is the execution priority minus the effects of AIRCR.PRIS,
  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
  * (v8M ARM ARM I_PKLD.)
  */
-int armv7m_nvic_raw_execution_priority(void *opaque);
+int armv7m_nvic_raw_execution_priority(NVICState *s);
 /**
  * armv7m_nvic_neg_prio_requested: return true if the requested execution
  * priority is negative for the specified security state.
- * @opaque: the NVIC
+ * @s: the NVIC
  * @secure: the security state to test
  * This corresponds to the pseudocode IsReqExecPriNeg().
  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 #else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     return false;
 }
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
     return MIN(running, s->exception_prio);
 }
 
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     /* Return true if the requested execution priority is negative
      * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      * mean we don't allow FAULTMASK_NS to actually make the execution
      * priority negative). Compare pseudocode IsReqExcPriNeg().
      */
-    NVICState *s = opaque;
-
     if (s->cpu->env.v7m.faultmask[secure]) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
     return false;
 }
 
-bool armv7m_nvic_can_take_pending_exception(void *opaque)
+bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return nvic_exec_prio(s) > nvic_pending_prio(s);
 }
 
-int armv7m_nvic_raw_execution_priority(void *opaque)
+int armv7m_nvic_raw_execution_priority(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return s->exception_prio;
 }
 
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
+static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
     }
 }
 
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
+    do_armv7m_nvic_set_pending(s, irq, secure, false);
 }
 
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
+    do_armv7m_nvic_set_pending(s, irq, secure, true);
 }
 
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
 {
     /*
      * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
      * whether we should escalate depends on the saved context
      * in the FPCCR register, not on the current state of the CPU/NVIC.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 }
 
 /* Make pending IRQ active.  */
-void armv7m_nvic_acknowledge_irq(void *opaque)
+void armv7m_nvic_acknowledge_irq(NVICState *s)
 {
-    NVICState *s = (NVICState *)opaque;
     CPUARMState *env = &s->cpu->env;
     const int pending = s->vectpending;
     const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
         exc_targets_secure(s, s->vectpending);
 }
 
-void armv7m_nvic_get_pending_irq_info(void *opaque,
+void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                       int *pirq, bool *ptargets_secure)
 {
-    NVICState *s = (NVICState *)opaque;
     const int pending = s->vectpending;
     bool targets_secure;
 
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
     *pirq = pending;
 }
 
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec = NULL;
     int ret = 0;
 
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
     return ret;
 }
 
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
 {
     /*
      * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
      * for non-banked exceptions secure is always false; for banked exceptions
      * it indicates which of the exceptions is required.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     int running = nvic_exec_prio(s);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#include "hw/intc/armv7m_nvic.h"
 #endif
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
      * that we will need later in order to do lazy FP reg stacking.
      */
     bool is_secure = env->v7m.secure;
-    void *nvic = env->nvic;
+    NVICState *nvic = env->nvic;
     /*
      * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
      * are banked and we want to update the bit in the bank for the
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

While dozens of files include "cpu.h", only 3 files require
these NVIC helper declarations.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
 target/arm/cpu.h              | 123 ----------------------------------
 target/arm/cpu.c              |   4 +-
 target/arm/cpu_tcg.c          |   3 +
 target/arm/m_helper.c         |   3 +
 5 files changed, 132 insertions(+), 124 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
     qemu_irq sysresetreq;
 };
 
+/* Interface between CPU and Interrupt controller.  */
+/**
+ * armv7m_nvic_set_pending: mark the specified exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Marks the specified exception as pending. Note that we will assert()
+ * if @secure is true and @irq does not specify one of the fixed set
+ * of architecturally banked exceptions.
+ */
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_derived: mark this derived exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for derived
+ * exceptions (exceptions generated in the course of trying to take
+ * a different exception).
+ */
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
+ * generated in the course of lazy stacking of FP registers.
+ */
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_pending_irq_info: return highest priority pending
+ *    exception, and whether it targets Secure state
+ * @s: the NVIC
+ * @pirq: set to pending exception number
+ * @ptargets_secure: set to whether pending exception targets Secure
+ *
+ * This function writes the number of the highest priority pending
+ * exception (the one which would be made active by
+ * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
+ * to true if the current highest priority pending exception should
+ * be taken to Secure state, false for NS.
+ */
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
+                                      bool *ptargets_secure);
+/**
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
+ * @s: the NVIC
+ *
+ * Move the current highest priority pending exception from the pending
+ * state to the active state, and update v7m.exception to indicate that
+ * it is the exception currently being handled.
+ */
+void armv7m_nvic_acknowledge_irq(NVICState *s);
+/**
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
+ * @s: the NVIC
+ * @irq: the exception number to complete
+ * @secure: true if this exception was secure
+ *
+ * Returns: -1 if the irq was not active
+ *           1 if completing this irq brought us back to base (no active irqs)
+ *           0 if there is still an irq active after this one was completed
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ */
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Return whether an exception is "ready", i.e. whether the exception is
+ * enabled and is configured at a priority which would allow it to
+ * interrupt the current execution priority. This controls whether the
+ * RDY bit for it in the FPCCR is set.
+ */
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_raw_execution_priority: return the raw execution priority
+ * @s: the NVIC
+ *
+ * Returns: the raw execution priority as defined by the v8M architecture.
+ * This is the execution priority minus the effects of AIRCR.PRIS,
+ * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
+ * (v8M ARM ARM I_PKLD.)
+ */
+int armv7m_nvic_raw_execution_priority(NVICState *s);
+/**
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
+ * priority is negative for the specified security state.
+ * @s: the NVIC
+ * @secure: the security state to test
+ * This corresponds to the pseudocode IsReqExecPriNeg().
+ */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
+#else
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
+{
+    return false;
+}
+#endif
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
+{
+    return true;
+}
+#endif
+
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface between CPU and Interrupt controller.  */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(NVICState *s);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
-{
-    return true;
-}
-#endif
-/**
- * armv7m_nvic_set_pending: mark the specified exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Marks the specified exception as pending. Note that we will assert()
- * if @secure is true and @irq does not specify one of the fixed set
- * of architecturally banked exceptions.
- */
-void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for derived
- * exceptions (exceptions generated in the course of trying to take
- * a different exception).
- */
-void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
- * generated in the course of lazy stacking of FP registers.
- */
-void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_pending_irq_info: return highest priority pending
- *    exception, and whether it targets Secure state
- * @s: the NVIC
- * @pirq: set to pending exception number
- * @ptargets_secure: set to whether pending exception targets Secure
- *
- * This function writes the number of the highest priority pending
- * exception (the one which would be made active by
- * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
- * to true if the current highest priority pending exception should
- * be taken to Secure state, false for NS.
- */
-void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
-                                      bool *ptargets_secure);
-/**
- * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @s: the NVIC
- *
- * Move the current highest priority pending exception from the pending
- * state to the active state, and update v7m.exception to indicate that
- * it is the exception currently being handled.
- */
-void armv7m_nvic_acknowledge_irq(NVICState *s);
-/**
- * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @s: the NVIC
- * @irq: the exception number to complete
- * @secure: true if this exception was secure
- *
- * Returns: -1 if the irq was not active
- *           1 if completing this irq brought us back to base (no active irqs)
- *           0 if there is still an irq active after this one was completed
- * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
- */
-int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Return whether an exception is "ready", i.e. whether the exception is
- * enabled and is configured at a priority which would allow it to
- * interrupt the current execution priority. This controls whether the
- * RDY bit for it in the FPCCR is set.
- */
-bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @s: the NVIC
- *
- * Returns: the raw execution priority as defined by the v8M architecture.
- * This is the execution priority minus the effects of AIRCR.PRIS,
- * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
- * (v8M ARM ARM I_PKLD.)
- */
-int armv7m_nvic_raw_execution_priority(NVICState *s);
-/**
- * armv7m_nvic_neg_prio_requested: return true if the requested execution
- * priority is negative for the specified security state.
- * @s: the NVIC
- * @secure: the security state to test
- * This corresponds to the pseudocode IsReqExecPriNeg().
- */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
-{
-    return false;
-}
-#endif
-
 /* Interface for defining coprocessor registers.
  * Registers are defined in tables of arm_cp_reginfo structs
  * which are passed to define_arm_cp_regs().
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#ifdef CONFIG_TCG
 #include "hw/intc/armv7m_nvic.h"
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
 #include "sysemu/hw_accel.h"
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #endif
 #include "cpregs.h"
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 
 /* Share AArch32 -cpu max features with AArch64. */
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                          uint32_t reg, uint32_t val)
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

The two TCG tests for GICv2 and GICv3 are very heavy weight distros
that take a long time to boot up, especially for an --enable-debug
build. The total code coverage they give is:

Overall coverage rate:
    lines......: 11.2% (59584 of 530123 lines)
    functions..: 15.0% (7436 of 49443 functions)
    branches...: 6.3% (19273 of 303933 branches)

We already get pretty close to that with the machine_aarch64_virt
tests which only does one full boot (~120s vs ~600s) of alpine. We
expand the kernel+initrd boot (~8s) to test both GICs and also add an
RNG device and a block device to generate a few IRQs and exercise the
storage layer. With that we get to a coverage of:

Overall coverage rate:
    lines......: 11.0% (58121 of 530123 lines)
    functions..: 14.9% (7343 of 49443 functions)
    branches...: 6.0% (18269 of 303933 branches)

which I feel is close enough given the massive time saving. If we want
to target any more sub-systems we can use lighter weight more directed
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux.py           | 48 ++++----------------
 tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 2 files changed, 65 insertions(+), 46 deletions(-)

diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
-# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
-# heavyweight. There are lighter weight distros which we use in the
-# machine_aarch64_virt.py tests.
+# For Aarch64 we only boot KVM tests in CI as booting the current
+# Fedora OS in TCG tests is very heavyweight. There are lighter weight
+# distros which we use in the machine_aarch64_virt.py tests.
 class BootLinuxAarch64(LinuxTest):
     """
     :avocado: tags=arch:aarch64
     :avocado: tags=machine:virt
-    :avocado: tags=machine:gic-version=2
     """
     timeout = 720
 
-    def add_common_args(self):
-        self.vm.add_args('-bios',
-                         os.path.join(BUILD_DIR, 'pc-bios',
-                                      'edk2-aarch64-code.fd'))
-        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
-        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv2(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv2
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=2")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv3(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv3
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=3")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
     def test_virt_kvm(self):
         """
         :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
         self.require_accelerator("kvm")
         self.vm.add_args("-accel", "kvm")
         self.vm.add_args("-machine", "virt,gic-version=host")
-        self.add_common_args()
+        self.vm.add_args('-bios',
+                         os.path.join(BUILD_DIR, 'pc-bios',
+                                      'edk2-aarch64-code.fd'))
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aarch64_virt.py
+++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
 
 import time
 import os
+import logging
 
 from avocado_qemu import QemuSystemTest
 from avocado_qemu import wait_for_console_pattern
 from avocado_qemu import exec_command
 from avocado_qemu import BUILD_DIR
+from avocado.utils import process
+from avocado.utils.path import find_command
 
 class Aarch64VirtMachine(QemuSystemTest):
     KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
         self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 
 
-    def test_aarch64_virt(self):
+    def common_aarch64_virt(self, machine):
         """
-        :avocado: tags=arch:aarch64
-        :avocado: tags=machine:virt
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
+        Common code to launch basic virt machine with kernel+initrd
+        and a scratch disk.
         """
+        logger = logging.getLogger('aarch64_virt')
+
         kernel_url = ('https://fileserver.linaro.org/s/'
                       'z6B2ARM7DQT3HWN/download')
-
         kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
         kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                'console=ttyAMA0')
         self.require_accelerator("tcg")
         self.vm.add_args('-cpu', 'max,pauth-impdef=on',
+                         '-machine', machine,
                          '-accel', 'tcg',
                          '-kernel', kernel_path,
                          '-append', kernel_command_line)
+
+        # A RNG offers an easy way to generate a few IRQs
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object',
+                         'rng-random,id=rng0,filename=/dev/urandom')
+
+        # Also add a scratch block device
+        logger.info('creating scratch qcow2 image')
+        image_path = os.path.join(self.workdir, 'scratch.qcow2')
+        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
+        if not os.path.exists(qemu_img):
+            qemu_img = find_command('qemu-img', False)
+        if qemu_img is False:
+            self.cancel('Could not find "qemu-img", which is required to '
+                        'create the temporary qcow2 image')
+        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
+        process.run(cmd)
+
+        # Add the device
+        self.vm.add_args('-blockdev',
+                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
+        self.vm.add_args('-device',
+                         'virtio-blk-device,drive=scratch')
+
         self.vm.launch()
         self.wait_for_console_pattern('Welcome to Buildroot')
         time.sleep(0.1)
         exec_command(self, 'root')
         time.sleep(0.1)
+        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
+        time.sleep(0.1)
+        exec_command(self, 'md5sum /dev/vda')
+        time.sleep(0.1)
+        exec_command(self, 'cat /proc/interrupts')
+        time.sleep(0.1)
         exec_command(self, 'cat /proc/self/maps')
         time.sleep(0.1)
+
+    def test_aarch64_virt_gicv3(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic_version=3")
+
+    def test_aarch64_virt_gicv2(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic-version=2")
-- 
2.34.1

From: Mostafa Saleh <smostafa@google.com>

GBPA register can be used to globally abort all
transactions.

It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).

Other fields have default values of Use Incoming.

If UPDATE is not set, the write is ignored. This is the only permitted
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)

As this patch adds a new state to the SMMU (GBPA), it is added
in a new subsection for forward migration compatibility.
GBPA is only migrated if its value is different from the reset value.
It does this to be backward migration compatible if SW didn't write
the register.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214094009.2445653-1-smostafa@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h |  7 +++++++
 include/hw/arm/smmuv3.h  |  1 +
 hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
 3 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
 REG32(CR1,                 0x28)
 REG32(CR2,                 0x2c)
 REG32(STATUSR,             0x40)
+REG32(GBPA,                0x44)
+    FIELD(GBPA, ABORT,        20, 1)
+    FIELD(GBPA, UPDATE,       31, 1)
+
+/* Use incoming. */
+#define SMMU_GBPA_RESET_VAL 0x1000
+
 REG32(IRQ_CTRL,            0x50)
     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
     uint32_t cr[3];
     uint32_t cr0ack;
     uint32_t statusr;
+    uint32_t gbpa;
     uint32_t irq_ctrl;
     uint32_t gerror;
     uint32_t gerrorn;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->gerror = 0;
     s->gerrorn = 0;
     s->statusr = 0;
+    s->gbpa = SMMU_GBPA_RESET_VAL;
 }
 
 static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
     qemu_mutex_lock(&s->mutex);
 
     if (!smmu_enabled(s)) {
-        status = SMMU_TRANS_DISABLE;
+        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
+            status = SMMU_TRANS_ABORT;
+        } else {
+            status = SMMU_TRANS_DISABLE;
+        }
         goto epilogue;
     }
 
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
     case A_GERROR_IRQ_CFG2:
         s->gerror_irq_cfg2 = data;
         return MEMTX_OK;
+    case A_GBPA:
+        /*
+         * If UPDATE is not set, the write is ignored. This is the only
+         * permitted behavior in SMMUv3.2 and later.
+         */
+        if (data & R_GBPA_UPDATE_MASK) {
+            /* Ignore update bit as write is synchronous. */
+            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
+        }
+        return MEMTX_OK;
     case A_STRTAB_BASE: /* 64b */
         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
         return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
     case A_STATUSR:
         *data = s->statusr;
         return MEMTX_OK;
+    case A_GBPA:
+        *data = s->gbpa;
+        return MEMTX_OK;
     case A_IRQ_CTRL:
     case A_IRQ_CTRL_ACK:
         *data = s->irq_ctrl;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
     },
 };
 
+static bool smmuv3_gbpa_needed(void *opaque)
+{
+    SMMUv3State *s = opaque;
+
+    /* Only migrate GBPA if it has different reset value. */
+    return s->gbpa != SMMU_GBPA_RESET_VAL;
+}
+
+static const VMStateDescription vmstate_gbpa = {
+    .name = "smmuv3/gbpa",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = smmuv3_gbpa_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(gbpa, SMMUv3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_smmuv3 = {
     .name = "smmuv3",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
 
         VMSTATE_END_OF_LIST(),
     },
+    .subsections = (const VMStateDescription * []) {
+        &vmstate_gbpa,
+        NULL
+    }
 };
 
 static void smmuv3_instance_init(Object *obj)
-- 
2.34.1

From: Cornelia Huck <cohuck@redhat.com>

Just use current_accel_name() directly.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Security extensions (TrustZone) to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Virtualization extensions to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "MTE to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Chris Rauer <crauer@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                |   6 +-
 include/hw/ssi/npcm_pspi.h |  53 +++++++++
 hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
 hw/ssi/meson.build         |   2 +-
 hw/ssi/trace-events        |   5 +
 5 files changed, 283 insertions(+), 4 deletions(-)
 create mode 100644 include/hw/ssi/npcm_pspi.h
 create mode 100644 hw/ssi/npcm_pspi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
 M: Hao Wu <wuhaotsh@google.com>
 L: qemu-arm@nongnu.org
 S: Supported
-F: hw/*/npcm7xx*
-F: include/hw/*/npcm7xx*
-F: tests/qtest/npcm7xx*
+F: hw/*/npcm*
+F: include/hw/*/npcm*
+F: tests/qtest/npcm*
 F: pc-bios/npcm7xx_bootrom.bin
 F: roms/vbootrom
 F: docs/system/arm/nuvoton.rst
diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/ssi/npcm_pspi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton Peripheral SPI Module
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM_PSPI_H
+#define NPCM_PSPI_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM_PSPI_NR_REGS 3
+
+/**
+ * NPCMPSPIState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ * @irq: The interrupt request queue for this module.
+ *
+ * Each PSPI has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+typedef struct NPCMPSPIState {
+    SysBusDevice parent;
+
+    MemoryRegion mmio;
+
+    SSIBus *spi;
+    uint16_t regs[NPCM_PSPI_NR_REGS];
+    qemu_irq irq;
+} NPCMPSPIState;
+
+#define TYPE_NPCM_PSPI "npcm-pspi"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
+
+#endif /* NPCM_PSPI_H */
diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/ssi/npcm_pspi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM Peripheral SPI Module (PSPI)
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/npcm_pspi.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+REG16(PSPI_DATA, 0x0)
+REG16(PSPI_CTL1, 0x2)
+    FIELD(PSPI_CTL1, SPIEN, 0,  1)
+    FIELD(PSPI_CTL1, MOD,   2,  1)
+    FIELD(PSPI_CTL1, EIR,   5,  1)
+    FIELD(PSPI_CTL1, EIW,   6,  1)
+    FIELD(PSPI_CTL1, SCM,   7,  1)
+    FIELD(PSPI_CTL1, SCIDL, 8,  1)
+    FIELD(PSPI_CTL1, SCDV,  9,  7)
+REG16(PSPI_STAT, 0x4)
+    FIELD(PSPI_STAT, BSY,  0,  1)
+    FIELD(PSPI_STAT, RBF,  1,  1)
+
+static void npcm_pspi_update_irq(NPCMPSPIState *s)
+{
+    int level = 0;
+
+    /* Only fire IRQ when the module is enabled. */
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
+        /* Update interrupt as BSY is cleared. */
+        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
+            level = 1;
+        }
+
+        /* Update interrupt as RBF is set. */
+        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
+            level = 1;
+        }
+    }
+    qemu_set_irq(s->irq, level);
+}
+
+static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
+{
+    uint16_t value = s->regs[R_PSPI_DATA];
+
+    /* Clear stat bits as the value are read out. */
+    s->regs[R_PSPI_STAT] = 0;
+
+    return value;
+}
+
+static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
+{
+    uint16_t value = 0;
+
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
+        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
+    }
+    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
+    s->regs[R_PSPI_DATA] = value;
+
+    /* Mark data as available */
+    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
+}
+
+/* Control register read handler. */
+static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
+                                    unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value;
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        value = npcm_pspi_read_data(s);
+        break;
+
+    case A_PSPI_CTL1:
+        value = s->regs[R_PSPI_CTL1];
+        break;
+
+    case A_PSPI_STAT:
+        value = s->regs[R_PSPI_STAT];
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return 0;
+    }
+    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+    npcm_pspi_update_irq(s);
+
+    return value;
+}
+
+/* Control register write handler. */
+static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+                                 unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value = v;
+
+    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        npcm_pspi_write_data(s, value);
+        break;
+
+    case A_PSPI_CTL1:
+        s->regs[R_PSPI_CTL1] = value;
+        break;
+
+    case A_PSPI_STAT:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only register PSPI_STAT: 0x%08"
+                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return;
+    }
+    npcm_pspi_update_irq(s);
+}
+
+static const MemoryRegionOps npcm_pspi_ctrl_ops = {
+    .read = npcm_pspi_ctrl_read,
+    .write = npcm_pspi_ctrl_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+    .impl = {
+        .min_access_size = 2,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+};
+
+static void npcm_pspi_enter_reset(Object *obj, ResetType type)
+{
+    NPCMPSPIState *s = NPCM_PSPI(obj);
+
+    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void npcm_pspi_realize(DeviceState *dev, Error **errp)
+{
+    NPCMPSPIState *s = NPCM_PSPI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    Object *obj = OBJECT(dev);
+
+    s->spi = ssi_create_bus(dev, "pspi");
+    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
+                          "mmio", 4 * KiB);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_npcm_pspi = {
+    .name = "npcm-pspi",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+
+static void npcm_pspi_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM Peripheral SPI Module";
+    dc->realize = npcm_pspi_realize;
+    dc->vmsd = &vmstate_npcm_pspi;
+    rc->phases.enter = npcm_pspi_enter_reset;
+}
+
+static const TypeInfo npcm_pspi_types[] = {
+    {
+        .name = TYPE_NPCM_PSPI,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(NPCMPSPIState),
+        .class_init = npcm_pspi_class_init,
+    },
+};
+DEFINE_TYPES(npcm_pspi_types);
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
 softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
 softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
 softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
 npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 
+# npcm_pspi.c
+npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+
 # ibex_spi_host.c
 
 ibex_spi_host_reset(const char *msg) "%s"
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst |  2 +-
 include/hw/arm/npcm7xx.h    |  2 ++
 hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * SMBus controller (SMBF)
  * Ethernet controller (EMC)
  * Tachometer
+ * Peripheral SPI controller (PSPI)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
 
  * Ethernet controller (GMAC)
  * USB device (USBD)
- * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
  * PCI and PCIe root complex and bridges
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/ssi/npcm_pspi.h"
 #include "hw/usb/hcd-ehci.h"
 #include "hw/usb/hcd-ohci.h"
 #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
     NPCM7xxFIUState     fiu[2];
     NPCM7xxEMCState     emc[2];
     NPCM7xxSDHCIState   mmc;
+    NPCMPSPIState       pspi[2];
 };
 
 #define TYPE_NPCM7XX    "npcm7xx"
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_EMC1RX_IRQ          = 15,
     NPCM7XX_EMC1TX_IRQ,
     NPCM7XX_MMC_IRQ             = 26,
+    NPCM7XX_PSPI2_IRQ           = 28,
+    NPCM7XX_PSPI1_IRQ           = 31,
     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
     NPCM7XX_TIMER1_IRQ,
     NPCM7XX_TIMER2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
     0xf0826000,
 };
 
+/* Register base address for each PSPI Module */
+static const hwaddr npcm7xx_pspi_addr[] = {
+    0xf0200000,
+    0xf0201000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
     }
 
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
+    }
+
     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
 
+    /* PSPI */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
+        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
+
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
+        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+    }
+
     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 2 --
 hw/arm/smmu-common.c         | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@
 #define SMMU_PCI_DEVFN_MAX    256
 #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
 
-#define SMMU_MAX_VA_BITS      48
-
 /*
  * Page table walk error types
  */
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
 
         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
                                  s->mrtypename,
-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
+                                 OBJECT(s), name, UINT64_MAX);
         address_space_init(&sdev->as,
                            MEMORY_REGION(&sdev->iommu), name);
         trace_smmu_add_mr(name);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.

Reported-by: Ola Hugosson <ola.hugosson@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
         /* there is a ttbr0 region and we are in it (high bits all zero) */
         return &cfg->tt[0];
     } else if (cfg->tt[1].tsz &&
-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
+        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
         /* there is a ttbr1 region and we are in it (high bits all one) */
         return &cfg->tt[1];
     } else if (!cfg->tt[0].tsz) {
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

make it clearer from the name that this is a tcg-only function.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
  * trapped to the hypervisor in KVM.
  */
 #ifdef CONFIG_TCG
-static void handle_semihosting(CPUState *cs)
+static void tcg_handle_semihosting(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
      */
 #ifdef CONFIG_TCG
     if (cs->exception_index == EXCP_SEMIHOST) {
-        handle_semihosting(cs);
+        tcg_handle_semihosting(cs);
         return;
     }
 #endif
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
 #include "qapi/qapi-commands-machine-target.h"
 #include "qapi/error.h"
 #include "qemu/guest-random.h"
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
                       env->exception.syndrome);
     }
 
-    if (arm_is_psci_call(cpu, cs->exception_index)) {
+    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
         arm_handle_psci_call(cpu);
         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
         return;
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     unsigned int cur_el = arm_current_el(env);
     int rt;
 
-    /*
-     * Note that new_el can never be 0.  If cur_el is 0, then
-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-     */
-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    if (tcg_enabled()) {
+        /*
+         * Note that new_el can never be 0.  If cur_el is 0, then
+         * el0_a64 is is_a64(), else el0_a64 is ignored.
+         */
+        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    }
 
     if (cur_el < new_el) {
         /*
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/machine.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
+    /*
+     * Misaligned thumb pc is architecturally impossible. Fail the
+     * incoming migration. For TCG it would trigger the assert in
+     * thumb_tr_translate_insn().
+     */
+    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+        return -1;
+    }
+
     hw_breakpoint_update_all(cpu);
     hw_watchpoint_update_all(cpu);
 
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
-    /*
-     * Misaligned thumb pc is architecturally impossible.
-     * We have an assert in thumb_tr_translate_insn to verify this.
-     * Fail an incoming migrate to avoid this assert.
-     */
-    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-        return -1;
-    }
-
     if (!kvm_enabled()) {
         pmu_op_finish(&cpu->env);
     }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.

Code moved verbatim.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h    | 91 -----------------------------------------
 2 files changed, 98 insertions(+), 91 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SME                   = 1 << 19,
 };
 
+/*
+ * Interface for defining coprocessor registers.
+ * Registers are defined in tables of arm_cp_reginfo structs
+ * which are passed to define_arm_cp_regs().
+ */
+
+/*
+ * When looking up a coprocessor register we look for it
+ * via an integer which encodes all of:
+ *  coprocessor number
+ *  Crn, Crm, opc1, opc2 fields
+ *  32 or 64 bit register (ie is it accessed via MRC/MCR
+ *    or via MRRC/MCRR?)
+ *  non-secure/secure bank (AArch32 only)
+ * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
+ * (In this case crn and opc2 should be zero.)
+ * For AArch64, there is no 32/64 bit size distinction;
+ * instead all registers have a 2 bit op0, 3 bit op1 and op2,
+ * and 4 bit CRn and CRm. The encoding patterns are chosen
+ * to be easy to convert to and from the KVM encodings, and also
+ * so that the hashtable can contain both AArch32 and AArch64
+ * registers (to allow for interprocessing where we might run
+ * 32 bit code on a 64 bit core).
+ */
+/*
+ * This bit is private to our hashtable cpreg; in KVM register
+ * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
+ * in the upper bits of the 64 bit ID.
+ */
+#define CP_REG_AA64_SHIFT 28
+#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
+
+/*
+ * To enable banking of coprocessor registers depending on ns-bit we
+ * add a bit to distinguish between secure and non-secure cpregs in the
+ * hashtable.
+ */
+#define CP_REG_NS_SHIFT 29
+#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+
+#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
+    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
+     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
+
+#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
+    (CP_REG_AA64_MASK |                                 \
+     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
+     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
+     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
+     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
+     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
+     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+/*
+ * Convert a full 64 bit KVM register ID to the truncated 32 bit
+ * version used as a key for the coprocessor register hashtable
+ */
+static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
+{
+    uint32_t cpregid = kvmid;
+    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
+        cpregid |= CP_REG_AA64_MASK;
+    } else {
+        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
+            cpregid |= (1 << 15);
+        }
+
+        /*
+         * KVM is always non-secure so add the NS flag on AArch32 register
+         * entries.
+         */
+         cpregid |= 1 << CP_REG_NS_SHIFT;
+    }
+    return cpregid;
+}
+
+/*
+ * Convert a truncated 32 bit hashtable key into the full
+ * 64 bit KVM register ID.
+ */
+static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
+{
+    uint64_t kvmid;
+
+    if (cpregid & CP_REG_AA64_MASK) {
+        kvmid = cpregid & ~CP_REG_AA64_MASK;
+        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
+    } else {
+        kvmid = cpregid & ~(1 << 15);
+        if (cpregid & (1 << 15)) {
+            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
+        } else {
+            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
+        }
+    }
+    return kvmid;
+}
+
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
  * the AArch32 and AArch64 execution states this register is visible in.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface for defining coprocessor registers.
- * Registers are defined in tables of arm_cp_reginfo structs
- * which are passed to define_arm_cp_regs().
- */
-
-/* When looking up a coprocessor register we look for it
- * via an integer which encodes all of:
- *  coprocessor number
- *  Crn, Crm, opc1, opc2 fields
- *  32 or 64 bit register (ie is it accessed via MRC/MCR
- *    or via MRRC/MCRR?)
- *  non-secure/secure bank (AArch32 only)
- * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
- * (In this case crn and opc2 should be zero.)
- * For AArch64, there is no 32/64 bit size distinction;
- * instead all registers have a 2 bit op0, 3 bit op1 and op2,
- * and 4 bit CRn and CRm. The encoding patterns are chosen
- * to be easy to convert to and from the KVM encodings, and also
- * so that the hashtable can contain both AArch32 and AArch64
- * registers (to allow for interprocessing where we might run
- * 32 bit code on a 64 bit core).
- */
-/* This bit is private to our hashtable cpreg; in KVM register
- * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
- * in the upper bits of the 64 bit ID.
- */
-#define CP_REG_AA64_SHIFT 28
-#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
-
-/* To enable banking of coprocessor registers depending on ns-bit we
- * add a bit to distinguish between secure and non-secure cpregs in the
- * hashtable.
- */
-#define CP_REG_NS_SHIFT 29
-#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
-
-#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
-    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
-     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
-
-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
-    (CP_REG_AA64_MASK |                                 \
-     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
-     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
-     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
-     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
-     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
-     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
-
-/* Convert a full 64 bit KVM register ID to the truncated 32 bit
- * version used as a key for the coprocessor register hashtable
- */
-static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
-{
-    uint32_t cpregid = kvmid;
-    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
-        cpregid |= CP_REG_AA64_MASK;
-    } else {
-        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
-            cpregid |= (1 << 15);
-        }
-
-        /* KVM is always non-secure so add the NS flag on AArch32 register
-         * entries.
-         */
-         cpregid |= 1 << CP_REG_NS_SHIFT;
-    }
-    return cpregid;
-}
-
-/* Convert a truncated 32 bit hashtable key into the full
- * 64 bit KVM register ID.
- */
-static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
-{
-    uint64_t kvmid;
-
-    if (cpregid & CP_REG_AA64_MASK) {
-        kvmid = cpregid & ~CP_REG_AA64_MASK;
-        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
-    } else {
-        kvmid = cpregid & ~(1 << 15);
-        if (cpregid & (1 << 15)) {
-            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
-        } else {
-            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
-        }
-    }
-    return kvmid;
-}
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.

We can now write tests without explicit calls to require_accelerator,
just the tag is enough.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/avocado_qemu/__init__.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/avocado_qemu/__init__.py
+++ b/tests/avocado/avocado_qemu/__init__.py
@@ -XXX,XX +XXX,XX @@ def setUp(self):
 
         super().setUp('qemu-system-')
 
+        accel_required = self._get_unique_tag_val('accel')
+        if accel_required:
+            self.require_accelerator(accel_required)
+
         self.machine = self.params.get('machine',
                                        default=self._get_unique_tag_val('machine'))
 
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

This allows the test to be skipped when TCG is not present in the QEMU
binary.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux_console.py | 1 +
 tests/avocado/reverse_debugging.py  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
 
     def test_aarch64_raspi3_atf(self):
         """
+        :avocado: tags=accel:tcg
         :avocado: tags=arch:aarch64
         :avocado: tags=machine:raspi3b
         :avocado: tags=cpu:cortex-a53
diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/reverse_debugging.py
+++ b/tests/avocado/reverse_debugging.py
@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
         vm.shutdown()
 
 class ReverseDebugging_X86_64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 0x10
     REG_CS = 0x12
     def get_pc(self, g):
@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
         self.reverse_debugging()
 
 class ReverseDebugging_AArch64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 32
 
     # unidentified gitlab timeout problem
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.

Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->minimum_page_bits = 12;
     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+#ifdef CONFIG_TCG
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+#else
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
+#endif
     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
     mc->kvm_type = virt_kvm_type;
     assert(!mc->get_hotplug_handler);
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
 #define SVE_MAX_VQ 16
 
 #define MACHINE     "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
                     "  'arguments': { 'type': 'full', "
 #define QUERY_TAIL  "}}"
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
 {
     g_test_init(&argc, &argv, NULL);
 
-    qtest_add_data_func("/arm/query-cpu-model-expansion",
-                        NULL, test_query_cpu_model_expansion);
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/query-cpu-model-expansion",
+                            NULL, test_query_cpu_model_expansion);
+    }
+
+    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
+        goto out;
+    }
 
     /*
      * For now we only run KVM specific tests with AArch64 QEMU in
      * order avoid attempting to run an AArch32 QEMU with KVM on
      * AArch64 hosts. That won't work and isn't easy to detect.
      */
-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
+    if (qtest_has_accel("kvm")) {
         /*
          * This tests target the 'host' CPU type, so register it only if
          * KVM is available.
          */
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                             NULL, test_query_cpu_model_expansion_kvm);
-    }
 
-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
-                            NULL, sve_tests_sve_max_vq_8);
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
-                            NULL, sve_tests_sve_off);
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
                             NULL, sve_tests_sve_off_kvm);
     }
 
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+                            NULL, sve_tests_sve_max_vq_8);
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off);
+    }
+
+out:
     return g_test_run();
 }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

These tests set -accel tcg, so restrict them to when TCG is present.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
 qtests_aarch64 = \
   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
+  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
+    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
   ['arm-cpu-features',
-- 
2.34.1