1
Almost nothing in here is arm-related, but the target-arm
1
The following changes since commit 3db29dcac23da85486704ef9e7a8e7217f7829cd:
2
queue was convenient for these last minute bits and pieces
3
for 5.0...
4
2
5
thanks
3
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-01-12 13:51:36 +0000)
6
-- PMM
7
8
The following changes since commit 14e5526b51910efd62cd31cd95b49baca975c83f:
9
10
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-04-13 15:42:51 +0100)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200414
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230113
15
8
16
for you to fetch changes up to 84f82ddcbb4ac4ed04c8675e85155329f23184f0:
9
for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31:
17
10
18
Deprecate KVM support for AArch32 (2020-04-14 17:20:22 +0100)
11
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled (2023-01-13 13:19:36 +0000)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
patch queue:
14
target-arm queue:
22
* Fix some problems that trip up Coverity's scanner
15
hw/arm/stm32f405: correctly describe the memory layout
23
* run-coverity-scan: New script automating the scan-and-upload process
16
hw/arm: Add Olimex H405 board
24
* docs: Improve our gdbstub documentation
17
cubieboard: Support booting from an SD card image with u-boot on it
25
* configure: Honour --disable-werror for Sphinx
18
target/arm: Fix sve_probe_page
26
* docs: Fix errors produced when building with Sphinx 3.0
19
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
27
* docs: Require Sphinx 1.6 or better
20
various code cleanups
28
* Add deprecation notice for KVM support on AArch32 hosts
29
21
30
----------------------------------------------------------------
22
----------------------------------------------------------------
31
Peter Maydell (12):
23
Evgeny Iakovlev (1):
32
osdep.h: Drop no-longer-needed Coverity workarounds
24
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
33
thread.h: Fix Coverity version of qemu_cond_timedwait()
34
thread.h: Remove trailing semicolons from Coverity qemu_mutex_lock() etc
35
linux-user/flatload.c: Use "" for include of QEMU header target_flat.h
36
scripts/run-coverity-scan: Script to run Coverity Scan build
37
scripts/coverity-scan: Add Docker support
38
docs: Improve our gdbstub documentation
39
configure: Honour --disable-werror for Sphinx
40
scripts/kernel-doc: Add missing close-paren in c:function directives
41
kernel-doc: Use c:struct for Sphinx 3.0 and later
42
docs: Require Sphinx 1.6 or better
43
Deprecate KVM support for AArch32
44
25
45
configure | 9 +-
26
Felipe Balbi (2):
46
Makefile | 2 +-
27
hw/arm/stm32f405: correctly describe the memory layout
47
include/qemu/osdep.h | 14 -
28
hw/arm: Add Olimex H405
48
include/qemu/thread.h | 12 +-
49
linux-user/flatload.c | 2 +-
50
MAINTAINERS | 5 +
51
docs/conf.py | 6 +-
52
docs/sphinx/kerneldoc.py | 1 +
53
docs/system/deprecated.rst | 8 +
54
docs/system/gdb.rst | 22 +-
55
qemu-options.hx | 24 +-
56
scripts/coverity-scan/coverity-scan.docker | 131 ++++++++++
57
scripts/coverity-scan/run-coverity-scan | 401 +++++++++++++++++++++++++++++
58
scripts/kernel-doc | 18 +-
59
14 files changed, 615 insertions(+), 40 deletions(-)
60
create mode 100644 scripts/coverity-scan/coverity-scan.docker
61
create mode 100755 scripts/coverity-scan/run-coverity-scan
62
29
30
Philippe Mathieu-Daudé (27):
31
hw/arm/pxa2xx: Simplify pxa255_init()
32
hw/arm/pxa2xx: Simplify pxa270_init()
33
hw/arm/collie: Use the IEC binary prefix definitions
34
hw/arm/collie: Simplify flash creation using for() loop
35
hw/arm/gumstix: Improve documentation
36
hw/arm/gumstix: Use the IEC binary prefix definitions
37
hw/arm/mainstone: Use the IEC binary prefix definitions
38
hw/arm/musicpal: Use the IEC binary prefix definitions
39
hw/arm/omap_sx1: Remove unused 'total_ram' definitions
40
hw/arm/omap_sx1: Use the IEC binary prefix definitions
41
hw/arm/z2: Use the IEC binary prefix definitions
42
hw/arm/vexpress: Remove dead code in vexpress_common_init()
43
hw/arm: Remove unreachable code calling pflash_cfi01_register()
44
hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
45
hw/gpio/omap_gpio: Add local variable to avoid embedded cast
46
hw/arm/omap: Drop useless casts from void * to pointer
47
hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
48
hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
49
hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
50
hw/arm/stellaris: Drop useless casts from void * to pointer
51
hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
52
hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
53
hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
54
hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
55
hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
56
hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
57
hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'
58
59
Richard Henderson (1):
60
target/arm: Fix sve_probe_page
61
62
Strahinja Jankovic (7):
63
hw/misc: Allwinner-A10 Clock Controller Module Emulation
64
hw/misc: Allwinner A10 DRAM Controller Emulation
65
{hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation
66
hw/misc: AXP209 PMU Emulation
67
hw/arm: Add AXP209 to Cubieboard
68
hw/arm: Allwinner A10 enable SPL load from MMC
69
tests/avocado: Add SD boot test to Cubieboard
70
71
docs/system/arm/cubieboard.rst | 1 +
72
docs/system/arm/orangepi.rst | 1 +
73
docs/system/arm/stm32.rst | 1 +
74
configs/devices/arm-softmmu/default.mak | 1 +
75
include/hw/adc/npcm7xx_adc.h | 7 +-
76
include/hw/arm/allwinner-a10.h | 27 ++
77
include/hw/arm/allwinner-h3.h | 3 +
78
include/hw/arm/npcm7xx.h | 18 +-
79
include/hw/arm/omap.h | 24 +-
80
include/hw/arm/pxa.h | 11 +-
81
include/hw/arm/stm32f405_soc.h | 5 +-
82
include/hw/i2c/allwinner-i2c.h | 55 ++++
83
include/hw/i2c/npcm7xx_smbus.h | 7 +-
84
include/hw/misc/allwinner-a10-ccm.h | 67 +++++
85
include/hw/misc/allwinner-a10-dramc.h | 68 +++++
86
include/hw/misc/npcm7xx_clk.h | 2 +-
87
include/hw/misc/npcm7xx_gcr.h | 6 +-
88
include/hw/misc/npcm7xx_mft.h | 7 +-
89
include/hw/misc/npcm7xx_pwm.h | 3 +-
90
include/hw/misc/npcm7xx_rng.h | 6 +-
91
include/hw/net/npcm7xx_emc.h | 5 +-
92
include/hw/sd/npcm7xx_sdhci.h | 4 +-
93
hw/arm/allwinner-a10.c | 40 +++
94
hw/arm/allwinner-h3.c | 11 +-
95
hw/arm/bcm2836.c | 9 +-
96
hw/arm/collie.c | 25 +-
97
hw/arm/cubieboard.c | 11 +
98
hw/arm/gumstix.c | 45 ++--
99
hw/arm/mainstone.c | 37 ++-
100
hw/arm/musicpal.c | 9 +-
101
hw/arm/olimex-stm32-h405.c | 69 +++++
102
hw/arm/omap1.c | 115 ++++----
103
hw/arm/omap2.c | 40 ++-
104
hw/arm/omap_sx1.c | 53 ++--
105
hw/arm/palm.c | 2 +-
106
hw/arm/pxa2xx.c | 8 +-
107
hw/arm/spitz.c | 6 +-
108
hw/arm/stellaris.c | 73 +++--
109
hw/arm/stm32f405_soc.c | 8 +
110
hw/arm/tosa.c | 2 +-
111
hw/arm/versatilepb.c | 6 +-
112
hw/arm/vexpress.c | 10 +-
113
hw/arm/z2.c | 16 +-
114
hw/char/omap_uart.c | 7 +-
115
hw/display/omap_dss.c | 15 +-
116
hw/display/omap_lcdc.c | 9 +-
117
hw/dma/omap_dma.c | 15 +-
118
hw/gpio/omap_gpio.c | 48 ++--
119
hw/i2c/allwinner-i2c.c | 459 ++++++++++++++++++++++++++++++++
120
hw/intc/omap_intc.c | 38 +--
121
hw/intc/xilinx_intc.c | 28 +-
122
hw/misc/allwinner-a10-ccm.c | 224 ++++++++++++++++
123
hw/misc/allwinner-a10-dramc.c | 179 +++++++++++++
124
hw/misc/axp209.c | 238 +++++++++++++++++
125
hw/misc/omap_gpmc.c | 12 +-
126
hw/misc/omap_l4.c | 7 +-
127
hw/misc/omap_sdrc.c | 7 +-
128
hw/misc/omap_tap.c | 5 +-
129
hw/misc/sbsa_ec.c | 12 +-
130
hw/sd/omap_mmc.c | 9 +-
131
hw/ssi/omap_spi.c | 7 +-
132
hw/timer/omap_gptimer.c | 22 +-
133
hw/timer/omap_synctimer.c | 4 +-
134
hw/timer/xilinx_timer.c | 27 +-
135
target/arm/helper.c | 3 +
136
target/arm/sve_helper.c | 14 +-
137
MAINTAINERS | 8 +
138
hw/arm/Kconfig | 9 +
139
hw/arm/meson.build | 1 +
140
hw/i2c/Kconfig | 4 +
141
hw/i2c/meson.build | 1 +
142
hw/i2c/trace-events | 5 +
143
hw/misc/Kconfig | 10 +
144
hw/misc/meson.build | 3 +
145
hw/misc/trace-events | 5 +
146
tests/avocado/boot_linux_console.py | 47 ++++
147
76 files changed, 1951 insertions(+), 455 deletions(-)
148
create mode 100644 include/hw/i2c/allwinner-i2c.h
149
create mode 100644 include/hw/misc/allwinner-a10-ccm.h
150
create mode 100644 include/hw/misc/allwinner-a10-dramc.h
151
create mode 100644 hw/arm/olimex-stm32-h405.c
152
create mode 100644 hw/i2c/allwinner-i2c.c
153
create mode 100644 hw/misc/allwinner-a10-ccm.c
154
create mode 100644 hw/misc/allwinner-a10-dramc.c
155
create mode 100644 hw/misc/axp209.c
156
diff view generated by jsdifflib
New patch
1
From: Felipe Balbi <balbi@kernel.org>
1
2
3
STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
4
Memory) at a different base address. Correctly describe the memory
5
layout to give existing FW images a chance to run unmodified.
6
7
Reviewed-by: Alistair Francis <alistair@alistair23.me>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Felipe Balbi <balbi@kernel.org>
10
Message-id: 20221230145733.200496-2-balbi@kernel.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/stm32f405_soc.h | 5 ++++-
14
hw/arm/stm32f405_soc.c | 8 ++++++++
15
2 files changed, 12 insertions(+), 1 deletion(-)
16
17
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/stm32f405_soc.h
20
+++ b/include/hw/arm/stm32f405_soc.h
21
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
22
#define FLASH_BASE_ADDRESS 0x08000000
23
#define FLASH_SIZE (1024 * 1024)
24
#define SRAM_BASE_ADDRESS 0x20000000
25
-#define SRAM_SIZE (192 * 1024)
26
+#define SRAM_SIZE (128 * 1024)
27
+#define CCM_BASE_ADDRESS 0x10000000
28
+#define CCM_SIZE (64 * 1024)
29
30
struct STM32F405State {
31
/*< private >*/
32
@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
33
STM32F2XXADCState adc[STM_NUM_ADCS];
34
STM32F2XXSPIState spi[STM_NUM_SPIS];
35
36
+ MemoryRegion ccm;
37
MemoryRegion sram;
38
MemoryRegion flash;
39
MemoryRegion flash_alias;
40
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/stm32f405_soc.c
43
+++ b/hw/arm/stm32f405_soc.c
44
@@ -XXX,XX +XXX,XX @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
45
}
46
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
47
48
+ memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
49
+ &err);
50
+ if (err != NULL) {
51
+ error_propagate(errp, err);
52
+ return;
53
+ }
54
+ memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
55
+
56
armv7m = DEVICE(&s->armv7m);
57
qdev_prop_set_uint32(armv7m, "num-irq", 96);
58
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
59
--
60
2.34.1
61
62
diff view generated by jsdifflib
1
Add a new script to automate the process of running the Coverity
1
From: Felipe Balbi <balbi@kernel.org>
2
Scan build tools and uploading the resulting tarball to the
3
website.
4
2
5
This is intended eventually to be driven from Travis,
3
Olimex makes a series of low-cost STM32 boards. This commit introduces
6
but it can be run locally, if you are a maintainer of the
4
the minimum setup to support SMT32-H405. See [1] for details
7
QEMU project on the Coverity Scan website and have the secret
8
upload token.
9
5
10
The script must be run on a Fedora 30 system. Support for using a
6
[1] https://www.olimex.com/Products/ARM/ST/STM32-H405/
11
Docker container is added in a following commit.
12
7
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Felipe Balbi <balbi@kernel.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20221230145733.200496-3-balbi@kernel.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20200319193323.2038-6-peter.maydell@linaro.org
16
---
13
---
17
MAINTAINERS | 5 +
14
docs/system/arm/stm32.rst | 1 +
18
scripts/coverity-scan/run-coverity-scan | 311 ++++++++++++++++++++++++
15
configs/devices/arm-softmmu/default.mak | 1 +
19
2 files changed, 316 insertions(+)
16
hw/arm/olimex-stm32-h405.c | 69 +++++++++++++++++++++++++
20
create mode 100755 scripts/coverity-scan/run-coverity-scan
17
MAINTAINERS | 6 +++
18
hw/arm/Kconfig | 4 ++
19
hw/arm/meson.build | 1 +
20
6 files changed, 82 insertions(+)
21
create mode 100644 hw/arm/olimex-stm32-h405.c
21
22
23
diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
24
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/system/arm/stm32.rst
26
+++ b/docs/system/arm/stm32.rst
27
@@ -XXX,XX +XXX,XX @@ The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
28
compatible with STM32F2 series. The following machines are based on this chip :
29
30
- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller
31
+- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller
32
33
There are many other STM32 series that are currently not supported by QEMU.
34
35
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
36
index XXXXXXX..XXXXXXX 100644
37
--- a/configs/devices/arm-softmmu/default.mak
38
+++ b/configs/devices/arm-softmmu/default.mak
39
@@ -XXX,XX +XXX,XX @@ CONFIG_COLLIE=y
40
CONFIG_ASPEED_SOC=y
41
CONFIG_NETDUINO2=y
42
CONFIG_NETDUINOPLUS2=y
43
+CONFIG_OLIMEX_STM32_H405=y
44
CONFIG_MPS2=y
45
CONFIG_RASPI=y
46
CONFIG_DIGIC=y
47
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
48
new file mode 100644
49
index XXXXXXX..XXXXXXX
50
--- /dev/null
51
+++ b/hw/arm/olimex-stm32-h405.c
52
@@ -XXX,XX +XXX,XX @@
53
+/*
54
+ * ST STM32VLDISCOVERY machine
55
+ * Olimex STM32-H405 machine
56
+ *
57
+ * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
58
+ *
59
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
60
+ * of this software and associated documentation files (the "Software"), to deal
61
+ * in the Software without restriction, including without limitation the rights
62
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
63
+ * copies of the Software, and to permit persons to whom the Software is
64
+ * furnished to do so, subject to the following conditions:
65
+ *
66
+ * The above copyright notice and this permission notice shall be included in
67
+ * all copies or substantial portions of the Software.
68
+ *
69
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
70
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
71
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
72
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
73
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
74
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
75
+ * THE SOFTWARE.
76
+ */
77
+
78
+#include "qemu/osdep.h"
79
+#include "qapi/error.h"
80
+#include "hw/boards.h"
81
+#include "hw/qdev-properties.h"
82
+#include "hw/qdev-clock.h"
83
+#include "qemu/error-report.h"
84
+#include "hw/arm/stm32f405_soc.h"
85
+#include "hw/arm/boot.h"
86
+
87
+/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
88
+
89
+/* Main SYSCLK frequency in Hz (168MHz) */
90
+#define SYSCLK_FRQ 168000000ULL
91
+
92
+static void olimex_stm32_h405_init(MachineState *machine)
93
+{
94
+ DeviceState *dev;
95
+ Clock *sysclk;
96
+
97
+ /* This clock doesn't need migration because it is fixed-frequency */
98
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
99
+ clock_set_hz(sysclk, SYSCLK_FRQ);
100
+
101
+ dev = qdev_new(TYPE_STM32F405_SOC);
102
+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
103
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
104
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
105
+
106
+ armv7m_load_kernel(ARM_CPU(first_cpu),
107
+ machine->kernel_filename,
108
+ 0, FLASH_SIZE);
109
+}
110
+
111
+static void olimex_stm32_h405_machine_init(MachineClass *mc)
112
+{
113
+ mc->desc = "Olimex STM32-H405 (Cortex-M4)";
114
+ mc->init = olimex_stm32_h405_init;
115
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
116
+
117
+ /* SRAM pre-allocated as part of the SoC instantiation */
118
+ mc->default_ram_size = 0;
119
+}
120
+
121
+DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
22
diff --git a/MAINTAINERS b/MAINTAINERS
122
diff --git a/MAINTAINERS b/MAINTAINERS
23
index XXXXXXX..XXXXXXX 100644
123
index XXXXXXX..XXXXXXX 100644
24
--- a/MAINTAINERS
124
--- a/MAINTAINERS
25
+++ b/MAINTAINERS
125
+++ b/MAINTAINERS
26
@@ -XXX,XX +XXX,XX @@ M: Markus Armbruster <armbru@redhat.com>
126
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
27
S: Supported
127
S: Maintained
28
F: scripts/coverity-model.c
128
F: hw/arm/netduinoplus2.c
29
129
30
+Coverity Scan integration
130
+Olimex STM32 H405
31
+M: Peter Maydell <peter.maydell@linaro.org>
131
+M: Felipe Balbi <balbi@kernel.org>
132
+L: qemu-arm@nongnu.org
32
+S: Maintained
133
+S: Maintained
33
+F: scripts/coverity-scan/
134
+F: hw/arm/olimex-stm32-h405.c
34
+
135
+
35
Device Tree
136
SmartFusion2
36
M: Alistair Francis <alistair.francis@wdc.com>
137
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
37
R: David Gibson <david@gibson.dropbear.id.au>
138
M: Peter Maydell <peter.maydell@linaro.org>
38
diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan
139
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
39
new file mode 100755
140
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX
141
--- a/hw/arm/Kconfig
41
--- /dev/null
142
+++ b/hw/arm/Kconfig
42
+++ b/scripts/coverity-scan/run-coverity-scan
143
@@ -XXX,XX +XXX,XX @@ config NETDUINOPLUS2
43
@@ -XXX,XX +XXX,XX @@
144
bool
44
+#!/bin/sh -e
145
select STM32F405_SOC
146
147
+config OLIMEX_STM32_H405
148
+ bool
149
+ select STM32F405_SOC
45
+
150
+
46
+# Upload a created tarball to Coverity Scan, as per
151
config NSERIES
47
+# https://scan.coverity.com/projects/qemu/builds/new
152
bool
48
+
153
select OMAP
49
+# This work is licensed under the terms of the GNU GPL version 2,
154
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
50
+# or (at your option) any later version.
155
index XXXXXXX..XXXXXXX 100644
51
+# See the COPYING file in the top-level directory.
156
--- a/hw/arm/meson.build
52
+#
157
+++ b/hw/arm/meson.build
53
+# Copyright (c) 2017-2020 Linaro Limited
158
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
54
+# Written by Peter Maydell
159
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
55
+
160
arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
56
+# Note that this script will automatically download and
161
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
57
+# run the (closed-source) coverity build tools, so don't
162
+arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
58
+# use it if you don't trust them!
163
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
59
+
164
arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
60
+# This script assumes that you're running it from a QEMU source
165
arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
61
+# tree, and that tree is a fresh clean one, because we do an in-tree
62
+# build. (This is necessary so that the filenames that the Coverity
63
+# Scan server sees are relative paths that match up with the component
64
+# regular expressions it uses; an out-of-tree build won't work for this.)
65
+# The host machine should have as many of QEMU's dependencies
66
+# installed as possible, for maximum coverity coverage.
67
+
68
+# To do an upload you need to be a maintainer in the Coverity online
69
+# service, and you will need to know the "Coverity token", which is a
70
+# secret 8 digit hex string. You can find that from the web UI in the
71
+# project settings, if you have maintainer access there.
72
+
73
+# Command line options:
74
+# --dry-run : run the tools, but don't actually do the upload
75
+# --update-tools-only : update the cached copy of the tools, but don't run them
76
+# --tokenfile : file to read Coverity token from
77
+# --version ver : specify version being analyzed (default: ask git)
78
+# --description desc : specify description of this version (default: ask git)
79
+# --srcdir : QEMU source tree to analyze (default: current working dir)
80
+# --results-tarball : path to copy the results tarball to (default: don't
81
+# copy it anywhere, just upload it)
82
+#
83
+# User-specifiable environment variables:
84
+# COVERITY_TOKEN -- Coverity token
85
+# COVERITY_EMAIL -- the email address to use for uploads (default:
86
+# looks at your git user.email config)
87
+# COVERITY_BUILD_CMD -- make command (default: 'make -jN' where N is
88
+# number of CPUs as determined by 'nproc')
89
+# COVERITY_TOOL_BASE -- set to directory to put coverity tools
90
+# (default: /tmp/coverity-tools)
91
+#
92
+# You must specify the token, either by environment variable or by
93
+# putting it in a file and using --tokenfile. Everything else has
94
+# a reasonable default if this is run from a git tree.
95
+
96
+check_upload_permissions() {
97
+ # Check whether we can do an upload to the server; will exit the script
98
+ # with status 1 if the check failed (usually a bad token);
99
+ # will exit the script with status 0 if the check indicated that we
100
+ # can't upload yet (ie we are at quota)
101
+ # Assumes that PROJTOKEN, PROJNAME and DRYRUN have been initialized.
102
+
103
+ echo "Checking upload permissions..."
104
+
105
+ if ! up_perm="$(wget https://scan.coverity.com/api/upload_permitted --post-data "token=$PROJTOKEN&project=$PROJNAME" -q -O -)"; then
106
+ echo "Coverity Scan API access denied: bad token?"
107
+ exit 1
108
+ fi
109
+
110
+ # Really up_perm is a JSON response with either
111
+ # {upload_permitted:true} or {next_upload_permitted_at:<date>}
112
+ # We do some hacky string parsing instead of properly parsing it.
113
+ case "$up_perm" in
114
+ *upload_permitted*true*)
115
+ echo "Coverity Scan: upload permitted"
116
+ ;;
117
+ *next_upload_permitted_at*)
118
+ if [ "$DRYRUN" = yes ]; then
119
+ echo "Coverity Scan: upload quota reached, continuing dry run"
120
+ else
121
+ echo "Coverity Scan: upload quota reached; stopping here"
122
+ # Exit success as this isn't a build error.
123
+ exit 0
124
+ fi
125
+ ;;
126
+ *)
127
+ echo "Coverity Scan upload check: unexpected result $up_perm"
128
+ exit 1
129
+ ;;
130
+ esac
131
+}
132
+
133
+
134
+update_coverity_tools () {
135
+ # Check for whether we need to download the Coverity tools
136
+ # (either because we don't have a copy, or because it's out of date)
137
+ # Assumes that COVERITY_TOOL_BASE, PROJTOKEN and PROJNAME are set.
138
+
139
+ mkdir -p "$COVERITY_TOOL_BASE"
140
+ cd "$COVERITY_TOOL_BASE"
141
+
142
+ echo "Checking for new version of coverity build tools..."
143
+ wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME&md5=1" -O coverity_tool.md5.new
144
+
145
+ if ! cmp -s coverity_tool.md5 coverity_tool.md5.new; then
146
+ # out of date md5 or no md5: download new build tool
147
+ # blow away the old build tool
148
+ echo "Downloading coverity build tools..."
149
+ rm -rf coverity_tool coverity_tool.tgz
150
+ wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME" -O coverity_tool.tgz
151
+ if ! (cat coverity_tool.md5.new; echo " coverity_tool.tgz") | md5sum -c --status; then
152
+ echo "Downloaded tarball didn't match md5sum!"
153
+ exit 1
154
+ fi
155
+ # extract the new one, keeping it corralled in a 'coverity_tool' directory
156
+ echo "Unpacking coverity build tools..."
157
+ mkdir -p coverity_tool
158
+ cd coverity_tool
159
+ tar xf ../coverity_tool.tgz
160
+ cd ..
161
+ mv coverity_tool.md5.new coverity_tool.md5
162
+ fi
163
+
164
+ rm -f coverity_tool.md5.new
165
+}
166
+
167
+
168
+# Check user-provided environment variables and arguments
169
+DRYRUN=no
170
+UPDATE_ONLY=no
171
+
172
+while [ "$#" -ge 1 ]; do
173
+ case "$1" in
174
+ --dry-run)
175
+ shift
176
+ DRYRUN=yes
177
+ ;;
178
+ --update-tools-only)
179
+ shift
180
+ UPDATE_ONLY=yes
181
+ ;;
182
+ --version)
183
+ shift
184
+ if [ $# -eq 0 ]; then
185
+ echo "--version needs an argument"
186
+ exit 1
187
+ fi
188
+ VERSION="$1"
189
+ shift
190
+ ;;
191
+ --description)
192
+ shift
193
+ if [ $# -eq 0 ]; then
194
+ echo "--description needs an argument"
195
+ exit 1
196
+ fi
197
+ DESCRIPTION="$1"
198
+ shift
199
+ ;;
200
+ --tokenfile)
201
+ shift
202
+ if [ $# -eq 0 ]; then
203
+ echo "--tokenfile needs an argument"
204
+ exit 1
205
+ fi
206
+ COVERITY_TOKEN="$(cat "$1")"
207
+ shift
208
+ ;;
209
+ --srcdir)
210
+ shift
211
+ if [ $# -eq 0 ]; then
212
+ echo "--srcdir needs an argument"
213
+ exit 1
214
+ fi
215
+ SRCDIR="$1"
216
+ shift
217
+ ;;
218
+ --results-tarball)
219
+ shift
220
+ if [ $# -eq 0 ]; then
221
+ echo "--results-tarball needs an argument"
222
+ exit 1
223
+ fi
224
+ RESULTSTARBALL="$1"
225
+ shift
226
+ ;;
227
+ *)
228
+ echo "Unexpected argument '$1'"
229
+ exit 1
230
+ ;;
231
+ esac
232
+done
233
+
234
+if [ -z "$COVERITY_TOKEN" ]; then
235
+ echo "COVERITY_TOKEN environment variable not set"
236
+ exit 1
237
+fi
238
+
239
+if [ -z "$COVERITY_BUILD_CMD" ]; then
240
+ NPROC=$(nproc)
241
+ COVERITY_BUILD_CMD="make -j$NPROC"
242
+ echo "COVERITY_BUILD_CMD: using default '$COVERITY_BUILD_CMD'"
243
+fi
244
+
245
+if [ -z "$COVERITY_TOOL_BASE" ]; then
246
+ echo "COVERITY_TOOL_BASE: using default /tmp/coverity-tools"
247
+ COVERITY_TOOL_BASE=/tmp/coverity-tools
248
+fi
249
+
250
+if [ -z "$SRCDIR" ]; then
251
+ SRCDIR="$PWD"
252
+fi
253
+
254
+PROJTOKEN="$COVERITY_TOKEN"
255
+PROJNAME=QEMU
256
+TARBALL=cov-int.tar.xz
257
+
258
+
259
+if [ "$UPDATE_ONLY" = yes ]; then
260
+ # Just do the tools update; we don't need to check whether
261
+ # we are in a source tree or have upload rights for this,
262
+ # so do it before some of the command line and source tree checks.
263
+ update_coverity_tools
264
+ exit 0
265
+fi
266
+
267
+cd "$SRCDIR"
268
+
269
+echo "Checking this is a QEMU source tree..."
270
+if ! [ -e "$SRCDIR/VERSION" ]; then
271
+ echo "Not in a QEMU source tree?"
272
+ exit 1
273
+fi
274
+
275
+# Fill in defaults used by the non-update-only process
276
+if [ -z "$VERSION" ]; then
277
+ VERSION="$(git describe --always HEAD)"
278
+fi
279
+
280
+if [ -z "$DESCRIPTION" ]; then
281
+ DESCRIPTION="$(git rev-parse HEAD)"
282
+fi
283
+
284
+if [ -z "$COVERITY_EMAIL" ]; then
285
+ COVERITY_EMAIL="$(git config user.email)"
286
+fi
287
+
288
+check_upload_permissions
289
+
290
+update_coverity_tools
291
+
292
+TOOLBIN="$(cd "$COVERITY_TOOL_BASE" && echo $PWD/coverity_tool/cov-analysis-*/bin)"
293
+
294
+if ! test -x "$TOOLBIN/cov-build"; then
295
+ echo "Couldn't find cov-build in the coverity build-tool directory??"
296
+ exit 1
297
+fi
298
+
299
+export PATH="$TOOLBIN:$PATH"
300
+
301
+cd "$SRCDIR"
302
+
303
+echo "Doing make distclean..."
304
+make distclean
305
+
306
+echo "Configuring..."
307
+# We configure with a fixed set of enables here to ensure that we don't
308
+# accidentally reduce the scope of the analysis by doing the build on
309
+# the system that's missing a dependency that we need to build part of
310
+# the codebase.
311
+./configure --disable-modules --enable-sdl --enable-gtk \
312
+ --enable-opengl --enable-vte --enable-gnutls \
313
+ --enable-nettle --enable-curses --enable-curl \
314
+ --audio-drv-list=oss,alsa,sdl,pa --enable-virtfs \
315
+ --enable-vnc --enable-vnc-sasl --enable-vnc-jpeg --enable-vnc-png \
316
+ --enable-xen --enable-brlapi \
317
+ --enable-linux-aio --enable-attr \
318
+ --enable-cap-ng --enable-trace-backends=log --enable-spice --enable-rbd \
319
+ --enable-xfsctl --enable-libusb --enable-usb-redir \
320
+ --enable-libiscsi --enable-libnfs --enable-seccomp \
321
+ --enable-tpm --enable-libssh --enable-lzo --enable-snappy --enable-bzip2 \
322
+ --enable-numa --enable-rdma --enable-smartcard --enable-virglrenderer \
323
+ --enable-mpath --enable-libxml2 --enable-glusterfs \
324
+ --enable-virtfs --enable-zstd
325
+
326
+echo "Making libqemustub.a..."
327
+make libqemustub.a
328
+
329
+echo "Running cov-build..."
330
+rm -rf cov-int
331
+mkdir cov-int
332
+cov-build --dir cov-int $COVERITY_BUILD_CMD
333
+
334
+echo "Creating results tarball..."
335
+tar cvf - cov-int | xz > "$TARBALL"
336
+
337
+if [ ! -z "$RESULTSTARBALL" ]; then
338
+ echo "Copying results tarball to $RESULTSTARBALL..."
339
+ cp "$TARBALL" "$RESULTSTARBALL"
340
+fi
341
+
342
+echo "Uploading results tarball..."
343
+
344
+if [ "$DRYRUN" = yes ]; then
345
+ echo "Dry run only, not uploading $TARBALL"
346
+ exit 0
347
+fi
348
+
349
+curl --form token="$PROJTOKEN" --form email="$COVERITY_EMAIL" \
350
+ --form file=@"$TARBALL" --form version="$VERSION" \
351
+ --form description="$DESCRIPTION" \
352
+ https://scan.coverity.com/builds?project="$PROJNAME"
353
+
354
+echo "Done."
355
--
166
--
356
2.20.1
167
2.34.1
357
168
358
169
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
During SPL boot several Clock Controller Module (CCM) registers are
4
read, most important are PLL and Tuning, as well as divisor registers.
5
6
This patch adds these registers and initializes reset values from user's
7
guide.
8
9
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
10
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/arm/allwinner-a10.h | 2 +
16
include/hw/misc/allwinner-a10-ccm.h | 67 +++++++++
17
hw/arm/allwinner-a10.c | 7 +
18
hw/misc/allwinner-a10-ccm.c | 224 ++++++++++++++++++++++++++++
19
hw/arm/Kconfig | 1 +
20
hw/misc/Kconfig | 3 +
21
hw/misc/meson.build | 1 +
22
7 files changed, 305 insertions(+)
23
create mode 100644 include/hw/misc/allwinner-a10-ccm.h
24
create mode 100644 hw/misc/allwinner-a10-ccm.c
25
26
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/allwinner-a10.h
29
+++ b/include/hw/arm/allwinner-a10.h
30
@@ -XXX,XX +XXX,XX @@
31
#include "hw/usb/hcd-ohci.h"
32
#include "hw/usb/hcd-ehci.h"
33
#include "hw/rtc/allwinner-rtc.h"
34
+#include "hw/misc/allwinner-a10-ccm.h"
35
36
#include "target/arm/cpu.h"
37
#include "qom/object.h"
38
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
39
/*< public >*/
40
41
ARMCPU cpu;
42
+ AwA10ClockCtlState ccm;
43
AwA10PITState timer;
44
AwA10PICState intc;
45
AwEmacState emac;
46
diff --git a/include/hw/misc/allwinner-a10-ccm.h b/include/hw/misc/allwinner-a10-ccm.h
47
new file mode 100644
48
index XXXXXXX..XXXXXXX
49
--- /dev/null
50
+++ b/include/hw/misc/allwinner-a10-ccm.h
51
@@ -XXX,XX +XXX,XX @@
52
+/*
53
+ * Allwinner A10 Clock Control Module emulation
54
+ *
55
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
56
+ *
57
+ * This file is derived from Allwinner H3 CCU,
58
+ * by Niek Linnenbank.
59
+ *
60
+ * This program is free software: you can redistribute it and/or modify
61
+ * it under the terms of the GNU General Public License as published by
62
+ * the Free Software Foundation, either version 2 of the License, or
63
+ * (at your option) any later version.
64
+ *
65
+ * This program is distributed in the hope that it will be useful,
66
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
67
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
68
+ * GNU General Public License for more details.
69
+ *
70
+ * You should have received a copy of the GNU General Public License
71
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
72
+ */
73
+
74
+#ifndef HW_MISC_ALLWINNER_A10_CCM_H
75
+#define HW_MISC_ALLWINNER_A10_CCM_H
76
+
77
+#include "qom/object.h"
78
+#include "hw/sysbus.h"
79
+
80
+/**
81
+ * @name Constants
82
+ * @{
83
+ */
84
+
85
+/** Size of register I/O address space used by CCM device */
86
+#define AW_A10_CCM_IOSIZE (0x400)
87
+
88
+/** Total number of known registers */
89
+#define AW_A10_CCM_REGS_NUM (AW_A10_CCM_IOSIZE / sizeof(uint32_t))
90
+
91
+/** @} */
92
+
93
+/**
94
+ * @name Object model
95
+ * @{
96
+ */
97
+
98
+#define TYPE_AW_A10_CCM "allwinner-a10-ccm"
99
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10ClockCtlState, AW_A10_CCM)
100
+
101
+/** @} */
102
+
103
+/**
104
+ * Allwinner A10 CCM object instance state.
105
+ */
106
+struct AwA10ClockCtlState {
107
+ /*< private >*/
108
+ SysBusDevice parent_obj;
109
+ /*< public >*/
110
+
111
+ /** Maps I/O registers in physical memory */
112
+ MemoryRegion iomem;
113
+
114
+ /** Array of hardware registers */
115
+ uint32_t regs[AW_A10_CCM_REGS_NUM];
116
+};
117
+
118
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
119
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/hw/arm/allwinner-a10.c
122
+++ b/hw/arm/allwinner-a10.c
123
@@ -XXX,XX +XXX,XX @@
124
#include "hw/usb/hcd-ohci.h"
125
126
#define AW_A10_MMC0_BASE 0x01c0f000
127
+#define AW_A10_CCM_BASE 0x01c20000
128
#define AW_A10_PIC_REG_BASE 0x01c20400
129
#define AW_A10_PIT_REG_BASE 0x01c20c00
130
#define AW_A10_UART0_REG_BASE 0x01c28000
131
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
132
133
object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
134
135
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
136
+
137
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
138
139
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
140
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
141
memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
142
create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
143
144
+ /* Clock Control Module */
145
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
146
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
147
+
148
/* FIXME use qdev NIC properties instead of nd_table[] */
149
if (nd_table[0].used) {
150
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
151
diff --git a/hw/misc/allwinner-a10-ccm.c b/hw/misc/allwinner-a10-ccm.c
152
new file mode 100644
153
index XXXXXXX..XXXXXXX
154
--- /dev/null
155
+++ b/hw/misc/allwinner-a10-ccm.c
156
@@ -XXX,XX +XXX,XX @@
157
+/*
158
+ * Allwinner A10 Clock Control Module emulation
159
+ *
160
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
161
+ *
162
+ * This file is derived from Allwinner H3 CCU,
163
+ * by Niek Linnenbank.
164
+ *
165
+ * This program is free software: you can redistribute it and/or modify
166
+ * it under the terms of the GNU General Public License as published by
167
+ * the Free Software Foundation, either version 2 of the License, or
168
+ * (at your option) any later version.
169
+ *
170
+ * This program is distributed in the hope that it will be useful,
171
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
172
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
173
+ * GNU General Public License for more details.
174
+ *
175
+ * You should have received a copy of the GNU General Public License
176
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
177
+ */
178
+
179
+#include "qemu/osdep.h"
180
+#include "qemu/units.h"
181
+#include "hw/sysbus.h"
182
+#include "migration/vmstate.h"
183
+#include "qemu/log.h"
184
+#include "qemu/module.h"
185
+#include "hw/misc/allwinner-a10-ccm.h"
186
+
187
+/* CCM register offsets */
188
+enum {
189
+ REG_PLL1_CFG = 0x0000, /* PLL1 Control */
190
+ REG_PLL1_TUN = 0x0004, /* PLL1 Tuning */
191
+ REG_PLL2_CFG = 0x0008, /* PLL2 Control */
192
+ REG_PLL2_TUN = 0x000C, /* PLL2 Tuning */
193
+ REG_PLL3_CFG = 0x0010, /* PLL3 Control */
194
+ REG_PLL4_CFG = 0x0018, /* PLL4 Control */
195
+ REG_PLL5_CFG = 0x0020, /* PLL5 Control */
196
+ REG_PLL5_TUN = 0x0024, /* PLL5 Tuning */
197
+ REG_PLL6_CFG = 0x0028, /* PLL6 Control */
198
+ REG_PLL6_TUN = 0x002C, /* PLL6 Tuning */
199
+ REG_PLL7_CFG = 0x0030, /* PLL7 Control */
200
+ REG_PLL1_TUN2 = 0x0038, /* PLL1 Tuning2 */
201
+ REG_PLL5_TUN2 = 0x003C, /* PLL5 Tuning2 */
202
+ REG_PLL8_CFG = 0x0040, /* PLL8 Control */
203
+ REG_OSC24M_CFG = 0x0050, /* OSC24M Control */
204
+ REG_CPU_AHB_APB0_CFG = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
205
+};
206
+
207
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
208
+
209
+/* CCM register reset values */
210
+enum {
211
+ REG_PLL1_CFG_RST = 0x21005000,
212
+ REG_PLL1_TUN_RST = 0x0A101000,
213
+ REG_PLL2_CFG_RST = 0x08100010,
214
+ REG_PLL2_TUN_RST = 0x00000000,
215
+ REG_PLL3_CFG_RST = 0x0010D063,
216
+ REG_PLL4_CFG_RST = 0x21009911,
217
+ REG_PLL5_CFG_RST = 0x11049280,
218
+ REG_PLL5_TUN_RST = 0x14888000,
219
+ REG_PLL6_CFG_RST = 0x21009911,
220
+ REG_PLL6_TUN_RST = 0x00000000,
221
+ REG_PLL7_CFG_RST = 0x0010D063,
222
+ REG_PLL1_TUN2_RST = 0x00000000,
223
+ REG_PLL5_TUN2_RST = 0x00000000,
224
+ REG_PLL8_CFG_RST = 0x21009911,
225
+ REG_OSC24M_CFG_RST = 0x00138013,
226
+ REG_CPU_AHB_APB0_CFG_RST = 0x00010010,
227
+};
228
+
229
+static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset,
230
+ unsigned size)
231
+{
232
+ const AwA10ClockCtlState *s = AW_A10_CCM(opaque);
233
+ const uint32_t idx = REG_INDEX(offset);
234
+
235
+ switch (offset) {
236
+ case REG_PLL1_CFG:
237
+ case REG_PLL1_TUN:
238
+ case REG_PLL2_CFG:
239
+ case REG_PLL2_TUN:
240
+ case REG_PLL3_CFG:
241
+ case REG_PLL4_CFG:
242
+ case REG_PLL5_CFG:
243
+ case REG_PLL5_TUN:
244
+ case REG_PLL6_CFG:
245
+ case REG_PLL6_TUN:
246
+ case REG_PLL7_CFG:
247
+ case REG_PLL1_TUN2:
248
+ case REG_PLL5_TUN2:
249
+ case REG_PLL8_CFG:
250
+ case REG_OSC24M_CFG:
251
+ case REG_CPU_AHB_APB0_CFG:
252
+ break;
253
+ case 0x158 ... AW_A10_CCM_IOSIZE:
254
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
255
+ __func__, (uint32_t)offset);
256
+ return 0;
257
+ default:
258
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
259
+ __func__, (uint32_t)offset);
260
+ return 0;
261
+ }
262
+
263
+ return s->regs[idx];
264
+}
265
+
266
+static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
267
+ uint64_t val, unsigned size)
268
+{
269
+ AwA10ClockCtlState *s = AW_A10_CCM(opaque);
270
+ const uint32_t idx = REG_INDEX(offset);
271
+
272
+ switch (offset) {
273
+ case REG_PLL1_CFG:
274
+ case REG_PLL1_TUN:
275
+ case REG_PLL2_CFG:
276
+ case REG_PLL2_TUN:
277
+ case REG_PLL3_CFG:
278
+ case REG_PLL4_CFG:
279
+ case REG_PLL5_CFG:
280
+ case REG_PLL5_TUN:
281
+ case REG_PLL6_CFG:
282
+ case REG_PLL6_TUN:
283
+ case REG_PLL7_CFG:
284
+ case REG_PLL1_TUN2:
285
+ case REG_PLL5_TUN2:
286
+ case REG_PLL8_CFG:
287
+ case REG_OSC24M_CFG:
288
+ case REG_CPU_AHB_APB0_CFG:
289
+ break;
290
+ case 0x158 ... AW_A10_CCM_IOSIZE:
291
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
292
+ __func__, (uint32_t)offset);
293
+ break;
294
+ default:
295
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
296
+ __func__, (uint32_t)offset);
297
+ break;
298
+ }
299
+
300
+ s->regs[idx] = (uint32_t) val;
301
+}
302
+
303
+static const MemoryRegionOps allwinner_a10_ccm_ops = {
304
+ .read = allwinner_a10_ccm_read,
305
+ .write = allwinner_a10_ccm_write,
306
+ .endianness = DEVICE_NATIVE_ENDIAN,
307
+ .valid = {
308
+ .min_access_size = 4,
309
+ .max_access_size = 4,
310
+ },
311
+ .impl.min_access_size = 4,
312
+};
313
+
314
+static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type)
315
+{
316
+ AwA10ClockCtlState *s = AW_A10_CCM(obj);
317
+
318
+ /* Set default values for registers */
319
+ s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST;
320
+ s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST;
321
+ s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST;
322
+ s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST;
323
+ s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST;
324
+ s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST;
325
+ s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST;
326
+ s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST;
327
+ s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST;
328
+ s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST;
329
+ s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST;
330
+ s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST;
331
+ s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST;
332
+ s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST;
333
+ s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST;
334
+ s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST;
335
+}
336
+
337
+static void allwinner_a10_ccm_init(Object *obj)
338
+{
339
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
340
+ AwA10ClockCtlState *s = AW_A10_CCM(obj);
341
+
342
+ /* Memory mapping */
343
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s,
344
+ TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE);
345
+ sysbus_init_mmio(sbd, &s->iomem);
346
+}
347
+
348
+static const VMStateDescription allwinner_a10_ccm_vmstate = {
349
+ .name = "allwinner-a10-ccm",
350
+ .version_id = 1,
351
+ .minimum_version_id = 1,
352
+ .fields = (VMStateField[]) {
353
+ VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM),
354
+ VMSTATE_END_OF_LIST()
355
+ }
356
+};
357
+
358
+static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data)
359
+{
360
+ DeviceClass *dc = DEVICE_CLASS(klass);
361
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
362
+
363
+ rc->phases.enter = allwinner_a10_ccm_reset_enter;
364
+ dc->vmsd = &allwinner_a10_ccm_vmstate;
365
+}
366
+
367
+static const TypeInfo allwinner_a10_ccm_info = {
368
+ .name = TYPE_AW_A10_CCM,
369
+ .parent = TYPE_SYS_BUS_DEVICE,
370
+ .instance_init = allwinner_a10_ccm_init,
371
+ .instance_size = sizeof(AwA10ClockCtlState),
372
+ .class_init = allwinner_a10_ccm_class_init,
373
+};
374
+
375
+static void allwinner_a10_ccm_register(void)
376
+{
377
+ type_register_static(&allwinner_a10_ccm_info);
378
+}
379
+
380
+type_init(allwinner_a10_ccm_register)
381
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
382
index XXXXXXX..XXXXXXX 100644
383
--- a/hw/arm/Kconfig
384
+++ b/hw/arm/Kconfig
385
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
386
select AHCI
387
select ALLWINNER_A10_PIT
388
select ALLWINNER_A10_PIC
389
+ select ALLWINNER_A10_CCM
390
select ALLWINNER_EMAC
391
select SERIAL
392
select UNIMP
393
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
394
index XXXXXXX..XXXXXXX 100644
395
--- a/hw/misc/Kconfig
396
+++ b/hw/misc/Kconfig
397
@@ -XXX,XX +XXX,XX @@ config VIRT_CTRL
398
config LASI
399
bool
400
401
+config ALLWINNER_A10_CCM
402
+ bool
403
+
404
source macio/Kconfig
405
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
406
index XXXXXXX..XXXXXXX 100644
407
--- a/hw/misc/meson.build
408
+++ b/hw/misc/meson.build
409
@@ -XXX,XX +XXX,XX @@ subdir('macio')
410
411
softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
412
413
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
414
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
415
specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
416
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
417
--
418
2.34.1
diff view generated by jsdifflib
New patch
1
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
2
3
During SPL boot several DRAM Controller registers are used. Most
4
important registers are those related to DRAM initialization and
5
calibration, where SPL initiates process and waits until certain bit is
6
set/cleared.
7
8
This patch adds these registers, initializes reset values from user's
9
guide and updates state of registers as SPL expects it.
10
11
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
12
13
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
include/hw/arm/allwinner-a10.h | 2 +
18
include/hw/misc/allwinner-a10-dramc.h | 68 ++++++++++
19
hw/arm/allwinner-a10.c | 7 +
20
hw/misc/allwinner-a10-dramc.c | 179 ++++++++++++++++++++++++++
21
hw/arm/Kconfig | 1 +
22
hw/misc/Kconfig | 3 +
23
hw/misc/meson.build | 1 +
24
7 files changed, 261 insertions(+)
25
create mode 100644 include/hw/misc/allwinner-a10-dramc.h
26
create mode 100644 hw/misc/allwinner-a10-dramc.c
27
28
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-a10.h
31
+++ b/include/hw/arm/allwinner-a10.h
32
@@ -XXX,XX +XXX,XX @@
33
#include "hw/usb/hcd-ehci.h"
34
#include "hw/rtc/allwinner-rtc.h"
35
#include "hw/misc/allwinner-a10-ccm.h"
36
+#include "hw/misc/allwinner-a10-dramc.h"
37
38
#include "target/arm/cpu.h"
39
#include "qom/object.h"
40
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
41
42
ARMCPU cpu;
43
AwA10ClockCtlState ccm;
44
+ AwA10DramControllerState dramc;
45
AwA10PITState timer;
46
AwA10PICState intc;
47
AwEmacState emac;
48
diff --git a/include/hw/misc/allwinner-a10-dramc.h b/include/hw/misc/allwinner-a10-dramc.h
49
new file mode 100644
50
index XXXXXXX..XXXXXXX
51
--- /dev/null
52
+++ b/include/hw/misc/allwinner-a10-dramc.h
53
@@ -XXX,XX +XXX,XX @@
54
+/*
55
+ * Allwinner A10 DRAM Controller emulation
56
+ *
57
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
58
+ *
59
+ * This file is derived from Allwinner H3 DRAMC,
60
+ * by Niek Linnenbank.
61
+ *
62
+ * This program is free software: you can redistribute it and/or modify
63
+ * it under the terms of the GNU General Public License as published by
64
+ * the Free Software Foundation, either version 2 of the License, or
65
+ * (at your option) any later version.
66
+ *
67
+ * This program is distributed in the hope that it will be useful,
68
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
69
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
70
+ * GNU General Public License for more details.
71
+ *
72
+ * You should have received a copy of the GNU General Public License
73
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
74
+ */
75
+
76
+#ifndef HW_MISC_ALLWINNER_A10_DRAMC_H
77
+#define HW_MISC_ALLWINNER_A10_DRAMC_H
78
+
79
+#include "qom/object.h"
80
+#include "hw/sysbus.h"
81
+#include "hw/register.h"
82
+
83
+/**
84
+ * @name Constants
85
+ * @{
86
+ */
87
+
88
+/** Size of register I/O address space used by DRAMC device */
89
+#define AW_A10_DRAMC_IOSIZE (0x1000)
90
+
91
+/** Total number of known registers */
92
+#define AW_A10_DRAMC_REGS_NUM (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t))
93
+
94
+/** @} */
95
+
96
+/**
97
+ * @name Object model
98
+ * @{
99
+ */
100
+
101
+#define TYPE_AW_A10_DRAMC "allwinner-a10-dramc"
102
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC)
103
+
104
+/** @} */
105
+
106
+/**
107
+ * Allwinner A10 DRAMC object instance state.
108
+ */
109
+struct AwA10DramControllerState {
110
+ /*< private >*/
111
+ SysBusDevice parent_obj;
112
+ /*< public >*/
113
+
114
+ /** Maps I/O registers in physical memory */
115
+ MemoryRegion iomem;
116
+
117
+ /** Array of hardware registers */
118
+ uint32_t regs[AW_A10_DRAMC_REGS_NUM];
119
+};
120
+
121
+#endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */
122
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/arm/allwinner-a10.c
125
+++ b/hw/arm/allwinner-a10.c
126
@@ -XXX,XX +XXX,XX @@
127
#include "hw/boards.h"
128
#include "hw/usb/hcd-ohci.h"
129
130
+#define AW_A10_DRAMC_BASE 0x01c01000
131
#define AW_A10_MMC0_BASE 0x01c0f000
132
#define AW_A10_CCM_BASE 0x01c20000
133
#define AW_A10_PIC_REG_BASE 0x01c20400
134
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
135
136
object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
137
138
+ object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
139
+
140
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
141
142
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
143
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
144
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
145
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
146
147
+ /* DRAM Control Module */
148
+ sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
149
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
150
+
151
/* FIXME use qdev NIC properties instead of nd_table[] */
152
if (nd_table[0].used) {
153
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
154
diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
155
new file mode 100644
156
index XXXXXXX..XXXXXXX
157
--- /dev/null
158
+++ b/hw/misc/allwinner-a10-dramc.c
159
@@ -XXX,XX +XXX,XX @@
160
+/*
161
+ * Allwinner A10 DRAM Controller emulation
162
+ *
163
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
164
+ *
165
+ * This file is derived from Allwinner H3 DRAMC,
166
+ * by Niek Linnenbank.
167
+ *
168
+ * This program is free software: you can redistribute it and/or modify
169
+ * it under the terms of the GNU General Public License as published by
170
+ * the Free Software Foundation, either version 2 of the License, or
171
+ * (at your option) any later version.
172
+ *
173
+ * This program is distributed in the hope that it will be useful,
174
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
175
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
176
+ * GNU General Public License for more details.
177
+ *
178
+ * You should have received a copy of the GNU General Public License
179
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
180
+ */
181
+
182
+#include "qemu/osdep.h"
183
+#include "qemu/units.h"
184
+#include "hw/sysbus.h"
185
+#include "migration/vmstate.h"
186
+#include "qemu/log.h"
187
+#include "qemu/module.h"
188
+#include "hw/misc/allwinner-a10-dramc.h"
189
+
190
+/* DRAMC register offsets */
191
+enum {
192
+ REG_SDR_CCR = 0x0000,
193
+ REG_SDR_ZQCR0 = 0x00a8,
194
+ REG_SDR_ZQSR = 0x00b0
195
+};
196
+
197
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
198
+
199
+/* DRAMC register flags */
200
+enum {
201
+ REG_SDR_CCR_DATA_TRAINING = (1 << 30),
202
+ REG_SDR_CCR_DRAM_INIT = (1 << 31),
203
+};
204
+enum {
205
+ REG_SDR_ZQSR_ZCAL = (1 << 31),
206
+};
207
+
208
+/* DRAMC register reset values */
209
+enum {
210
+ REG_SDR_CCR_RESET = 0x80020000,
211
+ REG_SDR_ZQCR0_RESET = 0x07b00000,
212
+ REG_SDR_ZQSR_RESET = 0x80000000
213
+};
214
+
215
+static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset,
216
+ unsigned size)
217
+{
218
+ const AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
219
+ const uint32_t idx = REG_INDEX(offset);
220
+
221
+ switch (offset) {
222
+ case REG_SDR_CCR:
223
+ case REG_SDR_ZQCR0:
224
+ case REG_SDR_ZQSR:
225
+ break;
226
+ case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
227
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
228
+ __func__, (uint32_t)offset);
229
+ return 0;
230
+ default:
231
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
232
+ __func__, (uint32_t)offset);
233
+ return 0;
234
+ }
235
+
236
+ return s->regs[idx];
237
+}
238
+
239
+static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
240
+ uint64_t val, unsigned size)
241
+{
242
+ AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
243
+ const uint32_t idx = REG_INDEX(offset);
244
+
245
+ switch (offset) {
246
+ case REG_SDR_CCR:
247
+ if (val & REG_SDR_CCR_DRAM_INIT) {
248
+ /* Clear DRAM_INIT to indicate process is done. */
249
+ val &= ~REG_SDR_CCR_DRAM_INIT;
250
+ }
251
+ if (val & REG_SDR_CCR_DATA_TRAINING) {
252
+ /* Clear DATA_TRAINING to indicate process is done. */
253
+ val &= ~REG_SDR_CCR_DATA_TRAINING;
254
+ }
255
+ break;
256
+ case REG_SDR_ZQCR0:
257
+ /* Set ZCAL in ZQSR to indicate calibration is done. */
258
+ s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL;
259
+ break;
260
+ case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
261
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
262
+ __func__, (uint32_t)offset);
263
+ break;
264
+ default:
265
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
266
+ __func__, (uint32_t)offset);
267
+ break;
268
+ }
269
+
270
+ s->regs[idx] = (uint32_t) val;
271
+}
272
+
273
+static const MemoryRegionOps allwinner_a10_dramc_ops = {
274
+ .read = allwinner_a10_dramc_read,
275
+ .write = allwinner_a10_dramc_write,
276
+ .endianness = DEVICE_NATIVE_ENDIAN,
277
+ .valid = {
278
+ .min_access_size = 4,
279
+ .max_access_size = 4,
280
+ },
281
+ .impl.min_access_size = 4,
282
+};
283
+
284
+static void allwinner_a10_dramc_reset_enter(Object *obj, ResetType type)
285
+{
286
+ AwA10DramControllerState *s = AW_A10_DRAMC(obj);
287
+
288
+ /* Set default values for registers */
289
+ s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET;
290
+ s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET;
291
+ s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET;
292
+}
293
+
294
+static void allwinner_a10_dramc_init(Object *obj)
295
+{
296
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
297
+ AwA10DramControllerState *s = AW_A10_DRAMC(obj);
298
+
299
+ /* Memory mapping */
300
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_dramc_ops, s,
301
+ TYPE_AW_A10_DRAMC, AW_A10_DRAMC_IOSIZE);
302
+ sysbus_init_mmio(sbd, &s->iomem);
303
+}
304
+
305
+static const VMStateDescription allwinner_a10_dramc_vmstate = {
306
+ .name = "allwinner-a10-dramc",
307
+ .version_id = 1,
308
+ .minimum_version_id = 1,
309
+ .fields = (VMStateField[]) {
310
+ VMSTATE_UINT32_ARRAY(regs, AwA10DramControllerState,
311
+ AW_A10_DRAMC_REGS_NUM),
312
+ VMSTATE_END_OF_LIST()
313
+ }
314
+};
315
+
316
+static void allwinner_a10_dramc_class_init(ObjectClass *klass, void *data)
317
+{
318
+ DeviceClass *dc = DEVICE_CLASS(klass);
319
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
320
+
321
+ rc->phases.enter = allwinner_a10_dramc_reset_enter;
322
+ dc->vmsd = &allwinner_a10_dramc_vmstate;
323
+}
324
+
325
+static const TypeInfo allwinner_a10_dramc_info = {
326
+ .name = TYPE_AW_A10_DRAMC,
327
+ .parent = TYPE_SYS_BUS_DEVICE,
328
+ .instance_init = allwinner_a10_dramc_init,
329
+ .instance_size = sizeof(AwA10DramControllerState),
330
+ .class_init = allwinner_a10_dramc_class_init,
331
+};
332
+
333
+static void allwinner_a10_dramc_register(void)
334
+{
335
+ type_register_static(&allwinner_a10_dramc_info);
336
+}
337
+
338
+type_init(allwinner_a10_dramc_register)
339
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
340
index XXXXXXX..XXXXXXX 100644
341
--- a/hw/arm/Kconfig
342
+++ b/hw/arm/Kconfig
343
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
344
select ALLWINNER_A10_PIT
345
select ALLWINNER_A10_PIC
346
select ALLWINNER_A10_CCM
347
+ select ALLWINNER_A10_DRAMC
348
select ALLWINNER_EMAC
349
select SERIAL
350
select UNIMP
351
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
352
index XXXXXXX..XXXXXXX 100644
353
--- a/hw/misc/Kconfig
354
+++ b/hw/misc/Kconfig
355
@@ -XXX,XX +XXX,XX @@ config LASI
356
config ALLWINNER_A10_CCM
357
bool
358
359
+config ALLWINNER_A10_DRAMC
360
+ bool
361
+
362
source macio/Kconfig
363
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
364
index XXXXXXX..XXXXXXX 100644
365
--- a/hw/misc/meson.build
366
+++ b/hw/misc/meson.build
367
@@ -XXX,XX +XXX,XX @@ subdir('macio')
368
softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
369
370
softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
371
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinner-a10-dramc.c'))
372
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
373
specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
374
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
375
--
376
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
This patch implements Allwinner TWI/I2C controller emulation. Only
4
master-mode functionality is implemented.
5
6
The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
7
first part enabling the TWI/I2C bus operation.
8
9
Since both Allwinner A10 and H3 use the same module, it is added for
10
both boards.
11
12
Docs are also updated for Cubieboard and Orangepi-PC board to indicate
13
I2C availability.
14
15
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
16
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
17
Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
docs/system/arm/cubieboard.rst | 1 +
21
docs/system/arm/orangepi.rst | 1 +
22
include/hw/arm/allwinner-a10.h | 2 +
23
include/hw/arm/allwinner-h3.h | 3 +
24
include/hw/i2c/allwinner-i2c.h | 55 ++++
25
hw/arm/allwinner-a10.c | 8 +
26
hw/arm/allwinner-h3.c | 11 +-
27
hw/i2c/allwinner-i2c.c | 459 +++++++++++++++++++++++++++++++++
28
hw/arm/Kconfig | 2 +
29
hw/i2c/Kconfig | 4 +
30
hw/i2c/meson.build | 1 +
31
hw/i2c/trace-events | 5 +
32
12 files changed, 551 insertions(+), 1 deletion(-)
33
create mode 100644 include/hw/i2c/allwinner-i2c.h
34
create mode 100644 hw/i2c/allwinner-i2c.c
35
36
diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
37
index XXXXXXX..XXXXXXX 100644
38
--- a/docs/system/arm/cubieboard.rst
39
+++ b/docs/system/arm/cubieboard.rst
40
@@ -XXX,XX +XXX,XX @@ Emulated devices:
41
- SDHCI
42
- USB controller
43
- SATA controller
44
+- TWI (I2C) controller
45
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
46
index XXXXXXX..XXXXXXX 100644
47
--- a/docs/system/arm/orangepi.rst
48
+++ b/docs/system/arm/orangepi.rst
49
@@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices:
50
* Clock Control Unit
51
* System Control module
52
* Security Identifier device
53
+ * TWI (I2C)
54
55
Limitations
56
"""""""""""
57
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/hw/arm/allwinner-a10.h
60
+++ b/include/hw/arm/allwinner-a10.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "hw/rtc/allwinner-rtc.h"
63
#include "hw/misc/allwinner-a10-ccm.h"
64
#include "hw/misc/allwinner-a10-dramc.h"
65
+#include "hw/i2c/allwinner-i2c.h"
66
67
#include "target/arm/cpu.h"
68
#include "qom/object.h"
69
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
70
AwEmacState emac;
71
AllwinnerAHCIState sata;
72
AwSdHostState mmc0;
73
+ AWI2CState i2c0;
74
AwRtcState rtc;
75
MemoryRegion sram_a;
76
EHCISysBusState ehci[AW_A10_NUM_USB];
77
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
78
index XXXXXXX..XXXXXXX 100644
79
--- a/include/hw/arm/allwinner-h3.h
80
+++ b/include/hw/arm/allwinner-h3.h
81
@@ -XXX,XX +XXX,XX @@
82
#include "hw/sd/allwinner-sdhost.h"
83
#include "hw/net/allwinner-sun8i-emac.h"
84
#include "hw/rtc/allwinner-rtc.h"
85
+#include "hw/i2c/allwinner-i2c.h"
86
#include "target/arm/cpu.h"
87
#include "sysemu/block-backend.h"
88
89
@@ -XXX,XX +XXX,XX @@ enum {
90
AW_H3_DEV_UART2,
91
AW_H3_DEV_UART3,
92
AW_H3_DEV_EMAC,
93
+ AW_H3_DEV_TWI0,
94
AW_H3_DEV_DRAMCOM,
95
AW_H3_DEV_DRAMCTL,
96
AW_H3_DEV_DRAMPHY,
97
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
98
AwH3SysCtrlState sysctrl;
99
AwSidState sid;
100
AwSdHostState mmc0;
101
+ AWI2CState i2c0;
102
AwSun8iEmacState emac;
103
AwRtcState rtc;
104
GICState gic;
105
diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
106
new file mode 100644
107
index XXXXXXX..XXXXXXX
108
--- /dev/null
109
+++ b/include/hw/i2c/allwinner-i2c.h
110
@@ -XXX,XX +XXX,XX @@
111
+/*
112
+ * Allwinner I2C Bus Serial Interface registers definition
113
+ *
114
+ * Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
115
+ *
116
+ * This file is derived from IMX I2C controller,
117
+ * by Jean-Christophe DUBOIS .
118
+ *
119
+ * This program is free software; you can redistribute it and/or modify it
120
+ * under the terms of the GNU General Public License as published by the
121
+ * Free Software Foundation; either version 2 of the License, or
122
+ * (at your option) any later version.
123
+ *
124
+ * This program is distributed in the hope that it will be useful, but WITHOUT
125
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
126
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
127
+ * for more details.
128
+ *
129
+ * You should have received a copy of the GNU General Public License along
130
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
131
+ *
132
+ */
133
+
134
+#ifndef ALLWINNER_I2C_H
135
+#define ALLWINNER_I2C_H
136
+
137
+#include "hw/sysbus.h"
138
+#include "qom/object.h"
139
+
140
+#define TYPE_AW_I2C "allwinner.i2c"
141
+OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
142
+
143
+#define AW_I2C_MEM_SIZE 0x24
144
+
145
+struct AWI2CState {
146
+ /*< private >*/
147
+ SysBusDevice parent_obj;
148
+
149
+ /*< public >*/
150
+ MemoryRegion iomem;
151
+ I2CBus *bus;
152
+ qemu_irq irq;
153
+
154
+ uint8_t addr;
155
+ uint8_t xaddr;
156
+ uint8_t data;
157
+ uint8_t cntr;
158
+ uint8_t stat;
159
+ uint8_t ccr;
160
+ uint8_t srst;
161
+ uint8_t efr;
162
+ uint8_t lcr;
163
+};
164
+
165
+#endif /* ALLWINNER_I2C_H */
166
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/arm/allwinner-a10.c
169
+++ b/hw/arm/allwinner-a10.c
170
@@ -XXX,XX +XXX,XX @@
171
#define AW_A10_OHCI_BASE 0x01c14400
172
#define AW_A10_SATA_BASE 0x01c18000
173
#define AW_A10_RTC_BASE 0x01c20d00
174
+#define AW_A10_I2C0_BASE 0x01c2ac00
175
176
static void aw_a10_init(Object *obj)
177
{
178
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
179
180
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
181
182
+ object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
183
+
184
if (machine_usb(current_machine)) {
185
int i;
186
187
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
188
/* RTC */
189
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
190
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
191
+
192
+ /* I2C */
193
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
194
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
195
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
196
}
197
198
static void aw_a10_class_init(ObjectClass *oc, void *data)
199
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/arm/allwinner-h3.c
202
+++ b/hw/arm/allwinner-h3.c
203
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
204
[AW_H3_DEV_UART1] = 0x01c28400,
205
[AW_H3_DEV_UART2] = 0x01c28800,
206
[AW_H3_DEV_UART3] = 0x01c28c00,
207
+ [AW_H3_DEV_TWI0] = 0x01c2ac00,
208
[AW_H3_DEV_EMAC] = 0x01c30000,
209
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
210
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
211
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
212
{ "uart1", 0x01c28400, 1 * KiB },
213
{ "uart2", 0x01c28800, 1 * KiB },
214
{ "uart3", 0x01c28c00, 1 * KiB },
215
- { "twi0", 0x01c2ac00, 1 * KiB },
216
{ "twi1", 0x01c2b000, 1 * KiB },
217
{ "twi2", 0x01c2b400, 1 * KiB },
218
{ "scr", 0x01c2c400, 1 * KiB },
219
@@ -XXX,XX +XXX,XX @@ enum {
220
AW_H3_GIC_SPI_UART1 = 1,
221
AW_H3_GIC_SPI_UART2 = 2,
222
AW_H3_GIC_SPI_UART3 = 3,
223
+ AW_H3_GIC_SPI_TWI0 = 6,
224
AW_H3_GIC_SPI_TIMER0 = 18,
225
AW_H3_GIC_SPI_TIMER1 = 19,
226
AW_H3_GIC_SPI_MMC0 = 60,
227
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
228
"ram-size");
229
230
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
231
+
232
+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
233
}
234
235
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
236
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
237
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
238
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
239
240
+ /* I2C */
241
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
242
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
243
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
244
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
245
+
246
/* Unimplemented devices */
247
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
248
create_unimplemented_device(unimplemented[i].device_name,
249
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
250
new file mode 100644
251
index XXXXXXX..XXXXXXX
252
--- /dev/null
253
+++ b/hw/i2c/allwinner-i2c.c
254
@@ -XXX,XX +XXX,XX @@
255
+/*
256
+ * Allwinner I2C Bus Serial Interface Emulation
257
+ *
258
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
259
+ *
260
+ * This file is derived from IMX I2C controller,
261
+ * by Jean-Christophe DUBOIS .
262
+ *
263
+ * This program is free software; you can redistribute it and/or modify it
264
+ * under the terms of the GNU General Public License as published by the
265
+ * Free Software Foundation; either version 2 of the License, or
266
+ * (at your option) any later version.
267
+ *
268
+ * This program is distributed in the hope that it will be useful, but WITHOUT
269
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
270
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
271
+ * for more details.
272
+ *
273
+ * You should have received a copy of the GNU General Public License along
274
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
275
+ *
276
+ * SPDX-License-Identifier: MIT
277
+ */
278
+
279
+#include "qemu/osdep.h"
280
+#include "hw/i2c/allwinner-i2c.h"
281
+#include "hw/irq.h"
282
+#include "migration/vmstate.h"
283
+#include "hw/i2c/i2c.h"
284
+#include "qemu/log.h"
285
+#include "trace.h"
286
+#include "qemu/module.h"
287
+
288
+/* Allwinner I2C memory map */
289
+#define TWI_ADDR_REG 0x00 /* slave address register */
290
+#define TWI_XADDR_REG 0x04 /* extended slave address register */
291
+#define TWI_DATA_REG 0x08 /* data register */
292
+#define TWI_CNTR_REG 0x0c /* control register */
293
+#define TWI_STAT_REG 0x10 /* status register */
294
+#define TWI_CCR_REG 0x14 /* clock control register */
295
+#define TWI_SRST_REG 0x18 /* software reset register */
296
+#define TWI_EFR_REG 0x1c /* enhance feature register */
297
+#define TWI_LCR_REG 0x20 /* line control register */
298
+
299
+/* Used only in slave mode, do not set */
300
+#define TWI_ADDR_RESET 0
301
+#define TWI_XADDR_RESET 0
302
+
303
+/* Data register */
304
+#define TWI_DATA_MASK 0xFF
305
+#define TWI_DATA_RESET 0
306
+
307
+/* Control register */
308
+#define TWI_CNTR_INT_EN (1 << 7)
309
+#define TWI_CNTR_BUS_EN (1 << 6)
310
+#define TWI_CNTR_M_STA (1 << 5)
311
+#define TWI_CNTR_M_STP (1 << 4)
312
+#define TWI_CNTR_INT_FLAG (1 << 3)
313
+#define TWI_CNTR_A_ACK (1 << 2)
314
+#define TWI_CNTR_MASK 0xFC
315
+#define TWI_CNTR_RESET 0
316
+
317
+/* Status register */
318
+#define TWI_STAT_MASK 0xF8
319
+#define TWI_STAT_RESET 0xF8
320
+
321
+/* Clock register */
322
+#define TWI_CCR_CLK_M_MASK 0x78
323
+#define TWI_CCR_CLK_N_MASK 0x07
324
+#define TWI_CCR_MASK 0x7F
325
+#define TWI_CCR_RESET 0
326
+
327
+/* Soft reset */
328
+#define TWI_SRST_MASK 0x01
329
+#define TWI_SRST_RESET 0
330
+
331
+/* Enhance feature */
332
+#define TWI_EFR_MASK 0x03
333
+#define TWI_EFR_RESET 0
334
+
335
+/* Line control */
336
+#define TWI_LCR_SCL_STATE (1 << 5)
337
+#define TWI_LCR_SDA_STATE (1 << 4)
338
+#define TWI_LCR_SCL_CTL (1 << 3)
339
+#define TWI_LCR_SCL_CTL_EN (1 << 2)
340
+#define TWI_LCR_SDA_CTL (1 << 1)
341
+#define TWI_LCR_SDA_CTL_EN (1 << 0)
342
+#define TWI_LCR_MASK 0x3F
343
+#define TWI_LCR_RESET 0x3A
344
+
345
+/* Status value in STAT register is shifted by 3 bits */
346
+#define TWI_STAT_SHIFT 3
347
+#define STAT_FROM_STA(x) ((x) << TWI_STAT_SHIFT)
348
+#define STAT_TO_STA(x) ((x) >> TWI_STAT_SHIFT)
349
+
350
+enum {
351
+ STAT_BUS_ERROR = 0,
352
+ /* Master mode */
353
+ STAT_M_STA_TX,
354
+ STAT_M_RSTA_TX,
355
+ STAT_M_ADDR_WR_ACK,
356
+ STAT_M_ADDR_WR_NACK,
357
+ STAT_M_DATA_TX_ACK,
358
+ STAT_M_DATA_TX_NACK,
359
+ STAT_M_ARB_LOST,
360
+ STAT_M_ADDR_RD_ACK,
361
+ STAT_M_ADDR_RD_NACK,
362
+ STAT_M_DATA_RX_ACK,
363
+ STAT_M_DATA_RX_NACK,
364
+ /* Slave mode */
365
+ STAT_S_ADDR_WR_ACK,
366
+ STAT_S_ARB_LOST_AW_ACK,
367
+ STAT_S_GCA_ACK,
368
+ STAT_S_ARB_LOST_GCA_ACK,
369
+ STAT_S_DATA_RX_SA_ACK,
370
+ STAT_S_DATA_RX_SA_NACK,
371
+ STAT_S_DATA_RX_GCA_ACK,
372
+ STAT_S_DATA_RX_GCA_NACK,
373
+ STAT_S_STP_RSTA,
374
+ STAT_S_ADDR_RD_ACK,
375
+ STAT_S_ARB_LOST_AR_ACK,
376
+ STAT_S_DATA_TX_ACK,
377
+ STAT_S_DATA_TX_NACK,
378
+ STAT_S_LB_TX_ACK,
379
+ /* Master mode, 10-bit */
380
+ STAT_M_2ND_ADDR_WR_ACK,
381
+ STAT_M_2ND_ADDR_WR_NACK,
382
+ /* Idle */
383
+ STAT_IDLE = 0x1f
384
+} TWI_STAT_STA;
385
+
386
+static const char *allwinner_i2c_get_regname(unsigned offset)
387
+{
388
+ switch (offset) {
389
+ case TWI_ADDR_REG:
390
+ return "ADDR";
391
+ case TWI_XADDR_REG:
392
+ return "XADDR";
393
+ case TWI_DATA_REG:
394
+ return "DATA";
395
+ case TWI_CNTR_REG:
396
+ return "CNTR";
397
+ case TWI_STAT_REG:
398
+ return "STAT";
399
+ case TWI_CCR_REG:
400
+ return "CCR";
401
+ case TWI_SRST_REG:
402
+ return "SRST";
403
+ case TWI_EFR_REG:
404
+ return "EFR";
405
+ case TWI_LCR_REG:
406
+ return "LCR";
407
+ default:
408
+ return "[?]";
409
+ }
410
+}
411
+
412
+static inline bool allwinner_i2c_is_reset(AWI2CState *s)
413
+{
414
+ return s->srst & TWI_SRST_MASK;
415
+}
416
+
417
+static inline bool allwinner_i2c_bus_is_enabled(AWI2CState *s)
418
+{
419
+ return s->cntr & TWI_CNTR_BUS_EN;
420
+}
421
+
422
+static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
423
+{
424
+ return s->cntr & TWI_CNTR_INT_EN;
425
+}
426
+
427
+static void allwinner_i2c_reset_hold(Object *obj)
428
+{
429
+ AWI2CState *s = AW_I2C(obj);
430
+
431
+ if (STAT_TO_STA(s->stat) != STAT_IDLE) {
432
+ i2c_end_transfer(s->bus);
433
+ }
434
+
435
+ s->addr = TWI_ADDR_RESET;
436
+ s->xaddr = TWI_XADDR_RESET;
437
+ s->data = TWI_DATA_RESET;
438
+ s->cntr = TWI_CNTR_RESET;
439
+ s->stat = TWI_STAT_RESET;
440
+ s->ccr = TWI_CCR_RESET;
441
+ s->srst = TWI_SRST_RESET;
442
+ s->efr = TWI_EFR_RESET;
443
+ s->lcr = TWI_LCR_RESET;
444
+}
445
+
446
+static inline void allwinner_i2c_raise_interrupt(AWI2CState *s)
447
+{
448
+ /*
449
+ * Raise an interrupt if the device is not reset and it is configured
450
+ * to generate some interrupts.
451
+ */
452
+ if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) {
453
+ if (STAT_TO_STA(s->stat) != STAT_IDLE) {
454
+ s->cntr |= TWI_CNTR_INT_FLAG;
455
+ if (allwinner_i2c_interrupt_is_enabled(s)) {
456
+ qemu_irq_raise(s->irq);
457
+ }
458
+ }
459
+ }
460
+}
461
+
462
+static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset,
463
+ unsigned size)
464
+{
465
+ uint16_t value;
466
+ AWI2CState *s = AW_I2C(opaque);
467
+
468
+ switch (offset) {
469
+ case TWI_ADDR_REG:
470
+ value = s->addr;
471
+ break;
472
+ case TWI_XADDR_REG:
473
+ value = s->xaddr;
474
+ break;
475
+ case TWI_DATA_REG:
476
+ if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) ||
477
+ (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) ||
478
+ (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) {
479
+ /* Get the next byte */
480
+ s->data = i2c_recv(s->bus);
481
+
482
+ if (s->cntr & TWI_CNTR_A_ACK) {
483
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
484
+ } else {
485
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
486
+ }
487
+ allwinner_i2c_raise_interrupt(s);
488
+ }
489
+ value = s->data;
490
+ break;
491
+ case TWI_CNTR_REG:
492
+ value = s->cntr;
493
+ break;
494
+ case TWI_STAT_REG:
495
+ value = s->stat;
496
+ /*
497
+ * If polling when reading then change state to indicate data
498
+ * is available
499
+ */
500
+ if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) {
501
+ if (s->cntr & TWI_CNTR_A_ACK) {
502
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
503
+ } else {
504
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
505
+ }
506
+ allwinner_i2c_raise_interrupt(s);
507
+ }
508
+ break;
509
+ case TWI_CCR_REG:
510
+ value = s->ccr;
511
+ break;
512
+ case TWI_SRST_REG:
513
+ value = s->srst;
514
+ break;
515
+ case TWI_EFR_REG:
516
+ value = s->efr;
517
+ break;
518
+ case TWI_LCR_REG:
519
+ value = s->lcr;
520
+ break;
521
+ default:
522
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
523
+ HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
524
+ value = 0;
525
+ break;
526
+ }
527
+
528
+ trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value);
529
+
530
+ return (uint64_t)value;
531
+}
532
+
533
+static void allwinner_i2c_write(void *opaque, hwaddr offset,
534
+ uint64_t value, unsigned size)
535
+{
536
+ AWI2CState *s = AW_I2C(opaque);
537
+
538
+ value &= 0xff;
539
+
540
+ trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value);
541
+
542
+ switch (offset) {
543
+ case TWI_ADDR_REG:
544
+ s->addr = (uint8_t)value;
545
+ break;
546
+ case TWI_XADDR_REG:
547
+ s->xaddr = (uint8_t)value;
548
+ break;
549
+ case TWI_DATA_REG:
550
+ /* If the device is in reset or not enabled, nothing to do */
551
+ if (allwinner_i2c_is_reset(s) || (!allwinner_i2c_bus_is_enabled(s))) {
552
+ break;
553
+ }
554
+
555
+ s->data = value & TWI_DATA_MASK;
556
+
557
+ switch (STAT_TO_STA(s->stat)) {
558
+ case STAT_M_STA_TX:
559
+ case STAT_M_RSTA_TX:
560
+ /* Send address */
561
+ if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7),
562
+ extract32(s->data, 0, 1))) {
563
+ /* If non zero is returned, the address is not valid */
564
+ s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK);
565
+ } else {
566
+ /* Determine if read of write */
567
+ if (extract32(s->data, 0, 1)) {
568
+ s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK);
569
+ } else {
570
+ s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK);
571
+ }
572
+ allwinner_i2c_raise_interrupt(s);
573
+ }
574
+ break;
575
+ case STAT_M_ADDR_WR_ACK:
576
+ case STAT_M_DATA_TX_ACK:
577
+ if (i2c_send(s->bus, s->data)) {
578
+ /* If the target return non zero then end the transfer */
579
+ s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK);
580
+ i2c_end_transfer(s->bus);
581
+ } else {
582
+ s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK);
583
+ allwinner_i2c_raise_interrupt(s);
584
+ }
585
+ break;
586
+ default:
587
+ break;
588
+ }
589
+ break;
590
+ case TWI_CNTR_REG:
591
+ if (!allwinner_i2c_is_reset(s)) {
592
+ /* Do something only if not in software reset */
593
+ s->cntr = value & TWI_CNTR_MASK;
594
+
595
+ /* Check if start condition should be sent */
596
+ if (s->cntr & TWI_CNTR_M_STA) {
597
+ /* Update status */
598
+ if (STAT_TO_STA(s->stat) == STAT_IDLE) {
599
+ /* Send start condition */
600
+ s->stat = STAT_FROM_STA(STAT_M_STA_TX);
601
+ } else {
602
+ /* Send repeated start condition */
603
+ s->stat = STAT_FROM_STA(STAT_M_RSTA_TX);
604
+ }
605
+ /* Clear start condition */
606
+ s->cntr &= ~TWI_CNTR_M_STA;
607
+ }
608
+ if (s->cntr & TWI_CNTR_M_STP) {
609
+ /* Update status */
610
+ i2c_end_transfer(s->bus);
611
+ s->stat = STAT_FROM_STA(STAT_IDLE);
612
+ s->cntr &= ~TWI_CNTR_M_STP;
613
+ }
614
+ if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
615
+ /* Interrupt flag cleared */
616
+ qemu_irq_lower(s->irq);
617
+ }
618
+ if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
619
+ if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
620
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
621
+ }
622
+ } else {
623
+ if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) {
624
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
625
+ }
626
+ }
627
+ allwinner_i2c_raise_interrupt(s);
628
+
629
+ }
630
+ break;
631
+ case TWI_CCR_REG:
632
+ s->ccr = value & TWI_CCR_MASK;
633
+ break;
634
+ case TWI_SRST_REG:
635
+ if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) {
636
+ /* Perform reset */
637
+ allwinner_i2c_reset_hold(OBJECT(s));
638
+ }
639
+ s->srst = value & TWI_SRST_MASK;
640
+ break;
641
+ case TWI_EFR_REG:
642
+ s->efr = value & TWI_EFR_MASK;
643
+ break;
644
+ case TWI_LCR_REG:
645
+ s->lcr = value & TWI_LCR_MASK;
646
+ break;
647
+ default:
648
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
649
+ HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
650
+ break;
651
+ }
652
+}
653
+
654
+static const MemoryRegionOps allwinner_i2c_ops = {
655
+ .read = allwinner_i2c_read,
656
+ .write = allwinner_i2c_write,
657
+ .valid.min_access_size = 1,
658
+ .valid.max_access_size = 4,
659
+ .endianness = DEVICE_NATIVE_ENDIAN,
660
+};
661
+
662
+static const VMStateDescription allwinner_i2c_vmstate = {
663
+ .name = TYPE_AW_I2C,
664
+ .version_id = 1,
665
+ .minimum_version_id = 1,
666
+ .fields = (VMStateField[]) {
667
+ VMSTATE_UINT8(addr, AWI2CState),
668
+ VMSTATE_UINT8(xaddr, AWI2CState),
669
+ VMSTATE_UINT8(data, AWI2CState),
670
+ VMSTATE_UINT8(cntr, AWI2CState),
671
+ VMSTATE_UINT8(ccr, AWI2CState),
672
+ VMSTATE_UINT8(srst, AWI2CState),
673
+ VMSTATE_UINT8(efr, AWI2CState),
674
+ VMSTATE_UINT8(lcr, AWI2CState),
675
+ VMSTATE_END_OF_LIST()
676
+ }
677
+};
678
+
679
+static void allwinner_i2c_realize(DeviceState *dev, Error **errp)
680
+{
681
+ AWI2CState *s = AW_I2C(dev);
682
+
683
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s,
684
+ TYPE_AW_I2C, AW_I2C_MEM_SIZE);
685
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
686
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
687
+ s->bus = i2c_init_bus(dev, "i2c");
688
+}
689
+
690
+static void allwinner_i2c_class_init(ObjectClass *klass, void *data)
691
+{
692
+ DeviceClass *dc = DEVICE_CLASS(klass);
693
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
694
+
695
+ rc->phases.hold = allwinner_i2c_reset_hold;
696
+ dc->vmsd = &allwinner_i2c_vmstate;
697
+ dc->realize = allwinner_i2c_realize;
698
+ dc->desc = "Allwinner I2C Controller";
699
+}
700
+
701
+static const TypeInfo allwinner_i2c_type_info = {
702
+ .name = TYPE_AW_I2C,
703
+ .parent = TYPE_SYS_BUS_DEVICE,
704
+ .instance_size = sizeof(AWI2CState),
705
+ .class_init = allwinner_i2c_class_init,
706
+};
707
+
708
+static void allwinner_i2c_register_types(void)
709
+{
710
+ type_register_static(&allwinner_i2c_type_info);
711
+}
712
+
713
+type_init(allwinner_i2c_register_types)
714
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
715
index XXXXXXX..XXXXXXX 100644
716
--- a/hw/arm/Kconfig
717
+++ b/hw/arm/Kconfig
718
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
719
select ALLWINNER_A10_CCM
720
select ALLWINNER_A10_DRAMC
721
select ALLWINNER_EMAC
722
+ select ALLWINNER_I2C
723
select SERIAL
724
select UNIMP
725
726
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
727
bool
728
select ALLWINNER_A10_PIT
729
select ALLWINNER_SUN8I_EMAC
730
+ select ALLWINNER_I2C
731
select SERIAL
732
select ARM_TIMER
733
select ARM_GIC
734
diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
735
index XXXXXXX..XXXXXXX 100644
736
--- a/hw/i2c/Kconfig
737
+++ b/hw/i2c/Kconfig
738
@@ -XXX,XX +XXX,XX @@ config MPC_I2C
739
bool
740
select I2C
741
742
+config ALLWINNER_I2C
743
+ bool
744
+ select I2C
745
+
746
config PCA954X
747
bool
748
select I2C
749
diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build
750
index XXXXXXX..XXXXXXX 100644
751
--- a/hw/i2c/meson.build
752
+++ b/hw/i2c/meson.build
753
@@ -XXX,XX +XXX,XX @@ i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c'))
754
i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c'))
755
i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c'))
756
i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c'))
757
+i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
758
i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
759
i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
760
i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
761
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
762
index XXXXXXX..XXXXXXX 100644
763
--- a/hw/i2c/trace-events
764
+++ b/hw/i2c/trace-events
765
@@ -XXX,XX +XXX,XX @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0
766
i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
767
i2c_ack(void) ""
768
769
+# allwinner_i2c.c
770
+
771
+allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64
772
+allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64
773
+
774
# aspeed_i2c.c
775
776
aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x"
777
--
778
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
This patch adds minimal support for AXP-209 PMU.
4
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
5
the chip ID register, reset values for two more registers used by A10
6
U-Boot SPL are covered.
7
8
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
9
Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/misc/axp209.c | 238 +++++++++++++++++++++++++++++++++++++++++++
14
MAINTAINERS | 2 +
15
hw/misc/Kconfig | 4 +
16
hw/misc/meson.build | 1 +
17
hw/misc/trace-events | 5 +
18
5 files changed, 250 insertions(+)
19
create mode 100644 hw/misc/axp209.c
20
21
diff --git a/hw/misc/axp209.c b/hw/misc/axp209.c
22
new file mode 100644
23
index XXXXXXX..XXXXXXX
24
--- /dev/null
25
+++ b/hw/misc/axp209.c
26
@@ -XXX,XX +XXX,XX @@
27
+/*
28
+ * AXP-209 PMU Emulation
29
+ *
30
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
31
+ *
32
+ * Permission is hereby granted, free of charge, to any person obtaining a
33
+ * copy of this software and associated documentation files (the "Software"),
34
+ * to deal in the Software without restriction, including without limitation
35
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
36
+ * and/or sell copies of the Software, and to permit persons to whom the
37
+ * Software is furnished to do so, subject to the following conditions:
38
+ *
39
+ * The above copyright notice and this permission notice shall be included in
40
+ * all copies or substantial portions of the Software.
41
+ *
42
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
45
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
46
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
47
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
48
+ * DEALINGS IN THE SOFTWARE.
49
+ *
50
+ * SPDX-License-Identifier: MIT
51
+ */
52
+
53
+#include "qemu/osdep.h"
54
+#include "qemu/log.h"
55
+#include "trace.h"
56
+#include "hw/i2c/i2c.h"
57
+#include "migration/vmstate.h"
58
+
59
+#define TYPE_AXP209_PMU "axp209_pmu"
60
+
61
+#define AXP209(obj) \
62
+ OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU)
63
+
64
+/* registers */
65
+enum {
66
+ REG_POWER_STATUS = 0x0u,
67
+ REG_OPERATING_MODE,
68
+ REG_OTG_VBUS_STATUS,
69
+ REG_CHIP_VERSION,
70
+ REG_DATA_CACHE_0,
71
+ REG_DATA_CACHE_1,
72
+ REG_DATA_CACHE_2,
73
+ REG_DATA_CACHE_3,
74
+ REG_DATA_CACHE_4,
75
+ REG_DATA_CACHE_5,
76
+ REG_DATA_CACHE_6,
77
+ REG_DATA_CACHE_7,
78
+ REG_DATA_CACHE_8,
79
+ REG_DATA_CACHE_9,
80
+ REG_DATA_CACHE_A,
81
+ REG_DATA_CACHE_B,
82
+ REG_POWER_OUTPUT_CTRL = 0x12u,
83
+ REG_DC_DC2_OUT_V_CTRL = 0x23u,
84
+ REG_DC_DC2_DVS_CTRL = 0x25u,
85
+ REG_DC_DC3_OUT_V_CTRL = 0x27u,
86
+ REG_LDO2_4_OUT_V_CTRL,
87
+ REG_LDO3_OUT_V_CTRL,
88
+ REG_VBUS_CH_MGMT = 0x30u,
89
+ REG_SHUTDOWN_V_CTRL,
90
+ REG_SHUTDOWN_CTRL,
91
+ REG_CHARGE_CTRL_1,
92
+ REG_CHARGE_CTRL_2,
93
+ REG_SPARE_CHARGE_CTRL,
94
+ REG_PEK_KEY_CTRL,
95
+ REG_DC_DC_FREQ_SET,
96
+ REG_CHR_TEMP_TH_SET,
97
+ REG_CHR_HIGH_TEMP_TH_CTRL,
98
+ REG_IPSOUT_WARN_L1,
99
+ REG_IPSOUT_WARN_L2,
100
+ REG_DISCHR_TEMP_TH_SET,
101
+ REG_DISCHR_HIGH_TEMP_TH_CTRL,
102
+ REG_IRQ_BANK_1_CTRL = 0x40u,
103
+ REG_IRQ_BANK_2_CTRL,
104
+ REG_IRQ_BANK_3_CTRL,
105
+ REG_IRQ_BANK_4_CTRL,
106
+ REG_IRQ_BANK_5_CTRL,
107
+ REG_IRQ_BANK_1_STAT = 0x48u,
108
+ REG_IRQ_BANK_2_STAT,
109
+ REG_IRQ_BANK_3_STAT,
110
+ REG_IRQ_BANK_4_STAT,
111
+ REG_IRQ_BANK_5_STAT,
112
+ REG_ADC_ACIN_V_H = 0x56u,
113
+ REG_ADC_ACIN_V_L,
114
+ REG_ADC_ACIN_CURR_H,
115
+ REG_ADC_ACIN_CURR_L,
116
+ REG_ADC_VBUS_V_H,
117
+ REG_ADC_VBUS_V_L,
118
+ REG_ADC_VBUS_CURR_H,
119
+ REG_ADC_VBUS_CURR_L,
120
+ REG_ADC_INT_TEMP_H,
121
+ REG_ADC_INT_TEMP_L,
122
+ REG_ADC_TEMP_SENS_V_H = 0x62u,
123
+ REG_ADC_TEMP_SENS_V_L,
124
+ REG_ADC_BAT_V_H = 0x78u,
125
+ REG_ADC_BAT_V_L,
126
+ REG_ADC_BAT_DISCHR_CURR_H,
127
+ REG_ADC_BAT_DISCHR_CURR_L,
128
+ REG_ADC_BAT_CHR_CURR_H,
129
+ REG_ADC_BAT_CHR_CURR_L,
130
+ REG_ADC_IPSOUT_V_H,
131
+ REG_ADC_IPSOUT_V_L,
132
+ REG_DC_DC_MOD_SEL = 0x80u,
133
+ REG_ADC_EN_1,
134
+ REG_ADC_EN_2,
135
+ REG_ADC_SR_CTRL,
136
+ REG_ADC_IN_RANGE,
137
+ REG_GPIO1_ADC_IRQ_RISING_TH,
138
+ REG_GPIO1_ADC_IRQ_FALLING_TH,
139
+ REG_TIMER_CTRL = 0x8au,
140
+ REG_VBUS_CTRL_MON_SRP,
141
+ REG_OVER_TEMP_SHUTDOWN = 0x8fu,
142
+ REG_GPIO0_FEAT_SET,
143
+ REG_GPIO_OUT_HIGH_SET,
144
+ REG_GPIO1_FEAT_SET,
145
+ REG_GPIO2_FEAT_SET,
146
+ REG_GPIO_SIG_STATE_SET_MON,
147
+ REG_GPIO3_SET,
148
+ REG_COULOMB_CNTR_CTRL = 0xb8u,
149
+ REG_POWER_MEAS_RES,
150
+ NR_REGS
151
+};
152
+
153
+#define AXP209_CHIP_VERSION_ID (0x01)
154
+#define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16)
155
+#define AXP209_IRQ_BANK_1_CTRL_RESET (0xd8)
156
+
157
+/* A simple I2C slave which returns values of ID or CNT register. */
158
+typedef struct AXP209I2CState {
159
+ /*< private >*/
160
+ I2CSlave i2c;
161
+ /*< public >*/
162
+ uint8_t regs[NR_REGS]; /* peripheral registers */
163
+ uint8_t ptr; /* current register index */
164
+ uint8_t count; /* counter used for tx/rx */
165
+} AXP209I2CState;
166
+
167
+/* Reset all counters and load ID register */
168
+static void axp209_reset_enter(Object *obj, ResetType type)
169
+{
170
+ AXP209I2CState *s = AXP209(obj);
171
+
172
+ memset(s->regs, 0, NR_REGS);
173
+ s->ptr = 0;
174
+ s->count = 0;
175
+ s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID;
176
+ s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET;
177
+ s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET;
178
+}
179
+
180
+/* Handle events from master. */
181
+static int axp209_event(I2CSlave *i2c, enum i2c_event event)
182
+{
183
+ AXP209I2CState *s = AXP209(i2c);
184
+
185
+ s->count = 0;
186
+
187
+ return 0;
188
+}
189
+
190
+/* Called when master requests read */
191
+static uint8_t axp209_rx(I2CSlave *i2c)
192
+{
193
+ AXP209I2CState *s = AXP209(i2c);
194
+ uint8_t ret = 0xff;
195
+
196
+ if (s->ptr < NR_REGS) {
197
+ ret = s->regs[s->ptr++];
198
+ }
199
+
200
+ trace_axp209_rx(s->ptr - 1, ret);
201
+
202
+ return ret;
203
+}
204
+
205
+/*
206
+ * Called when master sends write.
207
+ * Update ptr with byte 0, then perform write with second byte.
208
+ */
209
+static int axp209_tx(I2CSlave *i2c, uint8_t data)
210
+{
211
+ AXP209I2CState *s = AXP209(i2c);
212
+
213
+ if (s->count == 0) {
214
+ /* Store register address */
215
+ s->ptr = data;
216
+ s->count++;
217
+ trace_axp209_select(data);
218
+ } else {
219
+ trace_axp209_tx(s->ptr, data);
220
+ if (s->ptr == REG_DC_DC2_OUT_V_CTRL) {
221
+ s->regs[s->ptr++] = data;
222
+ }
223
+ }
224
+
225
+ return 0;
226
+}
227
+
228
+static const VMStateDescription vmstate_axp209 = {
229
+ .name = TYPE_AXP209_PMU,
230
+ .version_id = 1,
231
+ .fields = (VMStateField[]) {
232
+ VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS),
233
+ VMSTATE_UINT8(count, AXP209I2CState),
234
+ VMSTATE_UINT8(ptr, AXP209I2CState),
235
+ VMSTATE_END_OF_LIST()
236
+ }
237
+};
238
+
239
+static void axp209_class_init(ObjectClass *oc, void *data)
240
+{
241
+ DeviceClass *dc = DEVICE_CLASS(oc);
242
+ I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
243
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
244
+
245
+ rc->phases.enter = axp209_reset_enter;
246
+ dc->vmsd = &vmstate_axp209;
247
+ isc->event = axp209_event;
248
+ isc->recv = axp209_rx;
249
+ isc->send = axp209_tx;
250
+}
251
+
252
+static const TypeInfo axp209_info = {
253
+ .name = TYPE_AXP209_PMU,
254
+ .parent = TYPE_I2C_SLAVE,
255
+ .instance_size = sizeof(AXP209I2CState),
256
+ .class_init = axp209_class_init
257
+};
258
+
259
+static void axp209_register_devices(void)
260
+{
261
+ type_register_static(&axp209_info);
262
+}
263
+
264
+type_init(axp209_register_devices);
265
diff --git a/MAINTAINERS b/MAINTAINERS
266
index XXXXXXX..XXXXXXX 100644
267
--- a/MAINTAINERS
268
+++ b/MAINTAINERS
269
@@ -XXX,XX +XXX,XX @@ ARM Machines
270
Allwinner-a10
271
M: Beniamino Galvani <b.galvani@gmail.com>
272
M: Peter Maydell <peter.maydell@linaro.org>
273
+R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
274
L: qemu-arm@nongnu.org
275
S: Odd Fixes
276
F: hw/*/allwinner*
277
F: include/hw/*/allwinner*
278
F: hw/arm/cubieboard.c
279
F: docs/system/arm/cubieboard.rst
280
+F: hw/misc/axp209.c
281
282
Allwinner-h3
283
M: Niek Linnenbank <nieklinnenbank@gmail.com>
284
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
285
index XXXXXXX..XXXXXXX 100644
286
--- a/hw/misc/Kconfig
287
+++ b/hw/misc/Kconfig
288
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10_CCM
289
config ALLWINNER_A10_DRAMC
290
bool
291
292
+config AXP209_PMU
293
+ bool
294
+ depends on I2C
295
+
296
source macio/Kconfig
297
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
298
index XXXXXXX..XXXXXXX 100644
299
--- a/hw/misc/meson.build
300
+++ b/hw/misc/meson.build
301
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'
302
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
303
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
304
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
305
+softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
306
softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
307
softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
308
softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
309
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
310
index XXXXXXX..XXXXXXX 100644
311
--- a/hw/misc/trace-events
312
+++ b/hw/misc/trace-events
313
@@ -XXX,XX +XXX,XX @@ allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%"
314
avr_power_read(uint8_t value) "power_reduc read value:%u"
315
avr_power_write(uint8_t value) "power_reduc write value:%u"
316
317
+# axp209.c
318
+axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
319
+axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
320
+axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
321
+
322
# eccmemctl.c
323
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
324
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
325
--
326
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus.
4
5
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20221226220303.14420-6-strahinja.p.jankovic@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/cubieboard.c | 6 ++++++
12
hw/arm/Kconfig | 1 +
13
2 files changed, 7 insertions(+)
14
15
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/cubieboard.c
18
+++ b/hw/arm/cubieboard.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/boards.h"
21
#include "hw/qdev-properties.h"
22
#include "hw/arm/allwinner-a10.h"
23
+#include "hw/i2c/i2c.h"
24
25
static struct arm_boot_info cubieboard_binfo = {
26
.loader_start = AW_A10_SDRAM_BASE,
27
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
28
BlockBackend *blk;
29
BusState *bus;
30
DeviceState *carddev;
31
+ I2CBus *i2c;
32
33
/* BIOS is not supported by this board */
34
if (machine->firmware) {
35
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
36
exit(1);
37
}
38
39
+ /* Connect AXP 209 */
40
+ i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c"));
41
+ i2c_slave_create_simple(i2c, "axp209_pmu", 0x34);
42
+
43
/* Retrieve SD bus */
44
di = drive_get(IF_SD, 0, 0);
45
blk = di ? blk_by_legacy_dinfo(di) : NULL;
46
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/Kconfig
49
+++ b/hw/arm/Kconfig
50
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
51
select ALLWINNER_A10_DRAMC
52
select ALLWINNER_EMAC
53
select ALLWINNER_I2C
54
+ select AXP209_PMU
55
select SERIAL
56
select UNIMP
57
58
--
59
2.34.1
60
61
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
This patch enables copying of SPL from MMC if `-kernel` parameter is not
4
passed when starting QEMU. SPL is copied to SRAM_A.
5
6
The approach is reused from Allwinner H3 implementation.
7
8
Tested with Armbian and custom Yocto image.
9
10
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
11
12
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Message-id: 20221226220303.14420-7-strahinja.p.jankovic@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/allwinner-a10.h | 21 +++++++++++++++++++++
17
hw/arm/allwinner-a10.c | 18 ++++++++++++++++++
18
hw/arm/cubieboard.c | 5 +++++
19
3 files changed, 44 insertions(+)
20
21
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/allwinner-a10.h
24
+++ b/include/hw/arm/allwinner-a10.h
25
@@ -XXX,XX +XXX,XX @@
26
#include "hw/misc/allwinner-a10-ccm.h"
27
#include "hw/misc/allwinner-a10-dramc.h"
28
#include "hw/i2c/allwinner-i2c.h"
29
+#include "sysemu/block-backend.h"
30
31
#include "target/arm/cpu.h"
32
#include "qom/object.h"
33
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
34
OHCISysBusState ohci[AW_A10_NUM_USB];
35
};
36
37
+/**
38
+ * Emulate Boot ROM firmware setup functionality.
39
+ *
40
+ * A real Allwinner A10 SoC contains a Boot ROM
41
+ * which is the first code that runs right after
42
+ * the SoC is powered on. The Boot ROM is responsible
43
+ * for loading user code (e.g. a bootloader) from any
44
+ * of the supported external devices and writing the
45
+ * downloaded code to internal SRAM. After loading the SoC
46
+ * begins executing the code written to SRAM.
47
+ *
48
+ * This function emulates the Boot ROM by copying 32 KiB
49
+ * of data at offset 8 KiB from the given block device and writes it to
50
+ * the start of the first internal SRAM memory.
51
+ *
52
+ * @s: Allwinner A10 state object pointer
53
+ * @blk: Block backend device object pointer
54
+ */
55
+void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk);
56
+
57
#endif
58
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/allwinner-a10.c
61
+++ b/hw/arm/allwinner-a10.c
62
@@ -XXX,XX +XXX,XX @@
63
#include "sysemu/sysemu.h"
64
#include "hw/boards.h"
65
#include "hw/usb/hcd-ohci.h"
66
+#include "hw/loader.h"
67
68
+#define AW_A10_SRAM_A_BASE 0x00000000
69
#define AW_A10_DRAMC_BASE 0x01c01000
70
#define AW_A10_MMC0_BASE 0x01c0f000
71
#define AW_A10_CCM_BASE 0x01c20000
72
@@ -XXX,XX +XXX,XX @@
73
#define AW_A10_RTC_BASE 0x01c20d00
74
#define AW_A10_I2C0_BASE 0x01c2ac00
75
76
+void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
77
+{
78
+ const int64_t rom_size = 32 * KiB;
79
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
80
+
81
+ if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
82
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
83
+ __func__);
84
+ return;
85
+ }
86
+
87
+ rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
88
+ rom_size, AW_A10_SRAM_A_BASE,
89
+ NULL, NULL, NULL, NULL, false);
90
+}
91
+
92
static void aw_a10_init(Object *obj)
93
{
94
AwA10State *s = AW_A10(obj);
95
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/arm/cubieboard.c
98
+++ b/hw/arm/cubieboard.c
99
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
100
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
101
machine->ram);
102
103
+ /* Load target kernel or start using BootROM */
104
+ if (!machine->kernel_filename && blk && blk_is_available(blk)) {
105
+ /* Use Boot ROM to copy data from SD card to SRAM */
106
+ allwinner_a10_bootrom_setup(a10, blk);
107
+ }
108
/* TODO create and connect IDE devices for ide_drive_get() */
109
110
cubieboard_binfo.ram_size = machine->ram_size;
111
--
112
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
Cubieboard now can boot directly from SD card, without the need to pass
4
`-kernel` parameter. Update Avocado tests to cover this functionality.
5
6
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
7
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
tests/avocado/boot_linux_console.py | 47 +++++++++++++++++++++++++++++
13
1 file changed, 47 insertions(+)
14
15
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tests/avocado/boot_linux_console.py
18
+++ b/tests/avocado/boot_linux_console.py
19
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
20
'sda')
21
# cubieboard's reboot is not functioning; omit reboot test.
22
23
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
24
+ def test_arm_cubieboard_openwrt_22_03_2(self):
25
+ """
26
+ :avocado: tags=arch:arm
27
+ :avocado: tags=machine:cubieboard
28
+ :avocado: tags=device:sd
29
+ """
30
+
31
+ # This test download a 7.5 MiB compressed image and expand it
32
+ # to 126 MiB.
33
+ image_url = ('https://downloads.openwrt.org/releases/22.03.2/targets/'
34
+ 'sunxi/cortexa8/openwrt-22.03.2-sunxi-cortexa8-'
35
+ 'cubietech_a10-cubieboard-ext4-sdcard.img.gz')
36
+ image_hash = ('94b5ecbfbc0b3b56276e5146b899eafa'
37
+ '2ac5dc2d08733d6705af9f144f39f554')
38
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash,
39
+ algorithm='sha256')
40
+ image_path = archive.extract(image_path_gz, self.workdir)
41
+ image_pow2ceil_expand(image_path)
42
+
43
+ self.vm.set_console()
44
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
45
+ '-nic', 'user',
46
+ '-no-reboot')
47
+ self.vm.launch()
48
+
49
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
50
+ 'usbcore.nousb '
51
+ 'noreboot')
52
+
53
+ self.wait_for_console_pattern('U-Boot SPL')
54
+
55
+ interrupt_interactive_console_until_pattern(
56
+ self, 'Hit any key to stop autoboot:', '=>')
57
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
58
+ kernel_command_line + "'", '=>')
59
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
60
+
61
+ self.wait_for_console_pattern(
62
+ 'Please press Enter to activate this console.')
63
+
64
+ exec_command_and_wait_for_pattern(self, ' ', 'root@')
65
+
66
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
67
+ 'Allwinner sun4i/sun5i')
68
+ # cubieboard's reboot is not functioning; omit reboot test.
69
+
70
@skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
71
def test_arm_quanta_gsj(self):
72
"""
73
--
74
2.34.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Don't dereference CPUTLBEntryFull until we verify that
4
the page is valid. Move the other user-only info field
5
updates after the valid check to match.
6
7
Cc: qemu-stable@nongnu.org
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1412
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20230104190056.305143-1-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/sve_helper.c | 14 +++++++++-----
15
1 file changed, 9 insertions(+), 5 deletions(-)
16
17
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/sve_helper.c
20
+++ b/target/arm/sve_helper.c
21
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
22
#ifdef CONFIG_USER_ONLY
23
flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
24
&info->host, retaddr);
25
- memset(&info->attrs, 0, sizeof(info->attrs));
26
- /* Require both ANON and MTE; see allocation_tag_mem(). */
27
- info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
28
#else
29
CPUTLBEntryFull *full;
30
flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
31
&info->host, &full, retaddr);
32
- info->attrs = full->attrs;
33
- info->tagged = full->pte_attrs == 0xf0;
34
#endif
35
info->flags = flags;
36
37
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
38
return false;
39
}
40
41
+#ifdef CONFIG_USER_ONLY
42
+ memset(&info->attrs, 0, sizeof(info->attrs));
43
+ /* Require both ANON and MTE; see allocation_tag_mem(). */
44
+ info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
45
+#else
46
+ info->attrs = full->attrs;
47
+ info->tagged = full->pte_attrs == 0xf0;
48
+#endif
49
+
50
/* Ensure that info->host[] is relative to addr, not addr + mem_off. */
51
info->host -= mem_off;
52
return true;
53
--
54
2.34.1
55
56
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since pxa255_init() must map the device in the system memory,
4
there is no point in passing get_system_memory() by argument.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109115316.2235-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/pxa.h | 2 +-
12
hw/arm/gumstix.c | 3 +--
13
hw/arm/pxa2xx.c | 4 +++-
14
hw/arm/tosa.c | 2 +-
15
4 files changed, 6 insertions(+), 5 deletions(-)
16
17
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/pxa.h
20
+++ b/include/hw/arm/pxa.h
21
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
22
23
PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
24
const char *revision);
25
-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
26
+PXA2xxState *pxa255_init(unsigned int sdram_size);
27
28
#endif /* PXA_H */
29
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/gumstix.c
32
+++ b/hw/arm/gumstix.c
33
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
34
{
35
PXA2xxState *cpu;
36
DriveInfo *dinfo;
37
- MemoryRegion *address_space_mem = get_system_memory();
38
39
uint32_t connex_rom = 0x01000000;
40
uint32_t connex_ram = 0x04000000;
41
42
- cpu = pxa255_init(address_space_mem, connex_ram);
43
+ cpu = pxa255_init(connex_ram);
44
45
dinfo = drive_get(IF_PFLASH, 0, 0);
46
if (!dinfo && !qtest_enabled()) {
47
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/pxa2xx.c
50
+++ b/hw/arm/pxa2xx.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "qemu/error-report.h"
53
#include "qemu/module.h"
54
#include "qapi/error.h"
55
+#include "exec/address-spaces.h"
56
#include "cpu.h"
57
#include "hw/sysbus.h"
58
#include "migration/vmstate.h"
59
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
60
}
61
62
/* Initialise a PXA255 integrated chip (ARM based core). */
63
-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
64
+PXA2xxState *pxa255_init(unsigned int sdram_size)
65
{
66
+ MemoryRegion *address_space = get_system_memory();
67
PXA2xxState *s;
68
int i;
69
DriveInfo *dinfo;
70
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/tosa.c
73
+++ b/hw/arm/tosa.c
74
@@ -XXX,XX +XXX,XX @@ static void tosa_init(MachineState *machine)
75
TC6393xbState *tmio;
76
DeviceState *scp0, *scp1;
77
78
- mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
79
+ mpu = pxa255_init(tosa_binfo.ram_size);
80
81
memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
82
memory_region_add_subregion(address_space_mem, 0, rom);
83
--
84
2.34.1
85
86
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since pxa270_init() must map the device in the system memory,
4
there is no point in passing get_system_memory() by argument.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109115316.2235-3-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/pxa.h | 3 +--
12
hw/arm/gumstix.c | 3 +--
13
hw/arm/mainstone.c | 10 ++++------
14
hw/arm/pxa2xx.c | 4 ++--
15
hw/arm/spitz.c | 6 ++----
16
hw/arm/z2.c | 3 +--
17
6 files changed, 11 insertions(+), 18 deletions(-)
18
19
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/pxa.h
22
+++ b/include/hw/arm/pxa.h
23
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
24
25
# define PA_FMT            "0x%08lx"
26
27
-PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
28
- const char *revision);
29
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
30
PXA2xxState *pxa255_init(unsigned int sdram_size);
31
32
#endif /* PXA_H */
33
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/gumstix.c
36
+++ b/hw/arm/gumstix.c
37
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
38
{
39
PXA2xxState *cpu;
40
DriveInfo *dinfo;
41
- MemoryRegion *address_space_mem = get_system_memory();
42
43
uint32_t verdex_rom = 0x02000000;
44
uint32_t verdex_ram = 0x10000000;
45
46
- cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
47
+ cpu = pxa270_init(verdex_ram, machine->cpu_type);
48
49
dinfo = drive_get(IF_PFLASH, 0, 0);
50
if (!dinfo && !qtest_enabled()) {
51
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/mainstone.c
54
+++ b/hw/arm/mainstone.c
55
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info mainstone_binfo = {
56
.ram_size = 0x04000000,
57
};
58
59
-static void mainstone_common_init(MemoryRegion *address_space_mem,
60
- MachineState *machine,
61
+static void mainstone_common_init(MachineState *machine,
62
enum mainstone_model_e model, int arm_id)
63
{
64
uint32_t sector_len = 256 * 1024;
65
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
66
MemoryRegion *rom = g_new(MemoryRegion, 1);
67
68
/* Setup CPU & memory */
69
- mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
70
- machine->cpu_type);
71
+ mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
72
memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
73
&error_fatal);
74
- memory_region_add_subregion(address_space_mem, 0, rom);
75
+ memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
76
77
/* There are two 32MiB flash devices on the board */
78
for (i = 0; i < 2; i ++) {
79
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
80
81
static void mainstone_init(MachineState *machine)
82
{
83
- mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
84
+ mainstone_common_init(machine, mainstone, 0x196);
85
}
86
87
static void mainstone2_machine_init(MachineClass *mc)
88
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/arm/pxa2xx.c
91
+++ b/hw/arm/pxa2xx.c
92
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_reset(void *opaque, int line, int level)
93
}
94
95
/* Initialise a PXA270 integrated chip (ARM based core). */
96
-PXA2xxState *pxa270_init(MemoryRegion *address_space,
97
- unsigned int sdram_size, const char *cpu_type)
98
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
99
{
100
+ MemoryRegion *address_space = get_system_memory();
101
PXA2xxState *s;
102
int i;
103
DriveInfo *dinfo;
104
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/arm/spitz.c
107
+++ b/hw/arm/spitz.c
108
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
109
SpitzMachineState *sms = SPITZ_MACHINE(machine);
110
enum spitz_model_e model = smc->model;
111
PXA2xxState *mpu;
112
- MemoryRegion *address_space_mem = get_system_memory();
113
MemoryRegion *rom = g_new(MemoryRegion, 1);
114
115
/* Setup CPU & memory */
116
- mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
117
- machine->cpu_type);
118
+ mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type);
119
sms->mpu = mpu;
120
121
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
122
123
memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
124
- memory_region_add_subregion(address_space_mem, 0, rom);
125
+ memory_region_add_subregion(get_system_memory(), 0, rom);
126
127
/* Setup peripherals */
128
spitz_keyboard_register(mpu);
129
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/arm/z2.c
132
+++ b/hw/arm/z2.c
133
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
134
135
static void z2_init(MachineState *machine)
136
{
137
- MemoryRegion *address_space_mem = get_system_memory();
138
uint32_t sector_len = 0x10000;
139
PXA2xxState *mpu;
140
DriveInfo *dinfo;
141
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
142
DeviceState *wm;
143
144
/* Setup CPU & memory */
145
- mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
146
+ mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
147
148
dinfo = drive_get(IF_PFLASH, 0, 0);
149
if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
150
--
151
2.34.1
152
153
diff view generated by jsdifflib
1
The Linux kernel has dropped support for allowing 32-bit Arm systems
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
to host KVM guests (kernel commit 541ad0150ca4aa663a2, which just
3
landed upstream in the 5.7 merge window). Mark QEMU's support for
4
this configuration as deprecated, so that we can delete that support
5
code in 5.2.
6
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add definitions for RAM / Flash / Flash blocksize.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-4-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
---
11
---
10
docs/system/deprecated.rst | 8 ++++++++
12
hw/arm/collie.c | 16 ++++++++++------
11
1 file changed, 8 insertions(+)
13
1 file changed, 10 insertions(+), 6 deletions(-)
12
14
13
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
15
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/deprecated.rst
17
--- a/hw/arm/collie.c
16
+++ b/docs/system/deprecated.rst
18
+++ b/hw/arm/collie.c
17
@@ -XXX,XX +XXX,XX @@ The ``compat`` property used to set backwards compatibility modes for
19
@@ -XXX,XX +XXX,XX @@
18
the processor has been deprecated. The ``max-cpu-compat`` property of
20
#include "cpu.h"
19
the ``pseries`` machine type should be used instead.
21
#include "qom/object.h"
20
22
21
+KVM guest support on 32-bit Arm hosts (since 5.0)
23
+#define RAM_SIZE (512 * MiB)
22
+'''''''''''''''''''''''''''''''''''''''''''''''''
24
+#define FLASH_SIZE (32 * MiB)
25
+#define FLASH_SECTOR_SIZE (64 * KiB)
23
+
26
+
24
+The Linux kernel has dropped support for allowing 32-bit Arm systems
27
struct CollieMachineState {
25
+to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
28
MachineState parent;
26
+its support for this configuration and will remove it in a future version.
29
27
+Running 32-bit guests on a 64-bit Arm host remains supported.
30
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
28
+
31
29
System emulator devices
32
static struct arm_boot_info collie_binfo = {
30
-----------------------
33
.loader_start = SA_SDCS0,
34
- .ram_size = 0x20000000,
35
+ .ram_size = RAM_SIZE,
36
};
37
38
static void collie_init(MachineState *machine)
39
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
40
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
41
42
dinfo = drive_get(IF_PFLASH, 0, 0);
43
- pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
44
+ pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
45
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
46
- 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
47
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
48
49
dinfo = drive_get(IF_PFLASH, 0, 1);
50
- pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000,
51
+ pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
52
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
53
- 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
54
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
55
56
sysbus_create_simple("scoop", 0x40800000, NULL);
57
58
@@ -XXX,XX +XXX,XX @@ static void collie_machine_class_init(ObjectClass *oc, void *data)
59
mc->init = collie_init;
60
mc->ignore_memory_transaction_failures = true;
61
mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
62
- mc->default_ram_size = 0x20000000;
63
+ mc->default_ram_size = RAM_SIZE;
64
mc->default_ram_id = "strongarm.sdram";
65
}
31
66
32
--
67
--
33
2.20.1
68
2.34.1
34
69
35
70
diff view generated by jsdifflib
1
The documentation of our -s and -gdb options is quite old; in
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
particular it still claims that it will cause QEMU to stop and wait
3
for the gdb connection, when this has not been true for some time:
4
you also need to pass -S if you want to make QEMU not launch the
5
guest on startup.
6
2
7
Improve the documentation to mention this requirement in the
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
executable's --help output, the documentation of the -gdb option in
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
the manual, and in the "GDB usage" chapter.
5
Message-id: 20230109115316.2235-5-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/collie.c | 17 +++++++----------
9
1 file changed, 7 insertions(+), 10 deletions(-)
10
10
11
Includes some minor tweaks to these paragraphs of documentation
11
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
12
since I was editing them anyway (such as dropping the description
13
of our gdb support as "primitive").
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
19
Message-id: 20200403094014.9589-1-peter.maydell@linaro.org
20
---
21
docs/system/gdb.rst | 22 +++++++++++++++-------
22
qemu-options.hx | 24 ++++++++++++++++++------
23
2 files changed, 33 insertions(+), 13 deletions(-)
24
25
diff --git a/docs/system/gdb.rst b/docs/system/gdb.rst
26
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
27
--- a/docs/system/gdb.rst
13
--- a/hw/arm/collie.c
28
+++ b/docs/system/gdb.rst
14
+++ b/hw/arm/collie.c
29
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info collie_binfo = {
30
GDB usage
16
31
---------
17
static void collie_init(MachineState *machine)
32
18
{
33
-QEMU has a primitive support to work with gdb, so that you can do
19
- DriveInfo *dinfo;
34
-'Ctrl-C' while the virtual machine is running and inspect its state.
20
MachineClass *mc = MACHINE_GET_CLASS(machine);
35
+QEMU supports working with gdb via gdb's remote-connection facility
21
CollieMachineState *cms = COLLIE_MACHINE(machine);
36
+(the "gdbstub"). This allows you to debug guest code in the same
22
37
+way that you might with a low-level debug facility like JTAG
23
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
38
+on real hardware. You can stop and start the virtual machine,
24
39
+examine state like registers and memory, and set breakpoints and
25
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
40
+watchpoints.
26
41
27
- dinfo = drive_get(IF_PFLASH, 0, 0);
42
-In order to use gdb, launch QEMU with the '-s' option. It will wait for
28
- pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
43
-a gdb connection:
29
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
44
+In order to use gdb, launch QEMU with the ``-s`` and ``-S`` options.
30
- FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
45
+The ``-s`` option will make QEMU listen for an incoming connection
31
-
46
+from gdb on TCP port 1234, and ``-S`` will make QEMU not start the
32
- dinfo = drive_get(IF_PFLASH, 0, 1);
47
+guest until you tell it to from gdb. (If you want to specify which
33
- pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
48
+TCP port to use or to use something other than TCP for the gdbstub
34
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
49
+connection, use the ``-gdb dev`` option instead of ``-s``.)
35
- FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
50
36
+ for (unsigned i = 0; i < 2; i++) {
51
.. parsed-literal::
37
+ DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i);
52
38
+ pflash_cfi01_register(i ? SA_CS1 : SA_CS0,
53
- |qemu_system| -s -kernel bzImage -hda rootdisk.img -append "root=/dev/hda"
39
+ i ? "collie.fl2" : "collie.fl1", FLASH_SIZE,
54
- Connected to host network interface: tun0
40
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
55
- Waiting gdb connection on port 1234
41
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
56
+ |qemu_system| -s -S -kernel bzImage -hda rootdisk.img -append "root=/dev/hda"
42
+ }
57
+
43
58
+QEMU will launch but will silently wait for gdb to connect.
44
sysbus_create_simple("scoop", 0x40800000, NULL);
59
60
Then launch gdb on the 'vmlinux' executable::
61
62
diff --git a/qemu-options.hx b/qemu-options.hx
63
index XXXXXXX..XXXXXXX 100644
64
--- a/qemu-options.hx
65
+++ b/qemu-options.hx
66
@@ -XXX,XX +XXX,XX @@ SRST
67
ERST
68
69
DEF("gdb", HAS_ARG, QEMU_OPTION_gdb, \
70
- "-gdb dev wait for gdb connection on 'dev'\n", QEMU_ARCH_ALL)
71
+ "-gdb dev accept gdb connection on 'dev'. (QEMU defaults to starting\n"
72
+ " the guest without waiting for gdb to connect; use -S too\n"
73
+ " if you want it to not start execution.)\n",
74
+ QEMU_ARCH_ALL)
75
SRST
76
``-gdb dev``
77
- Wait for gdb connection on device dev (see
78
- :ref:`gdb_005fusage`). Typical connections will likely be
79
- TCP-based, but also UDP, pseudo TTY, or even stdio are reasonable
80
- use case. The latter is allowing to start QEMU from within gdb and
81
- establish the connection via a pipe:
82
+ Accept a gdb connection on device dev (see
83
+ :ref:`gdb_005fusage`). Note that this option does not pause QEMU
84
+ execution -- if you want QEMU to not start the guest until you
85
+ connect with gdb and issue a ``continue`` command, you will need to
86
+ also pass the ``-S`` option to QEMU.
87
+
88
+ The most usual configuration is to listen on a local TCP socket::
89
+
90
+ -gdb tcp::3117
91
+
92
+ but you can specify other backends; UDP, pseudo TTY, or even stdio
93
+ are all reasonable use cases. For example, a stdio connection
94
+ allows you to start QEMU from within gdb and establish the
95
+ connection via a pipe:
96
97
.. parsed-literal::
98
45
99
--
46
--
100
2.20.1
47
2.34.1
101
48
102
49
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Add a comment describing the Connex uses a Numonyx RC28F128J3F75
4
flash, and the Verdex uses a Micron RC28F256P30TFA.
5
6
Correct the Verdex machine description (we model the 'Pro' board).
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230109115316.2235-6-philmd@linaro.org
11
Message-Id: <20200223231044.8003-3-philmd@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/gumstix.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/gumstix.c
20
+++ b/hw/arm/gumstix.c
21
@@ -XXX,XX +XXX,XX @@
22
* Contributions after 2012-01-13 are licensed under the terms of the
23
* GNU GPL, version 2 or (at your option) any later version.
24
*/
25
-
26
+
27
/*
28
* Example usage:
29
*
30
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
31
exit(1);
32
}
33
34
+ /* Numonyx RC28F128J3F75 */
35
if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
36
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
37
sector_len, 2, 0, 0, 0, 0, 0)) {
38
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
39
exit(1);
40
}
41
42
+ /* Micron RC28F256P30TFA */
43
if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
44
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
45
sector_len, 2, 0, 0, 0, 0, 0)) {
46
@@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data)
47
{
48
MachineClass *mc = MACHINE_CLASS(oc);
49
50
- mc->desc = "Gumstix Verdex (PXA270)";
51
+ mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
52
mc->init = verdex_init;
53
mc->ignore_memory_transaction_failures = true;
54
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
55
--
56
2.34.1
57
58
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add definitions for RAM / Flash / Flash blocksize.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-7-philmd@linaro.org
10
Message-Id: <20200223231044.8003-3-philmd@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/gumstix.c | 27 ++++++++++++++-------------
14
1 file changed, 14 insertions(+), 13 deletions(-)
15
16
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/gumstix.c
19
+++ b/hw/arm/gumstix.c
20
@@ -XXX,XX +XXX,XX @@
21
*/
22
23
#include "qemu/osdep.h"
24
+#include "qemu/units.h"
25
#include "qemu/error-report.h"
26
#include "hw/arm/pxa.h"
27
#include "net/net.h"
28
@@ -XXX,XX +XXX,XX @@
29
#include "sysemu/qtest.h"
30
#include "cpu.h"
31
32
-static const int sector_len = 128 * 1024;
33
+#define CONNEX_FLASH_SIZE (16 * MiB)
34
+#define CONNEX_RAM_SIZE (64 * MiB)
35
+
36
+#define VERDEX_FLASH_SIZE (32 * MiB)
37
+#define VERDEX_RAM_SIZE (256 * MiB)
38
+
39
+#define FLASH_SECTOR_SIZE (128 * KiB)
40
41
static void connex_init(MachineState *machine)
42
{
43
PXA2xxState *cpu;
44
DriveInfo *dinfo;
45
46
- uint32_t connex_rom = 0x01000000;
47
- uint32_t connex_ram = 0x04000000;
48
-
49
- cpu = pxa255_init(connex_ram);
50
+ cpu = pxa255_init(CONNEX_RAM_SIZE);
51
52
dinfo = drive_get(IF_PFLASH, 0, 0);
53
if (!dinfo && !qtest_enabled()) {
54
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
55
}
56
57
/* Numonyx RC28F128J3F75 */
58
- if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
59
+ if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
60
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
61
- sector_len, 2, 0, 0, 0, 0, 0)) {
62
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
63
error_report("Error registering flash memory");
64
exit(1);
65
}
66
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
67
PXA2xxState *cpu;
68
DriveInfo *dinfo;
69
70
- uint32_t verdex_rom = 0x02000000;
71
- uint32_t verdex_ram = 0x10000000;
72
-
73
- cpu = pxa270_init(verdex_ram, machine->cpu_type);
74
+ cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type);
75
76
dinfo = drive_get(IF_PFLASH, 0, 0);
77
if (!dinfo && !qtest_enabled()) {
78
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
79
}
80
81
/* Micron RC28F256P30TFA */
82
- if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
83
+ if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
84
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
85
- sector_len, 2, 0, 0, 0, 0, 0)) {
86
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
87
error_report("Error registering flash memory");
88
exit(1);
89
}
90
--
91
2.34.1
92
93
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add the FLASH_SECTOR_SIZE definition.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-8-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/mainstone.c | 18 ++++++++++--------
13
1 file changed, 10 insertions(+), 8 deletions(-)
14
15
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mainstone.c
18
+++ b/hw/arm/mainstone.c
19
@@ -XXX,XX +XXX,XX @@
20
* GNU GPL, version 2 or (at your option) any later version.
21
*/
22
#include "qemu/osdep.h"
23
+#include "qemu/units.h"
24
#include "qemu/error-report.h"
25
#include "qapi/error.h"
26
#include "hw/arm/pxa.h"
27
@@ -XXX,XX +XXX,XX @@ static const struct keymap map[0xE0] = {
28
29
enum mainstone_model_e { mainstone };
30
31
-#define MAINSTONE_RAM    0x04000000
32
-#define MAINSTONE_ROM    0x00800000
33
-#define MAINSTONE_FLASH    0x02000000
34
+#define MAINSTONE_RAM_SIZE (64 * MiB)
35
+#define MAINSTONE_ROM_SIZE (8 * MiB)
36
+#define MAINSTONE_FLASH_SIZE (32 * MiB)
37
38
static struct arm_boot_info mainstone_binfo = {
39
.loader_start = PXA2XX_SDRAM_BASE,
40
- .ram_size = 0x04000000,
41
+ .ram_size = MAINSTONE_RAM_SIZE,
42
};
43
44
+#define FLASH_SECTOR_SIZE (256 * KiB)
45
+
46
static void mainstone_common_init(MachineState *machine,
47
enum mainstone_model_e model, int arm_id)
48
{
49
- uint32_t sector_len = 256 * 1024;
50
hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
51
PXA2xxState *mpu;
52
DeviceState *mst_irq;
53
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
54
55
/* Setup CPU & memory */
56
mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
57
- memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
58
+ memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
59
&error_fatal);
60
memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
61
62
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
63
dinfo = drive_get(IF_PFLASH, 0, i);
64
if (!pflash_cfi01_register(mainstone_flash_base[i],
65
i ? "mainstone.flash1" : "mainstone.flash0",
66
- MAINSTONE_FLASH,
67
+ MAINSTONE_FLASH_SIZE,
68
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
69
- sector_len, 4, 0, 0, 0, 0, 0)) {
70
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
71
error_report("Error registering flash memory");
72
exit(1);
73
}
74
--
75
2.34.1
76
77
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add the FLASH_SECTOR_SIZE definition.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-9-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/musicpal.c | 9 ++++++---
13
1 file changed, 6 insertions(+), 3 deletions(-)
14
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/musicpal.c
18
+++ b/hw/arm/musicpal.c
19
@@ -XXX,XX +XXX,XX @@
20
*/
21
22
#include "qemu/osdep.h"
23
+#include "qemu/units.h"
24
#include "qapi/error.h"
25
#include "cpu.h"
26
#include "hw/sysbus.h"
27
@@ -XXX,XX +XXX,XX @@ static const TypeInfo musicpal_key_info = {
28
.class_init = musicpal_key_class_init,
29
};
30
31
+#define FLASH_SECTOR_SIZE (64 * KiB)
32
+
33
static struct arm_boot_info musicpal_binfo = {
34
.loader_start = 0x0,
35
.board_id = 0x20e,
36
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
37
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
38
39
flash_size = blk_getlength(blk);
40
- if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
41
- flash_size != 32*1024*1024) {
42
+ if (flash_size != 8 * MiB && flash_size != 16 * MiB &&
43
+ flash_size != 32 * MiB) {
44
error_report("Invalid flash image size");
45
exit(1);
46
}
47
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
48
*/
49
pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
50
"musicpal.flash", flash_size,
51
- blk, 0x10000,
52
+ blk, FLASH_SECTOR_SIZE,
53
MP_FLASH_SIZE_MAX / flash_size,
54
2, 0x00BF, 0x236D, 0x0000, 0x0000,
55
0x5555, 0x2AAA, 0);
56
--
57
2.34.1
58
59
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
The total_ram_v1/total_ram_v2 definitions were never used.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20230109115316.2235-10-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/omap_sx1.c | 2 --
11
1 file changed, 2 deletions(-)
12
13
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/omap_sx1.c
16
+++ b/hw/arm/omap_sx1.c
17
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
18
#define flash0_size    (16 * 1024 * 1024)
19
#define flash1_size    ( 8 * 1024 * 1024)
20
#define flash2_size    (32 * 1024 * 1024)
21
-#define total_ram_v1    (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
22
-#define total_ram_v2    (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
23
24
static struct arm_boot_info sx1_binfo = {
25
.loader_start = OMAP_EMIFF_BASE,
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
1
The target_flat.h file is a QEMU header, so we should include it using
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
quotes, not angle brackets.
3
2
4
Coverity otherwise is unable to find the header:
3
IEC binary prefixes ease code review: the unit is explicit.
5
4
6
"../linux-user/flatload.c", line 40: error #1712: cannot open source file
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
"target_flat.h"
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
#include <target_flat.h>
7
Message-id: 20230109115316.2235-11-philmd@linaro.org
9
^
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/omap_sx1.c | 33 +++++++++++++++++----------------
11
1 file changed, 17 insertions(+), 16 deletions(-)
10
12
11
because the relevant directory is only on the -iquote path, not the -I path.
13
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20200319193323.2038-5-peter.maydell@linaro.org
17
---
18
linux-user/flatload.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
20
21
diff --git a/linux-user/flatload.c b/linux-user/flatload.c
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/linux-user/flatload.c
15
--- a/hw/arm/omap_sx1.c
24
+++ b/linux-user/flatload.c
16
+++ b/hw/arm/omap_sx1.c
25
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@
26
18
* with this program; if not, see <http://www.gnu.org/licenses/>.
27
#include "qemu.h"
19
*/
28
#include "flat.h"
20
#include "qemu/osdep.h"
29
-#include <target_flat.h>
21
+#include "qemu/units.h"
30
+#include "target_flat.h"
22
#include "qapi/error.h"
31
23
#include "ui/console.h"
32
//#define DEBUG
24
#include "hw/arm/omap.h"
25
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
26
.endianness = DEVICE_NATIVE_ENDIAN,
27
};
28
29
-#define sdram_size    0x02000000
30
-#define sector_size    (128 * 1024)
31
-#define flash0_size    (16 * 1024 * 1024)
32
-#define flash1_size    ( 8 * 1024 * 1024)
33
-#define flash2_size    (32 * 1024 * 1024)
34
+#define SDRAM_SIZE (32 * MiB)
35
+#define SECTOR_SIZE (128 * KiB)
36
+#define FLASH0_SIZE (16 * MiB)
37
+#define FLASH1_SIZE (8 * MiB)
38
+#define FLASH2_SIZE (32 * MiB)
39
40
static struct arm_boot_info sx1_binfo = {
41
.loader_start = OMAP_EMIFF_BASE,
42
- .ram_size = sdram_size,
43
+ .ram_size = SDRAM_SIZE,
44
.board_id = 0x265,
45
};
46
47
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
48
static uint32_t cs3val = 0x00001139;
49
DriveInfo *dinfo;
50
int fl_idx;
51
- uint32_t flash_size = flash0_size;
52
+ uint32_t flash_size = FLASH0_SIZE;
53
54
if (machine->ram_size != mc->default_ram_size) {
55
char *sz = size_to_str(mc->default_ram_size);
56
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
57
}
58
59
if (version == 2) {
60
- flash_size = flash2_size;
61
+ flash_size = FLASH2_SIZE;
62
}
63
64
memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
65
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
66
if (!pflash_cfi01_register(OMAP_CS0_BASE,
67
"omap_sx1.flash0-1", flash_size,
68
blk_by_legacy_dinfo(dinfo),
69
- sector_size, 4, 0, 0, 0, 0, 0)) {
70
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
71
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
72
fl_idx);
73
}
74
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
75
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
76
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
77
memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
78
- flash1_size, &error_fatal);
79
+ FLASH1_SIZE, &error_fatal);
80
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
81
82
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
83
- "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
84
+ "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
85
memory_region_add_subregion(address_space,
86
- OMAP_CS1_BASE + flash1_size, &cs[1]);
87
+ OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
88
89
if (!pflash_cfi01_register(OMAP_CS1_BASE,
90
- "omap_sx1.flash1-1", flash1_size,
91
+ "omap_sx1.flash1-1", FLASH1_SIZE,
92
blk_by_legacy_dinfo(dinfo),
93
- sector_size, 4, 0, 0, 0, 0, 0)) {
94
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
95
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
96
fl_idx);
97
}
98
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
99
mc->init = sx1_init_v2;
100
mc->ignore_memory_transaction_failures = true;
101
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
102
- mc->default_ram_size = sdram_size;
103
+ mc->default_ram_size = SDRAM_SIZE;
104
mc->default_ram_id = "omap1.dram";
105
}
106
107
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
108
mc->init = sx1_init_v1;
109
mc->ignore_memory_transaction_failures = true;
110
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
111
- mc->default_ram_size = sdram_size;
112
+ mc->default_ram_size = SDRAM_SIZE;
113
mc->default_ram_id = "omap1.dram";
114
}
33
115
34
--
116
--
35
2.20.1
117
2.34.1
36
118
37
119
diff view generated by jsdifflib
1
Versions of Sphinx older than 1.6 can't build all of our documentation,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
because they are too picky about the syntax of the argument to the
3
option:: directive; see Sphinx bugs #646, #3366:
4
2
5
https://github.com/sphinx-doc/sphinx/issues/646
3
IEC binary prefixes ease code review: the unit is explicit.
6
https://github.com/sphinx-doc/sphinx/issues/3366
7
4
8
Trying to build with a 1.4.x Sphinx fails with
5
Add the FLASH_SECTOR_SIZE definition.
9
docs/system/images.rst:4: SEVERE: Duplicate ID: "cmdoption-qcow2-arg-encrypt"
10
and a 1.5.x Sphinx fails with
11
docs/system/invocation.rst:544: WARNING: Malformed option description '[enable=]PATTERN', should look like "opt", "-opt
12
args", "--opt args", "/opt args" or "+opt args"
13
6
14
Update our needs_sphinx setting to indicate that we require at least
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
1.6. This will allow configure to fall back to "don't build the
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
docs" rather than causing the build to fail entirely, which is
9
Message-id: 20230109115316.2235-12-philmd@linaro.org
17
probably what most users building on a host old enough to have such
18
an old Sphinx would want; if they do want the docs then they'll have
19
a useful indication of what they need to do (upgrade Sphinx!) rather
20
than a confusing error message.
21
22
In theory our distro support policy would suggest that we should
23
support building on the Sphinx shipped in those distros, but:
24
* EPEL7 has Sphinx 1.2.3 (which we've never supported!)
25
* Debian Stretch has Sphinx 1.4.8
26
27
Trying to get our docs to work with Sphinx 1.4 is not tractable
28
for the 5.0 release and I'm not sure it's worthwhile effort anyway;
29
at least with this change the build as a whole now succeeds.
30
31
Thanks to John Snow for doing the investigation and testing to
32
confirm what Sphinx versions fail in what ways and what distros
33
shipped what.
34
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
---
11
---
38
docs/conf.py | 6 ++++--
12
hw/arm/z2.c | 6 ++++--
39
1 file changed, 4 insertions(+), 2 deletions(-)
13
1 file changed, 4 insertions(+), 2 deletions(-)
40
14
41
diff --git a/docs/conf.py b/docs/conf.py
15
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
42
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
43
--- a/docs/conf.py
17
--- a/hw/arm/z2.c
44
+++ b/docs/conf.py
18
+++ b/hw/arm/z2.c
45
@@ -XXX,XX +XXX,XX @@ sys.path.insert(0, os.path.join(qemu_docdir, "sphinx"))
19
@@ -XXX,XX +XXX,XX @@
46
20
*/
47
# If your documentation needs a minimal Sphinx version, state it here.
21
48
#
22
#include "qemu/osdep.h"
49
-# 1.3 is where the 'alabaster' theme was shipped with Sphinx.
23
+#include "qemu/units.h"
50
-needs_sphinx = '1.3'
24
#include "hw/arm/pxa.h"
51
+# Sphinx 1.5 and earlier can't build our docs because they are too
25
#include "hw/arm/boot.h"
52
+# picky about the syntax of the argument to the option:: directive
26
#include "hw/i2c/i2c.h"
53
+# (see Sphinx bugs #646, #3366).
27
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
54
+needs_sphinx = '1.6'
28
.class_init = aer915_class_init,
55
29
};
56
# Add any Sphinx extension module names here, as strings. They can be
30
57
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
31
+#define FLASH_SECTOR_SIZE (64 * KiB)
32
+
33
static void z2_init(MachineState *machine)
34
{
35
- uint32_t sector_len = 0x10000;
36
PXA2xxState *mpu;
37
DriveInfo *dinfo;
38
void *z2_lcd;
39
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
40
dinfo = drive_get(IF_PFLASH, 0, 0);
41
if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
42
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
43
- sector_len, 4, 0, 0, 0, 0, 0)) {
44
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
45
error_report("Error registering flash memory");
46
exit(1);
47
}
58
--
48
--
59
2.20.1
49
2.34.1
60
50
61
51
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Upon introduction in commit b8433303fb ("Set proper device-width
4
for vexpress flash"), ve_pflash_cfi01_register() was calling
5
qdev_init_nofail() which can not fail. This call was later
6
converted with a script to use &error_fatal, still unable to
7
fail. Remove the unreachable code.
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230109115316.2235-13-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/vexpress.c | 10 +---------
15
1 file changed, 1 insertion(+), 9 deletions(-)
16
17
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/vexpress.c
20
+++ b/hw/arm/vexpress.c
21
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
22
dinfo = drive_get(IF_PFLASH, 0, 0);
23
pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
24
dinfo);
25
- if (!pflash0) {
26
- error_report("vexpress: error registering flash 0");
27
- exit(1);
28
- }
29
30
if (map[VE_NORFLASHALIAS] != -1) {
31
/* Map flash 0 as an alias into low memory */
32
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
33
}
34
35
dinfo = drive_get(IF_PFLASH, 0, 1);
36
- if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
37
- dinfo)) {
38
- error_report("vexpress: error registering flash 1");
39
- exit(1);
40
- }
41
+ ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
42
43
sram_size = 0x2000000;
44
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
45
--
46
2.34.1
47
48
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since its QOM'ification in commit 368a354f02 ("pflash_cfi0x:
4
QOMified") the pflash_cfi01_register() function does not fail.
5
6
This call was later converted with a script to use &error_fatal,
7
still unable to fail. Remove the unreachable code.
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230109115316.2235-14-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/gumstix.c | 18 ++++++------------
15
hw/arm/mainstone.c | 13 +++++--------
16
hw/arm/omap_sx1.c | 22 ++++++++--------------
17
hw/arm/versatilepb.c | 6 ++----
18
hw/arm/z2.c | 9 +++------
19
5 files changed, 24 insertions(+), 44 deletions(-)
20
21
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/gumstix.c
24
+++ b/hw/arm/gumstix.c
25
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
26
}
27
28
/* Numonyx RC28F128J3F75 */
29
- if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
30
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
31
- FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
32
- error_report("Error registering flash memory");
33
- exit(1);
34
- }
35
+ pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
36
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
37
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
38
39
/* Interrupt line of NIC is connected to GPIO line 36 */
40
smc91c111_init(&nd_table[0], 0x04000300,
41
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
42
}
43
44
/* Micron RC28F256P30TFA */
45
- if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
46
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
47
- FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
48
- error_report("Error registering flash memory");
49
- exit(1);
50
- }
51
+ pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
52
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
53
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
54
55
/* Interrupt line of NIC is connected to GPIO line 99 */
56
smc91c111_init(&nd_table[0], 0x04000300,
57
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/mainstone.c
60
+++ b/hw/arm/mainstone.c
61
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
62
/* There are two 32MiB flash devices on the board */
63
for (i = 0; i < 2; i ++) {
64
dinfo = drive_get(IF_PFLASH, 0, i);
65
- if (!pflash_cfi01_register(mainstone_flash_base[i],
66
- i ? "mainstone.flash1" : "mainstone.flash0",
67
- MAINSTONE_FLASH_SIZE,
68
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
69
- FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
70
- error_report("Error registering flash memory");
71
- exit(1);
72
- }
73
+ pflash_cfi01_register(mainstone_flash_base[i],
74
+ i ? "mainstone.flash1" : "mainstone.flash0",
75
+ MAINSTONE_FLASH_SIZE,
76
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
77
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
78
}
79
80
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
81
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/arm/omap_sx1.c
84
+++ b/hw/arm/omap_sx1.c
85
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
86
87
fl_idx = 0;
88
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
89
- if (!pflash_cfi01_register(OMAP_CS0_BASE,
90
- "omap_sx1.flash0-1", flash_size,
91
- blk_by_legacy_dinfo(dinfo),
92
- SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
93
- fprintf(stderr, "qemu: Error registering flash memory %d.\n",
94
- fl_idx);
95
- }
96
+ pflash_cfi01_register(OMAP_CS0_BASE,
97
+ "omap_sx1.flash0-1", flash_size,
98
+ blk_by_legacy_dinfo(dinfo),
99
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
100
fl_idx++;
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
104
memory_region_add_subregion(address_space,
105
OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
106
107
- if (!pflash_cfi01_register(OMAP_CS1_BASE,
108
- "omap_sx1.flash1-1", FLASH1_SIZE,
109
- blk_by_legacy_dinfo(dinfo),
110
- SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
111
- fprintf(stderr, "qemu: Error registering flash memory %d.\n",
112
- fl_idx);
113
- }
114
+ pflash_cfi01_register(OMAP_CS1_BASE,
115
+ "omap_sx1.flash1-1", FLASH1_SIZE,
116
+ blk_by_legacy_dinfo(dinfo),
117
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
118
fl_idx++;
119
} else {
120
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
121
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/hw/arm/versatilepb.c
124
+++ b/hw/arm/versatilepb.c
125
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
126
/* 0x34000000 NOR Flash */
127
128
dinfo = drive_get(IF_PFLASH, 0, 0);
129
- if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
130
+ pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
131
VERSATILE_FLASH_SIZE,
132
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
133
VERSATILE_FLASH_SECT_SIZE,
134
- 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
135
- fprintf(stderr, "qemu: Error registering flash memory.\n");
136
- }
137
+ 4, 0x0089, 0x0018, 0x0000, 0x0, 0);
138
139
versatile_binfo.ram_size = machine->ram_size;
140
versatile_binfo.board_id = board_id;
141
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/hw/arm/z2.c
144
+++ b/hw/arm/z2.c
145
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
146
mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
147
148
dinfo = drive_get(IF_PFLASH, 0, 0);
149
- if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
150
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
151
- FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
152
- error_report("Error registering flash memory");
153
- exit(1);
154
- }
155
+ pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
156
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
157
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
158
159
/* setup keypad */
160
pxa27x_register_keypad(mpu->kp, map, 0x100);
161
--
162
2.34.1
163
164
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
To avoid forward-declaring PXA2xxI2CState, declare
4
PXA2XX_I2C before its use in pxa2xx_i2c_init() prototype.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109140306.23161-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/pxa.h | 6 +++---
12
1 file changed, 3 insertions(+), 3 deletions(-)
13
14
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/arm/pxa.h
17
+++ b/include/hw/arm/pxa.h
18
@@ -XXX,XX +XXX,XX @@ void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
19
const struct keymap *map, int size);
20
21
/* pxa2xx.c */
22
-typedef struct PXA2xxI2CState PXA2xxI2CState;
23
+#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
24
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
25
+
26
PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
27
qemu_irq irq, uint32_t page_size);
28
I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
29
30
-#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
31
typedef struct PXA2xxI2SState PXA2xxI2SState;
32
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
33
34
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
35
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
36
--
37
2.34.1
38
39
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Add a local 'struct omap_gpif_s *' variable to improve readability.
4
(This also eases next commit conversion).
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109140306.23161-3-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/gpio/omap_gpio.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/gpio/omap_gpio.c
17
+++ b/hw/gpio/omap_gpio.c
18
@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
19
/* General-Purpose I/O of OMAP1 */
20
static void omap_gpio_set(void *opaque, int line, int level)
21
{
22
- struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
23
+ struct omap_gpif_s *p = opaque;
24
+ struct omap_gpio_s *s = &p->omap1;
25
uint16_t prev = s->inputs;
26
27
if (level)
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230109140306.23161-4-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/omap1.c | 115 ++++++++++++++++++--------------------
9
hw/arm/omap2.c | 40 ++++++-------
10
hw/arm/omap_sx1.c | 2 +-
11
hw/arm/palm.c | 2 +-
12
hw/char/omap_uart.c | 7 +--
13
hw/display/omap_dss.c | 15 +++--
14
hw/display/omap_lcdc.c | 9 ++-
15
hw/dma/omap_dma.c | 15 +++--
16
hw/gpio/omap_gpio.c | 15 +++--
17
hw/intc/omap_intc.c | 12 ++--
18
hw/misc/omap_gpmc.c | 12 ++--
19
hw/misc/omap_l4.c | 7 +--
20
hw/misc/omap_sdrc.c | 7 +--
21
hw/misc/omap_tap.c | 5 +-
22
hw/sd/omap_mmc.c | 9 ++-
23
hw/ssi/omap_spi.c | 7 +--
24
hw/timer/omap_gptimer.c | 22 ++++----
25
hw/timer/omap_synctimer.c | 4 +-
26
18 files changed, 142 insertions(+), 163 deletions(-)
27
28
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/omap1.c
31
+++ b/hw/arm/omap1.c
32
@@ -XXX,XX +XXX,XX @@ static void omap_timer_fire(void *opaque)
33
34
static void omap_timer_tick(void *opaque)
35
{
36
- struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
37
+ struct omap_mpu_timer_s *timer = opaque;
38
39
omap_timer_sync(timer);
40
omap_timer_fire(timer);
41
@@ -XXX,XX +XXX,XX @@ static void omap_timer_tick(void *opaque)
42
43
static void omap_timer_clk_update(void *opaque, int line, int on)
44
{
45
- struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
46
+ struct omap_mpu_timer_s *timer = opaque;
47
48
omap_timer_sync(timer);
49
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
50
@@ -XXX,XX +XXX,XX @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
51
static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
52
unsigned size)
53
{
54
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
55
+ struct omap_mpu_timer_s *s = opaque;
56
57
if (size != 4) {
58
return omap_badwidth_read32(opaque, addr);
59
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
60
static void omap_mpu_timer_write(void *opaque, hwaddr addr,
61
uint64_t value, unsigned size)
62
{
63
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
64
+ struct omap_mpu_timer_s *s = opaque;
65
66
if (size != 4) {
67
omap_badwidth_write32(opaque, addr, value);
68
@@ -XXX,XX +XXX,XX @@ struct omap_watchdog_timer_s {
69
static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
70
unsigned size)
71
{
72
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
73
+ struct omap_watchdog_timer_s *s = opaque;
74
75
if (size != 2) {
76
return omap_badwidth_read16(opaque, addr);
77
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
78
static void omap_wd_timer_write(void *opaque, hwaddr addr,
79
uint64_t value, unsigned size)
80
{
81
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
82
+ struct omap_watchdog_timer_s *s = opaque;
83
84
if (size != 2) {
85
omap_badwidth_write16(opaque, addr, value);
86
@@ -XXX,XX +XXX,XX @@ struct omap_32khz_timer_s {
87
static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
88
unsigned size)
89
{
90
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
91
+ struct omap_32khz_timer_s *s = opaque;
92
int offset = addr & OMAP_MPUI_REG_MASK;
93
94
if (size != 4) {
95
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
96
static void omap_os_timer_write(void *opaque, hwaddr addr,
97
uint64_t value, unsigned size)
98
{
99
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
100
+ struct omap_32khz_timer_s *s = opaque;
101
int offset = addr & OMAP_MPUI_REG_MASK;
102
103
if (size != 4) {
104
@@ -XXX,XX +XXX,XX @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
105
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
106
unsigned size)
107
{
108
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
109
+ struct omap_mpu_state_s *s = opaque;
110
uint16_t ret;
111
112
if (size != 2) {
113
@@ -XXX,XX +XXX,XX @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
114
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
115
uint64_t value, unsigned size)
116
{
117
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
118
+ struct omap_mpu_state_s *s = opaque;
119
int64_t now, ticks;
120
int div, mult;
121
static const int bypass_div[4] = { 1, 2, 4, 4 };
122
@@ -XXX,XX +XXX,XX @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
123
static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
124
unsigned size)
125
{
126
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
127
+ struct omap_mpu_state_s *s = opaque;
128
129
if (size != 4) {
130
return omap_badwidth_read32(opaque, addr);
131
@@ -XXX,XX +XXX,XX @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
132
static void omap_pin_cfg_write(void *opaque, hwaddr addr,
133
uint64_t value, unsigned size)
134
{
135
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
136
+ struct omap_mpu_state_s *s = opaque;
137
uint32_t diff;
138
139
if (size != 4) {
140
@@ -XXX,XX +XXX,XX @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
141
static uint64_t omap_id_read(void *opaque, hwaddr addr,
142
unsigned size)
143
{
144
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
145
+ struct omap_mpu_state_s *s = opaque;
146
147
if (size != 4) {
148
return omap_badwidth_read32(opaque, addr);
149
@@ -XXX,XX +XXX,XX @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
150
static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
151
unsigned size)
152
{
153
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
154
+ struct omap_mpu_state_s *s = opaque;
155
156
if (size != 4) {
157
return omap_badwidth_read32(opaque, addr);
158
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
159
static void omap_mpui_write(void *opaque, hwaddr addr,
160
uint64_t value, unsigned size)
161
{
162
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
163
+ struct omap_mpu_state_s *s = opaque;
164
165
if (size != 4) {
166
omap_badwidth_write32(opaque, addr, value);
167
@@ -XXX,XX +XXX,XX @@ struct omap_tipb_bridge_s {
168
static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
169
unsigned size)
170
{
171
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
172
+ struct omap_tipb_bridge_s *s = opaque;
173
174
if (size < 2) {
175
return omap_badwidth_read16(opaque, addr);
176
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
177
static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
178
uint64_t value, unsigned size)
179
{
180
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
181
+ struct omap_tipb_bridge_s *s = opaque;
182
183
if (size < 2) {
184
omap_badwidth_write16(opaque, addr, value);
185
@@ -XXX,XX +XXX,XX @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
186
static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
187
unsigned size)
188
{
189
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
190
+ struct omap_mpu_state_s *s = opaque;
191
uint32_t ret;
192
193
if (size != 4) {
194
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
195
static void omap_tcmi_write(void *opaque, hwaddr addr,
196
uint64_t value, unsigned size)
197
{
198
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
199
+ struct omap_mpu_state_s *s = opaque;
200
201
if (size != 4) {
202
omap_badwidth_write32(opaque, addr, value);
203
@@ -XXX,XX +XXX,XX @@ struct dpll_ctl_s {
204
static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
205
unsigned size)
206
{
207
- struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
208
+ struct dpll_ctl_s *s = opaque;
209
210
if (size != 2) {
211
return omap_badwidth_read16(opaque, addr);
212
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
213
static void omap_dpll_write(void *opaque, hwaddr addr,
214
uint64_t value, unsigned size)
215
{
216
- struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
217
+ struct dpll_ctl_s *s = opaque;
218
uint16_t diff;
219
static const int bypass_div[4] = { 1, 2, 4, 4 };
220
int div, mult;
221
@@ -XXX,XX +XXX,XX @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
222
static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
223
unsigned size)
224
{
225
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
226
+ struct omap_mpu_state_s *s = opaque;
227
228
if (size != 2) {
229
return omap_badwidth_read16(opaque, addr);
230
@@ -XXX,XX +XXX,XX @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
231
static void omap_clkm_write(void *opaque, hwaddr addr,
232
uint64_t value, unsigned size)
233
{
234
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
235
+ struct omap_mpu_state_s *s = opaque;
236
uint16_t diff;
237
omap_clk clk;
238
static const char *clkschemename[8] = {
239
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_clkm_ops = {
240
static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
241
unsigned size)
242
{
243
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
244
+ struct omap_mpu_state_s *s = opaque;
245
CPUState *cpu = CPU(s->cpu);
246
247
if (size != 2) {
248
@@ -XXX,XX +XXX,XX @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
249
static void omap_clkdsp_write(void *opaque, hwaddr addr,
250
uint64_t value, unsigned size)
251
{
252
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
253
+ struct omap_mpu_state_s *s = opaque;
254
uint16_t diff;
255
256
if (size != 2) {
257
@@ -XXX,XX +XXX,XX @@ struct omap_mpuio_s {
258
259
static void omap_mpuio_set(void *opaque, int line, int level)
260
{
261
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
262
+ struct omap_mpuio_s *s = opaque;
263
uint16_t prev = s->inputs;
264
265
if (level)
266
@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
267
static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
268
unsigned size)
269
{
270
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
271
+ struct omap_mpuio_s *s = opaque;
272
int offset = addr & OMAP_MPUI_REG_MASK;
273
uint16_t ret;
274
275
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
276
static void omap_mpuio_write(void *opaque, hwaddr addr,
277
uint64_t value, unsigned size)
278
{
279
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
280
+ struct omap_mpuio_s *s = opaque;
281
int offset = addr & OMAP_MPUI_REG_MASK;
282
uint16_t diff;
283
int ln;
284
@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_reset(struct omap_mpuio_s *s)
285
286
static void omap_mpuio_onoff(void *opaque, int line, int on)
287
{
288
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
289
+ struct omap_mpuio_s *s = opaque;
290
291
s->clk = on;
292
if (on)
293
@@ -XXX,XX +XXX,XX @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
294
}
295
}
296
297
-static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
298
- unsigned size)
299
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
300
{
301
- struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
302
+ struct omap_uwire_s *s = opaque;
303
int offset = addr & OMAP_MPUI_REG_MASK;
304
305
if (size != 2) {
306
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
307
static void omap_uwire_write(void *opaque, hwaddr addr,
308
uint64_t value, unsigned size)
309
{
310
- struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
311
+ struct omap_uwire_s *s = opaque;
312
int offset = addr & OMAP_MPUI_REG_MASK;
313
314
if (size != 2) {
315
@@ -XXX,XX +XXX,XX @@ static void omap_pwl_update(struct omap_pwl_s *s)
316
}
317
}
318
319
-static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
320
- unsigned size)
321
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
322
{
323
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
324
+ struct omap_pwl_s *s = opaque;
325
int offset = addr & OMAP_MPUI_REG_MASK;
326
327
if (size != 1) {
328
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
329
static void omap_pwl_write(void *opaque, hwaddr addr,
330
uint64_t value, unsigned size)
331
{
332
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
333
+ struct omap_pwl_s *s = opaque;
334
int offset = addr & OMAP_MPUI_REG_MASK;
335
336
if (size != 1) {
337
@@ -XXX,XX +XXX,XX @@ static void omap_pwl_reset(struct omap_pwl_s *s)
338
339
static void omap_pwl_clk_update(void *opaque, int line, int on)
340
{
341
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
342
+ struct omap_pwl_s *s = opaque;
343
344
s->clk = on;
345
omap_pwl_update(s);
346
@@ -XXX,XX +XXX,XX @@ struct omap_pwt_s {
347
omap_clk clk;
348
};
349
350
-static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
351
- unsigned size)
352
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
353
{
354
- struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
355
+ struct omap_pwt_s *s = opaque;
356
int offset = addr & OMAP_MPUI_REG_MASK;
357
358
if (size != 1) {
359
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
360
static void omap_pwt_write(void *opaque, hwaddr addr,
361
uint64_t value, unsigned size)
362
{
363
- struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
364
+ struct omap_pwt_s *s = opaque;
365
int offset = addr & OMAP_MPUI_REG_MASK;
366
367
if (size != 1) {
368
@@ -XXX,XX +XXX,XX @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
369
printf("%s: conversion failed\n", __func__);
370
}
371
372
-static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
373
- unsigned size)
374
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
375
{
376
- struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
377
+ struct omap_rtc_s *s = opaque;
378
int offset = addr & OMAP_MPUI_REG_MASK;
379
uint8_t i;
380
381
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
382
static void omap_rtc_write(void *opaque, hwaddr addr,
383
uint64_t value, unsigned size)
384
{
385
- struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
386
+ struct omap_rtc_s *s = opaque;
387
int offset = addr & OMAP_MPUI_REG_MASK;
388
struct tm new_tm;
389
time_t ti[2];
390
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
391
392
static void omap_mcbsp_source_tick(void *opaque)
393
{
394
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
395
+ struct omap_mcbsp_s *s = opaque;
396
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
397
398
if (!s->rx_rate)
399
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
400
401
static void omap_mcbsp_sink_tick(void *opaque)
402
{
403
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
404
+ struct omap_mcbsp_s *s = opaque;
405
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
406
407
if (!s->tx_rate)
408
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
409
static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
410
unsigned size)
411
{
412
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
413
+ struct omap_mcbsp_s *s = opaque;
414
int offset = addr & OMAP_MPUI_REG_MASK;
415
uint16_t ret;
416
417
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
418
static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
419
uint32_t value)
420
{
421
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
422
+ struct omap_mcbsp_s *s = opaque;
423
int offset = addr & OMAP_MPUI_REG_MASK;
424
425
switch (offset) {
426
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
427
static void omap_mcbsp_writew(void *opaque, hwaddr addr,
428
uint32_t value)
429
{
430
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
431
+ struct omap_mcbsp_s *s = opaque;
432
int offset = addr & OMAP_MPUI_REG_MASK;
433
434
if (offset == 0x04) {                /* DXR */
435
@@ -XXX,XX +XXX,XX @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
436
437
static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
438
{
439
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
440
+ struct omap_mcbsp_s *s = opaque;
441
442
if (s->rx_rate) {
443
s->rx_req = s->codec->in.len;
444
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
445
446
static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
447
{
448
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
449
+ struct omap_mcbsp_s *s = opaque;
450
451
if (s->tx_rate) {
452
s->tx_req = s->codec->out.size;
453
@@ -XXX,XX +XXX,XX @@ static void omap_lpg_reset(struct omap_lpg_s *s)
454
omap_lpg_update(s);
455
}
456
457
-static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
458
- unsigned size)
459
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
460
{
461
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
462
+ struct omap_lpg_s *s = opaque;
463
int offset = addr & OMAP_MPUI_REG_MASK;
464
465
if (size != 1) {
466
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
467
static void omap_lpg_write(void *opaque, hwaddr addr,
468
uint64_t value, unsigned size)
469
{
470
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
471
+ struct omap_lpg_s *s = opaque;
472
int offset = addr & OMAP_MPUI_REG_MASK;
473
474
if (size != 1) {
475
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_lpg_ops = {
476
477
static void omap_lpg_clk_update(void *opaque, int line, int on)
478
{
479
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
480
+ struct omap_lpg_s *s = opaque;
481
482
s->clk = on;
483
omap_lpg_update(s);
484
@@ -XXX,XX +XXX,XX @@ static void omap_setup_mpui_io(MemoryRegion *system_memory,
485
/* General chip reset */
486
static void omap1_mpu_reset(void *opaque)
487
{
488
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
489
+ struct omap_mpu_state_s *mpu = opaque;
490
491
omap_dma_reset(mpu->dma);
492
omap_mpu_timer_reset(mpu->timer[0]);
493
@@ -XXX,XX +XXX,XX @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
494
495
void omap_mpu_wakeup(void *opaque, int irq, int req)
496
{
497
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
498
+ struct omap_mpu_state_s *mpu = opaque;
499
CPUState *cpu = CPU(mpu->cpu);
500
501
if (cpu->halted) {
502
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
503
index XXXXXXX..XXXXXXX 100644
504
--- a/hw/arm/omap2.c
505
+++ b/hw/arm/omap2.c
506
@@ -XXX,XX +XXX,XX @@ static inline void omap_eac_out_empty(struct omap_eac_s *s)
507
508
static void omap_eac_in_cb(void *opaque, int avail_b)
509
{
510
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
511
+ struct omap_eac_s *s = opaque;
512
513
s->codec.rxavail = avail_b >> 2;
514
omap_eac_in_refill(s);
515
@@ -XXX,XX +XXX,XX @@ static void omap_eac_in_cb(void *opaque, int avail_b)
516
517
static void omap_eac_out_cb(void *opaque, int free_b)
518
{
519
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
520
+ struct omap_eac_s *s = opaque;
521
522
s->codec.txavail = free_b >> 2;
523
if (s->codec.txlen)
524
@@ -XXX,XX +XXX,XX @@ static void omap_eac_reset(struct omap_eac_s *s)
525
omap_eac_interrupt_update(s);
526
}
527
528
-static uint64_t omap_eac_read(void *opaque, hwaddr addr,
529
- unsigned size)
530
+static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
531
{
532
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
533
+ struct omap_eac_s *s = opaque;
534
uint32_t ret;
535
536
if (size != 2) {
537
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr,
538
static void omap_eac_write(void *opaque, hwaddr addr,
539
uint64_t value, unsigned size)
540
{
541
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
542
+ struct omap_eac_s *s = opaque;
543
544
if (size != 2) {
545
omap_badwidth_write16(opaque, addr, value);
546
@@ -XXX,XX +XXX,XX @@ static void omap_sti_reset(struct omap_sti_s *s)
547
static uint64_t omap_sti_read(void *opaque, hwaddr addr,
548
unsigned size)
549
{
550
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
551
+ struct omap_sti_s *s = opaque;
552
553
if (size != 4) {
554
return omap_badwidth_read32(opaque, addr);
555
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
556
static void omap_sti_write(void *opaque, hwaddr addr,
557
uint64_t value, unsigned size)
558
{
559
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
560
+ struct omap_sti_s *s = opaque;
561
562
if (size != 4) {
563
omap_badwidth_write32(opaque, addr, value);
564
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_sti_ops = {
565
.endianness = DEVICE_NATIVE_ENDIAN,
566
};
567
568
-static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
569
- unsigned size)
570
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
571
{
572
OMAP_BAD_REG(addr);
573
return 0;
574
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
575
static void omap_sti_fifo_write(void *opaque, hwaddr addr,
576
uint64_t value, unsigned size)
577
{
578
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
579
+ struct omap_sti_s *s = opaque;
580
int ch = addr >> 6;
581
uint8_t byte = value;
582
583
@@ -XXX,XX +XXX,XX @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
584
static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
585
unsigned size)
586
{
587
- struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
588
+ struct omap_prcm_s *s = opaque;
589
uint32_t ret;
590
591
if (size != 4) {
592
@@ -XXX,XX +XXX,XX @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
593
static void omap_prcm_write(void *opaque, hwaddr addr,
594
uint64_t value, unsigned size)
595
{
596
- struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
597
+ struct omap_prcm_s *s = opaque;
598
599
if (size != 4) {
600
omap_badwidth_write32(opaque, addr, value);
601
@@ -XXX,XX +XXX,XX @@ struct omap_sysctl_s {
602
static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
603
{
604
605
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
606
+ struct omap_sysctl_s *s = opaque;
607
int pad_offset, byte_offset;
608
int value;
609
610
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
611
612
static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
613
{
614
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
615
+ struct omap_sysctl_s *s = opaque;
616
617
switch (addr) {
618
case 0x000:    /* CONTROL_REVISION */
619
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
620
return 0;
621
}
622
623
-static void omap_sysctl_write8(void *opaque, hwaddr addr,
624
- uint32_t value)
625
+static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
626
{
627
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
628
+ struct omap_sysctl_s *s = opaque;
629
int pad_offset, byte_offset;
630
int prev_value;
631
632
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write8(void *opaque, hwaddr addr,
633
}
634
}
635
636
-static void omap_sysctl_write(void *opaque, hwaddr addr,
637
- uint32_t value)
638
+static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
639
{
640
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
641
+ struct omap_sysctl_s *s = opaque;
642
643
switch (addr) {
644
case 0x000:    /* CONTROL_REVISION */
645
@@ -XXX,XX +XXX,XX @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
646
/* General chip reset */
647
static void omap2_mpu_reset(void *opaque)
648
{
649
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
650
+ struct omap_mpu_state_s *mpu = opaque;
651
652
omap_dma_reset(mpu->dma);
653
omap_prcm_reset(mpu->prcm);
654
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
655
index XXXXXXX..XXXXXXX 100644
656
--- a/hw/arm/omap_sx1.c
657
+++ b/hw/arm/omap_sx1.c
658
@@ -XXX,XX +XXX,XX @@
659
static uint64_t static_read(void *opaque, hwaddr offset,
660
unsigned size)
661
{
662
- uint32_t *val = (uint32_t *) opaque;
663
+ uint32_t *val = opaque;
664
uint32_t mask = (4 / size) - 1;
665
666
return *val >> ((offset & mask) << 3);
667
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
668
index XXXXXXX..XXXXXXX 100644
669
--- a/hw/arm/palm.c
670
+++ b/hw/arm/palm.c
671
@@ -XXX,XX +XXX,XX @@ static struct {
672
673
static void palmte_button_event(void *opaque, int keycode)
674
{
675
- struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque;
676
+ struct omap_mpu_state_s *cpu = opaque;
677
678
if (palmte_keymap[keycode & 0x7f].row != -1)
679
omap_mpuio_key(cpu->mpuio,
680
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
681
index XXXXXXX..XXXXXXX 100644
682
--- a/hw/char/omap_uart.c
683
+++ b/hw/char/omap_uart.c
684
@@ -XXX,XX +XXX,XX @@ struct omap_uart_s *omap_uart_init(hwaddr base,
685
return s;
686
}
687
688
-static uint64_t omap_uart_read(void *opaque, hwaddr addr,
689
- unsigned size)
690
+static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
691
{
692
- struct omap_uart_s *s = (struct omap_uart_s *) opaque;
693
+ struct omap_uart_s *s = opaque;
694
695
if (size == 4) {
696
return omap_badwidth_read8(opaque, addr);
697
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr,
698
static void omap_uart_write(void *opaque, hwaddr addr,
699
uint64_t value, unsigned size)
700
{
701
- struct omap_uart_s *s = (struct omap_uart_s *) opaque;
702
+ struct omap_uart_s *s = opaque;
703
704
if (size == 4) {
705
omap_badwidth_write8(opaque, addr, value);
706
diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c
707
index XXXXXXX..XXXXXXX 100644
708
--- a/hw/display/omap_dss.c
709
+++ b/hw/display/omap_dss.c
710
@@ -XXX,XX +XXX,XX @@ void omap_dss_reset(struct omap_dss_s *s)
711
static uint64_t omap_diss_read(void *opaque, hwaddr addr,
712
unsigned size)
713
{
714
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
715
+ struct omap_dss_s *s = opaque;
716
717
if (size != 4) {
718
return omap_badwidth_read32(opaque, addr);
719
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
720
static void omap_diss_write(void *opaque, hwaddr addr,
721
uint64_t value, unsigned size)
722
{
723
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
724
+ struct omap_dss_s *s = opaque;
725
726
if (size != 4) {
727
omap_badwidth_write32(opaque, addr, value);
728
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_diss_ops = {
729
static uint64_t omap_disc_read(void *opaque, hwaddr addr,
730
unsigned size)
731
{
732
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
733
+ struct omap_dss_s *s = opaque;
734
735
if (size != 4) {
736
return omap_badwidth_read32(opaque, addr);
737
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
738
static void omap_disc_write(void *opaque, hwaddr addr,
739
uint64_t value, unsigned size)
740
{
741
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
742
+ struct omap_dss_s *s = opaque;
743
744
if (size != 4) {
745
omap_badwidth_write32(opaque, addr, value);
746
@@ -XXX,XX +XXX,XX @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
747
omap_dispc_interrupt_update(s);
748
}
749
750
-static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
751
- unsigned size)
752
+static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size)
753
{
754
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
755
+ struct omap_dss_s *s = opaque;
756
757
if (size != 4) {
758
return omap_badwidth_read32(opaque, addr);
759
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
760
static void omap_rfbi_write(void *opaque, hwaddr addr,
761
uint64_t value, unsigned size)
762
{
763
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
764
+ struct omap_dss_s *s = opaque;
765
766
if (size != 4) {
767
omap_badwidth_write32(opaque, addr, value);
768
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
769
index XXXXXXX..XXXXXXX 100644
770
--- a/hw/display/omap_lcdc.c
771
+++ b/hw/display/omap_lcdc.c
772
@@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
773
774
static void omap_update_display(void *opaque)
775
{
776
- struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
777
+ struct omap_lcd_panel_s *omap_lcd = opaque;
778
DisplaySurface *surface;
779
drawfn draw_line;
780
int size, height, first, last;
781
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
782
}
783
}
784
785
-static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
786
- unsigned size)
787
+static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size)
788
{
789
- struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
790
+ struct omap_lcd_panel_s *s = opaque;
791
792
switch (addr) {
793
case 0x00:    /* LCD_CONTROL */
794
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
795
static void omap_lcdc_write(void *opaque, hwaddr addr,
796
uint64_t value, unsigned size)
797
{
798
- struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
799
+ struct omap_lcd_panel_s *s = opaque;
800
801
switch (addr) {
802
case 0x00:    /* LCD_CONTROL */
803
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
804
index XXXXXXX..XXXXXXX 100644
805
--- a/hw/dma/omap_dma.c
806
+++ b/hw/dma/omap_dma.c
807
@@ -XXX,XX +XXX,XX @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
808
return 0;
809
}
810
811
-static uint64_t omap_dma_read(void *opaque, hwaddr addr,
812
- unsigned size)
813
+static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
814
{
815
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
816
+ struct omap_dma_s *s = opaque;
817
int reg, ch;
818
uint16_t ret;
819
820
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr,
821
static void omap_dma_write(void *opaque, hwaddr addr,
822
uint64_t value, unsigned size)
823
{
824
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
825
+ struct omap_dma_s *s = opaque;
826
int reg, ch;
827
828
if (size != 2) {
829
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_dma_ops = {
830
831
static void omap_dma_request(void *opaque, int drq, int req)
832
{
833
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
834
+ struct omap_dma_s *s = opaque;
835
/* The request pins are level triggered in QEMU. */
836
if (req) {
837
if (~s->dma->drqbmp & (1ULL << drq)) {
838
@@ -XXX,XX +XXX,XX @@ static void omap_dma_request(void *opaque, int drq, int req)
839
/* XXX: this won't be needed once soc_dma knows about clocks. */
840
static void omap_dma_clk_update(void *opaque, int line, int on)
841
{
842
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
843
+ struct omap_dma_s *s = opaque;
844
int i;
845
846
s->dma->freq = omap_clk_getrate(s->clk);
847
@@ -XXX,XX +XXX,XX @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
848
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
849
unsigned size)
850
{
851
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
852
+ struct omap_dma_s *s = opaque;
853
int irqn = 0, chnum;
854
struct omap_dma_channel_s *ch;
855
856
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
857
static void omap_dma4_write(void *opaque, hwaddr addr,
858
uint64_t value, unsigned size)
859
{
860
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
861
+ struct omap_dma_s *s = opaque;
862
int chnum, irqn = 0;
863
struct omap_dma_channel_s *ch;
864
865
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
866
index XXXXXXX..XXXXXXX 100644
867
--- a/hw/gpio/omap_gpio.c
868
+++ b/hw/gpio/omap_gpio.c
869
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_set(void *opaque, int line, int level)
870
static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
871
unsigned size)
872
{
873
- struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
874
+ struct omap_gpio_s *s = opaque;
875
int offset = addr & OMAP_MPUI_REG_MASK;
876
877
if (size != 2) {
878
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
879
static void omap_gpio_write(void *opaque, hwaddr addr,
880
uint64_t value, unsigned size)
881
{
882
- struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
883
+ struct omap_gpio_s *s = opaque;
884
int offset = addr & OMAP_MPUI_REG_MASK;
885
uint16_t diff;
886
int ln;
887
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
888
889
static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
890
{
891
- struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
892
+ struct omap2_gpio_s *s = opaque;
893
894
switch (addr) {
895
case 0x00:    /* GPIO_REVISION */
896
@@ -XXX,XX +XXX,XX @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
897
static void omap2_gpio_module_write(void *opaque, hwaddr addr,
898
uint32_t value)
899
{
900
- struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
901
+ struct omap2_gpio_s *s = opaque;
902
uint32_t diff;
903
int ln;
904
905
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
906
s->gpo = 0;
907
}
908
909
-static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
910
- unsigned size)
911
+static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
912
{
913
- struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
914
+ struct omap2_gpif_s *s = opaque;
915
916
switch (addr) {
917
case 0x00:    /* IPGENERICOCPSPL_REVISION */
918
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
919
static void omap2_gpif_top_write(void *opaque, hwaddr addr,
920
uint64_t value, unsigned size)
921
{
922
- struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
923
+ struct omap2_gpif_s *s = opaque;
924
925
switch (addr) {
926
case 0x00:    /* IPGENERICOCPSPL_REVISION */
927
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
928
index XXXXXXX..XXXXXXX 100644
929
--- a/hw/intc/omap_intc.c
930
+++ b/hw/intc/omap_intc.c
931
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
932
933
static void omap_set_intr(void *opaque, int irq, int req)
934
{
935
- struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
936
+ struct omap_intr_handler_s *ih = opaque;
937
uint32_t rise;
938
939
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
940
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
941
/* Simplified version with no edge detection */
942
static void omap_set_intr_noedge(void *opaque, int irq, int req)
943
{
944
- struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
945
+ struct omap_intr_handler_s *ih = opaque;
946
uint32_t rise;
947
948
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
949
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
950
static uint64_t omap_inth_read(void *opaque, hwaddr addr,
951
unsigned size)
952
{
953
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
954
+ struct omap_intr_handler_s *s = opaque;
955
int i, offset = addr;
956
int bank_no = offset >> 8;
957
int line_no;
958
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
959
static void omap_inth_write(void *opaque, hwaddr addr,
960
uint64_t value, unsigned size)
961
{
962
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
963
+ struct omap_intr_handler_s *s = opaque;
964
int i, offset = addr;
965
int bank_no = offset >> 8;
966
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
967
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
968
static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
969
unsigned size)
970
{
971
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
972
+ struct omap_intr_handler_s *s = opaque;
973
int offset = addr;
974
int bank_no, line_no;
975
struct omap_intr_handler_bank_s *bank = NULL;
976
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
977
static void omap2_inth_write(void *opaque, hwaddr addr,
978
uint64_t value, unsigned size)
979
{
980
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
981
+ struct omap_intr_handler_s *s = opaque;
982
int offset = addr;
983
int bank_no, line_no;
984
struct omap_intr_handler_bank_s *bank = NULL;
985
diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
986
index XXXXXXX..XXXXXXX 100644
987
--- a/hw/misc/omap_gpmc.c
988
+++ b/hw/misc/omap_gpmc.c
989
@@ -XXX,XX +XXX,XX @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
990
static uint64_t omap_nand_read(void *opaque, hwaddr addr,
991
unsigned size)
992
{
993
- struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
994
+ struct omap_gpmc_cs_file_s *f = opaque;
995
uint64_t v;
996
nand_setpins(f->dev, 0, 0, 0, 1, 0);
997
switch (omap_gpmc_devsize(f)) {
998
@@ -XXX,XX +XXX,XX @@ static void omap_nand_setio(DeviceState *dev, uint64_t value,
999
static void omap_nand_write(void *opaque, hwaddr addr,
1000
uint64_t value, unsigned size)
1001
{
1002
- struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
1003
+ struct omap_gpmc_cs_file_s *f = opaque;
1004
nand_setpins(f->dev, 0, 0, 0, 1, 0);
1005
omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
1006
}
1007
@@ -XXX,XX +XXX,XX @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
1008
static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
1009
unsigned size)
1010
{
1011
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1012
+ struct omap_gpmc_s *s = opaque;
1013
uint32_t data;
1014
if (s->prefetch.config1 & 1) {
1015
/* The TRM doesn't define the behaviour if you read from the
1016
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
1017
static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
1018
uint64_t value, unsigned size)
1019
{
1020
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1021
+ struct omap_gpmc_s *s = opaque;
1022
int cs = prefetch_cs(s->prefetch.config1);
1023
if ((s->prefetch.config1 & 1) == 0) {
1024
/* The TRM doesn't define the behaviour of writing to the
1025
@@ -XXX,XX +XXX,XX @@ static int gpmc_wordaccess_only(hwaddr addr)
1026
static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
1027
unsigned size)
1028
{
1029
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1030
+ struct omap_gpmc_s *s = opaque;
1031
int cs;
1032
struct omap_gpmc_cs_file_s *f;
1033
1034
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
1035
static void omap_gpmc_write(void *opaque, hwaddr addr,
1036
uint64_t value, unsigned size)
1037
{
1038
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1039
+ struct omap_gpmc_s *s = opaque;
1040
int cs;
1041
struct omap_gpmc_cs_file_s *f;
1042
1043
diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c
1044
index XXXXXXX..XXXXXXX 100644
1045
--- a/hw/misc/omap_l4.c
1046
+++ b/hw/misc/omap_l4.c
1047
@@ -XXX,XX +XXX,XX @@ hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
1048
return ta->start[region].size;
1049
}
1050
1051
-static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
1052
- unsigned size)
1053
+static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size)
1054
{
1055
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1056
+ struct omap_target_agent_s *s = opaque;
1057
1058
if (size != 2) {
1059
return omap_badwidth_read16(opaque, addr);
1060
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
1061
static void omap_l4ta_write(void *opaque, hwaddr addr,
1062
uint64_t value, unsigned size)
1063
{
1064
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1065
+ struct omap_target_agent_s *s = opaque;
1066
1067
if (size != 4) {
1068
omap_badwidth_write32(opaque, addr, value);
1069
diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c
1070
index XXXXXXX..XXXXXXX 100644
1071
--- a/hw/misc/omap_sdrc.c
1072
+++ b/hw/misc/omap_sdrc.c
1073
@@ -XXX,XX +XXX,XX @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
1074
s->config = 0x10;
1075
}
1076
1077
-static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
1078
- unsigned size)
1079
+static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size)
1080
{
1081
- struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
1082
+ struct omap_sdrc_s *s = opaque;
1083
1084
if (size != 4) {
1085
return omap_badwidth_read32(opaque, addr);
1086
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
1087
static void omap_sdrc_write(void *opaque, hwaddr addr,
1088
uint64_t value, unsigned size)
1089
{
1090
- struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
1091
+ struct omap_sdrc_s *s = opaque;
1092
1093
if (size != 4) {
1094
omap_badwidth_write32(opaque, addr, value);
1095
diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c
1096
index XXXXXXX..XXXXXXX 100644
1097
--- a/hw/misc/omap_tap.c
1098
+++ b/hw/misc/omap_tap.c
1099
@@ -XXX,XX +XXX,XX @@
1100
#include "hw/arm/omap.h"
1101
1102
/* TEST-Chip-level TAP */
1103
-static uint64_t omap_tap_read(void *opaque, hwaddr addr,
1104
- unsigned size)
1105
+static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size)
1106
{
1107
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1108
+ struct omap_mpu_state_s *s = opaque;
1109
1110
if (size != 4) {
1111
return omap_badwidth_read32(opaque, addr);
1112
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
1113
index XXXXXXX..XXXXXXX 100644
1114
--- a/hw/sd/omap_mmc.c
1115
+++ b/hw/sd/omap_mmc.c
1116
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
1117
device_cold_reset(DEVICE(host->card));
1118
}
1119
1120
-static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
1121
- unsigned size)
1122
+static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
1123
{
1124
uint16_t i;
1125
- struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
1126
+ struct omap_mmc_s *s = opaque;
1127
1128
if (size != 2) {
1129
return omap_badwidth_read16(opaque, offset);
1130
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
1131
uint64_t value, unsigned size)
1132
{
1133
int i;
1134
- struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
1135
+ struct omap_mmc_s *s = opaque;
1136
1137
if (size != 2) {
1138
omap_badwidth_write16(opaque, offset, value);
1139
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_mmc_ops = {
1140
1141
static void omap_mmc_cover_cb(void *opaque, int line, int level)
1142
{
1143
- struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
1144
+ struct omap_mmc_s *host = opaque;
1145
1146
if (!host->cdet_state && level) {
1147
host->status |= 0x0002;
1148
diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
1149
index XXXXXXX..XXXXXXX 100644
1150
--- a/hw/ssi/omap_spi.c
1151
+++ b/hw/ssi/omap_spi.c
1152
@@ -XXX,XX +XXX,XX @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
1153
omap_mcspi_interrupt_update(s);
1154
}
1155
1156
-static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1157
- unsigned size)
1158
+static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
1159
{
1160
- struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1161
+ struct omap_mcspi_s *s = opaque;
1162
int ch = 0;
1163
uint32_t ret;
1164
1165
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1166
static void omap_mcspi_write(void *opaque, hwaddr addr,
1167
uint64_t value, unsigned size)
1168
{
1169
- struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1170
+ struct omap_mcspi_s *s = opaque;
1171
int ch = 0;
1172
1173
if (size != 4) {
1174
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
1175
index XXXXXXX..XXXXXXX 100644
1176
--- a/hw/timer/omap_gptimer.c
1177
+++ b/hw/timer/omap_gptimer.c
1178
@@ -XXX,XX +XXX,XX @@ static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
1179
1180
static void omap_gp_timer_tick(void *opaque)
1181
{
1182
- struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
1183
+ struct omap_gp_timer_s *timer = opaque;
1184
1185
if (!timer->ar) {
1186
timer->st = 0;
1187
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_tick(void *opaque)
1188
1189
static void omap_gp_timer_match(void *opaque)
1190
{
1191
- struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
1192
+ struct omap_gp_timer_s *timer = opaque;
1193
1194
if (timer->trigger == gpt_trigger_both)
1195
omap_gp_timer_trigger(timer);
1196
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_match(void *opaque)
1197
1198
static void omap_gp_timer_input(void *opaque, int line, int on)
1199
{
1200
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1201
+ struct omap_gp_timer_s *s = opaque;
1202
int trigger;
1203
1204
switch (s->capture) {
1205
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_input(void *opaque, int line, int on)
1206
1207
static void omap_gp_timer_clk_update(void *opaque, int line, int on)
1208
{
1209
- struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
1210
+ struct omap_gp_timer_s *timer = opaque;
1211
1212
omap_gp_timer_sync(timer);
1213
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
1214
@@ -XXX,XX +XXX,XX @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
1215
1216
static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
1217
{
1218
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1219
+ struct omap_gp_timer_s *s = opaque;
1220
1221
switch (addr) {
1222
case 0x00:    /* TIDR */
1223
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
1224
1225
static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
1226
{
1227
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1228
+ struct omap_gp_timer_s *s = opaque;
1229
uint32_t ret;
1230
1231
if (addr & 2)
1232
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
1233
}
1234
}
1235
1236
-static void omap_gp_timer_write(void *opaque, hwaddr addr,
1237
- uint32_t value)
1238
+static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value)
1239
{
1240
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1241
+ struct omap_gp_timer_s *s = opaque;
1242
1243
switch (addr) {
1244
case 0x00:    /* TIDR */
1245
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
1246
}
1247
}
1248
1249
-static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
1250
- uint32_t value)
1251
+static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value)
1252
{
1253
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1254
+ struct omap_gp_timer_s *s = opaque;
1255
1256
if (addr & 2)
1257
omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
1258
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
1259
index XXXXXXX..XXXXXXX 100644
1260
--- a/hw/timer/omap_synctimer.c
1261
+++ b/hw/timer/omap_synctimer.c
1262
@@ -XXX,XX +XXX,XX @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
1263
1264
static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
1265
{
1266
- struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
1267
+ struct omap_synctimer_s *s = opaque;
1268
1269
switch (addr) {
1270
case 0x00:    /* 32KSYNCNT_REV */
1271
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
1272
1273
static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
1274
{
1275
- struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
1276
+ struct omap_synctimer_s *s = opaque;
1277
uint32_t ret;
1278
1279
if (addr & 2)
1280
--
1281
2.34.1
1282
1283
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Following docs/devel/style.rst guidelines, rename omap_gpif_s ->
4
Omap1GpioState. This also remove a use of 'struct' in the
5
DECLARE_INSTANCE_CHECKER() macro call.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-5-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/omap.h | 6 +++---
13
hw/gpio/omap_gpio.c | 16 ++++++++--------
14
2 files changed, 11 insertions(+), 11 deletions(-)
15
16
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/omap.h
19
+++ b/include/hw/arm/omap.h
20
@@ -XXX,XX +XXX,XX @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
21
22
/* omap_gpio.c */
23
#define TYPE_OMAP1_GPIO "omap-gpio"
24
-DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
25
+typedef struct Omap1GpioState Omap1GpioState;
26
+DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
27
TYPE_OMAP1_GPIO)
28
29
#define TYPE_OMAP2_GPIO "omap2-gpio"
30
DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
31
TYPE_OMAP2_GPIO)
32
33
-typedef struct omap_gpif_s omap_gpif;
34
typedef struct omap2_gpif_s omap2_gpif;
35
36
/* TODO: clock framework (see above) */
37
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
38
+void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
39
40
void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
41
void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
42
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/gpio/omap_gpio.c
45
+++ b/hw/gpio/omap_gpio.c
46
@@ -XXX,XX +XXX,XX @@ struct omap_gpio_s {
47
uint16_t pins;
48
};
49
50
-struct omap_gpif_s {
51
+struct Omap1GpioState {
52
SysBusDevice parent_obj;
53
54
MemoryRegion iomem;
55
@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
56
/* General-Purpose I/O of OMAP1 */
57
static void omap_gpio_set(void *opaque, int line, int level)
58
{
59
- struct omap_gpif_s *p = opaque;
60
+ Omap1GpioState *p = opaque;
61
struct omap_gpio_s *s = &p->omap1;
62
uint16_t prev = s->inputs;
63
64
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpio_module_ops = {
65
66
static void omap_gpif_reset(DeviceState *dev)
67
{
68
- struct omap_gpif_s *s = OMAP1_GPIO(dev);
69
+ Omap1GpioState *s = OMAP1_GPIO(dev);
70
71
omap_gpio_reset(&s->omap1);
72
}
73
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpif_top_ops = {
74
static void omap_gpio_init(Object *obj)
75
{
76
DeviceState *dev = DEVICE(obj);
77
- struct omap_gpif_s *s = OMAP1_GPIO(obj);
78
+ Omap1GpioState *s = OMAP1_GPIO(obj);
79
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
80
81
qdev_init_gpio_in(dev, omap_gpio_set, 16);
82
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_init(Object *obj)
83
84
static void omap_gpio_realize(DeviceState *dev, Error **errp)
85
{
86
- struct omap_gpif_s *s = OMAP1_GPIO(dev);
87
+ Omap1GpioState *s = OMAP1_GPIO(dev);
88
89
if (!s->clk) {
90
error_setg(errp, "omap-gpio: clk not connected");
91
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp)
92
}
93
}
94
95
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
96
+void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk)
97
{
98
gpio->clk = clk;
99
}
100
101
static Property omap_gpio_properties[] = {
102
- DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
103
+ DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0),
104
DEFINE_PROP_END_OF_LIST(),
105
};
106
107
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_class_init(ObjectClass *klass, void *data)
108
static const TypeInfo omap_gpio_info = {
109
.name = TYPE_OMAP1_GPIO,
110
.parent = TYPE_SYS_BUS_DEVICE,
111
- .instance_size = sizeof(struct omap_gpif_s),
112
+ .instance_size = sizeof(Omap1GpioState),
113
.instance_init = omap_gpio_init,
114
.class_init = omap_gpio_class_init,
115
};
116
--
117
2.34.1
118
119
diff view generated by jsdifflib
1
In commit a1a98357e3fd in 2018 we added some workarounds for Coverity
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
not being able to handle the _Float* types introduced by recent
3
glibc. Newer versions of the Coverity scan tools have support for
4
these types, and will fail with errors about duplicate typedefs if we
5
have our workaround. Remove our copy of the typedefs.
6
2
3
Following docs/devel/style.rst guidelines, rename omap2_gpif_s ->
4
Omap2GpioState. This also remove a use of 'struct' in the
5
DECLARE_INSTANCE_CHECKER() macro call.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-6-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200319193323.2038-2-peter.maydell@linaro.org
10
---
11
---
11
include/qemu/osdep.h | 14 --------------
12
include/hw/arm/omap.h | 9 ++++-----
12
1 file changed, 14 deletions(-)
13
hw/gpio/omap_gpio.c | 20 ++++++++++----------
14
2 files changed, 14 insertions(+), 15 deletions(-)
13
15
14
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
16
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/include/qemu/osdep.h
18
--- a/include/hw/arm/omap.h
17
+++ b/include/qemu/osdep.h
19
+++ b/include/hw/arm/omap.h
18
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
19
#else
21
TYPE_OMAP1_GPIO)
20
#include "exec/poison.h"
22
21
#endif
23
#define TYPE_OMAP2_GPIO "omap2-gpio"
22
-#ifdef __COVERITY__
24
-DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
23
-/* Coverity does not like the new _Float* types that are used by
25
+typedef struct Omap2GpioState Omap2GpioState;
24
- * recent glibc, and croaks on every single file that includes
26
+DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO,
25
- * stdlib.h. These typedefs are enough to please it.
27
TYPE_OMAP2_GPIO)
26
- *
28
27
- * Note that these fix parse errors so they cannot be placed in
29
-typedef struct omap2_gpif_s omap2_gpif;
28
- * scripts/coverity-model.c.
30
-
29
- */
31
/* TODO: clock framework (see above) */
30
-typedef float _Float32;
32
void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
31
-typedef double _Float32x;
33
32
-typedef double _Float64;
34
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
33
-typedef __float80 _Float64x;
35
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
34
-typedef __float128 _Float128;
36
+void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk);
35
-#endif
37
+void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk);
36
38
37
#include "qemu/compiler.h"
39
/* OMAP2 l4 Interconnect */
40
struct omap_l4_s;
41
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/gpio/omap_gpio.c
44
+++ b/hw/gpio/omap_gpio.c
45
@@ -XXX,XX +XXX,XX @@ struct omap2_gpio_s {
46
uint8_t delay;
47
};
48
49
-struct omap2_gpif_s {
50
+struct Omap2GpioState {
51
SysBusDevice parent_obj;
52
53
MemoryRegion iomem;
54
@@ -XXX,XX +XXX,XX @@ static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
55
56
static void omap2_gpio_set(void *opaque, int line, int level)
57
{
58
- struct omap2_gpif_s *p = opaque;
59
+ Omap2GpioState *p = opaque;
60
struct omap2_gpio_s *s = &p->modules[line >> 5];
61
62
line &= 31;
63
@@ -XXX,XX +XXX,XX @@ static void omap_gpif_reset(DeviceState *dev)
64
65
static void omap2_gpif_reset(DeviceState *dev)
66
{
67
- struct omap2_gpif_s *s = OMAP2_GPIO(dev);
68
+ Omap2GpioState *s = OMAP2_GPIO(dev);
69
int i;
70
71
for (i = 0; i < s->modulecount; i++) {
72
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
73
74
static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
75
{
76
- struct omap2_gpif_s *s = opaque;
77
+ Omap2GpioState *s = opaque;
78
79
switch (addr) {
80
case 0x00:    /* IPGENERICOCPSPL_REVISION */
81
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
82
static void omap2_gpif_top_write(void *opaque, hwaddr addr,
83
uint64_t value, unsigned size)
84
{
85
- struct omap2_gpif_s *s = opaque;
86
+ Omap2GpioState *s = opaque;
87
88
switch (addr) {
89
case 0x00:    /* IPGENERICOCPSPL_REVISION */
90
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_realize(DeviceState *dev, Error **errp)
91
92
static void omap2_gpio_realize(DeviceState *dev, Error **errp)
93
{
94
- struct omap2_gpif_s *s = OMAP2_GPIO(dev);
95
+ Omap2GpioState *s = OMAP2_GPIO(dev);
96
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
97
int i;
98
99
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_gpio_info = {
100
.class_init = omap_gpio_class_init,
101
};
102
103
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
104
+void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk)
105
{
106
gpio->iclk = clk;
107
}
108
109
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
110
+void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk)
111
{
112
assert(i <= 5);
113
gpio->fclk[i] = clk;
114
}
115
116
static Property omap2_gpio_properties[] = {
117
- DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
118
+ DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0),
119
DEFINE_PROP_END_OF_LIST(),
120
};
121
122
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data)
123
static const TypeInfo omap2_gpio_info = {
124
.name = TYPE_OMAP2_GPIO,
125
.parent = TYPE_SYS_BUS_DEVICE,
126
- .instance_size = sizeof(struct omap2_gpif_s),
127
+ .instance_size = sizeof(Omap2GpioState),
128
.class_init = omap2_gpio_class_init,
129
};
38
130
39
--
131
--
40
2.20.1
132
2.34.1
41
133
42
134
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
Following docs/devel/style.rst guidelines, rename
4
omap_intr_handler_s -> OMAPIntcState. This also remove a
5
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-7-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/omap.h | 9 ++++-----
13
hw/intc/omap_intc.c | 38 +++++++++++++++++++-------------------
14
2 files changed, 23 insertions(+), 24 deletions(-)
15
16
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/omap.h
19
+++ b/include/hw/arm/omap.h
20
@@ -XXX,XX +XXX,XX @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
21
22
/* omap_intc.c */
23
#define TYPE_OMAP_INTC "common-omap-intc"
24
-typedef struct omap_intr_handler_s omap_intr_handler;
25
-DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
26
- TYPE_OMAP_INTC)
27
+typedef struct OMAPIntcState OMAPIntcState;
28
+DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC)
29
30
31
/*
32
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
33
* (ie the struct omap_mpu_state_s*) to do the clockname to pointer
34
* translation.)
35
*/
36
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
37
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
38
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
39
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk);
40
41
/* omap_i2c.c */
42
#define TYPE_OMAP_I2C "omap_i2c"
43
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/omap_intc.c
46
+++ b/hw/intc/omap_intc.c
47
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_bank_s {
48
unsigned char priority[32];
49
};
50
51
-struct omap_intr_handler_s {
52
+struct OMAPIntcState {
53
SysBusDevice parent_obj;
54
55
qemu_irq *pins;
56
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_s {
57
struct omap_intr_handler_bank_s bank[3];
58
};
59
60
-static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
61
+static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
62
{
63
int i, j, sir_intr, p_intr, p;
64
uint32_t level;
65
@@ -XXX,XX +XXX,XX @@ static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
66
s->sir_intr[is_fiq] = sir_intr;
67
}
68
69
-static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
70
+static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
71
{
72
int i;
73
uint32_t has_intr = 0;
74
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
75
76
static void omap_set_intr(void *opaque, int irq, int req)
77
{
78
- struct omap_intr_handler_s *ih = opaque;
79
+ OMAPIntcState *ih = opaque;
80
uint32_t rise;
81
82
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
83
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
84
/* Simplified version with no edge detection */
85
static void omap_set_intr_noedge(void *opaque, int irq, int req)
86
{
87
- struct omap_intr_handler_s *ih = opaque;
88
+ OMAPIntcState *ih = opaque;
89
uint32_t rise;
90
91
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
92
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
93
static uint64_t omap_inth_read(void *opaque, hwaddr addr,
94
unsigned size)
95
{
96
- struct omap_intr_handler_s *s = opaque;
97
+ OMAPIntcState *s = opaque;
98
int i, offset = addr;
99
int bank_no = offset >> 8;
100
int line_no;
101
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
102
static void omap_inth_write(void *opaque, hwaddr addr,
103
uint64_t value, unsigned size)
104
{
105
- struct omap_intr_handler_s *s = opaque;
106
+ OMAPIntcState *s = opaque;
107
int i, offset = addr;
108
int bank_no = offset >> 8;
109
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
110
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_inth_mem_ops = {
111
112
static void omap_inth_reset(DeviceState *dev)
113
{
114
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
115
+ OMAPIntcState *s = OMAP_INTC(dev);
116
int i;
117
118
for (i = 0; i < s->nbanks; ++i){
119
@@ -XXX,XX +XXX,XX @@ static void omap_inth_reset(DeviceState *dev)
120
static void omap_intc_init(Object *obj)
121
{
122
DeviceState *dev = DEVICE(obj);
123
- struct omap_intr_handler_s *s = OMAP_INTC(obj);
124
+ OMAPIntcState *s = OMAP_INTC(obj);
125
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
126
127
s->nbanks = 1;
128
@@ -XXX,XX +XXX,XX @@ static void omap_intc_init(Object *obj)
129
130
static void omap_intc_realize(DeviceState *dev, Error **errp)
131
{
132
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
133
+ OMAPIntcState *s = OMAP_INTC(dev);
134
135
if (!s->iclk) {
136
error_setg(errp, "omap-intc: clk not connected");
137
}
138
}
139
140
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
141
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk)
142
{
143
intc->iclk = clk;
144
}
145
146
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
147
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk)
148
{
149
intc->fclk = clk;
150
}
151
152
static Property omap_intc_properties[] = {
153
- DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
154
+ DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100),
155
DEFINE_PROP_END_OF_LIST(),
156
};
157
158
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
159
static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
160
unsigned size)
161
{
162
- struct omap_intr_handler_s *s = opaque;
163
+ OMAPIntcState *s = opaque;
164
int offset = addr;
165
int bank_no, line_no;
166
struct omap_intr_handler_bank_s *bank = NULL;
167
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
168
static void omap2_inth_write(void *opaque, hwaddr addr,
169
uint64_t value, unsigned size)
170
{
171
- struct omap_intr_handler_s *s = opaque;
172
+ OMAPIntcState *s = opaque;
173
int offset = addr;
174
int bank_no, line_no;
175
struct omap_intr_handler_bank_s *bank = NULL;
176
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_inth_mem_ops = {
177
static void omap2_intc_init(Object *obj)
178
{
179
DeviceState *dev = DEVICE(obj);
180
- struct omap_intr_handler_s *s = OMAP_INTC(obj);
181
+ OMAPIntcState *s = OMAP_INTC(obj);
182
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
183
184
s->level_only = 1;
185
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_init(Object *obj)
186
187
static void omap2_intc_realize(DeviceState *dev, Error **errp)
188
{
189
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
190
+ OMAPIntcState *s = OMAP_INTC(dev);
191
192
if (!s->iclk) {
193
error_setg(errp, "omap2-intc: iclk not connected");
194
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_realize(DeviceState *dev, Error **errp)
195
}
196
197
static Property omap2_intc_properties[] = {
198
- DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
199
+ DEFINE_PROP_UINT8("revision", OMAPIntcState,
200
revision, 0x21),
201
DEFINE_PROP_END_OF_LIST(),
202
};
203
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap2_intc_info = {
204
static const TypeInfo omap_intc_type_info = {
205
.name = TYPE_OMAP_INTC,
206
.parent = TYPE_SYS_BUS_DEVICE,
207
- .instance_size = sizeof(omap_intr_handler),
208
+ .instance_size = sizeof(OMAPIntcState),
209
.abstract = true,
210
};
211
212
--
213
2.34.1
214
215
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230109140306.23161-8-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/stellaris.c | 6 +++---
9
1 file changed, 3 insertions(+), 3 deletions(-)
10
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/stellaris.c
14
+++ b/hw/arm/stellaris.c
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
16
17
static void stellaris_adc_trigger(void *opaque, int irq, int level)
18
{
19
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
20
+ stellaris_adc_state *s = opaque;
21
int n;
22
23
for (n = 0; n < 4; n++) {
24
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
25
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
26
unsigned size)
27
{
28
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
29
+ stellaris_adc_state *s = opaque;
30
31
/* TODO: Implement this. */
32
if (offset >= 0x40 && offset < 0xc0) {
33
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
34
static void stellaris_adc_write(void *opaque, hwaddr offset,
35
uint64_t value, unsigned size)
36
{
37
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
38
+ stellaris_adc_state *s = opaque;
39
40
/* TODO: Implement this. */
41
if (offset >= 0x40 && offset < 0xc0) {
42
--
43
2.34.1
44
45
diff view generated by jsdifflib
1
The kernel-doc Sphinx plugin and associated script currently emit
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
'c:type' directives for "struct foo" documentation.
3
2
4
Sphinx 3.0 warns about this:
3
Following docs/devel/style.rst guidelines, rename
5
/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:3: WARNING: Type must be either just a name or a typedef-like declaration.
4
stellaris_adc_state -> StellarisADCState. This also remove a
6
If just a name:
5
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
7
Error in declarator or parameters
8
Invalid C declaration: Expected identifier in nested name, got keyword: struct [error at 6]
9
struct MemoryListener
10
------^
11
If typedef-like declaration:
12
Error in declarator or parameters
13
Invalid C declaration: Expected identifier in nested name. [error at 21]
14
struct MemoryListener
15
---------------------^
16
6
17
because it wants us to use the new-in-3.0 'c:struct' instead.
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-9-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/stellaris.c | 73 +++++++++++++++++++++++-----------------------
13
1 file changed, 36 insertions(+), 37 deletions(-)
18
14
19
Plumb the Sphinx version through to the kernel-doc script
15
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
20
and use it to select 'c:struct' for newer versions than 3.0.
21
22
Fixes: LP:1872113
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
25
---
26
docs/sphinx/kerneldoc.py | 1 +
27
scripts/kernel-doc | 16 +++++++++++++++-
28
2 files changed, 16 insertions(+), 1 deletion(-)
29
30
diff --git a/docs/sphinx/kerneldoc.py b/docs/sphinx/kerneldoc.py
31
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
32
--- a/docs/sphinx/kerneldoc.py
17
--- a/hw/arm/stellaris.c
33
+++ b/docs/sphinx/kerneldoc.py
18
+++ b/hw/arm/stellaris.c
34
@@ -XXX,XX +XXX,XX @@ class KernelDocDirective(Directive):
19
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
35
env.note_dependency(os.path.abspath(f))
20
#define STELLARIS_ADC_FIFO_FULL 0x1000
36
cmd += ['-export-file', f]
21
37
22
#define TYPE_STELLARIS_ADC "stellaris-adc"
38
+ cmd += ['-sphinx-version', sphinx.__version__]
23
-typedef struct StellarisADCState stellaris_adc_state;
39
cmd += [filename]
24
-DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
40
25
- TYPE_STELLARIS_ADC)
41
try:
26
+typedef struct StellarisADCState StellarisADCState;
42
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
27
+DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
43
index XXXXXXX..XXXXXXX 100755
28
44
--- a/scripts/kernel-doc
29
struct StellarisADCState {
45
+++ b/scripts/kernel-doc
30
SysBusDevice parent_obj;
46
@@ -XXX,XX +XXX,XX @@ Output selection (mutually exclusive):
31
@@ -XXX,XX +XXX,XX @@ struct StellarisADCState {
47
            DOC: sections. May be specified multiple times.
32
qemu_irq irq[4];
48
49
Output selection modifiers:
50
+ -sphinx-version VER Generate rST syntax for the specified Sphinx version.
51
+ Only works with reStructuredTextFormat.
52
-no-doc-sections    Do not output DOC: sections.
53
-enable-lineno Enable output of #define LINENO lines. Only works with
54
reStructuredText format.
55
@@ -XXX,XX +XXX,XX @@ use constant {
56
};
33
};
57
my $output_selection = OUTPUT_ALL;
34
58
my $show_not_found = 0;    # No longer used
35
-static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
59
+my $sphinx_version = "0.0"; # if not specified, assume old
36
+static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
60
37
{
61
my @export_file_list;
38
int tail;
62
39
63
@@ -XXX,XX +XXX,XX @@ while ($ARGV[0] =~ m/^--?(.*)/) {
40
@@ -XXX,XX +XXX,XX @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
64
     $enable_lineno = 1;
41
return s->fifo[n].data[tail];
65
} elsif ($cmd eq 'show-not-found') {
42
}
66
    $show_not_found = 1; # A no-op but don't fail
43
67
+ } elsif ($cmd eq 'sphinx-version') {
44
-static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
68
+ $sphinx_version = shift @ARGV;
45
+static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
69
} else {
46
uint32_t value)
70
    # Unknown argument
47
{
71
usage();
48
int head;
72
@@ -XXX,XX +XXX,XX @@ sub output_struct_rst(%) {
49
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
73
my $oldprefix = $lineprefix;
50
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
74
my $name = $args{'type'} . " " . $args{'struct'};
51
}
75
52
76
- print "\n\n.. c:type:: " . $name . "\n\n";
53
-static void stellaris_adc_update(stellaris_adc_state *s)
77
+ # Sphinx 3.0 and up will emit warnings for "c:type:: struct Foo".
54
+static void stellaris_adc_update(StellarisADCState *s)
78
+ # It wants to see "c:struct:: Foo" (and will add the word 'struct' in
55
{
79
+ # the rendered output).
56
int level;
80
+ if ((split(/\./, $sphinx_version))[0] >= 3) {
57
int n;
81
+ my $sname = $name;
58
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
82
+ $sname =~ s/^struct //;
59
83
+ print "\n\n.. c:struct:: " . $sname . "\n\n";
60
static void stellaris_adc_trigger(void *opaque, int irq, int level)
84
+ } else {
61
{
85
+ print "\n\n.. c:type:: " . $name . "\n\n";
62
- stellaris_adc_state *s = opaque;
86
+ }
63
+ StellarisADCState *s = opaque;
87
print_lineno($declaration_start_line);
64
int n;
88
$lineprefix = " ";
65
89
output_highlight_rst($args{'purpose'});
66
for (n = 0; n < 4; n++) {
67
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
68
}
69
}
70
71
-static void stellaris_adc_reset(stellaris_adc_state *s)
72
+static void stellaris_adc_reset(StellarisADCState *s)
73
{
74
int n;
75
76
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
77
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
78
unsigned size)
79
{
80
- stellaris_adc_state *s = opaque;
81
+ StellarisADCState *s = opaque;
82
83
/* TODO: Implement this. */
84
if (offset >= 0x40 && offset < 0xc0) {
85
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
86
static void stellaris_adc_write(void *opaque, hwaddr offset,
87
uint64_t value, unsigned size)
88
{
89
- stellaris_adc_state *s = opaque;
90
+ StellarisADCState *s = opaque;
91
92
/* TODO: Implement this. */
93
if (offset >= 0x40 && offset < 0xc0) {
94
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
95
.version_id = 1,
96
.minimum_version_id = 1,
97
.fields = (VMStateField[]) {
98
- VMSTATE_UINT32(actss, stellaris_adc_state),
99
- VMSTATE_UINT32(ris, stellaris_adc_state),
100
- VMSTATE_UINT32(im, stellaris_adc_state),
101
- VMSTATE_UINT32(emux, stellaris_adc_state),
102
- VMSTATE_UINT32(ostat, stellaris_adc_state),
103
- VMSTATE_UINT32(ustat, stellaris_adc_state),
104
- VMSTATE_UINT32(sspri, stellaris_adc_state),
105
- VMSTATE_UINT32(sac, stellaris_adc_state),
106
- VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
107
- VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
108
- VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
109
- VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
110
- VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
111
- VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
112
- VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
113
- VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
114
- VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
115
- VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
116
- VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
117
- VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
118
- VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
119
- VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
120
- VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
121
- VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
122
- VMSTATE_UINT32(noise, stellaris_adc_state),
123
+ VMSTATE_UINT32(actss, StellarisADCState),
124
+ VMSTATE_UINT32(ris, StellarisADCState),
125
+ VMSTATE_UINT32(im, StellarisADCState),
126
+ VMSTATE_UINT32(emux, StellarisADCState),
127
+ VMSTATE_UINT32(ostat, StellarisADCState),
128
+ VMSTATE_UINT32(ustat, StellarisADCState),
129
+ VMSTATE_UINT32(sspri, StellarisADCState),
130
+ VMSTATE_UINT32(sac, StellarisADCState),
131
+ VMSTATE_UINT32(fifo[0].state, StellarisADCState),
132
+ VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
133
+ VMSTATE_UINT32(ssmux[0], StellarisADCState),
134
+ VMSTATE_UINT32(ssctl[0], StellarisADCState),
135
+ VMSTATE_UINT32(fifo[1].state, StellarisADCState),
136
+ VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
137
+ VMSTATE_UINT32(ssmux[1], StellarisADCState),
138
+ VMSTATE_UINT32(ssctl[1], StellarisADCState),
139
+ VMSTATE_UINT32(fifo[2].state, StellarisADCState),
140
+ VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
141
+ VMSTATE_UINT32(ssmux[2], StellarisADCState),
142
+ VMSTATE_UINT32(ssctl[2], StellarisADCState),
143
+ VMSTATE_UINT32(fifo[3].state, StellarisADCState),
144
+ VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
145
+ VMSTATE_UINT32(ssmux[3], StellarisADCState),
146
+ VMSTATE_UINT32(ssctl[3], StellarisADCState),
147
+ VMSTATE_UINT32(noise, StellarisADCState),
148
VMSTATE_END_OF_LIST()
149
}
150
};
151
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
152
static void stellaris_adc_init(Object *obj)
153
{
154
DeviceState *dev = DEVICE(obj);
155
- stellaris_adc_state *s = STELLARIS_ADC(obj);
156
+ StellarisADCState *s = STELLARIS_ADC(obj);
157
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
158
int n;
159
160
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
161
static const TypeInfo stellaris_adc_info = {
162
.name = TYPE_STELLARIS_ADC,
163
.parent = TYPE_SYS_BUS_DEVICE,
164
- .instance_size = sizeof(stellaris_adc_state),
165
+ .instance_size = sizeof(StellarisADCState),
166
.instance_init = stellaris_adc_init,
167
.class_init = stellaris_adc_class_init,
168
};
90
--
169
--
91
2.20.1
170
2.34.1
92
171
93
172
diff view generated by jsdifflib
1
When kernel-doc generates a 'c:function' directive for a function
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
one of whose arguments is a function pointer, it fails to print
3
the close-paren after the argument list of the function pointer
4
argument, for instance in the memory API documentation:
5
.. c:function:: void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp)
6
2
7
which should have a ')' after the 'void *host' which is the
3
The typedef and definitions are generated by the OBJECT_DECLARE_TYPE
8
last argument to 'resized'.
4
macro in "hw/arm/bcm2836.h":
9
5
10
Older versions of Sphinx don't try to parse the argumnet
6
20 #define TYPE_BCM283X "bcm283x"
11
to c:function, but Sphinx 3.0 does do this and will complain:
7
21 OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
12
8
13
/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:834: WARNING: Error in declarator or parameters
9
The script ran in commit a489d1951c ("Use OBJECT_DECLARE_TYPE when
14
Invalid C declaration: Expecting "," or ")" in parameters, got "EOF". [error at 208]
10
possible") missed them because they are declared in a different
15
void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp)
11
file unit. Remove them.
16
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------^
17
12
18
Add the missing close-paren.
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230109140306.23161-10-philmd@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/arm/bcm2836.c | 9 ++-------
19
1 file changed, 2 insertions(+), 7 deletions(-)
19
20
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
index XXXXXXX..XXXXXXX 100644
22
Message-id: 20200411182934.28678-3-peter.maydell@linaro.org
23
--- a/hw/arm/bcm2836.c
23
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
24
+++ b/hw/arm/bcm2836.c
24
---
25
@@ -XXX,XX +XXX,XX @@
25
scripts/kernel-doc | 2 +-
26
#include "hw/arm/raspi_platform.h"
26
1 file changed, 1 insertion(+), 1 deletion(-)
27
#include "hw/sysbus.h"
27
28
28
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
29
-typedef struct BCM283XClass {
29
index XXXXXXX..XXXXXXX 100755
30
+struct BCM283XClass {
30
--- a/scripts/kernel-doc
31
/*< private >*/
31
+++ b/scripts/kernel-doc
32
DeviceClass parent_class;
32
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
33
/*< public >*/
33
34
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass {
34
    if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
35
hwaddr peri_base; /* Peripheral base address seen by the CPU */
35
     # pointer-to-function
36
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
36
-     print $1 . $parameter . ") (" . $2;
37
int clusterid;
37
+     print $1 . $parameter . ") (" . $2 . ")";
38
-} BCM283XClass;
38
    } else {
39
-
39
     print $type . " " . $parameter;
40
-#define BCM283X_CLASS(klass) \
40
    }
41
- OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
42
-#define BCM283X_GET_CLASS(obj) \
43
- OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
44
+};
45
46
static Property bcm2836_enabled_cores_property =
47
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
41
--
48
--
42
2.20.1
49
2.34.1
43
50
44
51
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
NPCM7XX models have been commited after the conversion from
4
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
5
Manually convert them.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-11-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/adc/npcm7xx_adc.h | 7 +++----
13
include/hw/arm/npcm7xx.h | 18 ++++++------------
14
include/hw/i2c/npcm7xx_smbus.h | 7 +++----
15
include/hw/misc/npcm7xx_clk.h | 2 +-
16
include/hw/misc/npcm7xx_gcr.h | 6 +++---
17
include/hw/misc/npcm7xx_mft.h | 7 +++----
18
include/hw/misc/npcm7xx_pwm.h | 3 +--
19
include/hw/misc/npcm7xx_rng.h | 6 +++---
20
include/hw/net/npcm7xx_emc.h | 5 +----
21
include/hw/sd/npcm7xx_sdhci.h | 4 ++--
22
10 files changed, 26 insertions(+), 39 deletions(-)
23
24
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/adc/npcm7xx_adc.h
27
+++ b/include/hw/adc/npcm7xx_adc.h
28
@@ -XXX,XX +XXX,XX @@
29
* @iref: The internal reference voltage, initialized at launch time.
30
* @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
31
*/
32
-typedef struct {
33
+struct NPCM7xxADCState {
34
SysBusDevice parent;
35
36
MemoryRegion iomem;
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
uint32_t iref;
39
40
uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
41
-} NPCM7xxADCState;
42
+};
43
44
#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
45
-#define NPCM7XX_ADC(obj) \
46
- OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
47
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
48
49
#endif /* NPCM7XX_ADC_H */
50
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/include/hw/arm/npcm7xx.h
53
+++ b/include/hw/arm/npcm7xx.h
54
@@ -XXX,XX +XXX,XX @@
55
56
#define NPCM7XX_NR_PWM_MODULES 2
57
58
-typedef struct NPCM7xxMachine {
59
+struct NPCM7xxMachine {
60
MachineState parent;
61
/*
62
* PWM fan splitter. each splitter connects to one PWM output and
63
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachine {
64
*/
65
SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES *
66
NPCM7XX_PWM_PER_MODULE];
67
-} NPCM7xxMachine;
68
+};
69
70
#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
71
-#define NPCM7XX_MACHINE(obj) \
72
- OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
73
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
74
75
typedef struct NPCM7xxMachineClass {
76
MachineClass parent;
77
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachineClass {
78
#define NPCM7XX_MACHINE_GET_CLASS(obj) \
79
OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
80
81
-typedef struct NPCM7xxState {
82
+struct NPCM7xxState {
83
DeviceState parent;
84
85
ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
86
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
87
NPCM7xxFIUState fiu[2];
88
NPCM7xxEMCState emc[2];
89
NPCM7xxSDHCIState mmc;
90
-} NPCM7xxState;
91
+};
92
93
#define TYPE_NPCM7XX "npcm7xx"
94
-#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
95
+OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
96
97
#define TYPE_NPCM730 "npcm730"
98
#define TYPE_NPCM750 "npcm750"
99
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxClass {
100
uint32_t num_cpus;
101
} NPCM7xxClass;
102
103
-#define NPCM7XX_CLASS(klass) \
104
- OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
105
-#define NPCM7XX_GET_CLASS(obj) \
106
- OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
107
-
108
/**
109
* npcm7xx_load_kernel - Loads memory with everything needed to boot
110
* @machine - The machine containing the SoC to be booted.
111
diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/include/hw/i2c/npcm7xx_smbus.h
114
+++ b/include/hw/i2c/npcm7xx_smbus.h
115
@@ -XXX,XX +XXX,XX @@ typedef enum NPCM7xxSMBusStatus {
116
* @rx_cur: The current position of rx_fifo.
117
* @status: The current status of the SMBus.
118
*/
119
-typedef struct NPCM7xxSMBusState {
120
+struct NPCM7xxSMBusState {
121
SysBusDevice parent;
122
123
MemoryRegion iomem;
124
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSMBusState {
125
uint8_t rx_cur;
126
127
NPCM7xxSMBusStatus status;
128
-} NPCM7xxSMBusState;
129
+};
130
131
#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
132
-#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
133
- TYPE_NPCM7XX_SMBUS)
134
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
135
136
#endif /* NPCM7XX_SMBUS_H */
137
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/misc/npcm7xx_clk.h
140
+++ b/include/hw/misc/npcm7xx_clk.h
141
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxCLKState {
142
};
143
144
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
145
-#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
146
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
147
148
#endif /* NPCM7XX_CLK_H */
149
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
150
index XXXXXXX..XXXXXXX 100644
151
--- a/include/hw/misc/npcm7xx_gcr.h
152
+++ b/include/hw/misc/npcm7xx_gcr.h
153
@@ -XXX,XX +XXX,XX @@
154
*/
155
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
156
157
-typedef struct NPCM7xxGCRState {
158
+struct NPCM7xxGCRState {
159
SysBusDevice parent;
160
161
MemoryRegion iomem;
162
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxGCRState {
163
uint32_t reset_pwron;
164
uint32_t reset_mdlr;
165
uint32_t reset_intcr3;
166
-} NPCM7xxGCRState;
167
+};
168
169
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
170
-#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
171
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
172
173
#endif /* NPCM7XX_GCR_H */
174
diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h
175
index XXXXXXX..XXXXXXX 100644
176
--- a/include/hw/misc/npcm7xx_mft.h
177
+++ b/include/hw/misc/npcm7xx_mft.h
178
@@ -XXX,XX +XXX,XX @@
179
* @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
180
* @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
181
*/
182
-typedef struct NPCM7xxMFTState {
183
+struct NPCM7xxMFTState {
184
SysBusDevice parent;
185
186
MemoryRegion iomem;
187
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMFTState {
188
189
uint32_t max_rpm[NPCM7XX_MFT_FANIN_COUNT];
190
uint32_t duty[NPCM7XX_MFT_FANIN_COUNT];
191
-} NPCM7xxMFTState;
192
+};
193
194
#define TYPE_NPCM7XX_MFT "npcm7xx-mft"
195
-#define NPCM7XX_MFT(obj) \
196
- OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
197
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT)
198
199
#endif /* NPCM7XX_MFT_H */
200
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
201
index XXXXXXX..XXXXXXX 100644
202
--- a/include/hw/misc/npcm7xx_pwm.h
203
+++ b/include/hw/misc/npcm7xx_pwm.h
204
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxPWMState {
205
};
206
207
#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
208
-#define NPCM7XX_PWM(obj) \
209
- OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
210
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
211
212
#endif /* NPCM7XX_PWM_H */
213
diff --git a/include/hw/misc/npcm7xx_rng.h b/include/hw/misc/npcm7xx_rng.h
214
index XXXXXXX..XXXXXXX 100644
215
--- a/include/hw/misc/npcm7xx_rng.h
216
+++ b/include/hw/misc/npcm7xx_rng.h
217
@@ -XXX,XX +XXX,XX @@
218
219
#include "hw/sysbus.h"
220
221
-typedef struct NPCM7xxRNGState {
222
+struct NPCM7xxRNGState {
223
SysBusDevice parent;
224
225
MemoryRegion iomem;
226
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRNGState {
227
uint8_t rngcs;
228
uint8_t rngd;
229
uint8_t rngmode;
230
-} NPCM7xxRNGState;
231
+};
232
233
#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
234
-#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
235
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG)
236
237
#endif /* NPCM7XX_RNG_H */
238
diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h
239
index XXXXXXX..XXXXXXX 100644
240
--- a/include/hw/net/npcm7xx_emc.h
241
+++ b/include/hw/net/npcm7xx_emc.h
242
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxEMCState {
243
bool rx_active;
244
};
245
246
-typedef struct NPCM7xxEMCState NPCM7xxEMCState;
247
-
248
#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
249
-#define NPCM7XX_EMC(obj) \
250
- OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
251
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
252
253
#endif /* NPCM7XX_EMC_H */
254
diff --git a/include/hw/sd/npcm7xx_sdhci.h b/include/hw/sd/npcm7xx_sdhci.h
255
index XXXXXXX..XXXXXXX 100644
256
--- a/include/hw/sd/npcm7xx_sdhci.h
257
+++ b/include/hw/sd/npcm7xx_sdhci.h
258
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRegs {
259
uint32_t boottoctrl;
260
} NPCM7xxRegisters;
261
262
-typedef struct NPCM7xxSDHCIState {
263
+struct NPCM7xxSDHCIState {
264
SysBusDevice parent;
265
266
MemoryRegion container;
267
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSDHCIState {
268
NPCM7xxRegisters regs;
269
270
SDHCIState sdhci;
271
-} NPCM7xxSDHCIState;
272
+};
273
274
#endif /* NPCM7XX_SDHCI_H */
275
--
276
2.34.1
277
278
diff view generated by jsdifflib
1
If we are not making warnings fatal for compilation, make them
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
non-fatal when building the Sphinx documentation also. (For instance
3
Sphinx 3.0 warns about some constructs that older versions were happy
4
with, which is a build failure if we use the warnings-as-errors
5
flag.)
6
2
7
This provides a workaround at least for LP:1872113.
3
The structure is named SECUREECState. Rename the type accordingly.
8
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20230109140306.23161-12-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200411182934.28678-2-peter.maydell@linaro.org
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
---
9
---
14
configure | 9 ++++++++-
10
hw/misc/sbsa_ec.c | 13 +++++++------
15
Makefile | 2 +-
11
1 file changed, 7 insertions(+), 6 deletions(-)
16
2 files changed, 9 insertions(+), 2 deletions(-)
17
12
18
diff --git a/configure b/configure
13
diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
19
index XXXXXXX..XXXXXXX 100755
14
index XXXXXXX..XXXXXXX 100644
20
--- a/configure
15
--- a/hw/misc/sbsa_ec.c
21
+++ b/configure
16
+++ b/hw/misc/sbsa_ec.c
22
@@ -XXX,XX +XXX,XX @@ if check_include sys/kcov.h ; then
17
@@ -XXX,XX +XXX,XX @@
23
kcov=yes
18
#include "hw/sysbus.h"
24
fi
19
#include "sysemu/runstate.h"
25
20
26
+# If we're making warnings fatal, apply this to Sphinx runs as well
21
-typedef struct {
27
+sphinx_werror=""
22
+typedef struct SECUREECState {
28
+if test "$werror" = "yes"; then
23
SysBusDevice parent_obj;
29
+ sphinx_werror="-W"
24
MemoryRegion iomem;
30
+fi
25
} SECUREECState;
31
+
26
32
# Check we have a new enough version of sphinx-build
27
-#define TYPE_SBSA_EC "sbsa-ec"
33
has_sphinx_build() {
28
-#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC)
34
# This is a bit awkward but works: create a trivial document and
29
+#define TYPE_SBSA_SECURE_EC "sbsa-ec"
35
@@ -XXX,XX +XXX,XX @@ has_sphinx_build() {
30
+#define SBSA_SECURE_EC(obj) \
36
# sphinx-build doesn't exist at all or if it is too old.
31
+ OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
37
mkdir -p "$TMPDIR1/sphinx"
32
38
touch "$TMPDIR1/sphinx/index.rst"
33
enum sbsa_ec_powerstates {
39
- "$sphinx_build" -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1
34
SBSA_EC_CMD_POWEROFF = 0x01,
40
+ "$sphinx_build" $sphinx_werror -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1
35
@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size)
41
}
36
}
42
37
43
# Check if tools are available to build documentation.
38
static void sbsa_ec_write(void *opaque, hwaddr offset,
44
@@ -XXX,XX +XXX,XX @@ echo "INSTALL_PROG=$install -c -m 0755" >> $config_host_mak
39
- uint64_t value, unsigned size)
45
echo "INSTALL_LIB=$install -c -m 0644" >> $config_host_mak
40
+ uint64_t value, unsigned size)
46
echo "PYTHON=$python" >> $config_host_mak
41
{
47
echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak
42
if (offset == 0) { /* PSCI machine power command register */
48
+echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak
43
switch (value) {
49
echo "GENISOIMAGE=$genisoimage" >> $config_host_mak
44
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sbsa_ec_ops = {
50
echo "CC=$cc" >> $config_host_mak
45
51
if $iasl -h > /dev/null 2>&1; then
46
static void sbsa_ec_init(Object *obj)
52
diff --git a/Makefile b/Makefile
47
{
53
index XXXXXXX..XXXXXXX 100644
48
- SECUREECState *s = SECURE_EC(obj);
54
--- a/Makefile
49
+ SECUREECState *s = SBSA_SECURE_EC(obj);
55
+++ b/Makefile
50
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
56
@@ -XXX,XX +XXX,XX @@ sphinxdocs: $(MANUAL_BUILDDIR)/devel/index.html \
51
57
# Note the use of different doctree for each (manual, builder) tuple;
52
memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec",
58
# this works around Sphinx not handling parallel invocation on
53
@@ -XXX,XX +XXX,XX @@ static void sbsa_ec_class_init(ObjectClass *klass, void *data)
59
# a single doctree: https://github.com/sphinx-doc/sphinx/issues/2946
54
}
60
-build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) -W -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1")
55
61
+build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) $(SPHINX_WERROR) -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1")
56
static const TypeInfo sbsa_ec_info = {
62
# We assume all RST files in the manual's directory are used in it
57
- .name = TYPE_SBSA_EC,
63
manual-deps = $(wildcard $(SRC_PATH)/docs/$1/*.rst $(SRC_PATH)/docs/$1/*/*.rst) \
58
+ .name = TYPE_SBSA_SECURE_EC,
64
$(SRC_PATH)/docs/defs.rst.inc \
59
.parent = TYPE_SYS_BUS_DEVICE,
60
.instance_size = sizeof(SECUREECState),
61
.instance_init = sbsa_ec_init,
65
--
62
--
66
2.20.1
63
2.34.1
67
64
68
65
diff view generated by jsdifflib
1
Add support for running the Coverity Scan tools inside a Docker
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
container rather than directly on the host system.
3
2
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
This model was merged few days before the QOM cleanup from
4
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible")
5
was pulled and merged. Manually adapt.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-13-philmd@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Message-id: 20200319193323.2038-7-peter.maydell@linaro.org
7
---
11
---
8
scripts/coverity-scan/coverity-scan.docker | 131 +++++++++++++++++++++
12
hw/misc/sbsa_ec.c | 3 +--
9
scripts/coverity-scan/run-coverity-scan | 90 ++++++++++++++
13
1 file changed, 1 insertion(+), 2 deletions(-)
10
2 files changed, 221 insertions(+)
11
create mode 100644 scripts/coverity-scan/coverity-scan.docker
12
14
13
diff --git a/scripts/coverity-scan/coverity-scan.docker b/scripts/coverity-scan/coverity-scan.docker
15
diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
14
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX
17
--- a/hw/misc/sbsa_ec.c
16
--- /dev/null
18
+++ b/hw/misc/sbsa_ec.c
17
+++ b/scripts/coverity-scan/coverity-scan.docker
19
@@ -XXX,XX +XXX,XX @@ typedef struct SECUREECState {
18
@@ -XXX,XX +XXX,XX @@
20
} SECUREECState;
19
+# syntax=docker/dockerfile:1.0.0-experimental
21
20
+#
22
#define TYPE_SBSA_SECURE_EC "sbsa-ec"
21
+# Docker setup for running the "Coverity Scan" tools over the source
23
-#define SBSA_SECURE_EC(obj) \
22
+# tree and uploading them to the website, as per
24
- OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
23
+# https://scan.coverity.com/projects/qemu/builds/new
25
+OBJECT_DECLARE_SIMPLE_TYPE(SECUREECState, SBSA_SECURE_EC)
24
+# We do this on a fixed config (currently Fedora 30 with a known
26
25
+# set of dependencies and a configure command that enables a specific
27
enum sbsa_ec_powerstates {
26
+# set of options) so that random changes don't result in our accidentally
28
SBSA_EC_CMD_POWEROFF = 0x01,
27
+# dropping some files from the scan.
28
+#
29
+# We don't build on top of the fedora.docker file because we don't
30
+# want to accidentally change or break the scan config when that
31
+# is updated.
32
+
33
+# The work of actually doing the build is handled by the
34
+# run-coverity-scan script.
35
+
36
+FROM fedora:30
37
+ENV PACKAGES \
38
+ alsa-lib-devel \
39
+ bc \
40
+ bison \
41
+ brlapi-devel \
42
+ bzip2 \
43
+ bzip2-devel \
44
+ ccache \
45
+ clang \
46
+ curl \
47
+ cyrus-sasl-devel \
48
+ dbus-daemon \
49
+ device-mapper-multipath-devel \
50
+ findutils \
51
+ flex \
52
+ gcc \
53
+ gcc-c++ \
54
+ gettext \
55
+ git \
56
+ glib2-devel \
57
+ glusterfs-api-devel \
58
+ gnutls-devel \
59
+ gtk3-devel \
60
+ hostname \
61
+ libaio-devel \
62
+ libasan \
63
+ libattr-devel \
64
+ libblockdev-mpath-devel \
65
+ libcap-devel \
66
+ libcap-ng-devel \
67
+ libcurl-devel \
68
+ libepoxy-devel \
69
+ libfdt-devel \
70
+ libgbm-devel \
71
+ libiscsi-devel \
72
+ libjpeg-devel \
73
+ libpmem-devel \
74
+ libnfs-devel \
75
+ libpng-devel \
76
+ librbd-devel \
77
+ libseccomp-devel \
78
+ libssh-devel \
79
+ libubsan \
80
+ libudev-devel \
81
+ libusbx-devel \
82
+ libxml2-devel \
83
+ libzstd-devel \
84
+ llvm \
85
+ lzo-devel \
86
+ make \
87
+ mingw32-bzip2 \
88
+ mingw32-curl \
89
+ mingw32-glib2 \
90
+ mingw32-gmp \
91
+ mingw32-gnutls \
92
+ mingw32-gtk3 \
93
+ mingw32-libjpeg-turbo \
94
+ mingw32-libpng \
95
+ mingw32-libtasn1 \
96
+ mingw32-nettle \
97
+ mingw32-nsis \
98
+ mingw32-pixman \
99
+ mingw32-pkg-config \
100
+ mingw32-SDL2 \
101
+ mingw64-bzip2 \
102
+ mingw64-curl \
103
+ mingw64-glib2 \
104
+ mingw64-gmp \
105
+ mingw64-gnutls \
106
+ mingw64-gtk3 \
107
+ mingw64-libjpeg-turbo \
108
+ mingw64-libpng \
109
+ mingw64-libtasn1 \
110
+ mingw64-nettle \
111
+ mingw64-pixman \
112
+ mingw64-pkg-config \
113
+ mingw64-SDL2 \
114
+ ncurses-devel \
115
+ nettle-devel \
116
+ nss-devel \
117
+ numactl-devel \
118
+ perl \
119
+ perl-Test-Harness \
120
+ pixman-devel \
121
+ pulseaudio-libs-devel \
122
+ python3 \
123
+ python3-sphinx \
124
+ PyYAML \
125
+ rdma-core-devel \
126
+ SDL2-devel \
127
+ snappy-devel \
128
+ sparse \
129
+ spice-server-devel \
130
+ systemd-devel \
131
+ systemtap-sdt-devel \
132
+ tar \
133
+ texinfo \
134
+ usbredir-devel \
135
+ virglrenderer-devel \
136
+ vte291-devel \
137
+ wget \
138
+ which \
139
+ xen-devel \
140
+ xfsprogs-devel \
141
+ zlib-devel
142
+ENV QEMU_CONFIGURE_OPTS --python=/usr/bin/python3
143
+
144
+RUN dnf install -y $PACKAGES
145
+RUN rpm -q $PACKAGES | sort > /packages.txt
146
+ENV PATH $PATH:/usr/libexec/python3-sphinx/
147
+ENV COVERITY_TOOL_BASE=/coverity-tools
148
+COPY run-coverity-scan run-coverity-scan
149
+RUN --mount=type=secret,id=coverity.token,required ./run-coverity-scan --update-tools-only --tokenfile /run/secrets/coverity.token
150
diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan
151
index XXXXXXX..XXXXXXX 100755
152
--- a/scripts/coverity-scan/run-coverity-scan
153
+++ b/scripts/coverity-scan/run-coverity-scan
154
@@ -XXX,XX +XXX,XX @@
155
156
# Command line options:
157
# --dry-run : run the tools, but don't actually do the upload
158
+# --docker : create and work inside a docker container
159
# --update-tools-only : update the cached copy of the tools, but don't run them
160
# --tokenfile : file to read Coverity token from
161
# --version ver : specify version being analyzed (default: ask git)
162
@@ -XXX,XX +XXX,XX @@
163
# --srcdir : QEMU source tree to analyze (default: current working dir)
164
# --results-tarball : path to copy the results tarball to (default: don't
165
# copy it anywhere, just upload it)
166
+# --src-tarball : tarball to untar into src dir (default: none); this
167
+# is intended mainly for internal use by the Docker support
168
#
169
# User-specifiable environment variables:
170
# COVERITY_TOKEN -- Coverity token
171
@@ -XXX,XX +XXX,XX @@ update_coverity_tools () {
172
# Check user-provided environment variables and arguments
173
DRYRUN=no
174
UPDATE_ONLY=no
175
+DOCKER=no
176
177
while [ "$#" -ge 1 ]; do
178
case "$1" in
179
@@ -XXX,XX +XXX,XX @@ while [ "$#" -ge 1 ]; do
180
RESULTSTARBALL="$1"
181
shift
182
;;
183
+ --src-tarball)
184
+ shift
185
+ if [ $# -eq 0 ]; then
186
+ echo "--src-tarball needs an argument"
187
+ exit 1
188
+ fi
189
+ SRCTARBALL="$1"
190
+ shift
191
+ ;;
192
+ --docker)
193
+ DOCKER=yes
194
+ shift
195
+ ;;
196
*)
197
echo "Unexpected argument '$1'"
198
exit 1
199
@@ -XXX,XX +XXX,XX @@ PROJTOKEN="$COVERITY_TOKEN"
200
PROJNAME=QEMU
201
TARBALL=cov-int.tar.xz
202
203
+if [ "$UPDATE_ONLY" = yes ] && [ "$DOCKER" = yes ]; then
204
+ echo "Combining --docker and --update-only is not supported"
205
+ exit 1
206
+fi
207
208
if [ "$UPDATE_ONLY" = yes ]; then
209
# Just do the tools update; we don't need to check whether
210
@@ -XXX,XX +XXX,XX @@ if [ "$UPDATE_ONLY" = yes ]; then
211
exit 0
212
fi
213
214
+if [ ! -e "$SRCDIR" ]; then
215
+ mkdir "$SRCDIR"
216
+fi
217
+
218
cd "$SRCDIR"
219
220
+if [ ! -z "$SRCTARBALL" ]; then
221
+ echo "Untarring source tarball into $SRCDIR..."
222
+ tar xvf "$SRCTARBALL"
223
+fi
224
+
225
echo "Checking this is a QEMU source tree..."
226
if ! [ -e "$SRCDIR/VERSION" ]; then
227
echo "Not in a QEMU source tree?"
228
@@ -XXX,XX +XXX,XX @@ if [ -z "$COVERITY_EMAIL" ]; then
229
COVERITY_EMAIL="$(git config user.email)"
230
fi
231
232
+# Run ourselves inside docker if that's what the user wants
233
+if [ "$DOCKER" = yes ]; then
234
+ # build docker container including the coverity-scan tools
235
+ # Put the Coverity token into a temporary file that only
236
+ # we have read access to, and then pass it to docker build
237
+ # using --secret. This requires at least Docker 18.09.
238
+ # Mostly what we are trying to do here is ensure we don't leak
239
+ # the token into the Docker image.
240
+ umask 077
241
+ SECRETDIR=$(mktemp -d)
242
+ if [ -z "$SECRETDIR" ]; then
243
+ echo "Failed to create temporary directory"
244
+ exit 1
245
+ fi
246
+ trap 'rm -rf "$SECRETDIR"' INT TERM EXIT
247
+ echo "Created temporary directory $SECRETDIR"
248
+ SECRET="$SECRETDIR/token"
249
+ echo "$COVERITY_TOKEN" > "$SECRET"
250
+ echo "Building docker container..."
251
+ # TODO: This re-downloads the tools every time, rather than
252
+ # caching and reusing the image produced with the downloaded tools.
253
+ # Not sure why.
254
+ # TODO: how do you get 'docker build' to print the output of the
255
+ # commands it is running to its stdout? This would be useful for debug.
256
+ DOCKER_BUILDKIT=1 docker build -t coverity-scanner \
257
+ --secret id=coverity.token,src="$SECRET" \
258
+ -f scripts/coverity-scan/coverity-scan.docker \
259
+ scripts/coverity-scan
260
+ echo "Archiving sources to be analyzed..."
261
+ ./scripts/archive-source.sh "$SECRETDIR/qemu-sources.tgz"
262
+ if [ "$DRYRUN" = yes ]; then
263
+ DRYRUNARG=--dry-run
264
+ fi
265
+ echo "Running scanner..."
266
+ # If we need to capture the output tarball, get the inner run to
267
+ # save it to the secrets directory so we can copy it out before the
268
+ # directory is cleaned up.
269
+ if [ ! -z "$RESULTSTARBALL" ]; then
270
+ RTARGS="--results-tarball /work/cov-int.tar.xz"
271
+ else
272
+ RTARGS=""
273
+ fi
274
+ # Arrange for this docker run to get access to the sources with -v.
275
+ # We pass through all the configuration from the outer script to the inner.
276
+ export COVERITY_EMAIL COVERITY_BUILD_CMD
277
+ docker run -it --env COVERITY_EMAIL --env COVERITY_BUILD_CMD \
278
+ -v "$SECRETDIR:/work" coverity-scanner \
279
+ ./run-coverity-scan --version "$VERSION" \
280
+ --description "$DESCRIPTION" $DRYRUNARG --tokenfile /work/token \
281
+ --srcdir /qemu --src-tarball /work/qemu-sources.tgz $RTARGS
282
+ if [ ! -z "$RESULTSTARBALL" ]; then
283
+ echo "Copying results tarball to $RESULTSTARBALL..."
284
+ cp "$SECRETDIR/cov-int.tar.xz" "$RESULTSTARBALL"
285
+ fi
286
+ echo "Docker work complete."
287
+ exit 0
288
+fi
289
+
290
+# Otherwise, continue with the full build and upload process.
291
+
292
check_upload_permissions
293
294
update_coverity_tools
295
--
29
--
296
2.20.1
30
2.34.1
297
31
298
32
diff view generated by jsdifflib
1
All the Coverity-specific definitions of qemu_mutex_lock() and friends
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
have a trailing semicolon. This works fine almost everywhere because
3
of QEMU's mandatory-braces coding style and because most callsites are
4
simple, but target/s390x/sigp.c has a use of qemu_mutex_trylock() as
5
an if() statement, which makes the ';' a syntax error:
6
"../target/s390x/sigp.c", line 461: warning #18: expected a ")"
7
if (qemu_mutex_trylock(&qemu_sigp_mutex)) {
8
^
9
2
10
Remove the bogus semicolons from the macro definitions.
3
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
4
macro call, to avoid after a QOM refactor:
11
5
6
hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a definition
7
DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
8
^
9
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
13
Message-id: 20230109140306.23161-14-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20200319193323.2038-4-peter.maydell@linaro.org
16
---
15
---
17
include/qemu/thread.h | 12 ++++++------
16
hw/intc/xilinx_intc.c | 28 +++++++++++++---------------
18
1 file changed, 6 insertions(+), 6 deletions(-)
17
1 file changed, 13 insertions(+), 15 deletions(-)
19
18
20
diff --git a/include/qemu/thread.h b/include/qemu/thread.h
19
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/include/qemu/thread.h
21
--- a/hw/intc/xilinx_intc.c
23
+++ b/include/qemu/thread.h
22
+++ b/hw/intc/xilinx_intc.c
24
@@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func;
23
@@ -XXX,XX +XXX,XX @@
25
* hide them.
24
#define R_MAX 8
26
*/
25
27
#define qemu_mutex_lock(m) \
26
#define TYPE_XILINX_INTC "xlnx.xps-intc"
28
- qemu_mutex_lock_impl(m, __FILE__, __LINE__);
27
-DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
29
+ qemu_mutex_lock_impl(m, __FILE__, __LINE__)
28
- TYPE_XILINX_INTC)
30
#define qemu_mutex_trylock(m) \
29
+typedef struct XpsIntc XpsIntc;
31
- qemu_mutex_trylock_impl(m, __FILE__, __LINE__);
30
+DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
32
+ qemu_mutex_trylock_impl(m, __FILE__, __LINE__)
31
33
#define qemu_rec_mutex_lock(m) \
32
-struct xlx_pic
34
- qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__);
33
+struct XpsIntc
35
+ qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__)
34
{
36
#define qemu_rec_mutex_trylock(m) \
35
SysBusDevice parent_obj;
37
- qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__);
36
38
+ qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__)
37
@@ -XXX,XX +XXX,XX @@ struct xlx_pic
39
#define qemu_cond_wait(c, m) \
38
uint32_t irq_pin_state;
40
- qemu_cond_wait_impl(c, m, __FILE__, __LINE__);
39
};
41
+ qemu_cond_wait_impl(c, m, __FILE__, __LINE__)
40
42
#define qemu_cond_timedwait(c, m, ms) \
41
-static void update_irq(struct xlx_pic *p)
43
- qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__);
42
+static void update_irq(XpsIntc *p)
44
+ qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__)
43
{
45
#else
44
uint32_t i;
46
#define qemu_mutex_lock(m) ({ \
45
47
QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func); \
46
@@ -XXX,XX +XXX,XX @@ static void update_irq(struct xlx_pic *p)
47
qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
48
}
49
50
-static uint64_t
51
-pic_read(void *opaque, hwaddr addr, unsigned int size)
52
+static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
53
{
54
- struct xlx_pic *p = opaque;
55
+ XpsIntc *p = opaque;
56
uint32_t r = 0;
57
58
addr >>= 2;
59
@@ -XXX,XX +XXX,XX @@ pic_read(void *opaque, hwaddr addr, unsigned int size)
60
return r;
61
}
62
63
-static void
64
-pic_write(void *opaque, hwaddr addr,
65
- uint64_t val64, unsigned int size)
66
+static void pic_write(void *opaque, hwaddr addr,
67
+ uint64_t val64, unsigned int size)
68
{
69
- struct xlx_pic *p = opaque;
70
+ XpsIntc *p = opaque;
71
uint32_t value = val64;
72
73
addr >>= 2;
74
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = {
75
76
static void irq_handler(void *opaque, int irq, int level)
77
{
78
- struct xlx_pic *p = opaque;
79
+ XpsIntc *p = opaque;
80
81
/* edge triggered interrupt */
82
if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
83
@@ -XXX,XX +XXX,XX @@ static void irq_handler(void *opaque, int irq, int level)
84
85
static void xilinx_intc_init(Object *obj)
86
{
87
- struct xlx_pic *p = XILINX_INTC(obj);
88
+ XpsIntc *p = XILINX_INTC(obj);
89
90
qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
91
sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
92
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj)
93
}
94
95
static Property xilinx_intc_properties[] = {
96
- DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
97
+ DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
98
DEFINE_PROP_END_OF_LIST(),
99
};
100
101
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
102
static const TypeInfo xilinx_intc_info = {
103
.name = TYPE_XILINX_INTC,
104
.parent = TYPE_SYS_BUS_DEVICE,
105
- .instance_size = sizeof(struct xlx_pic),
106
+ .instance_size = sizeof(XpsIntc),
107
.instance_init = xilinx_intc_init,
108
.class_init = xilinx_intc_class_init,
109
};
48
--
110
--
49
2.20.1
111
2.34.1
50
112
51
113
diff view generated by jsdifflib
1
For Coverity's benefit, we provide simpler versions of functions like
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
qemu_mutex_lock(), qemu_cond_wait() and qemu_cond_timedwait(). When
3
we added qemu_cond_timedwait() in commit 3dcc9c6ec4ea, a cut and
4
paste error meant that the Coverity version of qemu_cond_timedwait()
5
was using the wrong _impl function, which makes the Coverity parser
6
complain:
7
2
8
"/qemu/include/qemu/thread.h", line 159: warning #140: too many arguments in
3
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
9
function call
4
macro call, to avoid after a QOM refactor:
10
return qemu_cond_timedwait(cond, mutex, ms);
11
^
12
5
13
"/qemu/include/qemu/thread.h", line 159: warning #120: return value type does
6
hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be a definition
14
not match the function type
7
DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
15
return qemu_cond_timedwait(cond, mutex, ms);
8
^
16
^
17
9
18
"/qemu/include/qemu/thread.h", line 156: warning #1563: function
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
19
"qemu_cond_timedwait" not emitted, consider modeling it or review
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
parse diagnostics to improve fidelity
12
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
21
static inline bool (qemu_cond_timedwait)(QemuCond *cond, QemuMutex *mutex,
13
Message-id: 20230109140306.23161-15-philmd@linaro.org
22
^
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/timer/xilinx_timer.c | 27 +++++++++++++--------------
17
1 file changed, 13 insertions(+), 14 deletions(-)
23
18
24
These aren't fatal, but reduce the scope of the analysis. Fix the error.
19
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
25
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Message-id: 20200319193323.2038-3-peter.maydell@linaro.org
30
---
31
include/qemu/thread.h | 2 +-
32
1 file changed, 1 insertion(+), 1 deletion(-)
33
34
diff --git a/include/qemu/thread.h b/include/qemu/thread.h
35
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
36
--- a/include/qemu/thread.h
21
--- a/hw/timer/xilinx_timer.c
37
+++ b/include/qemu/thread.h
22
+++ b/hw/timer/xilinx_timer.c
38
@@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func;
23
@@ -XXX,XX +XXX,XX @@ struct xlx_timer
39
#define qemu_cond_wait(c, m) \
24
};
40
qemu_cond_wait_impl(c, m, __FILE__, __LINE__);
25
41
#define qemu_cond_timedwait(c, m, ms) \
26
#define TYPE_XILINX_TIMER "xlnx.xps-timer"
42
- qemu_cond_wait_impl(c, m, ms, __FILE__, __LINE__);
27
-DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
43
+ qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__);
28
- TYPE_XILINX_TIMER)
44
#else
29
+typedef struct XpsTimerState XpsTimerState;
45
#define qemu_mutex_lock(m) ({ \
30
+DECLARE_INSTANCE_CHECKER(XpsTimerState, XILINX_TIMER, TYPE_XILINX_TIMER)
46
QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func); \
31
32
-struct timerblock
33
+struct XpsTimerState
34
{
35
SysBusDevice parent_obj;
36
37
@@ -XXX,XX +XXX,XX @@ struct timerblock
38
struct xlx_timer *timers;
39
};
40
41
-static inline unsigned int num_timers(struct timerblock *t)
42
+static inline unsigned int num_timers(XpsTimerState *t)
43
{
44
return 2 - t->one_timer_only;
45
}
46
@@ -XXX,XX +XXX,XX @@ static inline unsigned int timer_from_addr(hwaddr addr)
47
return addr >> 2;
48
}
49
50
-static void timer_update_irq(struct timerblock *t)
51
+static void timer_update_irq(XpsTimerState *t)
52
{
53
unsigned int i, irq = 0;
54
uint32_t csr;
55
@@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct timerblock *t)
56
static uint64_t
57
timer_read(void *opaque, hwaddr addr, unsigned int size)
58
{
59
- struct timerblock *t = opaque;
60
+ XpsTimerState *t = opaque;
61
struct xlx_timer *xt;
62
uint32_t r = 0;
63
unsigned int timer;
64
@@ -XXX,XX +XXX,XX @@ static void
65
timer_write(void *opaque, hwaddr addr,
66
uint64_t val64, unsigned int size)
67
{
68
- struct timerblock *t = opaque;
69
+ XpsTimerState *t = opaque;
70
struct xlx_timer *xt;
71
unsigned int timer;
72
uint32_t value = val64;
73
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
74
static void timer_hit(void *opaque)
75
{
76
struct xlx_timer *xt = opaque;
77
- struct timerblock *t = xt->parent;
78
+ XpsTimerState *t = xt->parent;
79
D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
80
xt->regs[R_TCSR] |= TCSR_TINT;
81
82
@@ -XXX,XX +XXX,XX @@ static void timer_hit(void *opaque)
83
84
static void xilinx_timer_realize(DeviceState *dev, Error **errp)
85
{
86
- struct timerblock *t = XILINX_TIMER(dev);
87
+ XpsTimerState *t = XILINX_TIMER(dev);
88
unsigned int i;
89
90
/* Init all the ptimers. */
91
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
92
93
static void xilinx_timer_init(Object *obj)
94
{
95
- struct timerblock *t = XILINX_TIMER(obj);
96
+ XpsTimerState *t = XILINX_TIMER(obj);
97
98
/* All timers share a single irq line. */
99
sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
100
}
101
102
static Property xilinx_timer_properties[] = {
103
- DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
104
- 62 * 1000000),
105
- DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
106
+ DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
107
+ DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
108
DEFINE_PROP_END_OF_LIST(),
109
};
110
111
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_class_init(ObjectClass *klass, void *data)
112
static const TypeInfo xilinx_timer_info = {
113
.name = TYPE_XILINX_TIMER,
114
.parent = TYPE_SYS_BUS_DEVICE,
115
- .instance_size = sizeof(struct timerblock),
116
+ .instance_size = sizeof(XpsTimerState),
117
.instance_init = xilinx_timer_init,
118
.class_init = xilinx_timer_class_init,
119
};
47
--
120
--
48
2.20.1
121
2.34.1
49
122
50
123
diff view generated by jsdifflib
New patch
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
1
2
3
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
4
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
5
uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
6
write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is
7
enabled and exposed to the guest. As a result EL3 writes of that bit are
8
ignored.
9
10
Cc: qemu-stable@nongnu.org
11
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
12
Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/helper.c | 3 +++
17
1 file changed, 3 insertions(+)
18
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
24
if (cpu_isar_feature(aa64_sme, cpu)) {
25
valid_mask |= SCR_ENTP2;
26
}
27
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
28
+ valid_mask |= SCR_HXEN;
29
+ }
30
} else {
31
valid_mask &= ~(SCR_RW | SCR_ST);
32
if (cpu_isar_feature(aa32_ras, cpu)) {
33
--
34
2.34.1
diff view generated by jsdifflib