1 | Almost nothing in here is arm-related, but the target-arm | 1 | Arm queue; not huge but I figured I might as well send it out since |
---|---|---|---|
2 | queue was convenient for these last minute bits and pieces | 2 | I've been doing code review today and there's no queue of unprocessed |
3 | for 5.0... | 3 | pullreqs... |
4 | 4 | ||
5 | thanks | 5 | thanks |
6 | -- PMM | 6 | -- PMM |
7 | 7 | ||
8 | The following changes since commit 14e5526b51910efd62cd31cd95b49baca975c83f: | 8 | The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92: |
9 | 9 | ||
10 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-04-13 15:42:51 +0100) | 10 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000) |
11 | 11 | ||
12 | are available in the Git repository at: | 12 | are available in the Git repository at: |
13 | 13 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200414 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112 |
15 | 15 | ||
16 | for you to fetch changes up to 84f82ddcbb4ac4ed04c8675e85155329f23184f0: | 16 | for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de: |
17 | 17 | ||
18 | Deprecate KVM support for AArch32 (2020-04-14 17:20:22 +0100) | 18 | ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000) |
19 | 19 | ||
20 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
21 | patch queue: | 21 | target-arm queue: |
22 | * Fix some problems that trip up Coverity's scanner | 22 | * arm: Support emulation of ARMv8.4-TTST extension |
23 | * run-coverity-scan: New script automating the scan-and-upload process | 23 | * arm: Update cpu.h ID register field definitions |
24 | * docs: Improve our gdbstub documentation | 24 | * arm: Fix breakage of XScale instruction emulation |
25 | * configure: Honour --disable-werror for Sphinx | 25 | * hw/net/lan9118: Fix RX Status FIFO PEEK value |
26 | * docs: Fix errors produced when building with Sphinx 3.0 | 26 | * npcm7xx: Add ADC and PWM emulation |
27 | * docs: Require Sphinx 1.6 or better | 27 | * ui/cocoa: Make "open docs" help menu entry work again when binary |
28 | * Add deprecation notice for KVM support on AArch32 hosts | 28 | is run from the build tree |
29 | * ui/cocoa: Fix openFile: deprecation on Big Sur | ||
30 | * docs: Add qemu-storage-daemon(1) manpage to meson.build | ||
31 | * docs: Build and install all the docs in a single manual | ||
29 | 32 | ||
30 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
31 | Peter Maydell (12): | 34 | Hao Wu (6): |
32 | osdep.h: Drop no-longer-needed Coverity workarounds | 35 | hw/misc: Add clock converter in NPCM7XX CLK module |
33 | thread.h: Fix Coverity version of qemu_cond_timedwait() | 36 | hw/timer: Refactor NPCM7XX Timer to use CLK clock |
34 | thread.h: Remove trailing semicolons from Coverity qemu_mutex_lock() etc | 37 | hw/adc: Add an ADC module for NPCM7XX |
35 | linux-user/flatload.c: Use "" for include of QEMU header target_flat.h | 38 | hw/misc: Add a PWM module for NPCM7XX |
36 | scripts/run-coverity-scan: Script to run Coverity Scan build | 39 | hw/misc: Add QTest for NPCM7XX PWM Module |
37 | scripts/coverity-scan: Add Docker support | 40 | hw/*: Use type casting for SysBusDevice in NPCM7XX |
38 | docs: Improve our gdbstub documentation | ||
39 | configure: Honour --disable-werror for Sphinx | ||
40 | scripts/kernel-doc: Add missing close-paren in c:function directives | ||
41 | kernel-doc: Use c:struct for Sphinx 3.0 and later | ||
42 | docs: Require Sphinx 1.6 or better | ||
43 | Deprecate KVM support for AArch32 | ||
44 | 41 | ||
45 | configure | 9 +- | 42 | Leif Lindholm (6): |
46 | Makefile | 2 +- | 43 | target/arm: fix typo in cpu.h ID_AA64PFR1 field name |
47 | include/qemu/osdep.h | 14 - | 44 | target/arm: make ARMCPU.clidr 64-bit |
48 | include/qemu/thread.h | 12 +- | 45 | target/arm: make ARMCPU.ctr 64-bit |
49 | linux-user/flatload.c | 2 +- | 46 | target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h |
50 | MAINTAINERS | 5 + | 47 | target/arm: add aarch64 ID register fields to cpu.h |
51 | docs/conf.py | 6 +- | 48 | target/arm: add aarch32 ID register fields to cpu.h |
52 | docs/sphinx/kerneldoc.py | 1 + | ||
53 | docs/system/deprecated.rst | 8 + | ||
54 | docs/system/gdb.rst | 22 +- | ||
55 | qemu-options.hx | 24 +- | ||
56 | scripts/coverity-scan/coverity-scan.docker | 131 ++++++++++ | ||
57 | scripts/coverity-scan/run-coverity-scan | 401 +++++++++++++++++++++++++++++ | ||
58 | scripts/kernel-doc | 18 +- | ||
59 | 14 files changed, 615 insertions(+), 40 deletions(-) | ||
60 | create mode 100644 scripts/coverity-scan/coverity-scan.docker | ||
61 | create mode 100755 scripts/coverity-scan/run-coverity-scan | ||
62 | 49 | ||
50 | Peter Maydell (5): | ||
51 | docs: Add qemu-storage-daemon(1) manpage to meson.build | ||
52 | docs: Build and install all the docs in a single manual | ||
53 | target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns | ||
54 | hw/net/lan9118: Fix RX Status FIFO PEEK value | ||
55 | hw/net/lan9118: Add symbolic constants for register offsets | ||
56 | |||
57 | Roman Bolshakov (2): | ||
58 | ui/cocoa: Update path to docs in build tree | ||
59 | ui/cocoa: Fix openFile: deprecation on Big Sur | ||
60 | |||
61 | Rémi Denis-Courmont (2): | ||
62 | target/arm: ARMv8.4-TTST extension | ||
63 | target/arm: enable Small Translation tables in max CPU | ||
64 | |||
65 | docs/conf.py | 46 ++- | ||
66 | docs/devel/conf.py | 15 - | ||
67 | docs/index.html.in | 17 - | ||
68 | docs/interop/conf.py | 28 -- | ||
69 | docs/meson.build | 65 ++-- | ||
70 | docs/specs/conf.py | 16 - | ||
71 | docs/system/arm/nuvoton.rst | 4 +- | ||
72 | docs/system/conf.py | 28 -- | ||
73 | docs/tools/conf.py | 37 -- | ||
74 | docs/user/conf.py | 15 - | ||
75 | meson.build | 1 + | ||
76 | hw/adc/trace.h | 1 + | ||
77 | include/hw/adc/npcm7xx_adc.h | 69 ++++ | ||
78 | include/hw/arm/npcm7xx.h | 4 + | ||
79 | include/hw/misc/npcm7xx_clk.h | 146 ++++++- | ||
80 | include/hw/misc/npcm7xx_pwm.h | 105 +++++ | ||
81 | include/hw/timer/npcm7xx_timer.h | 1 + | ||
82 | target/arm/cpu.h | 85 ++++- | ||
83 | hw/adc/npcm7xx_adc.c | 301 +++++++++++++++ | ||
84 | hw/arm/npcm7xx.c | 55 ++- | ||
85 | hw/arm/npcm7xx_boards.c | 2 +- | ||
86 | hw/mem/npcm7xx_mc.c | 2 +- | ||
87 | hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++- | ||
88 | hw/misc/npcm7xx_gcr.c | 2 +- | ||
89 | hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++ | ||
90 | hw/misc/npcm7xx_rng.c | 2 +- | ||
91 | hw/net/lan9118.c | 26 +- | ||
92 | hw/nvram/npcm7xx_otp.c | 2 +- | ||
93 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
94 | hw/timer/npcm7xx_timer.c | 39 +- | ||
95 | target/arm/cpu64.c | 1 + | ||
96 | target/arm/helper.c | 15 +- | ||
97 | target/arm/translate.c | 7 + | ||
98 | tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++ | ||
99 | tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++ | ||
100 | hw/adc/meson.build | 1 + | ||
101 | hw/adc/trace-events | 5 + | ||
102 | hw/misc/meson.build | 1 + | ||
103 | hw/misc/trace-events | 6 + | ||
104 | tests/qtest/meson.build | 4 +- | ||
105 | ui/cocoa.m | 7 +- | ||
106 | 41 files changed, 3124 insertions(+), 263 deletions(-) | ||
107 | delete mode 100644 docs/devel/conf.py | ||
108 | delete mode 100644 docs/index.html.in | ||
109 | delete mode 100644 docs/interop/conf.py | ||
110 | delete mode 100644 docs/specs/conf.py | ||
111 | delete mode 100644 docs/system/conf.py | ||
112 | delete mode 100644 docs/tools/conf.py | ||
113 | delete mode 100644 docs/user/conf.py | ||
114 | create mode 100644 hw/adc/trace.h | ||
115 | create mode 100644 include/hw/adc/npcm7xx_adc.h | ||
116 | create mode 100644 include/hw/misc/npcm7xx_pwm.h | ||
117 | create mode 100644 hw/adc/npcm7xx_adc.c | ||
118 | create mode 100644 hw/misc/npcm7xx_pwm.c | ||
119 | create mode 100644 tests/qtest/npcm7xx_adc-test.c | ||
120 | create mode 100644 tests/qtest/npcm7xx_pwm-test.c | ||
121 | create mode 100644 hw/adc/trace-events | ||
122 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
1 | 2 | ||
3 | This adds for the Small Translation tables extension in AArch64 state. | ||
4 | |||
5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | target/arm/cpu.h | 5 +++++ | ||
10 | target/arm/helper.c | 15 +++++++++++++-- | ||
11 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/cpu.h | ||
16 | +++ b/target/arm/cpu.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) | ||
18 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; | ||
19 | } | ||
20 | |||
21 | +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) | ||
22 | +{ | ||
23 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; | ||
24 | +} | ||
25 | + | ||
26 | static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) | ||
27 | { | ||
28 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | ||
29 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/helper.c | ||
32 | +++ b/target/arm/helper.c | ||
33 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
34 | { | ||
35 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | ||
36 | bool epd, hpd, using16k, using64k; | ||
37 | - int select, tsz, tbi; | ||
38 | + int select, tsz, tbi, max_tsz; | ||
39 | |||
40 | if (!regime_has_2_ranges(mmu_idx)) { | ||
41 | select = 0; | ||
42 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
43 | hpd = extract64(tcr, 42, 1); | ||
44 | } | ||
45 | } | ||
46 | - tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | ||
47 | + | ||
48 | + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { | ||
49 | + max_tsz = 48 - using64k; | ||
50 | + } else { | ||
51 | + max_tsz = 39; | ||
52 | + } | ||
53 | + | ||
54 | + tsz = MIN(tsz, max_tsz); | ||
55 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | ||
56 | |||
57 | /* Present TBI as a composite with TBID. */ | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
59 | if (!aarch64 || stride == 9) { | ||
60 | /* AArch32 or 4KB pages */ | ||
61 | startlevel = 2 - sl0; | ||
62 | + | ||
63 | + if (cpu_isar_feature(aa64_st, cpu)) { | ||
64 | + startlevel &= 3; | ||
65 | + } | ||
66 | } else { | ||
67 | /* 16KB or 64KB pages */ | ||
68 | startlevel = 3 - sl0; | ||
69 | -- | ||
70 | 2.20.1 | ||
71 | |||
72 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
1 | 2 | ||
3 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | --- | ||
7 | target/arm/cpu64.c | 1 + | ||
8 | 1 file changed, 1 insertion(+) | ||
9 | |||
10 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/arm/cpu64.c | ||
13 | +++ b/target/arm/cpu64.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
15 | t = cpu->isar.id_aa64mmfr2; | ||
16 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | ||
17 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | ||
18 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
19 | cpu->isar.id_aa64mmfr2 = t; | ||
20 | |||
21 | /* Replicate the same data to the 32-bit id registers. */ | ||
22 | -- | ||
23 | 2.20.1 | ||
24 | |||
25 | diff view generated by jsdifflib |
1 | The target_flat.h file is a QEMU header, so we should include it using | 1 | From: Leif Lindholm <leif@nuviainc.com> |
---|---|---|---|
2 | quotes, not angle brackets. | ||
3 | 2 | ||
4 | Coverity otherwise is unable to find the header: | 3 | SBSS -> SSBS |
5 | 4 | ||
6 | "../linux-user/flatload.c", line 40: error #1712: cannot open source file | 5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> |
7 | "target_flat.h" | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | #include <target_flat.h> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | ^ | 8 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> |
10 | 9 | Message-id: 20210108185154.8108-2-leif@nuviainc.com | |
11 | because the relevant directory is only on the -iquote path, not the -I path. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
16 | Message-id: 20200319193323.2038-5-peter.maydell@linaro.org | ||
17 | --- | 11 | --- |
18 | linux-user/flatload.c | 2 +- | 12 | target/arm/cpu.h | 2 +- |
19 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
20 | 14 | ||
21 | diff --git a/linux-user/flatload.c b/linux-user/flatload.c | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/linux-user/flatload.c | 17 | --- a/target/arm/cpu.h |
24 | +++ b/linux-user/flatload.c | 18 | +++ b/target/arm/cpu.h |
25 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4) |
26 | 20 | FIELD(ID_AA64PFR0, SVE, 32, 4) | |
27 | #include "qemu.h" | 21 | |
28 | #include "flat.h" | 22 | FIELD(ID_AA64PFR1, BT, 0, 4) |
29 | -#include <target_flat.h> | 23 | -FIELD(ID_AA64PFR1, SBSS, 4, 4) |
30 | +#include "target_flat.h" | 24 | +FIELD(ID_AA64PFR1, SSBS, 4, 4) |
31 | 25 | FIELD(ID_AA64PFR1, MTE, 8, 4) | |
32 | //#define DEBUG | 26 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) |
33 | 27 | ||
34 | -- | 28 | -- |
35 | 2.20.1 | 29 | 2.20.1 |
36 | 30 | ||
37 | 31 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Leif Lindholm <leif@nuviainc.com> | ||
1 | 2 | ||
3 | The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit | ||
4 | 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. | ||
5 | Extend the clidr field to be able to hold this context. | ||
6 | |||
7 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
11 | Message-id: 20210108185154.8108-3-leif@nuviainc.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/cpu.h | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
22 | uint32_t id_afr0; | ||
23 | uint64_t id_aa64afr0; | ||
24 | uint64_t id_aa64afr1; | ||
25 | - uint32_t clidr; | ||
26 | + uint64_t clidr; | ||
27 | uint64_t mp_affinity; /* MP ID without feature bits */ | ||
28 | /* The elements of this array are the CCSIDR values for each cache, | ||
29 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | ||
30 | -- | ||
31 | 2.20.1 | ||
32 | |||
33 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Leif Lindholm <leif@nuviainc.com> | ||
1 | 2 | ||
3 | When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the | ||
4 | TminLine field in bits [37:32]. | ||
5 | Extend the ctr field to be able to hold this context. | ||
6 | |||
7 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | ||
8 | Reviewed-by: Hao Wu <wuhaotsh@google.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
11 | Message-id: 20210108185154.8108-4-leif@nuviainc.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/cpu.h | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
22 | uint64_t midr; | ||
23 | uint32_t revidr; | ||
24 | uint32_t reset_fpsid; | ||
25 | - uint32_t ctr; | ||
26 | + uint64_t ctr; | ||
27 | uint32_t reset_sctlr; | ||
28 | uint64_t pmceid0; | ||
29 | uint64_t pmceid1; | ||
30 | -- | ||
31 | 2.20.1 | ||
32 | |||
33 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Leif Lindholm <leif@nuviainc.com> | ||
1 | 2 | ||
3 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | ||
4 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
5 | Message-id: 20210108185154.8108-5-leif@nuviainc.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 31 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) | ||
16 | /* | ||
17 | * System register ID fields. | ||
18 | */ | ||
19 | +FIELD(CLIDR_EL1, CTYPE1, 0, 3) | ||
20 | +FIELD(CLIDR_EL1, CTYPE2, 3, 3) | ||
21 | +FIELD(CLIDR_EL1, CTYPE3, 6, 3) | ||
22 | +FIELD(CLIDR_EL1, CTYPE4, 9, 3) | ||
23 | +FIELD(CLIDR_EL1, CTYPE5, 12, 3) | ||
24 | +FIELD(CLIDR_EL1, CTYPE6, 15, 3) | ||
25 | +FIELD(CLIDR_EL1, CTYPE7, 18, 3) | ||
26 | +FIELD(CLIDR_EL1, LOUIS, 21, 3) | ||
27 | +FIELD(CLIDR_EL1, LOC, 24, 3) | ||
28 | +FIELD(CLIDR_EL1, LOUU, 27, 3) | ||
29 | +FIELD(CLIDR_EL1, ICB, 30, 3) | ||
30 | + | ||
31 | +/* When FEAT_CCIDX is implemented */ | ||
32 | +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) | ||
33 | +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) | ||
34 | +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) | ||
35 | + | ||
36 | +/* When FEAT_CCIDX is not implemented */ | ||
37 | +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) | ||
38 | +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) | ||
39 | +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) | ||
40 | + | ||
41 | +FIELD(CTR_EL0, IMINLINE, 0, 4) | ||
42 | +FIELD(CTR_EL0, L1IP, 14, 2) | ||
43 | +FIELD(CTR_EL0, DMINLINE, 16, 4) | ||
44 | +FIELD(CTR_EL0, ERG, 20, 4) | ||
45 | +FIELD(CTR_EL0, CWG, 24, 4) | ||
46 | +FIELD(CTR_EL0, IDC, 28, 1) | ||
47 | +FIELD(CTR_EL0, DIC, 29, 1) | ||
48 | +FIELD(CTR_EL0, TMINLINE, 32, 6) | ||
49 | + | ||
50 | FIELD(MIDR_EL1, REVISION, 0, 4) | ||
51 | FIELD(MIDR_EL1, PARTNUM, 4, 12) | ||
52 | FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) | ||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Leif Lindholm <leif@nuviainc.com> | ||
1 | 2 | ||
3 | Add entries present in ARM DDI 0487F.c (August 2020). | ||
4 | |||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
8 | Message-id: 20210108185154.8108-6-leif@nuviainc.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 15 +++++++++++++++ | ||
12 | 1 file changed, 15 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4) | ||
19 | FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) | ||
20 | FIELD(ID_AA64ISAR1, SB, 36, 4) | ||
21 | FIELD(ID_AA64ISAR1, SPECRES, 40, 4) | ||
22 | +FIELD(ID_AA64ISAR1, BF16, 44, 4) | ||
23 | +FIELD(ID_AA64ISAR1, DGH, 48, 4) | ||
24 | +FIELD(ID_AA64ISAR1, I8MM, 52, 4) | ||
25 | |||
26 | FIELD(ID_AA64PFR0, EL0, 0, 4) | ||
27 | FIELD(ID_AA64PFR0, EL1, 4, 4) | ||
28 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) | ||
29 | FIELD(ID_AA64PFR0, GIC, 24, 4) | ||
30 | FIELD(ID_AA64PFR0, RAS, 28, 4) | ||
31 | FIELD(ID_AA64PFR0, SVE, 32, 4) | ||
32 | +FIELD(ID_AA64PFR0, SEL2, 36, 4) | ||
33 | +FIELD(ID_AA64PFR0, MPAM, 40, 4) | ||
34 | +FIELD(ID_AA64PFR0, AMU, 44, 4) | ||
35 | +FIELD(ID_AA64PFR0, DIT, 48, 4) | ||
36 | +FIELD(ID_AA64PFR0, CSV2, 56, 4) | ||
37 | +FIELD(ID_AA64PFR0, CSV3, 60, 4) | ||
38 | |||
39 | FIELD(ID_AA64PFR1, BT, 0, 4) | ||
40 | FIELD(ID_AA64PFR1, SSBS, 4, 4) | ||
41 | FIELD(ID_AA64PFR1, MTE, 8, 4) | ||
42 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | ||
43 | +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) | ||
44 | |||
45 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) | ||
46 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | ||
47 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) | ||
48 | FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) | ||
49 | FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) | ||
50 | FIELD(ID_AA64MMFR0, EXS, 44, 4) | ||
51 | +FIELD(ID_AA64MMFR0, FGT, 56, 4) | ||
52 | +FIELD(ID_AA64MMFR0, ECV, 60, 4) | ||
53 | |||
54 | FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) | ||
55 | FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) | ||
56 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4) | ||
57 | FIELD(ID_AA64MMFR1, PAN, 20, 4) | ||
58 | FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) | ||
59 | FIELD(ID_AA64MMFR1, XNX, 28, 4) | ||
60 | +FIELD(ID_AA64MMFR1, TWED, 32, 4) | ||
61 | +FIELD(ID_AA64MMFR1, ETS, 36, 4) | ||
62 | |||
63 | FIELD(ID_AA64MMFR2, CNP, 0, 4) | ||
64 | FIELD(ID_AA64MMFR2, UAO, 4, 4) | ||
65 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) | ||
66 | FIELD(ID_AA64DFR0, PMSVER, 32, 4) | ||
67 | FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) | ||
68 | FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) | ||
69 | +FIELD(ID_AA64DFR0, MTPMU, 48, 4) | ||
70 | |||
71 | FIELD(ID_DFR0, COPDBG, 0, 4) | ||
72 | FIELD(ID_DFR0, COPSDBG, 4, 4) | ||
73 | -- | ||
74 | 2.20.1 | ||
75 | |||
76 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Leif Lindholm <leif@nuviainc.com> | ||
1 | 2 | ||
3 | Add entries present in ARM DDI 0487F.c (August 2020). | ||
4 | |||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
8 | Message-id: 20210108185154.8108-7-leif@nuviainc.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ | ||
12 | 1 file changed, 28 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4) | ||
19 | FIELD(ID_ISAR6, FHM, 8, 4) | ||
20 | FIELD(ID_ISAR6, SB, 12, 4) | ||
21 | FIELD(ID_ISAR6, SPECRES, 16, 4) | ||
22 | +FIELD(ID_ISAR6, BF16, 20, 4) | ||
23 | +FIELD(ID_ISAR6, I8MM, 24, 4) | ||
24 | |||
25 | FIELD(ID_MMFR0, VMSA, 0, 4) | ||
26 | FIELD(ID_MMFR0, PMSA, 4, 4) | ||
27 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4) | ||
28 | FIELD(ID_MMFR0, FCSE, 24, 4) | ||
29 | FIELD(ID_MMFR0, INNERSHR, 28, 4) | ||
30 | |||
31 | +FIELD(ID_MMFR1, L1HVDVA, 0, 4) | ||
32 | +FIELD(ID_MMFR1, L1UNIVA, 4, 4) | ||
33 | +FIELD(ID_MMFR1, L1HVDSW, 8, 4) | ||
34 | +FIELD(ID_MMFR1, L1UNISW, 12, 4) | ||
35 | +FIELD(ID_MMFR1, L1HVD, 16, 4) | ||
36 | +FIELD(ID_MMFR1, L1UNI, 20, 4) | ||
37 | +FIELD(ID_MMFR1, L1TSTCLN, 24, 4) | ||
38 | +FIELD(ID_MMFR1, BPRED, 28, 4) | ||
39 | + | ||
40 | +FIELD(ID_MMFR2, L1HVDFG, 0, 4) | ||
41 | +FIELD(ID_MMFR2, L1HVDBG, 4, 4) | ||
42 | +FIELD(ID_MMFR2, L1HVDRNG, 8, 4) | ||
43 | +FIELD(ID_MMFR2, HVDTLB, 12, 4) | ||
44 | +FIELD(ID_MMFR2, UNITLB, 16, 4) | ||
45 | +FIELD(ID_MMFR2, MEMBARR, 20, 4) | ||
46 | +FIELD(ID_MMFR2, WFISTALL, 24, 4) | ||
47 | +FIELD(ID_MMFR2, HWACCFLG, 28, 4) | ||
48 | + | ||
49 | FIELD(ID_MMFR3, CMAINTVA, 0, 4) | ||
50 | FIELD(ID_MMFR3, CMAINTSW, 4, 4) | ||
51 | FIELD(ID_MMFR3, BPMAINT, 8, 4) | ||
52 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4) | ||
53 | FIELD(ID_MMFR4, CCIDX, 24, 4) | ||
54 | FIELD(ID_MMFR4, EVT, 28, 4) | ||
55 | |||
56 | +FIELD(ID_MMFR5, ETS, 0, 4) | ||
57 | + | ||
58 | FIELD(ID_PFR0, STATE0, 0, 4) | ||
59 | FIELD(ID_PFR0, STATE1, 4, 4) | ||
60 | FIELD(ID_PFR0, STATE2, 8, 4) | ||
61 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4) | ||
62 | FIELD(ID_PFR1, VIRT_FRAC, 24, 4) | ||
63 | FIELD(ID_PFR1, GIC, 28, 4) | ||
64 | |||
65 | +FIELD(ID_PFR2, CSV3, 0, 4) | ||
66 | +FIELD(ID_PFR2, SSBS, 4, 4) | ||
67 | +FIELD(ID_PFR2, RAS_FRAC, 8, 4) | ||
68 | + | ||
69 | FIELD(ID_AA64ISAR0, AES, 4, 4) | ||
70 | FIELD(ID_AA64ISAR0, SHA1, 8, 4) | ||
71 | FIELD(ID_AA64ISAR0, SHA2, 12, 4) | ||
72 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) | ||
73 | FIELD(ID_DFR0, PERFMON, 24, 4) | ||
74 | FIELD(ID_DFR0, TRACEFILT, 28, 4) | ||
75 | |||
76 | +FIELD(ID_DFR1, MTPMU, 0, 4) | ||
77 | + | ||
78 | FIELD(DBGDIDR, SE_IMP, 12, 1) | ||
79 | FIELD(DBGDIDR, NSUHD_IMP, 14, 1) | ||
80 | FIELD(DBGDIDR, VERSION, 16, 4) | ||
81 | -- | ||
82 | 2.20.1 | ||
83 | |||
84 | diff view generated by jsdifflib |
1 | When kernel-doc generates a 'c:function' directive for a function | 1 | From: Roman Bolshakov <r.bolshakov@yadro.com> |
---|---|---|---|
2 | one of whose arguments is a function pointer, it fails to print | ||
3 | the close-paren after the argument list of the function pointer | ||
4 | argument, for instance in the memory API documentation: | ||
5 | .. c:function:: void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp) | ||
6 | 2 | ||
7 | which should have a ')' after the 'void *host' which is the | 3 | QEMU documentation can't be opened if QEMU is run from build tree |
8 | last argument to 'resized'. | 4 | because executables are placed in the top of build tree after conversion |
5 | to meson. | ||
9 | 6 | ||
10 | Older versions of Sphinx don't try to parse the argumnet | 7 | Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> |
11 | to c:function, but Sphinx 3.0 does do this and will complain: | 8 | Reported-by: Peter Maydell <peter.maydell@linaro.org> |
12 | 9 | Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com | |
13 | /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:834: WARNING: Error in declarator or parameters | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Invalid C declaration: Expecting "," or ")" in parameters, got "EOF". [error at 208] | ||
15 | void memory_region_init_resizeable_ram (MemoryRegion * mr, struct Object * owner, const char * name, uint64_t size, uint64_t max_size, void (*resized) (const char*, uint64_t length, void *host, Error ** errp) | ||
16 | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------^ | ||
17 | |||
18 | Add the missing close-paren. | ||
19 | |||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
22 | Message-id: 20200411182934.28678-3-peter.maydell@linaro.org | ||
23 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
24 | --- | 12 | --- |
25 | scripts/kernel-doc | 2 +- | 13 | ui/cocoa.m | 2 +- |
26 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
27 | 15 | ||
28 | diff --git a/scripts/kernel-doc b/scripts/kernel-doc | 16 | diff --git a/ui/cocoa.m b/ui/cocoa.m |
29 | index XXXXXXX..XXXXXXX 100755 | 17 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/scripts/kernel-doc | 18 | --- a/ui/cocoa.m |
31 | +++ b/scripts/kernel-doc | 19 | +++ b/ui/cocoa.m |
32 | @@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) { | 20 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; |
33 | 21 | - (void) openDocumentation: (NSString *) filename | |
34 | if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) { | 22 | { |
35 | # pointer-to-function | 23 | /* Where to look for local files */ |
36 | - print $1 . $parameter . ") (" . $2; | 24 | - NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"}; |
37 | + print $1 . $parameter . ") (" . $2 . ")"; | 25 | + NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"}; |
38 | } else { | 26 | NSString *full_file_path; |
39 | print $type . " " . $parameter; | 27 | |
40 | } | 28 | /* iterate thru the possible paths until the file is found */ |
41 | -- | 29 | -- |
42 | 2.20.1 | 30 | 2.20.1 |
43 | 31 | ||
44 | 32 | diff view generated by jsdifflib |
1 | The documentation of our -s and -gdb options is quite old; in | 1 | In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage. |
---|---|---|---|
2 | particular it still claims that it will cause QEMU to stop and wait | 2 | At the moment new manpages have to be listed both in the conf.py for |
3 | for the gdb connection, when this has not been true for some time: | 3 | Sphinx and also in docs/meson.build for Meson. We forgot the second |
4 | you also need to pass -S if you want to make QEMU not launch the | 4 | of those -- correct the omission. |
5 | guest on startup. | ||
6 | |||
7 | Improve the documentation to mention this requirement in the | ||
8 | executable's --help output, the documentation of the -gdb option in | ||
9 | the manual, and in the "GDB usage" chapter. | ||
10 | |||
11 | Includes some minor tweaks to these paragraphs of documentation | ||
12 | since I was editing them anyway (such as dropping the description | ||
13 | of our gdb support as "primitive"). | ||
14 | 5 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
19 | Message-id: 20200403094014.9589-1-peter.maydell@linaro.org | 9 | Message-id: 20210108161416.21129-2-peter.maydell@linaro.org |
20 | --- | 10 | --- |
21 | docs/system/gdb.rst | 22 +++++++++++++++------- | 11 | docs/meson.build | 1 + |
22 | qemu-options.hx | 24 ++++++++++++++++++------ | 12 | 1 file changed, 1 insertion(+) |
23 | 2 files changed, 33 insertions(+), 13 deletions(-) | ||
24 | 13 | ||
25 | diff --git a/docs/system/gdb.rst b/docs/system/gdb.rst | 14 | diff --git a/docs/meson.build b/docs/meson.build |
26 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/docs/system/gdb.rst | 16 | --- a/docs/meson.build |
28 | +++ b/docs/system/gdb.rst | 17 | +++ b/docs/meson.build |
29 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ if build_docs |
30 | GDB usage | 19 | 'qemu-img.1': (have_tools ? 'man1' : ''), |
31 | --------- | 20 | 'qemu-nbd.8': (have_tools ? 'man8' : ''), |
32 | 21 | 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), | |
33 | -QEMU has a primitive support to work with gdb, so that you can do | 22 | + 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''), |
34 | -'Ctrl-C' while the virtual machine is running and inspect its state. | 23 | 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), |
35 | +QEMU supports working with gdb via gdb's remote-connection facility | 24 | 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), |
36 | +(the "gdbstub"). This allows you to debug guest code in the same | 25 | 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), |
37 | +way that you might with a low-level debug facility like JTAG | ||
38 | +on real hardware. You can stop and start the virtual machine, | ||
39 | +examine state like registers and memory, and set breakpoints and | ||
40 | +watchpoints. | ||
41 | |||
42 | -In order to use gdb, launch QEMU with the '-s' option. It will wait for | ||
43 | -a gdb connection: | ||
44 | +In order to use gdb, launch QEMU with the ``-s`` and ``-S`` options. | ||
45 | +The ``-s`` option will make QEMU listen for an incoming connection | ||
46 | +from gdb on TCP port 1234, and ``-S`` will make QEMU not start the | ||
47 | +guest until you tell it to from gdb. (If you want to specify which | ||
48 | +TCP port to use or to use something other than TCP for the gdbstub | ||
49 | +connection, use the ``-gdb dev`` option instead of ``-s``.) | ||
50 | |||
51 | .. parsed-literal:: | ||
52 | |||
53 | - |qemu_system| -s -kernel bzImage -hda rootdisk.img -append "root=/dev/hda" | ||
54 | - Connected to host network interface: tun0 | ||
55 | - Waiting gdb connection on port 1234 | ||
56 | + |qemu_system| -s -S -kernel bzImage -hda rootdisk.img -append "root=/dev/hda" | ||
57 | + | ||
58 | +QEMU will launch but will silently wait for gdb to connect. | ||
59 | |||
60 | Then launch gdb on the 'vmlinux' executable:: | ||
61 | |||
62 | diff --git a/qemu-options.hx b/qemu-options.hx | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/qemu-options.hx | ||
65 | +++ b/qemu-options.hx | ||
66 | @@ -XXX,XX +XXX,XX @@ SRST | ||
67 | ERST | ||
68 | |||
69 | DEF("gdb", HAS_ARG, QEMU_OPTION_gdb, \ | ||
70 | - "-gdb dev wait for gdb connection on 'dev'\n", QEMU_ARCH_ALL) | ||
71 | + "-gdb dev accept gdb connection on 'dev'. (QEMU defaults to starting\n" | ||
72 | + " the guest without waiting for gdb to connect; use -S too\n" | ||
73 | + " if you want it to not start execution.)\n", | ||
74 | + QEMU_ARCH_ALL) | ||
75 | SRST | ||
76 | ``-gdb dev`` | ||
77 | - Wait for gdb connection on device dev (see | ||
78 | - :ref:`gdb_005fusage`). Typical connections will likely be | ||
79 | - TCP-based, but also UDP, pseudo TTY, or even stdio are reasonable | ||
80 | - use case. The latter is allowing to start QEMU from within gdb and | ||
81 | - establish the connection via a pipe: | ||
82 | + Accept a gdb connection on device dev (see | ||
83 | + :ref:`gdb_005fusage`). Note that this option does not pause QEMU | ||
84 | + execution -- if you want QEMU to not start the guest until you | ||
85 | + connect with gdb and issue a ``continue`` command, you will need to | ||
86 | + also pass the ``-S`` option to QEMU. | ||
87 | + | ||
88 | + The most usual configuration is to listen on a local TCP socket:: | ||
89 | + | ||
90 | + -gdb tcp::3117 | ||
91 | + | ||
92 | + but you can specify other backends; UDP, pseudo TTY, or even stdio | ||
93 | + are all reasonable use cases. For example, a stdio connection | ||
94 | + allows you to start QEMU from within gdb and establish the | ||
95 | + connection via a pipe: | ||
96 | |||
97 | .. parsed-literal:: | ||
98 | |||
99 | -- | 26 | -- |
100 | 2.20.1 | 27 | 2.20.1 |
101 | 28 | ||
102 | 29 | diff view generated by jsdifflib |
1 | Versions of Sphinx older than 1.6 can't build all of our documentation, | 1 | When we first converted our documentation to Sphinx, we split it into |
---|---|---|---|
2 | because they are too picky about the syntax of the argument to the | 2 | multiple manuals (system, interop, tools, etc), which are all built |
3 | option:: directive; see Sphinx bugs #646, #3366: | 3 | separately. The primary driver for this was wanting to be able to |
4 | 4 | avoid shipping the 'devel' manual to end-users. However, this is | |
5 | https://github.com/sphinx-doc/sphinx/issues/646 | 5 | working against the grain of the way Sphinx wants to be used and |
6 | https://github.com/sphinx-doc/sphinx/issues/3366 | 6 | causes some annoyances: |
7 | 7 | * Cross-references between documents become much harder or | |
8 | Trying to build with a 1.4.x Sphinx fails with | 8 | possibly impossible |
9 | docs/system/images.rst:4: SEVERE: Duplicate ID: "cmdoption-qcow2-arg-encrypt" | 9 | * There is no single index to the whole documentation |
10 | and a 1.5.x Sphinx fails with | 10 | * Within one manual there's no links or table-of-contents info |
11 | docs/system/invocation.rst:544: WARNING: Malformed option description '[enable=]PATTERN', should look like "opt", "-opt | 11 | that lets you easily navigate to the others |
12 | args", "--opt args", "/opt args" or "+opt args" | 12 | * The devel manual doesn't get published on the QEMU website |
13 | 13 | (it would be nice to able to refer to it there) | |
14 | Update our needs_sphinx setting to indicate that we require at least | 14 | |
15 | 1.6. This will allow configure to fall back to "don't build the | 15 | Merely hiding our developer documentation from end users seems like |
16 | docs" rather than causing the build to fail entirely, which is | 16 | it's not enough benefit for these costs. Combine all the |
17 | probably what most users building on a host old enough to have such | 17 | documentation into a single manual (the same way that the readthedocs |
18 | an old Sphinx would want; if they do want the docs then they'll have | 18 | site builds it) and install the whole thing. The previous manual |
19 | a useful indication of what they need to do (upgrade Sphinx!) rather | 19 | divisions remain as the new top level sections in the manual. |
20 | than a confusing error message. | 20 | |
21 | 21 | * The per-manual conf.py files are no longer needed | |
22 | In theory our distro support policy would suggest that we should | 22 | * The man_pages[] specifications previously in each per-manual |
23 | support building on the Sphinx shipped in those distros, but: | 23 | conf.py move to the top level conf.py |
24 | * EPEL7 has Sphinx 1.2.3 (which we've never supported!) | 24 | * docs/meson.build logic is simplified as we now only need to run |
25 | * Debian Stretch has Sphinx 1.4.8 | 25 | Sphinx once for the HTML and then once for the manpages5B |
26 | 26 | * The old index.html.in that produced the top-level page with | |
27 | Trying to get our docs to work with Sphinx 1.4 is not tractable | 27 | links to each manual is no longer needed |
28 | for the 5.0 release and I'm not sure it's worthwhile effort anyway; | 28 | |
29 | at least with this change the build as a whole now succeeds. | 29 | Unfortunately this means that we now have to build the HTML |
30 | 30 | documentation into docs/manual in the build tree rather than directly | |
31 | Thanks to John Snow for doing the investigation and testing to | 31 | into docs/; otherwise it is too awkward to ensure we install only the |
32 | confirm what Sphinx versions fail in what ways and what distros | 32 | built manual and not also the dependency info, stamp file, etc. The |
33 | shipped what. | 33 | manual still ends up in the same place in the final installed |
34 | directory, but anybody who was consulting documentation from within | ||
35 | the build tree will have to adjust where they're looking. | ||
34 | 36 | ||
35 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
36 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 38 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> |
39 | Message-id: 20210108161416.21129-3-peter.maydell@linaro.org | ||
37 | --- | 40 | --- |
38 | docs/conf.py | 6 ++++-- | 41 | docs/conf.py | 46 ++++++++++++++++++++++++++++++- |
39 | 1 file changed, 4 insertions(+), 2 deletions(-) | 42 | docs/devel/conf.py | 15 ----------- |
43 | docs/index.html.in | 17 ------------ | ||
44 | docs/interop/conf.py | 28 ------------------- | ||
45 | docs/meson.build | 64 +++++++++++++++++--------------------------- | ||
46 | docs/specs/conf.py | 16 ----------- | ||
47 | docs/system/conf.py | 28 ------------------- | ||
48 | docs/tools/conf.py | 37 ------------------------- | ||
49 | docs/user/conf.py | 15 ----------- | ||
50 | 9 files changed, 70 insertions(+), 196 deletions(-) | ||
51 | delete mode 100644 docs/devel/conf.py | ||
52 | delete mode 100644 docs/index.html.in | ||
53 | delete mode 100644 docs/interop/conf.py | ||
54 | delete mode 100644 docs/specs/conf.py | ||
55 | delete mode 100644 docs/system/conf.py | ||
56 | delete mode 100644 docs/tools/conf.py | ||
57 | delete mode 100644 docs/user/conf.py | ||
40 | 58 | ||
41 | diff --git a/docs/conf.py b/docs/conf.py | 59 | diff --git a/docs/conf.py b/docs/conf.py |
42 | index XXXXXXX..XXXXXXX 100644 | 60 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/docs/conf.py | 61 | --- a/docs/conf.py |
44 | +++ b/docs/conf.py | 62 | +++ b/docs/conf.py |
45 | @@ -XXX,XX +XXX,XX @@ sys.path.insert(0, os.path.join(qemu_docdir, "sphinx")) | 63 | @@ -XXX,XX +XXX,XX @@ latex_documents = [ |
46 | 64 | ||
47 | # If your documentation needs a minimal Sphinx version, state it here. | 65 | # -- Options for manual page output --------------------------------------- |
48 | # | 66 | # Individual manual/conf.py can override this to create man pages |
49 | -# 1.3 is where the 'alabaster' theme was shipped with Sphinx. | 67 | -man_pages = [] |
50 | -needs_sphinx = '1.3' | 68 | +man_pages = [ |
51 | +# Sphinx 1.5 and earlier can't build our docs because they are too | 69 | + ('interop/qemu-ga', 'qemu-ga', |
52 | +# picky about the syntax of the argument to the option:: directive | 70 | + 'QEMU Guest Agent', |
53 | +# (see Sphinx bugs #646, #3366). | 71 | + ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8), |
54 | +needs_sphinx = '1.6' | 72 | + ('interop/qemu-ga-ref', 'qemu-ga-ref', |
55 | 73 | + 'QEMU Guest Agent Protocol Reference', | |
56 | # Add any Sphinx extension module names here, as strings. They can be | 74 | + [], 7), |
57 | # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom | 75 | + ('interop/qemu-qmp-ref', 'qemu-qmp-ref', |
76 | + 'QEMU QMP Reference Manual', | ||
77 | + [], 7), | ||
78 | + ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', | ||
79 | + 'QEMU Storage Daemon QMP Reference Manual', | ||
80 | + [], 7), | ||
81 | + ('system/qemu-manpage', 'qemu', | ||
82 | + 'QEMU User Documentation', | ||
83 | + ['Fabrice Bellard'], 1), | ||
84 | + ('system/qemu-block-drivers', 'qemu-block-drivers', | ||
85 | + 'QEMU block drivers reference', | ||
86 | + ['Fabrice Bellard and the QEMU Project developers'], 7), | ||
87 | + ('system/qemu-cpu-models', 'qemu-cpu-models', | ||
88 | + 'QEMU CPU Models', | ||
89 | + ['The QEMU Project developers'], 7), | ||
90 | + ('tools/qemu-img', 'qemu-img', | ||
91 | + 'QEMU disk image utility', | ||
92 | + ['Fabrice Bellard'], 1), | ||
93 | + ('tools/qemu-nbd', 'qemu-nbd', | ||
94 | + 'QEMU Disk Network Block Device Server', | ||
95 | + ['Anthony Liguori <anthony@codemonkey.ws>'], 8), | ||
96 | + ('tools/qemu-pr-helper', 'qemu-pr-helper', | ||
97 | + 'QEMU persistent reservation helper', | ||
98 | + [], 8), | ||
99 | + ('tools/qemu-storage-daemon', 'qemu-storage-daemon', | ||
100 | + 'QEMU storage daemon', | ||
101 | + [], 1), | ||
102 | + ('tools/qemu-trace-stap', 'qemu-trace-stap', | ||
103 | + 'QEMU SystemTap trace tool', | ||
104 | + [], 1), | ||
105 | + ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper', | ||
106 | + 'QEMU 9p virtfs proxy filesystem helper', | ||
107 | + ['M. Mohan Kumar'], 1), | ||
108 | + ('tools/virtiofsd', 'virtiofsd', | ||
109 | + 'QEMU virtio-fs shared file system daemon', | ||
110 | + ['Stefan Hajnoczi <stefanha@redhat.com>', | ||
111 | + 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1), | ||
112 | +] | ||
113 | |||
114 | # -- Options for Texinfo output ------------------------------------------- | ||
115 | |||
116 | diff --git a/docs/devel/conf.py b/docs/devel/conf.py | ||
117 | deleted file mode 100644 | ||
118 | index XXXXXXX..XXXXXXX | ||
119 | --- a/docs/devel/conf.py | ||
120 | +++ /dev/null | ||
121 | @@ -XXX,XX +XXX,XX @@ | ||
122 | -# -*- coding: utf-8 -*- | ||
123 | -# | ||
124 | -# QEMU documentation build configuration file for the 'devel' manual. | ||
125 | -# | ||
126 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
127 | -import sys | ||
128 | -import os | ||
129 | - | ||
130 | -qemu_docdir = os.path.abspath("..") | ||
131 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
132 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
133 | - | ||
134 | -# This slightly misuses the 'description', but is the best way to get | ||
135 | -# the manual title to appear in the sidebar. | ||
136 | -html_theme_options['description'] = u'Developer''s Guide' | ||
137 | diff --git a/docs/index.html.in b/docs/index.html.in | ||
138 | deleted file mode 100644 | ||
139 | index XXXXXXX..XXXXXXX | ||
140 | --- a/docs/index.html.in | ||
141 | +++ /dev/null | ||
142 | @@ -XXX,XX +XXX,XX @@ | ||
143 | -<!DOCTYPE html> | ||
144 | -<html lang="en"> | ||
145 | - <head> | ||
146 | - <meta charset="UTF-8"> | ||
147 | - <title>QEMU @VERSION@ Documentation</title> | ||
148 | - </head> | ||
149 | - <body> | ||
150 | - <h1>QEMU @VERSION@ Documentation</h1> | ||
151 | - <ul> | ||
152 | - <li><a href="system/index.html">System Emulation User's Guide</a></li> | ||
153 | - <li><a href="user/index.html">User Mode Emulation User's Guide</a></li> | ||
154 | - <li><a href="tools/index.html">Tools Guide</a></li> | ||
155 | - <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li> | ||
156 | - <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li> | ||
157 | - </ul> | ||
158 | - </body> | ||
159 | -</html> | ||
160 | diff --git a/docs/interop/conf.py b/docs/interop/conf.py | ||
161 | deleted file mode 100644 | ||
162 | index XXXXXXX..XXXXXXX | ||
163 | --- a/docs/interop/conf.py | ||
164 | +++ /dev/null | ||
165 | @@ -XXX,XX +XXX,XX @@ | ||
166 | -# -*- coding: utf-8 -*- | ||
167 | -# | ||
168 | -# QEMU documentation build configuration file for the 'interop' manual. | ||
169 | -# | ||
170 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
171 | -import sys | ||
172 | -import os | ||
173 | - | ||
174 | -qemu_docdir = os.path.abspath("..") | ||
175 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
176 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
177 | - | ||
178 | -# This slightly misuses the 'description', but is the best way to get | ||
179 | -# the manual title to appear in the sidebar. | ||
180 | -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide' | ||
181 | - | ||
182 | -# One entry per manual page. List of tuples | ||
183 | -# (source start file, name, description, authors, manual section). | ||
184 | -man_pages = [ | ||
185 | - ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent', | ||
186 | - ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8), | ||
187 | - ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference', | ||
188 | - [], 7), | ||
189 | - ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual', | ||
190 | - [], 7), | ||
191 | - ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', | ||
192 | - 'QEMU Storage Daemon QMP Reference Manual', [], 7), | ||
193 | -] | ||
194 | diff --git a/docs/meson.build b/docs/meson.build | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/docs/meson.build | ||
197 | +++ b/docs/meson.build | ||
198 | @@ -XXX,XX +XXX,XX @@ if build_docs | ||
199 | meson.source_root() / 'docs/sphinx/qmp_lexer.py', | ||
200 | qapi_gen_depends ] | ||
201 | |||
202 | - configure_file(output: 'index.html', | ||
203 | - input: files('index.html.in'), | ||
204 | - configuration: {'VERSION': meson.project_version()}, | ||
205 | - install_dir: qemu_docdir) | ||
206 | - manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ] | ||
207 | man_pages = { | ||
208 | - 'interop' : { | ||
209 | 'qemu-ga.8': (have_tools ? 'man8' : ''), | ||
210 | 'qemu-ga-ref.7': 'man7', | ||
211 | 'qemu-qmp-ref.7': 'man7', | ||
212 | 'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''), | ||
213 | - }, | ||
214 | - 'tools': { | ||
215 | 'qemu-img.1': (have_tools ? 'man1' : ''), | ||
216 | 'qemu-nbd.8': (have_tools ? 'man8' : ''), | ||
217 | 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), | ||
218 | @@ -XXX,XX +XXX,XX @@ if build_docs | ||
219 | 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), | ||
220 | 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), | ||
221 | 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), | ||
222 | - }, | ||
223 | - 'system': { | ||
224 | 'qemu.1': 'man1', | ||
225 | 'qemu-block-drivers.7': 'man7', | ||
226 | 'qemu-cpu-models.7': 'man7' | ||
227 | - }, | ||
228 | } | ||
229 | |||
230 | sphinxdocs = [] | ||
231 | sphinxmans = [] | ||
232 | - foreach manual : manuals | ||
233 | - private_dir = meson.current_build_dir() / (manual + '.p') | ||
234 | - output_dir = meson.current_build_dir() / manual | ||
235 | - input_dir = meson.current_source_dir() / manual | ||
236 | |||
237 | - this_manual = custom_target(manual + ' manual', | ||
238 | + private_dir = meson.current_build_dir() / 'manual.p' | ||
239 | + output_dir = meson.current_build_dir() / 'manual' | ||
240 | + input_dir = meson.current_source_dir() | ||
241 | + | ||
242 | + this_manual = custom_target('QEMU manual', | ||
243 | build_by_default: build_docs, | ||
244 | - output: [manual + '.stamp'], | ||
245 | - input: [files('conf.py'), files(manual / 'conf.py')], | ||
246 | - depfile: manual + '.d', | ||
247 | + output: 'docs.stamp', | ||
248 | + input: files('conf.py'), | ||
249 | + depfile: 'docs.d', | ||
250 | depend_files: sphinx_extn_depends, | ||
251 | command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@', | ||
252 | '-Ddepfile_stamp=@OUTPUT0@', | ||
253 | '-b', 'html', '-d', private_dir, | ||
254 | input_dir, output_dir]) | ||
255 | - sphinxdocs += this_manual | ||
256 | - if build_docs and manual != 'devel' | ||
257 | - install_subdir(output_dir, install_dir: qemu_docdir) | ||
258 | - endif | ||
259 | + sphinxdocs += this_manual | ||
260 | + install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true) | ||
261 | |||
262 | - these_man_pages = [] | ||
263 | - install_dirs = [] | ||
264 | - foreach page, section : man_pages.get(manual, {}) | ||
265 | - these_man_pages += page | ||
266 | - install_dirs += section == '' ? false : get_option('mandir') / section | ||
267 | - endforeach | ||
268 | - if these_man_pages.length() > 0 | ||
269 | - sphinxmans += custom_target(manual + ' man pages', | ||
270 | - build_by_default: build_docs, | ||
271 | - output: these_man_pages, | ||
272 | - input: this_manual, | ||
273 | - install: build_docs, | ||
274 | - install_dir: install_dirs, | ||
275 | - command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, | ||
276 | - input_dir, meson.current_build_dir()]) | ||
277 | - endif | ||
278 | + these_man_pages = [] | ||
279 | + install_dirs = [] | ||
280 | + foreach page, section : man_pages | ||
281 | + these_man_pages += page | ||
282 | + install_dirs += section == '' ? false : get_option('mandir') / section | ||
283 | endforeach | ||
284 | + | ||
285 | + sphinxmans += custom_target('QEMU man pages', | ||
286 | + build_by_default: build_docs, | ||
287 | + output: these_man_pages, | ||
288 | + input: this_manual, | ||
289 | + install: build_docs, | ||
290 | + install_dir: install_dirs, | ||
291 | + command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, | ||
292 | + input_dir, meson.current_build_dir()]) | ||
293 | + | ||
294 | alias_target('sphinxdocs', sphinxdocs) | ||
295 | alias_target('html', sphinxdocs) | ||
296 | alias_target('man', sphinxmans) | ||
297 | diff --git a/docs/specs/conf.py b/docs/specs/conf.py | ||
298 | deleted file mode 100644 | ||
299 | index XXXXXXX..XXXXXXX | ||
300 | --- a/docs/specs/conf.py | ||
301 | +++ /dev/null | ||
302 | @@ -XXX,XX +XXX,XX @@ | ||
303 | -# -*- coding: utf-8 -*- | ||
304 | -# | ||
305 | -# QEMU documentation build configuration file for the 'specs' manual. | ||
306 | -# | ||
307 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
308 | -import sys | ||
309 | -import os | ||
310 | - | ||
311 | -qemu_docdir = os.path.abspath("..") | ||
312 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
313 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
314 | - | ||
315 | -# This slightly misuses the 'description', but is the best way to get | ||
316 | -# the manual title to appear in the sidebar. | ||
317 | -html_theme_options['description'] = \ | ||
318 | - u'System Emulation Guest Hardware Specifications' | ||
319 | diff --git a/docs/system/conf.py b/docs/system/conf.py | ||
320 | deleted file mode 100644 | ||
321 | index XXXXXXX..XXXXXXX | ||
322 | --- a/docs/system/conf.py | ||
323 | +++ /dev/null | ||
324 | @@ -XXX,XX +XXX,XX @@ | ||
325 | -# -*- coding: utf-8 -*- | ||
326 | -# | ||
327 | -# QEMU documentation build configuration file for the 'system' manual. | ||
328 | -# | ||
329 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
330 | -import sys | ||
331 | -import os | ||
332 | - | ||
333 | -qemu_docdir = os.path.abspath("..") | ||
334 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
335 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
336 | - | ||
337 | -# This slightly misuses the 'description', but is the best way to get | ||
338 | -# the manual title to appear in the sidebar. | ||
339 | -html_theme_options['description'] = u'System Emulation User''s Guide' | ||
340 | - | ||
341 | -# One entry per manual page. List of tuples | ||
342 | -# (source start file, name, description, authors, manual section). | ||
343 | -man_pages = [ | ||
344 | - ('qemu-manpage', 'qemu', u'QEMU User Documentation', | ||
345 | - ['Fabrice Bellard'], 1), | ||
346 | - ('qemu-block-drivers', 'qemu-block-drivers', | ||
347 | - u'QEMU block drivers reference', | ||
348 | - ['Fabrice Bellard and the QEMU Project developers'], 7), | ||
349 | - ('qemu-cpu-models', 'qemu-cpu-models', | ||
350 | - u'QEMU CPU Models', | ||
351 | - ['The QEMU Project developers'], 7) | ||
352 | -] | ||
353 | diff --git a/docs/tools/conf.py b/docs/tools/conf.py | ||
354 | deleted file mode 100644 | ||
355 | index XXXXXXX..XXXXXXX | ||
356 | --- a/docs/tools/conf.py | ||
357 | +++ /dev/null | ||
358 | @@ -XXX,XX +XXX,XX @@ | ||
359 | -# -*- coding: utf-8 -*- | ||
360 | -# | ||
361 | -# QEMU documentation build configuration file for the 'tools' manual. | ||
362 | -# | ||
363 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
364 | -import sys | ||
365 | -import os | ||
366 | - | ||
367 | -qemu_docdir = os.path.abspath("..") | ||
368 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
369 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
370 | - | ||
371 | -# This slightly misuses the 'description', but is the best way to get | ||
372 | -# the manual title to appear in the sidebar. | ||
373 | -html_theme_options['description'] = \ | ||
374 | - u'Tools Guide' | ||
375 | - | ||
376 | -# One entry per manual page. List of tuples | ||
377 | -# (source start file, name, description, authors, manual section). | ||
378 | -man_pages = [ | ||
379 | - ('qemu-img', 'qemu-img', u'QEMU disk image utility', | ||
380 | - ['Fabrice Bellard'], 1), | ||
381 | - ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon', | ||
382 | - [], 1), | ||
383 | - ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server', | ||
384 | - ['Anthony Liguori <anthony@codemonkey.ws>'], 8), | ||
385 | - ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper', | ||
386 | - [], 8), | ||
387 | - ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool', | ||
388 | - [], 1), | ||
389 | - ('virtfs-proxy-helper', 'virtfs-proxy-helper', | ||
390 | - u'QEMU 9p virtfs proxy filesystem helper', | ||
391 | - ['M. Mohan Kumar'], 1), | ||
392 | - ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon', | ||
393 | - ['Stefan Hajnoczi <stefanha@redhat.com>', | ||
394 | - 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1), | ||
395 | -] | ||
396 | diff --git a/docs/user/conf.py b/docs/user/conf.py | ||
397 | deleted file mode 100644 | ||
398 | index XXXXXXX..XXXXXXX | ||
399 | --- a/docs/user/conf.py | ||
400 | +++ /dev/null | ||
401 | @@ -XXX,XX +XXX,XX @@ | ||
402 | -# -*- coding: utf-8 -*- | ||
403 | -# | ||
404 | -# QEMU documentation build configuration file for the 'user' manual. | ||
405 | -# | ||
406 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
407 | -import sys | ||
408 | -import os | ||
409 | - | ||
410 | -qemu_docdir = os.path.abspath("..") | ||
411 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
412 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
413 | - | ||
414 | -# This slightly misuses the 'description', but is the best way to get | ||
415 | -# the manual title to appear in the sidebar. | ||
416 | -html_theme_options['description'] = u'User Mode Emulation User''s Guide' | ||
58 | -- | 417 | -- |
59 | 2.20.1 | 418 | 2.20.1 |
60 | 419 | ||
61 | 420 | diff view generated by jsdifflib |
1 | All the Coverity-specific definitions of qemu_mutex_lock() and friends | 1 | In commit cd8be50e58f63413c0 we converted the A32 coprocessor |
---|---|---|---|
2 | have a trailing semicolon. This works fine almost everywhere because | 2 | insns to decodetree. This accidentally broke XScale/iWMMXt insns, |
3 | of QEMU's mandatory-braces coding style and because most callsites are | 3 | because it moved the handling of "cp insns which are handled |
4 | simple, but target/s390x/sigp.c has a use of qemu_mutex_trylock() as | 4 | by looking up the cp register in the hashtable" from after the |
5 | an if() statement, which makes the ';' a syntax error: | 5 | call to the legacy disas_xscale_insn() decode to before it, |
6 | "../target/s390x/sigp.c", line 461: warning #18: expected a ")" | 6 | with the result that all XScale/iWMMXt insns now UNDEF. |
7 | if (qemu_mutex_trylock(&qemu_sigp_mutex)) { | ||
8 | ^ | ||
9 | 7 | ||
10 | Remove the bogus semicolons from the macro definitions. | 8 | Update valid_cp() so that it knows that on XScale cp 0 and 1 |
9 | are not standard coprocessor instructions; this will cause | ||
10 | the decodetree trans_ functions to ignore them, so that | ||
11 | execution will correctly get through to the legacy decode again. | ||
11 | 12 | ||
13 | Cc: qemu-stable@nongnu.org | ||
14 | Reported-by: Guenter Roeck <linux@roeck-us.net> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 17 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
15 | Message-id: 20200319193323.2038-4-peter.maydell@linaro.org | 18 | Message-id: 20210108195157.32067-1-peter.maydell@linaro.org |
16 | --- | 19 | --- |
17 | include/qemu/thread.h | 12 ++++++------ | 20 | target/arm/translate.c | 7 +++++++ |
18 | 1 file changed, 6 insertions(+), 6 deletions(-) | 21 | 1 file changed, 7 insertions(+) |
19 | 22 | ||
20 | diff --git a/include/qemu/thread.h b/include/qemu/thread.h | 23 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
21 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/qemu/thread.h | 25 | --- a/target/arm/translate.c |
23 | +++ b/include/qemu/thread.h | 26 | +++ b/target/arm/translate.c |
24 | @@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func; | 27 | @@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp) |
25 | * hide them. | 28 | * only cp14 and cp15 are valid, and other values aren't considered |
26 | */ | 29 | * to be in the coprocessor-instruction space at all. v8M still |
27 | #define qemu_mutex_lock(m) \ | 30 | * permits coprocessors 0..7. |
28 | - qemu_mutex_lock_impl(m, __FILE__, __LINE__); | 31 | + * For XScale, we must not decode the XScale cp0, cp1 space as |
29 | + qemu_mutex_lock_impl(m, __FILE__, __LINE__) | 32 | + * a standard coprocessor insn, because we want to fall through to |
30 | #define qemu_mutex_trylock(m) \ | 33 | + * the legacy disas_xscale_insn() decoder after decodetree is done. |
31 | - qemu_mutex_trylock_impl(m, __FILE__, __LINE__); | 34 | */ |
32 | + qemu_mutex_trylock_impl(m, __FILE__, __LINE__) | 35 | + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { |
33 | #define qemu_rec_mutex_lock(m) \ | 36 | + return false; |
34 | - qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__); | 37 | + } |
35 | + qemu_rec_mutex_lock_impl(m, __FILE__, __LINE__) | 38 | + |
36 | #define qemu_rec_mutex_trylock(m) \ | 39 | if (arm_dc_feature(s, ARM_FEATURE_V8) && |
37 | - qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__); | 40 | !arm_dc_feature(s, ARM_FEATURE_M)) { |
38 | + qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__) | 41 | return cp >= 14; |
39 | #define qemu_cond_wait(c, m) \ | ||
40 | - qemu_cond_wait_impl(c, m, __FILE__, __LINE__); | ||
41 | + qemu_cond_wait_impl(c, m, __FILE__, __LINE__) | ||
42 | #define qemu_cond_timedwait(c, m, ms) \ | ||
43 | - qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__); | ||
44 | + qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__) | ||
45 | #else | ||
46 | #define qemu_mutex_lock(m) ({ \ | ||
47 | QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func); \ | ||
48 | -- | 42 | -- |
49 | 2.20.1 | 43 | 2.20.1 |
50 | 44 | ||
51 | 45 | diff view generated by jsdifflib |
1 | For Coverity's benefit, we provide simpler versions of functions like | 1 | A copy-and-paste error meant that the return value for register offset 0x44 |
---|---|---|---|
2 | qemu_mutex_lock(), qemu_cond_wait() and qemu_cond_timedwait(). When | 2 | (the RX Status FIFO PEEK register) returned a byte from a bogus offset in |
3 | we added qemu_cond_timedwait() in commit 3dcc9c6ec4ea, a cut and | 3 | the rx status FIFO. Fix the typo. |
4 | paste error meant that the Coverity version of qemu_cond_timedwait() | ||
5 | was using the wrong _impl function, which makes the Coverity parser | ||
6 | complain: | ||
7 | 4 | ||
8 | "/qemu/include/qemu/thread.h", line 159: warning #140: too many arguments in | 5 | Cc: qemu-stable@nongnu.org |
9 | function call | 6 | Fixes: https://bugs.launchpad.net/qemu/+bug/1904954 |
10 | return qemu_cond_timedwait(cond, mutex, ms); | ||
11 | ^ | ||
12 | |||
13 | "/qemu/include/qemu/thread.h", line 159: warning #120: return value type does | ||
14 | not match the function type | ||
15 | return qemu_cond_timedwait(cond, mutex, ms); | ||
16 | ^ | ||
17 | |||
18 | "/qemu/include/qemu/thread.h", line 156: warning #1563: function | ||
19 | "qemu_cond_timedwait" not emitted, consider modeling it or review | ||
20 | parse diagnostics to improve fidelity | ||
21 | static inline bool (qemu_cond_timedwait)(QemuCond *cond, QemuMutex *mutex, | ||
22 | ^ | ||
23 | |||
24 | These aren't fatal, but reduce the scope of the analysis. Fix the error. | ||
25 | |||
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
28 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 9 | Message-id: 20210108180401.2263-2-peter.maydell@linaro.org |
29 | Message-id: 20200319193323.2038-3-peter.maydell@linaro.org | ||
30 | --- | 10 | --- |
31 | include/qemu/thread.h | 2 +- | 11 | hw/net/lan9118.c | 2 +- |
32 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
33 | 13 | ||
34 | diff --git a/include/qemu/thread.h b/include/qemu/thread.h | 14 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c |
35 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/include/qemu/thread.h | 16 | --- a/hw/net/lan9118.c |
37 | +++ b/include/qemu/thread.h | 17 | +++ b/hw/net/lan9118.c |
38 | @@ -XXX,XX +XXX,XX @@ extern QemuCondTimedWaitFunc qemu_cond_timedwait_func; | 18 | @@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, |
39 | #define qemu_cond_wait(c, m) \ | 19 | case 0x40: |
40 | qemu_cond_wait_impl(c, m, __FILE__, __LINE__); | 20 | return rx_status_fifo_pop(s); |
41 | #define qemu_cond_timedwait(c, m, ms) \ | 21 | case 0x44: |
42 | - qemu_cond_wait_impl(c, m, ms, __FILE__, __LINE__); | 22 | - return s->rx_status_fifo[s->tx_status_fifo_head]; |
43 | + qemu_cond_timedwait_impl(c, m, ms, __FILE__, __LINE__); | 23 | + return s->rx_status_fifo[s->rx_status_fifo_head]; |
44 | #else | 24 | case 0x48: |
45 | #define qemu_mutex_lock(m) ({ \ | 25 | return tx_status_fifo_pop(s); |
46 | QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func); \ | 26 | case 0x4c: |
47 | -- | 27 | -- |
48 | 2.20.1 | 28 | 2.20.1 |
49 | 29 | ||
50 | 30 | diff view generated by jsdifflib |
1 | The Linux kernel has dropped support for allowing 32-bit Arm systems | 1 | The lan9118 code mostly uses symbolic constants for register offsets; |
---|---|---|---|
2 | to host KVM guests (kernel commit 541ad0150ca4aa663a2, which just | 2 | the exceptions are those which the datasheet doesn't give an official |
3 | landed upstream in the 5.7 merge window). Mark QEMU's support for | 3 | symbolic name to. |
4 | this configuration as deprecated, so that we can delete that support | 4 | |
5 | code in 5.2. | 5 | Add some names for the registers which don't already have them, based |
6 | on the longer names they are given in the memory map. | ||
6 | 7 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Andrew Jones <drjones@redhat.com> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Message-id: 20210108180401.2263-3-peter.maydell@linaro.org | ||
9 | --- | 11 | --- |
10 | docs/system/deprecated.rst | 8 ++++++++ | 12 | hw/net/lan9118.c | 24 ++++++++++++++++++------ |
11 | 1 file changed, 8 insertions(+) | 13 | 1 file changed, 18 insertions(+), 6 deletions(-) |
12 | 14 | ||
13 | diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst | 15 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/docs/system/deprecated.rst | 17 | --- a/hw/net/lan9118.c |
16 | +++ b/docs/system/deprecated.rst | 18 | +++ b/hw/net/lan9118.c |
17 | @@ -XXX,XX +XXX,XX @@ The ``compat`` property used to set backwards compatibility modes for | 19 | @@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
18 | the processor has been deprecated. The ``max-cpu-compat`` property of | 20 | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
19 | the ``pseries`` machine type should be used instead. | 21 | #endif |
20 | 22 | ||
21 | +KVM guest support on 32-bit Arm hosts (since 5.0) | 23 | +/* The tx and rx fifo ports are a range of aliased 32-bit registers */ |
22 | +''''''''''''''''''''''''''''''''''''''''''''''''' | 24 | +#define RX_DATA_FIFO_PORT_FIRST 0x00 |
25 | +#define RX_DATA_FIFO_PORT_LAST 0x1f | ||
26 | +#define TX_DATA_FIFO_PORT_FIRST 0x20 | ||
27 | +#define TX_DATA_FIFO_PORT_LAST 0x3f | ||
23 | + | 28 | + |
24 | +The Linux kernel has dropped support for allowing 32-bit Arm systems | 29 | +#define RX_STATUS_FIFO_PORT 0x40 |
25 | +to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating | 30 | +#define RX_STATUS_FIFO_PEEK 0x44 |
26 | +its support for this configuration and will remove it in a future version. | 31 | +#define TX_STATUS_FIFO_PORT 0x48 |
27 | +Running 32-bit guests on a 64-bit Arm host remains supported. | 32 | +#define TX_STATUS_FIFO_PEEK 0x4c |
28 | + | 33 | + |
29 | System emulator devices | 34 | #define CSR_ID_REV 0x50 |
30 | ----------------------- | 35 | #define CSR_IRQ_CFG 0x54 |
31 | 36 | #define CSR_INT_STS 0x58 | |
37 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
38 | offset &= 0xff; | ||
39 | |||
40 | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); | ||
41 | - if (offset >= 0x20 && offset < 0x40) { | ||
42 | + if (offset >= TX_DATA_FIFO_PORT_FIRST && | ||
43 | + offset <= TX_DATA_FIFO_PORT_LAST) { | ||
44 | /* TX FIFO */ | ||
45 | tx_fifo_push(s, val); | ||
46 | return; | ||
47 | @@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, | ||
48 | lan9118_state *s = (lan9118_state *)opaque; | ||
49 | |||
50 | //DPRINTF("Read reg 0x%02x\n", (int)offset); | ||
51 | - if (offset < 0x20) { | ||
52 | + if (offset <= RX_DATA_FIFO_PORT_LAST) { | ||
53 | /* RX FIFO */ | ||
54 | return rx_fifo_pop(s); | ||
55 | } | ||
56 | switch (offset) { | ||
57 | - case 0x40: | ||
58 | + case RX_STATUS_FIFO_PORT: | ||
59 | return rx_status_fifo_pop(s); | ||
60 | - case 0x44: | ||
61 | + case RX_STATUS_FIFO_PEEK: | ||
62 | return s->rx_status_fifo[s->rx_status_fifo_head]; | ||
63 | - case 0x48: | ||
64 | + case TX_STATUS_FIFO_PORT: | ||
65 | return tx_status_fifo_pop(s); | ||
66 | - case 0x4c: | ||
67 | + case TX_STATUS_FIFO_PEEK: | ||
68 | return s->tx_status_fifo[s->tx_status_fifo_head]; | ||
69 | case CSR_ID_REV: | ||
70 | return 0x01180001; | ||
32 | -- | 71 | -- |
33 | 2.20.1 | 72 | 2.20.1 |
34 | 73 | ||
35 | 74 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
1 | 2 | ||
3 | This patch allows NPCM7XX CLK module to compute clocks that are used by | ||
4 | other NPCM7XX modules. | ||
5 | |||
6 | Add a new struct NPCM7xxClockConverterState which represents a | ||
7 | single converter. Each clock converter in CLK module represents one | ||
8 | converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter | ||
9 | takes one or more input clocks and converts them into one output clock. | ||
10 | They form a clock hierarchy in the CLK module and are responsible for | ||
11 | outputing clocks for various other modules in an NPCM7XX SoC. | ||
12 | |||
13 | Each converter has a function pointer called "convert" which represents | ||
14 | the unique logic for that converter. | ||
15 | |||
16 | The clock contains two initialization information: ConverterInitInfo and | ||
17 | ConverterConnectionInfo. They represent the vertices and edges in the | ||
18 | clock diagram respectively. | ||
19 | |||
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
21 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
22 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | Message-id: 20210108190945.949196-2-wuhaotsh@google.com | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | --- | ||
27 | include/hw/misc/npcm7xx_clk.h | 140 +++++- | ||
28 | hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++- | ||
29 | 2 files changed, 932 insertions(+), 13 deletions(-) | ||
30 | |||
31 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/include/hw/misc/npcm7xx_clk.h | ||
34 | +++ b/include/hw/misc/npcm7xx_clk.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | #define NPCM7XX_CLK_H | ||
37 | |||
38 | #include "exec/memory.h" | ||
39 | +#include "hw/clock.h" | ||
40 | #include "hw/sysbus.h" | ||
41 | |||
42 | /* | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | |||
45 | #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" | ||
46 | |||
47 | -typedef struct NPCM7xxCLKState { | ||
48 | +/* Maximum amount of clock inputs in a SEL module. */ | ||
49 | +#define NPCM7XX_CLK_SEL_MAX_INPUT 5 | ||
50 | + | ||
51 | +/* PLLs in CLK module. */ | ||
52 | +typedef enum NPCM7xxClockPLL { | ||
53 | + NPCM7XX_CLOCK_PLL0, | ||
54 | + NPCM7XX_CLOCK_PLL1, | ||
55 | + NPCM7XX_CLOCK_PLL2, | ||
56 | + NPCM7XX_CLOCK_PLLG, | ||
57 | + NPCM7XX_CLOCK_NR_PLLS, | ||
58 | +} NPCM7xxClockPLL; | ||
59 | + | ||
60 | +/* SEL/MUX in CLK module. */ | ||
61 | +typedef enum NPCM7xxClockSEL { | ||
62 | + NPCM7XX_CLOCK_PIXCKSEL, | ||
63 | + NPCM7XX_CLOCK_MCCKSEL, | ||
64 | + NPCM7XX_CLOCK_CPUCKSEL, | ||
65 | + NPCM7XX_CLOCK_CLKOUTSEL, | ||
66 | + NPCM7XX_CLOCK_UARTCKSEL, | ||
67 | + NPCM7XX_CLOCK_TIMCKSEL, | ||
68 | + NPCM7XX_CLOCK_SDCKSEL, | ||
69 | + NPCM7XX_CLOCK_GFXMSEL, | ||
70 | + NPCM7XX_CLOCK_SUCKSEL, | ||
71 | + NPCM7XX_CLOCK_NR_SELS, | ||
72 | +} NPCM7xxClockSEL; | ||
73 | + | ||
74 | +/* Dividers in CLK module. */ | ||
75 | +typedef enum NPCM7xxClockDivider { | ||
76 | + NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */ | ||
77 | + NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */ | ||
78 | + NPCM7XX_CLOCK_MC_DIVIDER, | ||
79 | + NPCM7XX_CLOCK_AXI_DIVIDER, | ||
80 | + NPCM7XX_CLOCK_AHB_DIVIDER, | ||
81 | + NPCM7XX_CLOCK_AHB3_DIVIDER, | ||
82 | + NPCM7XX_CLOCK_SPI0_DIVIDER, | ||
83 | + NPCM7XX_CLOCK_SPIX_DIVIDER, | ||
84 | + NPCM7XX_CLOCK_APB1_DIVIDER, | ||
85 | + NPCM7XX_CLOCK_APB2_DIVIDER, | ||
86 | + NPCM7XX_CLOCK_APB3_DIVIDER, | ||
87 | + NPCM7XX_CLOCK_APB4_DIVIDER, | ||
88 | + NPCM7XX_CLOCK_APB5_DIVIDER, | ||
89 | + NPCM7XX_CLOCK_CLKOUT_DIVIDER, | ||
90 | + NPCM7XX_CLOCK_UART_DIVIDER, | ||
91 | + NPCM7XX_CLOCK_TIMER_DIVIDER, | ||
92 | + NPCM7XX_CLOCK_ADC_DIVIDER, | ||
93 | + NPCM7XX_CLOCK_MMC_DIVIDER, | ||
94 | + NPCM7XX_CLOCK_SDHC_DIVIDER, | ||
95 | + NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */ | ||
96 | + NPCM7XX_CLOCK_UTMI_DIVIDER, | ||
97 | + NPCM7XX_CLOCK_NR_DIVIDERS, | ||
98 | +} NPCM7xxClockConverter; | ||
99 | + | ||
100 | +typedef struct NPCM7xxCLKState NPCM7xxCLKState; | ||
101 | + | ||
102 | +/** | ||
103 | + * struct NPCM7xxClockPLLState - A PLL module in CLK module. | ||
104 | + * @name: The name of the module. | ||
105 | + * @clk: The CLK module that owns this module. | ||
106 | + * @clock_in: The input clock of this module. | ||
107 | + * @clock_out: The output clock of this module. | ||
108 | + * @reg: The control registers for this PLL module. | ||
109 | + */ | ||
110 | +typedef struct NPCM7xxClockPLLState { | ||
111 | + DeviceState parent; | ||
112 | + | ||
113 | + const char *name; | ||
114 | + NPCM7xxCLKState *clk; | ||
115 | + Clock *clock_in; | ||
116 | + Clock *clock_out; | ||
117 | + | ||
118 | + int reg; | ||
119 | +} NPCM7xxClockPLLState; | ||
120 | + | ||
121 | +/** | ||
122 | + * struct NPCM7xxClockSELState - A SEL module in CLK module. | ||
123 | + * @name: The name of the module. | ||
124 | + * @clk: The CLK module that owns this module. | ||
125 | + * @input_size: The size of inputs of this module. | ||
126 | + * @clock_in: The input clocks of this module. | ||
127 | + * @clock_out: The output clocks of this module. | ||
128 | + * @offset: The offset of this module in the control register. | ||
129 | + * @len: The length of this module in the control register. | ||
130 | + */ | ||
131 | +typedef struct NPCM7xxClockSELState { | ||
132 | + DeviceState parent; | ||
133 | + | ||
134 | + const char *name; | ||
135 | + NPCM7xxCLKState *clk; | ||
136 | + uint8_t input_size; | ||
137 | + Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
138 | + Clock *clock_out; | ||
139 | + | ||
140 | + int offset; | ||
141 | + int len; | ||
142 | +} NPCM7xxClockSELState; | ||
143 | + | ||
144 | +/** | ||
145 | + * struct NPCM7xxClockDividerState - A Divider module in CLK module. | ||
146 | + * @name: The name of the module. | ||
147 | + * @clk: The CLK module that owns this module. | ||
148 | + * @clock_in: The input clock of this module. | ||
149 | + * @clock_out: The output clock of this module. | ||
150 | + * @divide: The function the divider uses to divide the input. | ||
151 | + * @reg: The index of the control register that contains the divisor. | ||
152 | + * @offset: The offset of the divisor in the control register. | ||
153 | + * @len: The length of the divisor in the control register. | ||
154 | + * @divisor: The divisor for a constant divisor | ||
155 | + */ | ||
156 | +typedef struct NPCM7xxClockDividerState { | ||
157 | + DeviceState parent; | ||
158 | + | ||
159 | + const char *name; | ||
160 | + NPCM7xxCLKState *clk; | ||
161 | + Clock *clock_in; | ||
162 | + Clock *clock_out; | ||
163 | + | ||
164 | + uint32_t (*divide)(struct NPCM7xxClockDividerState *s); | ||
165 | + union { | ||
166 | + struct { | ||
167 | + int reg; | ||
168 | + int offset; | ||
169 | + int len; | ||
170 | + }; | ||
171 | + int divisor; | ||
172 | + }; | ||
173 | +} NPCM7xxClockDividerState; | ||
174 | + | ||
175 | +struct NPCM7xxCLKState { | ||
176 | SysBusDevice parent; | ||
177 | |||
178 | MemoryRegion iomem; | ||
179 | |||
180 | + /* Clock converters */ | ||
181 | + NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; | ||
182 | + NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; | ||
183 | + NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; | ||
184 | + | ||
185 | uint32_t regs[NPCM7XX_CLK_NR_REGS]; | ||
186 | |||
187 | /* Time reference for SECCNT and CNTR25M, initialized by power on reset */ | ||
188 | int64_t ref_ns; | ||
189 | -} NPCM7xxCLKState; | ||
190 | + | ||
191 | + /* The incoming reference clock. */ | ||
192 | + Clock *clkref; | ||
193 | +}; | ||
194 | |||
195 | #define TYPE_NPCM7XX_CLK "npcm7xx-clk" | ||
196 | #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) | ||
197 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c | ||
198 | index XXXXXXX..XXXXXXX 100644 | ||
199 | --- a/hw/misc/npcm7xx_clk.c | ||
200 | +++ b/hw/misc/npcm7xx_clk.c | ||
201 | @@ -XXX,XX +XXX,XX @@ | ||
202 | |||
203 | #include "hw/misc/npcm7xx_clk.h" | ||
204 | #include "hw/timer/npcm7xx_timer.h" | ||
205 | +#include "hw/qdev-clock.h" | ||
206 | #include "migration/vmstate.h" | ||
207 | #include "qemu/error-report.h" | ||
208 | #include "qemu/log.h" | ||
209 | @@ -XXX,XX +XXX,XX @@ | ||
210 | #include "trace.h" | ||
211 | #include "sysemu/watchdog.h" | ||
212 | |||
213 | +/* | ||
214 | + * The reference clock hz, and the SECCNT and CNTR25M registers in this module, | ||
215 | + * is always 25 MHz. | ||
216 | + */ | ||
217 | +#define NPCM7XX_CLOCK_REF_HZ (25000000) | ||
218 | + | ||
219 | +/* Register Field Definitions */ | ||
220 | +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ | ||
221 | + | ||
222 | #define PLLCON_LOKI BIT(31) | ||
223 | #define PLLCON_LOKS BIT(30) | ||
224 | #define PLLCON_PWDEN BIT(12) | ||
225 | +#define PLLCON_FBDV(con) extract32((con), 16, 12) | ||
226 | +#define PLLCON_OTDV2(con) extract32((con), 13, 3) | ||
227 | +#define PLLCON_OTDV1(con) extract32((con), 8, 3) | ||
228 | +#define PLLCON_INDV(con) extract32((con), 0, 6) | ||
229 | |||
230 | enum NPCM7xxCLKRegisters { | ||
231 | NPCM7XX_CLK_CLKEN1, | ||
232 | @@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = { | ||
233 | [NPCM7XX_CLK_AHBCKFI] = 0x000000c8, | ||
234 | }; | ||
235 | |||
236 | -/* Register Field Definitions */ | ||
237 | -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ | ||
238 | - | ||
239 | /* The number of watchdogs that can trigger a reset. */ | ||
240 | #define NPCM7XX_NR_WATCHDOGS (3) | ||
241 | |||
242 | +/* Clock converter functions */ | ||
243 | + | ||
244 | +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll" | ||
245 | +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \ | ||
246 | + (obj), TYPE_NPCM7XX_CLOCK_PLL) | ||
247 | +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel" | ||
248 | +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \ | ||
249 | + (obj), TYPE_NPCM7XX_CLOCK_SEL) | ||
250 | +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider" | ||
251 | +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \ | ||
252 | + (obj), TYPE_NPCM7XX_CLOCK_DIVIDER) | ||
253 | + | ||
254 | +static void npcm7xx_clk_update_pll(void *opaque) | ||
255 | +{ | ||
256 | + NPCM7xxClockPLLState *s = opaque; | ||
257 | + uint32_t con = s->clk->regs[s->reg]; | ||
258 | + uint64_t freq; | ||
259 | + | ||
260 | + /* The PLL is grounded if it is not locked yet. */ | ||
261 | + if (con & PLLCON_LOKI) { | ||
262 | + freq = clock_get_hz(s->clock_in); | ||
263 | + freq *= PLLCON_FBDV(con); | ||
264 | + freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); | ||
265 | + } else { | ||
266 | + freq = 0; | ||
267 | + } | ||
268 | + | ||
269 | + clock_update_hz(s->clock_out, freq); | ||
270 | +} | ||
271 | + | ||
272 | +static void npcm7xx_clk_update_sel(void *opaque) | ||
273 | +{ | ||
274 | + NPCM7xxClockSELState *s = opaque; | ||
275 | + uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, | ||
276 | + s->len); | ||
277 | + | ||
278 | + if (index >= s->input_size) { | ||
279 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
280 | + "%s: SEL index: %u out of range\n", | ||
281 | + __func__, index); | ||
282 | + index = 0; | ||
283 | + } | ||
284 | + clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); | ||
285 | +} | ||
286 | + | ||
287 | +static void npcm7xx_clk_update_divider(void *opaque) | ||
288 | +{ | ||
289 | + NPCM7xxClockDividerState *s = opaque; | ||
290 | + uint32_t freq; | ||
291 | + | ||
292 | + freq = s->divide(s); | ||
293 | + clock_update_hz(s->clock_out, freq); | ||
294 | +} | ||
295 | + | ||
296 | +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s) | ||
297 | +{ | ||
298 | + return clock_get_hz(s->clock_in) / s->divisor; | ||
299 | +} | ||
300 | + | ||
301 | +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s) | ||
302 | +{ | ||
303 | + return clock_get_hz(s->clock_in) / | ||
304 | + (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); | ||
305 | +} | ||
306 | + | ||
307 | +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s) | ||
308 | +{ | ||
309 | + return divide_by_reg_divisor(s) / 2; | ||
310 | +} | ||
311 | + | ||
312 | +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s) | ||
313 | +{ | ||
314 | + return clock_get_hz(s->clock_in) >> | ||
315 | + extract32(s->clk->regs[s->reg], s->offset, s->len); | ||
316 | +} | ||
317 | + | ||
318 | +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg) | ||
319 | +{ | ||
320 | + switch (reg) { | ||
321 | + case NPCM7XX_CLK_PLLCON0: | ||
322 | + return NPCM7XX_CLOCK_PLL0; | ||
323 | + case NPCM7XX_CLK_PLLCON1: | ||
324 | + return NPCM7XX_CLOCK_PLL1; | ||
325 | + case NPCM7XX_CLK_PLLCON2: | ||
326 | + return NPCM7XX_CLOCK_PLL2; | ||
327 | + case NPCM7XX_CLK_PLLCONG: | ||
328 | + return NPCM7XX_CLOCK_PLLG; | ||
329 | + default: | ||
330 | + g_assert_not_reached(); | ||
331 | + } | ||
332 | +} | ||
333 | + | ||
334 | +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) | ||
335 | +{ | ||
336 | + int i; | ||
337 | + | ||
338 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
339 | + npcm7xx_clk_update_pll(&clk->plls[i]); | ||
340 | + } | ||
341 | +} | ||
342 | + | ||
343 | +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) | ||
344 | +{ | ||
345 | + int i; | ||
346 | + | ||
347 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
348 | + npcm7xx_clk_update_sel(&clk->sels[i]); | ||
349 | + } | ||
350 | +} | ||
351 | + | ||
352 | +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) | ||
353 | +{ | ||
354 | + int i; | ||
355 | + | ||
356 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
357 | + npcm7xx_clk_update_divider(&clk->dividers[i]); | ||
358 | + } | ||
359 | +} | ||
360 | + | ||
361 | +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) | ||
362 | +{ | ||
363 | + clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); | ||
364 | + npcm7xx_clk_update_all_plls(clk); | ||
365 | + npcm7xx_clk_update_all_sels(clk); | ||
366 | + npcm7xx_clk_update_all_dividers(clk); | ||
367 | +} | ||
368 | + | ||
369 | +/* Types of clock sources. */ | ||
370 | +typedef enum ClockSrcType { | ||
371 | + CLKSRC_REF, | ||
372 | + CLKSRC_PLL, | ||
373 | + CLKSRC_SEL, | ||
374 | + CLKSRC_DIV, | ||
375 | +} ClockSrcType; | ||
376 | + | ||
377 | +typedef struct PLLInitInfo { | ||
378 | + const char *name; | ||
379 | + ClockSrcType src_type; | ||
380 | + int src_index; | ||
381 | + int reg; | ||
382 | + const char *public_name; | ||
383 | +} PLLInitInfo; | ||
384 | + | ||
385 | +typedef struct SELInitInfo { | ||
386 | + const char *name; | ||
387 | + uint8_t input_size; | ||
388 | + ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
389 | + int src_index[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
390 | + int offset; | ||
391 | + int len; | ||
392 | + const char *public_name; | ||
393 | +} SELInitInfo; | ||
394 | + | ||
395 | +typedef struct DividerInitInfo { | ||
396 | + const char *name; | ||
397 | + ClockSrcType src_type; | ||
398 | + int src_index; | ||
399 | + uint32_t (*divide)(NPCM7xxClockDividerState *s); | ||
400 | + int reg; /* not used when type == CONSTANT */ | ||
401 | + int offset; /* not used when type == CONSTANT */ | ||
402 | + int len; /* not used when type == CONSTANT */ | ||
403 | + int divisor; /* used only when type == CONSTANT */ | ||
404 | + const char *public_name; | ||
405 | +} DividerInitInfo; | ||
406 | + | ||
407 | +static const PLLInitInfo pll_init_info_list[] = { | ||
408 | + [NPCM7XX_CLOCK_PLL0] = { | ||
409 | + .name = "pll0", | ||
410 | + .src_type = CLKSRC_REF, | ||
411 | + .reg = NPCM7XX_CLK_PLLCON0, | ||
412 | + }, | ||
413 | + [NPCM7XX_CLOCK_PLL1] = { | ||
414 | + .name = "pll1", | ||
415 | + .src_type = CLKSRC_REF, | ||
416 | + .reg = NPCM7XX_CLK_PLLCON1, | ||
417 | + }, | ||
418 | + [NPCM7XX_CLOCK_PLL2] = { | ||
419 | + .name = "pll2", | ||
420 | + .src_type = CLKSRC_REF, | ||
421 | + .reg = NPCM7XX_CLK_PLLCON2, | ||
422 | + }, | ||
423 | + [NPCM7XX_CLOCK_PLLG] = { | ||
424 | + .name = "pllg", | ||
425 | + .src_type = CLKSRC_REF, | ||
426 | + .reg = NPCM7XX_CLK_PLLCONG, | ||
427 | + }, | ||
428 | +}; | ||
429 | + | ||
430 | +static const SELInitInfo sel_init_info_list[] = { | ||
431 | + [NPCM7XX_CLOCK_PIXCKSEL] = { | ||
432 | + .name = "pixcksel", | ||
433 | + .input_size = 2, | ||
434 | + .src_type = {CLKSRC_PLL, CLKSRC_REF}, | ||
435 | + .src_index = {NPCM7XX_CLOCK_PLLG, 0}, | ||
436 | + .offset = 5, | ||
437 | + .len = 1, | ||
438 | + .public_name = "pixel-clock", | ||
439 | + }, | ||
440 | + [NPCM7XX_CLOCK_MCCKSEL] = { | ||
441 | + .name = "mccksel", | ||
442 | + .input_size = 4, | ||
443 | + .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF, | ||
444 | + /*MCBPCK, shouldn't be used in normal operation*/ | ||
445 | + CLKSRC_REF}, | ||
446 | + .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0}, | ||
447 | + .offset = 12, | ||
448 | + .len = 2, | ||
449 | + .public_name = "mc-phy-clock", | ||
450 | + }, | ||
451 | + [NPCM7XX_CLOCK_CPUCKSEL] = { | ||
452 | + .name = "cpucksel", | ||
453 | + .input_size = 4, | ||
454 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, | ||
455 | + /*SYSBPCK, shouldn't be used in normal operation*/ | ||
456 | + CLKSRC_REF}, | ||
457 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0}, | ||
458 | + .offset = 0, | ||
459 | + .len = 2, | ||
460 | + .public_name = "system-clock", | ||
461 | + }, | ||
462 | + [NPCM7XX_CLOCK_CLKOUTSEL] = { | ||
463 | + .name = "clkoutsel", | ||
464 | + .input_size = 5, | ||
465 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, | ||
466 | + CLKSRC_PLL, CLKSRC_DIV}, | ||
467 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
468 | + NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2}, | ||
469 | + .offset = 18, | ||
470 | + .len = 3, | ||
471 | + .public_name = "tock", | ||
472 | + }, | ||
473 | + [NPCM7XX_CLOCK_UARTCKSEL] = { | ||
474 | + .name = "uartcksel", | ||
475 | + .input_size = 4, | ||
476 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
477 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
478 | + NPCM7XX_CLOCK_PLL2D2}, | ||
479 | + .offset = 8, | ||
480 | + .len = 2, | ||
481 | + }, | ||
482 | + [NPCM7XX_CLOCK_TIMCKSEL] = { | ||
483 | + .name = "timcksel", | ||
484 | + .input_size = 4, | ||
485 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
486 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
487 | + NPCM7XX_CLOCK_PLL2D2}, | ||
488 | + .offset = 14, | ||
489 | + .len = 2, | ||
490 | + }, | ||
491 | + [NPCM7XX_CLOCK_SDCKSEL] = { | ||
492 | + .name = "sdcksel", | ||
493 | + .input_size = 4, | ||
494 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
495 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
496 | + NPCM7XX_CLOCK_PLL2D2}, | ||
497 | + .offset = 6, | ||
498 | + .len = 2, | ||
499 | + }, | ||
500 | + [NPCM7XX_CLOCK_GFXMSEL] = { | ||
501 | + .name = "gfxmksel", | ||
502 | + .input_size = 2, | ||
503 | + .src_type = {CLKSRC_REF, CLKSRC_PLL}, | ||
504 | + .src_index = {0, NPCM7XX_CLOCK_PLL2}, | ||
505 | + .offset = 21, | ||
506 | + .len = 1, | ||
507 | + }, | ||
508 | + [NPCM7XX_CLOCK_SUCKSEL] = { | ||
509 | + .name = "sucksel", | ||
510 | + .input_size = 4, | ||
511 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
512 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
513 | + NPCM7XX_CLOCK_PLL2D2}, | ||
514 | + .offset = 10, | ||
515 | + .len = 2, | ||
516 | + }, | ||
517 | +}; | ||
518 | + | ||
519 | +static const DividerInitInfo divider_init_info_list[] = { | ||
520 | + [NPCM7XX_CLOCK_PLL1D2] = { | ||
521 | + .name = "pll1d2", | ||
522 | + .src_type = CLKSRC_PLL, | ||
523 | + .src_index = NPCM7XX_CLOCK_PLL1, | ||
524 | + .divide = divide_by_constant, | ||
525 | + .divisor = 2, | ||
526 | + }, | ||
527 | + [NPCM7XX_CLOCK_PLL2D2] = { | ||
528 | + .name = "pll2d2", | ||
529 | + .src_type = CLKSRC_PLL, | ||
530 | + .src_index = NPCM7XX_CLOCK_PLL2, | ||
531 | + .divide = divide_by_constant, | ||
532 | + .divisor = 2, | ||
533 | + }, | ||
534 | + [NPCM7XX_CLOCK_MC_DIVIDER] = { | ||
535 | + .name = "mc-divider", | ||
536 | + .src_type = CLKSRC_SEL, | ||
537 | + .src_index = NPCM7XX_CLOCK_MCCKSEL, | ||
538 | + .divide = divide_by_constant, | ||
539 | + .divisor = 2, | ||
540 | + .public_name = "mc-clock" | ||
541 | + }, | ||
542 | + [NPCM7XX_CLOCK_AXI_DIVIDER] = { | ||
543 | + .name = "axi-divider", | ||
544 | + .src_type = CLKSRC_SEL, | ||
545 | + .src_index = NPCM7XX_CLOCK_CPUCKSEL, | ||
546 | + .divide = shift_by_reg_divisor, | ||
547 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
548 | + .offset = 0, | ||
549 | + .len = 1, | ||
550 | + .public_name = "clk2" | ||
551 | + }, | ||
552 | + [NPCM7XX_CLOCK_AHB_DIVIDER] = { | ||
553 | + .name = "ahb-divider", | ||
554 | + .src_type = CLKSRC_DIV, | ||
555 | + .src_index = NPCM7XX_CLOCK_AXI_DIVIDER, | ||
556 | + .divide = divide_by_reg_divisor, | ||
557 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
558 | + .offset = 26, | ||
559 | + .len = 2, | ||
560 | + .public_name = "clk4" | ||
561 | + }, | ||
562 | + [NPCM7XX_CLOCK_AHB3_DIVIDER] = { | ||
563 | + .name = "ahb3-divider", | ||
564 | + .src_type = CLKSRC_DIV, | ||
565 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
566 | + .divide = divide_by_reg_divisor, | ||
567 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
568 | + .offset = 6, | ||
569 | + .len = 5, | ||
570 | + .public_name = "ahb3-spi3-clock" | ||
571 | + }, | ||
572 | + [NPCM7XX_CLOCK_SPI0_DIVIDER] = { | ||
573 | + .name = "spi0-divider", | ||
574 | + .src_type = CLKSRC_DIV, | ||
575 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
576 | + .divide = divide_by_reg_divisor, | ||
577 | + .reg = NPCM7XX_CLK_CLKDIV3, | ||
578 | + .offset = 6, | ||
579 | + .len = 5, | ||
580 | + .public_name = "spi0-clock", | ||
581 | + }, | ||
582 | + [NPCM7XX_CLOCK_SPIX_DIVIDER] = { | ||
583 | + .name = "spix-divider", | ||
584 | + .src_type = CLKSRC_DIV, | ||
585 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
586 | + .divide = divide_by_reg_divisor, | ||
587 | + .reg = NPCM7XX_CLK_CLKDIV3, | ||
588 | + .offset = 1, | ||
589 | + .len = 5, | ||
590 | + .public_name = "spix-clock", | ||
591 | + }, | ||
592 | + [NPCM7XX_CLOCK_APB1_DIVIDER] = { | ||
593 | + .name = "apb1-divider", | ||
594 | + .src_type = CLKSRC_DIV, | ||
595 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
596 | + .divide = shift_by_reg_divisor, | ||
597 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
598 | + .offset = 24, | ||
599 | + .len = 2, | ||
600 | + .public_name = "apb1-clock", | ||
601 | + }, | ||
602 | + [NPCM7XX_CLOCK_APB2_DIVIDER] = { | ||
603 | + .name = "apb2-divider", | ||
604 | + .src_type = CLKSRC_DIV, | ||
605 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
606 | + .divide = shift_by_reg_divisor, | ||
607 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
608 | + .offset = 26, | ||
609 | + .len = 2, | ||
610 | + .public_name = "apb2-clock", | ||
611 | + }, | ||
612 | + [NPCM7XX_CLOCK_APB3_DIVIDER] = { | ||
613 | + .name = "apb3-divider", | ||
614 | + .src_type = CLKSRC_DIV, | ||
615 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
616 | + .divide = shift_by_reg_divisor, | ||
617 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
618 | + .offset = 28, | ||
619 | + .len = 2, | ||
620 | + .public_name = "apb3-clock", | ||
621 | + }, | ||
622 | + [NPCM7XX_CLOCK_APB4_DIVIDER] = { | ||
623 | + .name = "apb4-divider", | ||
624 | + .src_type = CLKSRC_DIV, | ||
625 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
626 | + .divide = shift_by_reg_divisor, | ||
627 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
628 | + .offset = 30, | ||
629 | + .len = 2, | ||
630 | + .public_name = "apb4-clock", | ||
631 | + }, | ||
632 | + [NPCM7XX_CLOCK_APB5_DIVIDER] = { | ||
633 | + .name = "apb5-divider", | ||
634 | + .src_type = CLKSRC_DIV, | ||
635 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
636 | + .divide = shift_by_reg_divisor, | ||
637 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
638 | + .offset = 22, | ||
639 | + .len = 2, | ||
640 | + .public_name = "apb5-clock", | ||
641 | + }, | ||
642 | + [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = { | ||
643 | + .name = "clkout-divider", | ||
644 | + .src_type = CLKSRC_SEL, | ||
645 | + .src_index = NPCM7XX_CLOCK_CLKOUTSEL, | ||
646 | + .divide = divide_by_reg_divisor, | ||
647 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
648 | + .offset = 16, | ||
649 | + .len = 5, | ||
650 | + .public_name = "clkout", | ||
651 | + }, | ||
652 | + [NPCM7XX_CLOCK_UART_DIVIDER] = { | ||
653 | + .name = "uart-divider", | ||
654 | + .src_type = CLKSRC_SEL, | ||
655 | + .src_index = NPCM7XX_CLOCK_UARTCKSEL, | ||
656 | + .divide = divide_by_reg_divisor, | ||
657 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
658 | + .offset = 16, | ||
659 | + .len = 5, | ||
660 | + .public_name = "uart-clock", | ||
661 | + }, | ||
662 | + [NPCM7XX_CLOCK_TIMER_DIVIDER] = { | ||
663 | + .name = "timer-divider", | ||
664 | + .src_type = CLKSRC_SEL, | ||
665 | + .src_index = NPCM7XX_CLOCK_TIMCKSEL, | ||
666 | + .divide = divide_by_reg_divisor, | ||
667 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
668 | + .offset = 21, | ||
669 | + .len = 5, | ||
670 | + .public_name = "timer-clock", | ||
671 | + }, | ||
672 | + [NPCM7XX_CLOCK_ADC_DIVIDER] = { | ||
673 | + .name = "adc-divider", | ||
674 | + .src_type = CLKSRC_DIV, | ||
675 | + .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER, | ||
676 | + .divide = shift_by_reg_divisor, | ||
677 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
678 | + .offset = 28, | ||
679 | + .len = 3, | ||
680 | + .public_name = "adc-clock", | ||
681 | + }, | ||
682 | + [NPCM7XX_CLOCK_MMC_DIVIDER] = { | ||
683 | + .name = "mmc-divider", | ||
684 | + .src_type = CLKSRC_SEL, | ||
685 | + .src_index = NPCM7XX_CLOCK_SDCKSEL, | ||
686 | + .divide = divide_by_reg_divisor, | ||
687 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
688 | + .offset = 11, | ||
689 | + .len = 5, | ||
690 | + .public_name = "mmc-clock", | ||
691 | + }, | ||
692 | + [NPCM7XX_CLOCK_SDHC_DIVIDER] = { | ||
693 | + .name = "sdhc-divider", | ||
694 | + .src_type = CLKSRC_SEL, | ||
695 | + .src_index = NPCM7XX_CLOCK_SDCKSEL, | ||
696 | + .divide = divide_by_reg_divisor_times_2, | ||
697 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
698 | + .offset = 0, | ||
699 | + .len = 4, | ||
700 | + .public_name = "sdhc-clock", | ||
701 | + }, | ||
702 | + [NPCM7XX_CLOCK_GFXM_DIVIDER] = { | ||
703 | + .name = "gfxm-divider", | ||
704 | + .src_type = CLKSRC_SEL, | ||
705 | + .src_index = NPCM7XX_CLOCK_GFXMSEL, | ||
706 | + .divide = divide_by_constant, | ||
707 | + .divisor = 3, | ||
708 | + .public_name = "gfxm-clock", | ||
709 | + }, | ||
710 | + [NPCM7XX_CLOCK_UTMI_DIVIDER] = { | ||
711 | + .name = "utmi-divider", | ||
712 | + .src_type = CLKSRC_SEL, | ||
713 | + .src_index = NPCM7XX_CLOCK_SUCKSEL, | ||
714 | + .divide = divide_by_reg_divisor, | ||
715 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
716 | + .offset = 8, | ||
717 | + .len = 5, | ||
718 | + .public_name = "utmi-clock", | ||
719 | + }, | ||
720 | +}; | ||
721 | + | ||
722 | +static void npcm7xx_clk_pll_init(Object *obj) | ||
723 | +{ | ||
724 | + NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj); | ||
725 | + | ||
726 | + pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", | ||
727 | + npcm7xx_clk_update_pll, pll); | ||
728 | + pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); | ||
729 | +} | ||
730 | + | ||
731 | +static void npcm7xx_clk_sel_init(Object *obj) | ||
732 | +{ | ||
733 | + int i; | ||
734 | + NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); | ||
735 | + | ||
736 | + for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { | ||
737 | + sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), | ||
738 | + g_strdup_printf("clock-in[%d]", i), | ||
739 | + npcm7xx_clk_update_sel, sel); | ||
740 | + } | ||
741 | + sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); | ||
742 | +} | ||
743 | +static void npcm7xx_clk_divider_init(Object *obj) | ||
744 | +{ | ||
745 | + NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj); | ||
746 | + | ||
747 | + div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in", | ||
748 | + npcm7xx_clk_update_divider, div); | ||
749 | + div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out"); | ||
750 | +} | ||
751 | + | ||
752 | +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, | ||
753 | + NPCM7xxCLKState *clk, const PLLInitInfo *init_info) | ||
754 | +{ | ||
755 | + pll->name = init_info->name; | ||
756 | + pll->clk = clk; | ||
757 | + pll->reg = init_info->reg; | ||
758 | + if (init_info->public_name != NULL) { | ||
759 | + qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), | ||
760 | + init_info->public_name); | ||
761 | + } | ||
762 | +} | ||
763 | + | ||
764 | +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, | ||
765 | + NPCM7xxCLKState *clk, const SELInitInfo *init_info) | ||
766 | +{ | ||
767 | + int input_size = init_info->input_size; | ||
768 | + | ||
769 | + sel->name = init_info->name; | ||
770 | + sel->clk = clk; | ||
771 | + sel->input_size = init_info->input_size; | ||
772 | + g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT); | ||
773 | + sel->offset = init_info->offset; | ||
774 | + sel->len = init_info->len; | ||
775 | + if (init_info->public_name != NULL) { | ||
776 | + qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), | ||
777 | + init_info->public_name); | ||
778 | + } | ||
779 | +} | ||
780 | + | ||
781 | +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, | ||
782 | + NPCM7xxCLKState *clk, const DividerInitInfo *init_info) | ||
783 | +{ | ||
784 | + div->name = init_info->name; | ||
785 | + div->clk = clk; | ||
786 | + | ||
787 | + div->divide = init_info->divide; | ||
788 | + if (div->divide == divide_by_constant) { | ||
789 | + div->divisor = init_info->divisor; | ||
790 | + } else { | ||
791 | + div->reg = init_info->reg; | ||
792 | + div->offset = init_info->offset; | ||
793 | + div->len = init_info->len; | ||
794 | + } | ||
795 | + if (init_info->public_name != NULL) { | ||
796 | + qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), | ||
797 | + init_info->public_name); | ||
798 | + } | ||
799 | +} | ||
800 | + | ||
801 | +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, | ||
802 | + int index) | ||
803 | +{ | ||
804 | + switch (type) { | ||
805 | + case CLKSRC_REF: | ||
806 | + return clk->clkref; | ||
807 | + case CLKSRC_PLL: | ||
808 | + return clk->plls[index].clock_out; | ||
809 | + case CLKSRC_SEL: | ||
810 | + return clk->sels[index].clock_out; | ||
811 | + case CLKSRC_DIV: | ||
812 | + return clk->dividers[index].clock_out; | ||
813 | + default: | ||
814 | + g_assert_not_reached(); | ||
815 | + } | ||
816 | +} | ||
817 | + | ||
818 | +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) | ||
819 | +{ | ||
820 | + int i, j; | ||
821 | + Clock *src; | ||
822 | + | ||
823 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
824 | + src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type, | ||
825 | + pll_init_info_list[i].src_index); | ||
826 | + clock_set_source(clk->plls[i].clock_in, src); | ||
827 | + } | ||
828 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
829 | + for (j = 0; j < sel_init_info_list[i].input_size; ++j) { | ||
830 | + src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j], | ||
831 | + sel_init_info_list[i].src_index[j]); | ||
832 | + clock_set_source(clk->sels[i].clock_in[j], src); | ||
833 | + } | ||
834 | + } | ||
835 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
836 | + src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type, | ||
837 | + divider_init_info_list[i].src_index); | ||
838 | + clock_set_source(clk->dividers[i].clock_in, src); | ||
839 | + } | ||
840 | +} | ||
841 | + | ||
842 | static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) | ||
843 | { | ||
844 | uint32_t reg = offset / sizeof(uint32_t); | ||
845 | @@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) | ||
846 | * | ||
847 | * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000. | ||
848 | */ | ||
849 | - value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ; | ||
850 | + value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ; | ||
851 | break; | ||
852 | |||
853 | default: | ||
854 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset, | ||
855 | value |= (value & PLLCON_LOKS); | ||
856 | } | ||
857 | } | ||
858 | + /* Only update PLL when it is locked. */ | ||
859 | + if (value & PLLCON_LOKI) { | ||
860 | + npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); | ||
861 | + } | ||
862 | + break; | ||
863 | + | ||
864 | + case NPCM7XX_CLK_CLKSEL: | ||
865 | + npcm7xx_clk_update_all_sels(s); | ||
866 | + break; | ||
867 | + | ||
868 | + case NPCM7XX_CLK_CLKDIV1: | ||
869 | + case NPCM7XX_CLK_CLKDIV2: | ||
870 | + case NPCM7XX_CLK_CLKDIV3: | ||
871 | + npcm7xx_clk_update_all_dividers(s); | ||
872 | break; | ||
873 | |||
874 | case NPCM7XX_CLK_CNTR25M: | ||
875 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) | ||
876 | case RESET_TYPE_COLD: | ||
877 | memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); | ||
878 | s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
879 | + npcm7xx_clk_update_all_clocks(s); | ||
880 | return; | ||
881 | } | ||
882 | |||
883 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) | ||
884 | __func__, type); | ||
885 | } | ||
886 | |||
887 | +static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) | ||
888 | +{ | ||
889 | + int i; | ||
890 | + | ||
891 | + s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); | ||
892 | + | ||
893 | + /* First pass: init all converter modules */ | ||
894 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS); | ||
895 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS); | ||
896 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list) | ||
897 | + != NPCM7XX_CLOCK_NR_DIVIDERS); | ||
898 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
899 | + object_initialize_child(OBJECT(s), pll_init_info_list[i].name, | ||
900 | + &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); | ||
901 | + npcm7xx_init_clock_pll(&s->plls[i], s, | ||
902 | + &pll_init_info_list[i]); | ||
903 | + } | ||
904 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
905 | + object_initialize_child(OBJECT(s), sel_init_info_list[i].name, | ||
906 | + &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); | ||
907 | + npcm7xx_init_clock_sel(&s->sels[i], s, | ||
908 | + &sel_init_info_list[i]); | ||
909 | + } | ||
910 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
911 | + object_initialize_child(OBJECT(s), divider_init_info_list[i].name, | ||
912 | + &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); | ||
913 | + npcm7xx_init_clock_divider(&s->dividers[i], s, | ||
914 | + ÷r_init_info_list[i]); | ||
915 | + } | ||
916 | + | ||
917 | + /* Second pass: connect converter modules */ | ||
918 | + npcm7xx_connect_clocks(s); | ||
919 | + | ||
920 | + clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); | ||
921 | +} | ||
922 | + | ||
923 | static void npcm7xx_clk_init(Object *obj) | ||
924 | { | ||
925 | NPCM7xxCLKState *s = NPCM7XX_CLK(obj); | ||
926 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj) | ||
927 | memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, | ||
928 | TYPE_NPCM7XX_CLK, 4 * KiB); | ||
929 | sysbus_init_mmio(&s->parent, &s->iomem); | ||
930 | - qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, | ||
931 | - NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); | ||
932 | } | ||
933 | |||
934 | -static const VMStateDescription vmstate_npcm7xx_clk = { | ||
935 | - .name = "npcm7xx-clk", | ||
936 | +static int npcm7xx_clk_post_load(void *opaque, int version_id) | ||
937 | +{ | ||
938 | + if (version_id >= 1) { | ||
939 | + NPCM7xxCLKState *clk = opaque; | ||
940 | + | ||
941 | + npcm7xx_clk_update_all_clocks(clk); | ||
942 | + } | ||
943 | + | ||
944 | + return 0; | ||
945 | +} | ||
946 | + | ||
947 | +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) | ||
948 | +{ | ||
949 | + int i; | ||
950 | + NPCM7xxCLKState *s = NPCM7XX_CLK(dev); | ||
951 | + | ||
952 | + qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, | ||
953 | + NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); | ||
954 | + npcm7xx_clk_init_clock_hierarchy(s); | ||
955 | + | ||
956 | + /* Realize child devices */ | ||
957 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
958 | + if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { | ||
959 | + return; | ||
960 | + } | ||
961 | + } | ||
962 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
963 | + if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { | ||
964 | + return; | ||
965 | + } | ||
966 | + } | ||
967 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
968 | + if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { | ||
969 | + return; | ||
970 | + } | ||
971 | + } | ||
972 | +} | ||
973 | + | ||
974 | +static const VMStateDescription vmstate_npcm7xx_clk_pll = { | ||
975 | + .name = "npcm7xx-clock-pll", | ||
976 | .version_id = 0, | ||
977 | .minimum_version_id = 0, | ||
978 | - .fields = (VMStateField[]) { | ||
979 | - VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), | ||
980 | - VMSTATE_INT64(ref_ns, NPCM7xxCLKState), | ||
981 | + .fields = (VMStateField[]) { | ||
982 | + VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState), | ||
983 | VMSTATE_END_OF_LIST(), | ||
984 | }, | ||
985 | }; | ||
986 | |||
987 | +static const VMStateDescription vmstate_npcm7xx_clk_sel = { | ||
988 | + .name = "npcm7xx-clock-sel", | ||
989 | + .version_id = 0, | ||
990 | + .minimum_version_id = 0, | ||
991 | + .fields = (VMStateField[]) { | ||
992 | + VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState, | ||
993 | + NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock), | ||
994 | + VMSTATE_END_OF_LIST(), | ||
995 | + }, | ||
996 | +}; | ||
997 | + | ||
998 | +static const VMStateDescription vmstate_npcm7xx_clk_divider = { | ||
999 | + .name = "npcm7xx-clock-divider", | ||
1000 | + .version_id = 0, | ||
1001 | + .minimum_version_id = 0, | ||
1002 | + .fields = (VMStateField[]) { | ||
1003 | + VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState), | ||
1004 | + VMSTATE_END_OF_LIST(), | ||
1005 | + }, | ||
1006 | +}; | ||
1007 | + | ||
1008 | +static const VMStateDescription vmstate_npcm7xx_clk = { | ||
1009 | + .name = "npcm7xx-clk", | ||
1010 | + .version_id = 1, | ||
1011 | + .minimum_version_id = 1, | ||
1012 | + .post_load = npcm7xx_clk_post_load, | ||
1013 | + .fields = (VMStateField[]) { | ||
1014 | + VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), | ||
1015 | + VMSTATE_INT64(ref_ns, NPCM7xxCLKState), | ||
1016 | + VMSTATE_CLOCK(clkref, NPCM7xxCLKState), | ||
1017 | + VMSTATE_END_OF_LIST(), | ||
1018 | + }, | ||
1019 | +}; | ||
1020 | + | ||
1021 | +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) | ||
1022 | +{ | ||
1023 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1024 | + | ||
1025 | + dc->desc = "NPCM7xx Clock PLL Module"; | ||
1026 | + dc->vmsd = &vmstate_npcm7xx_clk_pll; | ||
1027 | +} | ||
1028 | + | ||
1029 | +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) | ||
1030 | +{ | ||
1031 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1032 | + | ||
1033 | + dc->desc = "NPCM7xx Clock SEL Module"; | ||
1034 | + dc->vmsd = &vmstate_npcm7xx_clk_sel; | ||
1035 | +} | ||
1036 | + | ||
1037 | +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) | ||
1038 | +{ | ||
1039 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1040 | + | ||
1041 | + dc->desc = "NPCM7xx Clock Divider Module"; | ||
1042 | + dc->vmsd = &vmstate_npcm7xx_clk_divider; | ||
1043 | +} | ||
1044 | + | ||
1045 | static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) | ||
1046 | { | ||
1047 | ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
1048 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) | ||
1049 | |||
1050 | dc->desc = "NPCM7xx Clock Control Registers"; | ||
1051 | dc->vmsd = &vmstate_npcm7xx_clk; | ||
1052 | + dc->realize = npcm7xx_clk_realize; | ||
1053 | rc->phases.enter = npcm7xx_clk_enter_reset; | ||
1054 | } | ||
1055 | |||
1056 | +static const TypeInfo npcm7xx_clk_pll_info = { | ||
1057 | + .name = TYPE_NPCM7XX_CLOCK_PLL, | ||
1058 | + .parent = TYPE_DEVICE, | ||
1059 | + .instance_size = sizeof(NPCM7xxClockPLLState), | ||
1060 | + .instance_init = npcm7xx_clk_pll_init, | ||
1061 | + .class_init = npcm7xx_clk_pll_class_init, | ||
1062 | +}; | ||
1063 | + | ||
1064 | +static const TypeInfo npcm7xx_clk_sel_info = { | ||
1065 | + .name = TYPE_NPCM7XX_CLOCK_SEL, | ||
1066 | + .parent = TYPE_DEVICE, | ||
1067 | + .instance_size = sizeof(NPCM7xxClockSELState), | ||
1068 | + .instance_init = npcm7xx_clk_sel_init, | ||
1069 | + .class_init = npcm7xx_clk_sel_class_init, | ||
1070 | +}; | ||
1071 | + | ||
1072 | +static const TypeInfo npcm7xx_clk_divider_info = { | ||
1073 | + .name = TYPE_NPCM7XX_CLOCK_DIVIDER, | ||
1074 | + .parent = TYPE_DEVICE, | ||
1075 | + .instance_size = sizeof(NPCM7xxClockDividerState), | ||
1076 | + .instance_init = npcm7xx_clk_divider_init, | ||
1077 | + .class_init = npcm7xx_clk_divider_class_init, | ||
1078 | +}; | ||
1079 | + | ||
1080 | static const TypeInfo npcm7xx_clk_info = { | ||
1081 | .name = TYPE_NPCM7XX_CLK, | ||
1082 | .parent = TYPE_SYS_BUS_DEVICE, | ||
1083 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = { | ||
1084 | |||
1085 | static void npcm7xx_clk_register_type(void) | ||
1086 | { | ||
1087 | + type_register_static(&npcm7xx_clk_pll_info); | ||
1088 | + type_register_static(&npcm7xx_clk_sel_info); | ||
1089 | + type_register_static(&npcm7xx_clk_divider_info); | ||
1090 | type_register_static(&npcm7xx_clk_info); | ||
1091 | } | ||
1092 | type_init(npcm7xx_clk_register_type); | ||
1093 | -- | ||
1094 | 2.20.1 | ||
1095 | |||
1096 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
1 | 2 | ||
3 | This patch makes NPCM7XX Timer to use a the timer clock generated by the | ||
4 | CLK module instead of the magic number TIMER_REF_HZ. | ||
5 | |||
6 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
7 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
8 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
9 | Message-id: 20210108190945.949196-3-wuhaotsh@google.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/npcm7xx_clk.h | 6 ----- | ||
14 | include/hw/timer/npcm7xx_timer.h | 1 + | ||
15 | hw/arm/npcm7xx.c | 5 ++++ | ||
16 | hw/timer/npcm7xx_timer.c | 39 +++++++++++++++----------------- | ||
17 | 4 files changed, 24 insertions(+), 27 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/misc/npcm7xx_clk.h | ||
22 | +++ b/include/hw/misc/npcm7xx_clk.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | #include "hw/clock.h" | ||
25 | #include "hw/sysbus.h" | ||
26 | |||
27 | -/* | ||
28 | - * The reference clock frequency for the timer modules, and the SECCNT and | ||
29 | - * CNTR25M registers in this module, is always 25 MHz. | ||
30 | - */ | ||
31 | -#define NPCM7XX_TIMER_REF_HZ (25000000) | ||
32 | - | ||
33 | /* | ||
34 | * Number of registers in our device state structure. Don't change this without | ||
35 | * incrementing the version_id in the vmstate. | ||
36 | diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/include/hw/timer/npcm7xx_timer.h | ||
39 | +++ b/include/hw/timer/npcm7xx_timer.h | ||
40 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState { | ||
41 | |||
42 | uint32_t tisr; | ||
43 | |||
44 | + Clock *clock; | ||
45 | NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; | ||
46 | NPCM7xxWatchdogTimer watchdog_timer; | ||
47 | }; | ||
48 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/npcm7xx.c | ||
51 | +++ b/hw/arm/npcm7xx.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | #include "hw/char/serial.h" | ||
54 | #include "hw/loader.h" | ||
55 | #include "hw/misc/unimp.h" | ||
56 | +#include "hw/qdev-clock.h" | ||
57 | #include "hw/qdev-properties.h" | ||
58 | #include "qapi/error.h" | ||
59 | #include "qemu/units.h" | ||
60 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
61 | int first_irq; | ||
62 | int j; | ||
63 | |||
64 | + /* Connect the timer clock. */ | ||
65 | + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( | ||
66 | + DEVICE(&s->clk), "timer-clock")); | ||
67 | + | ||
68 | sysbus_realize(sbd, &error_abort); | ||
69 | sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); | ||
70 | |||
71 | diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/hw/timer/npcm7xx_timer.c | ||
74 | +++ b/hw/timer/npcm7xx_timer.c | ||
75 | @@ -XXX,XX +XXX,XX @@ | ||
76 | #include "qemu/osdep.h" | ||
77 | |||
78 | #include "hw/irq.h" | ||
79 | +#include "hw/qdev-clock.h" | ||
80 | #include "hw/qdev-properties.h" | ||
81 | -#include "hw/misc/npcm7xx_clk.h" | ||
82 | #include "hw/timer/npcm7xx_timer.h" | ||
83 | #include "migration/vmstate.h" | ||
84 | #include "qemu/bitops.h" | ||
85 | @@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) | ||
86 | /* Convert a timer cycle count to a time interval in nanoseconds. */ | ||
87 | static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) | ||
88 | { | ||
89 | - int64_t ns = count; | ||
90 | + int64_t ticks = count; | ||
91 | |||
92 | - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; | ||
93 | - ns *= npcm7xx_tcsr_prescaler(t->tcsr); | ||
94 | + ticks *= npcm7xx_tcsr_prescaler(t->tcsr); | ||
95 | |||
96 | - return ns; | ||
97 | + return clock_ticks_to_ns(t->ctrl->clock, ticks); | ||
98 | } | ||
99 | |||
100 | /* Convert a time interval in nanoseconds to a timer cycle count. */ | ||
101 | static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) | ||
102 | { | ||
103 | - int64_t count; | ||
104 | - | ||
105 | - count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); | ||
106 | - count /= npcm7xx_tcsr_prescaler(t->tcsr); | ||
107 | - | ||
108 | - return count; | ||
109 | + return ns / clock_ticks_to_ns(t->ctrl->clock, | ||
110 | + npcm7xx_tcsr_prescaler(t->tcsr)); | ||
111 | } | ||
112 | |||
113 | static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) | ||
114 | @@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) | ||
115 | static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, | ||
116 | int64_t cycles) | ||
117 | { | ||
118 | - uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t); | ||
119 | - int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles; | ||
120 | + int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); | ||
121 | + int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks); | ||
122 | |||
123 | /* | ||
124 | * The reset function always clears the current timer. The caller of the | ||
125 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, | ||
126 | */ | ||
127 | npcm7xx_timer_clear(&t->base_timer); | ||
128 | |||
129 | - ns *= prescaler; | ||
130 | t->base_timer.remaining_ns = ns; | ||
131 | } | ||
132 | |||
133 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj) | ||
134 | qemu_irq_lower(s->watchdog_timer.irq); | ||
135 | } | ||
136 | |||
137 | -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) | ||
138 | +static void npcm7xx_timer_init(Object *obj) | ||
139 | { | ||
140 | - NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev); | ||
141 | - SysBusDevice *sbd = &s->parent; | ||
142 | + NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); | ||
143 | + DeviceState *dev = DEVICE(obj); | ||
144 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
145 | int i; | ||
146 | NPCM7xxWatchdogTimer *w; | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) | ||
149 | npcm7xx_watchdog_timer_expired, w); | ||
150 | sysbus_init_irq(sbd, &w->irq); | ||
151 | |||
152 | - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, | ||
153 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, | ||
154 | TYPE_NPCM7XX_TIMER, 4 * KiB); | ||
155 | sysbus_init_mmio(sbd, &s->iomem); | ||
156 | qdev_init_gpio_out_named(dev, &w->reset_signal, | ||
157 | NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); | ||
158 | + s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL); | ||
159 | } | ||
160 | |||
161 | static const VMStateDescription vmstate_npcm7xx_base_timer = { | ||
162 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = { | ||
163 | |||
164 | static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { | ||
165 | .name = "npcm7xx-timer-ctrl", | ||
166 | - .version_id = 1, | ||
167 | - .minimum_version_id = 1, | ||
168 | + .version_id = 2, | ||
169 | + .minimum_version_id = 2, | ||
170 | .fields = (VMStateField[]) { | ||
171 | VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), | ||
172 | + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), | ||
173 | VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, | ||
174 | NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer, | ||
175 | NPCM7xxTimer), | ||
176 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data) | ||
177 | QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); | ||
178 | |||
179 | dc->desc = "NPCM7xx Timer Controller"; | ||
180 | - dc->realize = npcm7xx_timer_realize; | ||
181 | dc->vmsd = &vmstate_npcm7xx_timer_ctrl; | ||
182 | rc->phases.enter = npcm7xx_timer_enter_reset; | ||
183 | rc->phases.hold = npcm7xx_timer_hold_reset; | ||
184 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = { | ||
185 | .parent = TYPE_SYS_BUS_DEVICE, | ||
186 | .instance_size = sizeof(NPCM7xxTimerCtrlState), | ||
187 | .class_init = npcm7xx_timer_class_init, | ||
188 | + .instance_init = npcm7xx_timer_init, | ||
189 | }; | ||
190 | |||
191 | static void npcm7xx_timer_register_type(void) | ||
192 | -- | ||
193 | 2.20.1 | ||
194 | |||
195 | diff view generated by jsdifflib |
1 | The kernel-doc Sphinx plugin and associated script currently emit | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 'c:type' directives for "struct foo" documentation. | ||
3 | 2 | ||
4 | Sphinx 3.0 warns about this: | 3 | The ADC is part of NPCM7XX Module. Its behavior is controled by the |
5 | /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/exec/memory.h:3: WARNING: Type must be either just a name or a typedef-like declaration. | 4 | ADC_CON register. It converts one of the eight analog inputs into a |
6 | If just a name: | 5 | digital input and stores it in the ADC_DATA register when enabled. |
7 | Error in declarator or parameters | ||
8 | Invalid C declaration: Expected identifier in nested name, got keyword: struct [error at 6] | ||
9 | struct MemoryListener | ||
10 | ------^ | ||
11 | If typedef-like declaration: | ||
12 | Error in declarator or parameters | ||
13 | Invalid C declaration: Expected identifier in nested name. [error at 21] | ||
14 | struct MemoryListener | ||
15 | ---------------------^ | ||
16 | 6 | ||
17 | because it wants us to use the new-in-3.0 'c:struct' instead. | 7 | Users can alter input value by using qom-set QMP command. |
18 | 8 | ||
19 | Plumb the Sphinx version through to the kernel-doc script | 9 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> |
20 | and use it to select 'c:struct' for newer versions than 3.0. | 10 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> |
11 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
12 | Message-id: 20210108190945.949196-4-wuhaotsh@google.com | ||
13 | [PMM: Added missing hw/adc/trace.h file] | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | docs/system/arm/nuvoton.rst | 2 +- | ||
18 | meson.build | 1 + | ||
19 | hw/adc/trace.h | 1 + | ||
20 | include/hw/adc/npcm7xx_adc.h | 69 ++++++ | ||
21 | include/hw/arm/npcm7xx.h | 2 + | ||
22 | hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++ | ||
23 | hw/arm/npcm7xx.c | 24 ++- | ||
24 | tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++ | ||
25 | hw/adc/meson.build | 1 + | ||
26 | hw/adc/trace-events | 5 + | ||
27 | tests/qtest/meson.build | 3 +- | ||
28 | 11 files changed, 783 insertions(+), 3 deletions(-) | ||
29 | create mode 100644 hw/adc/trace.h | ||
30 | create mode 100644 include/hw/adc/npcm7xx_adc.h | ||
31 | create mode 100644 hw/adc/npcm7xx_adc.c | ||
32 | create mode 100644 tests/qtest/npcm7xx_adc-test.c | ||
33 | create mode 100644 hw/adc/trace-events | ||
21 | 34 | ||
22 | Fixes: LP:1872113 | 35 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
25 | --- | ||
26 | docs/sphinx/kerneldoc.py | 1 + | ||
27 | scripts/kernel-doc | 16 +++++++++++++++- | ||
28 | 2 files changed, 16 insertions(+), 1 deletion(-) | ||
29 | |||
30 | diff --git a/docs/sphinx/kerneldoc.py b/docs/sphinx/kerneldoc.py | ||
31 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/docs/sphinx/kerneldoc.py | 37 | --- a/docs/system/arm/nuvoton.rst |
33 | +++ b/docs/sphinx/kerneldoc.py | 38 | +++ b/docs/system/arm/nuvoton.rst |
34 | @@ -XXX,XX +XXX,XX @@ class KernelDocDirective(Directive): | 39 | @@ -XXX,XX +XXX,XX @@ Supported devices |
35 | env.note_dependency(os.path.abspath(f)) | 40 | * Random Number Generator (RNG) |
36 | cmd += ['-export-file', f] | 41 | * USB host (USBH) |
37 | 42 | * GPIO controller | |
38 | + cmd += ['-sphinx-version', sphinx.__version__] | 43 | + * Analog to Digital Converter (ADC) |
39 | cmd += [filename] | 44 | |
40 | 45 | Missing devices | |
41 | try: | 46 | --------------- |
42 | diff --git a/scripts/kernel-doc b/scripts/kernel-doc | 47 | @@ -XXX,XX +XXX,XX @@ Missing devices |
43 | index XXXXXXX..XXXXXXX 100755 | 48 | * USB device (USBD) |
44 | --- a/scripts/kernel-doc | 49 | * SMBus controller (SMBF) |
45 | +++ b/scripts/kernel-doc | 50 | * Peripheral SPI controller (PSPI) |
46 | @@ -XXX,XX +XXX,XX @@ Output selection (mutually exclusive): | 51 | - * Analog to Digital Converter (ADC) |
47 | DOC: sections. May be specified multiple times. | 52 | * SD/MMC host |
48 | 53 | * PECI interface | |
49 | Output selection modifiers: | 54 | * Pulse Width Modulation (PWM) |
50 | + -sphinx-version VER Generate rST syntax for the specified Sphinx version. | 55 | diff --git a/meson.build b/meson.build |
51 | + Only works with reStructuredTextFormat. | 56 | index XXXXXXX..XXXXXXX 100644 |
52 | -no-doc-sections Do not output DOC: sections. | 57 | --- a/meson.build |
53 | -enable-lineno Enable output of #define LINENO lines. Only works with | 58 | +++ b/meson.build |
54 | reStructuredText format. | 59 | @@ -XXX,XX +XXX,XX @@ if have_system |
55 | @@ -XXX,XX +XXX,XX @@ use constant { | 60 | 'chardev', |
56 | }; | 61 | 'hw/9pfs', |
57 | my $output_selection = OUTPUT_ALL; | 62 | 'hw/acpi', |
58 | my $show_not_found = 0; # No longer used | 63 | + 'hw/adc', |
59 | +my $sphinx_version = "0.0"; # if not specified, assume old | 64 | 'hw/alpha', |
60 | 65 | 'hw/arm', | |
61 | my @export_file_list; | 66 | 'hw/audio', |
62 | 67 | diff --git a/hw/adc/trace.h b/hw/adc/trace.h | |
63 | @@ -XXX,XX +XXX,XX @@ while ($ARGV[0] =~ m/^--?(.*)/) { | 68 | new file mode 100644 |
64 | $enable_lineno = 1; | 69 | index XXXXXXX..XXXXXXX |
65 | } elsif ($cmd eq 'show-not-found') { | 70 | --- /dev/null |
66 | $show_not_found = 1; # A no-op but don't fail | 71 | +++ b/hw/adc/trace.h |
67 | + } elsif ($cmd eq 'sphinx-version') { | 72 | @@ -0,0 +1 @@ |
68 | + $sphinx_version = shift @ARGV; | 73 | +#include "trace/trace-hw_adc.h" |
69 | } else { | 74 | diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h |
70 | # Unknown argument | 75 | new file mode 100644 |
71 | usage(); | 76 | index XXXXXXX..XXXXXXX |
72 | @@ -XXX,XX +XXX,XX @@ sub output_struct_rst(%) { | 77 | --- /dev/null |
73 | my $oldprefix = $lineprefix; | 78 | +++ b/include/hw/adc/npcm7xx_adc.h |
74 | my $name = $args{'type'} . " " . $args{'struct'}; | 79 | @@ -XXX,XX +XXX,XX @@ |
75 | 80 | +/* | |
76 | - print "\n\n.. c:type:: " . $name . "\n\n"; | 81 | + * Nuvoton NPCM7xx ADC Module |
77 | + # Sphinx 3.0 and up will emit warnings for "c:type:: struct Foo". | 82 | + * |
78 | + # It wants to see "c:struct:: Foo" (and will add the word 'struct' in | 83 | + * Copyright 2020 Google LLC |
79 | + # the rendered output). | 84 | + * |
80 | + if ((split(/\./, $sphinx_version))[0] >= 3) { | 85 | + * This program is free software; you can redistribute it and/or modify it |
81 | + my $sname = $name; | 86 | + * under the terms of the GNU General Public License as published by the |
82 | + $sname =~ s/^struct //; | 87 | + * Free Software Foundation; either version 2 of the License, or |
83 | + print "\n\n.. c:struct:: " . $sname . "\n\n"; | 88 | + * (at your option) any later version. |
84 | + } else { | 89 | + * |
85 | + print "\n\n.. c:type:: " . $name . "\n\n"; | 90 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
86 | + } | 91 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
87 | print_lineno($declaration_start_line); | 92 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
88 | $lineprefix = " "; | 93 | + * for more details. |
89 | output_highlight_rst($args{'purpose'}); | 94 | + */ |
95 | +#ifndef NPCM7XX_ADC_H | ||
96 | +#define NPCM7XX_ADC_H | ||
97 | + | ||
98 | +#include "hw/clock.h" | ||
99 | +#include "hw/irq.h" | ||
100 | +#include "hw/sysbus.h" | ||
101 | +#include "qemu/timer.h" | ||
102 | + | ||
103 | +#define NPCM7XX_ADC_NUM_INPUTS 8 | ||
104 | +/** | ||
105 | + * This value should not be changed unless write_adc_calibration function in | ||
106 | + * hw/arm/npcm7xx.c is also changed. | ||
107 | + */ | ||
108 | +#define NPCM7XX_ADC_NUM_CALIB 2 | ||
109 | + | ||
110 | +/** | ||
111 | + * struct NPCM7xxADCState - Analog to Digital Converter Module device state. | ||
112 | + * @parent: System bus device. | ||
113 | + * @iomem: Memory region through which registers are accessed. | ||
114 | + * @conv_timer: The timer counts down remaining cycles for the conversion. | ||
115 | + * @irq: GIC interrupt line to fire on expiration (if enabled). | ||
116 | + * @con: The Control Register. | ||
117 | + * @data: The Data Buffer. | ||
118 | + * @clock: The ADC Clock. | ||
119 | + * @adci: The input voltage in units of uV. 1uv = 1e-6V. | ||
120 | + * @vref: The external reference voltage. | ||
121 | + * @iref: The internal reference voltage, initialized at launch time. | ||
122 | + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC. | ||
123 | + */ | ||
124 | +typedef struct { | ||
125 | + SysBusDevice parent; | ||
126 | + | ||
127 | + MemoryRegion iomem; | ||
128 | + | ||
129 | + QEMUTimer conv_timer; | ||
130 | + | ||
131 | + qemu_irq irq; | ||
132 | + uint32_t con; | ||
133 | + uint32_t data; | ||
134 | + Clock *clock; | ||
135 | + | ||
136 | + /* Voltages are in unit of uV. 1V = 1000000uV. */ | ||
137 | + uint32_t adci[NPCM7XX_ADC_NUM_INPUTS]; | ||
138 | + uint32_t vref; | ||
139 | + uint32_t iref; | ||
140 | + | ||
141 | + uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB]; | ||
142 | +} NPCM7xxADCState; | ||
143 | + | ||
144 | +#define TYPE_NPCM7XX_ADC "npcm7xx-adc" | ||
145 | +#define NPCM7XX_ADC(obj) \ | ||
146 | + OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC) | ||
147 | + | ||
148 | +#endif /* NPCM7XX_ADC_H */ | ||
149 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/include/hw/arm/npcm7xx.h | ||
152 | +++ b/include/hw/arm/npcm7xx.h | ||
153 | @@ -XXX,XX +XXX,XX @@ | ||
154 | #define NPCM7XX_H | ||
155 | |||
156 | #include "hw/boards.h" | ||
157 | +#include "hw/adc/npcm7xx_adc.h" | ||
158 | #include "hw/cpu/a9mpcore.h" | ||
159 | #include "hw/gpio/npcm7xx_gpio.h" | ||
160 | #include "hw/mem/npcm7xx_mc.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | ||
162 | NPCM7xxGCRState gcr; | ||
163 | NPCM7xxCLKState clk; | ||
164 | NPCM7xxTimerCtrlState tim[3]; | ||
165 | + NPCM7xxADCState adc; | ||
166 | NPCM7xxOTPState key_storage; | ||
167 | NPCM7xxOTPState fuse_array; | ||
168 | NPCM7xxMCState mc; | ||
169 | diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c | ||
170 | new file mode 100644 | ||
171 | index XXXXXXX..XXXXXXX | ||
172 | --- /dev/null | ||
173 | +++ b/hw/adc/npcm7xx_adc.c | ||
174 | @@ -XXX,XX +XXX,XX @@ | ||
175 | +/* | ||
176 | + * Nuvoton NPCM7xx ADC Module | ||
177 | + * | ||
178 | + * Copyright 2020 Google LLC | ||
179 | + * | ||
180 | + * This program is free software; you can redistribute it and/or modify it | ||
181 | + * under the terms of the GNU General Public License as published by the | ||
182 | + * Free Software Foundation; either version 2 of the License, or | ||
183 | + * (at your option) any later version. | ||
184 | + * | ||
185 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
186 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
187 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
188 | + * for more details. | ||
189 | + */ | ||
190 | + | ||
191 | +#include "qemu/osdep.h" | ||
192 | +#include "hw/adc/npcm7xx_adc.h" | ||
193 | +#include "hw/qdev-clock.h" | ||
194 | +#include "hw/qdev-properties.h" | ||
195 | +#include "hw/registerfields.h" | ||
196 | +#include "migration/vmstate.h" | ||
197 | +#include "qemu/log.h" | ||
198 | +#include "qemu/module.h" | ||
199 | +#include "qemu/timer.h" | ||
200 | +#include "qemu/units.h" | ||
201 | +#include "trace.h" | ||
202 | + | ||
203 | +REG32(NPCM7XX_ADC_CON, 0x0) | ||
204 | +REG32(NPCM7XX_ADC_DATA, 0x4) | ||
205 | + | ||
206 | +/* Register field definitions. */ | ||
207 | +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) | ||
208 | +#define NPCM7XX_ADC_CON_INT_EN BIT(21) | ||
209 | +#define NPCM7XX_ADC_CON_REFSEL BIT(19) | ||
210 | +#define NPCM7XX_ADC_CON_INT BIT(18) | ||
211 | +#define NPCM7XX_ADC_CON_EN BIT(17) | ||
212 | +#define NPCM7XX_ADC_CON_RST BIT(16) | ||
213 | +#define NPCM7XX_ADC_CON_CONV BIT(14) | ||
214 | +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) | ||
215 | + | ||
216 | +#define NPCM7XX_ADC_MAX_RESULT 1023 | ||
217 | +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 | ||
218 | +#define NPCM7XX_ADC_CONV_CYCLES 20 | ||
219 | +#define NPCM7XX_ADC_RESET_CYCLES 10 | ||
220 | +#define NPCM7XX_ADC_R0_INPUT 500000 | ||
221 | +#define NPCM7XX_ADC_R1_INPUT 1500000 | ||
222 | + | ||
223 | +static void npcm7xx_adc_reset(NPCM7xxADCState *s) | ||
224 | +{ | ||
225 | + timer_del(&s->conv_timer); | ||
226 | + s->con = 0x000c0001; | ||
227 | + s->data = 0x00000000; | ||
228 | +} | ||
229 | + | ||
230 | +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) | ||
231 | +{ | ||
232 | + uint32_t result; | ||
233 | + | ||
234 | + result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; | ||
235 | + if (result > NPCM7XX_ADC_MAX_RESULT) { | ||
236 | + result = NPCM7XX_ADC_MAX_RESULT; | ||
237 | + } | ||
238 | + | ||
239 | + return result; | ||
240 | +} | ||
241 | + | ||
242 | +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) | ||
243 | +{ | ||
244 | + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); | ||
245 | +} | ||
246 | + | ||
247 | +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, | ||
248 | + uint32_t cycles, uint32_t prescaler) | ||
249 | +{ | ||
250 | + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
251 | + int64_t ticks = cycles; | ||
252 | + int64_t ns; | ||
253 | + | ||
254 | + ticks *= prescaler; | ||
255 | + ns = clock_ticks_to_ns(clk, ticks); | ||
256 | + ns += now; | ||
257 | + timer_mod(timer, ns); | ||
258 | +} | ||
259 | + | ||
260 | +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) | ||
261 | +{ | ||
262 | + uint32_t prescaler = npcm7xx_adc_prescaler(s); | ||
263 | + | ||
264 | + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES, | ||
265 | + prescaler); | ||
266 | +} | ||
267 | + | ||
268 | +static void npcm7xx_adc_convert_done(void *opaque) | ||
269 | +{ | ||
270 | + NPCM7xxADCState *s = opaque; | ||
271 | + uint32_t input = NPCM7XX_ADC_CON_MUX(s->con); | ||
272 | + uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL) | ||
273 | + ? s->iref : s->vref; | ||
274 | + | ||
275 | + if (input >= NPCM7XX_ADC_NUM_INPUTS) { | ||
276 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n", | ||
277 | + __func__, input); | ||
278 | + return; | ||
279 | + } | ||
280 | + s->data = npcm7xx_adc_convert(s->adci[input], ref); | ||
281 | + if (s->con & NPCM7XX_ADC_CON_INT_EN) { | ||
282 | + s->con |= NPCM7XX_ADC_CON_INT; | ||
283 | + qemu_irq_raise(s->irq); | ||
284 | + } | ||
285 | + s->con &= ~NPCM7XX_ADC_CON_CONV; | ||
286 | +} | ||
287 | + | ||
288 | +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) | ||
289 | +{ | ||
290 | + adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT, | ||
291 | + adc->iref); | ||
292 | + adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT, | ||
293 | + adc->iref); | ||
294 | +} | ||
295 | + | ||
296 | +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) | ||
297 | +{ | ||
298 | + uint32_t old_con = s->con; | ||
299 | + | ||
300 | + /* Write ADC_INT to 1 to clear it */ | ||
301 | + if (new_con & NPCM7XX_ADC_CON_INT) { | ||
302 | + new_con &= ~NPCM7XX_ADC_CON_INT; | ||
303 | + qemu_irq_lower(s->irq); | ||
304 | + } else if (old_con & NPCM7XX_ADC_CON_INT) { | ||
305 | + new_con |= NPCM7XX_ADC_CON_INT; | ||
306 | + } | ||
307 | + | ||
308 | + s->con = new_con; | ||
309 | + | ||
310 | + if (s->con & NPCM7XX_ADC_CON_RST) { | ||
311 | + npcm7xx_adc_reset(s); | ||
312 | + return; | ||
313 | + } | ||
314 | + | ||
315 | + if ((s->con & NPCM7XX_ADC_CON_EN)) { | ||
316 | + if (s->con & NPCM7XX_ADC_CON_CONV) { | ||
317 | + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { | ||
318 | + npcm7xx_adc_start_convert(s); | ||
319 | + } | ||
320 | + } else { | ||
321 | + timer_del(&s->conv_timer); | ||
322 | + } | ||
323 | + } | ||
324 | +} | ||
325 | + | ||
326 | +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size) | ||
327 | +{ | ||
328 | + uint64_t value = 0; | ||
329 | + NPCM7xxADCState *s = opaque; | ||
330 | + | ||
331 | + switch (offset) { | ||
332 | + case A_NPCM7XX_ADC_CON: | ||
333 | + value = s->con; | ||
334 | + break; | ||
335 | + | ||
336 | + case A_NPCM7XX_ADC_DATA: | ||
337 | + value = s->data; | ||
338 | + break; | ||
339 | + | ||
340 | + default: | ||
341 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
342 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
343 | + __func__, offset); | ||
344 | + break; | ||
345 | + } | ||
346 | + | ||
347 | + trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value); | ||
348 | + return value; | ||
349 | +} | ||
350 | + | ||
351 | +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v, | ||
352 | + unsigned size) | ||
353 | +{ | ||
354 | + NPCM7xxADCState *s = opaque; | ||
355 | + | ||
356 | + trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v); | ||
357 | + switch (offset) { | ||
358 | + case A_NPCM7XX_ADC_CON: | ||
359 | + npcm7xx_adc_write_con(s, v); | ||
360 | + break; | ||
361 | + | ||
362 | + case A_NPCM7XX_ADC_DATA: | ||
363 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
364 | + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", | ||
365 | + __func__, offset); | ||
366 | + break; | ||
367 | + | ||
368 | + default: | ||
369 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
370 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
371 | + __func__, offset); | ||
372 | + break; | ||
373 | + } | ||
374 | + | ||
375 | +} | ||
376 | + | ||
377 | +static const struct MemoryRegionOps npcm7xx_adc_ops = { | ||
378 | + .read = npcm7xx_adc_read, | ||
379 | + .write = npcm7xx_adc_write, | ||
380 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
381 | + .valid = { | ||
382 | + .min_access_size = 4, | ||
383 | + .max_access_size = 4, | ||
384 | + .unaligned = false, | ||
385 | + }, | ||
386 | +}; | ||
387 | + | ||
388 | +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type) | ||
389 | +{ | ||
390 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
391 | + | ||
392 | + npcm7xx_adc_reset(s); | ||
393 | +} | ||
394 | + | ||
395 | +static void npcm7xx_adc_hold_reset(Object *obj) | ||
396 | +{ | ||
397 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
398 | + | ||
399 | + qemu_irq_lower(s->irq); | ||
400 | +} | ||
401 | + | ||
402 | +static void npcm7xx_adc_init(Object *obj) | ||
403 | +{ | ||
404 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
405 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
406 | + int i; | ||
407 | + | ||
408 | + sysbus_init_irq(sbd, &s->irq); | ||
409 | + | ||
410 | + timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL, | ||
411 | + npcm7xx_adc_convert_done, s); | ||
412 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, | ||
413 | + TYPE_NPCM7XX_ADC, 4 * KiB); | ||
414 | + sysbus_init_mmio(sbd, &s->iomem); | ||
415 | + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); | ||
416 | + | ||
417 | + for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { | ||
418 | + object_property_add_uint32_ptr(obj, "adci[*]", | ||
419 | + &s->adci[i], OBJ_PROP_FLAG_WRITE); | ||
420 | + } | ||
421 | + object_property_add_uint32_ptr(obj, "vref", | ||
422 | + &s->vref, OBJ_PROP_FLAG_WRITE); | ||
423 | + npcm7xx_adc_calibrate(s); | ||
424 | +} | ||
425 | + | ||
426 | +static const VMStateDescription vmstate_npcm7xx_adc = { | ||
427 | + .name = "npcm7xx-adc", | ||
428 | + .version_id = 0, | ||
429 | + .minimum_version_id = 0, | ||
430 | + .fields = (VMStateField[]) { | ||
431 | + VMSTATE_TIMER(conv_timer, NPCM7xxADCState), | ||
432 | + VMSTATE_UINT32(con, NPCM7xxADCState), | ||
433 | + VMSTATE_UINT32(data, NPCM7xxADCState), | ||
434 | + VMSTATE_CLOCK(clock, NPCM7xxADCState), | ||
435 | + VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS), | ||
436 | + VMSTATE_UINT32(vref, NPCM7xxADCState), | ||
437 | + VMSTATE_UINT32(iref, NPCM7xxADCState), | ||
438 | + VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState, | ||
439 | + NPCM7XX_ADC_NUM_CALIB), | ||
440 | + VMSTATE_END_OF_LIST(), | ||
441 | + }, | ||
442 | +}; | ||
443 | + | ||
444 | +static Property npcm7xx_timer_properties[] = { | ||
445 | + DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF), | ||
446 | + DEFINE_PROP_END_OF_LIST(), | ||
447 | +}; | ||
448 | + | ||
449 | +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data) | ||
450 | +{ | ||
451 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
452 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
453 | + | ||
454 | + dc->desc = "NPCM7xx ADC Module"; | ||
455 | + dc->vmsd = &vmstate_npcm7xx_adc; | ||
456 | + rc->phases.enter = npcm7xx_adc_enter_reset; | ||
457 | + rc->phases.hold = npcm7xx_adc_hold_reset; | ||
458 | + | ||
459 | + device_class_set_props(dc, npcm7xx_timer_properties); | ||
460 | +} | ||
461 | + | ||
462 | +static const TypeInfo npcm7xx_adc_info = { | ||
463 | + .name = TYPE_NPCM7XX_ADC, | ||
464 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
465 | + .instance_size = sizeof(NPCM7xxADCState), | ||
466 | + .class_init = npcm7xx_adc_class_init, | ||
467 | + .instance_init = npcm7xx_adc_init, | ||
468 | +}; | ||
469 | + | ||
470 | +static void npcm7xx_adc_register_types(void) | ||
471 | +{ | ||
472 | + type_register_static(&npcm7xx_adc_info); | ||
473 | +} | ||
474 | + | ||
475 | +type_init(npcm7xx_adc_register_types); | ||
476 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
477 | index XXXXXXX..XXXXXXX 100644 | ||
478 | --- a/hw/arm/npcm7xx.c | ||
479 | +++ b/hw/arm/npcm7xx.c | ||
480 | @@ -XXX,XX +XXX,XX @@ | ||
481 | #define NPCM7XX_EHCI_BA (0xf0806000) | ||
482 | #define NPCM7XX_OHCI_BA (0xf0807000) | ||
483 | |||
484 | +/* ADC Module */ | ||
485 | +#define NPCM7XX_ADC_BA (0xf000c000) | ||
486 | + | ||
487 | /* Internal AHB SRAM */ | ||
488 | #define NPCM7XX_RAM3_BA (0xc0008000) | ||
489 | #define NPCM7XX_RAM3_SZ (4 * KiB) | ||
490 | @@ -XXX,XX +XXX,XX @@ | ||
491 | #define NPCM7XX_ROM_BA (0xffff0000) | ||
492 | #define NPCM7XX_ROM_SZ (64 * KiB) | ||
493 | |||
494 | + | ||
495 | /* Clock configuration values to be fixed up when bypassing bootloader */ | ||
496 | |||
497 | /* Run PLL1 at 1600 MHz */ | ||
498 | @@ -XXX,XX +XXX,XX @@ | ||
499 | * interrupts. | ||
500 | */ | ||
501 | enum NPCM7xxInterrupt { | ||
502 | + NPCM7XX_ADC_IRQ = 0, | ||
503 | NPCM7XX_UART0_IRQ = 2, | ||
504 | NPCM7XX_UART1_IRQ, | ||
505 | NPCM7XX_UART2_IRQ, | ||
506 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s) | ||
507 | sizeof(value)); | ||
508 | } | ||
509 | |||
510 | +static void npcm7xx_write_adc_calibration(NPCM7xxState *s) | ||
511 | +{ | ||
512 | + /* Both ADC and the fuse array must have realized. */ | ||
513 | + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); | ||
514 | + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, | ||
515 | + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); | ||
516 | +} | ||
517 | + | ||
518 | static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) | ||
519 | { | ||
520 | return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
521 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
522 | TYPE_NPCM7XX_FUSE_ARRAY); | ||
523 | object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); | ||
524 | object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); | ||
525 | + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); | ||
526 | |||
527 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { | ||
528 | object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); | ||
529 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
530 | sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); | ||
531 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); | ||
532 | |||
533 | + /* ADC Modules. Cannot fail. */ | ||
534 | + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( | ||
535 | + DEVICE(&s->clk), "adc-clock")); | ||
536 | + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); | ||
537 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); | ||
538 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | ||
539 | + npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); | ||
540 | + npcm7xx_write_adc_calibration(s); | ||
541 | + | ||
542 | /* Timer Modules (TIM). Cannot fail. */ | ||
543 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); | ||
544 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
546 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | ||
547 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | ||
548 | create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); | ||
549 | - create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); | ||
550 | create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); | ||
551 | create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); | ||
552 | create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); | ||
553 | diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c | ||
554 | new file mode 100644 | ||
555 | index XXXXXXX..XXXXXXX | ||
556 | --- /dev/null | ||
557 | +++ b/tests/qtest/npcm7xx_adc-test.c | ||
558 | @@ -XXX,XX +XXX,XX @@ | ||
559 | +/* | ||
560 | + * QTests for Nuvoton NPCM7xx ADCModules. | ||
561 | + * | ||
562 | + * Copyright 2020 Google LLC | ||
563 | + * | ||
564 | + * This program is free software; you can redistribute it and/or modify it | ||
565 | + * under the terms of the GNU General Public License as published by the | ||
566 | + * Free Software Foundation; either version 2 of the License, or | ||
567 | + * (at your option) any later version. | ||
568 | + * | ||
569 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
570 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
571 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
572 | + * for more details. | ||
573 | + */ | ||
574 | + | ||
575 | +#include "qemu/osdep.h" | ||
576 | +#include "qemu/bitops.h" | ||
577 | +#include "qemu/timer.h" | ||
578 | +#include "libqos/libqtest.h" | ||
579 | +#include "qapi/qmp/qdict.h" | ||
580 | + | ||
581 | +#define REF_HZ (25000000) | ||
582 | + | ||
583 | +#define CON_OFFSET 0x0 | ||
584 | +#define DATA_OFFSET 0x4 | ||
585 | + | ||
586 | +#define NUM_INPUTS 8 | ||
587 | +#define DEFAULT_IREF 2000000 | ||
588 | +#define CONV_CYCLES 20 | ||
589 | +#define RESET_CYCLES 10 | ||
590 | +#define R0_INPUT 500000 | ||
591 | +#define R1_INPUT 1500000 | ||
592 | +#define MAX_RESULT 1023 | ||
593 | + | ||
594 | +#define DEFAULT_CLKDIV 5 | ||
595 | + | ||
596 | +#define FUSE_ARRAY_BA 0xf018a000 | ||
597 | +#define FCTL_OFFSET 0x14 | ||
598 | +#define FST_OFFSET 0x0 | ||
599 | +#define FADDR_OFFSET 0x4 | ||
600 | +#define FDATA_OFFSET 0x8 | ||
601 | +#define ADC_CALIB_ADDR 24 | ||
602 | +#define FUSE_READ 0x2 | ||
603 | + | ||
604 | +/* Register field definitions. */ | ||
605 | +#define CON_MUX(rv) ((rv) << 24) | ||
606 | +#define CON_INT_EN BIT(21) | ||
607 | +#define CON_REFSEL BIT(19) | ||
608 | +#define CON_INT BIT(18) | ||
609 | +#define CON_EN BIT(17) | ||
610 | +#define CON_RST BIT(16) | ||
611 | +#define CON_CONV BIT(14) | ||
612 | +#define CON_DIV(rv) extract32(rv, 1, 8) | ||
613 | + | ||
614 | +#define FST_RDST BIT(1) | ||
615 | +#define FDATA_MASK 0xff | ||
616 | + | ||
617 | +#define MAX_ERROR 10000 | ||
618 | +#define MIN_CALIB_INPUT 100000 | ||
619 | +#define MAX_CALIB_INPUT 1800000 | ||
620 | + | ||
621 | +static const uint32_t input_list[] = { | ||
622 | + 100000, | ||
623 | + 500000, | ||
624 | + 1000000, | ||
625 | + 1500000, | ||
626 | + 1800000, | ||
627 | + 2000000, | ||
628 | +}; | ||
629 | + | ||
630 | +static const uint32_t vref_list[] = { | ||
631 | + 2000000, | ||
632 | + 2200000, | ||
633 | + 2500000, | ||
634 | +}; | ||
635 | + | ||
636 | +static const uint32_t iref_list[] = { | ||
637 | + 1800000, | ||
638 | + 1900000, | ||
639 | + 2000000, | ||
640 | + 2100000, | ||
641 | + 2200000, | ||
642 | +}; | ||
643 | + | ||
644 | +static const uint32_t div_list[] = {0, 1, 3, 7, 15}; | ||
645 | + | ||
646 | +typedef struct ADC { | ||
647 | + int irq; | ||
648 | + uint64_t base_addr; | ||
649 | +} ADC; | ||
650 | + | ||
651 | +ADC adc = { | ||
652 | + .irq = 0, | ||
653 | + .base_addr = 0xf000c000 | ||
654 | +}; | ||
655 | + | ||
656 | +static uint32_t adc_read_con(QTestState *qts, const ADC *adc) | ||
657 | +{ | ||
658 | + return qtest_readl(qts, adc->base_addr + CON_OFFSET); | ||
659 | +} | ||
660 | + | ||
661 | +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) | ||
662 | +{ | ||
663 | + qtest_writel(qts, adc->base_addr + CON_OFFSET, value); | ||
664 | +} | ||
665 | + | ||
666 | +static uint32_t adc_read_data(QTestState *qts, const ADC *adc) | ||
667 | +{ | ||
668 | + return qtest_readl(qts, adc->base_addr + DATA_OFFSET); | ||
669 | +} | ||
670 | + | ||
671 | +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv) | ||
672 | +{ | ||
673 | + return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0]) | ||
674 | + / (int32_t)(rv[1] - rv[0]); | ||
675 | +} | ||
676 | + | ||
677 | +static void adc_qom_set(QTestState *qts, const ADC *adc, | ||
678 | + const char *name, uint32_t value) | ||
679 | +{ | ||
680 | + QDict *response; | ||
681 | + const char *path = "/machine/soc/adc"; | ||
682 | + | ||
683 | + g_test_message("Setting properties %s of %s with value %u", | ||
684 | + name, path, value); | ||
685 | + response = qtest_qmp(qts, "{ 'execute': 'qom-set'," | ||
686 | + " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}", | ||
687 | + path, name, value); | ||
688 | + /* The qom set message returns successfully. */ | ||
689 | + g_assert_true(qdict_haskey(response, "return")); | ||
690 | +} | ||
691 | + | ||
692 | +static void adc_write_input(QTestState *qts, const ADC *adc, | ||
693 | + uint32_t index, uint32_t value) | ||
694 | +{ | ||
695 | + char name[100]; | ||
696 | + | ||
697 | + sprintf(name, "adci[%u]", index); | ||
698 | + adc_qom_set(qts, adc, name, value); | ||
699 | +} | ||
700 | + | ||
701 | +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) | ||
702 | +{ | ||
703 | + adc_qom_set(qts, adc, "vref", value); | ||
704 | +} | ||
705 | + | ||
706 | +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref) | ||
707 | +{ | ||
708 | + uint32_t output; | ||
709 | + | ||
710 | + g_assert_cmpuint(input, <=, ref); | ||
711 | + output = (input * (MAX_RESULT + 1)) / ref; | ||
712 | + if (output > MAX_RESULT) { | ||
713 | + output = MAX_RESULT; | ||
714 | + } | ||
715 | + | ||
716 | + return output; | ||
717 | +} | ||
718 | + | ||
719 | +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) | ||
720 | +{ | ||
721 | + uint32_t div = extract32(adc_read_con(qts, adc), 1, 8); | ||
722 | + | ||
723 | + return 2 * (div + 1); | ||
724 | +} | ||
725 | + | ||
726 | +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, | ||
727 | + uint32_t clkdiv) | ||
728 | +{ | ||
729 | + return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; | ||
730 | +} | ||
731 | + | ||
732 | +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, | ||
733 | + uint32_t clkdiv) | ||
734 | +{ | ||
735 | + uint32_t prescaler = adc_prescaler(qts, adc); | ||
736 | + | ||
737 | + /* | ||
738 | + * ADC should takes roughly 20 cycles to convert one sample. So we assert it | ||
739 | + * should take 10~30 cycles here. | ||
740 | + */ | ||
741 | + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler, | ||
742 | + clkdiv)); | ||
743 | + /* ADC is still converting. */ | ||
744 | + g_assert_true(adc_read_con(qts, adc) & CON_CONV); | ||
745 | + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv)); | ||
746 | + /* ADC has finished conversion. */ | ||
747 | + g_assert_false(adc_read_con(qts, adc) & CON_CONV); | ||
748 | +} | ||
749 | + | ||
750 | +/* Check ADC can be reset to default value. */ | ||
751 | +static void test_init(gconstpointer adc_p) | ||
752 | +{ | ||
753 | + const ADC *adc = adc_p; | ||
754 | + | ||
755 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
756 | + adc_write_con(qts, adc, CON_REFSEL | CON_INT); | ||
757 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL); | ||
758 | + qtest_quit(qts); | ||
759 | +} | ||
760 | + | ||
761 | +/* Check ADC can convert from an internal reference. */ | ||
762 | +static void test_convert_internal(gconstpointer adc_p) | ||
763 | +{ | ||
764 | + const ADC *adc = adc_p; | ||
765 | + uint32_t index, input, output, expected_output; | ||
766 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
767 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
768 | + | ||
769 | + for (index = 0; index < NUM_INPUTS; ++index) { | ||
770 | + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
771 | + input = input_list[i]; | ||
772 | + expected_output = adc_calculate_output(input, DEFAULT_IREF); | ||
773 | + | ||
774 | + adc_write_input(qts, adc, index, input); | ||
775 | + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | | ||
776 | + CON_EN | CON_CONV); | ||
777 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
778 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | | ||
779 | + CON_REFSEL | CON_EN); | ||
780 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
781 | + output = adc_read_data(qts, adc); | ||
782 | + g_assert_cmpuint(output, ==, expected_output); | ||
783 | + } | ||
784 | + } | ||
785 | + | ||
786 | + qtest_quit(qts); | ||
787 | +} | ||
788 | + | ||
789 | +/* Check ADC can convert from an external reference. */ | ||
790 | +static void test_convert_external(gconstpointer adc_p) | ||
791 | +{ | ||
792 | + const ADC *adc = adc_p; | ||
793 | + uint32_t index, input, vref, output, expected_output; | ||
794 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
795 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
796 | + | ||
797 | + for (index = 0; index < NUM_INPUTS; ++index) { | ||
798 | + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
799 | + for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) { | ||
800 | + input = input_list[i]; | ||
801 | + vref = vref_list[j]; | ||
802 | + expected_output = adc_calculate_output(input, vref); | ||
803 | + | ||
804 | + adc_write_input(qts, adc, index, input); | ||
805 | + adc_write_vref(qts, adc, vref); | ||
806 | + adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN | | ||
807 | + CON_CONV); | ||
808 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
809 | + g_assert_cmphex(adc_read_con(qts, adc), ==, | ||
810 | + CON_MUX(index) | CON_EN); | ||
811 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
812 | + output = adc_read_data(qts, adc); | ||
813 | + g_assert_cmpuint(output, ==, expected_output); | ||
814 | + } | ||
815 | + } | ||
816 | + } | ||
817 | + | ||
818 | + qtest_quit(qts); | ||
819 | +} | ||
820 | + | ||
821 | +/* Check ADC interrupt files if and only if CON_INT_EN is set. */ | ||
822 | +static void test_interrupt(gconstpointer adc_p) | ||
823 | +{ | ||
824 | + const ADC *adc = adc_p; | ||
825 | + uint32_t index, input, output, expected_output; | ||
826 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
827 | + | ||
828 | + index = 1; | ||
829 | + input = input_list[1]; | ||
830 | + expected_output = adc_calculate_output(input, DEFAULT_IREF); | ||
831 | + | ||
832 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
833 | + adc_write_input(qts, adc, index, input); | ||
834 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
835 | + adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT | ||
836 | + | CON_EN | CON_CONV); | ||
837 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
838 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN | ||
839 | + | CON_REFSEL | CON_INT | CON_EN); | ||
840 | + g_assert_true(qtest_get_irq(qts, adc->irq)); | ||
841 | + output = adc_read_data(qts, adc); | ||
842 | + g_assert_cmpuint(output, ==, expected_output); | ||
843 | + | ||
844 | + qtest_quit(qts); | ||
845 | +} | ||
846 | + | ||
847 | +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */ | ||
848 | +static void test_reset(gconstpointer adc_p) | ||
849 | +{ | ||
850 | + const ADC *adc = adc_p; | ||
851 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
852 | + | ||
853 | + for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) { | ||
854 | + uint32_t div = div_list[i]; | ||
855 | + | ||
856 | + adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div)); | ||
857 | + qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES, | ||
858 | + adc_prescaler(qts, adc), DEFAULT_CLKDIV)); | ||
859 | + g_assert_false(adc_read_con(qts, adc) & CON_EN); | ||
860 | + } | ||
861 | + qtest_quit(qts); | ||
862 | +} | ||
863 | + | ||
864 | +/* Check ADC Calibration works as desired. */ | ||
865 | +static void test_calibrate(gconstpointer adc_p) | ||
866 | +{ | ||
867 | + int i, j; | ||
868 | + const ADC *adc = adc_p; | ||
869 | + | ||
870 | + for (j = 0; j < ARRAY_SIZE(iref_list); ++j) { | ||
871 | + uint32_t iref = iref_list[j]; | ||
872 | + uint32_t expected_rv[] = { | ||
873 | + adc_calculate_output(R0_INPUT, iref), | ||
874 | + adc_calculate_output(R1_INPUT, iref), | ||
875 | + }; | ||
876 | + char buf[100]; | ||
877 | + QTestState *qts; | ||
878 | + | ||
879 | + sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref); | ||
880 | + qts = qtest_init(buf); | ||
881 | + | ||
882 | + /* Check the converted value is correct using the calibration value. */ | ||
883 | + for (i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
884 | + uint32_t input; | ||
885 | + uint32_t output; | ||
886 | + uint32_t expected_output; | ||
887 | + uint32_t calibrated_voltage; | ||
888 | + uint32_t index = 0; | ||
889 | + | ||
890 | + input = input_list[i]; | ||
891 | + /* Calibration only works for input range 0.1V ~ 1.8V. */ | ||
892 | + if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) { | ||
893 | + continue; | ||
894 | + } | ||
895 | + expected_output = adc_calculate_output(input, iref); | ||
896 | + | ||
897 | + adc_write_input(qts, adc, index, input); | ||
898 | + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | | ||
899 | + CON_EN | CON_CONV); | ||
900 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
901 | + g_assert_cmphex(adc_read_con(qts, adc), ==, | ||
902 | + CON_REFSEL | CON_MUX(index) | CON_EN); | ||
903 | + output = adc_read_data(qts, adc); | ||
904 | + g_assert_cmpuint(output, ==, expected_output); | ||
905 | + | ||
906 | + calibrated_voltage = adc_calibrate(output, expected_rv); | ||
907 | + g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR); | ||
908 | + g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR); | ||
909 | + } | ||
910 | + | ||
911 | + qtest_quit(qts); | ||
912 | + } | ||
913 | +} | ||
914 | + | ||
915 | +static void adc_add_test(const char *name, const ADC* wd, | ||
916 | + GTestDataFunc fn) | ||
917 | +{ | ||
918 | + g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name); | ||
919 | + qtest_add_data_func(full_name, wd, fn); | ||
920 | +} | ||
921 | +#define add_test(name, td) adc_add_test(#name, td, test_##name) | ||
922 | + | ||
923 | +int main(int argc, char **argv) | ||
924 | +{ | ||
925 | + g_test_init(&argc, &argv, NULL); | ||
926 | + | ||
927 | + add_test(init, &adc); | ||
928 | + add_test(convert_internal, &adc); | ||
929 | + add_test(convert_external, &adc); | ||
930 | + add_test(interrupt, &adc); | ||
931 | + add_test(reset, &adc); | ||
932 | + add_test(calibrate, &adc); | ||
933 | + | ||
934 | + return g_test_run(); | ||
935 | +} | ||
936 | diff --git a/hw/adc/meson.build b/hw/adc/meson.build | ||
937 | index XXXXXXX..XXXXXXX 100644 | ||
938 | --- a/hw/adc/meson.build | ||
939 | +++ b/hw/adc/meson.build | ||
940 | @@ -1 +1,2 @@ | ||
941 | softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) | ||
942 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) | ||
943 | diff --git a/hw/adc/trace-events b/hw/adc/trace-events | ||
944 | new file mode 100644 | ||
945 | index XXXXXXX..XXXXXXX | ||
946 | --- /dev/null | ||
947 | +++ b/hw/adc/trace-events | ||
948 | @@ -XXX,XX +XXX,XX @@ | ||
949 | +# See docs/devel/tracing.txt for syntax documentation. | ||
950 | + | ||
951 | +# npcm7xx_adc.c | ||
952 | +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 | ||
953 | +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 | ||
954 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
955 | index XXXXXXX..XXXXXXX 100644 | ||
956 | --- a/tests/qtest/meson.build | ||
957 | +++ b/tests/qtest/meson.build | ||
958 | @@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \ | ||
959 | ['prom-env-test', 'boot-serial-test'] | ||
960 | |||
961 | qtests_npcm7xx = \ | ||
962 | - ['npcm7xx_gpio-test', | ||
963 | + ['npcm7xx_adc-test', | ||
964 | + 'npcm7xx_gpio-test', | ||
965 | 'npcm7xx_rng-test', | ||
966 | 'npcm7xx_timer-test', | ||
967 | 'npcm7xx_watchdog_timer-test'] | ||
90 | -- | 968 | -- |
91 | 2.20.1 | 969 | 2.20.1 |
92 | 970 | ||
93 | 971 | diff view generated by jsdifflib |
1 | Add a new script to automate the process of running the Coverity | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | Scan build tools and uploading the resulting tarball to the | ||
3 | website. | ||
4 | 2 | ||
5 | This is intended eventually to be driven from Travis, | 3 | The PWM module is part of NPCM7XX module. Each NPCM7XX module has two |
6 | but it can be run locally, if you are a maintainer of the | 4 | identical PWM modules. Each module contains 4 PWM entries. Each PWM has |
7 | QEMU project on the Coverity Scan website and have the secret | 5 | two outputs: frequency and duty_cycle. Both are computed using inputs |
8 | upload token. | 6 | from software side. |
9 | 7 | ||
10 | The script must be run on a Fedora 30 system. Support for using a | 8 | This module does not model detail pulse signals since it is expensive. |
11 | Docker container is added in a following commit. | 9 | It also does not model interrupts and watchdogs that are dependant on |
10 | the detail models. The interfaces for these are left in the module so | ||
11 | that anyone in need for these functionalities can implement on their | ||
12 | own. | ||
12 | 13 | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 14 | The user can read the duty cycle and frequency using qom-get command. |
15 | |||
16 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
17 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
18 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
19 | Message-id: 20210108190945.949196-5-wuhaotsh@google.com | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Message-id: 20200319193323.2038-6-peter.maydell@linaro.org | ||
16 | --- | 22 | --- |
17 | MAINTAINERS | 5 + | 23 | docs/system/arm/nuvoton.rst | 2 +- |
18 | scripts/coverity-scan/run-coverity-scan | 311 ++++++++++++++++++++++++ | 24 | include/hw/arm/npcm7xx.h | 2 + |
19 | 2 files changed, 316 insertions(+) | 25 | include/hw/misc/npcm7xx_pwm.h | 105 +++++++ |
20 | create mode 100755 scripts/coverity-scan/run-coverity-scan | 26 | hw/arm/npcm7xx.c | 26 +- |
27 | hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++ | ||
28 | hw/misc/meson.build | 1 + | ||
29 | hw/misc/trace-events | 6 + | ||
30 | 7 files changed, 689 insertions(+), 3 deletions(-) | ||
31 | create mode 100644 include/hw/misc/npcm7xx_pwm.h | ||
32 | create mode 100644 hw/misc/npcm7xx_pwm.c | ||
21 | 33 | ||
22 | diff --git a/MAINTAINERS b/MAINTAINERS | 34 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
23 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/MAINTAINERS | 36 | --- a/docs/system/arm/nuvoton.rst |
25 | +++ b/MAINTAINERS | 37 | +++ b/docs/system/arm/nuvoton.rst |
26 | @@ -XXX,XX +XXX,XX @@ M: Markus Armbruster <armbru@redhat.com> | 38 | @@ -XXX,XX +XXX,XX @@ Supported devices |
27 | S: Supported | 39 | * USB host (USBH) |
28 | F: scripts/coverity-model.c | 40 | * GPIO controller |
29 | 41 | * Analog to Digital Converter (ADC) | |
30 | +Coverity Scan integration | 42 | + * Pulse Width Modulation (PWM) |
31 | +M: Peter Maydell <peter.maydell@linaro.org> | 43 | |
32 | +S: Maintained | 44 | Missing devices |
33 | +F: scripts/coverity-scan/ | 45 | --------------- |
34 | + | 46 | @@ -XXX,XX +XXX,XX @@ Missing devices |
35 | Device Tree | 47 | * Peripheral SPI controller (PSPI) |
36 | M: Alistair Francis <alistair.francis@wdc.com> | 48 | * SD/MMC host |
37 | R: David Gibson <david@gibson.dropbear.id.au> | 49 | * PECI interface |
38 | diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan | 50 | - * Pulse Width Modulation (PWM) |
39 | new file mode 100755 | 51 | * Tachometer |
52 | * PCI and PCIe root complex and bridges | ||
53 | * VDM and MCTP support | ||
54 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/include/hw/arm/npcm7xx.h | ||
57 | +++ b/include/hw/arm/npcm7xx.h | ||
58 | @@ -XXX,XX +XXX,XX @@ | ||
59 | #include "hw/mem/npcm7xx_mc.h" | ||
60 | #include "hw/misc/npcm7xx_clk.h" | ||
61 | #include "hw/misc/npcm7xx_gcr.h" | ||
62 | +#include "hw/misc/npcm7xx_pwm.h" | ||
63 | #include "hw/misc/npcm7xx_rng.h" | ||
64 | #include "hw/nvram/npcm7xx_otp.h" | ||
65 | #include "hw/timer/npcm7xx_timer.h" | ||
66 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | ||
67 | NPCM7xxCLKState clk; | ||
68 | NPCM7xxTimerCtrlState tim[3]; | ||
69 | NPCM7xxADCState adc; | ||
70 | + NPCM7xxPWMState pwm[2]; | ||
71 | NPCM7xxOTPState key_storage; | ||
72 | NPCM7xxOTPState fuse_array; | ||
73 | NPCM7xxMCState mc; | ||
74 | diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h | ||
75 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | 76 | index XXXXXXX..XXXXXXX |
41 | --- /dev/null | 77 | --- /dev/null |
42 | +++ b/scripts/coverity-scan/run-coverity-scan | 78 | +++ b/include/hw/misc/npcm7xx_pwm.h |
43 | @@ -XXX,XX +XXX,XX @@ | 79 | @@ -XXX,XX +XXX,XX @@ |
44 | +#!/bin/sh -e | 80 | +/* |
45 | + | 81 | + * Nuvoton NPCM7xx PWM Module |
46 | +# Upload a created tarball to Coverity Scan, as per | 82 | + * |
47 | +# https://scan.coverity.com/projects/qemu/builds/new | 83 | + * Copyright 2020 Google LLC |
48 | + | 84 | + * |
49 | +# This work is licensed under the terms of the GNU GPL version 2, | 85 | + * This program is free software; you can redistribute it and/or modify it |
50 | +# or (at your option) any later version. | 86 | + * under the terms of the GNU General Public License as published by the |
51 | +# See the COPYING file in the top-level directory. | 87 | + * Free Software Foundation; either version 2 of the License, or |
52 | +# | 88 | + * (at your option) any later version. |
53 | +# Copyright (c) 2017-2020 Linaro Limited | 89 | + * |
54 | +# Written by Peter Maydell | 90 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
55 | + | 91 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
56 | +# Note that this script will automatically download and | 92 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
57 | +# run the (closed-source) coverity build tools, so don't | 93 | + * for more details. |
58 | +# use it if you don't trust them! | 94 | + */ |
59 | + | 95 | +#ifndef NPCM7XX_PWM_H |
60 | +# This script assumes that you're running it from a QEMU source | 96 | +#define NPCM7XX_PWM_H |
61 | +# tree, and that tree is a fresh clean one, because we do an in-tree | 97 | + |
62 | +# build. (This is necessary so that the filenames that the Coverity | 98 | +#include "hw/clock.h" |
63 | +# Scan server sees are relative paths that match up with the component | 99 | +#include "hw/sysbus.h" |
64 | +# regular expressions it uses; an out-of-tree build won't work for this.) | 100 | +#include "hw/irq.h" |
65 | +# The host machine should have as many of QEMU's dependencies | 101 | + |
66 | +# installed as possible, for maximum coverity coverage. | 102 | +/* Each PWM module holds 4 PWM channels. */ |
67 | + | 103 | +#define NPCM7XX_PWM_PER_MODULE 4 |
68 | +# To do an upload you need to be a maintainer in the Coverity online | 104 | + |
69 | +# service, and you will need to know the "Coverity token", which is a | 105 | +/* |
70 | +# secret 8 digit hex string. You can find that from the web UI in the | 106 | + * Number of registers in one pwm module. Don't change this without increasing |
71 | +# project settings, if you have maintainer access there. | 107 | + * the version_id in vmstate. |
72 | + | 108 | + */ |
73 | +# Command line options: | 109 | +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t)) |
74 | +# --dry-run : run the tools, but don't actually do the upload | 110 | + |
75 | +# --update-tools-only : update the cached copy of the tools, but don't run them | 111 | +/* |
76 | +# --tokenfile : file to read Coverity token from | 112 | + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY |
77 | +# --version ver : specify version being analyzed (default: ask git) | 113 | + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty |
78 | +# --description desc : specify description of this version (default: ask git) | 114 | + * value of 100,000 the duty cycle for that PWM is 10%. |
79 | +# --srcdir : QEMU source tree to analyze (default: current working dir) | 115 | + */ |
80 | +# --results-tarball : path to copy the results tarball to (default: don't | 116 | +#define NPCM7XX_PWM_MAX_DUTY 1000000 |
81 | +# copy it anywhere, just upload it) | 117 | + |
82 | +# | 118 | +typedef struct NPCM7xxPWMState NPCM7xxPWMState; |
83 | +# User-specifiable environment variables: | 119 | + |
84 | +# COVERITY_TOKEN -- Coverity token | 120 | +/** |
85 | +# COVERITY_EMAIL -- the email address to use for uploads (default: | 121 | + * struct NPCM7xxPWM - The state of a single PWM channel. |
86 | +# looks at your git user.email config) | 122 | + * @module: The PWM module that contains this channel. |
87 | +# COVERITY_BUILD_CMD -- make command (default: 'make -jN' where N is | 123 | + * @irq: GIC interrupt line to fire on expiration if enabled. |
88 | +# number of CPUs as determined by 'nproc') | 124 | + * @running: Whether this PWM channel is generating output. |
89 | +# COVERITY_TOOL_BASE -- set to directory to put coverity tools | 125 | + * @inverted: Whether this PWM channel is inverted. |
90 | +# (default: /tmp/coverity-tools) | 126 | + * @index: The index of this PWM channel. |
91 | +# | 127 | + * @cnr: The counter register. |
92 | +# You must specify the token, either by environment variable or by | 128 | + * @cmr: The comparator register. |
93 | +# putting it in a file and using --tokenfile. Everything else has | 129 | + * @pdr: The data register. |
94 | +# a reasonable default if this is run from a git tree. | 130 | + * @pwdr: The watchdog register. |
95 | + | 131 | + * @freq: The frequency of this PWM channel. |
96 | +check_upload_permissions() { | 132 | + * @duty: The duty cycle of this PWM channel. One unit represents |
97 | + # Check whether we can do an upload to the server; will exit the script | 133 | + * 1/NPCM7XX_MAX_DUTY cycles. |
98 | + # with status 1 if the check failed (usually a bad token); | 134 | + */ |
99 | + # will exit the script with status 0 if the check indicated that we | 135 | +typedef struct NPCM7xxPWM { |
100 | + # can't upload yet (ie we are at quota) | 136 | + NPCM7xxPWMState *module; |
101 | + # Assumes that PROJTOKEN, PROJNAME and DRYRUN have been initialized. | 137 | + |
102 | + | 138 | + qemu_irq irq; |
103 | + echo "Checking upload permissions..." | 139 | + |
104 | + | 140 | + bool running; |
105 | + if ! up_perm="$(wget https://scan.coverity.com/api/upload_permitted --post-data "token=$PROJTOKEN&project=$PROJNAME" -q -O -)"; then | 141 | + bool inverted; |
106 | + echo "Coverity Scan API access denied: bad token?" | 142 | + |
107 | + exit 1 | 143 | + uint8_t index; |
108 | + fi | 144 | + uint32_t cnr; |
109 | + | 145 | + uint32_t cmr; |
110 | + # Really up_perm is a JSON response with either | 146 | + uint32_t pdr; |
111 | + # {upload_permitted:true} or {next_upload_permitted_at:<date>} | 147 | + uint32_t pwdr; |
112 | + # We do some hacky string parsing instead of properly parsing it. | 148 | + |
113 | + case "$up_perm" in | 149 | + uint32_t freq; |
114 | + *upload_permitted*true*) | 150 | + uint32_t duty; |
115 | + echo "Coverity Scan: upload permitted" | 151 | +} NPCM7xxPWM; |
116 | + ;; | 152 | + |
117 | + *next_upload_permitted_at*) | 153 | +/** |
118 | + if [ "$DRYRUN" = yes ]; then | 154 | + * struct NPCM7xxPWMState - Pulse Width Modulation device state. |
119 | + echo "Coverity Scan: upload quota reached, continuing dry run" | 155 | + * @parent: System bus device. |
120 | + else | 156 | + * @iomem: Memory region through which registers are accessed. |
121 | + echo "Coverity Scan: upload quota reached; stopping here" | 157 | + * @clock: The PWM clock. |
122 | + # Exit success as this isn't a build error. | 158 | + * @pwm: The PWM channels owned by this module. |
123 | + exit 0 | 159 | + * @ppr: The prescaler register. |
124 | + fi | 160 | + * @csr: The clock selector register. |
125 | + ;; | 161 | + * @pcr: The control register. |
126 | + *) | 162 | + * @pier: The interrupt enable register. |
127 | + echo "Coverity Scan upload check: unexpected result $up_perm" | 163 | + * @piir: The interrupt indication register. |
128 | + exit 1 | 164 | + */ |
129 | + ;; | 165 | +struct NPCM7xxPWMState { |
130 | + esac | 166 | + SysBusDevice parent; |
131 | +} | 167 | + |
132 | + | 168 | + MemoryRegion iomem; |
133 | + | 169 | + |
134 | +update_coverity_tools () { | 170 | + Clock *clock; |
135 | + # Check for whether we need to download the Coverity tools | 171 | + NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE]; |
136 | + # (either because we don't have a copy, or because it's out of date) | 172 | + |
137 | + # Assumes that COVERITY_TOOL_BASE, PROJTOKEN and PROJNAME are set. | 173 | + uint32_t ppr; |
138 | + | 174 | + uint32_t csr; |
139 | + mkdir -p "$COVERITY_TOOL_BASE" | 175 | + uint32_t pcr; |
140 | + cd "$COVERITY_TOOL_BASE" | 176 | + uint32_t pier; |
141 | + | 177 | + uint32_t piir; |
142 | + echo "Checking for new version of coverity build tools..." | 178 | +}; |
143 | + wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME&md5=1" -O coverity_tool.md5.new | 179 | + |
144 | + | 180 | +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm" |
145 | + if ! cmp -s coverity_tool.md5 coverity_tool.md5.new; then | 181 | +#define NPCM7XX_PWM(obj) \ |
146 | + # out of date md5 or no md5: download new build tool | 182 | + OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) |
147 | + # blow away the old build tool | 183 | + |
148 | + echo "Downloading coverity build tools..." | 184 | +#endif /* NPCM7XX_PWM_H */ |
149 | + rm -rf coverity_tool coverity_tool.tgz | 185 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c |
150 | + wget https://scan.coverity.com/download/linux64 --post-data "token=$PROJTOKEN&project=$PROJNAME" -O coverity_tool.tgz | 186 | index XXXXXXX..XXXXXXX 100644 |
151 | + if ! (cat coverity_tool.md5.new; echo " coverity_tool.tgz") | md5sum -c --status; then | 187 | --- a/hw/arm/npcm7xx.c |
152 | + echo "Downloaded tarball didn't match md5sum!" | 188 | +++ b/hw/arm/npcm7xx.c |
153 | + exit 1 | 189 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { |
154 | + fi | 190 | NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ |
155 | + # extract the new one, keeping it corralled in a 'coverity_tool' directory | 191 | NPCM7XX_EHCI_IRQ = 61, |
156 | + echo "Unpacking coverity build tools..." | 192 | NPCM7XX_OHCI_IRQ = 62, |
157 | + mkdir -p coverity_tool | 193 | + NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ |
158 | + cd coverity_tool | 194 | + NPCM7XX_PWM1_IRQ, /* PWM module 1 */ |
159 | + tar xf ../coverity_tool.tgz | 195 | NPCM7XX_GPIO0_IRQ = 116, |
160 | + cd .. | 196 | NPCM7XX_GPIO1_IRQ, |
161 | + mv coverity_tool.md5.new coverity_tool.md5 | 197 | NPCM7XX_GPIO2_IRQ, |
162 | + fi | 198 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = { |
163 | + | 199 | 0xb8000000, /* CS3 */ |
164 | + rm -f coverity_tool.md5.new | 200 | }; |
165 | +} | 201 | |
166 | + | 202 | +/* Register base address for each PWM Module */ |
167 | + | 203 | +static const hwaddr npcm7xx_pwm_addr[] = { |
168 | +# Check user-provided environment variables and arguments | 204 | + 0xf0103000, |
169 | +DRYRUN=no | 205 | + 0xf0104000, |
170 | +UPDATE_ONLY=no | 206 | +}; |
171 | + | 207 | + |
172 | +while [ "$#" -ge 1 ]; do | 208 | static const struct { |
173 | + case "$1" in | 209 | hwaddr regs_addr; |
174 | + --dry-run) | 210 | uint32_t unconnected_pins; |
175 | + shift | 211 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) |
176 | + DRYRUN=yes | 212 | object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], |
177 | + ;; | 213 | TYPE_NPCM7XX_FIU); |
178 | + --update-tools-only) | 214 | } |
179 | + shift | 215 | + |
180 | + UPDATE_ONLY=yes | 216 | + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { |
181 | + ;; | 217 | + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); |
182 | + --version) | 218 | + } |
183 | + shift | 219 | } |
184 | + if [ $# -eq 0 ]; then | 220 | |
185 | + echo "--version needs an argument" | 221 | static void npcm7xx_realize(DeviceState *dev, Error **errp) |
186 | + exit 1 | 222 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
187 | + fi | 223 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, |
188 | + VERSION="$1" | 224 | npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); |
189 | + shift | 225 | |
190 | + ;; | 226 | + /* PWM Modules. Cannot fail. */ |
191 | + --description) | 227 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); |
192 | + shift | 228 | + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { |
193 | + if [ $# -eq 0 ]; then | 229 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); |
194 | + echo "--description needs an argument" | 230 | + |
195 | + exit 1 | 231 | + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( |
196 | + fi | 232 | + DEVICE(&s->clk), "apb3-clock")); |
197 | + DESCRIPTION="$1" | 233 | + sysbus_realize(sbd, &error_abort); |
198 | + shift | 234 | + sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); |
199 | + ;; | 235 | + sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); |
200 | + --tokenfile) | 236 | + } |
201 | + shift | 237 | + |
202 | + if [ $# -eq 0 ]; then | 238 | /* |
203 | + echo "--tokenfile needs an argument" | 239 | * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects |
204 | + exit 1 | 240 | * specified, but this is a programming error. |
205 | + fi | 241 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
206 | + COVERITY_TOKEN="$(cat "$1")" | 242 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); |
207 | + shift | 243 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); |
208 | + ;; | 244 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); |
209 | + --srcdir) | 245 | - create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); |
210 | + shift | 246 | - create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); |
211 | + if [ $# -eq 0 ]; then | 247 | create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); |
212 | + echo "--srcdir needs an argument" | 248 | create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); |
213 | + exit 1 | 249 | create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); |
214 | + fi | 250 | diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c |
215 | + SRCDIR="$1" | 251 | new file mode 100644 |
216 | + shift | 252 | index XXXXXXX..XXXXXXX |
217 | + ;; | 253 | --- /dev/null |
218 | + --results-tarball) | 254 | +++ b/hw/misc/npcm7xx_pwm.c |
219 | + shift | 255 | @@ -XXX,XX +XXX,XX @@ |
220 | + if [ $# -eq 0 ]; then | 256 | +/* |
221 | + echo "--results-tarball needs an argument" | 257 | + * Nuvoton NPCM7xx PWM Module |
222 | + exit 1 | 258 | + * |
223 | + fi | 259 | + * Copyright 2020 Google LLC |
224 | + RESULTSTARBALL="$1" | 260 | + * |
225 | + shift | 261 | + * This program is free software; you can redistribute it and/or modify it |
226 | + ;; | 262 | + * under the terms of the GNU General Public License as published by the |
227 | + *) | 263 | + * Free Software Foundation; either version 2 of the License, or |
228 | + echo "Unexpected argument '$1'" | 264 | + * (at your option) any later version. |
229 | + exit 1 | 265 | + * |
230 | + ;; | 266 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
231 | + esac | 267 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
232 | +done | 268 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
233 | + | 269 | + * for more details. |
234 | +if [ -z "$COVERITY_TOKEN" ]; then | 270 | + */ |
235 | + echo "COVERITY_TOKEN environment variable not set" | 271 | + |
236 | + exit 1 | 272 | +#include "qemu/osdep.h" |
237 | +fi | 273 | +#include "hw/irq.h" |
238 | + | 274 | +#include "hw/qdev-clock.h" |
239 | +if [ -z "$COVERITY_BUILD_CMD" ]; then | 275 | +#include "hw/qdev-properties.h" |
240 | + NPROC=$(nproc) | 276 | +#include "hw/misc/npcm7xx_pwm.h" |
241 | + COVERITY_BUILD_CMD="make -j$NPROC" | 277 | +#include "hw/registerfields.h" |
242 | + echo "COVERITY_BUILD_CMD: using default '$COVERITY_BUILD_CMD'" | 278 | +#include "migration/vmstate.h" |
243 | +fi | 279 | +#include "qemu/bitops.h" |
244 | + | 280 | +#include "qemu/error-report.h" |
245 | +if [ -z "$COVERITY_TOOL_BASE" ]; then | 281 | +#include "qemu/log.h" |
246 | + echo "COVERITY_TOOL_BASE: using default /tmp/coverity-tools" | 282 | +#include "qemu/module.h" |
247 | + COVERITY_TOOL_BASE=/tmp/coverity-tools | 283 | +#include "qemu/units.h" |
248 | +fi | 284 | +#include "trace.h" |
249 | + | 285 | + |
250 | +if [ -z "$SRCDIR" ]; then | 286 | +REG32(NPCM7XX_PWM_PPR, 0x00); |
251 | + SRCDIR="$PWD" | 287 | +REG32(NPCM7XX_PWM_CSR, 0x04); |
252 | +fi | 288 | +REG32(NPCM7XX_PWM_PCR, 0x08); |
253 | + | 289 | +REG32(NPCM7XX_PWM_CNR0, 0x0c); |
254 | +PROJTOKEN="$COVERITY_TOKEN" | 290 | +REG32(NPCM7XX_PWM_CMR0, 0x10); |
255 | +PROJNAME=QEMU | 291 | +REG32(NPCM7XX_PWM_PDR0, 0x14); |
256 | +TARBALL=cov-int.tar.xz | 292 | +REG32(NPCM7XX_PWM_CNR1, 0x18); |
257 | + | 293 | +REG32(NPCM7XX_PWM_CMR1, 0x1c); |
258 | + | 294 | +REG32(NPCM7XX_PWM_PDR1, 0x20); |
259 | +if [ "$UPDATE_ONLY" = yes ]; then | 295 | +REG32(NPCM7XX_PWM_CNR2, 0x24); |
260 | + # Just do the tools update; we don't need to check whether | 296 | +REG32(NPCM7XX_PWM_CMR2, 0x28); |
261 | + # we are in a source tree or have upload rights for this, | 297 | +REG32(NPCM7XX_PWM_PDR2, 0x2c); |
262 | + # so do it before some of the command line and source tree checks. | 298 | +REG32(NPCM7XX_PWM_CNR3, 0x30); |
263 | + update_coverity_tools | 299 | +REG32(NPCM7XX_PWM_CMR3, 0x34); |
264 | + exit 0 | 300 | +REG32(NPCM7XX_PWM_PDR3, 0x38); |
265 | +fi | 301 | +REG32(NPCM7XX_PWM_PIER, 0x3c); |
266 | + | 302 | +REG32(NPCM7XX_PWM_PIIR, 0x40); |
267 | +cd "$SRCDIR" | 303 | +REG32(NPCM7XX_PWM_PWDR0, 0x44); |
268 | + | 304 | +REG32(NPCM7XX_PWM_PWDR1, 0x48); |
269 | +echo "Checking this is a QEMU source tree..." | 305 | +REG32(NPCM7XX_PWM_PWDR2, 0x4c); |
270 | +if ! [ -e "$SRCDIR/VERSION" ]; then | 306 | +REG32(NPCM7XX_PWM_PWDR3, 0x50); |
271 | + echo "Not in a QEMU source tree?" | 307 | + |
272 | + exit 1 | 308 | +/* Register field definitions. */ |
273 | +fi | 309 | +#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8) |
274 | + | 310 | +#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3) |
275 | +# Fill in defaults used by the non-update-only process | 311 | +#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4) |
276 | +if [ -z "$VERSION" ]; then | 312 | +#define NPCM7XX_CH_EN BIT(0) |
277 | + VERSION="$(git describe --always HEAD)" | 313 | +#define NPCM7XX_CH_INV BIT(2) |
278 | +fi | 314 | +#define NPCM7XX_CH_MOD BIT(3) |
279 | + | 315 | + |
280 | +if [ -z "$DESCRIPTION" ]; then | 316 | +/* Offset of each PWM channel's prescaler in the PPR register. */ |
281 | + DESCRIPTION="$(git rev-parse HEAD)" | 317 | +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 }; |
282 | +fi | 318 | +/* Offset of each PWM channel's clock selector in the CSR register. */ |
283 | + | 319 | +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 }; |
284 | +if [ -z "$COVERITY_EMAIL" ]; then | 320 | +/* Offset of each PWM channel's control variable in the PCR register. */ |
285 | + COVERITY_EMAIL="$(git config user.email)" | 321 | +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 }; |
286 | +fi | 322 | + |
287 | + | 323 | +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p) |
288 | +check_upload_permissions | 324 | +{ |
289 | + | 325 | + uint32_t ppr; |
290 | +update_coverity_tools | 326 | + uint32_t csr; |
291 | + | 327 | + uint32_t freq; |
292 | +TOOLBIN="$(cd "$COVERITY_TOOL_BASE" && echo $PWD/coverity_tool/cov-analysis-*/bin)" | 328 | + |
293 | + | 329 | + if (!p->running) { |
294 | +if ! test -x "$TOOLBIN/cov-build"; then | 330 | + return 0; |
295 | + echo "Couldn't find cov-build in the coverity build-tool directory??" | 331 | + } |
296 | + exit 1 | 332 | + |
297 | +fi | 333 | + csr = NPCM7XX_CSR(p->module->csr, p->index); |
298 | + | 334 | + ppr = NPCM7XX_PPR(p->module->ppr, p->index); |
299 | +export PATH="$TOOLBIN:$PATH" | 335 | + freq = clock_get_hz(p->module->clock); |
300 | + | 336 | + freq /= ppr + 1; |
301 | +cd "$SRCDIR" | 337 | + /* csr can only be 0~4 */ |
302 | + | 338 | + if (csr > 4) { |
303 | +echo "Doing make distclean..." | 339 | + qemu_log_mask(LOG_GUEST_ERROR, |
304 | +make distclean | 340 | + "%s: invalid csr value %u\n", |
305 | + | 341 | + __func__, csr); |
306 | +echo "Configuring..." | 342 | + csr = 4; |
307 | +# We configure with a fixed set of enables here to ensure that we don't | 343 | + } |
308 | +# accidentally reduce the scope of the analysis by doing the build on | 344 | + /* freq won't be changed if csr == 4. */ |
309 | +# the system that's missing a dependency that we need to build part of | 345 | + if (csr < 4) { |
310 | +# the codebase. | 346 | + freq >>= csr + 1; |
311 | +./configure --disable-modules --enable-sdl --enable-gtk \ | 347 | + } |
312 | + --enable-opengl --enable-vte --enable-gnutls \ | 348 | + |
313 | + --enable-nettle --enable-curses --enable-curl \ | 349 | + return freq / (p->cnr + 1); |
314 | + --audio-drv-list=oss,alsa,sdl,pa --enable-virtfs \ | 350 | +} |
315 | + --enable-vnc --enable-vnc-sasl --enable-vnc-jpeg --enable-vnc-png \ | 351 | + |
316 | + --enable-xen --enable-brlapi \ | 352 | +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) |
317 | + --enable-linux-aio --enable-attr \ | 353 | +{ |
318 | + --enable-cap-ng --enable-trace-backends=log --enable-spice --enable-rbd \ | 354 | + uint64_t duty; |
319 | + --enable-xfsctl --enable-libusb --enable-usb-redir \ | 355 | + |
320 | + --enable-libiscsi --enable-libnfs --enable-seccomp \ | 356 | + if (p->running) { |
321 | + --enable-tpm --enable-libssh --enable-lzo --enable-snappy --enable-bzip2 \ | 357 | + if (p->cnr == 0) { |
322 | + --enable-numa --enable-rdma --enable-smartcard --enable-virglrenderer \ | 358 | + duty = 0; |
323 | + --enable-mpath --enable-libxml2 --enable-glusterfs \ | 359 | + } else if (p->cmr >= p->cnr) { |
324 | + --enable-virtfs --enable-zstd | 360 | + duty = NPCM7XX_PWM_MAX_DUTY; |
325 | + | 361 | + } else { |
326 | +echo "Making libqemustub.a..." | 362 | + duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); |
327 | +make libqemustub.a | 363 | + } |
328 | + | 364 | + } else { |
329 | +echo "Running cov-build..." | 365 | + duty = 0; |
330 | +rm -rf cov-int | 366 | + } |
331 | +mkdir cov-int | 367 | + |
332 | +cov-build --dir cov-int $COVERITY_BUILD_CMD | 368 | + if (p->inverted) { |
333 | + | 369 | + duty = NPCM7XX_PWM_MAX_DUTY - duty; |
334 | +echo "Creating results tarball..." | 370 | + } |
335 | +tar cvf - cov-int | xz > "$TARBALL" | 371 | + |
336 | + | 372 | + return duty; |
337 | +if [ ! -z "$RESULTSTARBALL" ]; then | 373 | +} |
338 | + echo "Copying results tarball to $RESULTSTARBALL..." | 374 | + |
339 | + cp "$TARBALL" "$RESULTSTARBALL" | 375 | +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p) |
340 | +fi | 376 | +{ |
341 | + | 377 | + uint32_t freq = npcm7xx_pwm_calculate_freq(p); |
342 | +echo "Uploading results tarball..." | 378 | + |
343 | + | 379 | + if (freq != p->freq) { |
344 | +if [ "$DRYRUN" = yes ]; then | 380 | + trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path, |
345 | + echo "Dry run only, not uploading $TARBALL" | 381 | + p->index, p->freq, freq); |
346 | + exit 0 | 382 | + p->freq = freq; |
347 | +fi | 383 | + } |
348 | + | 384 | +} |
349 | +curl --form token="$PROJTOKEN" --form email="$COVERITY_EMAIL" \ | 385 | + |
350 | + --form file=@"$TARBALL" --form version="$VERSION" \ | 386 | +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p) |
351 | + --form description="$DESCRIPTION" \ | 387 | +{ |
352 | + https://scan.coverity.com/builds?project="$PROJNAME" | 388 | + uint32_t duty = npcm7xx_pwm_calculate_duty(p); |
353 | + | 389 | + |
354 | +echo "Done." | 390 | + if (duty != p->duty) { |
391 | + trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path, | ||
392 | + p->index, p->duty, duty); | ||
393 | + p->duty = duty; | ||
394 | + } | ||
395 | +} | ||
396 | + | ||
397 | +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p) | ||
398 | +{ | ||
399 | + npcm7xx_pwm_update_freq(p); | ||
400 | + npcm7xx_pwm_update_duty(p); | ||
401 | +} | ||
402 | + | ||
403 | +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr) | ||
404 | +{ | ||
405 | + int i; | ||
406 | + uint32_t old_ppr = s->ppr; | ||
407 | + | ||
408 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE); | ||
409 | + s->ppr = new_ppr; | ||
410 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
411 | + if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) { | ||
412 | + npcm7xx_pwm_update_freq(&s->pwm[i]); | ||
413 | + } | ||
414 | + } | ||
415 | +} | ||
416 | + | ||
417 | +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr) | ||
418 | +{ | ||
419 | + int i; | ||
420 | + uint32_t old_csr = s->csr; | ||
421 | + | ||
422 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE); | ||
423 | + s->csr = new_csr; | ||
424 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
425 | + if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) { | ||
426 | + npcm7xx_pwm_update_freq(&s->pwm[i]); | ||
427 | + } | ||
428 | + } | ||
429 | +} | ||
430 | + | ||
431 | +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr) | ||
432 | +{ | ||
433 | + int i; | ||
434 | + bool inverted; | ||
435 | + uint32_t pcr; | ||
436 | + NPCM7xxPWM *p; | ||
437 | + | ||
438 | + s->pcr = new_pcr; | ||
439 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE); | ||
440 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
441 | + p = &s->pwm[i]; | ||
442 | + pcr = NPCM7XX_CH(new_pcr, i); | ||
443 | + inverted = pcr & NPCM7XX_CH_INV; | ||
444 | + | ||
445 | + /* | ||
446 | + * We only run a PWM channel with toggle mode. Single-shot mode does not | ||
447 | + * generate frequency and duty-cycle values. | ||
448 | + */ | ||
449 | + if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) { | ||
450 | + if (p->running) { | ||
451 | + /* Re-run this PWM channel if inverted changed. */ | ||
452 | + if (p->inverted ^ inverted) { | ||
453 | + p->inverted = inverted; | ||
454 | + npcm7xx_pwm_update_duty(p); | ||
455 | + } | ||
456 | + } else { | ||
457 | + /* Run this PWM channel. */ | ||
458 | + p->running = true; | ||
459 | + p->inverted = inverted; | ||
460 | + npcm7xx_pwm_update_output(p); | ||
461 | + } | ||
462 | + } else { | ||
463 | + /* Clear this PWM channel. */ | ||
464 | + p->running = false; | ||
465 | + p->inverted = inverted; | ||
466 | + npcm7xx_pwm_update_output(p); | ||
467 | + } | ||
468 | + } | ||
469 | + | ||
470 | +} | ||
471 | + | ||
472 | +static hwaddr npcm7xx_cnr_index(hwaddr offset) | ||
473 | +{ | ||
474 | + switch (offset) { | ||
475 | + case A_NPCM7XX_PWM_CNR0: | ||
476 | + return 0; | ||
477 | + case A_NPCM7XX_PWM_CNR1: | ||
478 | + return 1; | ||
479 | + case A_NPCM7XX_PWM_CNR2: | ||
480 | + return 2; | ||
481 | + case A_NPCM7XX_PWM_CNR3: | ||
482 | + return 3; | ||
483 | + default: | ||
484 | + g_assert_not_reached(); | ||
485 | + } | ||
486 | +} | ||
487 | + | ||
488 | +static hwaddr npcm7xx_cmr_index(hwaddr offset) | ||
489 | +{ | ||
490 | + switch (offset) { | ||
491 | + case A_NPCM7XX_PWM_CMR0: | ||
492 | + return 0; | ||
493 | + case A_NPCM7XX_PWM_CMR1: | ||
494 | + return 1; | ||
495 | + case A_NPCM7XX_PWM_CMR2: | ||
496 | + return 2; | ||
497 | + case A_NPCM7XX_PWM_CMR3: | ||
498 | + return 3; | ||
499 | + default: | ||
500 | + g_assert_not_reached(); | ||
501 | + } | ||
502 | +} | ||
503 | + | ||
504 | +static hwaddr npcm7xx_pdr_index(hwaddr offset) | ||
505 | +{ | ||
506 | + switch (offset) { | ||
507 | + case A_NPCM7XX_PWM_PDR0: | ||
508 | + return 0; | ||
509 | + case A_NPCM7XX_PWM_PDR1: | ||
510 | + return 1; | ||
511 | + case A_NPCM7XX_PWM_PDR2: | ||
512 | + return 2; | ||
513 | + case A_NPCM7XX_PWM_PDR3: | ||
514 | + return 3; | ||
515 | + default: | ||
516 | + g_assert_not_reached(); | ||
517 | + } | ||
518 | +} | ||
519 | + | ||
520 | +static hwaddr npcm7xx_pwdr_index(hwaddr offset) | ||
521 | +{ | ||
522 | + switch (offset) { | ||
523 | + case A_NPCM7XX_PWM_PWDR0: | ||
524 | + return 0; | ||
525 | + case A_NPCM7XX_PWM_PWDR1: | ||
526 | + return 1; | ||
527 | + case A_NPCM7XX_PWM_PWDR2: | ||
528 | + return 2; | ||
529 | + case A_NPCM7XX_PWM_PWDR3: | ||
530 | + return 3; | ||
531 | + default: | ||
532 | + g_assert_not_reached(); | ||
533 | + } | ||
534 | +} | ||
535 | + | ||
536 | +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size) | ||
537 | +{ | ||
538 | + NPCM7xxPWMState *s = opaque; | ||
539 | + uint64_t value = 0; | ||
540 | + | ||
541 | + switch (offset) { | ||
542 | + case A_NPCM7XX_PWM_CNR0: | ||
543 | + case A_NPCM7XX_PWM_CNR1: | ||
544 | + case A_NPCM7XX_PWM_CNR2: | ||
545 | + case A_NPCM7XX_PWM_CNR3: | ||
546 | + value = s->pwm[npcm7xx_cnr_index(offset)].cnr; | ||
547 | + break; | ||
548 | + | ||
549 | + case A_NPCM7XX_PWM_CMR0: | ||
550 | + case A_NPCM7XX_PWM_CMR1: | ||
551 | + case A_NPCM7XX_PWM_CMR2: | ||
552 | + case A_NPCM7XX_PWM_CMR3: | ||
553 | + value = s->pwm[npcm7xx_cmr_index(offset)].cmr; | ||
554 | + break; | ||
555 | + | ||
556 | + case A_NPCM7XX_PWM_PDR0: | ||
557 | + case A_NPCM7XX_PWM_PDR1: | ||
558 | + case A_NPCM7XX_PWM_PDR2: | ||
559 | + case A_NPCM7XX_PWM_PDR3: | ||
560 | + value = s->pwm[npcm7xx_pdr_index(offset)].pdr; | ||
561 | + break; | ||
562 | + | ||
563 | + case A_NPCM7XX_PWM_PWDR0: | ||
564 | + case A_NPCM7XX_PWM_PWDR1: | ||
565 | + case A_NPCM7XX_PWM_PWDR2: | ||
566 | + case A_NPCM7XX_PWM_PWDR3: | ||
567 | + value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr; | ||
568 | + break; | ||
569 | + | ||
570 | + case A_NPCM7XX_PWM_PPR: | ||
571 | + value = s->ppr; | ||
572 | + break; | ||
573 | + | ||
574 | + case A_NPCM7XX_PWM_CSR: | ||
575 | + value = s->csr; | ||
576 | + break; | ||
577 | + | ||
578 | + case A_NPCM7XX_PWM_PCR: | ||
579 | + value = s->pcr; | ||
580 | + break; | ||
581 | + | ||
582 | + case A_NPCM7XX_PWM_PIER: | ||
583 | + value = s->pier; | ||
584 | + break; | ||
585 | + | ||
586 | + case A_NPCM7XX_PWM_PIIR: | ||
587 | + value = s->piir; | ||
588 | + break; | ||
589 | + | ||
590 | + default: | ||
591 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
592 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
593 | + __func__, offset); | ||
594 | + break; | ||
595 | + } | ||
596 | + | ||
597 | + trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value); | ||
598 | + return value; | ||
599 | +} | ||
600 | + | ||
601 | +static void npcm7xx_pwm_write(void *opaque, hwaddr offset, | ||
602 | + uint64_t v, unsigned size) | ||
603 | +{ | ||
604 | + NPCM7xxPWMState *s = opaque; | ||
605 | + NPCM7xxPWM *p; | ||
606 | + uint32_t value = v; | ||
607 | + | ||
608 | + trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value); | ||
609 | + switch (offset) { | ||
610 | + case A_NPCM7XX_PWM_CNR0: | ||
611 | + case A_NPCM7XX_PWM_CNR1: | ||
612 | + case A_NPCM7XX_PWM_CNR2: | ||
613 | + case A_NPCM7XX_PWM_CNR3: | ||
614 | + p = &s->pwm[npcm7xx_cnr_index(offset)]; | ||
615 | + p->cnr = value; | ||
616 | + npcm7xx_pwm_update_output(p); | ||
617 | + break; | ||
618 | + | ||
619 | + case A_NPCM7XX_PWM_CMR0: | ||
620 | + case A_NPCM7XX_PWM_CMR1: | ||
621 | + case A_NPCM7XX_PWM_CMR2: | ||
622 | + case A_NPCM7XX_PWM_CMR3: | ||
623 | + p = &s->pwm[npcm7xx_cmr_index(offset)]; | ||
624 | + p->cmr = value; | ||
625 | + npcm7xx_pwm_update_output(p); | ||
626 | + break; | ||
627 | + | ||
628 | + case A_NPCM7XX_PWM_PDR0: | ||
629 | + case A_NPCM7XX_PWM_PDR1: | ||
630 | + case A_NPCM7XX_PWM_PDR2: | ||
631 | + case A_NPCM7XX_PWM_PDR3: | ||
632 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
633 | + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", | ||
634 | + __func__, offset); | ||
635 | + break; | ||
636 | + | ||
637 | + case A_NPCM7XX_PWM_PWDR0: | ||
638 | + case A_NPCM7XX_PWM_PWDR1: | ||
639 | + case A_NPCM7XX_PWM_PWDR2: | ||
640 | + case A_NPCM7XX_PWM_PWDR3: | ||
641 | + qemu_log_mask(LOG_UNIMP, | ||
642 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
643 | + __func__, offset); | ||
644 | + break; | ||
645 | + | ||
646 | + case A_NPCM7XX_PWM_PPR: | ||
647 | + npcm7xx_pwm_write_ppr(s, value); | ||
648 | + break; | ||
649 | + | ||
650 | + case A_NPCM7XX_PWM_CSR: | ||
651 | + npcm7xx_pwm_write_csr(s, value); | ||
652 | + break; | ||
653 | + | ||
654 | + case A_NPCM7XX_PWM_PCR: | ||
655 | + npcm7xx_pwm_write_pcr(s, value); | ||
656 | + break; | ||
657 | + | ||
658 | + case A_NPCM7XX_PWM_PIER: | ||
659 | + qemu_log_mask(LOG_UNIMP, | ||
660 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
661 | + __func__, offset); | ||
662 | + break; | ||
663 | + | ||
664 | + case A_NPCM7XX_PWM_PIIR: | ||
665 | + qemu_log_mask(LOG_UNIMP, | ||
666 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
667 | + __func__, offset); | ||
668 | + break; | ||
669 | + | ||
670 | + default: | ||
671 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
672 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
673 | + __func__, offset); | ||
674 | + break; | ||
675 | + } | ||
676 | +} | ||
677 | + | ||
678 | +static const struct MemoryRegionOps npcm7xx_pwm_ops = { | ||
679 | + .read = npcm7xx_pwm_read, | ||
680 | + .write = npcm7xx_pwm_write, | ||
681 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
682 | + .valid = { | ||
683 | + .min_access_size = 4, | ||
684 | + .max_access_size = 4, | ||
685 | + .unaligned = false, | ||
686 | + }, | ||
687 | +}; | ||
688 | + | ||
689 | +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type) | ||
690 | +{ | ||
691 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
692 | + int i; | ||
693 | + | ||
694 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
695 | + NPCM7xxPWM *p = &s->pwm[i]; | ||
696 | + | ||
697 | + p->cnr = 0x00000000; | ||
698 | + p->cmr = 0x00000000; | ||
699 | + p->pdr = 0x00000000; | ||
700 | + p->pwdr = 0x00000000; | ||
701 | + } | ||
702 | + | ||
703 | + s->ppr = 0x00000000; | ||
704 | + s->csr = 0x00000000; | ||
705 | + s->pcr = 0x00000000; | ||
706 | + s->pier = 0x00000000; | ||
707 | + s->piir = 0x00000000; | ||
708 | +} | ||
709 | + | ||
710 | +static void npcm7xx_pwm_hold_reset(Object *obj) | ||
711 | +{ | ||
712 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
713 | + int i; | ||
714 | + | ||
715 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
716 | + qemu_irq_lower(s->pwm[i].irq); | ||
717 | + } | ||
718 | +} | ||
719 | + | ||
720 | +static void npcm7xx_pwm_init(Object *obj) | ||
721 | +{ | ||
722 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
723 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
724 | + int i; | ||
725 | + | ||
726 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
727 | + NPCM7xxPWM *p = &s->pwm[i]; | ||
728 | + p->module = s; | ||
729 | + p->index = i; | ||
730 | + sysbus_init_irq(sbd, &p->irq); | ||
731 | + } | ||
732 | + | ||
733 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, | ||
734 | + TYPE_NPCM7XX_PWM, 4 * KiB); | ||
735 | + sysbus_init_mmio(sbd, &s->iomem); | ||
736 | + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); | ||
737 | + | ||
738 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
739 | + object_property_add_uint32_ptr(obj, "freq[*]", | ||
740 | + &s->pwm[i].freq, OBJ_PROP_FLAG_READ); | ||
741 | + object_property_add_uint32_ptr(obj, "duty[*]", | ||
742 | + &s->pwm[i].duty, OBJ_PROP_FLAG_READ); | ||
743 | + } | ||
744 | +} | ||
745 | + | ||
746 | +static const VMStateDescription vmstate_npcm7xx_pwm = { | ||
747 | + .name = "npcm7xx-pwm", | ||
748 | + .version_id = 0, | ||
749 | + .minimum_version_id = 0, | ||
750 | + .fields = (VMStateField[]) { | ||
751 | + VMSTATE_BOOL(running, NPCM7xxPWM), | ||
752 | + VMSTATE_BOOL(inverted, NPCM7xxPWM), | ||
753 | + VMSTATE_UINT8(index, NPCM7xxPWM), | ||
754 | + VMSTATE_UINT32(cnr, NPCM7xxPWM), | ||
755 | + VMSTATE_UINT32(cmr, NPCM7xxPWM), | ||
756 | + VMSTATE_UINT32(pdr, NPCM7xxPWM), | ||
757 | + VMSTATE_UINT32(pwdr, NPCM7xxPWM), | ||
758 | + VMSTATE_UINT32(freq, NPCM7xxPWM), | ||
759 | + VMSTATE_UINT32(duty, NPCM7xxPWM), | ||
760 | + VMSTATE_END_OF_LIST(), | ||
761 | + }, | ||
762 | +}; | ||
763 | + | ||
764 | +static const VMStateDescription vmstate_npcm7xx_pwm_module = { | ||
765 | + .name = "npcm7xx-pwm-module", | ||
766 | + .version_id = 0, | ||
767 | + .minimum_version_id = 0, | ||
768 | + .fields = (VMStateField[]) { | ||
769 | + VMSTATE_CLOCK(clock, NPCM7xxPWMState), | ||
770 | + VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState, | ||
771 | + NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm, | ||
772 | + NPCM7xxPWM), | ||
773 | + VMSTATE_UINT32(ppr, NPCM7xxPWMState), | ||
774 | + VMSTATE_UINT32(csr, NPCM7xxPWMState), | ||
775 | + VMSTATE_UINT32(pcr, NPCM7xxPWMState), | ||
776 | + VMSTATE_UINT32(pier, NPCM7xxPWMState), | ||
777 | + VMSTATE_UINT32(piir, NPCM7xxPWMState), | ||
778 | + VMSTATE_END_OF_LIST(), | ||
779 | + }, | ||
780 | +}; | ||
781 | + | ||
782 | +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data) | ||
783 | +{ | ||
784 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
785 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
786 | + | ||
787 | + dc->desc = "NPCM7xx PWM Controller"; | ||
788 | + dc->vmsd = &vmstate_npcm7xx_pwm_module; | ||
789 | + rc->phases.enter = npcm7xx_pwm_enter_reset; | ||
790 | + rc->phases.hold = npcm7xx_pwm_hold_reset; | ||
791 | +} | ||
792 | + | ||
793 | +static const TypeInfo npcm7xx_pwm_info = { | ||
794 | + .name = TYPE_NPCM7XX_PWM, | ||
795 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
796 | + .instance_size = sizeof(NPCM7xxPWMState), | ||
797 | + .class_init = npcm7xx_pwm_class_init, | ||
798 | + .instance_init = npcm7xx_pwm_init, | ||
799 | +}; | ||
800 | + | ||
801 | +static void npcm7xx_pwm_register_type(void) | ||
802 | +{ | ||
803 | + type_register_static(&npcm7xx_pwm_info); | ||
804 | +} | ||
805 | +type_init(npcm7xx_pwm_register_type); | ||
806 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
807 | index XXXXXXX..XXXXXXX 100644 | ||
808 | --- a/hw/misc/meson.build | ||
809 | +++ b/hw/misc/meson.build | ||
810 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c')) | ||
811 | softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( | ||
812 | 'npcm7xx_clk.c', | ||
813 | 'npcm7xx_gcr.c', | ||
814 | + 'npcm7xx_pwm.c', | ||
815 | 'npcm7xx_rng.c', | ||
816 | )) | ||
817 | softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files( | ||
818 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
819 | index XXXXXXX..XXXXXXX 100644 | ||
820 | --- a/hw/misc/trace-events | ||
821 | +++ b/hw/misc/trace-events | ||
822 | @@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu | ||
823 | npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | ||
824 | npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | ||
825 | |||
826 | +# npcm7xx_pwm.c | ||
827 | +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | ||
828 | +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | ||
829 | +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" | ||
830 | +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" | ||
831 | + | ||
832 | # stm32f4xx_syscfg.c | ||
833 | stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" | ||
834 | stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" | ||
355 | -- | 835 | -- |
356 | 2.20.1 | 836 | 2.20.1 |
357 | 837 | ||
358 | 838 | diff view generated by jsdifflib |
1 | Add support for running the Coverity Scan tools inside a Docker | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | container rather than directly on the host system. | ||
3 | 2 | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 3 | We add a qtest for the PWM in the previous patch. It proves it works as |
4 | expected. | ||
5 | |||
6 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
7 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
8 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20210108190945.949196-6-wuhaotsh@google.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Message-id: 20200319193323.2038-7-peter.maydell@linaro.org | ||
7 | --- | 12 | --- |
8 | scripts/coverity-scan/coverity-scan.docker | 131 +++++++++++++++++++++ | 13 | tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++ |
9 | scripts/coverity-scan/run-coverity-scan | 90 ++++++++++++++ | 14 | tests/qtest/meson.build | 1 + |
10 | 2 files changed, 221 insertions(+) | 15 | 2 files changed, 491 insertions(+) |
11 | create mode 100644 scripts/coverity-scan/coverity-scan.docker | 16 | create mode 100644 tests/qtest/npcm7xx_pwm-test.c |
12 | 17 | ||
13 | diff --git a/scripts/coverity-scan/coverity-scan.docker b/scripts/coverity-scan/coverity-scan.docker | 18 | diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c |
14 | new file mode 100644 | 19 | new file mode 100644 |
15 | index XXXXXXX..XXXXXXX | 20 | index XXXXXXX..XXXXXXX |
16 | --- /dev/null | 21 | --- /dev/null |
17 | +++ b/scripts/coverity-scan/coverity-scan.docker | 22 | +++ b/tests/qtest/npcm7xx_pwm-test.c |
18 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ |
19 | +# syntax=docker/dockerfile:1.0.0-experimental | 24 | +/* |
20 | +# | 25 | + * QTests for Nuvoton NPCM7xx PWM Modules. |
21 | +# Docker setup for running the "Coverity Scan" tools over the source | 26 | + * |
22 | +# tree and uploading them to the website, as per | 27 | + * Copyright 2020 Google LLC |
23 | +# https://scan.coverity.com/projects/qemu/builds/new | 28 | + * |
24 | +# We do this on a fixed config (currently Fedora 30 with a known | 29 | + * This program is free software; you can redistribute it and/or modify it |
25 | +# set of dependencies and a configure command that enables a specific | 30 | + * under the terms of the GNU General Public License as published by the |
26 | +# set of options) so that random changes don't result in our accidentally | 31 | + * Free Software Foundation; either version 2 of the License, or |
27 | +# dropping some files from the scan. | 32 | + * (at your option) any later version. |
28 | +# | 33 | + * |
29 | +# We don't build on top of the fedora.docker file because we don't | 34 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
30 | +# want to accidentally change or break the scan config when that | 35 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
31 | +# is updated. | 36 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
32 | + | 37 | + * for more details. |
33 | +# The work of actually doing the build is handled by the | 38 | + */ |
34 | +# run-coverity-scan script. | 39 | + |
35 | + | 40 | +#include "qemu/osdep.h" |
36 | +FROM fedora:30 | 41 | +#include "qemu/bitops.h" |
37 | +ENV PACKAGES \ | 42 | +#include "libqos/libqtest.h" |
38 | + alsa-lib-devel \ | 43 | +#include "qapi/qmp/qdict.h" |
39 | + bc \ | 44 | +#include "qapi/qmp/qnum.h" |
40 | + bison \ | 45 | + |
41 | + brlapi-devel \ | 46 | +#define REF_HZ 25000000 |
42 | + bzip2 \ | 47 | + |
43 | + bzip2-devel \ | 48 | +/* Register field definitions. */ |
44 | + ccache \ | 49 | +#define CH_EN BIT(0) |
45 | + clang \ | 50 | +#define CH_INV BIT(2) |
46 | + curl \ | 51 | +#define CH_MOD BIT(3) |
47 | + cyrus-sasl-devel \ | 52 | + |
48 | + dbus-daemon \ | 53 | +/* Registers shared between all PWMs in a module */ |
49 | + device-mapper-multipath-devel \ | 54 | +#define PPR 0x00 |
50 | + findutils \ | 55 | +#define CSR 0x04 |
51 | + flex \ | 56 | +#define PCR 0x08 |
52 | + gcc \ | 57 | +#define PIER 0x3c |
53 | + gcc-c++ \ | 58 | +#define PIIR 0x40 |
54 | + gettext \ | 59 | + |
55 | + git \ | 60 | +/* CLK module related */ |
56 | + glib2-devel \ | 61 | +#define CLK_BA 0xf0801000 |
57 | + glusterfs-api-devel \ | 62 | +#define CLKSEL 0x04 |
58 | + gnutls-devel \ | 63 | +#define CLKDIV1 0x08 |
59 | + gtk3-devel \ | 64 | +#define CLKDIV2 0x2c |
60 | + hostname \ | 65 | +#define PLLCON0 0x0c |
61 | + libaio-devel \ | 66 | +#define PLLCON1 0x10 |
62 | + libasan \ | 67 | +#define PLL_INDV(rv) extract32((rv), 0, 6) |
63 | + libattr-devel \ | 68 | +#define PLL_FBDV(rv) extract32((rv), 16, 12) |
64 | + libblockdev-mpath-devel \ | 69 | +#define PLL_OTDV1(rv) extract32((rv), 8, 3) |
65 | + libcap-devel \ | 70 | +#define PLL_OTDV2(rv) extract32((rv), 13, 3) |
66 | + libcap-ng-devel \ | 71 | +#define APB3CKDIV(rv) extract32((rv), 28, 2) |
67 | + libcurl-devel \ | 72 | +#define CLK2CKDIV(rv) extract32((rv), 0, 1) |
68 | + libepoxy-devel \ | 73 | +#define CLK4CKDIV(rv) extract32((rv), 26, 2) |
69 | + libfdt-devel \ | 74 | +#define CPUCKSEL(rv) extract32((rv), 0, 2) |
70 | + libgbm-devel \ | 75 | + |
71 | + libiscsi-devel \ | 76 | +#define MAX_DUTY 1000000 |
72 | + libjpeg-devel \ | 77 | + |
73 | + libpmem-devel \ | 78 | +typedef struct PWMModule { |
74 | + libnfs-devel \ | 79 | + int irq; |
75 | + libpng-devel \ | 80 | + uint64_t base_addr; |
76 | + librbd-devel \ | 81 | +} PWMModule; |
77 | + libseccomp-devel \ | 82 | + |
78 | + libssh-devel \ | 83 | +typedef struct PWM { |
79 | + libubsan \ | 84 | + uint32_t cnr_offset; |
80 | + libudev-devel \ | 85 | + uint32_t cmr_offset; |
81 | + libusbx-devel \ | 86 | + uint32_t pdr_offset; |
82 | + libxml2-devel \ | 87 | + uint32_t pwdr_offset; |
83 | + libzstd-devel \ | 88 | +} PWM; |
84 | + llvm \ | 89 | + |
85 | + lzo-devel \ | 90 | +typedef struct TestData { |
86 | + make \ | 91 | + const PWMModule *module; |
87 | + mingw32-bzip2 \ | 92 | + const PWM *pwm; |
88 | + mingw32-curl \ | 93 | +} TestData; |
89 | + mingw32-glib2 \ | 94 | + |
90 | + mingw32-gmp \ | 95 | +static const PWMModule pwm_module_list[] = { |
91 | + mingw32-gnutls \ | 96 | + { |
92 | + mingw32-gtk3 \ | 97 | + .irq = 93, |
93 | + mingw32-libjpeg-turbo \ | 98 | + .base_addr = 0xf0103000 |
94 | + mingw32-libpng \ | 99 | + }, |
95 | + mingw32-libtasn1 \ | 100 | + { |
96 | + mingw32-nettle \ | 101 | + .irq = 94, |
97 | + mingw32-nsis \ | 102 | + .base_addr = 0xf0104000 |
98 | + mingw32-pixman \ | 103 | + } |
99 | + mingw32-pkg-config \ | 104 | +}; |
100 | + mingw32-SDL2 \ | 105 | + |
101 | + mingw64-bzip2 \ | 106 | +static const PWM pwm_list[] = { |
102 | + mingw64-curl \ | 107 | + { |
103 | + mingw64-glib2 \ | 108 | + .cnr_offset = 0x0c, |
104 | + mingw64-gmp \ | 109 | + .cmr_offset = 0x10, |
105 | + mingw64-gnutls \ | 110 | + .pdr_offset = 0x14, |
106 | + mingw64-gtk3 \ | 111 | + .pwdr_offset = 0x44, |
107 | + mingw64-libjpeg-turbo \ | 112 | + }, |
108 | + mingw64-libpng \ | 113 | + { |
109 | + mingw64-libtasn1 \ | 114 | + .cnr_offset = 0x18, |
110 | + mingw64-nettle \ | 115 | + .cmr_offset = 0x1c, |
111 | + mingw64-pixman \ | 116 | + .pdr_offset = 0x20, |
112 | + mingw64-pkg-config \ | 117 | + .pwdr_offset = 0x48, |
113 | + mingw64-SDL2 \ | 118 | + }, |
114 | + ncurses-devel \ | 119 | + { |
115 | + nettle-devel \ | 120 | + .cnr_offset = 0x24, |
116 | + nss-devel \ | 121 | + .cmr_offset = 0x28, |
117 | + numactl-devel \ | 122 | + .pdr_offset = 0x2c, |
118 | + perl \ | 123 | + .pwdr_offset = 0x4c, |
119 | + perl-Test-Harness \ | 124 | + }, |
120 | + pixman-devel \ | 125 | + { |
121 | + pulseaudio-libs-devel \ | 126 | + .cnr_offset = 0x30, |
122 | + python3 \ | 127 | + .cmr_offset = 0x34, |
123 | + python3-sphinx \ | 128 | + .pdr_offset = 0x38, |
124 | + PyYAML \ | 129 | + .pwdr_offset = 0x50, |
125 | + rdma-core-devel \ | 130 | + }, |
126 | + SDL2-devel \ | 131 | +}; |
127 | + snappy-devel \ | 132 | + |
128 | + sparse \ | 133 | +static const int ppr_base[] = { 0, 0, 8, 8 }; |
129 | + spice-server-devel \ | 134 | +static const int csr_base[] = { 0, 4, 8, 12 }; |
130 | + systemd-devel \ | 135 | +static const int pcr_base[] = { 0, 8, 12, 16 }; |
131 | + systemtap-sdt-devel \ | 136 | + |
132 | + tar \ | 137 | +static const uint32_t ppr_list[] = { |
133 | + texinfo \ | 138 | + 0, |
134 | + usbredir-devel \ | 139 | + 1, |
135 | + virglrenderer-devel \ | 140 | + 10, |
136 | + vte291-devel \ | 141 | + 100, |
137 | + wget \ | 142 | + 255, /* Max possible value. */ |
138 | + which \ | 143 | +}; |
139 | + xen-devel \ | 144 | + |
140 | + xfsprogs-devel \ | 145 | +static const uint32_t csr_list[] = { |
141 | + zlib-devel | 146 | + 0, |
142 | +ENV QEMU_CONFIGURE_OPTS --python=/usr/bin/python3 | 147 | + 1, |
143 | + | 148 | + 2, |
144 | +RUN dnf install -y $PACKAGES | 149 | + 3, |
145 | +RUN rpm -q $PACKAGES | sort > /packages.txt | 150 | + 4, /* Max possible value. */ |
146 | +ENV PATH $PATH:/usr/libexec/python3-sphinx/ | 151 | +}; |
147 | +ENV COVERITY_TOOL_BASE=/coverity-tools | 152 | + |
148 | +COPY run-coverity-scan run-coverity-scan | 153 | +static const uint32_t cnr_list[] = { |
149 | +RUN --mount=type=secret,id=coverity.token,required ./run-coverity-scan --update-tools-only --tokenfile /run/secrets/coverity.token | 154 | + 0, |
150 | diff --git a/scripts/coverity-scan/run-coverity-scan b/scripts/coverity-scan/run-coverity-scan | 155 | + 1, |
151 | index XXXXXXX..XXXXXXX 100755 | 156 | + 50, |
152 | --- a/scripts/coverity-scan/run-coverity-scan | 157 | + 100, |
153 | +++ b/scripts/coverity-scan/run-coverity-scan | 158 | + 150, |
154 | @@ -XXX,XX +XXX,XX @@ | 159 | + 200, |
155 | 160 | + 1000, | |
156 | # Command line options: | 161 | + 10000, |
157 | # --dry-run : run the tools, but don't actually do the upload | 162 | + 65535, /* Max possible value. */ |
158 | +# --docker : create and work inside a docker container | 163 | +}; |
159 | # --update-tools-only : update the cached copy of the tools, but don't run them | 164 | + |
160 | # --tokenfile : file to read Coverity token from | 165 | +static const uint32_t cmr_list[] = { |
161 | # --version ver : specify version being analyzed (default: ask git) | 166 | + 0, |
162 | @@ -XXX,XX +XXX,XX @@ | 167 | + 1, |
163 | # --srcdir : QEMU source tree to analyze (default: current working dir) | 168 | + 10, |
164 | # --results-tarball : path to copy the results tarball to (default: don't | 169 | + 50, |
165 | # copy it anywhere, just upload it) | 170 | + 100, |
166 | +# --src-tarball : tarball to untar into src dir (default: none); this | 171 | + 150, |
167 | +# is intended mainly for internal use by the Docker support | 172 | + 200, |
168 | # | 173 | + 1000, |
169 | # User-specifiable environment variables: | 174 | + 10000, |
170 | # COVERITY_TOKEN -- Coverity token | 175 | + 65535, /* Max possible value. */ |
171 | @@ -XXX,XX +XXX,XX @@ update_coverity_tools () { | 176 | +}; |
172 | # Check user-provided environment variables and arguments | 177 | + |
173 | DRYRUN=no | 178 | +/* Returns the index of the PWM module. */ |
174 | UPDATE_ONLY=no | 179 | +static int pwm_module_index(const PWMModule *module) |
175 | +DOCKER=no | 180 | +{ |
176 | 181 | + ptrdiff_t diff = module - pwm_module_list; | |
177 | while [ "$#" -ge 1 ]; do | 182 | + |
178 | case "$1" in | 183 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list)); |
179 | @@ -XXX,XX +XXX,XX @@ while [ "$#" -ge 1 ]; do | 184 | + |
180 | RESULTSTARBALL="$1" | 185 | + return diff; |
181 | shift | 186 | +} |
182 | ;; | 187 | + |
183 | + --src-tarball) | 188 | +/* Returns the index of the PWM entry. */ |
184 | + shift | 189 | +static int pwm_index(const PWM *pwm) |
185 | + if [ $# -eq 0 ]; then | 190 | +{ |
186 | + echo "--src-tarball needs an argument" | 191 | + ptrdiff_t diff = pwm - pwm_list; |
187 | + exit 1 | 192 | + |
188 | + fi | 193 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list)); |
189 | + SRCTARBALL="$1" | 194 | + |
190 | + shift | 195 | + return diff; |
191 | + ;; | 196 | +} |
192 | + --docker) | 197 | + |
193 | + DOCKER=yes | 198 | +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name) |
194 | + shift | 199 | +{ |
195 | + ;; | 200 | + QDict *response; |
196 | *) | 201 | + |
197 | echo "Unexpected argument '$1'" | 202 | + g_test_message("Getting properties %s from %s", name, path); |
198 | exit 1 | 203 | + response = qtest_qmp(qts, "{ 'execute': 'qom-get'," |
199 | @@ -XXX,XX +XXX,XX @@ PROJTOKEN="$COVERITY_TOKEN" | 204 | + " 'arguments': { 'path': %s, 'property': %s}}", |
200 | PROJNAME=QEMU | 205 | + path, name); |
201 | TARBALL=cov-int.tar.xz | 206 | + /* The qom set message returns successfully. */ |
202 | 207 | + g_assert_true(qdict_haskey(response, "return")); | |
203 | +if [ "$UPDATE_ONLY" = yes ] && [ "$DOCKER" = yes ]; then | 208 | + return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return"))); |
204 | + echo "Combining --docker and --update-only is not supported" | 209 | +} |
205 | + exit 1 | 210 | + |
206 | +fi | 211 | +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index) |
207 | 212 | +{ | |
208 | if [ "$UPDATE_ONLY" = yes ]; then | 213 | + char path[100]; |
209 | # Just do the tools update; we don't need to check whether | 214 | + char name[100]; |
210 | @@ -XXX,XX +XXX,XX @@ if [ "$UPDATE_ONLY" = yes ]; then | 215 | + |
211 | exit 0 | 216 | + sprintf(path, "/machine/soc/pwm[%d]", module_index); |
212 | fi | 217 | + sprintf(name, "freq[%d]", pwm_index); |
213 | 218 | + | |
214 | +if [ ! -e "$SRCDIR" ]; then | 219 | + return pwm_qom_get(qts, path, name); |
215 | + mkdir "$SRCDIR" | 220 | +} |
216 | +fi | 221 | + |
217 | + | 222 | +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index) |
218 | cd "$SRCDIR" | 223 | +{ |
219 | 224 | + char path[100]; | |
220 | +if [ ! -z "$SRCTARBALL" ]; then | 225 | + char name[100]; |
221 | + echo "Untarring source tarball into $SRCDIR..." | 226 | + |
222 | + tar xvf "$SRCTARBALL" | 227 | + sprintf(path, "/machine/soc/pwm[%d]", module_index); |
223 | +fi | 228 | + sprintf(name, "duty[%d]", pwm_index); |
224 | + | 229 | + |
225 | echo "Checking this is a QEMU source tree..." | 230 | + return pwm_qom_get(qts, path, name); |
226 | if ! [ -e "$SRCDIR/VERSION" ]; then | 231 | +} |
227 | echo "Not in a QEMU source tree?" | 232 | + |
228 | @@ -XXX,XX +XXX,XX @@ if [ -z "$COVERITY_EMAIL" ]; then | 233 | +static uint32_t get_pll(uint32_t con) |
229 | COVERITY_EMAIL="$(git config user.email)" | 234 | +{ |
230 | fi | 235 | + return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con) |
231 | 236 | + * PLL_OTDV2(con)); | |
232 | +# Run ourselves inside docker if that's what the user wants | 237 | +} |
233 | +if [ "$DOCKER" = yes ]; then | 238 | + |
234 | + # build docker container including the coverity-scan tools | 239 | +static uint64_t read_pclk(QTestState *qts) |
235 | + # Put the Coverity token into a temporary file that only | 240 | +{ |
236 | + # we have read access to, and then pass it to docker build | 241 | + uint64_t freq = REF_HZ; |
237 | + # using --secret. This requires at least Docker 18.09. | 242 | + uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); |
238 | + # Mostly what we are trying to do here is ensure we don't leak | 243 | + uint32_t pllcon; |
239 | + # the token into the Docker image. | 244 | + uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1); |
240 | + umask 077 | 245 | + uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2); |
241 | + SECRETDIR=$(mktemp -d) | 246 | + |
242 | + if [ -z "$SECRETDIR" ]; then | 247 | + switch (CPUCKSEL(clksel)) { |
243 | + echo "Failed to create temporary directory" | 248 | + case 0: |
244 | + exit 1 | 249 | + pllcon = qtest_readl(qts, CLK_BA + PLLCON0); |
245 | + fi | 250 | + freq = get_pll(pllcon); |
246 | + trap 'rm -rf "$SECRETDIR"' INT TERM EXIT | 251 | + break; |
247 | + echo "Created temporary directory $SECRETDIR" | 252 | + case 1: |
248 | + SECRET="$SECRETDIR/token" | 253 | + pllcon = qtest_readl(qts, CLK_BA + PLLCON1); |
249 | + echo "$COVERITY_TOKEN" > "$SECRET" | 254 | + freq = get_pll(pllcon); |
250 | + echo "Building docker container..." | 255 | + break; |
251 | + # TODO: This re-downloads the tools every time, rather than | 256 | + case 2: |
252 | + # caching and reusing the image produced with the downloaded tools. | 257 | + break; |
253 | + # Not sure why. | 258 | + case 3: |
254 | + # TODO: how do you get 'docker build' to print the output of the | 259 | + break; |
255 | + # commands it is running to its stdout? This would be useful for debug. | 260 | + default: |
256 | + DOCKER_BUILDKIT=1 docker build -t coverity-scanner \ | 261 | + g_assert_not_reached(); |
257 | + --secret id=coverity.token,src="$SECRET" \ | 262 | + } |
258 | + -f scripts/coverity-scan/coverity-scan.docker \ | 263 | + |
259 | + scripts/coverity-scan | 264 | + freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2)); |
260 | + echo "Archiving sources to be analyzed..." | 265 | + |
261 | + ./scripts/archive-source.sh "$SECRETDIR/qemu-sources.tgz" | 266 | + return freq; |
262 | + if [ "$DRYRUN" = yes ]; then | 267 | +} |
263 | + DRYRUNARG=--dry-run | 268 | + |
264 | + fi | 269 | +static uint32_t pwm_selector(uint32_t csr) |
265 | + echo "Running scanner..." | 270 | +{ |
266 | + # If we need to capture the output tarball, get the inner run to | 271 | + switch (csr) { |
267 | + # save it to the secrets directory so we can copy it out before the | 272 | + case 0: |
268 | + # directory is cleaned up. | 273 | + return 2; |
269 | + if [ ! -z "$RESULTSTARBALL" ]; then | 274 | + case 1: |
270 | + RTARGS="--results-tarball /work/cov-int.tar.xz" | 275 | + return 4; |
271 | + else | 276 | + case 2: |
272 | + RTARGS="" | 277 | + return 8; |
273 | + fi | 278 | + case 3: |
274 | + # Arrange for this docker run to get access to the sources with -v. | 279 | + return 16; |
275 | + # We pass through all the configuration from the outer script to the inner. | 280 | + case 4: |
276 | + export COVERITY_EMAIL COVERITY_BUILD_CMD | 281 | + return 1; |
277 | + docker run -it --env COVERITY_EMAIL --env COVERITY_BUILD_CMD \ | 282 | + default: |
278 | + -v "$SECRETDIR:/work" coverity-scanner \ | 283 | + g_assert_not_reached(); |
279 | + ./run-coverity-scan --version "$VERSION" \ | 284 | + } |
280 | + --description "$DESCRIPTION" $DRYRUNARG --tokenfile /work/token \ | 285 | +} |
281 | + --srcdir /qemu --src-tarball /work/qemu-sources.tgz $RTARGS | 286 | + |
282 | + if [ ! -z "$RESULTSTARBALL" ]; then | 287 | +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, |
283 | + echo "Copying results tarball to $RESULTSTARBALL..." | 288 | + uint32_t cnr) |
284 | + cp "$SECRETDIR/cov-int.tar.xz" "$RESULTSTARBALL" | 289 | +{ |
285 | + fi | 290 | + return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1)); |
286 | + echo "Docker work complete." | 291 | +} |
287 | + exit 0 | 292 | + |
288 | +fi | 293 | +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) |
289 | + | 294 | +{ |
290 | +# Otherwise, continue with the full build and upload process. | 295 | + uint64_t duty; |
291 | + | 296 | + |
292 | check_upload_permissions | 297 | + if (cnr == 0) { |
293 | 298 | + /* PWM is stopped. */ | |
294 | update_coverity_tools | 299 | + duty = 0; |
300 | + } else if (cmr >= cnr) { | ||
301 | + duty = MAX_DUTY; | ||
302 | + } else { | ||
303 | + duty = MAX_DUTY * (cmr + 1) / (cnr + 1); | ||
304 | + } | ||
305 | + | ||
306 | + if (inverted) { | ||
307 | + duty = MAX_DUTY - duty; | ||
308 | + } | ||
309 | + | ||
310 | + return duty; | ||
311 | +} | ||
312 | + | ||
313 | +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset) | ||
314 | +{ | ||
315 | + return qtest_readl(qts, td->module->base_addr + offset); | ||
316 | +} | ||
317 | + | ||
318 | +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset, | ||
319 | + uint32_t value) | ||
320 | +{ | ||
321 | + qtest_writel(qts, td->module->base_addr + offset, value); | ||
322 | +} | ||
323 | + | ||
324 | +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td) | ||
325 | +{ | ||
326 | + return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8); | ||
327 | +} | ||
328 | + | ||
329 | +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value) | ||
330 | +{ | ||
331 | + pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]); | ||
332 | +} | ||
333 | + | ||
334 | +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td) | ||
335 | +{ | ||
336 | + return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3); | ||
337 | +} | ||
338 | + | ||
339 | +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value) | ||
340 | +{ | ||
341 | + pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]); | ||
342 | +} | ||
343 | + | ||
344 | +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td) | ||
345 | +{ | ||
346 | + return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4); | ||
347 | +} | ||
348 | + | ||
349 | +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value) | ||
350 | +{ | ||
351 | + pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]); | ||
352 | +} | ||
353 | + | ||
354 | +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td) | ||
355 | +{ | ||
356 | + return pwm_read(qts, td, td->pwm->cnr_offset); | ||
357 | +} | ||
358 | + | ||
359 | +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value) | ||
360 | +{ | ||
361 | + pwm_write(qts, td, td->pwm->cnr_offset, value); | ||
362 | +} | ||
363 | + | ||
364 | +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td) | ||
365 | +{ | ||
366 | + return pwm_read(qts, td, td->pwm->cmr_offset); | ||
367 | +} | ||
368 | + | ||
369 | +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value) | ||
370 | +{ | ||
371 | + pwm_write(qts, td, td->pwm->cmr_offset, value); | ||
372 | +} | ||
373 | + | ||
374 | +/* Check pwm registers can be reset to default value */ | ||
375 | +static void test_init(gconstpointer test_data) | ||
376 | +{ | ||
377 | + const TestData *td = test_data; | ||
378 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
379 | + int module = pwm_module_index(td->module); | ||
380 | + int pwm = pwm_index(td->pwm); | ||
381 | + | ||
382 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); | ||
383 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); | ||
384 | + | ||
385 | + qtest_quit(qts); | ||
386 | +} | ||
387 | + | ||
388 | +/* One-shot mode should not change frequency and duty cycle. */ | ||
389 | +static void test_oneshot(gconstpointer test_data) | ||
390 | +{ | ||
391 | + const TestData *td = test_data; | ||
392 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
393 | + int module = pwm_module_index(td->module); | ||
394 | + int pwm = pwm_index(td->pwm); | ||
395 | + uint32_t ppr, csr, pcr; | ||
396 | + int i, j; | ||
397 | + | ||
398 | + pcr = CH_EN; | ||
399 | + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { | ||
400 | + ppr = ppr_list[i]; | ||
401 | + pwm_write_ppr(qts, td, ppr); | ||
402 | + | ||
403 | + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { | ||
404 | + csr = csr_list[j]; | ||
405 | + pwm_write_csr(qts, td, csr); | ||
406 | + pwm_write_pcr(qts, td, pcr); | ||
407 | + | ||
408 | + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); | ||
409 | + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); | ||
410 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); | ||
411 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); | ||
412 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); | ||
413 | + } | ||
414 | + } | ||
415 | + | ||
416 | + qtest_quit(qts); | ||
417 | +} | ||
418 | + | ||
419 | +/* In toggle mode, the PWM generates correct outputs. */ | ||
420 | +static void test_toggle(gconstpointer test_data) | ||
421 | +{ | ||
422 | + const TestData *td = test_data; | ||
423 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
424 | + int module = pwm_module_index(td->module); | ||
425 | + int pwm = pwm_index(td->pwm); | ||
426 | + uint32_t ppr, csr, pcr, cnr, cmr; | ||
427 | + int i, j, k, l; | ||
428 | + uint64_t expected_freq, expected_duty; | ||
429 | + | ||
430 | + pcr = CH_EN | CH_MOD; | ||
431 | + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { | ||
432 | + ppr = ppr_list[i]; | ||
433 | + pwm_write_ppr(qts, td, ppr); | ||
434 | + | ||
435 | + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { | ||
436 | + csr = csr_list[j]; | ||
437 | + pwm_write_csr(qts, td, csr); | ||
438 | + | ||
439 | + for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) { | ||
440 | + cnr = cnr_list[k]; | ||
441 | + pwm_write_cnr(qts, td, cnr); | ||
442 | + | ||
443 | + for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) { | ||
444 | + cmr = cmr_list[l]; | ||
445 | + pwm_write_cmr(qts, td, cmr); | ||
446 | + expected_freq = pwm_compute_freq(qts, ppr, csr, cnr); | ||
447 | + expected_duty = pwm_compute_duty(cnr, cmr, false); | ||
448 | + | ||
449 | + pwm_write_pcr(qts, td, pcr); | ||
450 | + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); | ||
451 | + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); | ||
452 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); | ||
453 | + g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr); | ||
454 | + g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr); | ||
455 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), | ||
456 | + ==, expected_duty); | ||
457 | + if (expected_duty != 0 && expected_duty != 100) { | ||
458 | + /* Duty cycle with 0 or 100 doesn't need frequency. */ | ||
459 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), | ||
460 | + ==, expected_freq); | ||
461 | + } | ||
462 | + | ||
463 | + /* Test inverted mode */ | ||
464 | + expected_duty = pwm_compute_duty(cnr, cmr, true); | ||
465 | + pwm_write_pcr(qts, td, pcr | CH_INV); | ||
466 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV); | ||
467 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), | ||
468 | + ==, expected_duty); | ||
469 | + if (expected_duty != 0 && expected_duty != 100) { | ||
470 | + /* Duty cycle with 0 or 100 doesn't need frequency. */ | ||
471 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), | ||
472 | + ==, expected_freq); | ||
473 | + } | ||
474 | + | ||
475 | + } | ||
476 | + } | ||
477 | + } | ||
478 | + } | ||
479 | + | ||
480 | + qtest_quit(qts); | ||
481 | +} | ||
482 | + | ||
483 | +static void pwm_add_test(const char *name, const TestData* td, | ||
484 | + GTestDataFunc fn) | ||
485 | +{ | ||
486 | + g_autofree char *full_name = g_strdup_printf( | ||
487 | + "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module), | ||
488 | + pwm_index(td->pwm), name); | ||
489 | + qtest_add_data_func(full_name, td, fn); | ||
490 | +} | ||
491 | +#define add_test(name, td) pwm_add_test(#name, td, test_##name) | ||
492 | + | ||
493 | +int main(int argc, char **argv) | ||
494 | +{ | ||
495 | + TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)]; | ||
496 | + | ||
497 | + g_test_init(&argc, &argv, NULL); | ||
498 | + | ||
499 | + for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) { | ||
500 | + for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) { | ||
501 | + TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j]; | ||
502 | + | ||
503 | + td->module = &pwm_module_list[i]; | ||
504 | + td->pwm = &pwm_list[j]; | ||
505 | + | ||
506 | + add_test(init, td); | ||
507 | + add_test(oneshot, td); | ||
508 | + add_test(toggle, td); | ||
509 | + } | ||
510 | + } | ||
511 | + | ||
512 | + return g_test_run(); | ||
513 | +} | ||
514 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
515 | index XXXXXXX..XXXXXXX 100644 | ||
516 | --- a/tests/qtest/meson.build | ||
517 | +++ b/tests/qtest/meson.build | ||
518 | @@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \ | ||
519 | qtests_npcm7xx = \ | ||
520 | ['npcm7xx_adc-test', | ||
521 | 'npcm7xx_gpio-test', | ||
522 | + 'npcm7xx_pwm-test', | ||
523 | 'npcm7xx_rng-test', | ||
524 | 'npcm7xx_timer-test', | ||
525 | 'npcm7xx_watchdog_timer-test'] | ||
295 | -- | 526 | -- |
296 | 2.20.1 | 527 | 2.20.1 |
297 | 528 | ||
298 | 529 | diff view generated by jsdifflib |
1 | If we are not making warnings fatal for compilation, make them | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | non-fatal when building the Sphinx documentation also. (For instance | ||
3 | Sphinx 3.0 warns about some constructs that older versions were happy | ||
4 | with, which is a build failure if we use the warnings-as-errors | ||
5 | flag.) | ||
6 | 2 | ||
7 | This provides a workaround at least for LP:1872113. | 3 | A device shouldn't access its parent object which is QOM internal. |
4 | Instead it should use type cast for this purporse. This patch fixes this | ||
5 | issue for all NPCM7XX Devices. | ||
8 | 6 | ||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20210108190945.949196-7-wuhaotsh@google.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20200411182934.28678-2-peter.maydell@linaro.org | ||
12 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
13 | --- | 11 | --- |
14 | configure | 9 ++++++++- | 12 | hw/arm/npcm7xx_boards.c | 2 +- |
15 | Makefile | 2 +- | 13 | hw/mem/npcm7xx_mc.c | 2 +- |
16 | 2 files changed, 9 insertions(+), 2 deletions(-) | 14 | hw/misc/npcm7xx_clk.c | 2 +- |
15 | hw/misc/npcm7xx_gcr.c | 2 +- | ||
16 | hw/misc/npcm7xx_rng.c | 2 +- | ||
17 | hw/nvram/npcm7xx_otp.c | 2 +- | ||
18 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
19 | 7 files changed, 7 insertions(+), 7 deletions(-) | ||
17 | 20 | ||
18 | diff --git a/configure b/configure | 21 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c |
19 | index XXXXXXX..XXXXXXX 100755 | 22 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/configure | 23 | --- a/hw/arm/npcm7xx_boards.c |
21 | +++ b/configure | 24 | +++ b/hw/arm/npcm7xx_boards.c |
22 | @@ -XXX,XX +XXX,XX @@ if check_include sys/kcov.h ; then | 25 | @@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, |
23 | kcov=yes | 26 | uint32_t hw_straps) |
24 | fi | 27 | { |
25 | 28 | NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); | |
26 | +# If we're making warnings fatal, apply this to Sphinx runs as well | 29 | - MachineClass *mc = &nmc->parent; |
27 | +sphinx_werror="" | 30 | + MachineClass *mc = MACHINE_CLASS(nmc); |
28 | +if test "$werror" = "yes"; then | 31 | Object *obj; |
29 | + sphinx_werror="-W" | 32 | |
30 | +fi | 33 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { |
31 | + | 34 | diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c |
32 | # Check we have a new enough version of sphinx-build | 35 | index XXXXXXX..XXXXXXX 100644 |
33 | has_sphinx_build() { | 36 | --- a/hw/mem/npcm7xx_mc.c |
34 | # This is a bit awkward but works: create a trivial document and | 37 | +++ b/hw/mem/npcm7xx_mc.c |
35 | @@ -XXX,XX +XXX,XX @@ has_sphinx_build() { | 38 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp) |
36 | # sphinx-build doesn't exist at all or if it is too old. | 39 | |
37 | mkdir -p "$TMPDIR1/sphinx" | 40 | memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs", |
38 | touch "$TMPDIR1/sphinx/index.rst" | 41 | NPCM7XX_MC_REGS_SIZE); |
39 | - "$sphinx_build" -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1 | 42 | - sysbus_init_mmio(&s->parent, &s->mmio); |
40 | + "$sphinx_build" $sphinx_werror -c "$source_path/docs" -b html "$TMPDIR1/sphinx" "$TMPDIR1/sphinx/out" >/dev/null 2>&1 | 43 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); |
41 | } | 44 | } |
42 | 45 | ||
43 | # Check if tools are available to build documentation. | 46 | static void npcm7xx_mc_class_init(ObjectClass *klass, void *data) |
44 | @@ -XXX,XX +XXX,XX @@ echo "INSTALL_PROG=$install -c -m 0755" >> $config_host_mak | 47 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c |
45 | echo "INSTALL_LIB=$install -c -m 0644" >> $config_host_mak | ||
46 | echo "PYTHON=$python" >> $config_host_mak | ||
47 | echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak | ||
48 | +echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak | ||
49 | echo "GENISOIMAGE=$genisoimage" >> $config_host_mak | ||
50 | echo "CC=$cc" >> $config_host_mak | ||
51 | if $iasl -h > /dev/null 2>&1; then | ||
52 | diff --git a/Makefile b/Makefile | ||
53 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
54 | --- a/Makefile | 49 | --- a/hw/misc/npcm7xx_clk.c |
55 | +++ b/Makefile | 50 | +++ b/hw/misc/npcm7xx_clk.c |
56 | @@ -XXX,XX +XXX,XX @@ sphinxdocs: $(MANUAL_BUILDDIR)/devel/index.html \ | 51 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj) |
57 | # Note the use of different doctree for each (manual, builder) tuple; | 52 | |
58 | # this works around Sphinx not handling parallel invocation on | 53 | memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, |
59 | # a single doctree: https://github.com/sphinx-doc/sphinx/issues/2946 | 54 | TYPE_NPCM7XX_CLK, 4 * KiB); |
60 | -build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) -W -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1") | 55 | - sysbus_init_mmio(&s->parent, &s->iomem); |
61 | +build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) $(SPHINX_WERROR) -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1") | 56 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); |
62 | # We assume all RST files in the manual's directory are used in it | 57 | } |
63 | manual-deps = $(wildcard $(SRC_PATH)/docs/$1/*.rst $(SRC_PATH)/docs/$1/*/*.rst) \ | 58 | |
64 | $(SRC_PATH)/docs/defs.rst.inc \ | 59 | static int npcm7xx_clk_post_load(void *opaque, int version_id) |
60 | diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/hw/misc/npcm7xx_gcr.c | ||
63 | +++ b/hw/misc/npcm7xx_gcr.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj) | ||
65 | |||
66 | memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, | ||
67 | TYPE_NPCM7XX_GCR, 4 * KiB); | ||
68 | - sysbus_init_mmio(&s->parent, &s->iomem); | ||
69 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
70 | } | ||
71 | |||
72 | static const VMStateDescription vmstate_npcm7xx_gcr = { | ||
73 | diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/hw/misc/npcm7xx_rng.c | ||
76 | +++ b/hw/misc/npcm7xx_rng.c | ||
77 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj) | ||
78 | |||
79 | memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs", | ||
80 | NPCM7XX_RNG_REGS_SIZE); | ||
81 | - sysbus_init_mmio(&s->parent, &s->iomem); | ||
82 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
83 | } | ||
84 | |||
85 | static const VMStateDescription vmstate_npcm7xx_rng = { | ||
86 | diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/nvram/npcm7xx_otp.c | ||
89 | +++ b/hw/nvram/npcm7xx_otp.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp) | ||
91 | { | ||
92 | NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev); | ||
93 | NPCM7xxOTPState *s = NPCM7XX_OTP(dev); | ||
94 | - SysBusDevice *sbd = &s->parent; | ||
95 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
96 | |||
97 | memset(s->array, 0, sizeof(s->array)); | ||
98 | |||
99 | diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/hw/ssi/npcm7xx_fiu.c | ||
102 | +++ b/hw/ssi/npcm7xx_fiu.c | ||
103 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj) | ||
104 | static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp) | ||
105 | { | ||
106 | NPCM7xxFIUState *s = NPCM7XX_FIU(dev); | ||
107 | - SysBusDevice *sbd = &s->parent; | ||
108 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
109 | int i; | ||
110 | |||
111 | if (s->cs_count <= 0) { | ||
65 | -- | 112 | -- |
66 | 2.20.1 | 113 | 2.20.1 |
67 | 114 | ||
68 | 115 | diff view generated by jsdifflib |
1 | In commit a1a98357e3fd in 2018 we added some workarounds for Coverity | 1 | From: Roman Bolshakov <r.bolshakov@yadro.com> |
---|---|---|---|
2 | not being able to handle the _Float* types introduced by recent | ||
3 | glibc. Newer versions of the Coverity scan tools have support for | ||
4 | these types, and will fail with errors about duplicate typedefs if we | ||
5 | have our workaround. Remove our copy of the typedefs. | ||
6 | 2 | ||
3 | ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead. | ||
4 | [-Wdeprecated-declarations] | ||
5 | if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) { | ||
6 | ^ | ||
7 | /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note: | ||
8 | 'openFile:' has been explicitly marked deprecated here | ||
9 | - (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0)); | ||
10 | ^ | ||
11 | |||
12 | Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200319193323.2038-2-peter.maydell@linaro.org | ||
10 | --- | 16 | --- |
11 | include/qemu/osdep.h | 14 -------------- | 17 | ui/cocoa.m | 5 ++++- |
12 | 1 file changed, 14 deletions(-) | 18 | 1 file changed, 4 insertions(+), 1 deletion(-) |
13 | 19 | ||
14 | diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h | 20 | diff --git a/ui/cocoa.m b/ui/cocoa.m |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/qemu/osdep.h | 22 | --- a/ui/cocoa.m |
17 | +++ b/include/qemu/osdep.h | 23 | +++ b/ui/cocoa.m |
18 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; |
19 | #else | 25 | /* Where to look for local files */ |
20 | #include "exec/poison.h" | 26 | NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"}; |
21 | #endif | 27 | NSString *full_file_path; |
22 | -#ifdef __COVERITY__ | 28 | + NSURL *full_file_url; |
23 | -/* Coverity does not like the new _Float* types that are used by | 29 | |
24 | - * recent glibc, and croaks on every single file that includes | 30 | /* iterate thru the possible paths until the file is found */ |
25 | - * stdlib.h. These typedefs are enough to please it. | 31 | int index; |
26 | - * | 32 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; |
27 | - * Note that these fix parse errors so they cannot be placed in | 33 | full_file_path = [full_file_path stringByDeletingLastPathComponent]; |
28 | - * scripts/coverity-model.c. | 34 | full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path, |
29 | - */ | 35 | path_array[index], filename]; |
30 | -typedef float _Float32; | 36 | - if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) { |
31 | -typedef double _Float32x; | 37 | + full_file_url = [NSURL fileURLWithPath: full_file_path |
32 | -typedef double _Float64; | 38 | + isDirectory: false]; |
33 | -typedef __float80 _Float64x; | 39 | + if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) { |
34 | -typedef __float128 _Float128; | 40 | return; |
35 | -#endif | 41 | } |
36 | 42 | } | |
37 | #include "qemu/compiler.h" | ||
38 | |||
39 | -- | 43 | -- |
40 | 2.20.1 | 44 | 2.20.1 |
41 | 45 | ||
42 | 46 | diff view generated by jsdifflib |