[PULL for-5.0 0/1] tcg patch queue
[PULL v2 00/21] tcg patch queue
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The following changes since commit 17e1e49814096a3daaa8e5a73acd56a0f30bdc18:
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Version 2: Drop signed 32-bit guest patches while CI failure examined.
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Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2020-04-09 19:00:41 +0100)
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The following changes since commit 3d1fbc59665ff8a5d74b0fd30583044fe99e1117:
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Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging (2022-03-04 15:31:23 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/rth7680/qemu.git tags/pull-tcg-20200412
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220304
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for you to fetch changes up to a4e57084c16d5b0eff3651693fba04f26b30b551:
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for you to fetch changes up to cf320769476c3e2820be2a6280bfa1e15baf396f:
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tcg/mips: mips sync* encode error (2020-04-12 14:07:07 -0700)
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tcg/i386: Implement bitsel for avx512 (2022-03-04 08:50:41 -1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Fix tcg/mips barrier encoding
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Reorder do_constant_folding_cond test to satisfy valgrind.
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Fix value of MAX_OPC_PARAM_IARGS.
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Add opcodes for vector nand, nor, eqv.
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Support vector nand, nor, eqv on PPC and S390X hosts.
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Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
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----------------------------------------------------------------
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----------------------------------------------------------------
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lixinyu (1):
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Alex Bennée (1):
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tcg/mips: mips sync* encode error
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tcg/optimize: only read val after const check
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tcg/mips/tcg-target.inc.c | 10 +++++-----
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Richard Henderson (19):
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1 file changed, 5 insertions(+), 5 deletions(-)
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tcg: Add opcodes for vector nand, nor, eqv
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tcg/ppc: Implement vector NAND, NOR, EQV
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tcg/s390x: Implement vector NAND, NOR, EQV
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tcg/i386: Detect AVX512
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tcg/i386: Add tcg_out_evex_opc
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tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
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tcg/i386: Implement avx512 variable shifts
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tcg/i386: Implement avx512 scalar shift
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tcg/i386: Implement avx512 immediate sari shift
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tcg/i386: Implement avx512 immediate rotate
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tcg/i386: Implement avx512 variable rotate
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tcg/i386: Support avx512vbmi2 vector shift-double instructions
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tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
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tcg/i386: Remove rotls_vec from tcg_target_op_def
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tcg/i386: Expand scalar rotate with avx512 insns
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tcg/i386: Implement avx512 min/max/abs
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tcg/i386: Implement avx512 multiply
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tcg/i386: Implement more logical operations for avx512
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tcg/i386: Implement bitsel for avx512
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Ziqiao Kong (1):
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tcg: Set MAX_OPC_PARAM_IARGS to 7
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include/qemu/cpuid.h | 20 ++-
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include/tcg/tcg-opc.h | 3 +
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include/tcg/tcg.h | 5 +-
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tcg/aarch64/tcg-target.h | 3 +
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tcg/arm/tcg-target.h | 3 +
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tcg/i386/tcg-target-con-set.h | 1 +
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tcg/i386/tcg-target.h | 17 +-
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tcg/i386/tcg-target.opc.h | 3 +
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tcg/ppc/tcg-target.h | 3 +
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tcg/s390x/tcg-target.h | 3 +
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tcg/optimize.c | 20 +--
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tcg/tcg-op-vec.c | 27 ++-
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tcg/tcg.c | 6 +
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tcg/i386/tcg-target.c.inc | 387 +++++++++++++++++++++++++++++++++++-------
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tcg/ppc/tcg-target.c.inc | 15 ++
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tcg/s390x/tcg-target.c.inc | 17 ++
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tcg/tci/tcg-target.c.inc | 2 +-
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17 files changed, 441 insertions(+), 94 deletions(-)
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diff view generated by jsdifflib
[PULL for-5.0 1/1] tcg/mips: mips sync* encode error
Deleted patch
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From: lixinyu <precinct@mail.ustc.edu.cn>
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OPC_SYNC_WMB, OPC_SYNC_MB, OPC_SYNC_ACQUIRE, OPC_SYNC_RELEASE and
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OPC_SYNC_RMB have wrong encode. According to the mips manual,
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their encode should be 'OPC_SYNC | 0x?? << 6' rather than
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'OPC_SYNC | 0x?? << 5'. Wrong encode can lead illegal instruction
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errors. These instructions often appear with multi-threaded
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simulation.
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Fixes: 6f0b99104a3 ("tcg/mips: Add support for fence")
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Signed-off-by: lixinyu <precinct@mail.ustc.edu.cn>
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Message-Id: <20200411124612.12560-1-precinct@mail.ustc.edu.cn>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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tcg/mips/tcg-target.inc.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
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index XXXXXXX..XXXXXXX 100644
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--- a/tcg/mips/tcg-target.inc.c
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+++ b/tcg/mips/tcg-target.inc.c
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@@ -XXX,XX +XXX,XX @@ typedef enum {
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/* MIPS r6 introduced names for weaker variants of SYNC. These are
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backward compatible to previous architecture revisions. */
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- OPC_SYNC_WMB = OPC_SYNC | 0x04 << 5,
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- OPC_SYNC_MB = OPC_SYNC | 0x10 << 5,
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- OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 5,
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- OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 5,
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- OPC_SYNC_RMB = OPC_SYNC | 0x13 << 5,
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+ OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
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+ OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
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+ OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
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+ OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
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+ OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
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/* Aliases for convenience. */
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ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
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--
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2.20.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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