[PULL 00/11] target-arm queue
[PULL v2 00/29] target-arm queue
1
A collection of bug fixes for rc2...
1
v2: drop pvpanic-pci patches.
2
2
3
The following changes since commit 146aa0f104bb3bf88e43c4082a0bfc4bbda4fbd8:
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
4
4
5
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2020-04-03 15:30:11 +0100)
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
6
6
7
are available in the Git repository at:
7
are available in the Git repository at:
8
8
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200406
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
10
10
11
for you to fetch changes up to 8893790966d9c964557ad01be4a68ef50696ace8:
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
12
12
13
dma/xlnx-zdma: Reorg to fix CUR_DSCR (2020-04-06 10:59:56 +0100)
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
14
14
15
----------------------------------------------------------------
15
----------------------------------------------------------------
16
target-arm queue:
16
target-arm queue:
17
* don't expose "ieee_half" via gdbstub (prevents gdb crashes or errors
17
* Implement IMPDEF pauth algorithm
18
with older GDB versions)
18
* Support ARMv8.4-SEL2
19
* hw/arm/collie: Put StrongARMState* into a CollieMachineState struct
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
20
* PSTATE.PAN should not clear exec bits
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
21
* hw/gpio/aspeed_gpio.c: Don't directly include assert.h
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
22
(fixes compilation on some Windows build scenarios)
22
* docs: Build and install all the docs in a single manual
23
* dump: Fix writing of ELF section
24
* dma/xlnx-zdma: various bug fixes
25
* target/arm/helperc. delete obsolete TODO comment
26
23
27
----------------------------------------------------------------
24
----------------------------------------------------------------
28
Alex Bennée (1):
25
Gan Qixin (1):
29
target/arm: don't expose "ieee_half" via gdbstub
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
30
27
31
Edgar E. Iglesias (5):
28
Peter Maydell (1):
32
dma/xlnx-zdma: Remove comment
29
docs: Build and install all the docs in a single manual
33
dma/xlnx-zdma: Populate DBG0.CMN_BUF_FREE
34
dma/xlnx-zdma: Clear DMA_DONE when halting
35
dma/xlnx-zdma: Advance the descriptor address when stopping
36
dma/xlnx-zdma: Reorg to fix CUR_DSCR
37
30
38
Peter Maydell (5):
31
Philippe Mathieu-Daudé (1):
39
hw/arm/collie: Put StrongARMState* into a CollieMachineState struct
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
40
target/arm: PSTATE.PAN should not clear exec bits
41
target/arm: Remove obsolete TODO note from get_phys_addr_lpae()
42
hw/gpio/aspeed_gpio.c: Don't directly include assert.h
43
dump: Fix writing of ELF section
44
33
45
dump/dump.c | 2 +-
34
Richard Henderson (7):
46
hw/arm/collie.c | 33 +++++++++++++++++++++++++-----
35
target/arm: Implement an IMPDEF pauth algorithm
47
hw/dma/xlnx-zdma.c | 56 ++++++++++++++++++++++++++-------------------------
36
target/arm: Add cpu properties to control pauth
48
hw/gpio/aspeed_gpio.c | 2 --
37
target/arm: Use object_property_add_bool for "sve" property
49
target/arm/gdbstub.c | 7 ++++++-
38
target/arm: Introduce PREDDESC field definitions
50
target/arm/helper.c | 13 +++++-------
39
target/arm: Update PFIRST, PNEXT for pred_desc
51
6 files changed, 69 insertions(+), 44 deletions(-)
40
target/arm: Update ZIP, UZP, TRN for pred_desc
41
target/arm: Update REV, PUNPK for pred_desc
52
42
43
Rémi Denis-Courmont (19):
44
target/arm: remove redundant tests
45
target/arm: add arm_is_el2_enabled() helper
46
target/arm: use arm_is_el2_enabled() where applicable
47
target/arm: use arm_hcr_el2_eff() where applicable
48
target/arm: factor MDCR_EL2 common handling
49
target/arm: Define isar_feature function to test for presence of SEL2
50
target/arm: add 64-bit S-EL2 to EL exception table
51
target/arm: add MMU stage 1 for Secure EL2
52
target/arm: add ARMv8.4-SEL2 system registers
53
target/arm: handle VMID change in secure state
54
target/arm: do S1_ptw_translate() before address space lookup
55
target/arm: translate NS bit in page-walks
56
target/arm: generalize 2-stage page-walk condition
57
target/arm: secure stage 2 translation regime
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
59
target/arm: revector to run-time pick target EL
60
target/arm: Implement SCR_EL2.EEL2
61
target/arm: enable Secure EL2 in max CPU
62
target/arm: refactor vae1_tlbmask()
63
64
docs/conf.py | 46 ++++-
65
docs/devel/conf.py | 15 --
66
docs/index.html.in | 17 --
67
docs/interop/conf.py | 28 ---
68
docs/meson.build | 64 +++---
69
docs/specs/conf.py | 16 --
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
102
diff view generated by jsdifflib
[PULL 01/11] target/arm: don't expose "ieee_half" via gdbstub
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
While support for parsing ieee_half in the XML description was added
4
to gdb in 2019 (a6d0f249) there is no easy way for the gdbstub to know
5
if the gdb end will understand it. Disable it for now and allow older
6
gdbs to successfully connect to the default -cpu max SVE enabled
7
QEMUs.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200402143913.24005-1-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/gdbstub.c | 7 ++++++-
15
1 file changed, 6 insertions(+), 1 deletion(-)
16
17
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/gdbstub.c
20
+++ b/target/arm/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ static const struct TypeSize vec_lanes[] = {
22
/* 16 bit */
23
{ "uint16", 16, 'h', 'u' },
24
{ "int16", 16, 'h', 's' },
25
- { "ieee_half", 16, 'h', 'f' },
26
+ /*
27
+ * TODO: currently there is no reliable way of telling
28
+ * if the remote gdb actually understands ieee_half so
29
+ * we don't expose it in the target description for now.
30
+ * { "ieee_half", 16, 'h', 'f' },
31
+ */
32
/* bytes */
33
{ "uint8", 8, 'b', 'u' },
34
{ "int8", 8, 'b', 's' },
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
[PULL 02/11] hw/arm/collie: Put StrongARMState* into a CollieMachineState struct
Deleted patch
1
Coverity complains that the collie_init() function leaks the memory
2
allocated in sa1110_init(). This is true but not significant since
3
the function is called only once on machine init and the memory must
4
remain in existence until QEMU exits anyway.
5
1
6
Still, we can avoid the technical memory leak by keeping the pointer
7
to the StrongARMState inside the machine state struct. Switch from
8
the simple DEFINE_MACHINE() style to defining a subclass of
9
TYPE_MACHINE which extends the MachineState struct, and keep the
10
pointer there.
11
12
Fixes: CID 1421921
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20200326204919.22006-1-peter.maydell@linaro.org
17
---
18
hw/arm/collie.c | 33 ++++++++++++++++++++++++++++-----
19
1 file changed, 28 insertions(+), 5 deletions(-)
20
21
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/collie.c
24
+++ b/hw/arm/collie.c
25
@@ -XXX,XX +XXX,XX @@
26
#include "exec/address-spaces.h"
27
#include "cpu.h"
28
29
+typedef struct {
30
+ MachineState parent;
31
+
32
+ StrongARMState *sa1110;
33
+} CollieMachineState;
34
+
35
+#define TYPE_COLLIE_MACHINE MACHINE_TYPE_NAME("collie")
36
+#define COLLIE_MACHINE(obj) \
37
+ OBJECT_CHECK(CollieMachineState, obj, TYPE_COLLIE_MACHINE)
38
+
39
static struct arm_boot_info collie_binfo = {
40
.loader_start = SA_SDCS0,
41
.ram_size = 0x20000000,
42
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info collie_binfo = {
43
44
static void collie_init(MachineState *machine)
45
{
46
- StrongARMState *s;
47
DriveInfo *dinfo;
48
MachineClass *mc = MACHINE_GET_CLASS(machine);
49
+ CollieMachineState *cms = COLLIE_MACHINE(machine);
50
51
if (machine->ram_size != mc->default_ram_size) {
52
char *sz = size_to_str(mc->default_ram_size);
53
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
54
exit(EXIT_FAILURE);
55
}
56
57
- s = sa1110_init(machine->cpu_type);
58
+ cms->sa1110 = sa1110_init(machine->cpu_type);
59
60
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
61
62
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
63
sysbus_create_simple("scoop", 0x40800000, NULL);
64
65
collie_binfo.board_id = 0x208;
66
- arm_load_kernel(s->cpu, machine, &collie_binfo);
67
+ arm_load_kernel(cms->sa1110->cpu, machine, &collie_binfo);
68
}
69
70
-static void collie_machine_init(MachineClass *mc)
71
+static void collie_machine_class_init(ObjectClass *oc, void *data)
72
{
73
+ MachineClass *mc = MACHINE_CLASS(oc);
74
+
75
mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
76
mc->init = collie_init;
77
mc->ignore_memory_transaction_failures = true;
78
@@ -XXX,XX +XXX,XX @@ static void collie_machine_init(MachineClass *mc)
79
mc->default_ram_id = "strongarm.sdram";
80
}
81
82
-DEFINE_MACHINE("collie", collie_machine_init)
83
+static const TypeInfo collie_machine_typeinfo = {
84
+ .name = TYPE_COLLIE_MACHINE,
85
+ .parent = TYPE_MACHINE,
86
+ .class_init = collie_machine_class_init,
87
+ .instance_size = sizeof(CollieMachineState),
88
+};
89
+
90
+static void collie_machine_register_types(void)
91
+{
92
+ type_register_static(&collie_machine_typeinfo);
93
+}
94
+type_init(collie_machine_register_types);
95
--
96
2.20.1
97
98
diff view generated by jsdifflib
[PULL 03/11] target/arm: PSTATE.PAN should not clear exec bits
Deleted patch
1
Our implementation of the PSTATE.PAN bit incorrectly cleared all
2
access permission bits for privileged access to memory which is
3
user-accessible. It should only affect the privileged read and write
4
permissions; execute permission is dealt with via XN/PXN instead.
5
1
6
Fixes: 81636b70c226dc27d7ebc8d
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200330170651.20901-1-peter.maydell@linaro.org
10
---
11
target/arm/helper.c | 6 ++++--
12
1 file changed, 4 insertions(+), 2 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
19
prot_rw = user_rw;
20
} else {
21
if (user_rw && regime_is_pan(env, mmu_idx)) {
22
- return 0;
23
+ /* PAN forbids data accesses but doesn't affect insn fetch */
24
+ prot_rw = 0;
25
+ } else {
26
+ prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
27
}
28
- prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
29
}
30
31
if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
32
--
33
2.20.1
34
35
diff view generated by jsdifflib
[PULL 04/11] target/arm: Remove obsolete TODO note from get_phys_addr_lpae()
Deleted patch
1
An old comment in get_phys_addr_lpae() claims that the code does not
2
support the different format TCR for VTCR_EL2. This used to be true
3
but it is not true now (in particular the aa64_va_parameters() and
4
aa32_va_parameters() functions correctly handle the different
5
register format by checking whether the mmu_idx is Stage2).
6
Remove the out of date parts of the comment.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200331143407.3186-1-peter.maydell@linaro.org
11
---
12
target/arm/helper.c | 7 +------
13
1 file changed, 1 insertion(+), 6 deletions(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
20
bool aarch64 = arm_el_is_aa64(env, el);
21
bool guarded = false;
22
23
- /* TODO:
24
- * This code does not handle the different format TCR for VTCR_EL2.
25
- * This code also does not support shareability levels.
26
- * Attribute and permission bit handling should also be checked when adding
27
- * support for those page table walks.
28
- */
29
+ /* TODO: This code does not support shareability levels. */
30
if (aarch64) {
31
param = aa64_va_parameters(env, address, mmu_idx,
32
access_type != MMU_INST_FETCH);
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
[PULL 05/11] hw/gpio/aspeed_gpio.c: Don't directly include assert.h
Deleted patch
1
Remove a direct include of assert.h -- this is already
2
provided by qemu/osdep.h, and it breaks our rule that the
3
first include must always be osdep.h.
4
1
5
In particular we must get the assert() macro via osdep.h
6
to avoid compile failures on mingw (see the comment in
7
osdep.h where we redefine assert() for that platform).
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20200403124712.24826-1-peter.maydell@linaro.org
13
---
14
hw/gpio/aspeed_gpio.c | 2 --
15
1 file changed, 2 deletions(-)
16
17
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/gpio/aspeed_gpio.c
20
+++ b/hw/gpio/aspeed_gpio.c
21
@@ -XXX,XX +XXX,XX @@
22
* SPDX-License-Identifier: GPL-2.0-or-later
23
*/
24
25
-#include <assert.h>
26
-
27
#include "qemu/osdep.h"
28
#include "qemu/host-utils.h"
29
#include "qemu/log.h"
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
[PULL 06/11] dump: Fix writing of ELF section
Deleted patch
1
In write_elf_section() we set the 'shdr' pointer to point to local
2
structures shdr32 or shdr64, which we fill in to be written out to
3
the ELF dump. Unfortunately the address we pass to fd_write_vmcore()
4
has a spurious '&' operator, so instead of writing out the section
5
header we write out the literal pointer value followed by whatever is
6
on the stack after the 'shdr' local variable.
7
1
8
Pass the correct address into fd_write_vmcore().
9
10
Spotted by Coverity: CID 1421970.
11
12
Cc: qemu-stable@nongnu.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20200324173630.12221-1-peter.maydell@linaro.org
17
---
18
dump/dump.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
20
21
diff --git a/dump/dump.c b/dump/dump.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/dump/dump.c
24
+++ b/dump/dump.c
25
@@ -XXX,XX +XXX,XX @@ static void write_elf_section(DumpState *s, int type, Error **errp)
26
shdr = &shdr64;
27
}
28
29
- ret = fd_write_vmcore(&shdr, shdr_size, s);
30
+ ret = fd_write_vmcore(shdr, shdr_size, s);
31
if (ret < 0) {
32
error_setg_errno(errp, -ret,
33
"dump: failed to write section header table");
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[PULL 07/11] dma/xlnx-zdma: Remove comment
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Remove comment.
4
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Message-id: 20200402134721.27863-2-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/dma/xlnx-zdma.c | 1 -
12
1 file changed, 1 deletion(-)
13
14
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/dma/xlnx-zdma.c
17
+++ b/hw/dma/xlnx-zdma.c
18
@@ -XXX,XX +XXX,XX @@ static void zdma_process_descr(XlnxZDMA *s)
19
zdma_src_done(s);
20
}
21
22
- /* Load next descriptor. */
23
if (ptype == PT_REG || src_cmd == CMD_STOP) {
24
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0);
25
zdma_set_state(s, DISABLED);
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[PULL 08/11] dma/xlnx-zdma: Populate DBG0.CMN_BUF_FREE
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Populate DBG0.CMN_BUF_FREE so that SW can see some free space.
4
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Message-id: 20200402134721.27863-3-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/dma/xlnx-zdma.c | 6 ++++++
12
1 file changed, 6 insertions(+)
13
14
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/dma/xlnx-zdma.c
17
+++ b/hw/dma/xlnx-zdma.c
18
@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo zdma_regs_info[] = {
19
},{ .name = "ZDMA_CH_DBG0", .addr = A_ZDMA_CH_DBG0,
20
.rsvd = 0xfffffe00,
21
.ro = 0x1ff,
22
+
23
+ /*
24
+ * There's SW out there that will check the debug regs for free space.
25
+ * Claim that we always have 0x100 free.
26
+ */
27
+ .reset = 0x100
28
},{ .name = "ZDMA_CH_DBG1", .addr = A_ZDMA_CH_DBG1,
29
.rsvd = 0xfffffe00,
30
.ro = 0x1ff,
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[PULL 09/11] dma/xlnx-zdma: Clear DMA_DONE when halting
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Clear DMA_DONE when halting the DMA channel.
4
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200402134721.27863-4-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/dma/xlnx-zdma.c | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/dma/xlnx-zdma.c
17
+++ b/hw/dma/xlnx-zdma.c
18
@@ -XXX,XX +XXX,XX @@ static void zdma_process_descr(XlnxZDMA *s)
19
if (src_cmd == CMD_HALT) {
20
zdma_set_state(s, PAUSED);
21
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1);
22
+ ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, false);
23
zdma_ch_imr_update_irq(s);
24
return;
25
}
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[PULL 10/11] dma/xlnx-zdma: Advance the descriptor address when stopping
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Advance the descriptor address when stopping the channel.
4
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200402134721.27863-5-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/dma/xlnx-zdma.c | 1 -
12
1 file changed, 1 deletion(-)
13
14
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/dma/xlnx-zdma.c
17
+++ b/hw/dma/xlnx-zdma.c
18
@@ -XXX,XX +XXX,XX @@ static void zdma_process_descr(XlnxZDMA *s)
19
if (ptype == PT_REG || src_cmd == CMD_STOP) {
20
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0);
21
zdma_set_state(s, DISABLED);
22
- return;
23
}
24
25
if (src_cmd == CMD_HALT) {
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[PULL 11/11] dma/xlnx-zdma: Reorg to fix CUR_DSCR
Deleted patch
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
1
3
Reorganize the descriptor handling so that CUR_DSCR always
4
points to the next descriptor to be processed.
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Message-id: 20200402134721.27863-6-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/dma/xlnx-zdma.c | 47 ++++++++++++++++++++++------------------------
13
1 file changed, 22 insertions(+), 25 deletions(-)
14
15
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/dma/xlnx-zdma.c
18
+++ b/hw/dma/xlnx-zdma.c
19
@@ -XXX,XX +XXX,XX @@ static void zdma_load_src_descriptor(XlnxZDMA *s)
20
}
21
}
22
23
+static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
24
+ unsigned int basereg)
25
+{
26
+ uint64_t addr, next;
27
+
28
+ if (type == DTYPE_LINEAR) {
29
+ addr = zdma_get_regaddr64(s, basereg);
30
+ next = addr + sizeof(s->dsc_dst);
31
+ } else {
32
+ addr = zdma_get_regaddr64(s, basereg);
33
+ addr += sizeof(s->dsc_dst);
34
+ address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8);
35
+ }
36
+
37
+ zdma_put_regaddr64(s, basereg, next);
38
+}
39
+
40
static void zdma_load_dst_descriptor(XlnxZDMA *s)
41
{
42
uint64_t dst_addr;
43
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
44
+ bool dst_type;
45
46
if (ptype == PT_REG) {
47
memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
48
@@ -XXX,XX +XXX,XX @@ static void zdma_load_dst_descriptor(XlnxZDMA *s)
49
if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) {
50
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true);
51
}
52
-}
53
54
-static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
55
- unsigned int basereg)
56
-{
57
- uint64_t addr, next;
58
-
59
- if (type == DTYPE_LINEAR) {
60
- next = zdma_get_regaddr64(s, basereg);
61
- next += sizeof(s->dsc_dst);
62
- zdma_put_regaddr64(s, basereg, next);
63
- } else {
64
- addr = zdma_get_regaddr64(s, basereg);
65
- addr += sizeof(s->dsc_dst);
66
- address_space_read(s->dma_as, addr, s->attr, &next, 8);
67
- zdma_put_regaddr64(s, basereg, next);
68
- }
69
- return next;
70
+ /* Advance the descriptor pointer. */
71
+ dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3, TYPE);
72
+ zdma_update_descr_addr(s, dst_type, R_ZDMA_CH_DST_CUR_DSCR_LSB);
73
}
74
75
static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
76
@@ -XXX,XX +XXX,XX @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
77
dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
78
SIZE);
79
if (dst_size == 0 && ptype == PT_MEM) {
80
- uint64_t next;
81
- bool dst_type = FIELD_EX32(s->dsc_dst.words[3],
82
- ZDMA_CH_DST_DSCR_WORD3,
83
- TYPE);
84
-
85
- next = zdma_update_descr_addr(s, dst_type,
86
- R_ZDMA_CH_DST_CUR_DSCR_LSB);
87
- zdma_load_descriptor(s, next, &s->dsc_dst);
88
+ zdma_load_dst_descriptor(s);
89
dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
90
SIZE);
91
}
92
--
93
2.20.1
94
95
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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