[v7] target/riscv: support vector extension v0.7.1

[PATCH v7 00/61] target/riscv: support vector extension v0.7.1

Posted by LIU Zhiwei 4 years ago

This patchset implements the vector extension for RISC-V on QEMU.

You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.

You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.

Features:
  * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
  * support basic vector extension.
  * support Zvlsseg.
  * support Zvamo.
  * not support Zvediv as it is changing.
  * SLEN always equals VLEN.
  * element width support 8bit, 16bit, 32bit, 64bit.

Changelog:
v7
  * move vl == 0 check to translation time by add a global cpu_vl.
  * implement vector element inline load and store function by TCG IR.
  * based on vec_element_load(store), implement some permutation instructions.
  * implement rsubs GVEC IR.
  * fixup vsmul, vmfne, vfmerge, vslidedown.
  * some other small bugs and indentation errors.

v6
  * use gvec_dup Gvec IR to accellerate move and merge.
  * a better way to implement fixed point instructions.
  * a global check when vl == 0.
  * limit some macros to only one inline function call.
  * fixup sew error when use Gvec IR.
  * fixup bugs for corner cases.

v5
  * fixup a bug in tb flags.

v4
  * no change

v3
  * move check code from execution-time to translation-time
  * use a continous memory block for vector register description.
  * vector registers as direct fields in RISCVCPUState.
  * support VLEN configure from qemu command line.
  * support ELEN configure from qemu command line.
  * support vector specification version configure from qemu command line.
  * probe pages before real load or store access.
  * use probe_page_check for no-fault operations in linux user mode.
  * generation atomic exit exception when in parallel environment.
  * fixup a lot of concrete bugs.

V2
  * use float16_compare{_quiet}
  * only use GETPC() in outer most helper
  * add ctx.ext_v Property



LIU Zhiwei (61):
  target/riscv: add vector extension field in CPURISCVState
  target/riscv: implementation-defined constant parameters
  target/riscv: support vector extension csr
  target/riscv: add vector configure instruction
  target/riscv: add an internals.h header
  target/riscv: add vector stride load and store instructions
  target/riscv: add vector index load and store instructions
  target/riscv: add fault-only-first unit stride load
  target/riscv: add vector amo operations
  target/riscv: vector single-width integer add and subtract
  target/riscv: vector widening integer add and subtract
  target/riscv: vector integer add-with-carry / subtract-with-borrow
    instructions
  target/riscv: vector bitwise logical instructions
  target/riscv: vector single-width bit shift instructions
  target/riscv: vector narrowing integer right shift instructions
  target/riscv: vector integer comparison instructions
  target/riscv: vector integer min/max instructions
  target/riscv: vector single-width integer multiply instructions
  target/riscv: vector integer divide instructions
  target/riscv: vector widening integer multiply instructions
  target/riscv: vector single-width integer multiply-add instructions
  target/riscv: vector widening integer multiply-add instructions
  target/riscv: vector integer merge and move instructions
  target/riscv: vector single-width saturating add and subtract
  target/riscv: vector single-width averaging add and subtract
  target/riscv: vector single-width fractional multiply with rounding
    and saturation
  target/riscv: vector widening saturating scaled multiply-add
  target/riscv: vector single-width scaling shift instructions
  target/riscv: vector narrowing fixed-point clip instructions
  target/riscv: vector single-width floating-point add/subtract
    instructions
  target/riscv: vector widening floating-point add/subtract instructions
  target/riscv: vector single-width floating-point multiply/divide
    instructions
  target/riscv: vector widening floating-point multiply
  target/riscv: vector single-width floating-point fused multiply-add
    instructions
  target/riscv: vector widening floating-point fused multiply-add
    instructions
  target/riscv: vector floating-point square-root instruction
  target/riscv: vector floating-point min/max instructions
  target/riscv: vector floating-point sign-injection instructions
  target/riscv: vector floating-point compare instructions
  target/riscv: vector floating-point classify instructions
  target/riscv: vector floating-point merge instructions
  target/riscv: vector floating-point/integer type-convert instructions
  target/riscv: widening floating-point/integer type-convert
    instructions
  target/riscv: narrowing floating-point/integer type-convert
    instructions
  target/riscv: vector single-width integer reduction instructions
  target/riscv: vector wideing integer reduction instructions
  target/riscv: vector single-width floating-point reduction
    instructions
  target/riscv: vector widening floating-point reduction instructions
  target/riscv: vector mask-register logical instructions
  target/riscv: vector mask population count vmpopc
  target/riscv: vmfirst find-first-set mask bit
  target/riscv: set-X-first mask bit
  target/riscv: vector iota instruction
  target/riscv: vector element index instruction
  target/riscv: integer extract instruction
  target/riscv: integer scalar move instruction
  target/riscv: floating-point scalar move instructions
  target/riscv: vector slide instructions
  target/riscv: vector register gather instruction
  target/riscv: vector compress instruction
  target/riscv: configure and turn on vector extension from command line

 target/riscv/Makefile.objs              |    2 +-
 target/riscv/cpu.c                      |   49 +
 target/riscv/cpu.h                      |   82 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/csr.c                      |   75 +-
 target/riscv/fpu_helper.c               |   33 +-
 target/riscv/helper.h                   | 1068 +++++
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  372 ++
 target/riscv/insn_trans/trans_rvv.inc.c | 2907 ++++++++++++++
 target/riscv/internals.h                |   35 +
 target/riscv/translate.c                |   27 +-
 target/riscv/vector_helper.c            | 4898 +++++++++++++++++++++++
 13 files changed, 9530 insertions(+), 44 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/internals.h
 create mode 100644 target/riscv/vector_helper.c

-- 
2.23.0

Re: [PATCH v7 00/61] target/riscv: support vector extension v0.7.1

Posted by no-reply@patchew.org 4 years ago

Patchew URL: https://patchew.org/QEMU/20200330153633.15298-1-zhiwei_liu@c-sky.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v7 00/61] target/riscv: support vector extension v0.7.1
Message-id: 20200330153633.15298-1-zhiwei_liu@c-sky.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
d8a846a target/riscv: configure and turn on vector extension from command line
80d5dd0 target/riscv: vector compress instruction
ddaff45 target/riscv: vector register gather instruction
1f9c2fc target/riscv: vector slide instructions
a1e1941 target/riscv: floating-point scalar move instructions
10d50e9 target/riscv: integer scalar move instruction
90d4c29 target/riscv: integer extract instruction
fff9730 target/riscv: vector element index instruction
c5b2d30 target/riscv: vector iota instruction
9ce49c4 target/riscv: set-X-first mask bit
8f6ed7e target/riscv: vmfirst find-first-set mask bit
ad40921 target/riscv: vector mask population count vmpopc
e848169 target/riscv: vector mask-register logical instructions
7d93518 target/riscv: vector widening floating-point reduction instructions
d8a3120 target/riscv: vector single-width floating-point reduction instructions
0785cc0 target/riscv: vector wideing integer reduction instructions
dbbbe33 target/riscv: vector single-width integer reduction instructions
37dc448 target/riscv: narrowing floating-point/integer type-convert instructions
8099b1d target/riscv: widening floating-point/integer type-convert instructions
88e3454 target/riscv: vector floating-point/integer type-convert instructions
6434267 target/riscv: vector floating-point merge instructions
e79ef28 target/riscv: vector floating-point classify instructions
e3f6610 target/riscv: vector floating-point compare instructions
d49e4cc target/riscv: vector floating-point sign-injection instructions
98e0e85 target/riscv: vector floating-point min/max instructions
f38f04c target/riscv: vector floating-point square-root instruction
98f4904 target/riscv: vector widening floating-point fused multiply-add instructions
f41fad0 target/riscv: vector single-width floating-point fused multiply-add instructions
64595c9 target/riscv: vector widening floating-point multiply
85e3d27 target/riscv: vector single-width floating-point multiply/divide instructions
b08dbba target/riscv: vector widening floating-point add/subtract instructions
f6875e1 target/riscv: vector single-width floating-point add/subtract instructions
d17b65d target/riscv: vector narrowing fixed-point clip instructions
308fd7f target/riscv: vector single-width scaling shift instructions
9e35107 target/riscv: vector widening saturating scaled multiply-add
238f880 target/riscv: vector single-width fractional multiply with rounding and saturation
653be93 target/riscv: vector single-width averaging add and subtract
043d704 target/riscv: vector single-width saturating add and subtract
39b6b30 target/riscv: vector integer merge and move instructions
ddf3012 target/riscv: vector widening integer multiply-add instructions
f3fb29d target/riscv: vector single-width integer multiply-add instructions
db13c0f target/riscv: vector widening integer multiply instructions
b8db57e target/riscv: vector integer divide instructions
cd6b0b1 target/riscv: vector single-width integer multiply instructions
f164fd5 target/riscv: vector integer min/max instructions
4207b55 target/riscv: vector integer comparison instructions
3dc7955 target/riscv: vector narrowing integer right shift instructions
4546862 target/riscv: vector single-width bit shift instructions
df26fc3 target/riscv: vector bitwise logical instructions
2720080 target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
77af4d8 target/riscv: vector widening integer add and subtract
3f6915b target/riscv: vector single-width integer add and subtract
0cd49c3 target/riscv: add vector amo operations
67a344c target/riscv: add fault-only-first unit stride load
222615c target/riscv: add vector index load and store instructions
1a65664 target/riscv: add vector stride load and store instructions
5f74bcf target/riscv: add an internals.h header
623ef59 target/riscv: add vector configure instruction
6b75359 target/riscv: support vector extension csr
3033f93 target/riscv: implementation-defined constant parameters
8c8565f target/riscv: add vector extension field in CPURISCVState

=== OUTPUT BEGIN ===
1/61 Checking commit 8c8565f4a8f4 (target/riscv: add vector extension field in CPURISCVState)
2/61 Checking commit 3033f9305517 (target/riscv: implementation-defined constant parameters)
3/61 Checking commit 6b753595f677 (target/riscv: support vector extension csr)
4/61 Checking commit 623ef59a8390 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#160: 
new file mode 100644

total: 0 errors, 1 warnings, 294 lines checked

Patch 4/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/61 Checking commit 5f74bcfcab15 (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 24 lines checked

Patch 5/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/61 Checking commit 1a65664915f2 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#274: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                    ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                     ^

total: 5 errors, 0 warnings, 982 lines checked

Patch 6/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

7/61 Checking commit 222615c22b72 (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#251: FILE: target/riscv/vector_helper.c:487:
+                vext_ldst_elem_fn *ldst_elem,
                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#252: FILE: target/riscv/vector_helper.c:488:
+                clear_fn *clear_elem,
                          ^

total: 2 errors, 0 warnings, 308 lines checked

Patch 7/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

8/61 Checking commit 67a344c1c9e4 (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#161: FILE: target/riscv/vector_helper.c:587:
+          vext_ldst_elem_fn *ldst_elem,
                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#162: FILE: target/riscv/vector_helper.c:588:
+          clear_fn *clear_elem,
                    ^

total: 2 errors, 0 warnings, 226 lines checked

Patch 8/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/61 Checking commit 0cd49c3bdc65 (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#365: FILE: target/riscv/vector_helper.c:769:
+                  vext_amo_noatomic_fn *noatomic_op,
                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#366: FILE: target/riscv/vector_helper.c:770:
+                  clear_fn *clear_elem,
                            ^

total: 2 errors, 0 warnings, 382 lines checked

Patch 9/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/61 Checking commit 3f6915b787c4 (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#93: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:875:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:875:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#490: FILE: target/riscv/vector_helper.c:940:
+                       opivx2_fn fn, clear_fn *clearfn)
                                               ^

total: 4 errors, 0 warnings, 535 lines checked

Patch 10/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/61 Checking commit 77af4d8e0b23 (target/riscv: vector widening integer add and subtract)
12/61 Checking commit 27200807dc74 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
13/61 Checking commit df26fc3f7da4 (target/riscv: vector bitwise logical instructions)
14/61 Checking commit 4546862d4024 (target/riscv: vector single-width bit shift instructions)
15/61 Checking commit 3dc79552f890 (target/riscv: vector narrowing integer right shift instructions)
16/61 Checking commit 4207b550f7de (target/riscv: vector integer comparison instructions)
17/61 Checking commit f164fd549dc3 (target/riscv: vector integer min/max instructions)
18/61 Checking commit cd6b0b12390c (target/riscv: vector single-width integer multiply instructions)
19/61 Checking commit b8db57e221f5 (target/riscv: vector integer divide instructions)
20/61 Checking commit db13c0fc9cfc (target/riscv: vector widening integer multiply instructions)
21/61 Checking commit f3fb29d3a978 (target/riscv: vector single-width integer multiply-add instructions)
22/61 Checking commit ddf3012ea329 (target/riscv: vector widening integer multiply-add instructions)
23/61 Checking commit 39b6b306bf26 (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                                                        ^

total: 1 errors, 0 warnings, 270 lines checked

Patch 23/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

24/61 Checking commit 043d704999f2 (target/riscv: vector single-width saturating add and subtract)
25/61 Checking commit 653be930ac29 (target/riscv: vector single-width averaging add and subtract)
26/61 Checking commit 238f88039c54 (target/riscv: vector single-width fractional multiply with rounding and saturation)
27/61 Checking commit 9e35107242ca (target/riscv: vector widening saturating scaled multiply-add)
28/61 Checking commit 308fd7fb2555 (target/riscv: vector single-width scaling shift instructions)
29/61 Checking commit d17b65dcf136 (target/riscv: vector narrowing fixed-point clip instructions)
30/61 Checking commit f6875e1aacd0 (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#280: FILE: target/riscv/vector_helper.c:3259:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 269 lines checked

Patch 30/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/61 Checking commit b08dbba3819b (target/riscv: vector widening floating-point add/subtract instructions)
32/61 Checking commit 85e3d278d9ef (target/riscv: vector single-width floating-point multiply/divide instructions)
33/61 Checking commit 64595c90c89d (target/riscv: vector widening floating-point multiply)
34/61 Checking commit f41fad00b6ec (target/riscv: vector single-width floating-point fused multiply-add instructions)
35/61 Checking commit 98f4904afee3 (target/riscv: vector widening floating-point fused multiply-add instructions)
36/61 Checking commit f38f04c6953a (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#66: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2117:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#76: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2127:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 119 lines checked

Patch 36/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

37/61 Checking commit 98e0e85fbc52 (target/riscv: vector floating-point min/max instructions)
38/61 Checking commit d49e4cc18c0f (target/riscv: vector floating-point sign-injection instructions)
39/61 Checking commit e3f661059ea8 (target/riscv: vector floating-point compare instructions)
40/61 Checking commit e79ef2829a5c (target/riscv: vector floating-point classify instructions)
41/61 Checking commit 6434267fc714 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#47: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2208:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                                                          ^

total: 1 errors, 0 warnings, 83 lines checked

Patch 41/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

42/61 Checking commit 88e345449454 (target/riscv: vector floating-point/integer type-convert instructions)
43/61 Checking commit 8099b1d51d78 (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2255:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2267:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 120 lines checked

Patch 43/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

44/61 Checking commit 37dc4480817a (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2302:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2314:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 117 lines checked

Patch 44/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

45/61 Checking commit dbbbe338e9b1 (target/riscv: vector single-width integer reduction instructions)
46/61 Checking commit 0785cc077499 (target/riscv: vector wideing integer reduction instructions)
47/61 Checking commit d8a31209c85c (target/riscv: vector single-width floating-point reduction instructions)
48/61 Checking commit 7d93518b2f68 (target/riscv: vector widening floating-point reduction instructions)
49/61 Checking commit e848169398ca (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2379:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

total: 1 errors, 0 warnings, 107 lines checked

Patch 49/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

50/61 Checking commit ad4092104e77 (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#43: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2409:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 50/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

51/61 Checking commit 8f6ed7e3c843 (target/riscv: vmfirst find-first-set mask bit)
52/61 Checking commit 9ce49c4083cb (target/riscv: set-X-first mask bit)
53/61 Checking commit c5b2d30c8162 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#46: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2501:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 77 lines checked

Patch 53/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

54/61 Checking commit fff973027ff5 (target/riscv: vector element index instruction)
55/61 Checking commit 90d4c2915a3a (target/riscv: integer extract instruction)
56/61 Checking commit 10d50e93656b (target/riscv: integer scalar move instruction)
57/61 Checking commit a1e1941d126f (target/riscv: floating-point scalar move instructions)
58/61 Checking commit 1f9c2fcf5c98 (target/riscv: vector slide instructions)
59/61 Checking commit ddaff455d71c (target/riscv: vector register gather instruction)
60/61 Checking commit 80d5dd0f5c70 (target/riscv: vector compress instruction)
61/61 Checking commit d8a846ab2616 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200330153633.15298-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
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