1
A handful of bugfixes before rc1 tomorrow...
1
A last small test of bug fixes before rc1.
2
2
3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit f9fe8450fa7cdc6268e05c93fa258f583f4514b7:
6
The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:
7
7
8
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-03-30 11:32:01 +0100)
8
Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200330
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717
13
13
14
for you to fetch changes up to 88828bf133b64b7a860c166af3423ef1a47c5d3b:
14
for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:
15
15
16
target/arm: fix incorrect current EL bug in aarch32 exception emulation (2020-03-30 13:55:32 +0100)
16
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available
20
* hw/arm/sbsa-ref: set 'slots' property of xhci
21
* hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address
21
* linux-user: Remove pointless NULL check in clock_adjtime handling
22
* docs/conf.py: Raise ConfigError for bad Sphinx Python version
22
* ptw: Fix S1_ptw_translate() debug path
23
* hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path
23
* ptw: Account for FEAT_RME when applying {N}SW, SA bits
24
* hw/arm/xlnx-zynqmp.c: Add missing error-propagation code
24
* accel/tcg: Zero-pad PC in TCG CPU exec trace lines
25
* target/arm: fix incorrect current EL bug in aarch32 exception emulation
25
* hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
26
26
27
----------------------------------------------------------------
27
----------------------------------------------------------------
28
Changbin Du (1):
28
Peter Maydell (5):
29
target/arm: fix incorrect current EL bug in aarch32 exception emulation
29
linux-user: Remove pointless NULL check in clock_adjtime handling
30
target/arm/ptw.c: Add comments to S1Translate struct fields
31
target/arm: Fix S1_ptw_translate() debug path
32
target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
33
accel/tcg: Zero-pad PC in TCG CPU exec trace lines
30
34
31
Niek Linnenbank (2):
35
Tong Ho (1):
32
hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available
36
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
33
hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address
34
37
35
Peter Maydell (3):
38
Yuquan Wang (1):
36
docs/conf.py: Raise ConfigError for bad Sphinx Python version
39
hw/arm/sbsa-ref: set 'slots' property of xhci
37
hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path
38
hw/arm/xlnx-zynqmp.c: Add missing error-propagation code
39
40
40
hw/arm/orangepi.c | 2 +-
41
accel/tcg/cpu-exec.c | 4 +--
41
hw/arm/xlnx-zynqmp.c | 27 ++++++++++++++++++++++++++-
42
accel/tcg/translate-all.c | 2 +-
42
hw/misc/allwinner-h3-dramc.c | 4 ++--
43
hw/arm/sbsa-ref.c | 1 +
43
target/arm/helper.c | 5 ++++-
44
hw/nvram/xlnx-efuse.c | 11 ++++--
44
docs/conf.py | 9 +++++----
45
linux-user/syscall.c | 12 +++----
45
5 files changed, 38 insertions(+), 9 deletions(-)
46
target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------
46
47
6 files changed, 98 insertions(+), 22 deletions(-)
diff view generated by jsdifflib
New patch
1
From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
1
2
3
This extends the slots of xhci to 64, since the default xhci_sysbus
4
just supports one slot.
5
6
Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn>
7
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
10
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
11
Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/sbsa-ref.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
20
+++ b/hw/arm/sbsa-ref.c
21
@@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms)
22
hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
23
int irq = sbsa_ref_irqmap[SBSA_XHCI];
24
DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
25
+ qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
26
27
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
28
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
29
--
30
2.34.1
diff view generated by jsdifflib
1
In some places in xlnx_zynqmp_realize() we were putting an
1
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
2
error into our local Error*, but forgetting to check for
2
the address of the local variable htx. This means it can never be
3
failure and pass it back to the caller. Add the missing code.
3
NULL, but later in the code we check it for NULL anyway. Coverity
4
complains about this (CID 1507683) because the NULL check comes after
5
a call to clock_adjtime() that assumes it is non-NULL.
6
7
Since phtx is always &htx, and is used only in three places, it's not
8
really necessary. Remove it, bringing the code structure in to line
9
with that for TARGET_NR_clock_adjtime64, which already uses a simple
10
'&htx' when it wants a pointer to 'htx'.
4
11
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org
9
Message-id: 20200324134947.15384-3-peter.maydell@linaro.org
10
---
16
---
11
hw/arm/xlnx-zynqmp.c | 24 ++++++++++++++++++++++++
17
linux-user/syscall.c | 12 +++++-------
12
1 file changed, 24 insertions(+)
18
1 file changed, 5 insertions(+), 7 deletions(-)
13
19
14
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
20
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-zynqmp.c
22
--- a/linux-user/syscall.c
17
+++ b/hw/arm/xlnx-zynqmp.c
23
+++ b/linux-user/syscall.c
18
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
24
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,
19
* - eMMC Specification Version 4.51
25
#if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME)
20
*/
26
case TARGET_NR_clock_adjtime:
21
object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
27
{
22
+ if (err) {
28
- struct timex htx, *phtx = &htx;
23
+ error_propagate(errp, err);
29
+ struct timex htx;
24
+ return;
30
25
+ }
31
- if (target_to_host_timex(phtx, arg2) != 0) {
26
object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
32
+ if (target_to_host_timex(&htx, arg2) != 0) {
27
+ if (err) {
33
return -TARGET_EFAULT;
28
+ error_propagate(errp, err);
34
}
29
+ return;
35
- ret = get_errno(clock_adjtime(arg1, phtx));
30
+ }
36
- if (!is_error(ret) && phtx) {
31
object_property_set_uint(sdhci, UHS_I, "uhs", &err);
37
- if (host_to_target_timex(arg2, phtx) != 0) {
32
+ if (err) {
38
- return -TARGET_EFAULT;
33
+ error_propagate(errp, err);
39
- }
34
+ return;
40
+ ret = get_errno(clock_adjtime(arg1, &htx));
35
+ }
41
+ if (!is_error(ret) && host_to_target_timex(arg2, &htx)) {
36
object_property_set_bool(sdhci, true, "realized", &err);
42
+ return -TARGET_EFAULT;
37
if (err) {
43
}
38
error_propagate(errp, err);
44
}
39
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
45
return ret;
40
gchar *bus_name;
41
42
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
43
+ if (err) {
44
+ error_propagate(errp, err);
45
+ return;
46
+ }
47
48
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
49
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
50
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
51
}
52
53
object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
54
+ if (err) {
55
+ error_propagate(errp, err);
56
+ return;
57
+ }
58
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
61
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
62
63
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
64
object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
65
+ if (err) {
66
+ error_propagate(errp, err);
67
+ return;
68
+ }
69
object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
70
if (err) {
71
error_propagate(errp, err);
72
--
46
--
73
2.20.1
47
2.34.1
74
48
75
49
diff view generated by jsdifflib
1
In xlnx_zynqmp_realize() if the attempt to realize the SD
1
Add comments to the in_* fields in the S1Translate struct
2
controller object fails then the error-return path will leak
2
that explain what they're doing.
3
the 'bus_name' string. Fix this by deferring the allocation
4
until after the realize has succeeded.
5
3
6
Fixes: Coverity CID 1421911
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200324134947.15384-2-peter.maydell@linaro.org
12
---
7
---
13
hw/arm/xlnx-zynqmp.c | 3 ++-
8
target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++
14
1 file changed, 2 insertions(+), 1 deletion(-)
9
1 file changed, 40 insertions(+)
15
10
16
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
11
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/xlnx-zynqmp.c
13
--- a/target/arm/ptw.c
19
+++ b/hw/arm/xlnx-zynqmp.c
14
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
15
@@ -XXX,XX +XXX,XX @@
21
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
16
#endif
22
17
23
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
18
typedef struct S1Translate {
24
- char *bus_name = g_strdup_printf("sd-bus%d", i);
19
+ /*
25
+ char *bus_name;
20
+ * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk.
26
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
21
+ * Together with in_space, specifies the architectural translation regime.
27
Object *sdhci = OBJECT(&s->sdhci[i]);
22
+ */
28
23
ARMMMUIdx in_mmu_idx;
29
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
24
+ /*
30
sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
25
+ * in_ptw_idx: specifies which mmuidx to use for the actual
31
26
+ * page table descriptor load operations. This will be one of the
32
/* Alias controller SD bus to the SoC itself */
27
+ * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes.
33
+ bus_name = g_strdup_printf("sd-bus%d", i);
28
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
34
object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
29
+ * this field is updated accordingly.
35
&error_abort);
30
+ */
36
g_free(bus_name);
31
ARMMMUIdx in_ptw_idx;
32
+ /*
33
+ * in_space: the security space for this walk. This plus
34
+ * the in_mmu_idx specify the architectural translation regime.
35
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
36
+ * this field is updated accordingly.
37
+ *
38
+ * Note that the security space for the in_ptw_idx may be different
39
+ * from that for the in_mmu_idx. We do not need to explicitly track
40
+ * the in_ptw_idx security space because:
41
+ * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
42
+ * itself specifies the security space
43
+ * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
44
+ * space used for ptw reads is the same as that of the security
45
+ * space of the stage 1 translation for all cases except where
46
+ * stage 1 is Secure; in that case the only possibilities for
47
+ * the ptw read are Secure and NonSecure, and the in_ptw_idx
48
+ * value being Stage2 vs Stage2_S distinguishes those.
49
+ */
50
ARMSecuritySpace in_space;
51
+ /*
52
+ * in_secure: whether the translation regime is a Secure one.
53
+ * This is always equal to arm_space_is_secure(in_space).
54
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
55
+ * this field is updated accordingly.
56
+ */
57
bool in_secure;
58
+ /*
59
+ * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
60
+ * accesses will not update the guest page table access flags
61
+ * and will not change the state of the softmmu TLBs.
62
+ */
63
bool in_debug;
64
/*
65
* If this is stage 2 of a stage 1+2 page table walk, then this must
37
--
66
--
38
2.20.1
67
2.34.1
39
40
diff view generated by jsdifflib
1
From: Changbin Du <changbin.du@gmail.com>
1
In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate()
2
so that the debug-access "call get_phys_addr_*" codepath is used both
3
when S1 is doing ptw reads from stage 2 and when it is doing ptw
4
reads from physical memory. However, we didn't update the
5
calculation of s2ptw->in_space and s2ptw->in_secure to account for
6
the "ptw reads from physical memory" case. This meant that debug
7
accesses when in Secure state broke.
2
8
3
The arm_current_el() should be invoked after mode switching. Otherwise, we
9
Create a new function S2_security_space() which returns the
4
get a wrong current EL value, since current EL is also determined by
10
correct security space to use for the ptw load, and use it to
5
current mode.
11
determine the correct .in_secure and .in_space fields for the
12
stage 2 lookup for the ptw load.
6
13
7
Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry")
14
Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Signed-off-by: Changbin Du <changbin.du@gmail.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200328140232.17278-1-changbin.du@gmail.com
18
Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org
19
Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate")
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
21
---
13
target/arm/helper.c | 5 ++++-
22
target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++-----
14
1 file changed, 4 insertions(+), 1 deletion(-)
23
1 file changed, 32 insertions(+), 5 deletions(-)
15
24
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
27
--- a/target/arm/ptw.c
19
+++ b/target/arm/helper.c
28
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
29
@@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
21
30
}
22
/* Change the CPU state so as to actually take the exception. */
31
}
23
switch_mode(env, new_mode);
32
24
- new_el = arm_current_el(env);
33
+static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space,
25
34
+ ARMMMUIdx s2_mmu_idx)
26
/*
35
+{
27
* For exceptions taken to AArch32 we must clear the SS bit in both
36
+ /*
28
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
37
+ * Return the security space to use for stage 2 when doing
29
env->condexec_bits = 0;
38
+ * the S1 page table descriptor load.
30
/* Switch to the new mode, and to the correct instruction set. */
39
+ */
31
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
40
+ if (regime_is_stage2(s2_mmu_idx)) {
41
+ /*
42
+ * The security space for ptw reads is almost always the same
43
+ * as that of the security space of the stage 1 translation.
44
+ * The only exception is when stage 1 is Secure; in that case
45
+ * the ptw read might be to the Secure or the NonSecure space
46
+ * (but never Realm or Root), and the s2_mmu_idx tells us which.
47
+ * Root translations are always single-stage.
48
+ */
49
+ if (s1_space == ARMSS_Secure) {
50
+ return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S);
51
+ } else {
52
+ assert(s2_mmu_idx != ARMMMUIdx_Stage2_S);
53
+ assert(s1_space != ARMSS_Root);
54
+ return s1_space;
55
+ }
56
+ } else {
57
+ /* ptw loads are from phys: the mmu idx itself says which space */
58
+ return arm_phys_to_space(s2_mmu_idx);
59
+ }
60
+}
32
+
61
+
33
+ /* This must be after mode switching. */
62
/* Translate a S1 pagetable walk through S2 if needed. */
34
+ new_el = arm_current_el(env);
63
static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
35
+
64
hwaddr addr, ARMMMUFaultInfo *fi)
36
/* Set new mode endianness */
65
{
37
env->uncached_cpsr &= ~CPSR_E;
66
- ARMSecuritySpace space = ptw->in_space;
38
if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
67
bool is_secure = ptw->in_secure;
68
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
69
ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
70
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
71
* From gdbstub, do not use softmmu so that we don't modify the
72
* state of the cpu at all, including softmmu tlb contents.
73
*/
74
+ ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx);
75
S1Translate s2ptw = {
76
.in_mmu_idx = s2_mmu_idx,
77
.in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
78
- .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
79
- .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
80
- : space == ARMSS_Realm ? ARMSS_Realm
81
- : ARMSS_NonSecure),
82
+ .in_secure = arm_space_is_secure(s2_space),
83
+ .in_space = s2_space,
84
.in_debug = true,
85
};
86
GetPhysAddrResult s2 = { };
39
--
87
--
40
2.20.1
88
2.34.1
41
42
diff view generated by jsdifflib
1
Raise ConfigError rather than VersionRequirementError when we detect
1
In get_phys_addr_twostage() the code that applies the effects of
2
that the Python being used by Sphinx is too old.
2
VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
3
Now we also have f.attrs.space for FEAT_RME, we need to keep the two
4
in sync.
3
5
4
Currently the way we flag the Python version problem up to the user
6
These bits only have an effect for Secure space translations, not
5
causes Sphinx to print an unnecessary Python stack trace as well as
7
for Root, so use the input in_space field to determine whether to
6
the information about the problem; in most versions of Sphinx this is
8
apply them rather than the input is_secure. This doesn't actually
7
unavoidable.
9
make a difference because Root translations are never two-stage,
8
10
but it's a little clearer.
9
The upstream Sphinx developers kindly added a feature to allow
10
conf.py to report errors to the user without the backtrace:
11
https://github.com/sphinx-doc/sphinx/commit/be608ca2313fc08eb842f3dc19d0f5d2d8227d08
12
but the exception type they chose for this was ConfigError.
13
14
Switch to ConfigError, which won't make any difference with currently
15
deployed Sphinx versions, but will be prettier one day when the user
16
is using a Sphinx version with the new feature.
17
11
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: John Snow <jsnow@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20200313163616.30674-1-peter.maydell@linaro.org
14
Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org
21
---
15
---
22
docs/conf.py | 9 +++++----
16
target/arm/ptw.c | 13 ++++++++-----
23
1 file changed, 5 insertions(+), 4 deletions(-)
17
1 file changed, 8 insertions(+), 5 deletions(-)
24
18
25
diff --git a/docs/conf.py b/docs/conf.py
19
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
26
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
27
--- a/docs/conf.py
21
--- a/target/arm/ptw.c
28
+++ b/docs/conf.py
22
+++ b/target/arm/ptw.c
29
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
30
import os
24
hwaddr ipa;
31
import sys
25
int s1_prot, s1_lgpgsz;
32
import sphinx
26
bool is_secure = ptw->in_secure;
33
-from sphinx.errors import VersionRequirementError
27
+ ARMSecuritySpace in_space = ptw->in_space;
34
+from sphinx.errors import ConfigError
28
bool ret, ipa_secure;
35
29
ARMCacheAttrs cacheattrs1;
36
# Make Sphinx fail cleanly if using an old Python, rather than obscurely
30
ARMSecuritySpace ipa_space;
37
# failing because some code in one of our extensions doesn't work there.
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
38
-# Unfortunately this doesn't display very neatly (there's an unavoidable
32
* Check if IPA translates to secure or non-secure PA space.
39
-# Python backtrace) but at least the information gets printed...
33
* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
40
+# In newer versions of Sphinx this will display nicely; in older versions
34
*/
41
+# Sphinx will also produce a Python backtrace but at least the information
35
- result->f.attrs.secure =
42
+# gets printed...
36
- (is_secure
43
if sys.version_info < (3,5):
37
- && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
44
- raise VersionRequirementError(
38
- && (ipa_secure
45
+ raise ConfigError(
39
- || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
46
"QEMU requires a Sphinx that uses Python 3.5 or better\n")
40
+ if (in_space == ARMSS_Secure) {
47
41
+ result->f.attrs.secure =
48
# The per-manual conf.py will set qemu_docdir for a single-manual build;
42
+ !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
43
+ && (ipa_secure
44
+ || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)));
45
+ result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);
46
+ }
47
48
return false;
49
}
49
--
50
--
50
2.20.1
51
2.34.1
51
52
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
In commit f0a08b0913befbd we changed the type of the PC from
2
target_ulong to vaddr. In doing so we inadvertently dropped the
3
zero-padding on the PC in trace lines (the second item inside the []
4
in these lines). They used to look like this on AArch64, for
5
instance:
2
6
3
The Orange Pi PC initialization function needs to verify that the SD card
7
Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000]
4
block backend is usable before calling the Boot ROM setup routine. When
5
calling blk_is_available() the input parameter should not be NULL.
6
This commit ensures that blk_is_available is only called with non-NULL input.
7
8
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
and now they look like this:
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000]
10
Message-id: 20200322205439.15231-1-nieklinnenbank@gmail.com
11
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
and if the PC happens to be somewhere low like 0x5000
13
then the field is shown as /5000/.
14
15
This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier,
16
depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64
17
with no width specifier.
18
19
Restore the zero-padding by adding an 016 width specifier to
20
this tracing and a couple of others that were similarly recently
21
changed to use VADDR_PRIx without a width specifier.
22
23
We can't unfortunately restore the "32-bit guests are padded to
24
8 hex digits and 64-bit guests to 16 hex digits" behaviour so
25
easily.
26
27
Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr")
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
30
Reviewed-by: Anton Johansson <anjo@rev.ng>
31
Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
13
---
32
---
14
hw/arm/orangepi.c | 2 +-
33
accel/tcg/cpu-exec.c | 4 ++--
15
1 file changed, 1 insertion(+), 1 deletion(-)
34
accel/tcg/translate-all.c | 2 +-
35
2 files changed, 3 insertions(+), 3 deletions(-)
16
36
17
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
37
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
18
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/orangepi.c
39
--- a/accel/tcg/cpu-exec.c
20
+++ b/hw/arm/orangepi.c
40
+++ b/accel/tcg/cpu-exec.c
21
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
41
@@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu,
22
machine->ram);
42
if (qemu_log_in_addr_range(pc)) {
23
43
qemu_log_mask(CPU_LOG_EXEC,
24
/* Load target kernel or start using BootROM */
44
"Trace %d: %p [%08" PRIx64
25
- if (!machine->kernel_filename && blk_is_available(blk)) {
45
- "/%" VADDR_PRIx "/%08x/%08x] %s\n",
26
+ if (!machine->kernel_filename && blk && blk_is_available(blk)) {
46
+ "/%016" VADDR_PRIx "/%08x/%08x] %s\n",
27
/* Use Boot ROM to copy data from SD card to SRAM */
47
cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
28
allwinner_h3_bootrom_setup(h3, blk);
48
tb->flags, tb->cflags, lookup_symbol(pc));
49
50
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
51
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
52
vaddr pc = log_pc(cpu, last_tb);
53
if (qemu_log_in_addr_range(pc)) {
54
- qemu_log("Stopped execution of TB chain before %p [%"
55
+ qemu_log("Stopped execution of TB chain before %p [%016"
56
VADDR_PRIx "] %s\n",
57
last_tb->tc.ptr, pc, lookup_symbol(pc));
58
}
59
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/accel/tcg/translate-all.c
62
+++ b/accel/tcg/translate-all.c
63
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
64
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
65
vaddr pc = log_pc(cpu, tb);
66
if (qemu_log_in_addr_range(pc)) {
67
- qemu_log("cpu_io_recompile: rewound execution of TB to %"
68
+ qemu_log("cpu_io_recompile: rewound execution of TB to %016"
69
VADDR_PRIx "\n", pc);
70
}
29
}
71
}
30
--
72
--
31
2.20.1
73
2.34.1
32
74
33
75
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@amd.com>
2
2
3
The allwinner_h3_dramc_map_rows function simulates row addressing behavior
3
Add a check in the bit-set operation to write the backstore
4
when bootloader software attempts to detect the amount of available SDRAM.
4
only if the affected bit is 0 before.
5
5
6
Currently the line that calculates the 64-bit address of the mirrored row
6
With this in place, there will be no need for callers to
7
uses a signed 32-bit multiply operation that in theory could result in the
7
do the checking in order to avoid unnecessary writes.
8
upper 32-bit be all 1s. This commit ensures that the row mirror address
9
is calculated using only 64-bit operations.
10
8
11
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Tong Ho <tong.ho@amd.com>
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200323192944.5967-1-nieklinnenbank@gmail.com
11
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
14
---
17
hw/misc/allwinner-h3-dramc.c | 4 ++--
15
hw/nvram/xlnx-efuse.c | 11 +++++++++--
18
1 file changed, 2 insertions(+), 2 deletions(-)
16
1 file changed, 9 insertions(+), 2 deletions(-)
19
17
20
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
18
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/allwinner-h3-dramc.c
20
--- a/hw/nvram/xlnx-efuse.c
23
+++ b/hw/misc/allwinner-h3-dramc.c
21
+++ b/hw/nvram/xlnx-efuse.c
24
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
22
@@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
25
23
26
} else if (row_bits_actual) {
24
bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
27
/* Row bits not matching ram_size, install the rows mirror */
25
{
28
- hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
26
+ uint32_t set, *row;
29
- bank_bits)) * page_size);
27
+
30
+ hwaddr row_mirror = s->ram_addr + ((1ULL << (row_bits_actual +
28
if (efuse_ro_bits_find(s, bit)) {
31
+ bank_bits)) * page_size);
29
g_autofree char *path = object_get_canonical_path(OBJECT(s));
32
30
33
memory_region_set_enabled(&s->row_mirror_alias, true);
31
@@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
34
memory_region_set_address(&s->row_mirror_alias, row_mirror);
32
return false;
33
}
34
35
- s->fuse32[bit / 32] |= 1 << (bit % 32);
36
- efuse_bdrv_sync(s, bit);
37
+ /* Avoid back-end write unless there is a real update */
38
+ row = &s->fuse32[bit / 32];
39
+ set = 1 << (bit % 32);
40
+ if (!(set & *row)) {
41
+ *row |= set;
42
+ efuse_bdrv_sync(s, bit);
43
+ }
44
return true;
45
}
46
35
--
47
--
36
2.20.1
48
2.34.1
37
49
38
50
diff view generated by jsdifflib