Hi; here's another arm pullreq; by volume most of this is

refactoring from me, but there are also some bugfixes and

other bits and pieces here.

thanks

-- PMM

The following changes since commit ed734377ab3f3f3cc15d7aa301a87ab6370f2eed:

Merge tag 'linux-user-fix-gupnp-pull-request' of https://github.com/hdeller/qemu-hppa into staging (2025-01-24 14:43:07 -0500)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250128-1

for you to fetch changes up to 664280abddcb3cacc9c6204706bb739fcc1316f7:

hw/usb/canokey: Fix buffer overflow for OUT packet (2025-01-28 18:40:19 +0000)

target-arm queue:

* hw/arm: Remove various uses of first_cpu global

* hw/char/imx_serial: Fix reset value of UFCR register

* hw/char/imx_serial: Update all state before restarting ageing timer

* hw/pci-host/designware: Expose MSI IRQ

* hw/arm/stellaris: refactoring, cleanup

* hw/arm/stellaris: map both I2C controllers

* tests/functional: Add a test for the arm microbit machine

* target/arm: arm_reset_sve_state() should set FPSR, not FPCR

* target/arm: refactorings preparatory to FEAT_AFP implementation

* fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed

* fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed

* hw/usb/canokey: Fix buffer overflow for OUT packet

Bernhard Beschow (3):

hw/char/imx_serial: Fix reset value of UFCR register

hw/char/imx_serial: Update all state before restarting ageing timer

hw/pci-host/designware: Expose MSI IRQ

Hongren Zheng (1):

hw/usb/canokey: Fix buffer overflow for OUT packet

Peter Maydell (22):

target/arm: arm_reset_sve_state() should set FPSR, not FPCR

target/arm: Use FPSR_ constants in vfp_exceptbits_from_host()

target/arm: Use uint32_t in vfp_exceptbits_from_host()

target/arm: Define new fp_status_a32 and fp_status_a64

target/arm: Use vfp.fp_status_a64 in A64-only helper functions

target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf()

target/arm: Use fp_status_a32 in vjvct helper

target/arm: Use fp_status_a32 in vfp_cmp helpers

target/arm: Use FPST_A32 in A32 decoder

target/arm: Use FPST_A64 in A64 decoder

target/arm: Remove now-unused vfp.fp_status and FPST_FPCR

target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64

target/arm: Use fp_status_f16_a32 in AArch32-only helpers

target/arm: Use fp_status_f16_a64 in AArch64-only helpers

target/arm: Use FPST_A32_F16 in A32 decoder

target/arm: Use FPST_A64_F16 in A64 decoder

target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16

fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed

fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed

fpu: Fix a comment in softfloat-types.h

target/arm: Remove redundant advsimd float16 helpers

target/arm: Use FPST_A64_F16 for halfprec-to-other conversions

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The ARMv7MState object is not simply a CPU, it also

contains the NVIC, SysTick timer, and various MemoryRegions.

Rename the field as 'armv7m', like other Cortex-M boards.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20250112225614.33723-2-philmd@linaro.org

include/hw/arm/nrf51_soc.h | 2 +-

hw/arm/nrf51_soc.c | 18 +++++++++---------

2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h

--- a/include/hw/arm/nrf51_soc.h

+++ b/include/hw/arm/nrf51_soc.h

@@ -XXX,XX +XXX,XX @@ struct NRF51State {

SysBusDevice parent_obj;

/*< public >*/

- ARMv7MState cpu;

+ ARMv7MState armv7m;

NRF51UARTState uart;

NRF51RNGState rng;

diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/nrf51_soc.c

+++ b/hw/arm/nrf51_soc.c

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

}

/* This clock doesn't need migration because it is fixed-frequency */

clock_set_hz(s->sysclk, HCLK_FRQ);

- qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);

+ qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk);

/*

* This SoC has no systick device, so don't connect refclk.

* TODO: model the lack of systick (currently the armv7m object

* will always provide one).

*/

- object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),

+ object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(&s->container),

&error_abort);

- if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {

return;

}

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);

memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);

sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,

- qdev_get_gpio_in(DEVICE(&s->cpu),

+ qdev_get_gpio_in(DEVICE(&s->armv7m),

BASE_TO_IRQ(NRF51_UART_BASE)));

/* RNG */

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);

memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);

sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,

- qdev_get_gpio_in(DEVICE(&s->cpu),

+ qdev_get_gpio_in(DEVICE(&s->armv7m),

BASE_TO_IRQ(NRF51_RNG_BASE)));

/* UICR, FICR, NVMC, FLASH */

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);

sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,

- qdev_get_gpio_in(DEVICE(&s->cpu),

+ qdev_get_gpio_in(DEVICE(&s->armv7m),

BASE_TO_IRQ(base_addr)));

}

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_init(Object *obj)

memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);

- object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);

- qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",

+ object_initialize_child(OBJECT(s), "armv6m", &s->armv7m, TYPE_ARMV7M);

+ qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",

ARM_CPU_TYPE_NAME("cortex-m0"));

- qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);

+ qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 32);

object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);

object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

While the TYPE_ARMV7M object forward its NVIC interrupt lines,

it is somehow misleading to name it 'nvic'. Add the 'armv7m'

local variable for clarity, but also keep the 'nvic' variable

behaving like before when used for wiring IRQ lines.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20250112225614.33723-3-philmd@linaro.org

hw/arm/stellaris.c | 21 +++++++++++----------

1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

*/

Object *soc_container;

- DeviceState *gpio_dev[7], *nvic;

+ DeviceState *gpio_dev[7], *armv7m, *nvic;

qemu_irq gpio_in[7][8];

qemu_irq gpio_out[7][8];

qemu_irq adc;

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);

sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);

- nvic = qdev_new(TYPE_ARMV7M);

- object_property_add_child(soc_container, "v7m", OBJECT(nvic));

- qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);

- qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);

- qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);

- qdev_prop_set_bit(nvic, "enable-bitband", true);

- qdev_connect_clock_in(nvic, "cpuclk",

+ armv7m = qdev_new(TYPE_ARMV7M);

+ object_property_add_child(soc_container, "v7m", OBJECT(armv7m));

+ qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES);

+ qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS);

+ qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type);

+ qdev_prop_set_bit(armv7m, "enable-bitband", true);

+ qdev_connect_clock_in(armv7m, "cpuclk",

qdev_get_clock_out(ssys_dev, "SYSCLK"));

/* This SoC does not connect the systick reference clock */

- object_property_set_link(OBJECT(nvic), "memory",

+ object_property_set_link(OBJECT(armv7m), "memory",

OBJECT(get_system_memory()), &error_abort);

/* This will exit with an error if the user passed us a bad cpu_type */

- sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);

+ sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal);

+ nvic = armv7m;

/* Now we can wire up the IRQ and MMIO of the system registers */

sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

When instanciating the machine model, the machine_init()

implementations usually create the CPUs, so have access

to its first CPU. Use that rather then the &first_cpu

global.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Samuel Tardieu <sam@rfc1149.net>

Message-id: 20250112225614.33723-4-philmd@linaro.org

hw/arm/b-l475e-iot01a.c | 2 +-

hw/arm/microbit.c | 2 +-

hw/arm/mps2-tz.c | 2 +-

hw/arm/mps2.c | 2 +-

hw/arm/msf2-som.c | 2 +-

hw/arm/musca.c | 2 +-

hw/arm/netduino2.c | 2 +-

hw/arm/netduinoplus2.c | 2 +-

hw/arm/olimex-stm32-h405.c | 2 +-

hw/arm/stellaris.c | 2 +-

hw/arm/stm32vldiscovery.c | 2 +-

11 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c

--- a/hw/arm/b-l475e-iot01a.c

+++ b/hw/arm/b-l475e-iot01a.c

@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)

sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);

sc = STM32L4X5_SOC_GET_CLASS(&s->soc);

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,

+ armv7m_load_kernel(s->soc.armv7m.cpu, machine->kernel_filename, 0,

sc->flash_size);

if (object_class_by_name(TYPE_DM163)) {

diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c

--- a/hw/arm/microbit.c

+++ b/hw/arm/microbit.c

@@ -XXX,XX +XXX,XX @@ static void microbit_init(MachineState *machine)

memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,

mr, -1);

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ armv7m_load_kernel(s->nrf51.armv7m.cpu, machine->kernel_filename,

0, s->nrf51.flash_size);

}

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/mps2-tz.c

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

mms->remap_irq);

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ armv7m_load_kernel(mms->iotkit.armv7m[0].cpu, machine->kernel_filename,

0, boot_ram_size(mms));

}

diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/mps2.c

+++ b/hw/arm/mps2.c

@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)

qdev_get_gpio_in(armv7m,

mmc->fpga_type == FPGA_AN511 ? 47 : 13));

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ armv7m_load_kernel(mms->armv7m.cpu, machine->kernel_filename,

0, 0x400000);

}

diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/msf2-som.c

+++ b/hw/arm/msf2-som.c

@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)

cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);

sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ armv7m_load_kernel(soc->armv7m.cpu, machine->kernel_filename,

0, soc->envm_size);

}

diff --git a/hw/arm/musca.c b/hw/arm/musca.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/musca.c

+++ b/hw/arm/musca.c

@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)

"cfg_sec_resp", 0));

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ armv7m_load_kernel(mms->sse.armv7m[0].cpu, machine->kernel_filename,

0, 0x2000000);

}

diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/netduino2.c

+++ b/hw/arm/netduino2.c

@@ -XXX,XX +XXX,XX @@ static void netduino2_init(MachineState *machine)

qdev_connect_clock_in(dev, "sysclk", sysclk);

sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename,

0, FLASH_SIZE);

}

diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/netduinoplus2.c

+++ b/hw/arm/netduinoplus2.c

@@ -XXX,XX +XXX,XX @@ static void netduinoplus2_init(MachineState *machine)

qdev_connect_clock_in(dev, "sysclk", sysclk);

sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

- armv7m_load_kernel(ARM_CPU(first_cpu),

+ armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,

machine->kernel_filename,

0, FLASH_SIZE);

}

diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/olimex-stm32-h405.c

+++ b/hw/arm/olimex-stm32-h405.c

@@ -XXX,XX +XXX,XX @@ static void olimex_stm32_h405_init(MachineState *machine)

qdev_connect_clock_in(dev, "sysclk", sysclk);

sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

- armv7m_load_kernel(ARM_CPU(first_cpu),

+ armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,

machine->kernel_filename,

0, FLASH_SIZE);

}

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

create_unimplemented_device("hibernation", 0x400fc000, 0x1000);

create_unimplemented_device("flash-control", 0x400fd000, 0x1000);

- armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);

+ armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size);

}

/* FIXME: Figure out how to generate these from stellaris_boards. */

diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/stm32vldiscovery.c

+++ b/hw/arm/stm32vldiscovery.c

@@ -XXX,XX +XXX,XX @@ static void stm32vldiscovery_init(MachineState *machine)

qdev_connect_clock_in(dev, "sysclk", sysclk);

sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

- armv7m_load_kernel(ARM_CPU(first_cpu),

+ armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu,

machine->kernel_filename,

0, FLASH_SIZE);

}

2.34.1

From: Bernhard Beschow <shentey@gmail.com>

Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of

each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share

the MSI IRQ with the INTx lines, so expose it as a dedicated pin.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>

include/hw/arm/fsl-imx6.h | 4 +++-

include/hw/arm/fsl-imx7.h | 4 +++-

include/hw/pci-host/designware.h | 1 +

hw/arm/fsl-imx6.c | 13 ++++++++++++-

hw/arm/fsl-imx7.c | 13 ++++++++++++-

hw/pci-host/designware.c | 7 +++----

hw/arm/Kconfig | 2 ++

7 files changed, 36 insertions(+), 8 deletions(-)

#include "hw/usb/chipidea.h"

#include "hw/usb/imx-usb-phy.h"

#include "hw/pci-host/designware.h"

+#include "hw/or-irq.h"

#include "qom/object.h"

@@ -XXX,XX +XXX,XX @@ struct FslIMX6State {

ChipideaState usb[FSL_IMX6_NUM_USBS];

IMXFECState eth;

DesignwarePCIEHost pcie;

+ OrIRQState pcie4_msi_irq;

MemoryRegion rom;

MemoryRegion caam;

MemoryRegion ocram;

@@ -XXX,XX +XXX,XX @@ struct FslIMX6State {

#define FSL_IMX6_PCIE1_IRQ 120

#define FSL_IMX6_PCIE2_IRQ 121

#define FSL_IMX6_PCIE3_IRQ 122

-#define FSL_IMX6_PCIE4_IRQ 123

+#define FSL_IMX6_PCIE4_MSI_IRQ 123

#define FSL_IMX6_DCIC1_IRQ 124

#define FSL_IMX6_DCIC2_IRQ 125

#define FSL_IMX6_MLB150_HIGH_IRQ 126

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/fsl-imx7.h

+++ b/include/hw/arm/fsl-imx7.h

#include "hw/net/imx_fec.h"

#include "hw/pci-host/designware.h"

#include "hw/usb/chipidea.h"

+#include "hw/or-irq.h"

#include "cpu.h"

#include "qom/object.h"

#include "qemu/units.h"

@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {

IMX7GPRState gpr;

ChipideaState usb[FSL_IMX7_NUM_USBS];

DesignwarePCIEHost pcie;

+ OrIRQState pcie4_msi_irq;

MemoryRegion rom;

MemoryRegion caam;

MemoryRegion ocram;

@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {

FSL_IMX7_PCI_INTA_IRQ = 125,

FSL_IMX7_PCI_INTB_IRQ = 124,

FSL_IMX7_PCI_INTC_IRQ = 123,

- FSL_IMX7_PCI_INTD_IRQ = 122,

+ FSL_IMX7_PCI_INTD_MSI_IRQ = 122,

FSL_IMX7_UART7_IRQ = 126,

diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/pci-host/designware.h

+++ b/include/hw/pci-host/designware.h

@@ -XXX,XX +XXX,XX @@ struct DesignwarePCIEHost {

MemoryRegion io;

qemu_irq irqs[4];

+ qemu_irq msi;

} pci;

MemoryRegion mmio;

#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)

#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C

-#define DESIGNWARE_PCIE_IRQ_MSI 3

-

static DesignwarePCIEHost *

designware_pcie_root_to_host(DesignwarePCIERoot *root)

{

@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,

root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;

if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {

- qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);

+ qemu_set_irq(host->pci.msi, 1);

}

@@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,

case DESIGNWARE_PCIE_MSI_INTR0_STATUS:

root->msi.intr[0].status ^= val;

if (!root->msi.intr[0].status) {

- qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);

+ qemu_set_irq(host->pci.msi, 0);

}

break;

@@ -XXX,XX +XXX,XX @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp)

for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {

sysbus_init_irq(sbd, &s->pci.irqs[i]);

+ sysbus_init_irq(sbd, &s->pci.msi);

memory_region_init_io(&s->mmio,

OBJECT(s),

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config FSL_IMX6

select PL310 # cache controller

select PCI_EXPRESS_DESIGNWARE

select SDHCI

+ select OR_IRQ

config ASPEED_SOC

bool

@@ -XXX,XX +XXX,XX @@ config FSL_IMX7

select WDT_IMX2

select PCI_EXPRESS_DESIGNWARE

select SDHCI

+ select OR_IRQ

select UNIMP

config ARM_SMMUV3

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Board schematic is useful to corroborate GPIOs/IRQs wiring.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

hw/arm/stellaris.c | 8 ++++++++

1 file changed, 8 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@ static void lm3s6965evb_init(MachineState *machine)

stellaris_init(machine, &stellaris_boards[1]);

}

+/*

+ * Stellaris LM3S811 Evaluation Board Schematics:

+ * https://www.ti.com/lit/ug/symlink/spmu030.pdf

+ */

static void lm3s811evb_class_init(ObjectClass *oc, void *data)

{

MachineClass *mc = MACHINE_CLASS(oc);

@@ -XXX,XX +XXX,XX @@ static const TypeInfo lm3s811evb_type = {

.class_init = lm3s811evb_class_init,

};

+/*

+ * Stellaris: LM3S6965 Evaluation Board Schematics:

+ * https://www.ti.com/lit/ug/symlink/spmu029.pdf

+ */

static void lm3s6965evb_class_init(ObjectClass *oc, void *data)

{

MachineClass *mc = MACHINE_CLASS(oc);

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

hw/arm/stellaris.c | 6 +++---

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@ static void ssys_update(ssys_state *s)

qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);

}

-static uint32_t pllcfg_sandstorm[16] = {

+static const uint32_t pllcfg_sandstorm[16] = {

0x31c0, /* 1 Mhz */

0x1ae0, /* 1.8432 Mhz */

0x18c0, /* 2 Mhz */

@@ -XXX,XX +XXX,XX @@ static uint32_t pllcfg_sandstorm[16] = {

0x585b /* 8.192 Mhz */

};

-static uint32_t pllcfg_fury[16] = {

+static const uint32_t pllcfg_fury[16] = {

0x3200, /* 1 Mhz */

0x1b20, /* 1.8432 Mhz */

0x1900, /* 2 Mhz */

@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)

}

/* Board init. */

-static stellaris_board_info stellaris_boards[] = {

+static const stellaris_board_info stellaris_boards[] = {

{ "LM3S811EVB",

0,

0x0032000e,

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

There is nothing mapped at 0x40002000.

I2C#0 is already mapped at 0x40021000.

Remove the invalid mapping added in commits aecfbbc97a2 & 394c8bbfb7a.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20250110160204.74997-4-philmd@linaro.org

hw/arm/stellaris.c | 2 --

1 file changed, 2 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

* http://www.ti.com/lit/ds/symlink/lm3s6965.pdf

*

* 40000000 wdtimer

- * 40002000 i2c (unimplemented)

* 40004000 GPIO

* 40005000 GPIO

* 40006000 GPIO

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

/* Add dummy regions for the devices we don't implement yet,

* so guest accesses don't cause unlogged crashes.

*/

- create_unimplemented_device("i2c-0", 0x40002000, 0x1000);

create_unimplemented_device("i2c-2", 0x40021000, 0x1000);

create_unimplemented_device("PWM", 0x40028000, 0x1000);

create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Add definitions for the number of controllers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

hw/arm/stellaris.c | 25 +++++++++++++++----------

1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@

#define NUM_IRQ_LINES 64

#define NUM_PRIO_BITS 3

+#define NUM_GPIO 7

+#define NUM_UART 4

+#define NUM_GPTM 4

+#define NUM_I2C 2

+

typedef const struct {

const char *name;

uint32_t did0;

@@ -XXX,XX +XXX,XX @@ static const stellaris_board_info stellaris_boards[] = {

static void stellaris_init(MachineState *ms, stellaris_board_info *board)

{

- static const int uart_irq[] = {5, 6, 33, 34};

- static const int timer_irq[] = {19, 21, 23, 35};

- static const uint32_t gpio_addr[7] =

+ static const int uart_irq[NUM_UART] = {5, 6, 33, 34};

+ static const int timer_irq[NUM_GPTM] = {19, 21, 23, 35};

+ static const uint32_t gpio_addr[NUM_GPIO] =

{ 0x40004000, 0x40005000, 0x40006000, 0x40007000,

0x40024000, 0x40025000, 0x40026000};

- static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};

+ static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31};

/* Memory map of SoC devices, from

* Stellaris LM3S6965 Microcontroller Data Sheet (rev I)

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

*/

Object *soc_container;

- DeviceState *gpio_dev[7], *armv7m, *nvic;

- qemu_irq gpio_in[7][8];

- qemu_irq gpio_out[7][8];

+ DeviceState *gpio_dev[NUM_GPIO], *armv7m, *nvic;

+ qemu_irq gpio_in[NUM_GPIO][8];

+ qemu_irq gpio_out[NUM_GPIO][8];

qemu_irq adc;

int sram_size;

int flash_size;

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

} else {

adc = NULL;

- for (i = 0; i < 4; i++) {

+ for (i = 0; i < NUM_GPTM; i++) {

if (board->dc2 & (0x10000 << i)) {

SysBusDevice *sbd;

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

}

- for (i = 0; i < 7; i++) {

+ for (i = 0; i < NUM_GPIO; i++) {

if (board->dc4 & (1 << i)) {

gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],

qdev_get_gpio_in(nvic,

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

}

}

- for (i = 0; i < 4; i++) {

+ for (i = 0; i < NUM_UART; i++) {

if (board->dc2 & (1 << i)) {

SysBusDevice *sbd;

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Add definitions (DCx_periph) for the DeviceCapability bits,

replace direct bitmask checks with the DEV_CAP() macro,

which use the extract/deposit API.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20250110160204.74997-6-philmd@linaro.org

hw/arm/stellaris.c | 37 +++++++++++++++++++++++++++++--------

1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

*/

#include "qemu/osdep.h"

+#include "qemu/bitops.h"

#include "hw/core/split-irq.h"

#include "hw/sysbus.h"

@@ -XXX,XX +XXX,XX @@

#define NUM_GPTM 4

#define NUM_I2C 2

+/*

+ * See Stellaris Data Sheet chapter 5.2.5 "System Control",

+ * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4).

+ */

+#define DC1_WDT 3

+#define DC1_HIB 6

+#define DC1_MPU 7

+#define DC1_ADC 16

+#define DC1_PWM 20

+#define DC2_UART(n) (n)

+#define DC2_SSI 4

+#define DC2_QEI(n) (8 + n)

+#define DC2_I2C(n) (12 + 2 * n)

+#define DC2_GPTM(n) (16 + n)

+#define DC2_COMP(n) (24 + n)

+#define DC4_GPIO(n) (n)

+#define DC4_EMAC 28

+

+#define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)

+

typedef const struct {

const char *name;

uint32_t did0;

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);

sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));

- if (board->dc1 & (1 << 16)) {

+ if (DEV_CAP(1, ADC)) {

dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,

qdev_get_gpio_in(nvic, 14),

qdev_get_gpio_in(nvic, 15),

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

adc = NULL;

for (i = 0; i < NUM_GPTM; i++) {

- if (board->dc2 & (0x10000 << i)) {

+ if (DEV_CAP(2, GPTM(i))) {

SysBusDevice *sbd;

dev = qdev_new(TYPE_STELLARIS_GPTM);

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

}

- if (board->dc1 & (1 << 3)) { /* watchdog present */

+ if (DEV_CAP(1, WDT)) {

dev = qdev_new(TYPE_LUMINARY_WATCHDOG);

object_property_add_child(soc_container, "wdg", OBJECT(dev));

qdev_connect_clock_in(dev, "WDOGCLK",

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

for (i = 0; i < NUM_GPIO; i++) {

- if (board->dc4 & (1 << i)) {

+ if (DEV_CAP(4, GPIO(i))) {

gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],

qdev_get_gpio_in(nvic,

gpio_irq[i]));

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

}

- if (board->dc2 & (1 << 12)) {

+ if (DEV_CAP(2, I2C(0))) {

dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,

qdev_get_gpio_in(nvic, 8));

i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

for (i = 0; i < NUM_UART; i++) {

- if (board->dc2 & (1 << i)) {

+ if (DEV_CAP(2, UART(i))) {

SysBusDevice *sbd;

dev = qdev_new("pl011_luminary");

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));