1
Last handful of arm patches before softfreeze...
1
Nothing too exciting, but does include the last bits of v8.1M support work.
2
2
3
The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
3
-- PMM
4
4
5
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +0000)
5
The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a:
6
7
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000)
6
8
7
are available in the Git repository at:
9
are available in the Git repository at:
8
10
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200317
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108
10
12
11
for you to fetch changes up to e88d3671e3bbd59d385838a4101ea19cdcf47309:
13
for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208:
12
14
13
hw/arm/pxa2xx: Do not wire up OHCI for PXA255 (2020-03-17 11:36:48 +0000)
15
docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000)
14
16
15
----------------------------------------------------------------
17
----------------------------------------------------------------
16
target-arm:
18
target-arm queue:
17
* hw/arm/pxa2xx: Do not wire up OHCI for PXA255
19
* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs
18
* aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
20
* target/arm: Fix MTE0_ACTIVE
19
* m25p80: Improve command handling for Jedec and unsupported commands
21
* target/arm: Implement v8.1M and Cortex-M55 model
20
* hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
22
* hw/arm/highbank: Drop dead KVM support code
21
* hw/arm/fsl-imx6, imx6ul: Wire up USB controllers
23
* util/qemu-timer: Make timer_free() imply timer_del()
22
* hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
24
* various devices: Use ptimer_free() in finalize function
25
* docs/system: arm: Add sabrelite board description
26
* sabrelite: Minor fixes to allow booting U-Boot
23
27
24
----------------------------------------------------------------
28
----------------------------------------------------------------
25
Chen Qun (1):
29
Andrew Jones (1):
26
hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
30
hw/arm/virt: Remove virt machine state 'smp_cpus'
27
31
28
Guenter Roeck (10):
32
Bin Meng (4):
29
hw/usb: Add basic i.MX USB Phy support
33
hw/misc: imx6_ccm: Update PMU_MISC0 reset value
30
hw/arm/fsl-imx6ul: Fix USB interrupt numbers
34
hw/msic: imx6_ccm: Correct register value for silicon type
31
hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
35
hw/arm: sabrelite: Connect the Ethernet PHY at address 6
32
hw/arm/fsl-imx6ul: Wire up USB controllers
36
docs/system: arm: Add sabrelite board description
33
hw/arm/fsl-imx6: Wire up USB controllers
34
m25p80: Convert to support tracing
35
m25p80: Improve command handling for Jedec commands
36
m25p80: Improve command handling for unsupported commands
37
aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
38
hw/arm/pxa2xx: Do not wire up OHCI for PXA255
39
37
40
hw/usb/Makefile.objs | 2 +
38
Edgar E. Iglesias (1):
41
include/hw/arm/fsl-imx6.h | 6 ++
39
intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs
42
include/hw/arm/fsl-imx6ul.h | 16 ++-
43
include/hw/usb/imx-usb-phy.h | 53 ++++++++++
44
hw/arm/fsl-imx6.c | 36 +++++++
45
hw/arm/fsl-imx6ul.c | 49 ++++++++++
46
hw/arm/pxa2xx.c | 3 -
47
hw/block/m25p80.c | 58 +++++------
48
hw/net/imx_fec.c | 6 +-
49
hw/ssi/aspeed_smc.c | 2 +-
50
hw/usb/imx-usb-phy.c | 225 +++++++++++++++++++++++++++++++++++++++++++
51
MAINTAINERS | 2 +
52
hw/arm/Kconfig | 1 +
53
hw/block/trace-events | 16 +++
54
hw/usb/Kconfig | 5 +
55
15 files changed, 444 insertions(+), 36 deletions(-)
56
create mode 100644 include/hw/usb/imx-usb-phy.h
57
create mode 100644 hw/usb/imx-usb-phy.c
58
40
41
Gan Qixin (7):
42
digic-timer: Use ptimer_free() in the finalize function to avoid memleaks
43
allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks
44
exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks
45
exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks
46
mss-timer: Use ptimer_free() in the finalize function to avoid memleaks
47
musicpal: Use ptimer_free() in the finalize function to avoid memleaks
48
exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks
49
50
Peter Maydell (9):
51
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
52
target/arm: Correct store of FPSCR value via FPCXT_S
53
target/arm: Implement FPCXT_NS fp system register
54
target/arm: Implement Cortex-M55 model
55
hw/arm/highbank: Drop dead KVM support code
56
util/qemu-timer: Make timer_free() imply timer_del()
57
scripts/coccinelle: New script to remove unnecessary timer_del() calls
58
Remove superfluous timer_del() calls
59
target/arm: Remove timer_del()/timer_deinit() before timer_free()
60
61
Richard Henderson (1):
62
target/arm: Fix MTE0_ACTIVE
63
64
docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++
65
docs/system/target-arm.rst | 1 +
66
scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++
67
include/hw/arm/virt.h | 3 +-
68
include/qemu/timer.h | 24 +++---
69
block/iscsi.c | 2 -
70
block/nbd.c | 1 -
71
block/qcow2.c | 1 -
72
hw/arm/highbank.c | 14 +--
73
hw/arm/musicpal.c | 12 +++
74
hw/arm/sabrelite.c | 4 +
75
hw/arm/virt-acpi-build.c | 9 +-
76
hw/arm/virt.c | 21 +++--
77
hw/block/nvme.c | 2 -
78
hw/char/serial.c | 2 -
79
hw/char/virtio-serial-bus.c | 2 -
80
hw/ide/core.c | 1 -
81
hw/input/hid.c | 1 -
82
hw/intc/apic.c | 1 -
83
hw/intc/arm_gic.c | 4 +-
84
hw/intc/armv7m_nvic.c | 15 ++++
85
hw/intc/ioapic.c | 1 -
86
hw/ipmi/ipmi_bmc_extern.c | 1 -
87
hw/misc/imx6_ccm.c | 4 +-
88
hw/net/e1000.c | 3 -
89
hw/net/e1000e_core.c | 8 --
90
hw/net/pcnet-pci.c | 1 -
91
hw/net/rtl8139.c | 1 -
92
hw/net/spapr_llan.c | 1 -
93
hw/net/virtio-net.c | 2 -
94
hw/rtc/exynos4210_rtc.c | 9 ++
95
hw/s390x/s390-pci-inst.c | 1 -
96
hw/sd/sd.c | 1 -
97
hw/sd/sdhci.c | 2 -
98
hw/timer/allwinner-a10-pit.c | 11 +++
99
hw/timer/digic-timer.c | 8 ++
100
hw/timer/exynos4210_mct.c | 14 +++
101
hw/timer/exynos4210_pwm.c | 11 +++
102
hw/timer/mss-timer.c | 13 +++
103
hw/usb/dev-hub.c | 1 -
104
hw/usb/hcd-ehci.c | 1 -
105
hw/usb/hcd-ohci-pci.c | 1 -
106
hw/usb/hcd-uhci.c | 1 -
107
hw/usb/hcd-xhci.c | 1 -
108
hw/usb/redirect.c | 1 -
109
hw/vfio/display.c | 1 -
110
hw/virtio/vhost-vsock-common.c | 1 -
111
hw/virtio/virtio-balloon.c | 1 -
112
hw/virtio/virtio-rng.c | 1 -
113
hw/watchdog/wdt_diag288.c | 1 -
114
hw/watchdog/wdt_i6300esb.c | 1 -
115
migration/colo.c | 1 -
116
monitor/hmp-cmds.c | 1 -
117
net/announce.c | 1 -
118
net/colo-compare.c | 1 -
119
net/slirp.c | 1 -
120
replay/replay-debugging.c | 1 -
121
target/arm/cpu.c | 2 -
122
target/arm/cpu_tcg.c | 42 +++++++++
123
target/arm/helper.c | 2 +-
124
target/s390x/cpu.c | 2 -
125
ui/console.c | 1 -
126
ui/spice-core.c | 1 -
127
util/throttle.c | 1 -
128
target/arm/translate-vfp.c.inc | 114 ++++++++++++++++++++++--
129
65 files changed, 421 insertions(+), 111 deletions(-)
130
create mode 100644 docs/system/arm/sabrelite.rst
131
create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci
132
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
While at it, add some trace messages to help debug problems
3
Correct the indexing into s->cpu_ctlr for vCPUs.
4
seen when running the latest Linux kernel.
5
4
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20201214222154.3480243-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/block/m25p80.c | 48 ++++++++++++++++++++-----------------------
11
hw/intc/arm_gic.c | 4 +++-
13
hw/block/trace-events | 16 +++++++++++++++
12
1 file changed, 3 insertions(+), 1 deletion(-)
14
2 files changed, 38 insertions(+), 26 deletions(-)
15
13
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
14
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
16
--- a/hw/intc/arm_gic.c
19
+++ b/hw/block/m25p80.c
17
+++ b/hw/intc/arm_gic.c
20
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static inline void gic_get_best_virq(GICState *s, int cpu,
21
#include "qemu/module.h"
19
static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
22
#include "qemu/error-report.h"
20
int group_mask)
23
#include "qapi/error.h"
21
{
24
-
22
+ int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu;
25
-#ifndef M25P80_ERR_DEBUG
23
+
26
-#define M25P80_ERR_DEBUG 0
24
if (!virt && !(s->ctlr & group_mask)) {
27
-#endif
25
return false;
28
-
29
-#define DB_PRINT_L(level, ...) do { \
30
- if (M25P80_ERR_DEBUG > (level)) { \
31
- fprintf(stderr, ": %s: ", __func__); \
32
- fprintf(stderr, ## __VA_ARGS__); \
33
- } \
34
-} while (0)
35
+#include "trace.h"
36
37
/* Fields for FlashPartInfo->flags */
38
39
@@ -XXX,XX +XXX,XX @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
40
abort();
41
}
26
}
42
27
@@ -XXX,XX +XXX,XX @@ static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
43
- DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
28
return false;
44
+ trace_m25p80_flash_erase(s, offset, len);
45
+
46
if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
47
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
48
" device\n", len);
49
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
50
}
29
}
51
30
52
if ((prev ^ data) & data) {
31
- if (!(s->cpu_ctlr[cpu] & group_mask)) {
53
- DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
32
+ if (!(s->cpu_ctlr[cpu_iface] & group_mask)) {
54
- " -> %" PRIx8 "\n", addr, prev, data);
33
return false;
55
+ trace_m25p80_programming_zero_to_one(s, addr, prev, data);
56
}
34
}
57
35
58
if (s->pi->flags & EEPROM) {
59
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
60
61
s->state = STATE_IDLE;
62
63
+ trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
64
+ s->cur_addr);
65
+
66
switch (s->cmd_in_progress) {
67
case DPP:
68
case QPP:
69
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
70
break;
71
}
72
73
- DB_PRINT_L(0, "Reset done.\n");
74
+ trace_m25p80_reset_done(s);
75
}
76
77
static void decode_fast_read_cmd(Flash *s)
78
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
79
80
static void decode_new_cmd(Flash *s, uint32_t value)
81
{
82
- s->cmd_in_progress = value;
83
int i;
84
- DB_PRINT_L(0, "decoded new command:%x\n", value);
85
+
86
+ s->cmd_in_progress = value;
87
+ trace_m25p80_command_decoded(s, value);
88
89
if (value != RESET_MEMORY) {
90
s->reset_enable = false;
91
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
92
break;
93
94
case JEDEC_READ:
95
- DB_PRINT_L(0, "populated jedec code\n");
96
+ trace_m25p80_populated_jedec(s);
97
for (i = 0; i < s->pi->id_len; i++) {
98
s->data[i] = s->pi->id[i];
99
}
100
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
101
case BULK_ERASE_60:
102
case BULK_ERASE:
103
if (s->write_enable) {
104
- DB_PRINT_L(0, "chip erase\n");
105
+ trace_m25p80_chip_erase(s);
106
flash_erase(s, 0, BULK_ERASE);
107
} else {
108
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
109
@@ -XXX,XX +XXX,XX @@ static int m25p80_cs(SSISlave *ss, bool select)
110
s->data_read_loop = false;
111
}
112
113
- DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
114
+ trace_m25p80_select(s, select ? "de" : "");
115
116
return 0;
117
}
118
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
119
Flash *s = M25P80(ss);
120
uint32_t r = 0;
121
122
+ trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
123
+ s->cur_addr, (uint8_t)tx);
124
+
125
switch (s->state) {
126
127
case STATE_PAGE_PROGRAM:
128
- DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
129
- s->cur_addr, (uint8_t)tx);
130
+ trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
131
flash_write8(s, s->cur_addr, (uint8_t)tx);
132
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
133
break;
134
135
case STATE_READ:
136
r = s->storage[s->cur_addr];
137
- DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
138
- (uint8_t)r);
139
+ trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
140
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
141
break;
142
143
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
144
}
145
146
r = s->data[s->pos];
147
+ trace_m25p80_read_data(s, s->pos, (uint8_t)r);
148
s->pos++;
149
if (s->pos == s->len) {
150
s->pos = 0;
151
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
152
return;
153
}
154
155
- DB_PRINT_L(0, "Binding to IF_MTD drive\n");
156
+ trace_m25p80_binding(s);
157
s->storage = blk_blockalign(s->blk, s->size);
158
159
if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
160
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
161
return;
162
}
163
} else {
164
- DB_PRINT_L(0, "No BDRV - binding to RAM\n");
165
+ trace_m25p80_binding_no_bdrv(s);
166
s->storage = blk_blockalign(NULL, s->size);
167
memset(s->storage, 0xFF, s->size);
168
}
169
diff --git a/hw/block/trace-events b/hw/block/trace-events
170
index XXXXXXX..XXXXXXX 100644
171
--- a/hw/block/trace-events
172
+++ b/hw/block/trace-events
173
@@ -XXX,XX +XXX,XX @@ xen_block_blockdev_add(char *str) "%s"
174
xen_block_blockdev_del(const char *node_name) "%s"
175
xen_block_device_create(unsigned int number) "%u"
176
xen_block_device_destroy(unsigned int number) "%u"
177
+
178
+# m25p80.c
179
+m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
180
+m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32" 0x%"PRIx8" -> 0x%"PRIx8
181
+m25p80_reset_done(void *s) "[%p] Reset done."
182
+m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
183
+m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
184
+m25p80_populated_jedec(void *s) "[%p] populated jedec code"
185
+m25p80_chip_erase(void *s) "[%p] chip erase"
186
+m25p80_select(void *s, const char *what) "[%p] %sselect"
187
+m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_addr=0x%"PRIx32" data=0x%"PRIx8
188
+m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
189
+m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
190
+m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
191
+m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
192
+m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
193
--
36
--
194
2.20.1
37
2.20.1
195
38
196
39
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
With this patch, the USB controllers on 'sabrelite' are detected
3
virt machine's 'smp_cpus' and machine->smp.cpus must always have the
4
and can be used to boot the system.
4
same value. And, anywhere we have virt machine state we have machine
5
state. So let's remove the redundancy. Also, to make it easier to see
6
that machine->smp is the true source for "smp_cpus" and "max_cpus",
7
avoid passing them in function parameters, preferring instead to get
8
them from the state.
5
9
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
10
No functional change intended.
7
Message-id: 20200313014551.12554-6-linux@roeck-us.net
11
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
14
Reviewed-by: Ying Fang <fangying1@huawei.com>
15
Message-id: 20201215174815.51520-1-drjones@redhat.com
16
[PMM: minor formatting tweak to smp_cpus variable declaration]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
18
---
11
include/hw/arm/fsl-imx6.h | 6 ++++++
19
include/hw/arm/virt.h | 3 +--
12
hw/arm/fsl-imx6.c | 36 ++++++++++++++++++++++++++++++++++++
20
hw/arm/virt-acpi-build.c | 9 +++++----
13
2 files changed, 42 insertions(+)
21
hw/arm/virt.c | 21 ++++++++++-----------
22
3 files changed, 16 insertions(+), 17 deletions(-)
14
23
15
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
24
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
16
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx6.h
26
--- a/include/hw/arm/virt.h
18
+++ b/include/hw/arm/fsl-imx6.h
27
+++ b/include/hw/arm/virt.h
28
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
29
MemMapEntry *memmap;
30
char *pciehb_nodename;
31
const int *irqmap;
32
- int smp_cpus;
33
void *fdt;
34
int fdt_size;
35
uint32_t clock_phandle;
36
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
37
38
assert(vms->gic_version == VIRT_GIC_VERSION_3);
39
40
- return vms->smp_cpus > redist0_capacity ? 2 : 1;
41
+ return MACHINE(vms)->smp.cpus > redist0_capacity ? 2 : 1;
42
}
43
44
#endif /* QEMU_ARM_VIRT_H */
45
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/virt-acpi-build.c
48
+++ b/hw/arm/virt-acpi-build.c
19
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@
20
#include "hw/sd/sdhci.h"
50
21
#include "hw/ssi/imx_spi.h"
51
#define ACPI_BUILD_TABLE_SIZE 0x20000
22
#include "hw/net/imx_fec.h"
52
23
+#include "hw/usb/chipidea.h"
53
-static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
24
+#include "hw/usb/imx-usb-phy.h"
54
+static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
25
#include "exec/memory.h"
55
{
26
#include "cpu.h"
56
+ MachineState *ms = MACHINE(vms);
27
57
uint16_t i;
28
@@ -XXX,XX +XXX,XX @@
58
29
#define FSL_IMX6_NUM_ESDHCS 4
59
- for (i = 0; i < smp_cpus; i++) {
30
#define FSL_IMX6_NUM_ECSPIS 5
60
+ for (i = 0; i < ms->smp.cpus; i++) {
31
#define FSL_IMX6_NUM_WDTS 2
61
Aml *dev = aml_device("C%.03X", i);
32
+#define FSL_IMX6_NUM_USB_PHYS 2
62
aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
33
+#define FSL_IMX6_NUM_USBS 4
63
aml_append(dev, aml_name_decl("_UID", aml_int(i)));
34
64
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
35
typedef struct FslIMX6State {
65
gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
36
/*< private >*/
66
gicd->version = vms->gic_version;
37
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
67
38
SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
68
- for (i = 0; i < vms->smp_cpus; i++) {
39
IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
69
+ for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
40
IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
70
AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
41
+ IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
71
sizeof(*gicc));
42
+ ChipideaState usb[FSL_IMX6_NUM_USBS];
72
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
43
IMXFECState eth;
73
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
44
MemoryRegion rom;
74
* the RTC ACPI device at all when using UEFI.
45
MemoryRegion caam;
75
*/
46
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
76
scope = aml_scope("\\_SB");
77
- acpi_dsdt_add_cpus(scope, vms->smp_cpus);
78
+ acpi_dsdt_add_cpus(scope, vms);
79
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
80
(irqmap[VIRT_UART] + ARM_SPI_BASE));
81
if (vmc->acpi_expose_flash) {
82
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
47
index XXXXXXX..XXXXXXX 100644
83
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/fsl-imx6.c
84
--- a/hw/arm/virt.c
49
+++ b/hw/arm/fsl-imx6.c
85
+++ b/hw/arm/virt.c
50
@@ -XXX,XX +XXX,XX @@
86
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
51
#include "qemu/osdep.h"
87
if (vms->gic_version == VIRT_GIC_VERSION_2) {
52
#include "qapi/error.h"
88
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
53
#include "hw/arm/fsl-imx6.h"
89
GIC_FDT_IRQ_PPI_CPU_WIDTH,
54
+#include "hw/usb/imx-usb-phy.h"
90
- (1 << vms->smp_cpus) - 1);
55
#include "hw/boards.h"
91
+ (1 << MACHINE(vms)->smp.cpus) - 1);
56
#include "hw/qdev-properties.h"
57
#include "sysemu/sysemu.h"
58
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
59
TYPE_IMX_USDHC);
60
}
92
}
61
93
62
+ for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
94
qemu_fdt_add_subnode(vms->fdt, "/timer");
63
+ snprintf(name, NAME_SIZE, "usbphy%d", i);
95
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
64
+ sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
96
int cpu;
65
+ TYPE_IMX_USBPHY);
97
int addr_cells = 1;
66
+ }
98
const MachineState *ms = MACHINE(vms);
67
+ for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
99
+ int smp_cpus = ms->smp.cpus;
68
+ snprintf(name, NAME_SIZE, "usb%d", i);
100
69
+ sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
101
/*
70
+ TYPE_CHIPIDEA);
102
* From Documentation/devicetree/bindings/arm/cpus.txt
71
+ }
103
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
72
+
104
* The simplest way to go is to examine affinity IDs of all our CPUs. If
73
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
105
* at least one of them has Aff3 populated, we set #address-cells to 2.
74
snprintf(name, NAME_SIZE, "spi%d", i + 1);
106
*/
75
sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
107
- for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
76
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
108
+ for (cpu = 0; cpu < smp_cpus; cpu++) {
77
esdhc_table[i].irq));
109
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
110
111
if (armcpu->mp_affinity & ARM_AFF3_MASK) {
112
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
113
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
114
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
115
116
- for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
117
+ for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
118
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
119
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
120
CPUState *cs = CPU(armcpu);
121
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
122
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
123
armcpu->dtb_compatible);
124
125
- if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
126
- && vms->smp_cpus > 1) {
127
+ if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
128
qemu_fdt_setprop_string(vms->fdt, nodename,
129
"enable-method", "psci");
130
}
131
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
132
if (vms->gic_version == VIRT_GIC_VERSION_2) {
133
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
134
GIC_FDT_IRQ_PPI_CPU_WIDTH,
135
- (1 << vms->smp_cpus) - 1);
136
+ (1 << MACHINE(vms)->smp.cpus) - 1);
78
}
137
}
79
138
80
+ /* USB */
139
qemu_fdt_add_subnode(vms->fdt, "/pmu");
81
+ for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
140
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
82
+ object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
141
* virt_cpu_post_init() must be called after the CPUs have
83
+ &error_abort);
142
* been realized and the GIC has been created.
84
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
143
*/
85
+ FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
144
-static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
86
+ }
145
- MemoryRegion *sysmem)
87
+ for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
146
+static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
88
+ static const int FSL_IMX6_USBn_IRQ[] = {
147
{
89
+ FSL_IMX6_USB_OTG_IRQ,
148
+ int max_cpus = MACHINE(vms)->smp.max_cpus;
90
+ FSL_IMX6_USB_HOST1_IRQ,
149
bool aarch64, pmu, steal_time;
91
+ FSL_IMX6_USB_HOST2_IRQ,
150
CPUState *cpu;
92
+ FSL_IMX6_USB_HOST3_IRQ,
151
93
+ };
152
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
94
+
153
exit(1);
95
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
154
}
96
+ &error_abort);
155
97
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
156
- vms->smp_cpus = smp_cpus;
98
+ FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
157
-
99
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
158
if (vms->virt && kvm_enabled()) {
100
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
159
error_report("mach-virt: KVM does not support providing "
101
+ FSL_IMX6_USBn_IRQ[i]));
160
"Virtualization extensions to the guest CPU");
102
+ }
161
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
103
+
162
create_fdt(vms);
104
/* Initialize all ECSPI */
163
105
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
164
possible_cpus = mc->possible_cpu_arch_ids(machine);
106
static const struct {
165
+ assert(possible_cpus->len == max_cpus);
166
for (n = 0; n < possible_cpus->len; n++) {
167
Object *cpuobj;
168
CPUState *cs;
169
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
170
171
create_gic(vms);
172
173
- virt_cpu_post_init(vms, possible_cpus->len, sysmem);
174
+ virt_cpu_post_init(vms, sysmem);
175
176
fdt_add_pmu_nodes(vms);
177
107
--
178
--
108
2.20.1
179
2.20.1
109
180
110
181
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
In 50244cc76abc we updated mte_check_fail to match the ARM
4
pseudocode, using the correct EL to select the TCF field.
5
But we failed to update MTE0_ACTIVE the same way, which led
6
to g_assert_not_reached().
7
8
Cc: qemu-stable@nongnu.org
9
Buglink: https://bugs.launchpad.net/bugs/1907137
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20201221204426.88514-1-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/helper.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
23
if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
24
&& tbid
25
&& !(env->pstate & PSTATE_TCO)
26
- && (sctlr & SCTLR_TCF0)
27
+ && (sctlr & SCTLR_TCF)
28
&& allocation_tag_access_enabled(env, 0, sctlr)) {
29
flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
30
}
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
New patch
1
The CCR is a register most of whose bits are banked between security
2
states but where BFHFNMIGN is not, and we keep it in the non-secure
3
entry of the v7m.ccr[] array. The logic which tries to handle this
4
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
5
is zero" requirement; correct the omission.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201210201433.26262-2-peter.maydell@linaro.org
10
---
11
hw/intc/armv7m_nvic.c | 15 +++++++++++++++
12
1 file changed, 15 insertions(+)
13
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
19
*/
20
val = cpu->env.v7m.ccr[attrs.secure];
21
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
22
+ /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */
23
+ if (!attrs.secure) {
24
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
25
+ val &= ~R_V7M_CCR_BFHFNMIGN_MASK;
26
+ }
27
+ }
28
return val;
29
case 0xd24: /* System Handler Control and State (SHCSR) */
30
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
31
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
32
(cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)
33
| (value & R_V7M_CCR_BFHFNMIGN_MASK);
34
value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
35
+ } else {
36
+ /*
37
+ * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so
38
+ * preserve the state currently in the NS element of the array
39
+ */
40
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
41
+ value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
42
+ value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
43
+ }
44
}
45
46
cpu->env.v7m.ccr[attrs.secure] = value;
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
New patch
1
In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register,
2
but we got the write behaviour wrong. On read, this register reads
3
bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't
4
just write back those bits -- it writes a value to the whole FPSCR,
5
whose upper 4 bits are zeroes.
1
6
7
We also incorrectly implemented the write-to-FPSCR as a simple store
8
to vfp.xregs; this skips the "update the softfloat flags" part of
9
the vfp_set_fpscr helper so the value would read back correctly but
10
not actually take effect.
11
12
Fix both of these things by doing a complete write to the FPSCR
13
using the helper function.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20201210201433.26262-3-peter.maydell@linaro.org
18
---
19
target/arm/translate-vfp.c.inc | 12 ++++++------
20
1 file changed, 6 insertions(+), 6 deletions(-)
21
22
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-vfp.c.inc
25
+++ b/target/arm/translate-vfp.c.inc
26
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
27
}
28
case ARM_VFP_FPCXT_S:
29
{
30
- TCGv_i32 sfpa, control, fpscr;
31
- /* Set FPSCR[27:0] and CONTROL.SFPA from value */
32
+ TCGv_i32 sfpa, control;
33
+ /*
34
+ * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes
35
+ * bits [27:0] from value and zeroes bits [31:28].
36
+ */
37
tmp = loadfn(s, opaque);
38
sfpa = tcg_temp_new_i32();
39
tcg_gen_shri_i32(sfpa, tmp, 31);
40
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
41
tcg_gen_deposit_i32(control, control, sfpa,
42
R_V7M_CONTROL_SFPA_SHIFT, 1);
43
store_cpu_field(control, v7m.control[M_REG_S]);
44
- fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
45
- tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
46
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
47
- tcg_gen_or_i32(fpscr, fpscr, tmp);
48
- store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
49
+ gen_helper_vfp_set_fpscr(cpu_env, tmp);
50
tcg_temp_free_i32(tmp);
51
tcg_temp_free_i32(sfpa);
52
break;
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
New patch
1
Implement the v8.1M FPCXT_NS floating-point system register. This is
2
a little more complicated than FPCXT_S, because it has specific
3
handling for "current FP state is inactive", and it only wants to do
4
PreserveFPState(), not the full set of actions done by
5
ExecuteFPCheck() which vfp_access_check() implements.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201210201433.26262-4-peter.maydell@linaro.org
10
---
11
target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++-
12
1 file changed, 99 insertions(+), 3 deletions(-)
13
14
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-vfp.c.inc
17
+++ b/target/arm/translate-vfp.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
19
}
20
break;
21
case ARM_VFP_FPCXT_S:
22
+ case ARM_VFP_FPCXT_NS:
23
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
24
return false;
25
}
26
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
27
return FPSysRegCheckFailed;
28
}
29
30
- if (!vfp_access_check(s)) {
31
+ /*
32
+ * FPCXT_NS is a special case: it has specific handling for
33
+ * "current FP state is inactive", and must do the PreserveFPState()
34
+ * but not the usual full set of actions done by ExecuteFPCheck().
35
+ * So we don't call vfp_access_check() and the callers must handle this.
36
+ */
37
+ if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) {
38
return FPSysRegCheckDone;
39
}
40
-
41
return FPSysRegCheckContinue;
42
}
43
44
+static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
45
+ TCGLabel *label)
46
+{
47
+ /*
48
+ * FPCXT_NS is a special case: it has specific handling for
49
+ * "current FP state is inactive", and must do the PreserveFPState()
50
+ * but not the usual full set of actions done by ExecuteFPCheck().
51
+ * We don't have a TB flag that matches the fpInactive check, so we
52
+ * do it at runtime as we don't expect FPCXT_NS accesses to be frequent.
53
+ *
54
+ * Emit code that checks fpInactive and does a conditional
55
+ * branch to label based on it:
56
+ * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive)
57
+ * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active)
58
+ */
59
+ assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);
60
+
61
+ /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */
62
+ TCGv_i32 aspen, fpca;
63
+ aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);
64
+ fpca = load_cpu_field(v7m.control[M_REG_S]);
65
+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
66
+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
67
+ tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);
68
+ tcg_gen_or_i32(fpca, fpca, aspen);
69
+ tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);
70
+ tcg_temp_free_i32(aspen);
71
+ tcg_temp_free_i32(fpca);
72
+}
73
+
74
static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
75
76
fp_sysreg_loadfn *loadfn,
77
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
78
{
79
/* Do a write to an M-profile floating point system register */
80
TCGv_i32 tmp;
81
+ TCGLabel *lab_end = NULL;
82
83
switch (fp_sysreg_checks(s, regno)) {
84
case FPSysRegCheckFailed:
85
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
86
tcg_temp_free_i32(tmp);
87
break;
88
}
89
+ case ARM_VFP_FPCXT_NS:
90
+ lab_end = gen_new_label();
91
+ /* fpInactive case: write is a NOP, so branch to end */
92
+ gen_branch_fpInactive(s, TCG_COND_NE, lab_end);
93
+ /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */
94
+ gen_preserve_fp_state(s);
95
+ /* fall through */
96
case ARM_VFP_FPCXT_S:
97
{
98
TCGv_i32 sfpa, control;
99
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
100
default:
101
g_assert_not_reached();
102
}
103
+ if (lab_end) {
104
+ gen_set_label(lab_end);
105
+ }
106
return true;
107
}
108
109
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
110
{
111
/* Do a read from an M-profile floating point system register */
112
TCGv_i32 tmp;
113
+ TCGLabel *lab_end = NULL;
114
+ bool lookup_tb = false;
115
116
switch (fp_sysreg_checks(s, regno)) {
117
case FPSysRegCheckFailed:
118
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
119
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
120
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
121
tcg_temp_free_i32(fpscr);
122
- gen_lookup_tb(s);
123
+ lookup_tb = true;
124
+ break;
125
+ }
126
+ case ARM_VFP_FPCXT_NS:
127
+ {
128
+ TCGv_i32 control, sfpa, fpscr, fpdscr, zero;
129
+ TCGLabel *lab_active = gen_new_label();
130
+
131
+ lookup_tb = true;
132
+
133
+ gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
134
+ /* fpInactive case: reads as FPDSCR_NS */
135
+ TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
136
+ storefn(s, opaque, tmp);
137
+ lab_end = gen_new_label();
138
+ tcg_gen_br(lab_end);
139
+
140
+ gen_set_label(lab_active);
141
+ /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */
142
+ gen_preserve_fp_state(s);
143
+ tmp = tcg_temp_new_i32();
144
+ sfpa = tcg_temp_new_i32();
145
+ fpscr = tcg_temp_new_i32();
146
+ gen_helper_vfp_get_fpscr(fpscr, cpu_env);
147
+ tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
148
+ control = load_cpu_field(v7m.control[M_REG_S]);
149
+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
150
+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
151
+ tcg_gen_or_i32(tmp, tmp, sfpa);
152
+ tcg_temp_free_i32(control);
153
+ /* Store result before updating FPSCR, in case it faults */
154
+ storefn(s, opaque, tmp);
155
+ /* If SFPA is zero then set FPSCR from FPDSCR_NS */
156
+ fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
157
+ zero = tcg_const_i32(0);
158
+ tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr);
159
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
160
+ tcg_temp_free_i32(zero);
161
+ tcg_temp_free_i32(sfpa);
162
+ tcg_temp_free_i32(fpdscr);
163
+ tcg_temp_free_i32(fpscr);
164
break;
165
}
166
default:
167
g_assert_not_reached();
168
}
169
+
170
+ if (lab_end) {
171
+ gen_set_label(lab_end);
172
+ }
173
+ if (lookup_tb) {
174
+ gen_lookup_tb(s);
175
+ }
176
return true;
177
}
178
179
--
180
2.20.1
181
182
diff view generated by jsdifflib
New patch
1
Now that we have implemented all the features needed by the v8.1M
2
architecture, we can add the model of the Cortex-M55. This is the
3
configuration without MVE support; we'll add MVE later.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201210201433.26262-5-peter.maydell@linaro.org
8
---
9
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 42 insertions(+)
11
12
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu_tcg.c
15
+++ b/target/arm/cpu_tcg.c
16
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
17
cpu->ctr = 0x8000c000;
18
}
19
20
+static void cortex_m55_initfn(Object *obj)
21
+{
22
+ ARMCPU *cpu = ARM_CPU(obj);
23
+
24
+ set_feature(&cpu->env, ARM_FEATURE_V8);
25
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
26
+ set_feature(&cpu->env, ARM_FEATURE_M);
27
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
28
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
29
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
30
+ cpu->midr = 0x410fd221; /* r0p1 */
31
+ cpu->revidr = 0;
32
+ cpu->pmsav7_dregion = 16;
33
+ cpu->sau_sregion = 8;
34
+ /*
35
+ * These are the MVFR* values for the FPU, no MVE configuration;
36
+ * we will update them later when we implement MVE
37
+ */
38
+ cpu->isar.mvfr0 = 0x10110221;
39
+ cpu->isar.mvfr1 = 0x12100011;
40
+ cpu->isar.mvfr2 = 0x00000040;
41
+ cpu->isar.id_pfr0 = 0x20000030;
42
+ cpu->isar.id_pfr1 = 0x00000230;
43
+ cpu->isar.id_dfr0 = 0x10200000;
44
+ cpu->id_afr0 = 0x00000000;
45
+ cpu->isar.id_mmfr0 = 0x00111040;
46
+ cpu->isar.id_mmfr1 = 0x00000000;
47
+ cpu->isar.id_mmfr2 = 0x01000000;
48
+ cpu->isar.id_mmfr3 = 0x00000011;
49
+ cpu->isar.id_isar0 = 0x01103110;
50
+ cpu->isar.id_isar1 = 0x02212000;
51
+ cpu->isar.id_isar2 = 0x20232232;
52
+ cpu->isar.id_isar3 = 0x01111131;
53
+ cpu->isar.id_isar4 = 0x01310132;
54
+ cpu->isar.id_isar5 = 0x00000000;
55
+ cpu->isar.id_isar6 = 0x00000000;
56
+ cpu->clidr = 0x00000000; /* caches not implemented */
57
+ cpu->ctr = 0x8303c003;
58
+}
59
+
60
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
61
/* Dummy the TCM region regs for the moment */
62
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
64
.class_init = arm_v7m_class_init },
65
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
66
.class_init = arm_v7m_class_init },
67
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
68
+ .class_init = arm_v7m_class_init },
69
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
70
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
71
{ .name = "ti925t", .initfn = ti925t_initfn },
72
--
73
2.20.1
74
75
diff view generated by jsdifflib
New patch
1
Support for running KVM on 32-bit Arm hosts was removed in commit
2
82bf7ae84ce739e. You can still run a 32-bit guest on a 64-bit Arm
3
host CPU, but because Arm KVM requires the host and guest CPU types
4
to match, it is not possible to run a guest that requires a Cortex-A9
5
or Cortex-A15 CPU there. That means that the code in the
6
highbank/midway board models to support KVM is no longer used, and we
7
can delete it.
1
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201215144215.28482-1-peter.maydell@linaro.org
13
---
14
hw/arm/highbank.c | 14 ++++----------
15
1 file changed, 4 insertions(+), 10 deletions(-)
16
17
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/highbank.c
20
+++ b/hw/arm/highbank.c
21
@@ -XXX,XX +XXX,XX @@
22
#include "hw/arm/boot.h"
23
#include "hw/loader.h"
24
#include "net/net.h"
25
-#include "sysemu/kvm.h"
26
#include "sysemu/runstate.h"
27
#include "sysemu/sysemu.h"
28
#include "hw/boards.h"
29
@@ -XXX,XX +XXX,XX @@
30
#include "hw/cpu/a15mpcore.h"
31
#include "qemu/log.h"
32
#include "qom/object.h"
33
+#include "cpu.h"
34
35
#define SMP_BOOT_ADDR 0x100
36
#define SMP_BOOT_REG 0x40
37
@@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
38
highbank_binfo.loader_start = 0;
39
highbank_binfo.write_secondary_boot = hb_write_secondary;
40
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
41
- if (!kvm_enabled()) {
42
- highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
43
- highbank_binfo.write_board_setup = hb_write_board_setup;
44
- highbank_binfo.secure_board_setup = true;
45
- } else {
46
- warn_report("cannot load built-in Monitor support "
47
- "if KVM is enabled. Some guests (such as Linux) "
48
- "may not boot.");
49
- }
50
+ highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
51
+ highbank_binfo.write_board_setup = hb_write_board_setup;
52
+ highbank_binfo.secure_board_setup = true;
53
54
arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
55
}
56
--
57
2.20.1
58
59
diff view generated by jsdifflib
New patch
1
Currently timer_free() is a simple wrapper for g_free(). This means
2
that the timer being freed must not be currently active, as otherwise
3
QEMU might crash later when the active list is processed and still
4
has a pointer to freed memory on it. As a result almost all calls to
5
timer_free() are preceded by a timer_del() call, as can be seen in
6
the output of
7
git grep -B1 '\<timer_free\>'
1
8
9
This is unfortunate API design as it makes it easy to accidentally
10
misuse (by forgetting the timer_del()), and the correct use is
11
annoyingly verbose.
12
13
Make timer_free() imply a timer_del().
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20201215154107.3255-2-peter.maydell@linaro.org
19
---
20
include/qemu/timer.h | 24 +++++++++++++-----------
21
1 file changed, 13 insertions(+), 11 deletions(-)
22
23
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/qemu/timer.h
26
+++ b/include/qemu/timer.h
27
@@ -XXX,XX +XXX,XX @@ static inline QEMUTimer *timer_new_ms(QEMUClockType type, QEMUTimerCB *cb,
28
*/
29
void timer_deinit(QEMUTimer *ts);
30
31
-/**
32
- * timer_free:
33
- * @ts: the timer
34
- *
35
- * Free a timer (it must not be on the active list)
36
- */
37
-static inline void timer_free(QEMUTimer *ts)
38
-{
39
- g_free(ts);
40
-}
41
-
42
/**
43
* timer_del:
44
* @ts: the timer
45
@@ -XXX,XX +XXX,XX @@ static inline void timer_free(QEMUTimer *ts)
46
*/
47
void timer_del(QEMUTimer *ts);
48
49
+/**
50
+ * timer_free:
51
+ * @ts: the timer
52
+ *
53
+ * Free a timer. This will call timer_del() for you to remove
54
+ * the timer from the active list if it was still active.
55
+ */
56
+static inline void timer_free(QEMUTimer *ts)
57
+{
58
+ timer_del(ts);
59
+ g_free(ts);
60
+}
61
+
62
/**
63
* timer_mod_ns:
64
* @ts: the timer
65
--
66
2.20.1
67
68
diff view generated by jsdifflib
New patch
1
Now that timer_free() implicitly calls timer_del(), sequences
2
timer_del(mytimer);
3
timer_free(mytimer);
1
4
5
can be simplified to just
6
timer_free(mytimer);
7
8
Add a Coccinelle script to do this transformation.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20201215154107.3255-3-peter.maydell@linaro.org
15
---
16
scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++++++++++++++++
17
1 file changed, 18 insertions(+)
18
create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci
19
20
diff --git a/scripts/coccinelle/timer-del-timer-free.cocci b/scripts/coccinelle/timer-del-timer-free.cocci
21
new file mode 100644
22
index XXXXXXX..XXXXXXX
23
--- /dev/null
24
+++ b/scripts/coccinelle/timer-del-timer-free.cocci
25
@@ -XXX,XX +XXX,XX @@
26
+// Remove superfluous timer_del() calls
27
+//
28
+// Copyright Linaro Limited 2020
29
+// This work is licensed under the terms of the GNU GPLv2 or later.
30
+//
31
+// spatch --macro-file scripts/cocci-macro-file.h \
32
+// --sp-file scripts/coccinelle/timer-del-timer-free.cocci \
33
+// --in-place --dir .
34
+//
35
+// The timer_free() function now implicitly calls timer_del()
36
+// for you, so calls to timer_del() immediately before the
37
+// timer_free() of the same timer can be deleted.
38
+
39
+@@
40
+expression T;
41
+@@
42
+-timer_del(T);
43
+ timer_free(T);
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
New patch
1
This commit is the result of running the timer-del-timer-free.cocci
2
script on the whole source tree.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Acked-by: Corey Minyard <cminyard@mvista.com>
6
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201215154107.3255-4-peter.maydell@linaro.org
10
---
11
block/iscsi.c | 2 --
12
block/nbd.c | 1 -
13
block/qcow2.c | 1 -
14
hw/block/nvme.c | 2 --
15
hw/char/serial.c | 2 --
16
hw/char/virtio-serial-bus.c | 2 --
17
hw/ide/core.c | 1 -
18
hw/input/hid.c | 1 -
19
hw/intc/apic.c | 1 -
20
hw/intc/ioapic.c | 1 -
21
hw/ipmi/ipmi_bmc_extern.c | 1 -
22
hw/net/e1000.c | 3 ---
23
hw/net/e1000e_core.c | 8 --------
24
hw/net/pcnet-pci.c | 1 -
25
hw/net/rtl8139.c | 1 -
26
hw/net/spapr_llan.c | 1 -
27
hw/net/virtio-net.c | 2 --
28
hw/s390x/s390-pci-inst.c | 1 -
29
hw/sd/sd.c | 1 -
30
hw/sd/sdhci.c | 2 --
31
hw/usb/dev-hub.c | 1 -
32
hw/usb/hcd-ehci.c | 1 -
33
hw/usb/hcd-ohci-pci.c | 1 -
34
hw/usb/hcd-uhci.c | 1 -
35
hw/usb/hcd-xhci.c | 1 -
36
hw/usb/redirect.c | 1 -
37
hw/vfio/display.c | 1 -
38
hw/virtio/vhost-vsock-common.c | 1 -
39
hw/virtio/virtio-balloon.c | 1 -
40
hw/virtio/virtio-rng.c | 1 -
41
hw/watchdog/wdt_diag288.c | 1 -
42
hw/watchdog/wdt_i6300esb.c | 1 -
43
migration/colo.c | 1 -
44
monitor/hmp-cmds.c | 1 -
45
net/announce.c | 1 -
46
net/colo-compare.c | 1 -
47
net/slirp.c | 1 -
48
replay/replay-debugging.c | 1 -
49
target/s390x/cpu.c | 2 --
50
ui/console.c | 1 -
51
ui/spice-core.c | 1 -
52
util/throttle.c | 1 -
53
42 files changed, 58 deletions(-)
54
55
diff --git a/block/iscsi.c b/block/iscsi.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/block/iscsi.c
58
+++ b/block/iscsi.c
59
@@ -XXX,XX +XXX,XX @@ static void iscsi_detach_aio_context(BlockDriverState *bs)
60
iscsilun->events = 0;
61
62
if (iscsilun->nop_timer) {
63
- timer_del(iscsilun->nop_timer);
64
timer_free(iscsilun->nop_timer);
65
iscsilun->nop_timer = NULL;
66
}
67
if (iscsilun->event_timer) {
68
- timer_del(iscsilun->event_timer);
69
timer_free(iscsilun->event_timer);
70
iscsilun->event_timer = NULL;
71
}
72
diff --git a/block/nbd.c b/block/nbd.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/block/nbd.c
75
+++ b/block/nbd.c
76
@@ -XXX,XX +XXX,XX @@ static void nbd_recv_coroutines_wake_all(BDRVNBDState *s)
77
static void reconnect_delay_timer_del(BDRVNBDState *s)
78
{
79
if (s->reconnect_delay_timer) {
80
- timer_del(s->reconnect_delay_timer);
81
timer_free(s->reconnect_delay_timer);
82
s->reconnect_delay_timer = NULL;
83
}
84
diff --git a/block/qcow2.c b/block/qcow2.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/block/qcow2.c
87
+++ b/block/qcow2.c
88
@@ -XXX,XX +XXX,XX @@ static void cache_clean_timer_del(BlockDriverState *bs)
89
{
90
BDRVQcow2State *s = bs->opaque;
91
if (s->cache_clean_timer) {
92
- timer_del(s->cache_clean_timer);
93
timer_free(s->cache_clean_timer);
94
s->cache_clean_timer = NULL;
95
}
96
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/hw/block/nvme.c
99
+++ b/hw/block/nvme.c
100
@@ -XXX,XX +XXX,XX @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
101
static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
102
{
103
n->sq[sq->sqid] = NULL;
104
- timer_del(sq->timer);
105
timer_free(sq->timer);
106
g_free(sq->io_req);
107
if (sq->sqid) {
108
@@ -XXX,XX +XXX,XX @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
109
static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
110
{
111
n->cq[cq->cqid] = NULL;
112
- timer_del(cq->timer);
113
timer_free(cq->timer);
114
msix_vector_unuse(&n->parent_obj, cq->vector);
115
if (cq->cqid) {
116
diff --git a/hw/char/serial.c b/hw/char/serial.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/char/serial.c
119
+++ b/hw/char/serial.c
120
@@ -XXX,XX +XXX,XX @@ static void serial_unrealize(DeviceState *dev)
121
122
qemu_chr_fe_deinit(&s->chr, false);
123
124
- timer_del(s->modem_status_poll);
125
timer_free(s->modem_status_poll);
126
127
- timer_del(s->fifo_timeout_timer);
128
timer_free(s->fifo_timeout_timer);
129
130
fifo8_destroy(&s->recv_fifo);
131
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/char/virtio-serial-bus.c
134
+++ b/hw/char/virtio-serial-bus.c
135
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_post_load_timer_cb(void *opaque)
136
}
137
}
138
g_free(s->post_load->connected);
139
- timer_del(s->post_load->timer);
140
timer_free(s->post_load->timer);
141
g_free(s->post_load);
142
s->post_load = NULL;
143
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_unrealize(DeviceState *dev)
144
g_free(vser->ports_map);
145
if (vser->post_load) {
146
g_free(vser->post_load->connected);
147
- timer_del(vser->post_load->timer);
148
timer_free(vser->post_load->timer);
149
g_free(vser->post_load);
150
}
151
diff --git a/hw/ide/core.c b/hw/ide/core.c
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/ide/core.c
154
+++ b/hw/ide/core.c
155
@@ -XXX,XX +XXX,XX @@ void ide_init2(IDEBus *bus, qemu_irq irq)
156
157
void ide_exit(IDEState *s)
158
{
159
- timer_del(s->sector_write_timer);
160
timer_free(s->sector_write_timer);
161
qemu_vfree(s->smart_selftest_data);
162
qemu_vfree(s->io_buffer);
163
diff --git a/hw/input/hid.c b/hw/input/hid.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/input/hid.c
166
+++ b/hw/input/hid.c
167
@@ -XXX,XX +XXX,XX @@ static void hid_idle_timer(void *opaque)
168
static void hid_del_idle_timer(HIDState *hs)
169
{
170
if (hs->idle_timer) {
171
- timer_del(hs->idle_timer);
172
timer_free(hs->idle_timer);
173
hs->idle_timer = NULL;
174
}
175
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/intc/apic.c
178
+++ b/hw/intc/apic.c
179
@@ -XXX,XX +XXX,XX @@ static void apic_unrealize(DeviceState *dev)
180
{
181
APICCommonState *s = APIC(dev);
182
183
- timer_del(s->timer);
184
timer_free(s->timer);
185
local_apics[s->id] = NULL;
186
}
187
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
188
index XXXXXXX..XXXXXXX 100644
189
--- a/hw/intc/ioapic.c
190
+++ b/hw/intc/ioapic.c
191
@@ -XXX,XX +XXX,XX @@ static void ioapic_unrealize(DeviceState *dev)
192
{
193
IOAPICCommonState *s = IOAPIC_COMMON(dev);
194
195
- timer_del(s->delayed_ioapic_service_timer);
196
timer_free(s->delayed_ioapic_service_timer);
197
}
198
199
diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/ipmi/ipmi_bmc_extern.c
202
+++ b/hw/ipmi/ipmi_bmc_extern.c
203
@@ -XXX,XX +XXX,XX @@ static void ipmi_bmc_extern_finalize(Object *obj)
204
{
205
IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj);
206
207
- timer_del(ibe->extern_timer);
208
timer_free(ibe->extern_timer);
209
}
210
211
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/net/e1000.c
214
+++ b/hw/net/e1000.c
215
@@ -XXX,XX +XXX,XX @@ pci_e1000_uninit(PCIDevice *dev)
216
{
217
E1000State *d = E1000(dev);
218
219
- timer_del(d->autoneg_timer);
220
timer_free(d->autoneg_timer);
221
- timer_del(d->mit_timer);
222
timer_free(d->mit_timer);
223
- timer_del(d->flush_queue_timer);
224
timer_free(d->flush_queue_timer);
225
qemu_del_nic(d->nic);
226
}
227
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/net/e1000e_core.c
230
+++ b/hw/net/e1000e_core.c
231
@@ -XXX,XX +XXX,XX @@ e1000e_intrmgr_pci_unint(E1000ECore *core)
232
{
233
int i;
234
235
- timer_del(core->radv.timer);
236
timer_free(core->radv.timer);
237
- timer_del(core->rdtr.timer);
238
timer_free(core->rdtr.timer);
239
- timer_del(core->raid.timer);
240
timer_free(core->raid.timer);
241
242
- timer_del(core->tadv.timer);
243
timer_free(core->tadv.timer);
244
- timer_del(core->tidv.timer);
245
timer_free(core->tidv.timer);
246
247
- timer_del(core->itr.timer);
248
timer_free(core->itr.timer);
249
250
for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
251
- timer_del(core->eitr[i].timer);
252
timer_free(core->eitr[i].timer);
253
}
254
}
255
@@ -XXX,XX +XXX,XX @@ e1000e_core_pci_uninit(E1000ECore *core)
256
{
257
int i;
258
259
- timer_del(core->autoneg_timer);
260
timer_free(core->autoneg_timer);
261
262
e1000e_intrmgr_pci_unint(core);
263
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
264
index XXXXXXX..XXXXXXX 100644
265
--- a/hw/net/pcnet-pci.c
266
+++ b/hw/net/pcnet-pci.c
267
@@ -XXX,XX +XXX,XX @@ static void pci_pcnet_uninit(PCIDevice *dev)
268
PCIPCNetState *d = PCI_PCNET(dev);
269
270
qemu_free_irq(d->state.irq);
271
- timer_del(d->state.poll_timer);
272
timer_free(d->state.poll_timer);
273
qemu_del_nic(d->state.nic);
274
}
275
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
276
index XXXXXXX..XXXXXXX 100644
277
--- a/hw/net/rtl8139.c
278
+++ b/hw/net/rtl8139.c
279
@@ -XXX,XX +XXX,XX @@ static void pci_rtl8139_uninit(PCIDevice *dev)
280
281
g_free(s->cplus_txbuffer);
282
s->cplus_txbuffer = NULL;
283
- timer_del(s->timer);
284
timer_free(s->timer);
285
qemu_del_nic(s->nic);
286
}
287
diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/net/spapr_llan.c
290
+++ b/hw/net/spapr_llan.c
291
@@ -XXX,XX +XXX,XX @@ static void spapr_vlan_instance_finalize(Object *obj)
292
}
293
294
if (dev->rxp_timer) {
295
- timer_del(dev->rxp_timer);
296
timer_free(dev->rxp_timer);
297
}
298
}
299
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
300
index XXXXXXX..XXXXXXX 100644
301
--- a/hw/net/virtio-net.c
302
+++ b/hw/net/virtio-net.c
303
@@ -XXX,XX +XXX,XX @@ static void virtio_net_rsc_cleanup(VirtIONet *n)
304
g_free(seg);
305
}
306
307
- timer_del(chain->drain_timer);
308
timer_free(chain->drain_timer);
309
QTAILQ_REMOVE(&n->rsc_chains, chain, next);
310
g_free(chain);
311
@@ -XXX,XX +XXX,XX @@ static void virtio_net_del_queue(VirtIONet *n, int index)
312
313
virtio_del_queue(vdev, index * 2);
314
if (q->tx_timer) {
315
- timer_del(q->tx_timer);
316
timer_free(q->tx_timer);
317
q->tx_timer = NULL;
318
} else {
319
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/s390x/s390-pci-inst.c
322
+++ b/hw/s390x/s390-pci-inst.c
323
@@ -XXX,XX +XXX,XX @@ void pci_dereg_ioat(S390PCIIOMMU *iommu)
324
void fmb_timer_free(S390PCIBusDevice *pbdev)
325
{
326
if (pbdev->fmb_timer) {
327
- timer_del(pbdev->fmb_timer);
328
timer_free(pbdev->fmb_timer);
329
pbdev->fmb_timer = NULL;
330
}
331
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
332
index XXXXXXX..XXXXXXX 100644
333
--- a/hw/sd/sd.c
334
+++ b/hw/sd/sd.c
335
@@ -XXX,XX +XXX,XX @@ static void sd_instance_finalize(Object *obj)
336
{
337
SDState *sd = SD_CARD(obj);
338
339
- timer_del(sd->ocr_power_timer);
340
timer_free(sd->ocr_power_timer);
341
}
342
343
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
344
index XXXXXXX..XXXXXXX 100644
345
--- a/hw/sd/sdhci.c
346
+++ b/hw/sd/sdhci.c
347
@@ -XXX,XX +XXX,XX @@ void sdhci_initfn(SDHCIState *s)
348
349
void sdhci_uninitfn(SDHCIState *s)
350
{
351
- timer_del(s->insert_timer);
352
timer_free(s->insert_timer);
353
- timer_del(s->transfer_timer);
354
timer_free(s->transfer_timer);
355
356
g_free(s->fifo_buffer);
357
diff --git a/hw/usb/dev-hub.c b/hw/usb/dev-hub.c
358
index XXXXXXX..XXXXXXX 100644
359
--- a/hw/usb/dev-hub.c
360
+++ b/hw/usb/dev-hub.c
361
@@ -XXX,XX +XXX,XX @@ static void usb_hub_unrealize(USBDevice *dev)
362
&s->ports[i].port);
363
}
364
365
- timer_del(s->port_timer);
366
timer_free(s->port_timer);
367
}
368
369
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
370
index XXXXXXX..XXXXXXX 100644
371
--- a/hw/usb/hcd-ehci.c
372
+++ b/hw/usb/hcd-ehci.c
373
@@ -XXX,XX +XXX,XX @@ void usb_ehci_unrealize(EHCIState *s, DeviceState *dev)
374
trace_usb_ehci_unrealize();
375
376
if (s->frame_timer) {
377
- timer_del(s->frame_timer);
378
timer_free(s->frame_timer);
379
s->frame_timer = NULL;
380
}
381
diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c
382
index XXXXXXX..XXXXXXX 100644
383
--- a/hw/usb/hcd-ohci-pci.c
384
+++ b/hw/usb/hcd-ohci-pci.c
385
@@ -XXX,XX +XXX,XX @@ static void usb_ohci_exit(PCIDevice *dev)
386
usb_bus_release(&s->bus);
387
}
388
389
- timer_del(s->eof_timer);
390
timer_free(s->eof_timer);
391
}
392
393
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
394
index XXXXXXX..XXXXXXX 100644
395
--- a/hw/usb/hcd-uhci.c
396
+++ b/hw/usb/hcd-uhci.c
397
@@ -XXX,XX +XXX,XX @@ static void usb_uhci_exit(PCIDevice *dev)
398
trace_usb_uhci_exit();
399
400
if (s->frame_timer) {
401
- timer_del(s->frame_timer);
402
timer_free(s->frame_timer);
403
s->frame_timer = NULL;
404
}
405
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
406
index XXXXXXX..XXXXXXX 100644
407
--- a/hw/usb/hcd-xhci.c
408
+++ b/hw/usb/hcd-xhci.c
409
@@ -XXX,XX +XXX,XX @@ static void usb_xhci_unrealize(DeviceState *dev)
410
}
411
412
if (xhci->mfwrap_timer) {
413
- timer_del(xhci->mfwrap_timer);
414
timer_free(xhci->mfwrap_timer);
415
xhci->mfwrap_timer = NULL;
416
}
417
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
418
index XXXXXXX..XXXXXXX 100644
419
--- a/hw/usb/redirect.c
420
+++ b/hw/usb/redirect.c
421
@@ -XXX,XX +XXX,XX @@ static void usbredir_unrealize(USBDevice *udev)
422
qemu_bh_delete(dev->chardev_close_bh);
423
qemu_bh_delete(dev->device_reject_bh);
424
425
- timer_del(dev->attach_timer);
426
timer_free(dev->attach_timer);
427
428
usbredir_cleanup_device_queues(dev);
429
diff --git a/hw/vfio/display.c b/hw/vfio/display.c
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/vfio/display.c
432
+++ b/hw/vfio/display.c
433
@@ -XXX,XX +XXX,XX @@ static void vfio_display_edid_exit(VFIODisplay *dpy)
434
435
g_free(dpy->edid_regs);
436
g_free(dpy->edid_blob);
437
- timer_del(dpy->edid_link_timer);
438
timer_free(dpy->edid_link_timer);
439
}
440
441
diff --git a/hw/virtio/vhost-vsock-common.c b/hw/virtio/vhost-vsock-common.c
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/virtio/vhost-vsock-common.c
444
+++ b/hw/virtio/vhost-vsock-common.c
445
@@ -XXX,XX +XXX,XX @@ static void vhost_vsock_common_post_load_timer_cleanup(VHostVSockCommon *vvc)
446
return;
447
}
448
449
- timer_del(vvc->post_load_timer);
450
timer_free(vvc->post_load_timer);
451
vvc->post_load_timer = NULL;
452
}
453
diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
454
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/virtio/virtio-balloon.c
456
+++ b/hw/virtio/virtio-balloon.c
457
@@ -XXX,XX +XXX,XX @@ static bool balloon_stats_enabled(const VirtIOBalloon *s)
458
static void balloon_stats_destroy_timer(VirtIOBalloon *s)
459
{
460
if (balloon_stats_enabled(s)) {
461
- timer_del(s->stats_timer);
462
timer_free(s->stats_timer);
463
s->stats_timer = NULL;
464
s->stats_poll_interval = 0;
465
diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c
466
index XXXXXXX..XXXXXXX 100644
467
--- a/hw/virtio/virtio-rng.c
468
+++ b/hw/virtio/virtio-rng.c
469
@@ -XXX,XX +XXX,XX @@ static void virtio_rng_device_unrealize(DeviceState *dev)
470
VirtIORNG *vrng = VIRTIO_RNG(dev);
471
472
qemu_del_vm_change_state_handler(vrng->vmstate);
473
- timer_del(vrng->rate_limit_timer);
474
timer_free(vrng->rate_limit_timer);
475
virtio_del_queue(vdev, 0);
476
virtio_cleanup(vdev);
477
diff --git a/hw/watchdog/wdt_diag288.c b/hw/watchdog/wdt_diag288.c
478
index XXXXXXX..XXXXXXX 100644
479
--- a/hw/watchdog/wdt_diag288.c
480
+++ b/hw/watchdog/wdt_diag288.c
481
@@ -XXX,XX +XXX,XX @@ static void wdt_diag288_unrealize(DeviceState *dev)
482
{
483
DIAG288State *diag288 = DIAG288(dev);
484
485
- timer_del(diag288->timer);
486
timer_free(diag288->timer);
487
}
488
489
diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c
490
index XXXXXXX..XXXXXXX 100644
491
--- a/hw/watchdog/wdt_i6300esb.c
492
+++ b/hw/watchdog/wdt_i6300esb.c
493
@@ -XXX,XX +XXX,XX @@ static void i6300esb_exit(PCIDevice *dev)
494
{
495
I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
496
497
- timer_del(d->timer);
498
timer_free(d->timer);
499
}
500
501
diff --git a/migration/colo.c b/migration/colo.c
502
index XXXXXXX..XXXXXXX 100644
503
--- a/migration/colo.c
504
+++ b/migration/colo.c
505
@@ -XXX,XX +XXX,XX @@ out:
506
* error.
507
*/
508
colo_compare_unregister_notifier(&packets_compare_notifier);
509
- timer_del(s->colo_delay_timer);
510
timer_free(s->colo_delay_timer);
511
qemu_event_destroy(&s->colo_checkpoint_event);
512
513
diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/monitor/hmp-cmds.c
516
+++ b/monitor/hmp-cmds.c
517
@@ -XXX,XX +XXX,XX @@ static void hmp_migrate_status_cb(void *opaque)
518
error_report("%s", info->error_desc);
519
}
520
monitor_resume(status->mon);
521
- timer_del(status->timer);
522
timer_free(status->timer);
523
g_free(status);
524
}
525
diff --git a/net/announce.c b/net/announce.c
526
index XXXXXXX..XXXXXXX 100644
527
--- a/net/announce.c
528
+++ b/net/announce.c
529
@@ -XXX,XX +XXX,XX @@ void qemu_announce_timer_del(AnnounceTimer *timer, bool free_named)
530
{
531
bool free_timer = false;
532
if (timer->tm) {
533
- timer_del(timer->tm);
534
timer_free(timer->tm);
535
timer->tm = NULL;
536
}
537
diff --git a/net/colo-compare.c b/net/colo-compare.c
538
index XXXXXXX..XXXXXXX 100644
539
--- a/net/colo-compare.c
540
+++ b/net/colo-compare.c
541
@@ -XXX,XX +XXX,XX @@ static void colo_compare_timer_init(CompareState *s)
542
static void colo_compare_timer_del(CompareState *s)
543
{
544
if (s->packet_check_timer) {
545
- timer_del(s->packet_check_timer);
546
timer_free(s->packet_check_timer);
547
s->packet_check_timer = NULL;
548
}
549
diff --git a/net/slirp.c b/net/slirp.c
550
index XXXXXXX..XXXXXXX 100644
551
--- a/net/slirp.c
552
+++ b/net/slirp.c
553
@@ -XXX,XX +XXX,XX @@ static void *net_slirp_timer_new(SlirpTimerCb cb,
554
555
static void net_slirp_timer_free(void *timer, void *opaque)
556
{
557
- timer_del(timer);
558
timer_free(timer);
559
}
560
561
diff --git a/replay/replay-debugging.c b/replay/replay-debugging.c
562
index XXXXXXX..XXXXXXX 100644
563
--- a/replay/replay-debugging.c
564
+++ b/replay/replay-debugging.c
565
@@ -XXX,XX +XXX,XX @@ static void replay_delete_break(void)
566
assert(replay_mutex_locked());
567
568
if (replay_break_timer) {
569
- timer_del(replay_break_timer);
570
timer_free(replay_break_timer);
571
replay_break_timer = NULL;
572
}
573
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
574
index XXXXXXX..XXXXXXX 100644
575
--- a/target/s390x/cpu.c
576
+++ b/target/s390x/cpu.c
577
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_finalize(Object *obj)
578
#if !defined(CONFIG_USER_ONLY)
579
S390CPU *cpu = S390_CPU(obj);
580
581
- timer_del(cpu->env.tod_timer);
582
timer_free(cpu->env.tod_timer);
583
- timer_del(cpu->env.cpu_timer);
584
timer_free(cpu->env.cpu_timer);
585
586
qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu);
587
diff --git a/ui/console.c b/ui/console.c
588
index XXXXXXX..XXXXXXX 100644
589
--- a/ui/console.c
590
+++ b/ui/console.c
591
@@ -XXX,XX +XXX,XX @@ static void gui_setup_refresh(DisplayState *ds)
592
timer_mod(ds->gui_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME));
593
}
594
if (!need_timer && ds->gui_timer != NULL) {
595
- timer_del(ds->gui_timer);
596
timer_free(ds->gui_timer);
597
ds->gui_timer = NULL;
598
}
599
diff --git a/ui/spice-core.c b/ui/spice-core.c
600
index XXXXXXX..XXXXXXX 100644
601
--- a/ui/spice-core.c
602
+++ b/ui/spice-core.c
603
@@ -XXX,XX +XXX,XX @@ static void timer_cancel(SpiceTimer *timer)
604
605
static void timer_remove(SpiceTimer *timer)
606
{
607
- timer_del(timer->timer);
608
timer_free(timer->timer);
609
g_free(timer);
610
}
611
diff --git a/util/throttle.c b/util/throttle.c
612
index XXXXXXX..XXXXXXX 100644
613
--- a/util/throttle.c
614
+++ b/util/throttle.c
615
@@ -XXX,XX +XXX,XX @@ static void throttle_timer_destroy(QEMUTimer **timer)
616
{
617
assert(*timer != NULL);
618
619
- timer_del(*timer);
620
timer_free(*timer);
621
*timer = NULL;
622
}
623
--
624
2.20.1
625
626
diff view generated by jsdifflib
New patch
1
The Arm CPU finalize function uses a sequence of timer_del(), timer_deinit(),
2
timer_free() to free the timer. The timer_deinit() step in this was always
3
unnecessary, and now the timer_del() is implied by timer_free(), so we can
4
collapse this down to simply calling timer_free().
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201215154107.3255-5-peter.maydell@linaro.org
10
---
11
target/arm/cpu.c | 2 --
12
1 file changed, 2 deletions(-)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
19
}
20
#ifndef CONFIG_USER_ONLY
21
if (cpu->pmu_timer) {
22
- timer_del(cpu->pmu_timer);
23
- timer_deinit(cpu->pmu_timer);
24
timer_free(cpu->pmu_timer);
25
}
26
#endif
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
1
From: Gan Qixin <ganqixin@huawei.com>
1
2
3
When running device-introspect-test, a memory leak occurred in the
4
digic_timer_init function, so use ptimer_free() in the finalize function to
5
avoid it.
6
7
ASAN shows memory leak stack:
8
9
Indirect leak of 288 byte(s) in 3 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf5b04084 in digic_timer_init /qemu/hw/timer/digic-timer.c:142
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564
16
#6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547
17
#7 0xaaabf5b40e84 in digic_init /qemu/hw/arm/digic.c:46
18
#8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
19
#9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
20
#10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
21
#11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
22
#12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
29
hw/timer/digic-timer.c | 8 ++++++++
30
1 file changed, 8 insertions(+)
31
32
diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/timer/digic-timer.c
35
+++ b/hw/timer/digic-timer.c
36
@@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj)
37
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
38
}
39
40
+static void digic_timer_finalize(Object *obj)
41
+{
42
+ DigicTimerState *s = DIGIC_TIMER(obj);
43
+
44
+ ptimer_free(s->ptimer);
45
+}
46
+
47
static void digic_timer_class_init(ObjectClass *klass, void *class_data)
48
{
49
DeviceClass *dc = DEVICE_CLASS(klass);
50
@@ -XXX,XX +XXX,XX @@ static const TypeInfo digic_timer_info = {
51
.parent = TYPE_SYS_BUS_DEVICE,
52
.instance_size = sizeof(DigicTimerState),
53
.instance_init = digic_timer_init,
54
+ .instance_finalize = digic_timer_finalize,
55
.class_init = digic_timer_class_init,
56
};
57
58
--
59
2.20.1
60
61
diff view generated by jsdifflib
New patch
1
From: Gan Qixin <ganqixin@huawei.com>
1
2
3
When running device-introspect-test, a memory leak occurred in the a10_pit_init
4
function, so use ptimer_free() in the finalize function to avoid it.
5
6
ASAN shows memory leak stack:
7
8
Indirect leak of 288 byte(s) in 6 object(s) allocated from:
9
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
10
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
11
#2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523
12
#3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544
13
#4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562
14
#5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
15
#6 0xaaabf57415e8 in a10_pit_init /qemu/hw/timer/allwinner-a10-pit.c:278
16
#7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
17
#8 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564
18
#9 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547
19
#10 0xaaabf5b94680 in aw_a10_init /qemu/hw/arm/allwinner-a10.c:49
20
#11 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
21
#12 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
22
23
Reported-by: Euler Robot <euler.robot@huawei.com>
24
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
28
hw/timer/allwinner-a10-pit.c | 11 +++++++++++
29
1 file changed, 11 insertions(+)
30
31
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/timer/allwinner-a10-pit.c
34
+++ b/hw/timer/allwinner-a10-pit.c
35
@@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj)
36
}
37
}
38
39
+static void a10_pit_finalize(Object *obj)
40
+{
41
+ AwA10PITState *s = AW_A10_PIT(obj);
42
+ int i;
43
+
44
+ for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
45
+ ptimer_free(s->timer[i]);
46
+ }
47
+}
48
+
49
static void a10_pit_class_init(ObjectClass *klass, void *data)
50
{
51
DeviceClass *dc = DEVICE_CLASS(klass);
52
@@ -XXX,XX +XXX,XX @@ static const TypeInfo a10_pit_info = {
53
.parent = TYPE_SYS_BUS_DEVICE,
54
.instance_size = sizeof(AwA10PITState),
55
.instance_init = a10_pit_init,
56
+ .instance_finalize = a10_pit_finalize,
57
.class_init = a10_pit_class_init,
58
};
59
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Gan Qixin <ganqixin@huawei.com>
2
2
3
PXA255 does not support a USB OHCI controller, so don't wire it up.
3
When running device-introspect-test, a memory leak occurred in the
4
exynos4210_rtc_init function, so use ptimer_free() in the finalize function to
5
avoid it.
4
6
5
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
ASAN shows memory leak stack:
6
Message-id: 20200313160215.28155-1-linux@roeck-us.net
8
9
Indirect leak of 96 byte(s) in 1 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf57b3934 in exynos4210_rtc_init /qemu/hw/rtc/exynos4210_rtc.c:567
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
16
#6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
17
#7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
18
#8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
19
#9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136
20
#10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164
21
#11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381
22
#12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
28
---
10
hw/arm/pxa2xx.c | 3 ---
29
hw/rtc/exynos4210_rtc.c | 9 +++++++++
11
1 file changed, 3 deletions(-)
30
1 file changed, 9 insertions(+)
12
31
13
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
32
diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c
14
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/pxa2xx.c
34
--- a/hw/rtc/exynos4210_rtc.c
16
+++ b/hw/arm/pxa2xx.c
35
+++ b/hw/rtc/exynos4210_rtc.c
17
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
36
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj)
18
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
37
sysbus_init_mmio(dev, &s->iomem);
19
}
38
}
20
39
21
- sysbus_create_simple("sysbus-ohci", 0x4c000000,
40
+static void exynos4210_rtc_finalize(Object *obj)
22
- qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
41
+{
23
-
42
+ Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
24
s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
43
+
25
s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
44
+ ptimer_free(s->ptimer);
45
+ ptimer_free(s->ptimer_1Hz);
46
+}
47
+
48
static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
49
{
50
DeviceClass *dc = DEVICE_CLASS(klass);
51
@@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_rtc_info = {
52
.parent = TYPE_SYS_BUS_DEVICE,
53
.instance_size = sizeof(Exynos4210RTCState),
54
.instance_init = exynos4210_rtc_init,
55
+ .instance_finalize = exynos4210_rtc_finalize,
56
.class_init = exynos4210_rtc_class_init,
57
};
26
58
27
--
59
--
28
2.20.1
60
2.20.1
29
61
30
62
diff view generated by jsdifflib
1
From: Chen Qun <kuhn.chenqun@huawei.com>
1
From: Gan Qixin <ganqixin@huawei.com>
2
2
3
The current code causes clang static code analyzer generate warning:
3
When running device-introspect-test, a memory leak occurred in the
4
hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
4
exynos4210_pwm_init function, so use ptimer_free() in the finalize function to
5
value = value & 0x0000000f;
5
avoid it.
6
^ ~~~~~~~~~~~~~~~~~~
7
hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
8
value = value & 0x000000fd;
9
^ ~~~~~~~~~~~~~~~~~~
10
6
11
According to the definition of the function, the two “value” assignments
7
ASAN shows memory leak stack:
12
should be written to registers.
8
9
Indirect leak of 240 byte(s) in 5 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523
13
#3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544
14
#4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562
15
#5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
16
#6 0xaaabf56a36cc in exynos4210_pwm_init /qemu/hw/timer/exynos4210_pwm.c:401
17
#7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
18
#8 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
19
#9 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
20
#10 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
21
#11 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
22
#12 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136
13
23
14
Reported-by: Euler Robot <euler.robot@huawei.com>
24
Reported-by: Euler Robot <euler.robot@huawei.com>
15
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
16
Message-id: 20200313123242.13236-1-kuhn.chenqun@huawei.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
28
---
20
hw/net/imx_fec.c | 6 ++++--
29
hw/timer/exynos4210_pwm.c | 11 +++++++++++
21
1 file changed, 4 insertions(+), 2 deletions(-)
30
1 file changed, 11 insertions(+)
22
31
23
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
32
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
24
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/net/imx_fec.c
34
--- a/hw/timer/exynos4210_pwm.c
26
+++ b/hw/net/imx_fec.c
35
+++ b/hw/timer/exynos4210_pwm.c
27
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
36
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj)
28
break;
37
sysbus_init_mmio(dev, &s->iomem);
29
case ENET_TGSR:
38
}
30
/* implement clear timer flag */
39
31
- value = value & 0x0000000f;
40
+static void exynos4210_pwm_finalize(Object *obj)
32
+ s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
41
+{
33
break;
42
+ Exynos4210PWMState *s = EXYNOS4210_PWM(obj);
34
case ENET_TCSR0:
43
+ int i;
35
case ENET_TCSR1:
44
+
36
case ENET_TCSR2:
45
+ for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
37
case ENET_TCSR3:
46
+ ptimer_free(s->timer[i].ptimer);
38
- value = value & 0x000000fd;
47
+ }
39
+ s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
48
+}
40
+ s->regs[index] &= ~0x0000007d; /* writable fields */
49
+
41
+ s->regs[index] |= (value & 0x0000007d);
50
static void exynos4210_pwm_class_init(ObjectClass *klass, void *data)
42
break;
51
{
43
case ENET_TCCR0:
52
DeviceClass *dc = DEVICE_CLASS(klass);
44
case ENET_TCCR1:
53
@@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_pwm_info = {
54
.parent = TYPE_SYS_BUS_DEVICE,
55
.instance_size = sizeof(Exynos4210PWMState),
56
.instance_init = exynos4210_pwm_init,
57
+ .instance_finalize = exynos4210_pwm_finalize,
58
.class_init = exynos4210_pwm_class_init,
59
};
60
45
--
61
--
46
2.20.1
62
2.20.1
47
63
48
64
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Gan Qixin <ganqixin@huawei.com>
2
2
3
IMX6UL USB controllers are quite similar to IMX7 USB controllers.
3
When running device-introspect-test, a memory leak occurred in the
4
Wire them up the same way.
4
mss_timer_init function, so use ptimer_free() in the finalize function to avoid
5
it.
5
6
6
The only real difference is that wiring up phy devices is necessary
7
ASAN shows memory leak stack:
7
to avoid phy reset timeouts in the Linux kernel.
8
8
9
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Indirect leak of 192 byte(s) in 2 object(s) allocated from:
10
Message-id: 20200313014551.12554-5-linux@roeck-us.net
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf58a0010 in mss_timer_init /qemu/hw/timer/mss-timer.c:235
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564
16
#6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547
17
#7 0xaaabf5b8316c in m2sxxx_soc_initfn /qemu/hw/arm/msf2-soc.c:70
18
#8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
19
#9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
20
#10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
21
#11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
22
#12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
28
---
14
include/hw/arm/fsl-imx6ul.h | 10 ++++++++++
29
hw/timer/mss-timer.c | 13 +++++++++++++
15
hw/arm/fsl-imx6ul.c | 35 +++++++++++++++++++++++++++++++++++
30
1 file changed, 13 insertions(+)
16
2 files changed, 45 insertions(+)
17
31
18
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
32
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
19
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/fsl-imx6ul.h
34
--- a/hw/timer/mss-timer.c
21
+++ b/include/hw/arm/fsl-imx6ul.h
35
+++ b/hw/timer/mss-timer.c
22
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj)
23
#include "hw/sd/sdhci.h"
37
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
24
#include "hw/ssi/imx_spi.h"
38
}
25
#include "hw/net/imx_fec.h"
39
26
+#include "hw/usb/chipidea.h"
40
+static void mss_timer_finalize(Object *obj)
27
+#include "hw/usb/imx-usb-phy.h"
41
+{
28
#include "exec/memory.h"
42
+ MSSTimerState *t = MSS_TIMER(obj);
29
#include "cpu.h"
43
+ int i;
30
44
+
31
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
45
+ for (i = 0; i < NUM_TIMERS; i++) {
32
FSL_IMX6UL_NUM_I2CS = 4,
46
+ struct Msf2Timer *st = &t->timers[i];
33
FSL_IMX6UL_NUM_ECSPIS = 4,
47
+
34
FSL_IMX6UL_NUM_ADCS = 2,
48
+ ptimer_free(st->ptimer);
35
+ FSL_IMX6UL_NUM_USB_PHYS = 2,
49
+ }
36
+ FSL_IMX6UL_NUM_USBS = 2,
50
+}
51
+
52
static const VMStateDescription vmstate_timers = {
53
.name = "mss-timer-block",
54
.version_id = 1,
55
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mss_timer_info = {
56
.parent = TYPE_SYS_BUS_DEVICE,
57
.instance_size = sizeof(MSSTimerState),
58
.instance_init = mss_timer_init,
59
+ .instance_finalize = mss_timer_finalize,
60
.class_init = mss_timer_class_init,
37
};
61
};
38
62
39
typedef struct FslIMX6ULState {
40
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
41
IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
42
SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
43
IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
44
+ IMXUSBPHYState usbphy[FSL_IMX6UL_NUM_USB_PHYS];
45
+ ChipideaState usb[FSL_IMX6UL_NUM_USBS];
46
MemoryRegion rom;
47
MemoryRegion caam;
48
MemoryRegion ocram;
49
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULMemoryMap {
50
FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
51
FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
52
FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
53
+ FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
54
+ FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024),
55
+ FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
56
+ FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024),
57
FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
58
FSL_IMX6UL_CCM_ADDR = 0x020C4000,
59
FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
60
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/arm/fsl-imx6ul.c
63
+++ b/hw/arm/fsl-imx6ul.c
64
@@ -XXX,XX +XXX,XX @@
65
#include "qapi/error.h"
66
#include "hw/arm/fsl-imx6ul.h"
67
#include "hw/misc/unimp.h"
68
+#include "hw/usb/imx-usb-phy.h"
69
#include "hw/boards.h"
70
#include "sysemu/sysemu.h"
71
#include "qemu/error-report.h"
72
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
73
TYPE_IMX_ENET);
74
}
75
76
+ /* USB */
77
+ for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
78
+ snprintf(name, NAME_SIZE, "usbphy%d", i);
79
+ sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
80
+ TYPE_IMX_USBPHY);
81
+ }
82
+ for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
83
+ snprintf(name, NAME_SIZE, "usb%d", i);
84
+ sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
85
+ TYPE_CHIPIDEA);
86
+ }
87
+
88
/*
89
* SDHCI
90
*/
91
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
92
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
93
}
94
95
+ /* USB */
96
+ for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
97
+ object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
98
+ &error_abort);
99
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
100
+ FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
101
+ }
102
+
103
+ for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
104
+ static const int FSL_IMX6UL_USBn_IRQ[] = {
105
+ FSL_IMX6UL_USB1_IRQ,
106
+ FSL_IMX6UL_USB2_IRQ,
107
+ };
108
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
109
+ &error_abort);
110
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
111
+ FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
112
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
113
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
114
+ FSL_IMX6UL_USBn_IRQ[i]));
115
+ }
116
+
117
/*
118
* USDHC
119
*/
120
--
63
--
121
2.20.1
64
2.20.1
122
65
123
66
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Gan Qixin <ganqixin@huawei.com>
2
2
3
USB1 and USB2 interrupt numbers were swapped. USB_PHY2 interrupt number
3
When running device-introspect-test, a memory leak occurred in the
4
is 45. That didn't really matter up to now since the interrupts were not
4
mv88w8618_pit_init function, so use ptimer_free() in the finalize function to
5
used, but it needs to be fixed to be able to wire up the USB controllers.
5
avoid it.
6
6
7
Fixes: 31cbf933f0e ("i.MX6UL: Add i.MX6UL SOC")
7
ASAN shows memory leak stack:
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
9
Message-id: 20200313014551.12554-3-linux@roeck-us.net
9
Indirect leak of 192 byte(s) in 4 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523
13
#3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544
14
#4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562
15
#5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
16
#6 0xaaabf5bb2290 in mv88w8618_timer_init /qemu/hw/arm/musicpal.c:862
17
#7 0xaaabf5bb2290 in mv88w8618_pit_init /qemu/hw/arm/musicpal.c:954
18
#8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
19
#9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
20
#10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
21
#11 0xaaabf5a95540 in qdev_device_help /qemu/softmmu/qdev-monitor.c:283
22
#12 0xaaabf5a96940 in qmp_device_add /qemu/softmmu/qdev-monitor.c:801
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
28
---
13
include/hw/arm/fsl-imx6ul.h | 6 +++---
29
hw/arm/musicpal.c | 12 ++++++++++++
14
1 file changed, 3 insertions(+), 3 deletions(-)
30
1 file changed, 12 insertions(+)
15
31
16
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
32
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
17
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx6ul.h
34
--- a/hw/arm/musicpal.c
19
+++ b/include/hw/arm/fsl-imx6ul.h
35
+++ b/hw/arm/musicpal.c
20
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULIRQs {
36
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_init(Object *obj)
21
FSL_IMX6UL_UART7_IRQ = 39,
37
sysbus_init_mmio(dev, &s->iomem);
22
FSL_IMX6UL_UART8_IRQ = 40,
38
}
23
39
24
- FSL_IMX6UL_USB1_IRQ = 42,
40
+static void mv88w8618_pit_finalize(Object *obj)
25
- FSL_IMX6UL_USB2_IRQ = 43,
41
+{
26
+ FSL_IMX6UL_USB1_IRQ = 43,
42
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
27
+ FSL_IMX6UL_USB2_IRQ = 42,
43
+ mv88w8618_pit_state *s = MV88W8618_PIT(dev);
28
FSL_IMX6UL_USB_PHY1_IRQ = 44,
44
+ int i;
29
- FSL_IMX6UL_USB_PHY2_IRQ = 44,
45
+
30
+ FSL_IMX6UL_USB_PHY2_IRQ = 45,
46
+ for (i = 0; i < 4; i++) {
31
47
+ ptimer_free(s->timer[i].ptimer);
32
FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
48
+ }
33
FSL_IMX6UL_CAAM_ERR_IRQ = 47,
49
+}
50
+
51
static const VMStateDescription mv88w8618_timer_vmsd = {
52
.name = "timer",
53
.version_id = 1,
54
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mv88w8618_pit_info = {
55
.parent = TYPE_SYS_BUS_DEVICE,
56
.instance_size = sizeof(mv88w8618_pit_state),
57
.instance_init = mv88w8618_pit_init,
58
+ .instance_finalize = mv88w8618_pit_finalize,
59
.class_init = mv88w8618_pit_class_init,
60
};
61
34
--
62
--
35
2.20.1
63
2.20.1
36
64
37
65
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Gan Qixin <ganqixin@huawei.com>
2
2
3
Recent Linux kernels (post v4.20) crash due to accesses to flexcan
3
When running device-introspect-test, a memory leak occurred in the
4
and pwm controllers. Instantiate as unimplemented devices to work
4
exynos4210_mct_init function, so use ptimer_free() in the finalize function to
5
around the problem.
5
avoid it.
6
6
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
ASAN shows memory leak stack:
8
Message-id: 20200313014551.12554-4-linux@roeck-us.net
8
9
Indirect leak of 96 byte(s) in 1 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf56b01a0 in exynos4210_mct_init /qemu/hw/timer/exynos4210_mct.c:1505
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
16
#6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
17
#7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
18
#8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
19
#9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136
20
#10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164
21
#11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381
22
#12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
28
---
12
hw/arm/fsl-imx6ul.c | 14 ++++++++++++++
29
hw/timer/exynos4210_mct.c | 14 ++++++++++++++
13
1 file changed, 14 insertions(+)
30
1 file changed, 14 insertions(+)
14
31
15
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
32
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/fsl-imx6ul.c
34
--- a/hw/timer/exynos4210_mct.c
18
+++ b/hw/arm/fsl-imx6ul.c
35
+++ b/hw/timer/exynos4210_mct.c
19
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
36
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj)
20
*/
37
sysbus_init_mmio(dev, &s->iomem);
21
create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
38
}
22
39
23
+ /*
40
+static void exynos4210_mct_finalize(Object *obj)
24
+ * PWM
41
+{
25
+ */
42
+ int i;
26
+ create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
43
+ Exynos4210MCTState *s = EXYNOS4210_MCT(obj);
27
+ create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
28
+ create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
29
+ create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
30
+
44
+
31
+ /*
45
+ ptimer_free(s->g_timer.ptimer_frc);
32
+ * CAN
33
+ */
34
+ create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
35
+ create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
36
+
46
+
37
/*
47
+ for (i = 0; i < 2; i++) {
38
* APHB_DMA
48
+ ptimer_free(s->l_timer[i].tick_timer.ptimer_tick);
39
*/
49
+ ptimer_free(s->l_timer[i].ptimer_frc);
50
+ }
51
+}
52
+
53
static void exynos4210_mct_class_init(ObjectClass *klass, void *data)
54
{
55
DeviceClass *dc = DEVICE_CLASS(klass);
56
@@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_mct_info = {
57
.parent = TYPE_SYS_BUS_DEVICE,
58
.instance_size = sizeof(Exynos4210MCTState),
59
.instance_init = exynos4210_mct_init,
60
+ .instance_finalize = exynos4210_mct_finalize,
61
.class_init = exynos4210_mct_class_init,
62
};
63
40
--
64
--
41
2.20.1
65
2.20.1
42
66
43
67
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
When requesting JEDEC data using the JEDEC_READ command, the Linux kernel
3
U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
4
always requests 6 bytes. The current implementation only returns three
4
in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
5
bytes, and interprets the remaining three bytes as new commands.
5
bandgap has stabilized.
6
While this does not matter most of the time, it is at the very least
7
confusing. To avoid the problem, always report up to 6 bytes of JEDEC
8
data. Fill remaining data with 0.
9
6
10
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
sabrelite board (mx6qsabrelite_defconfig), with a slight change made
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot
13
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
shell on QEMU with the following command:
11
12
$ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \
13
-display none -serial null -serial stdio
14
15
Boot log below:
16
17
U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800)
18
19
CPU: Freescale i.MX?? rev1.0 at 792 MHz
20
Reset cause: POR
21
Model: Freescale i.MX6 Quad SABRE Lite Board
22
Board: SABRE Lite
23
I2C: ready
24
DRAM: 1 GiB
25
force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55
26
force_idle_bus: failed to clear bus, sda=0 scl=0
27
force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c
28
force_idle_bus: failed to clear bus, sda=0 scl=0
29
force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5
30
force_idle_bus: failed to clear bus, sda=0 scl=0
31
MMC: FSL_SDHC: 0, FSL_SDHC: 1
32
Loading Environment from MMC... *** Warning - No block device, using default environment
33
34
In: serial
35
Out: serial
36
Err: serial
37
Net: Board Net Initialization Failed
38
No ethernet found.
39
starting USB...
40
Bus usb@2184000: usb dr_mode not found
41
USB EHCI 1.00
42
Bus usb@2184200: USB EHCI 1.00
43
scanning bus usb@2184000 for devices... 1 USB Device(s) found
44
scanning bus usb@2184200 for devices... 1 USB Device(s) found
45
scanning usb for storage devices... 0 Storage Device(s) found
46
scanning usb for ethernet devices... 0 Ethernet Device(s) found
47
Hit any key to stop autoboot: 0
48
=>
49
50
Signed-off-by: Bin Meng <bin.meng@windriver.com>
51
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
52
Message-id: 20210106063504.10841-2-bmeng.cn@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
53
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
54
---
16
hw/block/m25p80.c | 5 ++++-
55
hw/misc/imx6_ccm.c | 2 +-
17
1 file changed, 4 insertions(+), 1 deletion(-)
56
1 file changed, 1 insertion(+), 1 deletion(-)
18
57
19
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
58
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
20
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/block/m25p80.c
60
--- a/hw/misc/imx6_ccm.c
22
+++ b/hw/block/m25p80.c
61
+++ b/hw/misc/imx6_ccm.c
23
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
62
@@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev)
24
for (i = 0; i < s->pi->id_len; i++) {
63
s->analog[PMU_REG_3P0] = 0x00000F74;
25
s->data[i] = s->pi->id[i];
64
s->analog[PMU_REG_2P5] = 0x00005071;
26
}
65
s->analog[PMU_REG_CORE] = 0x00402010;
27
+ for (; i < SPI_NOR_MAX_ID_LEN; i++) {
66
- s->analog[PMU_MISC0] = 0x04000000;
28
+ s->data[i] = 0;
67
+ s->analog[PMU_MISC0] = 0x04000080;
29
+ }
68
s->analog[PMU_MISC1] = 0x00000000;
30
69
s->analog[PMU_MISC2] = 0x00272727;
31
- s->len = s->pi->id_len;
70
32
+ s->len = SPI_NOR_MAX_ID_LEN;
33
s->pos = 0;
34
s->state = STATE_READING_DATA;
35
break;
36
--
71
--
37
2.20.1
72
2.20.1
38
73
39
74
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
The Linux kernel recently started using FAST_READ_4 commands.
3
Currently when U-Boot boots, it prints "??" for i.MX processor:
4
This results in flash read failures. At the same time, the m25p80
5
emulation is seen to read 8 more bytes than expected. Adjusting the
6
expected number of dummy cycles to match FAST_READ fixes the problem.
7
4
8
Fixes: f95c4bffdc4c ("aspeed/smc: snoop SPI transfers to fake dummy cycles")
5
CPU: Freescale i.MX?? rev1.0 at 792 MHz
9
Reviewed-by: Cédric Le Goater <clg@kaod.org>
6
10
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
The register that was used to determine the silicon type is
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we
9
can refer to get_cpu_rev() in arch/arm/mach-imx/mx6/soc.c in
10
the U-Boot source codes that USB_ANALOG_DIGPROG is used.
11
12
Update its reset value to indicate i.MX6Q.
13
14
Signed-off-by: Bin Meng <bin.meng@windriver.com>
15
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Message-id: 20210106063504.10841-3-bmeng.cn@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
18
---
14
hw/ssi/aspeed_smc.c | 2 +-
19
hw/misc/imx6_ccm.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 1 insertion(+), 1 deletion(-)
16
21
17
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
22
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
18
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/ssi/aspeed_smc.c
24
--- a/hw/misc/imx6_ccm.c
20
+++ b/hw/ssi/aspeed_smc.c
25
+++ b/hw/misc/imx6_ccm.c
21
@@ -XXX,XX +XXX,XX @@ static int aspeed_smc_num_dummies(uint8_t command)
26
@@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev)
22
case FAST_READ:
27
s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x00000004;
23
case DOR:
28
s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000;
24
case QOR:
29
s->analog[USB_ANALOG_USB2_MISC] = 0x00000002;
25
+ case FAST_READ_4:
30
- s->analog[USB_ANALOG_DIGPROG] = 0x00000000;
26
case DOR_4:
31
+ s->analog[USB_ANALOG_DIGPROG] = 0x00630000;
27
case QOR_4:
32
28
return 1;
33
/* all PLLs need to be locked */
29
case DIOR:
34
s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK;
30
- case FAST_READ_4:
31
case DIOR_4:
32
return 2;
33
case QIOR:
34
--
35
--
35
2.20.1
36
2.20.1
36
37
37
38
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Whenever an unsupported command is encountered, the current code
3
At present, when booting U-Boot on QEMU sabrelite, we see:
4
interprets each transferred byte as new command. Most of the time, those
5
'commands' are interpreted as new unknown commands. However, in rare
6
cases, it may be that for example address or length information
7
passed with the original command is by itself a valid command.
8
If that happens, the state machine may get completely confused and,
9
worst case, start writing data into the flash or even erase it.
10
4
11
To avoid the problem, transition into STATE_READING_DATA and keep
5
Net: Board Net Initialization Failed
12
sending a value of 0 until the chip is deselected after encountering
6
No ethernet found.
13
an unsupported command.
14
7
15
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
17
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
board, the Ethernet PHY is at address 6. Adjust this by updating the
11
"fec-phy-num" property of the fsl_imx6 SoC object.
12
13
With this change, U-Boot sees the PHY but complains MAC address:
14
15
Net: using phy at 6
16
FEC [PRIME]
17
Error: FEC address not set.
18
19
This is due to U-Boot tries to read the MAC address from the fuse,
20
which QEMU does not have any valid content filled in. However this
21
does not prevent the Ethernet from working in QEMU. We just need to
22
set up the MAC address later in the U-Boot command shell, by:
23
24
=> setenv ethaddr 00:11:22:33:44:55
25
26
Signed-off-by: Bin Meng <bin.meng@windriver.com>
27
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
28
Message-id: 20210106063504.10841-4-bmeng.cn@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
30
---
20
hw/block/m25p80.c | 5 +++++
31
hw/arm/sabrelite.c | 4 ++++
21
1 file changed, 5 insertions(+)
32
1 file changed, 4 insertions(+)
22
33
23
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
34
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
24
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/block/m25p80.c
36
--- a/hw/arm/sabrelite.c
26
+++ b/hw/block/m25p80.c
37
+++ b/hw/arm/sabrelite.c
27
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
38
@@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine)
28
s->quad_enable = false;
39
29
break;
40
s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
30
default:
41
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
31
+ s->pos = 0;
42
+
32
+ s->len = 1;
43
+ /* Ethernet PHY address is 6 */
33
+ s->state = STATE_READING_DATA;
44
+ object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal);
34
+ s->data_read_loop = true;
45
+
35
+ s->data[0] = 0;
46
qdev_realize(DEVICE(s), NULL, &error_fatal);
36
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
47
37
break;
48
memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
38
}
39
--
49
--
40
2.20.1
50
2.20.1
41
51
42
52
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
3
This adds the target guide for SABRE Lite board, and documents how
4
and i.MX7 SoCs.
4
to boot a Linux kernel and U-Boot bootloader.
5
5
6
The only support really needed - at least to boot Linux - is support
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
for soft reset, which needs to reset various registers to their initial
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
value. Otherwise, just record register values.
8
Message-id: 20210106063504.10841-5-bmeng.cn@gmail.com
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
12
Message-id: 20200313014551.12554-2-linux@roeck-us.net
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
hw/usb/Makefile.objs | 2 +
11
docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++
16
include/hw/usb/imx-usb-phy.h | 53 +++++++++
12
docs/system/target-arm.rst | 1 +
17
hw/usb/imx-usb-phy.c | 225 +++++++++++++++++++++++++++++++++++
13
2 files changed, 120 insertions(+)
18
MAINTAINERS | 2 +
14
create mode 100644 docs/system/arm/sabrelite.rst
19
hw/arm/Kconfig | 1 +
20
hw/usb/Kconfig | 5 +
21
6 files changed, 288 insertions(+)
22
create mode 100644 include/hw/usb/imx-usb-phy.h
23
create mode 100644 hw/usb/imx-usb-phy.c
24
15
25
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
16
diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/usb/Makefile.objs
28
+++ b/hw/usb/Makefile.objs
29
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XEN) += xen-usb.o
30
xen-usb.o-cflags := $(LIBUSB_CFLAGS)
31
xen-usb.o-libs := $(LIBUSB_LIBS)
32
endif
33
+
34
+common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o
35
diff --git a/include/hw/usb/imx-usb-phy.h b/include/hw/usb/imx-usb-phy.h
36
new file mode 100644
17
new file mode 100644
37
index XXXXXXX..XXXXXXX
18
index XXXXXXX..XXXXXXX
38
--- /dev/null
19
--- /dev/null
39
+++ b/include/hw/usb/imx-usb-phy.h
20
+++ b/docs/system/arm/sabrelite.rst
40
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
41
+#ifndef IMX_USB_PHY_H
22
+Boundary Devices SABRE Lite (``sabrelite``)
42
+#define IMX_USB_PHY_H
23
+===========================================
43
+
24
+
44
+#include "hw/sysbus.h"
25
+Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development
45
+#include "qemu/bitops.h"
26
+platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Quad
27
+Applications Processor.
46
+
28
+
47
+enum IMXUsbPhyRegisters {
29
+Supported devices
48
+ USBPHY_PWD,
30
+-----------------
49
+ USBPHY_PWD_SET,
50
+ USBPHY_PWD_CLR,
51
+ USBPHY_PWD_TOG,
52
+ USBPHY_TX,
53
+ USBPHY_TX_SET,
54
+ USBPHY_TX_CLR,
55
+ USBPHY_TX_TOG,
56
+ USBPHY_RX,
57
+ USBPHY_RX_SET,
58
+ USBPHY_RX_CLR,
59
+ USBPHY_RX_TOG,
60
+ USBPHY_CTRL,
61
+ USBPHY_CTRL_SET,
62
+ USBPHY_CTRL_CLR,
63
+ USBPHY_CTRL_TOG,
64
+ USBPHY_STATUS,
65
+ USBPHY_DEBUG = 0x14,
66
+ USBPHY_DEBUG_SET,
67
+ USBPHY_DEBUG_CLR,
68
+ USBPHY_DEBUG_TOG,
69
+ USBPHY_DEBUG0_STATUS,
70
+ USBPHY_DEBUG1 = 0x1c,
71
+ USBPHY_DEBUG1_SET,
72
+ USBPHY_DEBUG1_CLR,
73
+ USBPHY_DEBUG1_TOG,
74
+ USBPHY_VERSION,
75
+ USBPHY_MAX
76
+};
77
+
31
+
78
+#define USBPHY_CTRL_SFTRST BIT(31)
32
+The SABRE Lite machine supports the following devices:
79
+
33
+
80
+#define TYPE_IMX_USBPHY "imx.usbphy"
34
+ * Up to 4 Cortex A9 cores
81
+#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
35
+ * Generic Interrupt Controller
36
+ * 1 Clock Controller Module
37
+ * 1 System Reset Controller
38
+ * 5 UARTs
39
+ * 2 EPIC timers
40
+ * 1 GPT timer
41
+ * 2 Watchdog timers
42
+ * 1 FEC Ethernet controller
43
+ * 3 I2C controllers
44
+ * 7 GPIO controllers
45
+ * 4 SDHC storage controllers
46
+ * 4 USB 2.0 host controllers
47
+ * 5 ECSPI controllers
48
+ * 1 SST 25VF016B flash
82
+
49
+
83
+typedef struct IMXUSBPHYState {
50
+Please note above list is a complete superset the QEMU SABRE Lite machine can
84
+ /* <private> */
51
+support. For a normal use case, a device tree blob that represents a real world
85
+ SysBusDevice parent_obj;
52
+SABRE Lite board, only exposes a subset of devices to the guest software.
86
+
53
+
87
+ /* <public> */
54
+Boot options
88
+ MemoryRegion iomem;
55
+------------
89
+
56
+
90
+ uint32_t usbphy[USBPHY_MAX];
57
+The SABRE Lite machine can start using the standard -kernel functionality
91
+} IMXUSBPHYState;
58
+for loading a Linux kernel, U-Boot bootloader or ELF executable.
92
+
59
+
93
+#endif /* IMX_USB_PHY_H */
60
+Running Linux kernel
94
diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
61
+--------------------
95
new file mode 100644
96
index XXXXXXX..XXXXXXX
97
--- /dev/null
98
+++ b/hw/usb/imx-usb-phy.c
99
@@ -XXX,XX +XXX,XX @@
100
+/*
101
+ * i.MX USB PHY
102
+ *
103
+ * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
104
+ *
105
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
106
+ * See the COPYING file in the top-level directory.
107
+ *
108
+ * We need to implement basic reset control in the PHY control register.
109
+ * For everything else, it is sufficient to set whatever is written.
110
+ */
111
+
62
+
112
+#include "qemu/osdep.h"
63
+Linux mainline v5.10 release is tested at the time of writing. To build a Linux
113
+#include "hw/usb/imx-usb-phy.h"
64
+mainline kernel that can be booted by the SABRE Lite machine, simply configure
114
+#include "migration/vmstate.h"
65
+the kernel using the imx_v6_v7_defconfig configuration:
115
+#include "qemu/log.h"
116
+#include "qemu/module.h"
117
+
66
+
118
+static const VMStateDescription vmstate_imx_usbphy = {
67
+.. code-block:: bash
119
+ .name = TYPE_IMX_USBPHY,
120
+ .version_id = 1,
121
+ .minimum_version_id = 1,
122
+ .fields = (VMStateField[]) {
123
+ VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
124
+ VMSTATE_END_OF_LIST()
125
+ },
126
+};
127
+
68
+
128
+static void imx_usbphy_softreset(IMXUSBPHYState *s)
69
+ $ export ARCH=arm
129
+{
70
+ $ export CROSS_COMPILE=arm-linux-gnueabihf-
130
+ s->usbphy[USBPHY_PWD] = 0x001e1c00;
71
+ $ make imx_v6_v7_defconfig
131
+ s->usbphy[USBPHY_TX] = 0x10060607;
72
+ $ make
132
+ s->usbphy[USBPHY_RX] = 0x00000000;
133
+ s->usbphy[USBPHY_CTRL] = 0xc0200000;
134
+}
135
+
73
+
136
+static void imx_usbphy_reset(DeviceState *dev)
74
+To boot the newly built Linux kernel in QEMU with the SABRE Lite machine, use:
137
+{
138
+ IMXUSBPHYState *s = IMX_USBPHY(dev);
139
+
75
+
140
+ s->usbphy[USBPHY_STATUS] = 0x00000000;
76
+.. code-block:: bash
141
+ s->usbphy[USBPHY_DEBUG] = 0x7f180000;
142
+ s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
143
+ s->usbphy[USBPHY_DEBUG1] = 0x00001000;
144
+ s->usbphy[USBPHY_VERSION] = 0x04020000;
145
+
77
+
146
+ imx_usbphy_softreset(s);
78
+ $ qemu-system-arm -M sabrelite -smp 4 -m 1G \
147
+}
79
+ -display none -serial null -serial stdio \
80
+ -kernel arch/arm/boot/zImage \
81
+ -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \
82
+ -initrd /path/to/rootfs.ext4 \
83
+ -append "root=/dev/ram"
148
+
84
+
149
+static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
85
+Running U-Boot
150
+{
86
+--------------
151
+ IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
152
+ uint32_t index = offset >> 2;
153
+ uint32_t value;
154
+
87
+
155
+ switch (index) {
88
+U-Boot mainline v2020.10 release is tested at the time of writing. To build a
156
+ case USBPHY_PWD_SET:
89
+U-Boot mainline bootloader that can be booted by the SABRE Lite machine, use
157
+ case USBPHY_TX_SET:
90
+the mx6qsabrelite_defconfig with similar commands as described above for Linux:
158
+ case USBPHY_RX_SET:
159
+ case USBPHY_CTRL_SET:
160
+ case USBPHY_DEBUG_SET:
161
+ case USBPHY_DEBUG1_SET:
162
+ /*
163
+ * All REG_NAME_SET register access are in fact targeting the
164
+ * REG_NAME register.
165
+ */
166
+ value = s->usbphy[index - 1];
167
+ break;
168
+ case USBPHY_PWD_CLR:
169
+ case USBPHY_TX_CLR:
170
+ case USBPHY_RX_CLR:
171
+ case USBPHY_CTRL_CLR:
172
+ case USBPHY_DEBUG_CLR:
173
+ case USBPHY_DEBUG1_CLR:
174
+ /*
175
+ * All REG_NAME_CLR register access are in fact targeting the
176
+ * REG_NAME register.
177
+ */
178
+ value = s->usbphy[index - 2];
179
+ break;
180
+ case USBPHY_PWD_TOG:
181
+ case USBPHY_TX_TOG:
182
+ case USBPHY_RX_TOG:
183
+ case USBPHY_CTRL_TOG:
184
+ case USBPHY_DEBUG_TOG:
185
+ case USBPHY_DEBUG1_TOG:
186
+ /*
187
+ * All REG_NAME_TOG register access are in fact targeting the
188
+ * REG_NAME register.
189
+ */
190
+ value = s->usbphy[index - 3];
191
+ break;
192
+ default:
193
+ value = s->usbphy[index];
194
+ break;
195
+ }
196
+ return (uint64_t)value;
197
+}
198
+
91
+
199
+static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
92
+.. code-block:: bash
200
+ unsigned size)
201
+{
202
+ IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
203
+ uint32_t index = offset >> 2;
204
+
93
+
205
+ switch (index) {
94
+ $ export CROSS_COMPILE=arm-linux-gnueabihf-
206
+ case USBPHY_CTRL:
95
+ $ make mx6qsabrelite_defconfig
207
+ s->usbphy[index] = value;
208
+ if (value & USBPHY_CTRL_SFTRST) {
209
+ imx_usbphy_softreset(s);
210
+ }
211
+ break;
212
+ case USBPHY_PWD:
213
+ case USBPHY_TX:
214
+ case USBPHY_RX:
215
+ case USBPHY_STATUS:
216
+ case USBPHY_DEBUG:
217
+ case USBPHY_DEBUG1:
218
+ s->usbphy[index] = value;
219
+ break;
220
+ case USBPHY_CTRL_SET:
221
+ s->usbphy[index - 1] |= value;
222
+ if (value & USBPHY_CTRL_SFTRST) {
223
+ imx_usbphy_softreset(s);
224
+ }
225
+ break;
226
+ case USBPHY_PWD_SET:
227
+ case USBPHY_TX_SET:
228
+ case USBPHY_RX_SET:
229
+ case USBPHY_DEBUG_SET:
230
+ case USBPHY_DEBUG1_SET:
231
+ /*
232
+ * All REG_NAME_SET register access are in fact targeting the
233
+ * REG_NAME register. So we change the value of the REG_NAME
234
+ * register, setting bits passed in the value.
235
+ */
236
+ s->usbphy[index - 1] |= value;
237
+ break;
238
+ case USBPHY_PWD_CLR:
239
+ case USBPHY_TX_CLR:
240
+ case USBPHY_RX_CLR:
241
+ case USBPHY_CTRL_CLR:
242
+ case USBPHY_DEBUG_CLR:
243
+ case USBPHY_DEBUG1_CLR:
244
+ /*
245
+ * All REG_NAME_CLR register access are in fact targeting the
246
+ * REG_NAME register. So we change the value of the REG_NAME
247
+ * register, unsetting bits passed in the value.
248
+ */
249
+ s->usbphy[index - 2] &= ~value;
250
+ break;
251
+ case USBPHY_CTRL_TOG:
252
+ s->usbphy[index - 3] ^= value;
253
+ if ((value & USBPHY_CTRL_SFTRST) &&
254
+ (s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
255
+ imx_usbphy_softreset(s);
256
+ }
257
+ break;
258
+ case USBPHY_PWD_TOG:
259
+ case USBPHY_TX_TOG:
260
+ case USBPHY_RX_TOG:
261
+ case USBPHY_DEBUG_TOG:
262
+ case USBPHY_DEBUG1_TOG:
263
+ /*
264
+ * All REG_NAME_TOG register access are in fact targeting the
265
+ * REG_NAME register. So we change the value of the REG_NAME
266
+ * register, toggling bits passed in the value.
267
+ */
268
+ s->usbphy[index - 3] ^= value;
269
+ break;
270
+ default:
271
+ /* Other registers are read-only */
272
+ break;
273
+ }
274
+}
275
+
96
+
276
+static const struct MemoryRegionOps imx_usbphy_ops = {
97
+Note we need to adjust settings by:
277
+ .read = imx_usbphy_read,
278
+ .write = imx_usbphy_write,
279
+ .endianness = DEVICE_NATIVE_ENDIAN,
280
+ .valid = {
281
+ /*
282
+ * Our device would not work correctly if the guest was doing
283
+ * unaligned access. This might not be a limitation on the real
284
+ * device but in practice there is no reason for a guest to access
285
+ * this device unaligned.
286
+ */
287
+ .min_access_size = 4,
288
+ .max_access_size = 4,
289
+ .unaligned = false,
290
+ },
291
+};
292
+
98
+
293
+static void imx_usbphy_realize(DeviceState *dev, Error **errp)
99
+.. code-block:: bash
294
+{
295
+ IMXUSBPHYState *s = IMX_USBPHY(dev);
296
+
100
+
297
+ memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
101
+ $ make menuconfig
298
+ "imx-usbphy", 0x1000);
299
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
300
+}
301
+
102
+
302
+static void imx_usbphy_class_init(ObjectClass *klass, void *data)
103
+then manually select the following configuration in U-Boot:
303
+{
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
305
+
104
+
306
+ dc->reset = imx_usbphy_reset;
105
+ Device Tree Control > Provider of DTB for DT Control > Embedded DTB
307
+ dc->vmsd = &vmstate_imx_usbphy;
308
+ dc->desc = "i.MX USB PHY Module";
309
+ dc->realize = imx_usbphy_realize;
310
+}
311
+
106
+
312
+static const TypeInfo imx_usbphy_info = {
107
+To start U-Boot using the SABRE Lite machine, provide the u-boot binary to
313
+ .name = TYPE_IMX_USBPHY,
108
+the -kernel argument, along with an SD card image with rootfs:
314
+ .parent = TYPE_SYS_BUS_DEVICE,
315
+ .instance_size = sizeof(IMXUSBPHYState),
316
+ .class_init = imx_usbphy_class_init,
317
+};
318
+
109
+
319
+static void imx_usbphy_register_types(void)
110
+.. code-block:: bash
320
+{
321
+ type_register_static(&imx_usbphy_info);
322
+}
323
+
111
+
324
+type_init(imx_usbphy_register_types)
112
+ $ qemu-system-arm -M sabrelite -smp 4 -m 1G \
325
diff --git a/MAINTAINERS b/MAINTAINERS
113
+ -display none -serial null -serial stdio \
114
+ -kernel u-boot
115
+
116
+The following example shows booting Linux kernel from dhcp, and uses the
117
+rootfs on an SD card. This requires some additional command line parameters
118
+for QEMU:
119
+
120
+.. code-block:: none
121
+
122
+ -nic user,tftp=/path/to/kernel/zImage \
123
+ -drive file=sdcard.img,id=rootfs -device sd-card,drive=rootfs
124
+
125
+The directory for the built-in TFTP server should also contain the device tree
126
+blob of the SABRE Lite board. The sample SD card image was populated with the
127
+root file system with one single partition. You may adjust the kernel "root="
128
+boot parameter accordingly.
129
+
130
+After U-Boot boots, type the following commands in the U-Boot command shell to
131
+boot the Linux kernel:
132
+
133
+.. code-block:: none
134
+
135
+ => setenv ethaddr 00:11:22:33:44:55
136
+ => setenv bootfile zImage
137
+ => dhcp
138
+ => tftpboot 14000000 imx6q-sabrelite.dtb
139
+ => setenv bootargs root=/dev/mmcblk3p1
140
+ => bootz 12000000 - 14000000
141
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
326
index XXXXXXX..XXXXXXX 100644
142
index XXXXXXX..XXXXXXX 100644
327
--- a/MAINTAINERS
143
--- a/docs/system/target-arm.rst
328
+++ b/MAINTAINERS
144
+++ b/docs/system/target-arm.rst
329
@@ -XXX,XX +XXX,XX @@ F: hw/arm/sabrelite.c
145
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
330
F: hw/arm/fsl-imx6.c
146
arm/versatile
331
F: hw/misc/imx6_*.c
147
arm/vexpress
332
F: hw/ssi/imx_spi.c
148
arm/aspeed
333
+F: hw/usb/imx-usb-phy.c
149
+ arm/sabrelite
334
+F: include/hw/usb/imx-usb-phy.h
150
arm/digic
335
F: include/hw/arm/fsl-imx6.h
151
arm/musicpal
336
F: include/hw/misc/imx6_*.h
152
arm/gumstix
337
F: include/hw/ssi/imx_spi.h
338
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
339
index XXXXXXX..XXXXXXX 100644
340
--- a/hw/arm/Kconfig
341
+++ b/hw/arm/Kconfig
342
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
343
select IMX
344
select IMX_FEC
345
select IMX_I2C
346
+ select IMX_USBPHY
347
select SDHCI
348
349
config ASPEED_SOC
350
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
351
index XXXXXXX..XXXXXXX 100644
352
--- a/hw/usb/Kconfig
353
+++ b/hw/usb/Kconfig
354
@@ -XXX,XX +XXX,XX @@ config USB_STORAGE_MTP
355
bool
356
default y
357
depends on USB
358
+
359
+config IMX_USBPHY
360
+ bool
361
+ default y
362
+ depends on USB
363
--
153
--
364
2.20.1
154
2.20.1
365
155
366
156
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