[v2] Support different CPU types for the sifive_e machine

[PATCH v2 0/2] Support different CPU types for the sifive_e machine

Corey Wharton posted 2 patches 4 years, 1 month ago

Diff against v1 v1
Download series mbox

Test docker-mingw@fedora passed

Test docker-quick@centos7 passed

Test checkpatch passed

Test FreeBSD passed

Test asan passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20200313193429.8035-1-coreyw7@fb.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>

hw/riscv/sifive_e.c |  3 ++-
target/riscv/cpu.c  | 10 ++++++++++
target/riscv/cpu.h  |  1 +
3 files changed, 13 insertions(+), 1 deletion(-)

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[PATCH v2 0/2] Support different CPU types for the sifive_e machine

Posted by Corey Wharton 4 years, 1 month ago

The purpose of this patch set is to allow the sifive_e machine to run
with different CPU targets to enable different ISA entensions. To that
end it also introduces a new sifive-e34 CPU type which provides the
same ISA as sifive-e31, with the addition of the single precision
floating-point extension (f). The default CPU for the sifive_e machine
is unchanged.

v2: Added missing RVU flag

Corey Wharton (2):
  riscv: sifive_e: Support changing CPU type
  target/riscv: Add a sifive-e34 cpu type

 hw/riscv/sifive_e.c |  3 ++-
 target/riscv/cpu.c  | 10 ++++++++++
 target/riscv/cpu.h  |  1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

-- 
2.21.1

Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine

Posted by Corey Wharton 4 years ago

ping

https://patchwork.kernel.org/patch/11437661/
https://patchwork.kernel.org/patch/11437665/

________________________________
From: Corey Wharton <coreyw7@fb.com>
Sent: Friday, March 13, 2020 12:35 PM
To: qemu-devel@nongnu.org <qemu-devel@nongnu.org>; qemu-riscv@nongnu.org <qemu-riscv@nongnu.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>; Alistair Francis <Alistair.Francis@wdc.com>; Sagar Karandikar <sagark@eecs.berkeley.edu>; Bastian Koppelmann <kbastian@mail.uni-paderborn.de>; Bin Meng <bmeng.cn@gmail.com>; Corey Wharton <coreyw7@fb.com>
Subject: [PATCH v2 0/2] Support different CPU types for the sifive_e machine

The purpose of this patch set is to allow the sifive_e machine to run
with different CPU targets to enable different ISA entensions. To that
end it also introduces a new sifive-e34 CPU type which provides the
same ISA as sifive-e31, with the addition of the single precision
floating-point extension (f). The default CPU for the sifive_e machine
is unchanged.

v2: Added missing RVU flag

Corey Wharton (2):
  riscv: sifive_e: Support changing CPU type
  target/riscv: Add a sifive-e34 cpu type

 hw/riscv/sifive_e.c |  3 ++-
 target/riscv/cpu.c  | 10 ++++++++++
 target/riscv/cpu.h  |  1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

--
2.21.1

Re: [PATCH v2 0/2] Support different CPU types for the sifive_e machine

Posted by Alistair Francis 3 years, 12 months ago

On Fri, Mar 13, 2020 at 12:36 PM Corey Wharton <coreyw7@fb.com> wrote:
>
> The purpose of this patch set is to allow the sifive_e machine to run
> with different CPU targets to enable different ISA entensions. To that
> end it also introduces a new sifive-e34 CPU type which provides the
> same ISA as sifive-e31, with the addition of the single precision
> floating-point extension (f). The default CPU for the sifive_e machine
> is unchanged.
>
> v2: Added missing RVU flag

Applied to the RISC-V tree for 5.1

Alistair

>
> Corey Wharton (2):
>   riscv: sifive_e: Support changing CPU type
>   target/riscv: Add a sifive-e34 cpu type
>
>  hw/riscv/sifive_e.c |  3 ++-
>  target/riscv/cpu.c  | 10 ++++++++++
>  target/riscv/cpu.h  |  1 +
>  3 files changed, 13 insertions(+), 1 deletion(-)
>
> --
> 2.21.1
>
>