arm queue; dunno if this will be the last before softfreeze

or not, but anyway probably the last large one. New orangepi-pc

board model is the big item here.

The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312

for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:

target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)

* Fix various bugs that might result in an assert() due to

incorrect hflags for M-profile CPUs

* Fix Aspeed SMC Controller user-mode select handling

* Report correct (with-tag) address in fault address register

when TBI is enabled

* cubieboard: make sure SOC object isn't leaked

* fsl-imx25: Wire up eSDHC controllers

* fsl-imx25: Wire up USB controllers

* New board model: orangepi-pc (OrangePi PC)

* ARM/KVM: if user doesn't select GIC version and the

host kernel can only provide GICv3, use that, rather

than defaulting to "fail because GICv2 isn't possible"

* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync

Beata Michalska (1):

target/arm: kvm: Inject events at the last stage of sync

Cédric Le Goater (2):

aspeed/smc: Add some tracing

aspeed/smc: Fix User mode select/unselect scheme

Eric Auger (6):

hw/arm/virt: Document 'max' value in gic-version property description

hw/arm/virt: Introduce VirtGICType enum type

hw/arm/virt: Introduce finalize_gic_version()

target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap

hw/arm/virt: kvm: Restructure finalize_gic_version()

hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work

Guenter Roeck (2):

hw/arm/fsl-imx25: Wire up eSDHC controllers

hw/arm/fsl-imx25: Wire up USB controllers

Igor Mammedov (1):

hw/arm/cubieboard: make sure SOC object isn't leaked

Niek Linnenbank (13):

hw/arm: add Allwinner H3 System-on-Chip

hw/arm: add Xunlong Orange Pi PC machine

hw/arm/allwinner-h3: add Clock Control Unit

hw/arm/allwinner-h3: add USB host controller

hw/arm/allwinner-h3: add System Control module

hw/arm/allwinner: add CPU Configuration module

hw/arm/allwinner: add Security Identifier device

hw/arm/allwinner: add SD/MMC host controller

hw/arm/allwinner-h3: add EMAC ethernet device

hw/arm/allwinner-h3: add Boot ROM support

hw/arm/allwinner-h3: add SDRAM controller device

hw/arm/allwinner: add RTC device support

docs: add Orange Pi PC document

Peter Maydell (4):

hw/intc/armv7m_nvic: Rebuild hflags on reset

target/arm: Update hflags in trans_CPS_v7m()

target/arm: Recalculate hflags correctly after writes to CONTROL

target/arm: Fix some comment typos

Philippe Mathieu-Daudé (5):

tests/boot_linux_console: Add a quick test for the OrangePi PC board

tests/boot_linux_console: Add initrd test for the Orange Pi PC board

tests/boot_linux_console: Add a SD card test for the OrangePi PC board

tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC

tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC

Richard Henderson (2):

target/arm: Check addresses for disabled regimes

target/arm: Disable clean_data_tbi for system mode

Makefile.objs | 1 +

hw/arm/Makefile.objs | 1 +

hw/misc/Makefile.objs | 5 +

hw/net/Makefile.objs | 1 +

hw/rtc/Makefile.objs | 1 +

hw/sd/Makefile.objs | 1 +

hw/usb/hcd-ehci.h | 1 +

include/hw/arm/allwinner-a10.h | 4 +

include/hw/arm/allwinner-h3.h | 161 ++++++

include/hw/arm/fsl-imx25.h | 18 +

include/hw/arm/virt.h | 12 +-

include/hw/misc/allwinner-cpucfg.h | 52 ++

include/hw/misc/allwinner-h3-ccu.h | 66 +++

include/hw/misc/allwinner-h3-dramc.h | 106 ++++

include/hw/misc/allwinner-h3-sysctrl.h | 67 +++

include/hw/misc/allwinner-sid.h | 60 +++

include/hw/net/allwinner-sun8i-emac.h | 99 ++++

include/hw/rtc/allwinner-rtc.h | 134 +++++

include/hw/sd/allwinner-sdhost.h | 135 +++++

target/arm/helper.h | 1 +

target/arm/kvm_arm.h | 3 +

hw/arm/allwinner-a10.c | 19 +

hw/arm/allwinner-h3.c | 465 ++++++++++++++++++

hw/arm/cubieboard.c | 18 +

hw/arm/fsl-imx25.c | 56 +++

hw/arm/imx25_pdk.c | 16 +

hw/arm/orangepi.c | 130 +++++

hw/arm/virt.c | 145 ++++--

hw/intc/armv7m_nvic.c | 6 +

hw/misc/allwinner-cpucfg.c | 282 +++++++++++

hw/misc/allwinner-h3-ccu.c | 242 +++++++++

hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++

hw/misc/allwinner-h3-sysctrl.c | 140 ++++++

hw/misc/allwinner-sid.c | 168 +++++++

hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++

hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++

hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++

hw/ssi/aspeed_smc.c | 56 ++-

hw/usb/hcd-ehci-sysbus.c | 17 +

target/arm/helper.c | 49 +-

target/arm/kvm.c | 14 +-

target/arm/kvm32.c | 15 +-

target/arm/kvm64.c | 15 +-

target/arm/translate-a64.c | 11 +

target/arm/translate.c | 14 +-

MAINTAINERS | 9 +

default-configs/arm-softmmu.mak | 1 +

docs/system/arm/orangepi.rst | 253 ++++++++++

docs/system/target-arm.rst | 2 +

hw/arm/Kconfig | 12 +

hw/misc/trace-events | 19 +

hw/net/Kconfig | 3 +

hw/net/trace-events | 10 +

hw/rtc/trace-events | 4 +

hw/sd/trace-events | 7 +

hw/ssi/trace-events | 10 +

tests/acceptance/boot_linux_console.py | 230 +++++++++

57 files changed, 5787 insertions(+), 74 deletions(-)

create mode 100644 include/hw/arm/allwinner-h3.h

create mode 100644 include/hw/misc/allwinner-cpucfg.h

create mode 100644 include/hw/misc/allwinner-h3-ccu.h

create mode 100644 include/hw/misc/allwinner-h3-dramc.h

create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h

create mode 100644 include/hw/misc/allwinner-sid.h

create mode 100644 include/hw/net/allwinner-sun8i-emac.h

create mode 100644 include/hw/rtc/allwinner-rtc.h

create mode 100644 include/hw/sd/allwinner-sdhost.h

create mode 100644 hw/arm/allwinner-h3.c

create mode 100644 hw/arm/orangepi.c

create mode 100644 hw/misc/allwinner-cpucfg.c

create mode 100644 hw/misc/allwinner-h3-ccu.c

create mode 100644 hw/misc/allwinner-h3-dramc.c

create mode 100644 hw/misc/allwinner-h3-sysctrl.c

create mode 100644 hw/misc/allwinner-sid.c

create mode 100644 hw/net/allwinner-sun8i-emac.c

create mode 100644 hw/rtc/allwinner-rtc.c

create mode 100644 hw/sd/allwinner-sdhost.c

create mode 100644 docs/system/arm/orangepi.rst

create mode 100644 hw/ssi/trace-events

From: Niek Linnenbank <nieklinnenbank@gmail.com>

The Xunlong Orange Pi PC machine is a functional ARM machine

based on the Allwinner H3 System-on-Chip. It supports mainline

Linux, U-Boot, NetBSD and is covered by acceptance tests.

This commit adds a documentation text file with a description

of the machine and instructions for the user.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com

[PMM: moved file into docs/system/arm to match the reorg

of the arm target part of the docs; tweaked heading to

match other boards]

MAINTAINERS | 1 +

docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++

docs/system/target-arm.rst | 2 +

3 files changed, 256 insertions(+)

create mode 100644 docs/system/arm/orangepi.rst

@@ -XXX,XX +XXX,XX @@ S: Maintained

F: hw/*/allwinner-h3*

F: include/hw/*/allwinner-h3*

F: hw/arm/orangepi.c

+F: docs/system/orangepi.rst

ARM PrimeCell and CMSDK devices

M: Peter Maydell <peter.maydell@linaro.org>

diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/system/arm/orangepi.rst

+Orange Pi PC (``orangepi-pc``)

+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

+

+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip

+based embedded computer with mainline support in both U-Boot

+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,

+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and

+various other I/O.

+

+Supported devices

+"""""""""""""""""

+

+The Orange Pi PC machine supports the following devices:

+

+ * SMP (Quad Core Cortex-A7)

+ * Generic Interrupt Controller configuration

+ * SRAM mappings

+ * SDRAM controller

+ * Real Time Clock

+ * Timer device (re-used from Allwinner A10)

+ * UART

+ * SD/MMC storage controller

+ * EMAC ethernet

+ * USB 2.0 interfaces

+ * Clock Control Unit

+ * System Control module

+ * Security Identifier device

+

+Limitations

+"""""""""""

+

+Currently, Orange Pi PC does *not* support the following features:

+

+- Graphical output via HDMI, GPU and/or the Display Engine

+- Audio output

+- Hardware Watchdog

+

+Also see the 'unimplemented' array in the Allwinner H3 SoC module

+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``

+

+Boot options

+""""""""""""

+

+The Orange Pi PC machine can start using the standard -kernel functionality

+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC

+machine can also emulate the BootROM which is present on an actual Allwinner H3

+based SoC, which loads the bootloader from a SD card, specified via the -sd argument

+to qemu-system-arm.

+

+Machine-specific options

+""""""""""""""""""""""""

+

+The following machine-specific options are supported:

+

+- allwinner-rtc.base-year=YYYY

+

+ The Allwinner RTC device is automatically created by the Orange Pi PC machine

+ and uses a default base year value which can be overridden using the 'base-year' property.

+ The base year is the actual represented year when the RTC year value is zero.

+ This option can be used in case the target operating system driver uses a different

+ base year value. The minimum value for the base year is 1900.

+

+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff

+

+ The Security Identifier value can be read by the guest.

+ For example, U-Boot uses it to determine a unique MAC address.

+

+The above machine-specific options can be specified in qemu-system-arm

+via the '-global' argument, for example:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \

+ -global allwinner-rtc.base-year=2000

+

+Running mainline Linux

+""""""""""""""""""""""

+

+Mainline Linux kernels from 4.19 up to latest master are known to work.

+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,

+simply configure the kernel using the sunxi_defconfig configuration:

+

+.. code-block:: bash

+

+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper

+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig

+

+To be able to use USB storage, you need to manually enable the corresponding

+configuration item. Start the kconfig configuration tool:

+

+.. code-block:: bash

+

+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig

+

+Navigate to the following item, enable it and save your configuration:

+

+ Device Drivers > USB support > USB Mass Storage support

+

+Build the Linux kernel with:

+

+.. code-block:: bash

+

+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make

+

+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \

+ -kernel /path/to/linux/arch/arm/boot/zImage \

+ -append 'console=ttyS0,115200' \

+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb

+

+Orange Pi PC images

+"""""""""""""""""""

+

+Note that the mainline kernel does not have a root filesystem. You may provide it

+with an official Orange Pi PC image from the official website:

+

+ http://www.orangepi.org/downloadresources/

+

+Another possibility is to run an Armbian image for Orange Pi PC which

+can be downloaded from:

+

+ https://www.armbian.com/orange-pi-pc/

+

+Alternatively, you can also choose to build you own image with buildroot

+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.

+

+You can choose to attach the selected image either as an SD card or as USB mass storage.

+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd

+argument and provide the proper root= kernel parameter:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \

+ -kernel /path/to/linux/arch/arm/boot/zImage \

+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \

+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \

+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img

+

+To attach the image as an USB mass storage device to the machine,

+simply append to the command:

+

+.. code-block:: bash

+

+ -drive if=none,id=stick,file=myimage.img \

+ -device usb-storage,bus=usb-bus.0,drive=stick

+

+Instead of providing a custom Linux kernel via the -kernel command you may also

+choose to let the Orange Pi PC machine load the bootloader from SD card, just like

+a real board would do using the BootROM. Simply pass the selected image via the -sd

+argument and remove the -kernel, -append, -dbt and -initrd arguments:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \

+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img

+

+Note that both the official Orange Pi PC images and Armbian images start

+a lot of userland programs via systemd. Depending on the host hardware and OS,

+they may be slow to emulate, especially due to emulating the 4 cores.

+To help reduce the performance slow down due to emulating the 4 cores, you can

+give the following kernel parameters via U-Boot (or via -append):

+

+.. code-block:: bash

+

+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'

+

+Running U-Boot

+""""""""""""""

+

+U-Boot mainline can be build and configured using the orangepi_pc_defconfig

+using similar commands as describe above for Linux. Note that it is recommended

+for development/testing to select the following configuration setting in U-Boot:

+

+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB

+

+To start U-Boot using the Orange Pi PC machine, provide the

+u-boot binary to the -kernel argument:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \

+ -kernel /path/to/uboot/u-boot -sd disk.img

+

+Use the following U-boot commands to load and boot a Linux kernel from SD card:

+

+.. code-block:: bash

+

+ => setenv bootargs console=ttyS0,115200

+ => ext2load mmc 0 0x42000000 zImage

+ => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb

+ => bootz 0x42000000 - 0x43000000

+

+Running NetBSD

+""""""""""""""

+

+The NetBSD operating system also includes support for Allwinner H3 based boards,

+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC

+board and provides a fully working system with serial console, networking and storage.

+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:

+

+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz

+

+The image requires manually installing U-Boot in the image. Build U-Boot with

+the orangepi_pc_defconfig configuration as described in the previous section.

+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:

+

+.. code-block:: bash

+

+ $ gunzip armv7.img.gz

+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc

+

+Finally, before starting the machine the SD image must be extended such

+that the NetBSD kernel will not conclude the NetBSD partition is larger than

+the emulated SD card:

+

+.. code-block:: bash

+

+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img

+

+Start the machine using the following command:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \

+ -sd armv7.img -global allwinner-rtc.base-year=2000

+

+At the U-Boot stage, interrupt the automatic boot process by pressing a key

+and set the following environment variables before booting:

+

+.. code-block:: bash

+

+ => setenv bootargs root=ld0a

+ => setenv kernel netbsd-GENERIC.ub

+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb

+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'

+

+Optionally you may save the environment variables to SD card with 'saveenv'.

+To continue booting simply give the 'boot' command and NetBSD boots.

+

+Orange Pi PC acceptance tests

+"""""""""""""""""""""""""""""

+

+The Orange Pi PC machine has several acceptance tests included.

+To run the whole set of tests, build QEMU from source and simply

+provide the following command:

+

+.. code-block:: bash

+

+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \

+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py

diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/target-arm.rst

+++ b/docs/system/target-arm.rst

@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running

``qemu-system-aarch64 --machine help``.

.. toctree::

+ :maxdepth: 1

arm/integratorcp

arm/versatile

@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running

arm/stellaris

arm/musicpal

arm/sx1

+ arm/orangepi

Arm CPU features

================

2.20.1

From: Eric Auger <eric.auger@redhat.com>

At the moment if the end-user does not specify the gic-version along

with KVM acceleration, v2 is set by default. However most of the

systems now have GICv3 and sometimes they do not support GICv2

compatibility.

This patch keeps the default v2 selection in all cases except

in the KVM accelerated mode when either

- the host does not support GICv2 in-kernel emulation or

- number of VCPUS exceeds 8.

Those cases did not work anyway so we do not break any compatibility.

Now we get v3 selected in such a case.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Message-id: 20200311131618.7187-7-eric.auger@redhat.com

hw/arm/virt.c | 17 ++++++++++++++++-

1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)

*/

static void finalize_gic_version(VirtMachineState *vms)

{

+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;

+

if (kvm_enabled()) {

int probe_bitmap;

@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)

}

return;

case VIRT_GIC_VERSION_NOSEL:

- vms->gic_version = VIRT_GIC_VERSION_2;

+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {

+ vms->gic_version = VIRT_GIC_VERSION_2;

+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {

+ /*

+ * in case the host does not support v2 in-kernel emulation or

+ * the end-user requested more than 8 VCPUs we now default

+ * to v3. In any case defaulting to v2 would be broken.

+ */

+ vms->gic_version = VIRT_GIC_VERSION_3;

+ } else if (max_cpus > GIC_NCPU) {

+ error_report("host only supports in-kernel GICv2 emulation "

+ "but more than 8 vcpus are requested");

+ exit(1);

+ }

break;

case VIRT_GIC_VERSION_2:

case VIRT_GIC_VERSION_3:

2.20.1

From: Niek Linnenbank <nieklinnenbank@gmail.com>

A real Allwinner H3 SoC contains a Boot ROM which is the

first code that runs right after the SoC is powered on.

The Boot ROM is responsible for loading user code (e.g. a bootloader)

from any of the supported external devices and writing the downloaded

code to internal SRAM. After loading the SoC begins executing the code

written to SRAM.

This commits adds emulation of the Boot ROM firmware setup functionality

by loading user code from SD card in the A1 SRAM. While the A1 SRAM is

64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects

sizes larger than 32KiB. For reference, this behaviour is documented

by the Linux Sunxi project wiki at:

https://linux-sunxi.org/BROM#U-Boot_SPL_limitations

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com

include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++

hw/arm/allwinner-h3.c | 17 +++++++++++++++++

hw/arm/orangepi.c | 5 +++++

3 files changed, 43 insertions(+)

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h

--- a/include/hw/arm/allwinner-h3.h

+++ b/include/hw/arm/allwinner-h3.h

#include "hw/sd/allwinner-sdhost.h"

#include "hw/net/allwinner-sun8i-emac.h"

#include "target/arm/cpu.h"

+#include "sysemu/block-backend.h"

/**

* Allwinner H3 device list

@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {

MemoryRegion sram_c;

} AwH3State;

+/**

+ * Emulate Boot ROM firmware setup functionality.

+ *

+ * A real Allwinner H3 SoC contains a Boot ROM

+ * which is the first code that runs right after

+ * the SoC is powered on. The Boot ROM is responsible

+ * for loading user code (e.g. a bootloader) from any

+ * of the supported external devices and writing the

+ * downloaded code to internal SRAM. After loading the SoC

+ * begins executing the code written to SRAM.

+ *

+ * This function emulates the Boot ROM by copying 32 KiB

+ * of data from the given block device and writes it to

+ * the start of the first internal SRAM memory.

+ *

+ * @s: Allwinner H3 state object pointer

+ * @blk: Block backend device object pointer

+ */

+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);

+

#endif /* HW_ARM_ALLWINNER_H3_H */

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/allwinner-h3.c

+++ b/hw/arm/allwinner-h3.c

@@ -XXX,XX +XXX,XX @@

#include "hw/char/serial.h"

#include "hw/misc/unimp.h"

#include "hw/usb/hcd-ehci.h"

+#include "hw/loader.h"

#include "sysemu/sysemu.h"

#include "hw/arm/allwinner-h3.h"

@@ -XXX,XX +XXX,XX @@ enum {

AW_H3_GIC_NUM_SPI = 128

+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)

+{

+ const int64_t rom_size = 32 * KiB;

+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);

+

+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {

+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",

+ __func__);

+ return;

+ }

+

+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,

+ rom_size, s->memmap[AW_H3_SRAM_A1],

+ NULL, NULL, NULL, NULL, false);

+}

+

static void allwinner_h3_init(Object *obj)

AwH3State *s = AW_H3(obj);

diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/orangepi.c

+++ b/hw/arm/orangepi.c

@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)

memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],

machine->ram);

+ /* Load target kernel or start using BootROM */

+ if (!machine->kernel_filename && blk_is_available(blk)) {

+ /* Use Boot ROM to copy data from SD card to SRAM */

+ allwinner_h3_bootrom_setup(h3, blk);

+ }

orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];

orangepi_binfo.ram_size = machine->ram_size;

arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);

2.20.1

From: Eric Auger <eric.auger@redhat.com>

Let's move the code which freezes which gic-version to

be applied in a dedicated function. We also now set by

default the VIRT_GIC_VERSION_NO_SET. This eventually

turns into the legacy v2 choice in the finalize() function.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Message-id: 20200311131618.7187-4-eric.auger@redhat.com

include/hw/arm/virt.h | 1 +

hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------

2 files changed, 34 insertions(+), 21 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h

--- a/include/hw/arm/virt.h

+++ b/include/hw/arm/virt.h

@@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType {

VIRT_GIC_VERSION_HOST,

VIRT_GIC_VERSION_2,

VIRT_GIC_VERSION_3,

+ VIRT_GIC_VERSION_NOSEL,

} VirtGICType;

typedef struct MemMapEntry {

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)

}

+/*

+ * finalize_gic_version - Determines the final gic_version

+ * according to the gic-version property

+ *

+ * Default GIC type is v2

+ */

+static void finalize_gic_version(VirtMachineState *vms)

+{

+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||

+ vms->gic_version == VIRT_GIC_VERSION_MAX) {

+ if (!kvm_enabled()) {

+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {

+ error_report("gic-version=host requires KVM");

+ exit(1);

+ } else {

+ /* "max": currently means 3 for TCG */

+ vms->gic_version = VIRT_GIC_VERSION_3;

+ }

+ } else {

+ vms->gic_version = kvm_arm_vgic_probe();

+ if (!vms->gic_version) {

+ error_report(

+ "Unable to determine GIC version supported by host");

+ exit(1);

+ }

+ }

+ } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {

+ vms->gic_version = VIRT_GIC_VERSION_2;

+ }

+}

+

static void machvirt_init(MachineState *machine)

VirtMachineState *vms = VIRT_MACHINE(machine);

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

/* We can probe only here because during property set

* KVM is not available yet

*/

- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||

- vms->gic_version == VIRT_GIC_VERSION_MAX) {

- if (!kvm_enabled()) {

- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {

- error_report("gic-version=host requires KVM");

- exit(1);

- } else {

- /* "max": currently means 3 for TCG */

- vms->gic_version = VIRT_GIC_VERSION_3;

- }

- } else {

- vms->gic_version = kvm_arm_vgic_probe();

- if (!vms->gic_version) {

- error_report(

- "Unable to determine GIC version supported by host");

- exit(1);

- }

- }

- }

+ finalize_gic_version(vms);

if (!cpu_type_valid(machine->cpu_type)) {

error_report("mach-virt: CPU type %s not supported", machine->cpu_type);

@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)

"Set on/off to enable/disable using "

"physical address space above 32 bits",

NULL);

- /* Default GIC type is v2 */

- vms->gic_version = VIRT_GIC_VERSION_2;

+ vms->gic_version = VIRT_GIC_VERSION_NOSEL;

object_property_add_str(obj, "gic-version", virt_get_gic_version,

virt_set_gic_version, NULL);

object_property_set_description(obj, "gic-version",

2.20.1

From: Niek Linnenbank <nieklinnenbank@gmail.com>

In the Allwinner H3 SoC the SDRAM controller is responsible

for interfacing with the external Synchronous Dynamic Random

Access Memory (SDRAM). Types of memory that the SDRAM controller

supports are DDR2/DDR3 and capacities of up to 2GiB. This commit

adds emulation support of the Allwinner H3 SDRAM controller.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com

hw/misc/Makefile.objs | 1 +

include/hw/arm/allwinner-h3.h | 5 +

include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++

hw/arm/allwinner-h3.c | 19 +-

hw/arm/orangepi.c | 6 +

hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++

hw/misc/trace-events | 10 +

7 files changed, 502 insertions(+), 3 deletions(-)

create mode 100644 include/hw/misc/allwinner-h3-dramc.h

create mode 100644 hw/misc/allwinner-h3-dramc.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o

common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o

obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o

+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o

common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o

common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o

common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/allwinner-h3.h

+++ b/include/hw/arm/allwinner-h3.h

#include "hw/intc/arm_gic.h"

#include "hw/misc/allwinner-h3-ccu.h"

#include "hw/misc/allwinner-cpucfg.h"

+#include "hw/misc/allwinner-h3-dramc.h"

#include "hw/misc/allwinner-h3-sysctrl.h"

#include "hw/misc/allwinner-sid.h"

#include "hw/sd/allwinner-sdhost.h"

@@ -XXX,XX +XXX,XX @@ enum {

AW_H3_UART2,

AW_H3_UART3,

AW_H3_EMAC,

+ AW_H3_DRAMCOM,

+ AW_H3_DRAMCTL,

+ AW_H3_DRAMPHY,

AW_H3_GIC_DIST,

AW_H3_GIC_CPU,

AW_H3_GIC_HYP,

@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {

AwA10PITState timer;

AwH3ClockCtlState ccu;

AwCpuCfgState cpucfg;

+ AwH3DramCtlState dramc;

AwH3SysCtrlState sysctrl;

AwSidState sid;

AwSdHostState mmc0;

diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/allwinner-h3-dramc.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Allwinner H3 SDRAM Controller emulation

+ *

+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>

+ *

+ * This program is free software: you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation, either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program. If not, see <http://www.gnu.org/licenses/>.

+ */

+

+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H

+#define HW_MISC_ALLWINNER_H3_DRAMC_H

+

+#include "qom/object.h"

+#include "hw/sysbus.h"

+#include "exec/hwaddr.h"

+

+/**

+ * Constants

+ * @{

+ */

+

+/** Highest register address used by DRAMCOM module */

+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)

+

+/** Total number of known DRAMCOM registers */

+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \

+ sizeof(uint32_t))

+

+/** Highest register address used by DRAMCTL module */

+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)

+

+/** Total number of known DRAMCTL registers */

+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \

+ sizeof(uint32_t))

+

+/** Highest register address used by DRAMPHY module */

+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)

+

+/** Total number of known DRAMPHY registers */

+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \

+ sizeof(uint32_t))

+

+/** @} */

+

+/**

+ * Object model

+ * @{

+ */

+

+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"

+#define AW_H3_DRAMC(obj) \

+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)

+

+/** @} */

+

+/**

+ * Allwinner H3 SDRAM Controller object instance state.

+ */

+typedef struct AwH3DramCtlState {

+ /*< private >*/

+ SysBusDevice parent_obj;

+ /*< public >*/

+

+ /** Physical base address for start of RAM */

+ hwaddr ram_addr;

+

+ /** Total RAM size in megabytes */

+ uint32_t ram_size;

+

+ /**

+ * @name Memory Regions

+ * @{

+ */

+

+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */

+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */

+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */

+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */

+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */

+

+ /** @} */

+

+ /**

+ * @name Hardware Registers

+ * @{

+ */

+

+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */

+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */

+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */

+

+ /** @} */

+

+} AwH3DramCtlState;

+

+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/allwinner-h3.c

+++ b/hw/arm/allwinner-h3.c

@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {

[AW_H3_UART2] = 0x01c28800,

[AW_H3_UART3] = 0x01c28c00,

[AW_H3_EMAC] = 0x01c30000,

+ [AW_H3_DRAMCOM] = 0x01c62000,

+ [AW_H3_DRAMCTL] = 0x01c63000,

+ [AW_H3_DRAMPHY] = 0x01c65000,

[AW_H3_GIC_DIST] = 0x01c81000,

[AW_H3_GIC_CPU] = 0x01c82000,

[AW_H3_GIC_HYP] = 0x01c84000,

@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {

{ "scr", 0x01c2c400, 1 * KiB },

{ "gpu", 0x01c40000, 64 * KiB },

{ "hstmr", 0x01c60000, 4 * KiB },

- { "dramcom", 0x01c62000, 4 * KiB },

- { "dramctl0", 0x01c63000, 4 * KiB },

- { "dramphy0", 0x01c65000, 4 * KiB },

{ "spi0", 0x01c68000, 4 * KiB },

{ "spi1", 0x01c69000, 4 * KiB },

{ "csi", 0x01cb0000, 320 * KiB },

@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)

sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),

TYPE_AW_SUN8I_EMAC);

+

+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),

+ TYPE_AW_H3_DRAMC);

+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),

+ "ram-addr", &error_abort);

+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),

+ "ram-size", &error_abort);

static void allwinner_h3_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)

qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),

115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);

+ /* DRAMC */

+ qdev_init_nofail(DEVICE(&s->dramc));

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);

+

/* Unimplemented devices */

for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {

create_unimplemented_device(unimplemented[i].device_name,

diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/orangepi.c

+++ b/hw/arm/orangepi.c

@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)

/* Setup EMAC properties */

object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);

+ /* DRAMC */

+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],

+ "ram-addr", &error_abort);

+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",

+ &error_abort);

+

/* Mark H3 object realized */

object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);

diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/allwinner-h3-dramc.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Allwinner H3 SDRAM Controller emulation

+ *

+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>

+ *

+ * This program is free software: you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation, either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program. If not, see <http://www.gnu.org/licenses/>.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/units.h"

+#include "qemu/error-report.h"

+#include "hw/sysbus.h"

+#include "migration/vmstate.h"

+#include "qemu/log.h"

+#include "qemu/module.h"

+#include "exec/address-spaces.h"

+#include "hw/qdev-properties.h"

+#include "qapi/error.h"

+#include "hw/misc/allwinner-h3-dramc.h"

+#include "trace.h"

+

+#define REG_INDEX(offset) (offset / sizeof(uint32_t))

+

+/* DRAMCOM register offsets */

+enum {

+ REG_DRAMCOM_CR = 0x0000, /* Control Register */

+};

+

+/* DRAMCTL register offsets */

+enum {

+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */

+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */

+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */

+};

+

+/* DRAMCTL register flags */

+enum {

+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),

+};

+

+enum {

+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),

+};

+

+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,

+ uint8_t bank_bits, uint16_t page_size)

+{

+ /*

+ * This function simulates row addressing behavior when bootloader

+ * software attempts to detect the amount of available SDRAM. In U-Boot

+ * the controller is configured with the widest row addressing available.

+ * Then a pattern is written to RAM at an offset on the row boundary size.

+ * If the value read back equals the value read back from the

+ * start of RAM, the bootloader knows the amount of row bits.

+ *

+ * This function inserts a mirrored memory region when the configured row

+ * bits are not matching the actual emulated memory, to simulate the

+ * same behavior on hardware as expected by the bootloader.

+ */

+ uint8_t row_bits_actual = 0;

+

+ /* Calculate the actual row bits using the ram_size property */

+ for (uint8_t i = 8; i < 12; i++) {

+ if (1 << i == s->ram_size) {

+ row_bits_actual = i + 3;

+ break;

+ }

+ }

+

+ if (s->ram_size == (1 << (row_bits - 3))) {

+ /* When row bits is the expected value, remove the mirror */

+ memory_region_set_enabled(&s->row_mirror_alias, false);

+ trace_allwinner_h3_dramc_rowmirror_disable();

+

+ } else if (row_bits_actual) {

+ /* Row bits not matching ram_size, install the rows mirror */

+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +

+ bank_bits)) * page_size);

+

+ memory_region_set_enabled(&s->row_mirror_alias, true);

+ memory_region_set_address(&s->row_mirror_alias, row_mirror);

+

+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);

+ }

+}

+

+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+

+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);

+

+ return s->dramcom[idx];

+}

+

+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,

+ uint64_t val, unsigned size)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ trace_allwinner_h3_dramcom_write(offset, val, size);

+

+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return;

+ }

+

+ switch (offset) {

+ case REG_DRAMCOM_CR: /* Control Register */

+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,

+ ((val >> 2) & 0x1) + 2,

+ 1 << (((val >> 8) & 0xf) + 3));

+ break;

+ default:

+ break;

+ };

+

+ s->dramcom[idx] = (uint32_t) val;

+}

+

+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+

+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);

+

+ return s->dramctl[idx];

+}

+

+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,

+ uint64_t val, unsigned size)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ trace_allwinner_h3_dramctl_write(offset, val, size);

+

+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return;

+ }

+

+ switch (offset) {

+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */

+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;

+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;