1 | arm queue; dunno if this will be the last before softfreeze | 1 | Hi; here's a target-arm pullreq. Mostly this is some decodetree |
---|---|---|---|
2 | or not, but anyway probably the last large one. New orangepi-pc | 2 | conversion patches from me, plus a scattering of other bug fixes. |
3 | board model is the big item here. | ||
4 | 3 | ||
5 | thanks | 4 | thanks |
6 | -- PMM | 5 | -- PMM |
7 | 6 | ||
8 | The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565: | 7 | The following changes since commit e3660cc1e3cb136af50c0eaaeac27943c2438d1d: |
9 | 8 | ||
10 | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000) | 9 | Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into staging (2023-06-16 12:30:16 +0200) |
11 | 10 | ||
12 | are available in the Git repository at: | 11 | are available in the Git repository at: |
13 | 12 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230619 |
15 | 14 | ||
16 | for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837: | 15 | for you to fetch changes up to 074259c0f2ac40042dce766d870318cc22f388eb: |
17 | 16 | ||
18 | target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000) | 17 | hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property (2023-06-19 15:27:21 +0100) |
19 | 18 | ||
20 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
21 | target-arm queue: | 20 | target-arm queue: |
22 | * Fix various bugs that might result in an assert() due to | 21 | * Fix return value from LDSMIN/LDSMAX 8/16 bit atomics |
23 | incorrect hflags for M-profile CPUs | 22 | * Return correct result for LDG when ATA=0 |
24 | * Fix Aspeed SMC Controller user-mode select handling | 23 | * Conversion of system insns, loads and stores to decodetree |
25 | * Report correct (with-tag) address in fault address register | 24 | * hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 |
26 | when TBI is enabled | 25 | * hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels |
27 | * cubieboard: make sure SOC object isn't leaked | 26 | * hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop |
28 | * fsl-imx25: Wire up eSDHC controllers | 27 | * hw/arm/Kconfig: sbsa-ref uses Bochs display |
29 | * fsl-imx25: Wire up USB controllers | 28 | * imx_serial: set wake bit when we receive a data byte |
30 | * New board model: orangepi-pc (OrangePi PC) | 29 | * docs: sbsa: document board to firmware interface |
31 | * ARM/KVM: if user doesn't select GIC version and the | 30 | * hw/misc/bcm2835_property: avoid hard-coded constants |
32 | host kernel can only provide GICv3, use that, rather | ||
33 | than defaulting to "fail because GICv2 isn't possible" | ||
34 | * kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync | ||
35 | 31 | ||
36 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
37 | Beata Michalska (1): | 33 | Marcin Juszkiewicz (2): |
38 | target/arm: kvm: Inject events at the last stage of sync | 34 | hw/arm/Kconfig: sbsa-ref uses Bochs display |
35 | docs: sbsa: document board to firmware interface | ||
39 | 36 | ||
40 | Cédric Le Goater (2): | 37 | Martin Kaiser (1): |
41 | aspeed/smc: Add some tracing | 38 | imx_serial: set wake bit when we receive a data byte |
42 | aspeed/smc: Fix User mode select/unselect scheme | ||
43 | 39 | ||
44 | Eric Auger (6): | 40 | Peter Maydell (26): |
45 | hw/arm/virt: Document 'max' value in gic-version property description | 41 | target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics |
46 | hw/arm/virt: Introduce VirtGICType enum type | 42 | target/arm: Return correct result for LDG when ATA=0 |
47 | hw/arm/virt: Introduce finalize_gic_version() | 43 | target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode |
48 | target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap | 44 | target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores |
49 | hw/arm/virt: kvm: Restructure finalize_gic_version() | 45 | target/arm: Convert hint instruction space to decodetree |
50 | hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work | 46 | target/arm: Convert barrier insns to decodetree |
47 | target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree | ||
48 | target/arm: Convert MSR (immediate) to decodetree | ||
49 | target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree | ||
50 | target/arm: Convert exception generation instructions to decodetree | ||
51 | target/arm: Convert load/store exclusive and ordered to decodetree | ||
52 | target/arm: Convert LDXP, STXP, CASP, CAS to decodetree | ||
53 | target/arm: Convert load reg (literal) group to decodetree | ||
54 | target/arm: Convert load/store-pair to decodetree | ||
55 | target/arm: Convert ld/st reg+imm9 insns to decodetree | ||
56 | target/arm: Convert LDR/STR with 12-bit immediate to decodetree | ||
57 | target/arm: Convert LDR/STR reg+reg to decodetree | ||
58 | target/arm: Convert atomic memory ops to decodetree | ||
59 | target/arm: Convert load (pointer auth) insns to decodetree | ||
60 | target/arm: Convert LDAPR/STLR (imm) to decodetree | ||
61 | target/arm: Convert load/store (multiple structures) to decodetree | ||
62 | target/arm: Convert load/store single structure to decodetree | ||
63 | target/arm: Convert load/store tags insns to decodetree | ||
64 | hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 | ||
65 | hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels | ||
66 | hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop | ||
51 | 67 | ||
52 | Guenter Roeck (2): | 68 | Sergey Kambalin (4): |
53 | hw/arm/fsl-imx25: Wire up eSDHC controllers | 69 | hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h' |
54 | hw/arm/fsl-imx25: Wire up USB controllers | 70 | hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions |
71 | hw/misc/bcm2835_property: Replace magic frequency values by definitions | ||
72 | hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property | ||
55 | 73 | ||
56 | Igor Mammedov (1): | 74 | docs/system/arm/sbsa.rst | 38 +- |
57 | hw/arm/cubieboard: make sure SOC object isn't leaked | 75 | include/hw/arm/raspi_platform.h | 10 + |
58 | 76 | include/hw/char/imx_serial.h | 1 + | |
59 | Niek Linnenbank (13): | 77 | include/hw/misc/raspberrypi-fw-defs.h | 163 ++ |
60 | hw/arm: add Allwinner H3 System-on-Chip | 78 | target/arm/tcg/a64.decode | 403 ++++ |
61 | hw/arm: add Xunlong Orange Pi PC machine | 79 | hw/char/imx_serial.c | 5 +- |
62 | hw/arm/allwinner-h3: add Clock Control Unit | 80 | hw/intc/allwinner-a10-pic.c | 2 +- |
63 | hw/arm/allwinner-h3: add USB host controller | 81 | hw/misc/bcm2835_property.c | 112 +- |
64 | hw/arm/allwinner-h3: add System Control module | 82 | hw/sd/allwinner-sdhost.c | 2 +- |
65 | hw/arm/allwinner: add CPU Configuration module | 83 | hw/timer/nrf51_timer.c | 7 +- |
66 | hw/arm/allwinner: add Security Identifier device | 84 | target/arm/tcg/translate-a64.c | 3319 +++++++++++++++------------------ |
67 | hw/arm/allwinner: add SD/MMC host controller | 85 | hw/arm/Kconfig | 1 + |
68 | hw/arm/allwinner-h3: add EMAC ethernet device | 86 | 12 files changed, 2157 insertions(+), 1906 deletions(-) |
69 | hw/arm/allwinner-h3: add Boot ROM support | 87 | create mode 100644 include/hw/misc/raspberrypi-fw-defs.h |
70 | hw/arm/allwinner-h3: add SDRAM controller device | ||
71 | hw/arm/allwinner: add RTC device support | ||
72 | docs: add Orange Pi PC document | ||
73 | |||
74 | Peter Maydell (4): | ||
75 | hw/intc/armv7m_nvic: Rebuild hflags on reset | ||
76 | target/arm: Update hflags in trans_CPS_v7m() | ||
77 | target/arm: Recalculate hflags correctly after writes to CONTROL | ||
78 | target/arm: Fix some comment typos | ||
79 | |||
80 | Philippe Mathieu-Daudé (5): | ||
81 | tests/boot_linux_console: Add a quick test for the OrangePi PC board | ||
82 | tests/boot_linux_console: Add initrd test for the Orange Pi PC board | ||
83 | tests/boot_linux_console: Add a SD card test for the OrangePi PC board | ||
84 | tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC | ||
85 | tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC | ||
86 | |||
87 | Richard Henderson (2): | ||
88 | target/arm: Check addresses for disabled regimes | ||
89 | target/arm: Disable clean_data_tbi for system mode | ||
90 | |||
91 | Makefile.objs | 1 + | ||
92 | hw/arm/Makefile.objs | 1 + | ||
93 | hw/misc/Makefile.objs | 5 + | ||
94 | hw/net/Makefile.objs | 1 + | ||
95 | hw/rtc/Makefile.objs | 1 + | ||
96 | hw/sd/Makefile.objs | 1 + | ||
97 | hw/usb/hcd-ehci.h | 1 + | ||
98 | include/hw/arm/allwinner-a10.h | 4 + | ||
99 | include/hw/arm/allwinner-h3.h | 161 ++++++ | ||
100 | include/hw/arm/fsl-imx25.h | 18 + | ||
101 | include/hw/arm/virt.h | 12 +- | ||
102 | include/hw/misc/allwinner-cpucfg.h | 52 ++ | ||
103 | include/hw/misc/allwinner-h3-ccu.h | 66 +++ | ||
104 | include/hw/misc/allwinner-h3-dramc.h | 106 ++++ | ||
105 | include/hw/misc/allwinner-h3-sysctrl.h | 67 +++ | ||
106 | include/hw/misc/allwinner-sid.h | 60 +++ | ||
107 | include/hw/net/allwinner-sun8i-emac.h | 99 ++++ | ||
108 | include/hw/rtc/allwinner-rtc.h | 134 +++++ | ||
109 | include/hw/sd/allwinner-sdhost.h | 135 +++++ | ||
110 | target/arm/helper.h | 1 + | ||
111 | target/arm/kvm_arm.h | 3 + | ||
112 | hw/arm/allwinner-a10.c | 19 + | ||
113 | hw/arm/allwinner-h3.c | 465 ++++++++++++++++++ | ||
114 | hw/arm/cubieboard.c | 18 + | ||
115 | hw/arm/fsl-imx25.c | 56 +++ | ||
116 | hw/arm/imx25_pdk.c | 16 + | ||
117 | hw/arm/orangepi.c | 130 +++++ | ||
118 | hw/arm/virt.c | 145 ++++-- | ||
119 | hw/intc/armv7m_nvic.c | 6 + | ||
120 | hw/misc/allwinner-cpucfg.c | 282 +++++++++++ | ||
121 | hw/misc/allwinner-h3-ccu.c | 242 +++++++++ | ||
122 | hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++ | ||
123 | hw/misc/allwinner-h3-sysctrl.c | 140 ++++++ | ||
124 | hw/misc/allwinner-sid.c | 168 +++++++ | ||
125 | hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++ | ||
126 | hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++ | ||
127 | hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++ | ||
128 | hw/ssi/aspeed_smc.c | 56 ++- | ||
129 | hw/usb/hcd-ehci-sysbus.c | 17 + | ||
130 | target/arm/helper.c | 49 +- | ||
131 | target/arm/kvm.c | 14 +- | ||
132 | target/arm/kvm32.c | 15 +- | ||
133 | target/arm/kvm64.c | 15 +- | ||
134 | target/arm/translate-a64.c | 11 + | ||
135 | target/arm/translate.c | 14 +- | ||
136 | MAINTAINERS | 9 + | ||
137 | default-configs/arm-softmmu.mak | 1 + | ||
138 | docs/system/arm/orangepi.rst | 253 ++++++++++ | ||
139 | docs/system/target-arm.rst | 2 + | ||
140 | hw/arm/Kconfig | 12 + | ||
141 | hw/misc/trace-events | 19 + | ||
142 | hw/net/Kconfig | 3 + | ||
143 | hw/net/trace-events | 10 + | ||
144 | hw/rtc/trace-events | 4 + | ||
145 | hw/sd/trace-events | 7 + | ||
146 | hw/ssi/trace-events | 10 + | ||
147 | tests/acceptance/boot_linux_console.py | 230 +++++++++ | ||
148 | 57 files changed, 5787 insertions(+), 74 deletions(-) | ||
149 | create mode 100644 include/hw/arm/allwinner-h3.h | ||
150 | create mode 100644 include/hw/misc/allwinner-cpucfg.h | ||
151 | create mode 100644 include/hw/misc/allwinner-h3-ccu.h | ||
152 | create mode 100644 include/hw/misc/allwinner-h3-dramc.h | ||
153 | create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h | ||
154 | create mode 100644 include/hw/misc/allwinner-sid.h | ||
155 | create mode 100644 include/hw/net/allwinner-sun8i-emac.h | ||
156 | create mode 100644 include/hw/rtc/allwinner-rtc.h | ||
157 | create mode 100644 include/hw/sd/allwinner-sdhost.h | ||
158 | create mode 100644 hw/arm/allwinner-h3.c | ||
159 | create mode 100644 hw/arm/orangepi.c | ||
160 | create mode 100644 hw/misc/allwinner-cpucfg.c | ||
161 | create mode 100644 hw/misc/allwinner-h3-ccu.c | ||
162 | create mode 100644 hw/misc/allwinner-h3-dramc.c | ||
163 | create mode 100644 hw/misc/allwinner-h3-sysctrl.c | ||
164 | create mode 100644 hw/misc/allwinner-sid.c | ||
165 | create mode 100644 hw/net/allwinner-sun8i-emac.c | ||
166 | create mode 100644 hw/rtc/allwinner-rtc.c | ||
167 | create mode 100644 hw/sd/allwinner-sdhost.c | ||
168 | create mode 100644 docs/system/arm/orangepi.rst | ||
169 | create mode 100644 hw/ssi/trace-events | ||
170 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | The atomic memory operations are supposed to return the old memory |
---|---|---|---|
2 | data value in the destination register. This value is not | ||
3 | sign-extended, even if the operation is the signed minimum or | ||
4 | maximum. (In the pseudocode for the instructions the returned data | ||
5 | value is passed to ZeroExtend() to create the value in the register.) | ||
2 | 6 | ||
3 | Restructure the finalize_gic_version with switch cases and | 7 | We got this wrong because we were doing a 32-to-64 zero extend on the |
4 | clearly separate the following cases: | 8 | result for 8 and 16 bit data values, rather than the correct amount |
9 | of zero extension. | ||
5 | 10 | ||
6 | - KVM mode / in-kernel irqchip | 11 | Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data |
7 | - KVM mode / userspace irqchip | 12 | sizes rather than ext32u. |
8 | - TCG mode | ||
9 | 13 | ||
10 | In KVM mode / in-kernel irqchip , we explictly check whether | 14 | Cc: qemu-stable@nongnu.org |
11 | the chosen version is supported by the host. If the end-user | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | explicitly sets v2/v3 and this is not supported by the host, | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | then the user gets an explicit error message. Note that for | 17 | Message-id: 20230602155223.2040685-2-peter.maydell@linaro.org |
14 | old kernels where the CREATE_DEVICE ioctl doesn't exist then | 18 | --- |
15 | we will now fail if the user specifically asked for gicv2, | 19 | target/arm/tcg/translate-a64.c | 18 ++++++++++++++++-- |
16 | where previously we (probably) would have succeeded. | 20 | 1 file changed, 16 insertions(+), 2 deletions(-) |
17 | 21 | ||
18 | In KVM mode / userspace irqchip we immediatly output an error | 22 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
19 | in case the end-user explicitly selected v3. Also we warn the | ||
20 | end-user about the unexpected usage of gic-version=host in | ||
21 | that case as only userspace GICv2 is supported. | ||
22 | |||
23 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
25 | Message-id: 20200311131618.7187-6-eric.auger@redhat.com | ||
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | --- | ||
28 | hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------ | ||
29 | 1 file changed, 67 insertions(+), 21 deletions(-) | ||
30 | |||
31 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/hw/arm/virt.c | 24 | --- a/target/arm/tcg/translate-a64.c |
34 | +++ b/hw/arm/virt.c | 25 | +++ b/target/arm/tcg/translate-a64.c |
35 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) | 26 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, |
36 | */ | 27 | */ |
37 | static void finalize_gic_version(VirtMachineState *vms) | 28 | fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); |
38 | { | 29 | |
39 | - if (vms->gic_version == VIRT_GIC_VERSION_HOST || | 30 | - if ((mop & MO_SIGN) && size != MO_64) { |
40 | - vms->gic_version == VIRT_GIC_VERSION_MAX) { | 31 | - tcg_gen_ext32u_i64(tcg_rt, tcg_rt); |
41 | - if (!kvm_enabled()) { | 32 | + if (mop & MO_SIGN) { |
42 | - if (vms->gic_version == VIRT_GIC_VERSION_HOST) { | 33 | + switch (size) { |
43 | - error_report("gic-version=host requires KVM"); | 34 | + case MO_8: |
44 | - exit(1); | 35 | + tcg_gen_ext8u_i64(tcg_rt, tcg_rt); |
45 | - } else { | 36 | + break; |
46 | - /* "max": currently means 3 for TCG */ | 37 | + case MO_16: |
47 | - vms->gic_version = VIRT_GIC_VERSION_3; | 38 | + tcg_gen_ext16u_i64(tcg_rt, tcg_rt); |
48 | - } | 39 | + break; |
49 | - } else { | 40 | + case MO_32: |
50 | - int probe_bitmap = kvm_arm_vgic_probe(); | 41 | + tcg_gen_ext32u_i64(tcg_rt, tcg_rt); |
51 | + if (kvm_enabled()) { | 42 | + break; |
52 | + int probe_bitmap; | 43 | + case MO_64: |
53 | 44 | + break; | |
54 | - if (!probe_bitmap) { | 45 | + default: |
55 | + if (!kvm_irqchip_in_kernel()) { | 46 | + g_assert_not_reached(); |
56 | + switch (vms->gic_version) { | ||
57 | + case VIRT_GIC_VERSION_HOST: | ||
58 | + warn_report( | ||
59 | + "gic-version=host not relevant with kernel-irqchip=off " | ||
60 | + "as only userspace GICv2 is supported. Using v2 ..."); | ||
61 | + return; | ||
62 | + case VIRT_GIC_VERSION_MAX: | ||
63 | + case VIRT_GIC_VERSION_NOSEL: | ||
64 | + vms->gic_version = VIRT_GIC_VERSION_2; | ||
65 | + return; | ||
66 | + case VIRT_GIC_VERSION_2: | ||
67 | + return; | ||
68 | + case VIRT_GIC_VERSION_3: | ||
69 | error_report( | ||
70 | - "Unable to determine GIC version supported by host"); | ||
71 | + "gic-version=3 is not supported with kernel-irqchip=off"); | ||
72 | exit(1); | ||
73 | - } else { | ||
74 | - if (probe_bitmap & KVM_ARM_VGIC_V3) { | ||
75 | - vms->gic_version = VIRT_GIC_VERSION_3; | ||
76 | - } else { | ||
77 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
78 | - } | ||
79 | } | ||
80 | } | ||
81 | - } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) { | ||
82 | + | ||
83 | + probe_bitmap = kvm_arm_vgic_probe(); | ||
84 | + if (!probe_bitmap) { | ||
85 | + error_report("Unable to determine GIC version supported by host"); | ||
86 | + exit(1); | ||
87 | + } | 47 | + } |
88 | + | ||
89 | + switch (vms->gic_version) { | ||
90 | + case VIRT_GIC_VERSION_HOST: | ||
91 | + case VIRT_GIC_VERSION_MAX: | ||
92 | + if (probe_bitmap & KVM_ARM_VGIC_V3) { | ||
93 | + vms->gic_version = VIRT_GIC_VERSION_3; | ||
94 | + } else { | ||
95 | + vms->gic_version = VIRT_GIC_VERSION_2; | ||
96 | + } | ||
97 | + return; | ||
98 | + case VIRT_GIC_VERSION_NOSEL: | ||
99 | + vms->gic_version = VIRT_GIC_VERSION_2; | ||
100 | + break; | ||
101 | + case VIRT_GIC_VERSION_2: | ||
102 | + case VIRT_GIC_VERSION_3: | ||
103 | + break; | ||
104 | + } | ||
105 | + | ||
106 | + /* Check chosen version is effectively supported by the host */ | ||
107 | + if (vms->gic_version == VIRT_GIC_VERSION_2 && | ||
108 | + !(probe_bitmap & KVM_ARM_VGIC_V2)) { | ||
109 | + error_report("host does not support in-kernel GICv2 emulation"); | ||
110 | + exit(1); | ||
111 | + } else if (vms->gic_version == VIRT_GIC_VERSION_3 && | ||
112 | + !(probe_bitmap & KVM_ARM_VGIC_V3)) { | ||
113 | + error_report("host does not support in-kernel GICv3 emulation"); | ||
114 | + exit(1); | ||
115 | + } | ||
116 | + return; | ||
117 | + } | ||
118 | + | ||
119 | + /* TCG mode */ | ||
120 | + switch (vms->gic_version) { | ||
121 | + case VIRT_GIC_VERSION_NOSEL: | ||
122 | vms->gic_version = VIRT_GIC_VERSION_2; | ||
123 | + break; | ||
124 | + case VIRT_GIC_VERSION_MAX: | ||
125 | + vms->gic_version = VIRT_GIC_VERSION_3; | ||
126 | + break; | ||
127 | + case VIRT_GIC_VERSION_HOST: | ||
128 | + error_report("gic-version=host requires KVM"); | ||
129 | + exit(1); | ||
130 | + case VIRT_GIC_VERSION_2: | ||
131 | + case VIRT_GIC_VERSION_3: | ||
132 | + break; | ||
133 | } | 48 | } |
134 | } | 49 | } |
135 | 50 | ||
136 | -- | 51 | -- |
137 | 2.20.1 | 52 | 2.34.1 |
138 | |||
139 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | The LDG instruction loads the tag from a memory address (identified |
---|---|---|---|
2 | by [Xn + offset]), and then merges that tag into the destination | ||
3 | register Xt. We implemented this correctly for the case when | ||
4 | allocation tags are enabled, but didn't get it right when ATA=0: | ||
5 | instead of merging the tag bits into Xt, we merged them into the | ||
6 | memory address [Xn + offset] and then set Xt to that. | ||
2 | 7 | ||
3 | At the moment if the end-user does not specify the gic-version along | 8 | Merge the tag bits into the old Xt value, as they should be. |
4 | with KVM acceleration, v2 is set by default. However most of the | ||
5 | systems now have GICv3 and sometimes they do not support GICv2 | ||
6 | compatibility. | ||
7 | 9 | ||
8 | This patch keeps the default v2 selection in all cases except | 10 | Cc: qemu-stable@nongnu.org |
9 | in the KVM accelerated mode when either | 11 | Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructions") |
10 | - the host does not support GICv2 in-kernel emulation or | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | - number of VCPUS exceeds 8. | ||
12 | |||
13 | Those cases did not work anyway so we do not break any compatibility. | ||
14 | Now we get v3 selected in such a case. | ||
15 | |||
16 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
17 | Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com> | ||
18 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
19 | Message-id: 20200311131618.7187-7-eric.auger@redhat.com | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 14 | --- |
22 | hw/arm/virt.c | 17 ++++++++++++++++- | 15 | target/arm/tcg/translate-a64.c | 6 +++++- |
23 | 1 file changed, 16 insertions(+), 1 deletion(-) | 16 | 1 file changed, 5 insertions(+), 1 deletion(-) |
24 | 17 | ||
25 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 18 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
26 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/arm/virt.c | 20 | --- a/target/arm/tcg/translate-a64.c |
28 | +++ b/hw/arm/virt.c | 21 | +++ b/target/arm/tcg/translate-a64.c |
29 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) | 22 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) |
30 | */ | 23 | if (s->ata) { |
31 | static void finalize_gic_version(VirtMachineState *vms) | 24 | gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); |
32 | { | 25 | } else { |
33 | + unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; | 26 | + /* |
34 | + | 27 | + * Tag access disabled: we must check for aborts on the load |
35 | if (kvm_enabled()) { | 28 | + * load from [rn+offset], and then insert a 0 tag into rt. |
36 | int probe_bitmap; | 29 | + */ |
37 | 30 | clean_addr = clean_data_tbi(s, addr); | |
38 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | 31 | gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); |
39 | } | 32 | - gen_address_with_allocation_tag0(tcg_rt, addr); |
40 | return; | 33 | + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); |
41 | case VIRT_GIC_VERSION_NOSEL: | 34 | } |
42 | - vms->gic_version = VIRT_GIC_VERSION_2; | 35 | } else { |
43 | + if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { | 36 | tcg_rt = cpu_reg_sp(s, rt); |
44 | + vms->gic_version = VIRT_GIC_VERSION_2; | ||
45 | + } else if (probe_bitmap & KVM_ARM_VGIC_V3) { | ||
46 | + /* | ||
47 | + * in case the host does not support v2 in-kernel emulation or | ||
48 | + * the end-user requested more than 8 VCPUs we now default | ||
49 | + * to v3. In any case defaulting to v2 would be broken. | ||
50 | + */ | ||
51 | + vms->gic_version = VIRT_GIC_VERSION_3; | ||
52 | + } else if (max_cpus > GIC_NCPU) { | ||
53 | + error_report("host only supports in-kernel GICv2 emulation " | ||
54 | + "but more than 8 vcpus are requested"); | ||
55 | + exit(1); | ||
56 | + } | ||
57 | break; | ||
58 | case VIRT_GIC_VERSION_2: | ||
59 | case VIRT_GIC_VERSION_3: | ||
60 | -- | 37 | -- |
61 | 2.20.1 | 38 | 2.34.1 |
62 | |||
63 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | In disas_ldst_reg_imm9() we missed one place where a call to |
---|---|---|---|
2 | a gen_mte_check* function should now be passed the memop we | ||
3 | have created rather than just being passed the size. Fix this. | ||
2 | 4 | ||
3 | The Xunlong Orange Pi PC machine is a functional ARM machine | 5 | Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*") |
4 | based on the Allwinner H3 System-on-Chip. It supports mainline | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Linux, U-Boot, NetBSD and is covered by acceptance tests. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | --- | ||
10 | target/arm/tcg/translate-a64.c | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
6 | 12 | ||
7 | This commit adds a documentation text file with a description | 13 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
8 | of the machine and instructions for the user. | ||
9 | |||
10 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
11 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
12 | Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com | ||
13 | [PMM: moved file into docs/system/arm to match the reorg | ||
14 | of the arm target part of the docs; tweaked heading to | ||
15 | match other boards] | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | MAINTAINERS | 1 + | ||
19 | docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++ | ||
20 | docs/system/target-arm.rst | 2 + | ||
21 | 3 files changed, 256 insertions(+) | ||
22 | create mode 100644 docs/system/arm/orangepi.rst | ||
23 | |||
24 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
25 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/MAINTAINERS | 15 | --- a/target/arm/tcg/translate-a64.c |
27 | +++ b/MAINTAINERS | 16 | +++ b/target/arm/tcg/translate-a64.c |
28 | @@ -XXX,XX +XXX,XX @@ S: Maintained | 17 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
29 | F: hw/*/allwinner-h3* | 18 | |
30 | F: include/hw/*/allwinner-h3* | 19 | clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store, |
31 | F: hw/arm/orangepi.c | 20 | writeback || rn != 31, |
32 | +F: docs/system/orangepi.rst | 21 | - size, is_unpriv, memidx); |
33 | 22 | + memop, is_unpriv, memidx); | |
34 | ARM PrimeCell and CMSDK devices | 23 | |
35 | M: Peter Maydell <peter.maydell@linaro.org> | 24 | if (is_vector) { |
36 | diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst | 25 | if (is_store) { |
37 | new file mode 100644 | ||
38 | index XXXXXXX..XXXXXXX | ||
39 | --- /dev/null | ||
40 | +++ b/docs/system/arm/orangepi.rst | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | +Orange Pi PC (``orangepi-pc``) | ||
43 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
44 | + | ||
45 | +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip | ||
46 | +based embedded computer with mainline support in both U-Boot | ||
47 | +and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz, | ||
48 | +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and | ||
49 | +various other I/O. | ||
50 | + | ||
51 | +Supported devices | ||
52 | +""""""""""""""""" | ||
53 | + | ||
54 | +The Orange Pi PC machine supports the following devices: | ||
55 | + | ||
56 | + * SMP (Quad Core Cortex-A7) | ||
57 | + * Generic Interrupt Controller configuration | ||
58 | + * SRAM mappings | ||
59 | + * SDRAM controller | ||
60 | + * Real Time Clock | ||
61 | + * Timer device (re-used from Allwinner A10) | ||
62 | + * UART | ||
63 | + * SD/MMC storage controller | ||
64 | + * EMAC ethernet | ||
65 | + * USB 2.0 interfaces | ||
66 | + * Clock Control Unit | ||
67 | + * System Control module | ||
68 | + * Security Identifier device | ||
69 | + | ||
70 | +Limitations | ||
71 | +""""""""""" | ||
72 | + | ||
73 | +Currently, Orange Pi PC does *not* support the following features: | ||
74 | + | ||
75 | +- Graphical output via HDMI, GPU and/or the Display Engine | ||
76 | +- Audio output | ||
77 | +- Hardware Watchdog | ||
78 | + | ||
79 | +Also see the 'unimplemented' array in the Allwinner H3 SoC module | ||
80 | +for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c`` | ||
81 | + | ||
82 | +Boot options | ||
83 | +"""""""""""" | ||
84 | + | ||
85 | +The Orange Pi PC machine can start using the standard -kernel functionality | ||
86 | +for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC | ||
87 | +machine can also emulate the BootROM which is present on an actual Allwinner H3 | ||
88 | +based SoC, which loads the bootloader from a SD card, specified via the -sd argument | ||
89 | +to qemu-system-arm. | ||
90 | + | ||
91 | +Machine-specific options | ||
92 | +"""""""""""""""""""""""" | ||
93 | + | ||
94 | +The following machine-specific options are supported: | ||
95 | + | ||
96 | +- allwinner-rtc.base-year=YYYY | ||
97 | + | ||
98 | + The Allwinner RTC device is automatically created by the Orange Pi PC machine | ||
99 | + and uses a default base year value which can be overridden using the 'base-year' property. | ||
100 | + The base year is the actual represented year when the RTC year value is zero. | ||
101 | + This option can be used in case the target operating system driver uses a different | ||
102 | + base year value. The minimum value for the base year is 1900. | ||
103 | + | ||
104 | +- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff | ||
105 | + | ||
106 | + The Security Identifier value can be read by the guest. | ||
107 | + For example, U-Boot uses it to determine a unique MAC address. | ||
108 | + | ||
109 | +The above machine-specific options can be specified in qemu-system-arm | ||
110 | +via the '-global' argument, for example: | ||
111 | + | ||
112 | +.. code-block:: bash | ||
113 | + | ||
114 | + $ qemu-system-arm -M orangepi-pc -sd mycard.img \ | ||
115 | + -global allwinner-rtc.base-year=2000 | ||
116 | + | ||
117 | +Running mainline Linux | ||
118 | +"""""""""""""""""""""" | ||
119 | + | ||
120 | +Mainline Linux kernels from 4.19 up to latest master are known to work. | ||
121 | +To build a Linux mainline kernel that can be booted by the Orange Pi PC machine, | ||
122 | +simply configure the kernel using the sunxi_defconfig configuration: | ||
123 | + | ||
124 | +.. code-block:: bash | ||
125 | + | ||
126 | + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper | ||
127 | + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig | ||
128 | + | ||
129 | +To be able to use USB storage, you need to manually enable the corresponding | ||
130 | +configuration item. Start the kconfig configuration tool: | ||
131 | + | ||
132 | +.. code-block:: bash | ||
133 | + | ||
134 | + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig | ||
135 | + | ||
136 | +Navigate to the following item, enable it and save your configuration: | ||
137 | + | ||
138 | + Device Drivers > USB support > USB Mass Storage support | ||
139 | + | ||
140 | +Build the Linux kernel with: | ||
141 | + | ||
142 | +.. code-block:: bash | ||
143 | + | ||
144 | + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make | ||
145 | + | ||
146 | +To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use: | ||
147 | + | ||
148 | +.. code-block:: bash | ||
149 | + | ||
150 | + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ | ||
151 | + -kernel /path/to/linux/arch/arm/boot/zImage \ | ||
152 | + -append 'console=ttyS0,115200' \ | ||
153 | + -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb | ||
154 | + | ||
155 | +Orange Pi PC images | ||
156 | +""""""""""""""""""" | ||
157 | + | ||
158 | +Note that the mainline kernel does not have a root filesystem. You may provide it | ||
159 | +with an official Orange Pi PC image from the official website: | ||
160 | + | ||
161 | + http://www.orangepi.org/downloadresources/ | ||
162 | + | ||
163 | +Another possibility is to run an Armbian image for Orange Pi PC which | ||
164 | +can be downloaded from: | ||
165 | + | ||
166 | + https://www.armbian.com/orange-pi-pc/ | ||
167 | + | ||
168 | +Alternatively, you can also choose to build you own image with buildroot | ||
169 | +using the orangepi_pc_defconfig. Also see https://buildroot.org for more information. | ||
170 | + | ||
171 | +You can choose to attach the selected image either as an SD card or as USB mass storage. | ||
172 | +For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd | ||
173 | +argument and provide the proper root= kernel parameter: | ||
174 | + | ||
175 | +.. code-block:: bash | ||
176 | + | ||
177 | + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ | ||
178 | + -kernel /path/to/linux/arch/arm/boot/zImage \ | ||
179 | + -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \ | ||
180 | + -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ | ||
181 | + -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img | ||
182 | + | ||
183 | +To attach the image as an USB mass storage device to the machine, | ||
184 | +simply append to the command: | ||
185 | + | ||
186 | +.. code-block:: bash | ||
187 | + | ||
188 | + -drive if=none,id=stick,file=myimage.img \ | ||
189 | + -device usb-storage,bus=usb-bus.0,drive=stick | ||
190 | + | ||
191 | +Instead of providing a custom Linux kernel via the -kernel command you may also | ||
192 | +choose to let the Orange Pi PC machine load the bootloader from SD card, just like | ||
193 | +a real board would do using the BootROM. Simply pass the selected image via the -sd | ||
194 | +argument and remove the -kernel, -append, -dbt and -initrd arguments: | ||
195 | + | ||
196 | +.. code-block:: bash | ||
197 | + | ||
198 | + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ | ||
199 | + -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img | ||
200 | + | ||
201 | +Note that both the official Orange Pi PC images and Armbian images start | ||
202 | +a lot of userland programs via systemd. Depending on the host hardware and OS, | ||
203 | +they may be slow to emulate, especially due to emulating the 4 cores. | ||
204 | +To help reduce the performance slow down due to emulating the 4 cores, you can | ||
205 | +give the following kernel parameters via U-Boot (or via -append): | ||
206 | + | ||
207 | +.. code-block:: bash | ||
208 | + | ||
209 | + => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200' | ||
210 | + | ||
211 | +Running U-Boot | ||
212 | +"""""""""""""" | ||
213 | + | ||
214 | +U-Boot mainline can be build and configured using the orangepi_pc_defconfig | ||
215 | +using similar commands as describe above for Linux. Note that it is recommended | ||
216 | +for development/testing to select the following configuration setting in U-Boot: | ||
217 | + | ||
218 | + Device Tree Control > Provider for DTB for DT Control > Embedded DTB | ||
219 | + | ||
220 | +To start U-Boot using the Orange Pi PC machine, provide the | ||
221 | +u-boot binary to the -kernel argument: | ||
222 | + | ||
223 | +.. code-block:: bash | ||
224 | + | ||
225 | + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ | ||
226 | + -kernel /path/to/uboot/u-boot -sd disk.img | ||
227 | + | ||
228 | +Use the following U-boot commands to load and boot a Linux kernel from SD card: | ||
229 | + | ||
230 | +.. code-block:: bash | ||
231 | + | ||
232 | + => setenv bootargs console=ttyS0,115200 | ||
233 | + => ext2load mmc 0 0x42000000 zImage | ||
234 | + => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb | ||
235 | + => bootz 0x42000000 - 0x43000000 | ||
236 | + | ||
237 | +Running NetBSD | ||
238 | +"""""""""""""" | ||
239 | + | ||
240 | +The NetBSD operating system also includes support for Allwinner H3 based boards, | ||
241 | +including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC | ||
242 | +board and provides a fully working system with serial console, networking and storage. | ||
243 | +For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from: | ||
244 | + | ||
245 | + https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz | ||
246 | + | ||
247 | +The image requires manually installing U-Boot in the image. Build U-Boot with | ||
248 | +the orangepi_pc_defconfig configuration as described in the previous section. | ||
249 | +Next, unzip the NetBSD image and write the U-Boot binary including SPL using: | ||
250 | + | ||
251 | +.. code-block:: bash | ||
252 | + | ||
253 | + $ gunzip armv7.img.gz | ||
254 | + $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc | ||
255 | + | ||
256 | +Finally, before starting the machine the SD image must be extended such | ||
257 | +that the NetBSD kernel will not conclude the NetBSD partition is larger than | ||
258 | +the emulated SD card: | ||
259 | + | ||
260 | +.. code-block:: bash | ||
261 | + | ||
262 | + $ dd if=/dev/zero bs=1M count=64 >> armv7.img | ||
263 | + | ||
264 | +Start the machine using the following command: | ||
265 | + | ||
266 | +.. code-block:: bash | ||
267 | + | ||
268 | + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ | ||
269 | + -sd armv7.img -global allwinner-rtc.base-year=2000 | ||
270 | + | ||
271 | +At the U-Boot stage, interrupt the automatic boot process by pressing a key | ||
272 | +and set the following environment variables before booting: | ||
273 | + | ||
274 | +.. code-block:: bash | ||
275 | + | ||
276 | + => setenv bootargs root=ld0a | ||
277 | + => setenv kernel netbsd-GENERIC.ub | ||
278 | + => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb | ||
279 | + => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}' | ||
280 | + | ||
281 | +Optionally you may save the environment variables to SD card with 'saveenv'. | ||
282 | +To continue booting simply give the 'boot' command and NetBSD boots. | ||
283 | + | ||
284 | +Orange Pi PC acceptance tests | ||
285 | +""""""""""""""""""""""""""""" | ||
286 | + | ||
287 | +The Orange Pi PC machine has several acceptance tests included. | ||
288 | +To run the whole set of tests, build QEMU from source and simply | ||
289 | +provide the following command: | ||
290 | + | ||
291 | +.. code-block:: bash | ||
292 | + | ||
293 | + $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \ | ||
294 | + -t machine:orangepi-pc tests/acceptance/boot_linux_console.py | ||
295 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
296 | index XXXXXXX..XXXXXXX 100644 | ||
297 | --- a/docs/system/target-arm.rst | ||
298 | +++ b/docs/system/target-arm.rst | ||
299 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
300 | ``qemu-system-aarch64 --machine help``. | ||
301 | |||
302 | .. toctree:: | ||
303 | + :maxdepth: 1 | ||
304 | |||
305 | arm/integratorcp | ||
306 | arm/versatile | ||
307 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
308 | arm/stellaris | ||
309 | arm/musicpal | ||
310 | arm/sx1 | ||
311 | + arm/orangepi | ||
312 | |||
313 | Arm CPU features | ||
314 | ================ | ||
315 | -- | 26 | -- |
316 | 2.20.1 | 27 | 2.34.1 |
317 | 28 | ||
318 | 29 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | In the recent refactoring we missed a few places which should be |
---|---|---|---|
2 | calling finalize_memop_asimd() for ASIMD loads and stores but | ||
3 | instead are just calling finalize_memop(); fix these. | ||
2 | 4 | ||
3 | This test boots U-Boot then NetBSD (stored on a SD card) on | 5 | For the disas_ldst_single_struct() and disas_ldst_multiple_struct() |
4 | a OrangePi PC board. | 6 | cases, this is not a behaviour change because there the size |
7 | is never MO_128 and the two finalize functions do the same thing. | ||
5 | 8 | ||
6 | As it requires ~1.3GB of storage, it is disabled by default. | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | target/arm/tcg/translate-a64.c | 10 ++++++---- | ||
13 | 1 file changed, 6 insertions(+), 4 deletions(-) | ||
7 | 14 | ||
8 | U-Boot is built by the Debian project [1], and the SD card image | 15 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
9 | is provided by the NetBSD organization [2]. | ||
10 | |||
11 | Once the compressed SD card image is downloaded (304MB) and | ||
12 | extracted, this test is fast: | ||
13 | |||
14 | $ AVOCADO_ALLOW_LARGE_STORAGE=yes \ | ||
15 | avocado --show=app,console run -t machine:orangepi-pc \ | ||
16 | tests/acceptance/boot_linux_console.py | ||
17 | console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) | ||
18 | console: DRAM: 1024 MiB | ||
19 | console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology | ||
20 | console: CPU: Allwinner H3 (SUN8I 0000) | ||
21 | console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found | ||
22 | console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found | ||
23 | console: scanning usb for storage devices... 0 Storage Device(s) found | ||
24 | console: Hit any key to stop autoboot: 0 | ||
25 | console: => setenv bootargs root=ld0a | ||
26 | console: => setenv kernel netbsd-GENERIC.ub | ||
27 | console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb | ||
28 | console: => boot | ||
29 | console: ## Booting kernel from Legacy Image at 42000000 ... | ||
30 | console: Image Name: NetBSD/earmv7hf 9.0_RC1 | ||
31 | console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed) | ||
32 | console: XIP Kernel Image (no loading done) | ||
33 | console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK | ||
34 | console: Starting kernel ... | ||
35 | console: [ 1.0000000] NetBSD/evbarm (fdt) booting ... | ||
36 | console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020 | ||
37 | console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC | ||
38 | console: [ 1.0000000] total memory = 1024 MB | ||
39 | console: [ 1.0000000] avail memory = 1003 MB | ||
40 | console: [ 1.0000000] armfdt0 (root) | ||
41 | console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC | ||
42 | console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core) | ||
43 | console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled | ||
44 | console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache | ||
45 | console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache | ||
46 | console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache | ||
47 | console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals | ||
48 | ... | ||
49 | console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0 | ||
50 | console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062> | ||
51 | console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors | ||
52 | console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz | ||
53 | console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log. | ||
54 | console: [ 3.1179868] boot device: ld0 | ||
55 | console: [ 3.1470623] root on ld0a dumps on ld0b | ||
56 | console: [ 3.2464436] root file system type: ffs | ||
57 | console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules | ||
58 | console: Mon Feb 17 20:33:35 UTC 2020 | ||
59 | console: Starting root file system check: | ||
60 | PASS (35.96 s) | ||
61 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
62 | JOB TIME : 36.09 s | ||
63 | |||
64 | Note, this test only took ~65 seconds to run on Travis-CI, see: [3]. | ||
65 | |||
66 | This test is based on a description from Niek Linnenbank from [4]. | ||
67 | |||
68 | [1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot | ||
69 | [2] https://wiki.netbsd.org/ports/evbarm/allwinner/ | ||
70 | [3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778 | ||
71 | [4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html | ||
72 | |||
73 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
74 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
75 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
76 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
77 | Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com | ||
78 | [NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year] | ||
79 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
80 | --- | ||
81 | tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++ | ||
82 | 1 file changed, 70 insertions(+) | ||
83 | |||
84 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | ||
85 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
86 | --- a/tests/acceptance/boot_linux_console.py | 17 | --- a/target/arm/tcg/translate-a64.c |
87 | +++ b/tests/acceptance/boot_linux_console.py | 18 | +++ b/target/arm/tcg/translate-a64.c |
88 | @@ -XXX,XX +XXX,XX @@ import shutil | 19 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
89 | from avocado import skipUnless | 20 | if (!fp_access_check(s)) { |
90 | from avocado_qemu import Test | 21 | return; |
91 | from avocado_qemu import exec_command_and_wait_for_pattern | 22 | } |
92 | +from avocado_qemu import interrupt_interactive_console_until_pattern | 23 | + memop = finalize_memop_asimd(s, size); |
93 | from avocado_qemu import wait_for_console_pattern | 24 | } else { |
94 | from avocado.utils import process | 25 | if (size == 3 && opc == 2) { |
95 | from avocado.utils import archive | 26 | /* PRFM - prefetch */ |
96 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | 27 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
97 | 'to <orangepipc>') | 28 | is_store = (opc == 0); |
98 | self.wait_for_console_pattern('Starting Load Kernel Modules...') | 29 | is_signed = !is_store && extract32(opc, 1, 1); |
99 | 30 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
100 | + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') | 31 | + memop = finalize_memop(s, size + is_signed * MO_SIGN); |
101 | + def test_arm_orangepi_uboot_netbsd9(self): | 32 | } |
102 | + """ | 33 | |
103 | + :avocado: tags=arch:arm | 34 | if (rn == 31) { |
104 | + :avocado: tags=machine:orangepi-pc | 35 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
105 | + """ | 36 | |
106 | + # This test download a 304MB compressed image and expand it to 1.3GB... | 37 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
107 | + deb_url = ('http://snapshot.debian.org/archive/debian/' | 38 | |
108 | + '20200108T145233Z/pool/main/u/u-boot/' | 39 | - memop = finalize_memop(s, size + is_signed * MO_SIGN); |
109 | + 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb') | 40 | clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, memop); |
110 | + deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99' | 41 | |
111 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | 42 | if (is_vector) { |
112 | + # We use the common OrangePi PC 'plus' build of U-Boot for our secondary | 43 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
113 | + # program loader (SPL). We will then set the path to the more specific | 44 | if (!fp_access_check(s)) { |
114 | + # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt, | 45 | return; |
115 | + # before to boot NetBSD. | 46 | } |
116 | + uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin' | 47 | + memop = finalize_memop_asimd(s, size); |
117 | + uboot_path = self.extract_from_deb(deb_path, uboot_path) | 48 | } else { |
118 | + image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/' | 49 | if (size == 3 && opc == 2) { |
119 | + 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz') | 50 | /* PRFM - prefetch */ |
120 | + image_hash = '2babb29d36d8360adcb39c09e31060945259917a' | 51 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
121 | + image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash) | 52 | is_store = (opc == 0); |
122 | + image_path = os.path.join(self.workdir, 'armv7.img') | 53 | is_signed = !is_store && extract32(opc, 1, 1); |
123 | + image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path | 54 | is_extended = (size < 3) && extract32(opc, 0, 1); |
124 | + archive.gzip_uncompress(image_path_gz, image_path) | 55 | + memop = finalize_memop(s, size + is_signed * MO_SIGN); |
125 | + | 56 | } |
126 | + # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc | 57 | |
127 | + with open(uboot_path, 'rb') as f_in: | 58 | if (rn == 31) { |
128 | + with open(image_path, 'r+b') as f_out: | 59 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
129 | + f_out.seek(8 * 1024) | 60 | offset = imm12 << size; |
130 | + shutil.copyfileobj(f_in, f_out) | 61 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
131 | + | 62 | |
132 | + # Extend image, to avoid that NetBSD thinks the partition | 63 | - memop = finalize_memop(s, size + is_signed * MO_SIGN); |
133 | + # inside the image is larger than device size itself | 64 | clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, memop); |
134 | + f_out.seek(0, 2) | 65 | |
135 | + f_out.seek(64 * 1024 * 1024, 1) | 66 | if (is_vector) { |
136 | + f_out.write(bytearray([0x00])) | 67 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
137 | + | 68 | * promote consecutive little-endian elements below. |
138 | + self.vm.set_console() | 69 | */ |
139 | + self.vm.add_args('-nic', 'user', | 70 | clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, |
140 | + '-drive', image_drive_args, | 71 | - total, finalize_memop(s, size)); |
141 | + '-global', 'allwinner-rtc.base-year=2000', | 72 | + total, finalize_memop_asimd(s, size)); |
142 | + '-no-reboot') | 73 | |
143 | + self.vm.launch() | 74 | /* |
144 | + wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1') | 75 | * Consecutive little-endian elements from a single register |
145 | + interrupt_interactive_console_until_pattern(self, | 76 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
146 | + 'Hit any key to stop autoboot:', | 77 | total = selem << scale; |
147 | + 'switch to partitions #0, OK') | 78 | tcg_rn = cpu_reg_sp(s, rn); |
148 | + | 79 | |
149 | + exec_command_and_wait_for_pattern(self, '', '=>') | 80 | - mop = finalize_memop(s, scale); |
150 | + cmd = 'setenv bootargs root=ld0a' | 81 | + mop = finalize_memop_asimd(s, scale); |
151 | + exec_command_and_wait_for_pattern(self, cmd, '=>') | 82 | |
152 | + cmd = 'setenv kernel netbsd-GENERIC.ub' | 83 | clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, |
153 | + exec_command_and_wait_for_pattern(self, cmd, '=>') | 84 | total, mop); |
154 | + cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb' | ||
155 | + exec_command_and_wait_for_pattern(self, cmd, '=>') | ||
156 | + cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; " | ||
157 | + "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; " | ||
158 | + "fdt addr ${fdt_addr_r}; " | ||
159 | + "bootm ${kernel_addr_r} - ${fdt_addr_r}'") | ||
160 | + exec_command_and_wait_for_pattern(self, cmd, '=>') | ||
161 | + | ||
162 | + exec_command_and_wait_for_pattern(self, 'boot', | ||
163 | + 'Booting kernel from Legacy Image') | ||
164 | + wait_for_console_pattern(self, 'Starting kernel ...') | ||
165 | + wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)') | ||
166 | + # Wait for user-space | ||
167 | + wait_for_console_pattern(self, 'Starting root file system check') | ||
168 | + | ||
169 | def test_s390x_s390_ccw_virtio(self): | ||
170 | """ | ||
171 | :avocado: tags=arch:s390x | ||
172 | -- | 85 | -- |
173 | 2.20.1 | 86 | 2.34.1 |
174 | |||
175 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Convert the various instructions in the hint instruction space |
---|---|---|---|
2 | to decodetree. | ||
2 | 3 | ||
3 | Convert kvm_arm_vgic_probe() so that it returns a | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | bitmap of supported in-kernel emulation VGIC versions instead | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | of the max version: at the moment values can be v2 and v3. | 6 | Message-id: 20230602155223.2040685-3-peter.maydell@linaro.org |
6 | This allows to expose the case where the host GICv3 also | 7 | --- |
7 | supports GICv2 emulation. This will be useful to choose the | 8 | target/arm/tcg/a64.decode | 31 ++++ |
8 | default version in KVM accelerated mode. | 9 | target/arm/tcg/translate-a64.c | 277 ++++++++++++++++++--------------- |
10 | 2 files changed, 185 insertions(+), 123 deletions(-) | ||
9 | 11 | ||
10 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
11 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20200311131618.7187-5-eric.auger@redhat.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | target/arm/kvm_arm.h | 3 +++ | ||
17 | hw/arm/virt.c | 11 +++++++++-- | ||
18 | target/arm/kvm.c | 14 ++++++++------ | ||
19 | 3 files changed, 20 insertions(+), 8 deletions(-) | ||
20 | |||
21 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/kvm_arm.h | 14 | --- a/target/arm/tcg/a64.decode |
24 | +++ b/target/arm/kvm_arm.h | 15 | +++ b/target/arm/tcg/a64.decode |
25 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB |
26 | #include "exec/memory.h" | 17 | # the processor is in halting debug state (which we don't implement). |
27 | #include "qemu/error-report.h" | 18 | # The pattern is listed here as documentation. |
28 | 19 | # DRPS 1101011 0101 11111 000000 11111 00000 | |
29 | +#define KVM_ARM_VGIC_V2 (1 << 0) | 20 | + |
30 | +#define KVM_ARM_VGIC_V3 (1 << 1) | 21 | +# Hint instruction group |
31 | + | 22 | +{ |
32 | /** | 23 | + [ |
33 | * kvm_arm_vcpu_init: | 24 | + YIELD 1101 0101 0000 0011 0010 0000 001 11111 |
34 | * @cs: CPUState | 25 | + WFE 1101 0101 0000 0011 0010 0000 010 11111 |
35 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 26 | + WFI 1101 0101 0000 0011 0010 0000 011 11111 |
27 | + # We implement WFE to never block, so our SEV/SEVL are NOPs | ||
28 | + # SEV 1101 0101 0000 0011 0010 0000 100 11111 | ||
29 | + # SEVL 1101 0101 0000 0011 0010 0000 101 11111 | ||
30 | + # Our DGL is a NOP because we don't merge memory accesses anyway. | ||
31 | + # DGL 1101 0101 0000 0011 0010 0000 110 11111 | ||
32 | + XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 | ||
33 | + PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 | ||
34 | + PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 | ||
35 | + AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 | ||
36 | + AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 | ||
37 | + ESB 1101 0101 0000 0011 0010 0010 000 11111 | ||
38 | + PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 | ||
39 | + PACIASP 1101 0101 0000 0011 0010 0011 001 11111 | ||
40 | + PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 | ||
41 | + PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 | ||
42 | + AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 | ||
43 | + AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 | ||
44 | + AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 | ||
45 | + AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 | ||
46 | + ] | ||
47 | + # The canonical NOP has CRm == op2 == 0, but all of the space | ||
48 | + # that isn't specifically allocated to an instruction must NOP | ||
49 | + NOP 1101 0101 0000 0011 0010 ---- --- 11111 | ||
50 | +} | ||
51 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/arm/virt.c | 53 | --- a/target/arm/tcg/translate-a64.c |
38 | +++ b/hw/arm/virt.c | 54 | +++ b/target/arm/tcg/translate-a64.c |
39 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | 55 | @@ -XXX,XX +XXX,XX @@ static bool trans_ERETA(DisasContext *s, arg_reta *a) |
40 | vms->gic_version = VIRT_GIC_VERSION_3; | 56 | return true; |
41 | } | 57 | } |
42 | } else { | 58 | |
43 | - vms->gic_version = kvm_arm_vgic_probe(); | 59 | -/* HINT instruction group, including various allocated HINTs */ |
44 | - if (!vms->gic_version) { | 60 | -static void handle_hint(DisasContext *s, uint32_t insn, |
45 | + int probe_bitmap = kvm_arm_vgic_probe(); | 61 | - unsigned int op1, unsigned int op2, unsigned int crm) |
46 | + | 62 | +static bool trans_NOP(DisasContext *s, arg_NOP *a) |
47 | + if (!probe_bitmap) { | 63 | { |
48 | error_report( | 64 | - unsigned int selector = crm << 3 | op2; |
49 | "Unable to determine GIC version supported by host"); | 65 | + return true; |
50 | exit(1); | 66 | +} |
51 | + } else { | 67 | |
52 | + if (probe_bitmap & KVM_ARM_VGIC_V3) { | 68 | - if (op1 != 3) { |
53 | + vms->gic_version = VIRT_GIC_VERSION_3; | 69 | - unallocated_encoding(s); |
54 | + } else { | 70 | - return; |
55 | + vms->gic_version = VIRT_GIC_VERSION_2; | 71 | +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) |
56 | + } | 72 | +{ |
57 | } | 73 | + /* |
74 | + * When running in MTTCG we don't generate jumps to the yield and | ||
75 | + * WFE helpers as it won't affect the scheduling of other vCPUs. | ||
76 | + * If we wanted to more completely model WFE/SEV so we don't busy | ||
77 | + * spin unnecessarily we would need to do something more involved. | ||
78 | + */ | ||
79 | + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { | ||
80 | + s->base.is_jmp = DISAS_YIELD; | ||
81 | } | ||
82 | + return true; | ||
83 | +} | ||
84 | |||
85 | - switch (selector) { | ||
86 | - case 0b00000: /* NOP */ | ||
87 | - break; | ||
88 | - case 0b00011: /* WFI */ | ||
89 | - s->base.is_jmp = DISAS_WFI; | ||
90 | - break; | ||
91 | - case 0b00001: /* YIELD */ | ||
92 | - /* When running in MTTCG we don't generate jumps to the yield and | ||
93 | - * WFE helpers as it won't affect the scheduling of other vCPUs. | ||
94 | - * If we wanted to more completely model WFE/SEV so we don't busy | ||
95 | - * spin unnecessarily we would need to do something more involved. | ||
96 | +static bool trans_WFI(DisasContext *s, arg_WFI *a) | ||
97 | +{ | ||
98 | + s->base.is_jmp = DISAS_WFI; | ||
99 | + return true; | ||
100 | +} | ||
101 | + | ||
102 | +static bool trans_WFE(DisasContext *s, arg_WFI *a) | ||
103 | +{ | ||
104 | + /* | ||
105 | + * When running in MTTCG we don't generate jumps to the yield and | ||
106 | + * WFE helpers as it won't affect the scheduling of other vCPUs. | ||
107 | + * If we wanted to more completely model WFE/SEV so we don't busy | ||
108 | + * spin unnecessarily we would need to do something more involved. | ||
109 | + */ | ||
110 | + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { | ||
111 | + s->base.is_jmp = DISAS_WFE; | ||
112 | + } | ||
113 | + return true; | ||
114 | +} | ||
115 | + | ||
116 | +static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a) | ||
117 | +{ | ||
118 | + if (s->pauth_active) { | ||
119 | + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); | ||
120 | + } | ||
121 | + return true; | ||
122 | +} | ||
123 | + | ||
124 | +static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a) | ||
125 | +{ | ||
126 | + if (s->pauth_active) { | ||
127 | + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
128 | + } | ||
129 | + return true; | ||
130 | +} | ||
131 | + | ||
132 | +static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a) | ||
133 | +{ | ||
134 | + if (s->pauth_active) { | ||
135 | + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
136 | + } | ||
137 | + return true; | ||
138 | +} | ||
139 | + | ||
140 | +static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a) | ||
141 | +{ | ||
142 | + if (s->pauth_active) { | ||
143 | + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
144 | + } | ||
145 | + return true; | ||
146 | +} | ||
147 | + | ||
148 | +static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a) | ||
149 | +{ | ||
150 | + if (s->pauth_active) { | ||
151 | + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
152 | + } | ||
153 | + return true; | ||
154 | +} | ||
155 | + | ||
156 | +static bool trans_ESB(DisasContext *s, arg_ESB *a) | ||
157 | +{ | ||
158 | + /* Without RAS, we must implement this as NOP. */ | ||
159 | + if (dc_isar_feature(aa64_ras, s)) { | ||
160 | + /* | ||
161 | + * QEMU does not have a source of physical SErrors, | ||
162 | + * so we are only concerned with virtual SErrors. | ||
163 | + * The pseudocode in the ARM for this case is | ||
164 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
165 | + * AArch64.vESBOperation(); | ||
166 | + * Most of the condition can be evaluated at translation time. | ||
167 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
168 | */ | ||
169 | - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { | ||
170 | - s->base.is_jmp = DISAS_YIELD; | ||
171 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
172 | + gen_helper_vesb(cpu_env); | ||
58 | } | 173 | } |
59 | } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) { | 174 | - break; |
60 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | 175 | - case 0b00010: /* WFE */ |
61 | index XXXXXXX..XXXXXXX 100644 | 176 | - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
62 | --- a/target/arm/kvm.c | 177 | - s->base.is_jmp = DISAS_WFE; |
63 | +++ b/target/arm/kvm.c | 178 | - } |
64 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s) | 179 | - break; |
65 | 180 | - case 0b00100: /* SEV */ | |
66 | int kvm_arm_vgic_probe(void) | 181 | - case 0b00101: /* SEVL */ |
67 | { | 182 | - case 0b00110: /* DGH */ |
68 | + int val = 0; | 183 | - /* we treat all as NOP at least for now */ |
69 | + | 184 | - break; |
70 | if (kvm_create_device(kvm_state, | 185 | - case 0b00111: /* XPACLRI */ |
71 | KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { | 186 | - if (s->pauth_active) { |
72 | - return 3; | 187 | - gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); |
73 | - } else if (kvm_create_device(kvm_state, | 188 | - } |
74 | - KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { | 189 | - break; |
75 | - return 2; | 190 | - case 0b01000: /* PACIA1716 */ |
76 | - } else { | 191 | - if (s->pauth_active) { |
77 | - return 0; | 192 | - gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); |
78 | + val |= KVM_ARM_VGIC_V3; | 193 | - } |
194 | - break; | ||
195 | - case 0b01010: /* PACIB1716 */ | ||
196 | - if (s->pauth_active) { | ||
197 | - gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
198 | - } | ||
199 | - break; | ||
200 | - case 0b01100: /* AUTIA1716 */ | ||
201 | - if (s->pauth_active) { | ||
202 | - gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
203 | - } | ||
204 | - break; | ||
205 | - case 0b01110: /* AUTIB1716 */ | ||
206 | - if (s->pauth_active) { | ||
207 | - gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | ||
208 | - } | ||
209 | - break; | ||
210 | - case 0b10000: /* ESB */ | ||
211 | - /* Without RAS, we must implement this as NOP. */ | ||
212 | - if (dc_isar_feature(aa64_ras, s)) { | ||
213 | - /* | ||
214 | - * QEMU does not have a source of physical SErrors, | ||
215 | - * so we are only concerned with virtual SErrors. | ||
216 | - * The pseudocode in the ARM for this case is | ||
217 | - * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
218 | - * AArch64.vESBOperation(); | ||
219 | - * Most of the condition can be evaluated at translation time. | ||
220 | - * Test for EL2 present, and defer test for SEL2 to runtime. | ||
221 | - */ | ||
222 | - if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
223 | - gen_helper_vesb(cpu_env); | ||
224 | - } | ||
225 | - } | ||
226 | - break; | ||
227 | - case 0b11000: /* PACIAZ */ | ||
228 | - if (s->pauth_active) { | ||
229 | - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | ||
230 | - tcg_constant_i64(0)); | ||
231 | - } | ||
232 | - break; | ||
233 | - case 0b11001: /* PACIASP */ | ||
234 | - if (s->pauth_active) { | ||
235 | - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
236 | - } | ||
237 | - break; | ||
238 | - case 0b11010: /* PACIBZ */ | ||
239 | - if (s->pauth_active) { | ||
240 | - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], | ||
241 | - tcg_constant_i64(0)); | ||
242 | - } | ||
243 | - break; | ||
244 | - case 0b11011: /* PACIBSP */ | ||
245 | - if (s->pauth_active) { | ||
246 | - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
247 | - } | ||
248 | - break; | ||
249 | - case 0b11100: /* AUTIAZ */ | ||
250 | - if (s->pauth_active) { | ||
251 | - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], | ||
252 | - tcg_constant_i64(0)); | ||
253 | - } | ||
254 | - break; | ||
255 | - case 0b11101: /* AUTIASP */ | ||
256 | - if (s->pauth_active) { | ||
257 | - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
258 | - } | ||
259 | - break; | ||
260 | - case 0b11110: /* AUTIBZ */ | ||
261 | - if (s->pauth_active) { | ||
262 | - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], | ||
263 | - tcg_constant_i64(0)); | ||
264 | - } | ||
265 | - break; | ||
266 | - case 0b11111: /* AUTIBSP */ | ||
267 | - if (s->pauth_active) { | ||
268 | - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
269 | - } | ||
270 | - break; | ||
271 | - default: | ||
272 | - /* default specified as NOP equivalent */ | ||
273 | - break; | ||
79 | } | 274 | } |
80 | + if (kvm_create_device(kvm_state, | 275 | + return true; |
81 | + KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { | 276 | +} |
82 | + val |= KVM_ARM_VGIC_V2; | 277 | + |
83 | + } | 278 | +static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a) |
84 | + return val; | 279 | +{ |
280 | + if (s->pauth_active) { | ||
281 | + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0)); | ||
282 | + } | ||
283 | + return true; | ||
284 | +} | ||
285 | + | ||
286 | +static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a) | ||
287 | +{ | ||
288 | + if (s->pauth_active) { | ||
289 | + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
290 | + } | ||
291 | + return true; | ||
292 | +} | ||
293 | + | ||
294 | +static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a) | ||
295 | +{ | ||
296 | + if (s->pauth_active) { | ||
297 | + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0)); | ||
298 | + } | ||
299 | + return true; | ||
300 | +} | ||
301 | + | ||
302 | +static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a) | ||
303 | +{ | ||
304 | + if (s->pauth_active) { | ||
305 | + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
306 | + } | ||
307 | + return true; | ||
308 | +} | ||
309 | + | ||
310 | +static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a) | ||
311 | +{ | ||
312 | + if (s->pauth_active) { | ||
313 | + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0)); | ||
314 | + } | ||
315 | + return true; | ||
316 | +} | ||
317 | + | ||
318 | +static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a) | ||
319 | +{ | ||
320 | + if (s->pauth_active) { | ||
321 | + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
322 | + } | ||
323 | + return true; | ||
324 | +} | ||
325 | + | ||
326 | +static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a) | ||
327 | +{ | ||
328 | + if (s->pauth_active) { | ||
329 | + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0)); | ||
330 | + } | ||
331 | + return true; | ||
332 | +} | ||
333 | + | ||
334 | +static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) | ||
335 | +{ | ||
336 | + if (s->pauth_active) { | ||
337 | + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | ||
338 | + } | ||
339 | + return true; | ||
85 | } | 340 | } |
86 | 341 | ||
87 | int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) | 342 | static void gen_clrex(DisasContext *s, uint32_t insn) |
343 | @@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn) | ||
344 | return; | ||
345 | } | ||
346 | switch (crn) { | ||
347 | - case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ | ||
348 | - handle_hint(s, insn, op1, op2, crm); | ||
349 | - break; | ||
350 | case 3: /* CLREX, DSB, DMB, ISB */ | ||
351 | handle_sync(s, insn, op1, op2, crm); | ||
352 | break; | ||
88 | -- | 353 | -- |
89 | 2.20.1 | 354 | 2.34.1 |
90 | |||
91 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | Convert the insns in the "Barriers" instruction class to |
---|---|---|---|
2 | decodetree: CLREX, DSB, DMB, ISB and SB. | ||
2 | 3 | ||
3 | This test boots Ubuntu Bionic on a OrangePi PC board. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | --- | ||
9 | target/arm/tcg/a64.decode | 7 +++ | ||
10 | target/arm/tcg/translate-a64.c | 92 ++++++++++++++-------------------- | ||
11 | 2 files changed, 46 insertions(+), 53 deletions(-) | ||
4 | 12 | ||
5 | As it requires 1GB of storage, and is slow, this test is disabled | 13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
6 | on automatic CI testing. | ||
7 | |||
8 | It is useful for workstation testing. Currently Avocado timeouts too | ||
9 | quickly, so we can't run userland commands. | ||
10 | |||
11 | The kernel image and DeviceTree blob are built by the Armbian | ||
12 | project (based on Debian): | ||
13 | https://www.armbian.com/orange-pi-pc/ | ||
14 | |||
15 | The Ubuntu image is downloaded from: | ||
16 | https://dl.armbian.com/orangepipc/Bionic_current | ||
17 | |||
18 | This test can be run using: | ||
19 | |||
20 | $ AVOCADO_ALLOW_LARGE_STORAGE=yes \ | ||
21 | avocado --show=app,console run -t machine:orangepi-pc \ | ||
22 | tests/acceptance/boot_linux_console.py | ||
23 | console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) | ||
24 | console: DRAM: 1024 MiB | ||
25 | console: Failed to set core voltage! Can't set CPU frequency | ||
26 | console: Trying to boot from MMC1 | ||
27 | console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology | ||
28 | console: CPU: Allwinner H3 (SUN8I 0000) | ||
29 | console: Model: Xunlong Orange Pi PC | ||
30 | console: DRAM: 1 GiB | ||
31 | console: MMC: mmc@1c0f000: 0 | ||
32 | [...] | ||
33 | console: Uncompressing Linux... done, booting the kernel. | ||
34 | console: Booting Linux on physical CPU 0x0 | ||
35 | console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019 | ||
36 | console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d | ||
37 | console: CPU: div instructions available: patching division code | ||
38 | console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
39 | console: OF: fdt: Machine model: Xunlong Orange Pi PC | ||
40 | [...] | ||
41 | console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null) | ||
42 | console: done. | ||
43 | console: Begin: Running /scripts/local-bottom ... done. | ||
44 | console: Begin: Running /scripts/init-bottom ... done. | ||
45 | console: systemd[1]: systemd 237 running in system mode. (...) | ||
46 | console: systemd[1]: Detected architecture arm. | ||
47 | console: Welcome to Ubuntu 18.04.3 LTS! | ||
48 | console: systemd[1]: Set hostname to <orangepipc>. | ||
49 | |||
50 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
51 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
52 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
53 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
54 | Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com | ||
55 | [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] | ||
56 | [NL: changed test to boot from SD card via BootROM, added check for 7z] | ||
57 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
58 | --- | ||
59 | tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++ | ||
60 | 1 file changed, 48 insertions(+) | ||
61 | |||
62 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | ||
63 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
64 | --- a/tests/acceptance/boot_linux_console.py | 15 | --- a/target/arm/tcg/a64.decode |
65 | +++ b/tests/acceptance/boot_linux_console.py | 16 | +++ b/target/arm/tcg/a64.decode |
66 | @@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern | 17 | @@ -XXX,XX +XXX,XX @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB |
67 | from avocado_qemu import wait_for_console_pattern | 18 | # that isn't specifically allocated to an instruction must NOP |
68 | from avocado.utils import process | 19 | NOP 1101 0101 0000 0011 0010 ---- --- 11111 |
69 | from avocado.utils import archive | 20 | } |
70 | +from avocado.utils.path import find_command, CmdNotFoundError | ||
71 | |||
72 | +P7ZIP_AVAILABLE = True | ||
73 | +try: | ||
74 | + find_command('7z') | ||
75 | +except CmdNotFoundError: | ||
76 | + P7ZIP_AVAILABLE = False | ||
77 | |||
78 | class BootLinuxConsole(Test): | ||
79 | """ | ||
80 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | ||
81 | exec_command_and_wait_for_pattern(self, 'reboot', | ||
82 | 'reboot: Restarting system') | ||
83 | |||
84 | + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') | ||
85 | + @skipUnless(P7ZIP_AVAILABLE, '7z not installed') | ||
86 | + def test_arm_orangepi_bionic(self): | ||
87 | + """ | ||
88 | + :avocado: tags=arch:arm | ||
89 | + :avocado: tags=machine:orangepi-pc | ||
90 | + """ | ||
91 | + | 21 | + |
92 | + # This test download a 196MB compressed image and expand it to 932MB... | 22 | +# Barriers |
93 | + image_url = ('https://dl.armbian.com/orangepipc/archive/' | ||
94 | + 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z') | ||
95 | + image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e' | ||
96 | + image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash) | ||
97 | + image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img' | ||
98 | + image_path = os.path.join(self.workdir, image_name) | ||
99 | + process.run("7z e -o%s %s" % (self.workdir, image_path_7z)) | ||
100 | + | 23 | + |
101 | + self.vm.set_console() | 24 | +CLREX 1101 0101 0000 0011 0011 ---- 010 11111 |
102 | + self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw', | 25 | +DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 |
103 | + '-nic', 'user', | 26 | +ISB 1101 0101 0000 0011 0011 ---- 110 11111 |
104 | + '-no-reboot') | 27 | +SB 1101 0101 0000 0011 0011 0000 111 11111 |
105 | + self.vm.launch() | 28 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
106 | + | 29 | index XXXXXXX..XXXXXXX 100644 |
107 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | 30 | --- a/target/arm/tcg/translate-a64.c |
108 | + 'console=ttyS0,115200 ' | 31 | +++ b/target/arm/tcg/translate-a64.c |
109 | + 'loglevel=7 ' | 32 | @@ -XXX,XX +XXX,XX @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) |
110 | + 'nosmp ' | 33 | return true; |
111 | + 'systemd.default_timeout_start_sec=9000 ' | 34 | } |
112 | + 'systemd.mask=armbian-zram-config.service ' | 35 | |
113 | + 'systemd.mask=armbian-ramlog.service') | 36 | -static void gen_clrex(DisasContext *s, uint32_t insn) |
114 | + | 37 | +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) |
115 | + self.wait_for_console_pattern('U-Boot SPL') | 38 | { |
116 | + self.wait_for_console_pattern('Autoboot in ') | 39 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); |
117 | + exec_command_and_wait_for_pattern(self, ' ', '=>') | 40 | + return true; |
118 | + exec_command_and_wait_for_pattern(self, "setenv extraargs '" + | 41 | } |
119 | + kernel_command_line + "'", '=>') | 42 | |
120 | + exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...'); | 43 | -/* CLREX, DSB, DMB, ISB */ |
121 | + | 44 | -static void handle_sync(DisasContext *s, uint32_t insn, |
122 | + self.wait_for_console_pattern('systemd[1]: Set hostname ' + | 45 | - unsigned int op1, unsigned int op2, unsigned int crm) |
123 | + 'to <orangepipc>') | 46 | +static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a) |
124 | + self.wait_for_console_pattern('Starting Load Kernel Modules...') | 47 | { |
125 | + | 48 | + /* We handle DSB and DMB the same way */ |
126 | def test_s390x_s390_ccw_virtio(self): | 49 | TCGBar bar; |
127 | """ | 50 | |
128 | :avocado: tags=arch:s390x | 51 | - if (op1 != 3) { |
52 | - unallocated_encoding(s); | ||
53 | - return; | ||
54 | + switch (a->types) { | ||
55 | + case 1: /* MBReqTypes_Reads */ | ||
56 | + bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | ||
57 | + break; | ||
58 | + case 2: /* MBReqTypes_Writes */ | ||
59 | + bar = TCG_BAR_SC | TCG_MO_ST_ST; | ||
60 | + break; | ||
61 | + default: /* MBReqTypes_All */ | ||
62 | + bar = TCG_BAR_SC | TCG_MO_ALL; | ||
63 | + break; | ||
64 | } | ||
65 | + tcg_gen_mb(bar); | ||
66 | + return true; | ||
67 | +} | ||
68 | |||
69 | - switch (op2) { | ||
70 | - case 2: /* CLREX */ | ||
71 | - gen_clrex(s, insn); | ||
72 | - return; | ||
73 | - case 4: /* DSB */ | ||
74 | - case 5: /* DMB */ | ||
75 | - switch (crm & 3) { | ||
76 | - case 1: /* MBReqTypes_Reads */ | ||
77 | - bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | ||
78 | - break; | ||
79 | - case 2: /* MBReqTypes_Writes */ | ||
80 | - bar = TCG_BAR_SC | TCG_MO_ST_ST; | ||
81 | - break; | ||
82 | - default: /* MBReqTypes_All */ | ||
83 | - bar = TCG_BAR_SC | TCG_MO_ALL; | ||
84 | - break; | ||
85 | - } | ||
86 | - tcg_gen_mb(bar); | ||
87 | - return; | ||
88 | - case 6: /* ISB */ | ||
89 | - /* We need to break the TB after this insn to execute | ||
90 | - * a self-modified code correctly and also to take | ||
91 | - * any pending interrupts immediately. | ||
92 | - */ | ||
93 | - reset_btype(s); | ||
94 | - gen_goto_tb(s, 0, 4); | ||
95 | - return; | ||
96 | +static bool trans_ISB(DisasContext *s, arg_ISB *a) | ||
97 | +{ | ||
98 | + /* | ||
99 | + * We need to break the TB after this insn to execute | ||
100 | + * self-modifying code correctly and also to take | ||
101 | + * any pending interrupts immediately. | ||
102 | + */ | ||
103 | + reset_btype(s); | ||
104 | + gen_goto_tb(s, 0, 4); | ||
105 | + return true; | ||
106 | +} | ||
107 | |||
108 | - case 7: /* SB */ | ||
109 | - if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { | ||
110 | - goto do_unallocated; | ||
111 | - } | ||
112 | - /* | ||
113 | - * TODO: There is no speculation barrier opcode for TCG; | ||
114 | - * MB and end the TB instead. | ||
115 | - */ | ||
116 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | ||
117 | - gen_goto_tb(s, 0, 4); | ||
118 | - return; | ||
119 | - | ||
120 | - default: | ||
121 | - do_unallocated: | ||
122 | - unallocated_encoding(s); | ||
123 | - return; | ||
124 | +static bool trans_SB(DisasContext *s, arg_SB *a) | ||
125 | +{ | ||
126 | + if (!dc_isar_feature(aa64_sb, s)) { | ||
127 | + return false; | ||
128 | } | ||
129 | + /* | ||
130 | + * TODO: There is no speculation barrier opcode for TCG; | ||
131 | + * MB and end the TB instead. | ||
132 | + */ | ||
133 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | ||
134 | + gen_goto_tb(s, 0, 4); | ||
135 | + return true; | ||
136 | } | ||
137 | |||
138 | static void gen_xaflag(void) | ||
139 | @@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn) | ||
140 | return; | ||
141 | } | ||
142 | switch (crn) { | ||
143 | - case 3: /* CLREX, DSB, DMB, ISB */ | ||
144 | - handle_sync(s, insn, op1, op2, crm); | ||
145 | - break; | ||
146 | case 4: /* MSR (immediate) */ | ||
147 | handle_msr_i(s, insn, op1, op2, crm); | ||
148 | break; | ||
129 | -- | 149 | -- |
130 | 2.20.1 | 150 | 2.34.1 |
131 | 151 | ||
132 | 152 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | Convert the CFINV, XAFLAG and AXFLAG insns to decodetree. |
---|---|---|---|
2 | The old decoder handles these in handle_msr_i(), but | ||
3 | the architecture defines them as separate instructions | ||
4 | from MSR (immediate). | ||
2 | 5 | ||
3 | i.MX25 supports two USB controllers. Let's wire them up. | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/a64.decode | 6 ++++ | ||
11 | target/arm/tcg/translate-a64.c | 53 +++++++++++++++++----------------- | ||
12 | 2 files changed, 32 insertions(+), 27 deletions(-) | ||
4 | 13 | ||
5 | With this patch, imx25-pdk can boot from both USB ports. | 14 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
6 | |||
7 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
8 | Message-id: 20200310215146.19688-3-linux@roeck-us.net | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/fsl-imx25.h | 9 +++++++++ | ||
13 | hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++ | ||
14 | 2 files changed, 33 insertions(+) | ||
15 | |||
16 | diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/fsl-imx25.h | 16 | --- a/target/arm/tcg/a64.decode |
19 | +++ b/include/hw/arm/fsl-imx25.h | 17 | +++ b/target/arm/tcg/a64.decode |
20 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ CLREX 1101 0101 0000 0011 0011 ---- 010 11111 |
21 | #include "hw/i2c/imx_i2c.h" | 19 | DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 |
22 | #include "hw/gpio/imx_gpio.h" | 20 | ISB 1101 0101 0000 0011 0011 ---- 110 11111 |
23 | #include "hw/sd/sdhci.h" | 21 | SB 1101 0101 0000 0011 0011 0000 111 11111 |
24 | +#include "hw/usb/chipidea.h" | 22 | + |
25 | #include "exec/memory.h" | 23 | +# PSTATE |
26 | #include "target/arm/cpu.h" | 24 | + |
27 | 25 | +CFINV 1101 0101 0000 0 000 0100 0000 000 11111 | |
28 | @@ -XXX,XX +XXX,XX @@ | 26 | +XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 |
29 | #define FSL_IMX25_NUM_I2CS 3 | 27 | +AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 |
30 | #define FSL_IMX25_NUM_GPIOS 4 | 28 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
31 | #define FSL_IMX25_NUM_ESDHCS 2 | ||
32 | +#define FSL_IMX25_NUM_USBS 2 | ||
33 | |||
34 | typedef struct FslIMX25State { | ||
35 | /*< private >*/ | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | ||
37 | IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; | ||
38 | IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; | ||
39 | SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS]; | ||
40 | + ChipideaState usb[FSL_IMX25_NUM_USBS]; | ||
41 | MemoryRegion rom[2]; | ||
42 | MemoryRegion iram; | ||
43 | MemoryRegion iram_alias; | ||
44 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | ||
45 | #define FSL_IMX25_GPIO1_SIZE 0x4000 | ||
46 | #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 | ||
47 | #define FSL_IMX25_GPIO2_SIZE 0x4000 | ||
48 | +#define FSL_IMX25_USB1_ADDR 0x53FF4000 | ||
49 | +#define FSL_IMX25_USB1_SIZE 0x0200 | ||
50 | +#define FSL_IMX25_USB2_ADDR 0x53FF4400 | ||
51 | +#define FSL_IMX25_USB2_SIZE 0x0200 | ||
52 | #define FSL_IMX25_AVIC_ADDR 0x68000000 | ||
53 | #define FSL_IMX25_AVIC_SIZE 0x4000 | ||
54 | #define FSL_IMX25_IRAM_ADDR 0x78000000 | ||
55 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | ||
56 | #define FSL_IMX25_GPIO4_IRQ 23 | ||
57 | #define FSL_IMX25_ESDHC1_IRQ 9 | ||
58 | #define FSL_IMX25_ESDHC2_IRQ 8 | ||
59 | +#define FSL_IMX25_USB1_IRQ 37 | ||
60 | +#define FSL_IMX25_USB2_IRQ 35 | ||
61 | |||
62 | #endif /* FSL_IMX25_H */ | ||
63 | diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
65 | --- a/hw/arm/fsl-imx25.c | 30 | --- a/target/arm/tcg/translate-a64.c |
66 | +++ b/hw/arm/fsl-imx25.c | 31 | +++ b/target/arm/tcg/translate-a64.c |
67 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj) | 32 | @@ -XXX,XX +XXX,XX @@ static bool trans_SB(DisasContext *s, arg_SB *a) |
68 | sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]), | 33 | return true; |
69 | TYPE_IMX_USDHC); | 34 | } |
70 | } | 35 | |
36 | -static void gen_xaflag(void) | ||
37 | +static bool trans_CFINV(DisasContext *s, arg_CFINV *a) | ||
38 | { | ||
39 | - TCGv_i32 z = tcg_temp_new_i32(); | ||
40 | + if (!dc_isar_feature(aa64_condm_4, s)) { | ||
41 | + return false; | ||
42 | + } | ||
43 | + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | ||
44 | + return true; | ||
45 | +} | ||
71 | + | 46 | + |
72 | + for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { | 47 | +static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a) |
73 | + sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]), | 48 | +{ |
74 | + TYPE_CHIPIDEA); | 49 | + TCGv_i32 z; |
50 | + | ||
51 | + if (!dc_isar_feature(aa64_condm_5, s)) { | ||
52 | + return false; | ||
75 | + } | 53 | + } |
76 | + | 54 | + |
55 | + z = tcg_temp_new_i32(); | ||
56 | |||
57 | tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ static void gen_xaflag(void) | ||
60 | |||
61 | /* C | Z */ | ||
62 | tcg_gen_or_i32(cpu_CF, cpu_CF, z); | ||
63 | + | ||
64 | + return true; | ||
77 | } | 65 | } |
78 | 66 | ||
79 | static void fsl_imx25_realize(DeviceState *dev, Error **errp) | 67 | -static void gen_axflag(void) |
80 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) | 68 | +static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a) |
81 | esdhc_table[i].irq)); | 69 | { |
82 | } | 70 | + if (!dc_isar_feature(aa64_condm_5, s)) { |
83 | 71 | + return false; | |
84 | + /* USB */ | ||
85 | + for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { | ||
86 | + static const struct { | ||
87 | + hwaddr addr; | ||
88 | + unsigned int irq; | ||
89 | + } usb_table[FSL_IMX25_NUM_USBS] = { | ||
90 | + { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ }, | ||
91 | + { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ }, | ||
92 | + }; | ||
93 | + | ||
94 | + object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", | ||
95 | + &error_abort); | ||
96 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); | ||
97 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
98 | + qdev_get_gpio_in(DEVICE(&s->avic), | ||
99 | + usb_table[i].irq)); | ||
100 | + } | 72 | + } |
101 | + | 73 | + |
102 | /* initialize 2 x 16 KB ROM */ | 74 | tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ |
103 | memory_region_init_rom(&s->rom[0], NULL, | 75 | tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ |
104 | "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); | 76 | |
77 | @@ -XXX,XX +XXX,XX @@ static void gen_axflag(void) | ||
78 | |||
79 | tcg_gen_movi_i32(cpu_NF, 0); | ||
80 | tcg_gen_movi_i32(cpu_VF, 0); | ||
81 | + | ||
82 | + return true; | ||
83 | } | ||
84 | |||
85 | /* MSR (immediate) - move immediate to processor state field */ | ||
86 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
87 | s->base.is_jmp = DISAS_TOO_MANY; | ||
88 | |||
89 | switch (op) { | ||
90 | - case 0x00: /* CFINV */ | ||
91 | - if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { | ||
92 | - goto do_unallocated; | ||
93 | - } | ||
94 | - tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | ||
95 | - s->base.is_jmp = DISAS_NEXT; | ||
96 | - break; | ||
97 | - | ||
98 | - case 0x01: /* XAFlag */ | ||
99 | - if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | ||
100 | - goto do_unallocated; | ||
101 | - } | ||
102 | - gen_xaflag(); | ||
103 | - s->base.is_jmp = DISAS_NEXT; | ||
104 | - break; | ||
105 | - | ||
106 | - case 0x02: /* AXFlag */ | ||
107 | - if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | ||
108 | - goto do_unallocated; | ||
109 | - } | ||
110 | - gen_axflag(); | ||
111 | - s->base.is_jmp = DISAS_NEXT; | ||
112 | - break; | ||
113 | - | ||
114 | case 0x03: /* UAO */ | ||
115 | if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { | ||
116 | goto do_unallocated; | ||
105 | -- | 117 | -- |
106 | 2.20.1 | 118 | 2.34.1 |
107 | |||
108 | diff view generated by jsdifflib |
1 | For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index | 1 | Convert the MSR (immediate) insn to decodetree. Our implementation |
---|---|---|---|
2 | (it changes the NegPri bit). We update the hflags after calls | 2 | has basically no commonality between the different destinations, |
3 | to the v7m_msr helper in trans_MSR_v7m() but forgot to do so | 3 | so we decode the destination register in a64.decode. |
4 | in trans_CPS_v7m(). | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20200303174950.3298-3-peter.maydell@linaro.org | 7 | Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org |
9 | --- | 8 | --- |
10 | target/arm/translate.c | 5 ++++- | 9 | target/arm/tcg/a64.decode | 13 ++ |
11 | 1 file changed, 4 insertions(+), 1 deletion(-) | 10 | target/arm/tcg/translate-a64.c | 251 ++++++++++++++++----------------- |
11 | 2 files changed, 136 insertions(+), 128 deletions(-) | ||
12 | 12 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 15 | --- a/target/arm/tcg/a64.decode |
16 | +++ b/target/arm/translate.c | 16 | +++ b/target/arm/tcg/a64.decode |
17 | @@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) | 17 | @@ -XXX,XX +XXX,XX @@ SB 1101 0101 0000 0011 0011 0000 111 11111 |
18 | 18 | CFINV 1101 0101 0000 0 000 0100 0000 000 11111 | |
19 | static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) | 19 | XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 |
20 | AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 | ||
21 | + | ||
22 | +# These are architecturally all "MSR (immediate)"; we decode the destination | ||
23 | +# register too because there is no commonality in our implementation. | ||
24 | +@msr_i .... .... .... . ... .... imm:4 ... ..... | ||
25 | +MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i | ||
26 | +MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i | ||
27 | +MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i | ||
28 | +MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i | ||
29 | +MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i | ||
30 | +MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i | ||
31 | +MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i | ||
32 | +MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i | ||
33 | +MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 | ||
34 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/tcg/translate-a64.c | ||
37 | +++ b/target/arm/tcg/translate-a64.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a) | ||
39 | return true; | ||
40 | } | ||
41 | |||
42 | -/* MSR (immediate) - move immediate to processor state field */ | ||
43 | -static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
44 | - unsigned int op1, unsigned int op2, unsigned int crm) | ||
45 | +static bool trans_MSR_i_UAO(DisasContext *s, arg_i *a) | ||
20 | { | 46 | { |
21 | - TCGv_i32 tmp, addr; | 47 | - int op = op1 << 3 | op2; |
22 | + TCGv_i32 tmp, addr, el; | 48 | - |
23 | 49 | - /* End the TB by default, chaining is ok. */ | |
24 | if (!arm_dc_feature(s, ARM_FEATURE_M)) { | 50 | - s->base.is_jmp = DISAS_TOO_MANY; |
25 | return false; | 51 | - |
26 | @@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) | 52 | - switch (op) { |
27 | gen_helper_v7m_msr(cpu_env, addr, tmp); | 53 | - case 0x03: /* UAO */ |
28 | tcg_temp_free_i32(addr); | 54 | - if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { |
55 | - goto do_unallocated; | ||
56 | - } | ||
57 | - if (crm & 1) { | ||
58 | - set_pstate_bits(PSTATE_UAO); | ||
59 | - } else { | ||
60 | - clear_pstate_bits(PSTATE_UAO); | ||
61 | - } | ||
62 | - gen_rebuild_hflags(s); | ||
63 | - break; | ||
64 | - | ||
65 | - case 0x04: /* PAN */ | ||
66 | - if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { | ||
67 | - goto do_unallocated; | ||
68 | - } | ||
69 | - if (crm & 1) { | ||
70 | - set_pstate_bits(PSTATE_PAN); | ||
71 | - } else { | ||
72 | - clear_pstate_bits(PSTATE_PAN); | ||
73 | - } | ||
74 | - gen_rebuild_hflags(s); | ||
75 | - break; | ||
76 | - | ||
77 | - case 0x05: /* SPSel */ | ||
78 | - if (s->current_el == 0) { | ||
79 | - goto do_unallocated; | ||
80 | - } | ||
81 | - gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP)); | ||
82 | - break; | ||
83 | - | ||
84 | - case 0x19: /* SSBS */ | ||
85 | - if (!dc_isar_feature(aa64_ssbs, s)) { | ||
86 | - goto do_unallocated; | ||
87 | - } | ||
88 | - if (crm & 1) { | ||
89 | - set_pstate_bits(PSTATE_SSBS); | ||
90 | - } else { | ||
91 | - clear_pstate_bits(PSTATE_SSBS); | ||
92 | - } | ||
93 | - /* Don't need to rebuild hflags since SSBS is a nop */ | ||
94 | - break; | ||
95 | - | ||
96 | - case 0x1a: /* DIT */ | ||
97 | - if (!dc_isar_feature(aa64_dit, s)) { | ||
98 | - goto do_unallocated; | ||
99 | - } | ||
100 | - if (crm & 1) { | ||
101 | - set_pstate_bits(PSTATE_DIT); | ||
102 | - } else { | ||
103 | - clear_pstate_bits(PSTATE_DIT); | ||
104 | - } | ||
105 | - /* There's no need to rebuild hflags because DIT is a nop */ | ||
106 | - break; | ||
107 | - | ||
108 | - case 0x1e: /* DAIFSet */ | ||
109 | - gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm)); | ||
110 | - break; | ||
111 | - | ||
112 | - case 0x1f: /* DAIFClear */ | ||
113 | - gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm)); | ||
114 | - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ | ||
115 | - s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
116 | - break; | ||
117 | - | ||
118 | - case 0x1c: /* TCO */ | ||
119 | - if (dc_isar_feature(aa64_mte, s)) { | ||
120 | - /* Full MTE is enabled -- set the TCO bit as directed. */ | ||
121 | - if (crm & 1) { | ||
122 | - set_pstate_bits(PSTATE_TCO); | ||
123 | - } else { | ||
124 | - clear_pstate_bits(PSTATE_TCO); | ||
125 | - } | ||
126 | - gen_rebuild_hflags(s); | ||
127 | - /* Many factors, including TCO, go into MTE_ACTIVE. */ | ||
128 | - s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
129 | - } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
130 | - /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ | ||
131 | - s->base.is_jmp = DISAS_NEXT; | ||
132 | - } else { | ||
133 | - goto do_unallocated; | ||
134 | - } | ||
135 | - break; | ||
136 | - | ||
137 | - case 0x1b: /* SVCR* */ | ||
138 | - if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) { | ||
139 | - goto do_unallocated; | ||
140 | - } | ||
141 | - if (sme_access_check(s)) { | ||
142 | - int old = s->pstate_sm | (s->pstate_za << 1); | ||
143 | - int new = (crm & 1) * 3; | ||
144 | - int msk = (crm >> 1) & 3; | ||
145 | - | ||
146 | - if ((old ^ new) & msk) { | ||
147 | - /* At least one bit changes. */ | ||
148 | - gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), | ||
149 | - tcg_constant_i32(msk)); | ||
150 | - } else { | ||
151 | - s->base.is_jmp = DISAS_NEXT; | ||
152 | - } | ||
153 | - } | ||
154 | - break; | ||
155 | - | ||
156 | - default: | ||
157 | - do_unallocated: | ||
158 | - unallocated_encoding(s); | ||
159 | - return; | ||
160 | + if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { | ||
161 | + return false; | ||
29 | } | 162 | } |
30 | + el = tcg_const_i32(s->current_el); | 163 | + if (a->imm & 1) { |
31 | + gen_helper_rebuild_hflags_m32(cpu_env, el); | 164 | + set_pstate_bits(PSTATE_UAO); |
32 | + tcg_temp_free_i32(el); | 165 | + } else { |
33 | tcg_temp_free_i32(tmp); | 166 | + clear_pstate_bits(PSTATE_UAO); |
34 | gen_lookup_tb(s); | 167 | + } |
35 | return true; | 168 | + gen_rebuild_hflags(s); |
169 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
170 | + return true; | ||
171 | +} | ||
172 | + | ||
173 | +static bool trans_MSR_i_PAN(DisasContext *s, arg_i *a) | ||
174 | +{ | ||
175 | + if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { | ||
176 | + return false; | ||
177 | + } | ||
178 | + if (a->imm & 1) { | ||
179 | + set_pstate_bits(PSTATE_PAN); | ||
180 | + } else { | ||
181 | + clear_pstate_bits(PSTATE_PAN); | ||
182 | + } | ||
183 | + gen_rebuild_hflags(s); | ||
184 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
185 | + return true; | ||
186 | +} | ||
187 | + | ||
188 | +static bool trans_MSR_i_SPSEL(DisasContext *s, arg_i *a) | ||
189 | +{ | ||
190 | + if (s->current_el == 0) { | ||
191 | + return false; | ||
192 | + } | ||
193 | + gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP)); | ||
194 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
195 | + return true; | ||
196 | +} | ||
197 | + | ||
198 | +static bool trans_MSR_i_SBSS(DisasContext *s, arg_i *a) | ||
199 | +{ | ||
200 | + if (!dc_isar_feature(aa64_ssbs, s)) { | ||
201 | + return false; | ||
202 | + } | ||
203 | + if (a->imm & 1) { | ||
204 | + set_pstate_bits(PSTATE_SSBS); | ||
205 | + } else { | ||
206 | + clear_pstate_bits(PSTATE_SSBS); | ||
207 | + } | ||
208 | + /* Don't need to rebuild hflags since SSBS is a nop */ | ||
209 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
210 | + return true; | ||
211 | +} | ||
212 | + | ||
213 | +static bool trans_MSR_i_DIT(DisasContext *s, arg_i *a) | ||
214 | +{ | ||
215 | + if (!dc_isar_feature(aa64_dit, s)) { | ||
216 | + return false; | ||
217 | + } | ||
218 | + if (a->imm & 1) { | ||
219 | + set_pstate_bits(PSTATE_DIT); | ||
220 | + } else { | ||
221 | + clear_pstate_bits(PSTATE_DIT); | ||
222 | + } | ||
223 | + /* There's no need to rebuild hflags because DIT is a nop */ | ||
224 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
225 | + return true; | ||
226 | +} | ||
227 | + | ||
228 | +static bool trans_MSR_i_TCO(DisasContext *s, arg_i *a) | ||
229 | +{ | ||
230 | + if (dc_isar_feature(aa64_mte, s)) { | ||
231 | + /* Full MTE is enabled -- set the TCO bit as directed. */ | ||
232 | + if (a->imm & 1) { | ||
233 | + set_pstate_bits(PSTATE_TCO); | ||
234 | + } else { | ||
235 | + clear_pstate_bits(PSTATE_TCO); | ||
236 | + } | ||
237 | + gen_rebuild_hflags(s); | ||
238 | + /* Many factors, including TCO, go into MTE_ACTIVE. */ | ||
239 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
240 | + return true; | ||
241 | + } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
242 | + /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ | ||
243 | + return true; | ||
244 | + } else { | ||
245 | + /* Insn not present */ | ||
246 | + return false; | ||
247 | + } | ||
248 | +} | ||
249 | + | ||
250 | +static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a) | ||
251 | +{ | ||
252 | + gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm)); | ||
253 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
254 | + return true; | ||
255 | +} | ||
256 | + | ||
257 | +static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a) | ||
258 | +{ | ||
259 | + gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm)); | ||
260 | + /* Exit the cpu loop to re-evaluate pending IRQs. */ | ||
261 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
262 | + return true; | ||
263 | +} | ||
264 | + | ||
265 | +static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) | ||
266 | +{ | ||
267 | + if (!dc_isar_feature(aa64_sme, s) || a->mask == 0) { | ||
268 | + return false; | ||
269 | + } | ||
270 | + if (sme_access_check(s)) { | ||
271 | + int old = s->pstate_sm | (s->pstate_za << 1); | ||
272 | + int new = a->imm * 3; | ||
273 | + | ||
274 | + if ((old ^ new) & a->mask) { | ||
275 | + /* At least one bit changes. */ | ||
276 | + gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), | ||
277 | + tcg_constant_i32(a->mask)); | ||
278 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
279 | + } | ||
280 | + } | ||
281 | + return true; | ||
282 | } | ||
283 | |||
284 | static void gen_get_nzcv(TCGv_i64 tcg_rt) | ||
285 | @@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn) | ||
286 | rt = extract32(insn, 0, 5); | ||
287 | |||
288 | if (op0 == 0) { | ||
289 | - if (l || rt != 31) { | ||
290 | - unallocated_encoding(s); | ||
291 | - return; | ||
292 | - } | ||
293 | - switch (crn) { | ||
294 | - case 4: /* MSR (immediate) */ | ||
295 | - handle_msr_i(s, insn, op1, op2, crm); | ||
296 | - break; | ||
297 | - default: | ||
298 | - unallocated_encoding(s); | ||
299 | - break; | ||
300 | - } | ||
301 | + unallocated_encoding(s); | ||
302 | return; | ||
303 | } | ||
304 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); | ||
36 | -- | 305 | -- |
37 | 2.20.1 | 306 | 2.34.1 |
38 | |||
39 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are |
---|---|---|---|
2 | all essentially the same instruction (system register access). | ||
2 | 3 | ||
3 | Allwinner System-on-Chips usually contain a Real Time Clock (RTC) | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | for non-volatile system date and time keeping. This commit adds a generic | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Allwinner RTC device that supports the RTC devices found in Allwinner SoC | 6 | Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org |
6 | family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc). | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | The following RTC functionality and features are implemented: | 8 | --- |
9 | target/arm/tcg/a64.decode | 8 ++++++++ | ||
10 | target/arm/tcg/translate-a64.c | 32 +++++--------------------------- | ||
11 | 2 files changed, 13 insertions(+), 27 deletions(-) | ||
8 | 12 | ||
9 | * Year-Month-Day read/write | 13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
10 | * Hour-Minute-Second read/write | ||
11 | * General Purpose storage | ||
12 | |||
13 | The following boards are extended with the RTC device: | ||
14 | |||
15 | * Cubieboard (hw/arm/cubieboard.c) | ||
16 | * Orange Pi PC (hw/arm/orangepi.c) | ||
17 | |||
18 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
19 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
20 | Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | hw/rtc/Makefile.objs | 1 + | ||
24 | include/hw/arm/allwinner-a10.h | 2 + | ||
25 | include/hw/arm/allwinner-h3.h | 3 + | ||
26 | include/hw/rtc/allwinner-rtc.h | 134 +++++++++++ | ||
27 | hw/arm/allwinner-a10.c | 8 + | ||
28 | hw/arm/allwinner-h3.c | 9 +- | ||
29 | hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++ | ||
30 | hw/rtc/trace-events | 4 + | ||
31 | 8 files changed, 571 insertions(+), 1 deletion(-) | ||
32 | create mode 100644 include/hw/rtc/allwinner-rtc.h | ||
33 | create mode 100644 hw/rtc/allwinner-rtc.c | ||
34 | |||
35 | diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs | ||
36 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/rtc/Makefile.objs | 15 | --- a/target/arm/tcg/a64.decode |
38 | +++ b/hw/rtc/Makefile.objs | 16 | +++ b/target/arm/tcg/a64.decode |
39 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o | 17 | @@ -XXX,XX +XXX,XX @@ MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i |
40 | common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o | 18 | MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i |
41 | common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o | 19 | MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i |
42 | common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o | 20 | MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 |
43 | +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o | 21 | + |
44 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | 22 | +# MRS, MSR (register), SYS, SYSL. These are all essentially the |
23 | +# same instruction as far as QEMU is concerned. | ||
24 | +# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have | ||
25 | +# to hand-decode it. | ||
26 | +SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 | ||
27 | +SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 | ||
28 | +SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 | ||
29 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
46 | --- a/include/hw/arm/allwinner-a10.h | 31 | --- a/target/arm/tcg/translate-a64.c |
47 | +++ b/include/hw/arm/allwinner-a10.h | 32 | +++ b/target/arm/tcg/translate-a64.c |
48 | @@ -XXX,XX +XXX,XX @@ | 33 | @@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread, |
49 | #include "hw/ide/ahci.h" | 34 | * These are all essentially the same insn in 'read' and 'write' |
50 | #include "hw/usb/hcd-ohci.h" | 35 | * versions, with varying op0 fields. |
51 | #include "hw/usb/hcd-ehci.h" | 36 | */ |
52 | +#include "hw/rtc/allwinner-rtc.h" | 37 | -static void handle_sys(DisasContext *s, uint32_t insn, bool isread, |
53 | 38 | +static void handle_sys(DisasContext *s, bool isread, | |
54 | #include "target/arm/cpu.h" | 39 | unsigned int op0, unsigned int op1, unsigned int op2, |
55 | 40 | unsigned int crn, unsigned int crm, unsigned int rt) | |
56 | @@ -XXX,XX +XXX,XX @@ typedef struct AwA10State { | ||
57 | AwEmacState emac; | ||
58 | AllwinnerAHCIState sata; | ||
59 | AwSdHostState mmc0; | ||
60 | + AwRtcState rtc; | ||
61 | MemoryRegion sram_a; | ||
62 | EHCISysBusState ehci[AW_A10_NUM_USB]; | ||
63 | OHCISysBusState ohci[AW_A10_NUM_USB]; | ||
64 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/include/hw/arm/allwinner-h3.h | ||
67 | +++ b/include/hw/arm/allwinner-h3.h | ||
68 | @@ -XXX,XX +XXX,XX @@ | ||
69 | #include "hw/misc/allwinner-sid.h" | ||
70 | #include "hw/sd/allwinner-sdhost.h" | ||
71 | #include "hw/net/allwinner-sun8i-emac.h" | ||
72 | +#include "hw/rtc/allwinner-rtc.h" | ||
73 | #include "target/arm/cpu.h" | ||
74 | #include "sysemu/block-backend.h" | ||
75 | |||
76 | @@ -XXX,XX +XXX,XX @@ enum { | ||
77 | AW_H3_GIC_CPU, | ||
78 | AW_H3_GIC_HYP, | ||
79 | AW_H3_GIC_VCPU, | ||
80 | + AW_H3_RTC, | ||
81 | AW_H3_CPUCFG, | ||
82 | AW_H3_SDRAM | ||
83 | }; | ||
84 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
85 | AwSidState sid; | ||
86 | AwSdHostState mmc0; | ||
87 | AwSun8iEmacState emac; | ||
88 | + AwRtcState rtc; | ||
89 | GICState gic; | ||
90 | MemoryRegion sram_a1; | ||
91 | MemoryRegion sram_a2; | ||
92 | diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h | ||
93 | new file mode 100644 | ||
94 | index XXXXXXX..XXXXXXX | ||
95 | --- /dev/null | ||
96 | +++ b/include/hw/rtc/allwinner-rtc.h | ||
97 | @@ -XXX,XX +XXX,XX @@ | ||
98 | +/* | ||
99 | + * Allwinner Real Time Clock emulation | ||
100 | + * | ||
101 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
102 | + * | ||
103 | + * This program is free software: you can redistribute it and/or modify | ||
104 | + * it under the terms of the GNU General Public License as published by | ||
105 | + * the Free Software Foundation, either version 2 of the License, or | ||
106 | + * (at your option) any later version. | ||
107 | + * | ||
108 | + * This program is distributed in the hope that it will be useful, | ||
109 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
110 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
111 | + * GNU General Public License for more details. | ||
112 | + * | ||
113 | + * You should have received a copy of the GNU General Public License | ||
114 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
115 | + */ | ||
116 | + | ||
117 | +#ifndef HW_MISC_ALLWINNER_RTC_H | ||
118 | +#define HW_MISC_ALLWINNER_RTC_H | ||
119 | + | ||
120 | +#include "qom/object.h" | ||
121 | +#include "hw/sysbus.h" | ||
122 | + | ||
123 | +/** | ||
124 | + * Constants | ||
125 | + * @{ | ||
126 | + */ | ||
127 | + | ||
128 | +/** Highest register address used by RTC device */ | ||
129 | +#define AW_RTC_REGS_MAXADDR (0x200) | ||
130 | + | ||
131 | +/** Total number of known registers */ | ||
132 | +#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t)) | ||
133 | + | ||
134 | +/** @} */ | ||
135 | + | ||
136 | +/** | ||
137 | + * Object model types | ||
138 | + * @{ | ||
139 | + */ | ||
140 | + | ||
141 | +/** Generic Allwinner RTC device (abstract) */ | ||
142 | +#define TYPE_AW_RTC "allwinner-rtc" | ||
143 | + | ||
144 | +/** Allwinner RTC sun4i family (A10, A12) */ | ||
145 | +#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i" | ||
146 | + | ||
147 | +/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */ | ||
148 | +#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i" | ||
149 | + | ||
150 | +/** Allwinner RTC sun7i family (A20) */ | ||
151 | +#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i" | ||
152 | + | ||
153 | +/** @} */ | ||
154 | + | ||
155 | +/** | ||
156 | + * Object model macros | ||
157 | + * @{ | ||
158 | + */ | ||
159 | + | ||
160 | +#define AW_RTC(obj) \ | ||
161 | + OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC) | ||
162 | +#define AW_RTC_CLASS(klass) \ | ||
163 | + OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC) | ||
164 | +#define AW_RTC_GET_CLASS(obj) \ | ||
165 | + OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC) | ||
166 | + | ||
167 | +/** @} */ | ||
168 | + | ||
169 | +/** | ||
170 | + * Allwinner RTC per-object instance state. | ||
171 | + */ | ||
172 | +typedef struct AwRtcState { | ||
173 | + /*< private >*/ | ||
174 | + SysBusDevice parent_obj; | ||
175 | + /*< public >*/ | ||
176 | + | ||
177 | + /** | ||
178 | + * Actual year represented by the device when year counter is zero | ||
179 | + * | ||
180 | + * Can be overridden by the user using the corresponding 'base-year' | ||
181 | + * property. The base year used by the target OS driver can vary, for | ||
182 | + * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000. | ||
183 | + */ | ||
184 | + int base_year; | ||
185 | + | ||
186 | + /** Maps I/O registers in physical memory */ | ||
187 | + MemoryRegion iomem; | ||
188 | + | ||
189 | + /** Array of hardware registers */ | ||
190 | + uint32_t regs[AW_RTC_REGS_NUM]; | ||
191 | + | ||
192 | +} AwRtcState; | ||
193 | + | ||
194 | +/** | ||
195 | + * Allwinner RTC class-level struct. | ||
196 | + * | ||
197 | + * This struct is filled by each sunxi device specific code | ||
198 | + * such that the generic code can use this struct to support | ||
199 | + * all devices. | ||
200 | + */ | ||
201 | +typedef struct AwRtcClass { | ||
202 | + /*< private >*/ | ||
203 | + SysBusDeviceClass parent_class; | ||
204 | + /*< public >*/ | ||
205 | + | ||
206 | + /** Defines device specific register map */ | ||
207 | + const uint8_t *regmap; | ||
208 | + | ||
209 | + /** Size of the regmap in bytes */ | ||
210 | + size_t regmap_size; | ||
211 | + | ||
212 | + /** | ||
213 | + * Read device specific register | ||
214 | + * | ||
215 | + * @offset: register offset to read | ||
216 | + * @return true if register read successful, false otherwise | ||
217 | + */ | ||
218 | + bool (*read)(AwRtcState *s, uint32_t offset); | ||
219 | + | ||
220 | + /** | ||
221 | + * Write device specific register | ||
222 | + * | ||
223 | + * @offset: register offset to write | ||
224 | + * @data: value to set in register | ||
225 | + * @return true if register write successful, false otherwise | ||
226 | + */ | ||
227 | + bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data); | ||
228 | + | ||
229 | +} AwRtcClass; | ||
230 | + | ||
231 | +#endif /* HW_MISC_ALLWINNER_RTC_H */ | ||
232 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
233 | index XXXXXXX..XXXXXXX 100644 | ||
234 | --- a/hw/arm/allwinner-a10.c | ||
235 | +++ b/hw/arm/allwinner-a10.c | ||
236 | @@ -XXX,XX +XXX,XX @@ | ||
237 | #define AW_A10_EHCI_BASE 0x01c14000 | ||
238 | #define AW_A10_OHCI_BASE 0x01c14400 | ||
239 | #define AW_A10_SATA_BASE 0x01c18000 | ||
240 | +#define AW_A10_RTC_BASE 0x01c20d00 | ||
241 | |||
242 | static void aw_a10_init(Object *obj) | ||
243 | { | 41 | { |
244 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) | 42 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, |
245 | 43 | } | |
246 | sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), | ||
247 | TYPE_AW_SDHOST_SUN4I); | ||
248 | + | ||
249 | + sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), | ||
250 | + TYPE_AW_RTC_SUN4I); | ||
251 | } | 44 | } |
252 | 45 | ||
253 | static void aw_a10_realize(DeviceState *dev, Error **errp) | 46 | -/* System |
254 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 47 | - * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
255 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); | 48 | - * +---------------------+---+-----+-----+-------+-------+-----+------+ |
256 | object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), | 49 | - * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | |
257 | "sd-bus", &error_abort); | 50 | - * +---------------------+---+-----+-----+-------+-------+-----+------+ |
258 | + | 51 | - */ |
259 | + /* RTC */ | 52 | -static void disas_system(DisasContext *s, uint32_t insn) |
260 | + qdev_init_nofail(DEVICE(&s->rtc)); | 53 | +static bool trans_SYS(DisasContext *s, arg_SYS *a) |
261 | + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); | 54 | { |
55 | - unsigned int l, op0, op1, crn, crm, op2, rt; | ||
56 | - l = extract32(insn, 21, 1); | ||
57 | - op0 = extract32(insn, 19, 2); | ||
58 | - op1 = extract32(insn, 16, 3); | ||
59 | - crn = extract32(insn, 12, 4); | ||
60 | - crm = extract32(insn, 8, 4); | ||
61 | - op2 = extract32(insn, 5, 3); | ||
62 | - rt = extract32(insn, 0, 5); | ||
63 | - | ||
64 | - if (op0 == 0) { | ||
65 | - unallocated_encoding(s); | ||
66 | - return; | ||
67 | - } | ||
68 | - handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); | ||
69 | + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt); | ||
70 | + return true; | ||
262 | } | 71 | } |
263 | 72 | ||
264 | static void aw_a10_class_init(ObjectClass *oc, void *data) | 73 | /* Exception generation |
265 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | 74 | @@ -XXX,XX +XXX,XX @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
266 | index XXXXXXX..XXXXXXX 100644 | 75 | switch (extract32(insn, 25, 7)) { |
267 | --- a/hw/arm/allwinner-h3.c | 76 | case 0x6a: /* Exception generation / System */ |
268 | +++ b/hw/arm/allwinner-h3.c | 77 | if (insn & (1 << 24)) { |
269 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | 78 | - if (extract32(insn, 22, 2) == 0) { |
270 | [AW_H3_GIC_CPU] = 0x01c82000, | 79 | - disas_system(s, insn); |
271 | [AW_H3_GIC_HYP] = 0x01c84000, | 80 | - } else { |
272 | [AW_H3_GIC_VCPU] = 0x01c86000, | 81 | - unallocated_encoding(s); |
273 | + [AW_H3_RTC] = 0x01f00000, | 82 | - } |
274 | [AW_H3_CPUCFG] = 0x01f01c00, | 83 | + unallocated_encoding(s); |
275 | [AW_H3_SDRAM] = 0x40000000 | 84 | } else { |
276 | }; | 85 | disas_exc(s, insn); |
277 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | 86 | } |
278 | { "csi", 0x01cb0000, 320 * KiB }, | ||
279 | { "tve", 0x01e00000, 64 * KiB }, | ||
280 | { "hdmi", 0x01ee0000, 128 * KiB }, | ||
281 | - { "rtc", 0x01f00000, 1 * KiB }, | ||
282 | { "r_timer", 0x01f00800, 1 * KiB }, | ||
283 | { "r_intc", 0x01f00c00, 1 * KiB }, | ||
284 | { "r_wdog", 0x01f01000, 1 * KiB }, | ||
285 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
286 | "ram-addr", &error_abort); | ||
287 | object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc), | ||
288 | "ram-size", &error_abort); | ||
289 | + | ||
290 | + sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), | ||
291 | + TYPE_AW_RTC_SUN6I); | ||
292 | } | ||
293 | |||
294 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
295 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
296 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]); | ||
297 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]); | ||
298 | |||
299 | + /* RTC */ | ||
300 | + qdev_init_nofail(DEVICE(&s->rtc)); | ||
301 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]); | ||
302 | + | ||
303 | /* Unimplemented devices */ | ||
304 | for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { | ||
305 | create_unimplemented_device(unimplemented[i].device_name, | ||
306 | diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c | ||
307 | new file mode 100644 | ||
308 | index XXXXXXX..XXXXXXX | ||
309 | --- /dev/null | ||
310 | +++ b/hw/rtc/allwinner-rtc.c | ||
311 | @@ -XXX,XX +XXX,XX @@ | ||
312 | +/* | ||
313 | + * Allwinner Real Time Clock emulation | ||
314 | + * | ||
315 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
316 | + * | ||
317 | + * This program is free software: you can redistribute it and/or modify | ||
318 | + * it under the terms of the GNU General Public License as published by | ||
319 | + * the Free Software Foundation, either version 2 of the License, or | ||
320 | + * (at your option) any later version. | ||
321 | + * | ||
322 | + * This program is distributed in the hope that it will be useful, | ||
323 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
324 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
325 | + * GNU General Public License for more details. | ||
326 | + * | ||
327 | + * You should have received a copy of the GNU General Public License | ||
328 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
329 | + */ | ||
330 | + | ||
331 | +#include "qemu/osdep.h" | ||
332 | +#include "qemu/units.h" | ||
333 | +#include "hw/sysbus.h" | ||
334 | +#include "migration/vmstate.h" | ||
335 | +#include "qemu/log.h" | ||
336 | +#include "qemu/module.h" | ||
337 | +#include "qemu-common.h" | ||
338 | +#include "hw/qdev-properties.h" | ||
339 | +#include "hw/rtc/allwinner-rtc.h" | ||
340 | +#include "trace.h" | ||
341 | + | ||
342 | +/* RTC registers */ | ||
343 | +enum { | ||
344 | + REG_LOSC = 1, /* Low Oscillator Control */ | ||
345 | + REG_YYMMDD, /* RTC Year-Month-Day */ | ||
346 | + REG_HHMMSS, /* RTC Hour-Minute-Second */ | ||
347 | + REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */ | ||
348 | + REG_ALARM1_EN, /* Alarm1 Enable */ | ||
349 | + REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */ | ||
350 | + REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */ | ||
351 | + REG_GP0, /* General Purpose Register 0 */ | ||
352 | + REG_GP1, /* General Purpose Register 1 */ | ||
353 | + REG_GP2, /* General Purpose Register 2 */ | ||
354 | + REG_GP3, /* General Purpose Register 3 */ | ||
355 | + | ||
356 | + /* sun4i registers */ | ||
357 | + REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */ | ||
358 | + REG_CPUCFG, /* CPU Configuration Register */ | ||
359 | + | ||
360 | + /* sun6i registers */ | ||
361 | + REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */ | ||
362 | + REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */ | ||
363 | + REG_ALARM0_COUNTER, /* Alarm0 Counter */ | ||
364 | + REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */ | ||
365 | + REG_ALARM0_ENABLE, /* Alarm0 Enable */ | ||
366 | + REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */ | ||
367 | + REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */ | ||
368 | + REG_ALARM_CONFIG, /* Alarm Config */ | ||
369 | + REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */ | ||
370 | + REG_GP4, /* General Purpose Register 4 */ | ||
371 | + REG_GP5, /* General Purpose Register 5 */ | ||
372 | + REG_GP6, /* General Purpose Register 6 */ | ||
373 | + REG_GP7, /* General Purpose Register 7 */ | ||
374 | + REG_RTC_DBG, /* RTC Debug Register */ | ||
375 | + REG_GPL_HOLD_OUT, /* GPL Hold Output Register */ | ||
376 | + REG_VDD_RTC, /* VDD RTC Regulate Register */ | ||
377 | + REG_IC_CHARA, /* IC Characteristics Register */ | ||
378 | +}; | ||
379 | + | ||
380 | +/* RTC register flags */ | ||
381 | +enum { | ||
382 | + REG_LOSC_YMD = (1 << 7), | ||
383 | + REG_LOSC_HMS = (1 << 8), | ||
384 | +}; | ||
385 | + | ||
386 | +/* RTC sun4i register map (offset to name) */ | ||
387 | +const uint8_t allwinner_rtc_sun4i_regmap[] = { | ||
388 | + [0x0000] = REG_LOSC, | ||
389 | + [0x0004] = REG_YYMMDD, | ||
390 | + [0x0008] = REG_HHMMSS, | ||
391 | + [0x000C] = REG_ALARM1_DDHHMMSS, | ||
392 | + [0x0010] = REG_ALARM1_WKHHMMSS, | ||
393 | + [0x0014] = REG_ALARM1_EN, | ||
394 | + [0x0018] = REG_ALARM1_IRQ_EN, | ||
395 | + [0x001C] = REG_ALARM1_IRQ_STA, | ||
396 | + [0x0020] = REG_GP0, | ||
397 | + [0x0024] = REG_GP1, | ||
398 | + [0x0028] = REG_GP2, | ||
399 | + [0x002C] = REG_GP3, | ||
400 | + [0x003C] = REG_CPUCFG, | ||
401 | +}; | ||
402 | + | ||
403 | +/* RTC sun6i register map (offset to name) */ | ||
404 | +const uint8_t allwinner_rtc_sun6i_regmap[] = { | ||
405 | + [0x0000] = REG_LOSC, | ||
406 | + [0x0004] = REG_LOSC_AUTOSTA, | ||
407 | + [0x0008] = REG_INT_OSC_PRE, | ||
408 | + [0x0010] = REG_YYMMDD, | ||
409 | + [0x0014] = REG_HHMMSS, | ||
410 | + [0x0020] = REG_ALARM0_COUNTER, | ||
411 | + [0x0024] = REG_ALARM0_CUR_VLU, | ||
412 | + [0x0028] = REG_ALARM0_ENABLE, | ||
413 | + [0x002C] = REG_ALARM0_IRQ_EN, | ||
414 | + [0x0030] = REG_ALARM0_IRQ_STA, | ||
415 | + [0x0040] = REG_ALARM1_WKHHMMSS, | ||
416 | + [0x0044] = REG_ALARM1_EN, | ||
417 | + [0x0048] = REG_ALARM1_IRQ_EN, | ||
418 | + [0x004C] = REG_ALARM1_IRQ_STA, | ||
419 | + [0x0050] = REG_ALARM_CONFIG, | ||
420 | + [0x0060] = REG_LOSC_OUT_GATING, | ||
421 | + [0x0100] = REG_GP0, | ||
422 | + [0x0104] = REG_GP1, | ||
423 | + [0x0108] = REG_GP2, | ||
424 | + [0x010C] = REG_GP3, | ||
425 | + [0x0110] = REG_GP4, | ||
426 | + [0x0114] = REG_GP5, | ||
427 | + [0x0118] = REG_GP6, | ||
428 | + [0x011C] = REG_GP7, | ||
429 | + [0x0170] = REG_RTC_DBG, | ||
430 | + [0x0180] = REG_GPL_HOLD_OUT, | ||
431 | + [0x0190] = REG_VDD_RTC, | ||
432 | + [0x01F0] = REG_IC_CHARA, | ||
433 | +}; | ||
434 | + | ||
435 | +static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset) | ||
436 | +{ | ||
437 | + /* no sun4i specific registers currently implemented */ | ||
438 | + return false; | ||
439 | +} | ||
440 | + | ||
441 | +static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset, | ||
442 | + uint32_t data) | ||
443 | +{ | ||
444 | + /* no sun4i specific registers currently implemented */ | ||
445 | + return false; | ||
446 | +} | ||
447 | + | ||
448 | +static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset) | ||
449 | +{ | ||
450 | + const AwRtcClass *c = AW_RTC_GET_CLASS(s); | ||
451 | + | ||
452 | + switch (c->regmap[offset]) { | ||
453 | + case REG_GP4: /* General Purpose Register 4 */ | ||
454 | + case REG_GP5: /* General Purpose Register 5 */ | ||
455 | + case REG_GP6: /* General Purpose Register 6 */ | ||
456 | + case REG_GP7: /* General Purpose Register 7 */ | ||
457 | + return true; | ||
458 | + default: | ||
459 | + break; | ||
460 | + } | ||
461 | + return false; | ||
462 | +} | ||
463 | + | ||
464 | +static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset, | ||
465 | + uint32_t data) | ||
466 | +{ | ||
467 | + const AwRtcClass *c = AW_RTC_GET_CLASS(s); | ||
468 | + | ||
469 | + switch (c->regmap[offset]) { | ||
470 | + case REG_GP4: /* General Purpose Register 4 */ | ||
471 | + case REG_GP5: /* General Purpose Register 5 */ | ||
472 | + case REG_GP6: /* General Purpose Register 6 */ | ||
473 | + case REG_GP7: /* General Purpose Register 7 */ | ||
474 | + return true; | ||
475 | + default: | ||
476 | + break; | ||
477 | + } | ||
478 | + return false; | ||
479 | +} | ||
480 | + | ||
481 | +static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset, | ||
482 | + unsigned size) | ||
483 | +{ | ||
484 | + AwRtcState *s = AW_RTC(opaque); | ||
485 | + const AwRtcClass *c = AW_RTC_GET_CLASS(s); | ||
486 | + uint64_t val = 0; | ||
487 | + | ||
488 | + if (offset >= c->regmap_size) { | ||
489 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
490 | + __func__, (uint32_t)offset); | ||
491 | + return 0; | ||
492 | + } | ||
493 | + | ||
494 | + if (!c->regmap[offset]) { | ||
495 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n", | ||
496 | + __func__, (uint32_t)offset); | ||
497 | + return 0; | ||
498 | + } | ||
499 | + | ||
500 | + switch (c->regmap[offset]) { | ||
501 | + case REG_LOSC: /* Low Oscillator Control */ | ||
502 | + val = s->regs[REG_LOSC]; | ||
503 | + s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS); | ||
504 | + break; | ||
505 | + case REG_YYMMDD: /* RTC Year-Month-Day */ | ||
506 | + case REG_HHMMSS: /* RTC Hour-Minute-Second */ | ||
507 | + case REG_GP0: /* General Purpose Register 0 */ | ||
508 | + case REG_GP1: /* General Purpose Register 1 */ | ||
509 | + case REG_GP2: /* General Purpose Register 2 */ | ||
510 | + case REG_GP3: /* General Purpose Register 3 */ | ||
511 | + val = s->regs[c->regmap[offset]]; | ||
512 | + break; | ||
513 | + default: | ||
514 | + if (!c->read(s, offset)) { | ||
515 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n", | ||
516 | + __func__, (uint32_t)offset); | ||
517 | + } | ||
518 | + val = s->regs[c->regmap[offset]]; | ||
519 | + break; | ||
520 | + } | ||
521 | + | ||
522 | + trace_allwinner_rtc_read(offset, val); | ||
523 | + return val; | ||
524 | +} | ||
525 | + | ||
526 | +static void allwinner_rtc_write(void *opaque, hwaddr offset, | ||
527 | + uint64_t val, unsigned size) | ||
528 | +{ | ||
529 | + AwRtcState *s = AW_RTC(opaque); | ||
530 | + const AwRtcClass *c = AW_RTC_GET_CLASS(s); | ||
531 | + | ||
532 | + if (offset >= c->regmap_size) { | ||
533 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
534 | + __func__, (uint32_t)offset); | ||
535 | + return; | ||
536 | + } | ||
537 | + | ||
538 | + if (!c->regmap[offset]) { | ||
539 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n", | ||
540 | + __func__, (uint32_t)offset); | ||
541 | + return; | ||
542 | + } | ||
543 | + | ||
544 | + trace_allwinner_rtc_write(offset, val); | ||
545 | + | ||
546 | + switch (c->regmap[offset]) { | ||
547 | + case REG_YYMMDD: /* RTC Year-Month-Day */ | ||
548 | + s->regs[REG_YYMMDD] = val; | ||
549 | + s->regs[REG_LOSC] |= REG_LOSC_YMD; | ||
550 | + break; | ||
551 | + case REG_HHMMSS: /* RTC Hour-Minute-Second */ | ||
552 | + s->regs[REG_HHMMSS] = val; | ||
553 | + s->regs[REG_LOSC] |= REG_LOSC_HMS; | ||
554 | + break; | ||
555 | + case REG_GP0: /* General Purpose Register 0 */ | ||
556 | + case REG_GP1: /* General Purpose Register 1 */ | ||
557 | + case REG_GP2: /* General Purpose Register 2 */ | ||
558 | + case REG_GP3: /* General Purpose Register 3 */ | ||
559 | + s->regs[c->regmap[offset]] = val; | ||
560 | + break; | ||
561 | + default: | ||
562 | + if (!c->write(s, offset, val)) { | ||
563 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n", | ||
564 | + __func__, (uint32_t)offset); | ||
565 | + } | ||
566 | + break; | ||
567 | + } | ||
568 | +} | ||
569 | + | ||
570 | +static const MemoryRegionOps allwinner_rtc_ops = { | ||
571 | + .read = allwinner_rtc_read, | ||
572 | + .write = allwinner_rtc_write, | ||
573 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
574 | + .valid = { | ||
575 | + .min_access_size = 4, | ||
576 | + .max_access_size = 4, | ||
577 | + }, | ||
578 | + .impl.min_access_size = 4, | ||
579 | +}; | ||
580 | + | ||
581 | +static void allwinner_rtc_reset(DeviceState *dev) | ||
582 | +{ | ||
583 | + AwRtcState *s = AW_RTC(dev); | ||
584 | + struct tm now; | ||
585 | + | ||
586 | + /* Clear registers */ | ||
587 | + memset(s->regs, 0, sizeof(s->regs)); | ||
588 | + | ||
589 | + /* Get current datetime */ | ||
590 | + qemu_get_timedate(&now, 0); | ||
591 | + | ||
592 | + /* Set RTC with current datetime */ | ||
593 | + if (s->base_year > 1900) { | ||
594 | + s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) | | ||
595 | + ((now.tm_mon + 1) << 8) | | ||
596 | + now.tm_mday; | ||
597 | + s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) | | ||
598 | + (now.tm_hour << 16) | | ||
599 | + (now.tm_min << 8) | | ||
600 | + now.tm_sec; | ||
601 | + } | ||
602 | +} | ||
603 | + | ||
604 | +static void allwinner_rtc_init(Object *obj) | ||
605 | +{ | ||
606 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
607 | + AwRtcState *s = AW_RTC(obj); | ||
608 | + | ||
609 | + /* Memory mapping */ | ||
610 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s, | ||
611 | + TYPE_AW_RTC, 1 * KiB); | ||
612 | + sysbus_init_mmio(sbd, &s->iomem); | ||
613 | +} | ||
614 | + | ||
615 | +static const VMStateDescription allwinner_rtc_vmstate = { | ||
616 | + .name = "allwinner-rtc", | ||
617 | + .version_id = 1, | ||
618 | + .minimum_version_id = 1, | ||
619 | + .fields = (VMStateField[]) { | ||
620 | + VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM), | ||
621 | + VMSTATE_END_OF_LIST() | ||
622 | + } | ||
623 | +}; | ||
624 | + | ||
625 | +static Property allwinner_rtc_properties[] = { | ||
626 | + DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0), | ||
627 | + DEFINE_PROP_END_OF_LIST(), | ||
628 | +}; | ||
629 | + | ||
630 | +static void allwinner_rtc_class_init(ObjectClass *klass, void *data) | ||
631 | +{ | ||
632 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
633 | + | ||
634 | + dc->reset = allwinner_rtc_reset; | ||
635 | + dc->vmsd = &allwinner_rtc_vmstate; | ||
636 | + device_class_set_props(dc, allwinner_rtc_properties); | ||
637 | +} | ||
638 | + | ||
639 | +static void allwinner_rtc_sun4i_init(Object *obj) | ||
640 | +{ | ||
641 | + AwRtcState *s = AW_RTC(obj); | ||
642 | + s->base_year = 2010; | ||
643 | +} | ||
644 | + | ||
645 | +static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data) | ||
646 | +{ | ||
647 | + AwRtcClass *arc = AW_RTC_CLASS(klass); | ||
648 | + | ||
649 | + arc->regmap = allwinner_rtc_sun4i_regmap; | ||
650 | + arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap); | ||
651 | + arc->read = allwinner_rtc_sun4i_read; | ||
652 | + arc->write = allwinner_rtc_sun4i_write; | ||
653 | +} | ||
654 | + | ||
655 | +static void allwinner_rtc_sun6i_init(Object *obj) | ||
656 | +{ | ||
657 | + AwRtcState *s = AW_RTC(obj); | ||
658 | + s->base_year = 1970; | ||
659 | +} | ||
660 | + | ||
661 | +static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data) | ||
662 | +{ | ||
663 | + AwRtcClass *arc = AW_RTC_CLASS(klass); | ||
664 | + | ||
665 | + arc->regmap = allwinner_rtc_sun6i_regmap; | ||
666 | + arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap); | ||
667 | + arc->read = allwinner_rtc_sun6i_read; | ||
668 | + arc->write = allwinner_rtc_sun6i_write; | ||
669 | +} | ||
670 | + | ||
671 | +static void allwinner_rtc_sun7i_init(Object *obj) | ||
672 | +{ | ||
673 | + AwRtcState *s = AW_RTC(obj); | ||
674 | + s->base_year = 1970; | ||
675 | +} | ||
676 | + | ||
677 | +static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data) | ||
678 | +{ | ||
679 | + AwRtcClass *arc = AW_RTC_CLASS(klass); | ||
680 | + allwinner_rtc_sun4i_class_init(klass, arc); | ||
681 | +} | ||
682 | + | ||
683 | +static const TypeInfo allwinner_rtc_info = { | ||
684 | + .name = TYPE_AW_RTC, | ||
685 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
686 | + .instance_init = allwinner_rtc_init, | ||
687 | + .instance_size = sizeof(AwRtcState), | ||
688 | + .class_init = allwinner_rtc_class_init, | ||
689 | + .class_size = sizeof(AwRtcClass), | ||
690 | + .abstract = true, | ||
691 | +}; | ||
692 | + | ||
693 | +static const TypeInfo allwinner_rtc_sun4i_info = { | ||
694 | + .name = TYPE_AW_RTC_SUN4I, | ||
695 | + .parent = TYPE_AW_RTC, | ||
696 | + .class_init = allwinner_rtc_sun4i_class_init, | ||
697 | + .instance_init = allwinner_rtc_sun4i_init, | ||
698 | +}; | ||
699 | + | ||
700 | +static const TypeInfo allwinner_rtc_sun6i_info = { | ||
701 | + .name = TYPE_AW_RTC_SUN6I, | ||
702 | + .parent = TYPE_AW_RTC, | ||
703 | + .class_init = allwinner_rtc_sun6i_class_init, | ||
704 | + .instance_init = allwinner_rtc_sun6i_init, | ||
705 | +}; | ||
706 | + | ||
707 | +static const TypeInfo allwinner_rtc_sun7i_info = { | ||
708 | + .name = TYPE_AW_RTC_SUN7I, | ||
709 | + .parent = TYPE_AW_RTC, | ||
710 | + .class_init = allwinner_rtc_sun7i_class_init, | ||
711 | + .instance_init = allwinner_rtc_sun7i_init, | ||
712 | +}; | ||
713 | + | ||
714 | +static void allwinner_rtc_register(void) | ||
715 | +{ | ||
716 | + type_register_static(&allwinner_rtc_info); | ||
717 | + type_register_static(&allwinner_rtc_sun4i_info); | ||
718 | + type_register_static(&allwinner_rtc_sun6i_info); | ||
719 | + type_register_static(&allwinner_rtc_sun7i_info); | ||
720 | +} | ||
721 | + | ||
722 | +type_init(allwinner_rtc_register) | ||
723 | diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events | ||
724 | index XXXXXXX..XXXXXXX 100644 | ||
725 | --- a/hw/rtc/trace-events | ||
726 | +++ b/hw/rtc/trace-events | ||
727 | @@ -XXX,XX +XXX,XX @@ | ||
728 | # See docs/devel/tracing.txt for syntax documentation. | ||
729 | |||
730 | +# allwinner-rtc.c | ||
731 | +allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64 | ||
732 | +allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64 | ||
733 | + | ||
734 | # sun4v-rtc.c | ||
735 | sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64 | ||
736 | sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64 | ||
737 | -- | 87 | -- |
738 | 2.20.1 | 88 | 2.34.1 |
739 | 89 | ||
740 | 90 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert the exception generation instructions SVC, HVC, SMC, BRK and |
---|---|---|---|
2 | HLT to decodetree. | ||
2 | 3 | ||
3 | The Allwinner System on Chip families sun4i and above contain | 4 | The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and |
4 | an integrated storage controller for Secure Digital (SD) and | 5 | DCPS3 just in order to then make them UNDEF; as with DRPS, we don't |
5 | Multi Media Card (MMC) interfaces. This commit adds support | 6 | bother to decode them, but document the patterns in a64.decode. |
6 | for the Allwinner SD/MMC storage controller with the following | ||
7 | emulated features: | ||
8 | 7 | ||
9 | * DMA transfers | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | * Direct FIFO I/O | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | * Short/Long format command responses | 10 | Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org |
12 | * Auto-Stop command (CMD12) | 11 | --- |
13 | * Insert & remove card detection | 12 | target/arm/tcg/a64.decode | 15 +++ |
13 | target/arm/tcg/translate-a64.c | 173 ++++++++++++--------------------- | ||
14 | 2 files changed, 79 insertions(+), 109 deletions(-) | ||
14 | 15 | ||
15 | The following boards are extended with the SD host controller: | 16 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
16 | |||
17 | * Cubieboard (hw/arm/cubieboard.c) | ||
18 | * Orange Pi PC (hw/arm/orangepi.c) | ||
19 | |||
20 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
21 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
22 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
23 | Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com | ||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
25 | --- | ||
26 | hw/sd/Makefile.objs | 1 + | ||
27 | include/hw/arm/allwinner-a10.h | 2 + | ||
28 | include/hw/arm/allwinner-h3.h | 3 + | ||
29 | include/hw/sd/allwinner-sdhost.h | 135 +++++ | ||
30 | hw/arm/allwinner-a10.c | 11 + | ||
31 | hw/arm/allwinner-h3.c | 15 +- | ||
32 | hw/arm/cubieboard.c | 15 + | ||
33 | hw/arm/orangepi.c | 16 + | ||
34 | hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++ | ||
35 | hw/arm/Kconfig | 1 + | ||
36 | hw/sd/trace-events | 7 + | ||
37 | 11 files changed, 1059 insertions(+), 1 deletion(-) | ||
38 | create mode 100644 include/hw/sd/allwinner-sdhost.h | ||
39 | create mode 100644 hw/sd/allwinner-sdhost.c | ||
40 | |||
41 | diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs | ||
42 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/hw/sd/Makefile.objs | 18 | --- a/target/arm/tcg/a64.decode |
44 | +++ b/hw/sd/Makefile.objs | 19 | +++ b/target/arm/tcg/a64.decode |
45 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o | 20 | @@ -XXX,XX +XXX,XX @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 |
46 | common-obj-$(CONFIG_SDHCI) += sdhci.o | 21 | SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 |
47 | common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o | 22 | SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 |
48 | 23 | SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 | |
49 | +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o | 24 | + |
50 | common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o | 25 | +# Exception generation |
51 | common-obj-$(CONFIG_OMAP) += omap_mmc.o | 26 | + |
52 | common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o | 27 | +@i16 .... .... ... imm:16 ... .. &i |
53 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | 28 | +SVC 1101 0100 000 ................ 000 01 @i16 |
29 | +HVC 1101 0100 000 ................ 000 10 @i16 | ||
30 | +SMC 1101 0100 000 ................ 000 11 @i16 | ||
31 | +BRK 1101 0100 001 ................ 000 00 @i16 | ||
32 | +HLT 1101 0100 010 ................ 000 00 @i16 | ||
33 | +# These insns always UNDEF unless in halting debug state, which | ||
34 | +# we don't implement. So we don't need to decode them. The patterns | ||
35 | +# are listed here as documentation. | ||
36 | +# DCPS1 1101 0100 101 ................ 000 01 @i16 | ||
37 | +# DCPS2 1101 0100 101 ................ 000 10 @i16 | ||
38 | +# DCPS3 1101 0100 101 ................ 000 11 @i16 | ||
39 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/include/hw/arm/allwinner-a10.h | 41 | --- a/target/arm/tcg/translate-a64.c |
56 | +++ b/include/hw/arm/allwinner-a10.h | 42 | +++ b/target/arm/tcg/translate-a64.c |
57 | @@ -XXX,XX +XXX,XX @@ | 43 | @@ -XXX,XX +XXX,XX @@ static bool trans_SYS(DisasContext *s, arg_SYS *a) |
58 | #include "hw/timer/allwinner-a10-pit.h" | 44 | return true; |
59 | #include "hw/intc/allwinner-a10-pic.h" | 45 | } |
60 | #include "hw/net/allwinner_emac.h" | 46 | |
61 | +#include "hw/sd/allwinner-sdhost.h" | 47 | -/* Exception generation |
62 | #include "hw/ide/ahci.h" | 48 | - * |
63 | #include "hw/usb/hcd-ohci.h" | 49 | - * 31 24 23 21 20 5 4 2 1 0 |
64 | #include "hw/usb/hcd-ehci.h" | 50 | - * +-----------------+-----+------------------------+-----+----+ |
65 | @@ -XXX,XX +XXX,XX @@ typedef struct AwA10State { | 51 | - * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | |
66 | AwA10PICState intc; | 52 | - * +-----------------------+------------------------+----------+ |
67 | AwEmacState emac; | 53 | - */ |
68 | AllwinnerAHCIState sata; | 54 | -static void disas_exc(DisasContext *s, uint32_t insn) |
69 | + AwSdHostState mmc0; | 55 | +static bool trans_SVC(DisasContext *s, arg_i *a) |
70 | MemoryRegion sram_a; | 56 | { |
71 | EHCISysBusState ehci[AW_A10_NUM_USB]; | 57 | - int opc = extract32(insn, 21, 3); |
72 | OHCISysBusState ohci[AW_A10_NUM_USB]; | 58 | - int op2_ll = extract32(insn, 0, 5); |
73 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 59 | - int imm16 = extract32(insn, 5, 16); |
74 | index XXXXXXX..XXXXXXX 100644 | 60 | - uint32_t syndrome; |
75 | --- a/include/hw/arm/allwinner-h3.h | 61 | - |
76 | +++ b/include/hw/arm/allwinner-h3.h | 62 | - switch (opc) { |
77 | @@ -XXX,XX +XXX,XX @@ | 63 | - case 0: |
78 | #include "hw/misc/allwinner-cpucfg.h" | 64 | - /* For SVC, HVC and SMC we advance the single-step state |
79 | #include "hw/misc/allwinner-h3-sysctrl.h" | 65 | - * machine before taking the exception. This is architecturally |
80 | #include "hw/misc/allwinner-sid.h" | 66 | - * mandated, to ensure that single-stepping a system call |
81 | +#include "hw/sd/allwinner-sdhost.h" | 67 | - * instruction works properly. |
82 | #include "target/arm/cpu.h" | 68 | - */ |
83 | 69 | - switch (op2_ll) { | |
84 | /** | 70 | - case 1: /* SVC */ |
85 | @@ -XXX,XX +XXX,XX @@ enum { | 71 | - syndrome = syn_aa64_svc(imm16); |
86 | AW_H3_SRAM_A2, | 72 | - if (s->fgt_svc) { |
87 | AW_H3_SRAM_C, | 73 | - gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); |
88 | AW_H3_SYSCTRL, | 74 | - break; |
89 | + AW_H3_MMC0, | 75 | - } |
90 | AW_H3_SID, | 76 | - gen_ss_advance(s); |
91 | AW_H3_EHCI0, | 77 | - gen_exception_insn(s, 4, EXCP_SWI, syndrome); |
92 | AW_H3_OHCI0, | 78 | - break; |
93 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | 79 | - case 2: /* HVC */ |
94 | AwCpuCfgState cpucfg; | 80 | - if (s->current_el == 0) { |
95 | AwH3SysCtrlState sysctrl; | 81 | - unallocated_encoding(s); |
96 | AwSidState sid; | 82 | - break; |
97 | + AwSdHostState mmc0; | 83 | - } |
98 | GICState gic; | 84 | - /* The pre HVC helper handles cases when HVC gets trapped |
99 | MemoryRegion sram_a1; | 85 | - * as an undefined insn by runtime configuration. |
100 | MemoryRegion sram_a2; | 86 | - */ |
101 | diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h | 87 | - gen_a64_update_pc(s, 0); |
102 | new file mode 100644 | 88 | - gen_helper_pre_hvc(cpu_env); |
103 | index XXXXXXX..XXXXXXX | 89 | - gen_ss_advance(s); |
104 | --- /dev/null | 90 | - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); |
105 | +++ b/include/hw/sd/allwinner-sdhost.h | 91 | - break; |
106 | @@ -XXX,XX +XXX,XX @@ | 92 | - case 3: /* SMC */ |
107 | +/* | 93 | - if (s->current_el == 0) { |
108 | + * Allwinner (sun4i and above) SD Host Controller emulation | 94 | - unallocated_encoding(s); |
109 | + * | 95 | - break; |
110 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | 96 | - } |
111 | + * | 97 | - gen_a64_update_pc(s, 0); |
112 | + * This program is free software: you can redistribute it and/or modify | 98 | - gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); |
113 | + * it under the terms of the GNU General Public License as published by | 99 | - gen_ss_advance(s); |
114 | + * the Free Software Foundation, either version 2 of the License, or | 100 | - gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); |
115 | + * (at your option) any later version. | 101 | - break; |
116 | + * | 102 | - default: |
117 | + * This program is distributed in the hope that it will be useful, | 103 | - unallocated_encoding(s); |
118 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 104 | - break; |
119 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 105 | - } |
120 | + * GNU General Public License for more details. | 106 | - break; |
121 | + * | 107 | - case 1: |
122 | + * You should have received a copy of the GNU General Public License | 108 | - if (op2_ll != 0) { |
123 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | 109 | - unallocated_encoding(s); |
124 | + */ | 110 | - break; |
125 | + | 111 | - } |
126 | +#ifndef HW_SD_ALLWINNER_SDHOST_H | 112 | - /* BRK */ |
127 | +#define HW_SD_ALLWINNER_SDHOST_H | 113 | - gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); |
128 | + | 114 | - break; |
129 | +#include "qom/object.h" | 115 | - case 2: |
130 | +#include "hw/sysbus.h" | 116 | - if (op2_ll != 0) { |
131 | +#include "hw/sd/sd.h" | 117 | - unallocated_encoding(s); |
132 | + | 118 | - break; |
133 | +/** | 119 | - } |
134 | + * Object model types | 120 | - /* HLT. This has two purposes. |
135 | + * @{ | 121 | - * Architecturally, it is an external halting debug instruction. |
136 | + */ | 122 | - * Since QEMU doesn't implement external debug, we treat this as |
137 | + | 123 | - * it is required for halting debug disabled: it will UNDEF. |
138 | +/** Generic Allwinner SD Host Controller (abstract) */ | 124 | - * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. |
139 | +#define TYPE_AW_SDHOST "allwinner-sdhost" | 125 | - */ |
140 | + | 126 | - if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) { |
141 | +/** Allwinner sun4i family (A10, A12) */ | 127 | - gen_exception_internal_insn(s, EXCP_SEMIHOST); |
142 | +#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i" | 128 | - } else { |
143 | + | 129 | - unallocated_encoding(s); |
144 | +/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */ | 130 | - } |
145 | +#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i" | 131 | - break; |
146 | + | 132 | - case 5: |
147 | +/** @} */ | 133 | - if (op2_ll < 1 || op2_ll > 3) { |
148 | + | 134 | - unallocated_encoding(s); |
149 | +/** | 135 | - break; |
150 | + * Object model macros | 136 | - } |
151 | + * @{ | 137 | - /* DCPS1, DCPS2, DCPS3 */ |
152 | + */ | 138 | - unallocated_encoding(s); |
153 | + | 139 | - break; |
154 | +#define AW_SDHOST(obj) \ | 140 | - default: |
155 | + OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST) | 141 | - unallocated_encoding(s); |
156 | +#define AW_SDHOST_CLASS(klass) \ | 142 | - break; |
157 | + OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST) | 143 | + /* |
158 | +#define AW_SDHOST_GET_CLASS(obj) \ | 144 | + * For SVC, HVC and SMC we advance the single-step state |
159 | + OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST) | 145 | + * machine before taking the exception. This is architecturally |
160 | + | 146 | + * mandated, to ensure that single-stepping a system call |
161 | +/** @} */ | 147 | + * instruction works properly. |
162 | + | ||
163 | +/** | ||
164 | + * Allwinner SD Host Controller object instance state. | ||
165 | + */ | ||
166 | +typedef struct AwSdHostState { | ||
167 | + /*< private >*/ | ||
168 | + SysBusDevice busdev; | ||
169 | + /*< public >*/ | ||
170 | + | ||
171 | + /** Secure Digital (SD) bus, which connects to SD card (if present) */ | ||
172 | + SDBus sdbus; | ||
173 | + | ||
174 | + /** Maps I/O registers in physical memory */ | ||
175 | + MemoryRegion iomem; | ||
176 | + | ||
177 | + /** Interrupt output signal to notify CPU */ | ||
178 | + qemu_irq irq; | ||
179 | + | ||
180 | + /** Number of bytes left in current DMA transfer */ | ||
181 | + uint32_t transfer_cnt; | ||
182 | + | ||
183 | + /** | ||
184 | + * @name Hardware Registers | ||
185 | + * @{ | ||
186 | + */ | 148 | + */ |
187 | + | 149 | + uint32_t syndrome = syn_aa64_svc(a->imm); |
188 | + uint32_t global_ctl; /**< Global Control */ | 150 | + if (s->fgt_svc) { |
189 | + uint32_t clock_ctl; /**< Clock Control */ | 151 | + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); |
190 | + uint32_t timeout; /**< Timeout */ | 152 | + return true; |
191 | + uint32_t bus_width; /**< Bus Width */ | ||
192 | + uint32_t block_size; /**< Block Size */ | ||
193 | + uint32_t byte_count; /**< Byte Count */ | ||
194 | + | ||
195 | + uint32_t command; /**< Command */ | ||
196 | + uint32_t command_arg; /**< Command Argument */ | ||
197 | + uint32_t response[4]; /**< Command Response */ | ||
198 | + | ||
199 | + uint32_t irq_mask; /**< Interrupt Mask */ | ||
200 | + uint32_t irq_status; /**< Raw Interrupt Status */ | ||
201 | + uint32_t status; /**< Status */ | ||
202 | + | ||
203 | + uint32_t fifo_wlevel; /**< FIFO Water Level */ | ||
204 | + uint32_t fifo_func_sel; /**< FIFO Function Select */ | ||
205 | + uint32_t debug_enable; /**< Debug Enable */ | ||
206 | + uint32_t auto12_arg; /**< Auto Command 12 Argument */ | ||
207 | + uint32_t newtiming_set; /**< SD New Timing Set */ | ||
208 | + uint32_t newtiming_debug; /**< SD New Timing Debug */ | ||
209 | + uint32_t hardware_rst; /**< Hardware Reset */ | ||
210 | + uint32_t dmac; /**< Internal DMA Controller Control */ | ||
211 | + uint32_t desc_base; /**< Descriptor List Base Address */ | ||
212 | + uint32_t dmac_status; /**< Internal DMA Controller Status */ | ||
213 | + uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */ | ||
214 | + uint32_t card_threshold; /**< Card Threshold Control */ | ||
215 | + uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */ | ||
216 | + uint32_t response_crc; /**< Response CRC */ | ||
217 | + uint32_t data_crc[8]; /**< Data CRC */ | ||
218 | + uint32_t status_crc; /**< Status CRC */ | ||
219 | + | ||
220 | + /** @} */ | ||
221 | + | ||
222 | +} AwSdHostState; | ||
223 | + | ||
224 | +/** | ||
225 | + * Allwinner SD Host Controller class-level struct. | ||
226 | + * | ||
227 | + * This struct is filled by each sunxi device specific code | ||
228 | + * such that the generic code can use this struct to support | ||
229 | + * all devices. | ||
230 | + */ | ||
231 | +typedef struct AwSdHostClass { | ||
232 | + /*< private >*/ | ||
233 | + SysBusDeviceClass parent_class; | ||
234 | + /*< public >*/ | ||
235 | + | ||
236 | + /** Maximum buffer size in bytes per DMA descriptor */ | ||
237 | + size_t max_desc_size; | ||
238 | + | ||
239 | +} AwSdHostClass; | ||
240 | + | ||
241 | +#endif /* HW_SD_ALLWINNER_SDHOST_H */ | ||
242 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
243 | index XXXXXXX..XXXXXXX 100644 | ||
244 | --- a/hw/arm/allwinner-a10.c | ||
245 | +++ b/hw/arm/allwinner-a10.c | ||
246 | @@ -XXX,XX +XXX,XX @@ | ||
247 | #include "hw/boards.h" | ||
248 | #include "hw/usb/hcd-ohci.h" | ||
249 | |||
250 | +#define AW_A10_MMC0_BASE 0x01c0f000 | ||
251 | #define AW_A10_PIC_REG_BASE 0x01c20400 | ||
252 | #define AW_A10_PIT_REG_BASE 0x01c20c00 | ||
253 | #define AW_A10_UART0_REG_BASE 0x01c28000 | ||
254 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) | ||
255 | sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI); | ||
256 | } | ||
257 | } | 153 | } |
258 | + | 154 | + gen_ss_advance(s); |
259 | + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), | 155 | + gen_exception_insn(s, 4, EXCP_SWI, syndrome); |
260 | + TYPE_AW_SDHOST_SUN4I); | 156 | + return true; |
261 | } | 157 | } |
262 | 158 | ||
263 | static void aw_a10_realize(DeviceState *dev, Error **errp) | 159 | -/* Branches, exception generating and system instructions */ |
264 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 160 | -static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
265 | qdev_get_gpio_in(dev, 64 + i)); | 161 | +static bool trans_HVC(DisasContext *s, arg_i *a) |
266 | } | 162 | { |
163 | - switch (extract32(insn, 25, 7)) { | ||
164 | - case 0x6a: /* Exception generation / System */ | ||
165 | - if (insn & (1 << 24)) { | ||
166 | - unallocated_encoding(s); | ||
167 | - } else { | ||
168 | - disas_exc(s, insn); | ||
169 | - } | ||
170 | - break; | ||
171 | - default: | ||
172 | + if (s->current_el == 0) { | ||
173 | unallocated_encoding(s); | ||
174 | - break; | ||
175 | + return true; | ||
267 | } | 176 | } |
268 | + | 177 | + /* |
269 | + /* SD/MMC */ | 178 | + * The pre HVC helper handles cases when HVC gets trapped |
270 | + qdev_init_nofail(DEVICE(&s->mmc0)); | 179 | + * as an undefined insn by runtime configuration. |
271 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE); | 180 | + */ |
272 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); | 181 | + gen_a64_update_pc(s, 0); |
273 | + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), | 182 | + gen_helper_pre_hvc(cpu_env); |
274 | + "sd-bus", &error_abort); | 183 | + /* Architecture requires ss advance before we do the actual work */ |
275 | } | 184 | + gen_ss_advance(s); |
276 | 185 | + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); | |
277 | static void aw_a10_class_init(ObjectClass *oc, void *data) | 186 | + return true; |
278 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | 187 | +} |
279 | index XXXXXXX..XXXXXXX 100644 | 188 | + |
280 | --- a/hw/arm/allwinner-h3.c | 189 | +static bool trans_SMC(DisasContext *s, arg_i *a) |
281 | +++ b/hw/arm/allwinner-h3.c | ||
282 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
283 | [AW_H3_SRAM_A2] = 0x00044000, | ||
284 | [AW_H3_SRAM_C] = 0x00010000, | ||
285 | [AW_H3_SYSCTRL] = 0x01c00000, | ||
286 | + [AW_H3_MMC0] = 0x01c0f000, | ||
287 | [AW_H3_SID] = 0x01c14000, | ||
288 | [AW_H3_EHCI0] = 0x01c1a000, | ||
289 | [AW_H3_OHCI0] = 0x01c1a400, | ||
290 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
291 | { "lcd0", 0x01c0c000, 4 * KiB }, | ||
292 | { "lcd1", 0x01c0d000, 4 * KiB }, | ||
293 | { "ve", 0x01c0e000, 4 * KiB }, | ||
294 | - { "mmc0", 0x01c0f000, 4 * KiB }, | ||
295 | { "mmc1", 0x01c10000, 4 * KiB }, | ||
296 | { "mmc2", 0x01c11000, 4 * KiB }, | ||
297 | { "crypto", 0x01c15000, 4 * KiB }, | ||
298 | @@ -XXX,XX +XXX,XX @@ enum { | ||
299 | AW_H3_GIC_SPI_UART3 = 3, | ||
300 | AW_H3_GIC_SPI_TIMER0 = 18, | ||
301 | AW_H3_GIC_SPI_TIMER1 = 19, | ||
302 | + AW_H3_GIC_SPI_MMC0 = 60, | ||
303 | AW_H3_GIC_SPI_EHCI0 = 72, | ||
304 | AW_H3_GIC_SPI_OHCI0 = 73, | ||
305 | AW_H3_GIC_SPI_EHCI1 = 74, | ||
306 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
307 | TYPE_AW_SID); | ||
308 | object_property_add_alias(obj, "identifier", OBJECT(&s->sid), | ||
309 | "identifier", &error_abort); | ||
310 | + | ||
311 | + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), | ||
312 | + TYPE_AW_SDHOST_SUN5I); | ||
313 | } | ||
314 | |||
315 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
316 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
317 | qdev_init_nofail(DEVICE(&s->sid)); | ||
318 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); | ||
319 | |||
320 | + /* SD/MMC */ | ||
321 | + qdev_init_nofail(DEVICE(&s->mmc0)); | ||
322 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]); | ||
323 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, | ||
324 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0)); | ||
325 | + | ||
326 | + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), | ||
327 | + "sd-bus", &error_abort); | ||
328 | + | ||
329 | /* Universal Serial Bus */ | ||
330 | sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], | ||
331 | qdev_get_gpio_in(DEVICE(&s->gic), | ||
332 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | ||
333 | index XXXXXXX..XXXXXXX 100644 | ||
334 | --- a/hw/arm/cubieboard.c | ||
335 | +++ b/hw/arm/cubieboard.c | ||
336 | @@ -XXX,XX +XXX,XX @@ | ||
337 | #include "sysemu/sysemu.h" | ||
338 | #include "hw/sysbus.h" | ||
339 | #include "hw/boards.h" | ||
340 | +#include "hw/qdev-properties.h" | ||
341 | #include "hw/arm/allwinner-a10.h" | ||
342 | |||
343 | static struct arm_boot_info cubieboard_binfo = { | ||
344 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | ||
345 | { | ||
346 | AwA10State *a10; | ||
347 | Error *err = NULL; | ||
348 | + DriveInfo *di; | ||
349 | + BlockBackend *blk; | ||
350 | + BusState *bus; | ||
351 | + DeviceState *carddev; | ||
352 | |||
353 | /* BIOS is not supported by this board */ | ||
354 | if (bios_name) { | ||
355 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | ||
356 | exit(1); | ||
357 | } | ||
358 | |||
359 | + /* Retrieve SD bus */ | ||
360 | + di = drive_get_next(IF_SD); | ||
361 | + blk = di ? blk_by_legacy_dinfo(di) : NULL; | ||
362 | + bus = qdev_get_child_bus(DEVICE(a10), "sd-bus"); | ||
363 | + | ||
364 | + /* Plug in SD card */ | ||
365 | + carddev = qdev_create(bus, TYPE_SD_CARD); | ||
366 | + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | ||
367 | + object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); | ||
368 | + | ||
369 | memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE, | ||
370 | machine->ram); | ||
371 | |||
372 | diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c | ||
373 | index XXXXXXX..XXXXXXX 100644 | ||
374 | --- a/hw/arm/orangepi.c | ||
375 | +++ b/hw/arm/orangepi.c | ||
376 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = { | ||
377 | static void orangepi_init(MachineState *machine) | ||
378 | { | ||
379 | AwH3State *h3; | ||
380 | + DriveInfo *di; | ||
381 | + BlockBackend *blk; | ||
382 | + BusState *bus; | ||
383 | + DeviceState *carddev; | ||
384 | |||
385 | /* BIOS is not supported by this board */ | ||
386 | if (bios_name) { | ||
387 | @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) | ||
388 | /* Mark H3 object realized */ | ||
389 | object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); | ||
390 | |||
391 | + /* Retrieve SD bus */ | ||
392 | + di = drive_get_next(IF_SD); | ||
393 | + blk = di ? blk_by_legacy_dinfo(di) : NULL; | ||
394 | + bus = qdev_get_child_bus(DEVICE(h3), "sd-bus"); | ||
395 | + | ||
396 | + /* Plug in SD card */ | ||
397 | + carddev = qdev_create(bus, TYPE_SD_CARD); | ||
398 | + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | ||
399 | + object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); | ||
400 | + | ||
401 | /* SDRAM */ | ||
402 | memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], | ||
403 | machine->ram); | ||
404 | @@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc) | ||
405 | { | ||
406 | mc->desc = "Orange Pi PC"; | ||
407 | mc->init = orangepi_init; | ||
408 | + mc->block_default_type = IF_SD; | ||
409 | + mc->units_per_default_bus = 1; | ||
410 | mc->min_cpus = AW_H3_NUM_CPUS; | ||
411 | mc->max_cpus = AW_H3_NUM_CPUS; | ||
412 | mc->default_cpus = AW_H3_NUM_CPUS; | ||
413 | diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c | ||
414 | new file mode 100644 | ||
415 | index XXXXXXX..XXXXXXX | ||
416 | --- /dev/null | ||
417 | +++ b/hw/sd/allwinner-sdhost.c | ||
418 | @@ -XXX,XX +XXX,XX @@ | ||
419 | +/* | ||
420 | + * Allwinner (sun4i and above) SD Host Controller emulation | ||
421 | + * | ||
422 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
423 | + * | ||
424 | + * This program is free software: you can redistribute it and/or modify | ||
425 | + * it under the terms of the GNU General Public License as published by | ||
426 | + * the Free Software Foundation, either version 2 of the License, or | ||
427 | + * (at your option) any later version. | ||
428 | + * | ||
429 | + * This program is distributed in the hope that it will be useful, | ||
430 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
431 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
432 | + * GNU General Public License for more details. | ||
433 | + * | ||
434 | + * You should have received a copy of the GNU General Public License | ||
435 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
436 | + */ | ||
437 | + | ||
438 | +#include "qemu/osdep.h" | ||
439 | +#include "qemu/log.h" | ||
440 | +#include "qemu/module.h" | ||
441 | +#include "qemu/units.h" | ||
442 | +#include "sysemu/blockdev.h" | ||
443 | +#include "hw/irq.h" | ||
444 | +#include "hw/sd/allwinner-sdhost.h" | ||
445 | +#include "migration/vmstate.h" | ||
446 | +#include "trace.h" | ||
447 | + | ||
448 | +#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus" | ||
449 | +#define AW_SDHOST_BUS(obj) \ | ||
450 | + OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS) | ||
451 | + | ||
452 | +/* SD Host register offsets */ | ||
453 | +enum { | ||
454 | + REG_SD_GCTL = 0x00, /* Global Control */ | ||
455 | + REG_SD_CKCR = 0x04, /* Clock Control */ | ||
456 | + REG_SD_TMOR = 0x08, /* Timeout */ | ||
457 | + REG_SD_BWDR = 0x0C, /* Bus Width */ | ||
458 | + REG_SD_BKSR = 0x10, /* Block Size */ | ||
459 | + REG_SD_BYCR = 0x14, /* Byte Count */ | ||
460 | + REG_SD_CMDR = 0x18, /* Command */ | ||
461 | + REG_SD_CAGR = 0x1C, /* Command Argument */ | ||
462 | + REG_SD_RESP0 = 0x20, /* Response Zero */ | ||
463 | + REG_SD_RESP1 = 0x24, /* Response One */ | ||
464 | + REG_SD_RESP2 = 0x28, /* Response Two */ | ||
465 | + REG_SD_RESP3 = 0x2C, /* Response Three */ | ||
466 | + REG_SD_IMKR = 0x30, /* Interrupt Mask */ | ||
467 | + REG_SD_MISR = 0x34, /* Masked Interrupt Status */ | ||
468 | + REG_SD_RISR = 0x38, /* Raw Interrupt Status */ | ||
469 | + REG_SD_STAR = 0x3C, /* Status */ | ||
470 | + REG_SD_FWLR = 0x40, /* FIFO Water Level */ | ||
471 | + REG_SD_FUNS = 0x44, /* FIFO Function Select */ | ||
472 | + REG_SD_DBGC = 0x50, /* Debug Enable */ | ||
473 | + REG_SD_A12A = 0x58, /* Auto command 12 argument */ | ||
474 | + REG_SD_NTSR = 0x5C, /* SD NewTiming Set */ | ||
475 | + REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */ | ||
476 | + REG_SD_HWRST = 0x78, /* Hardware Reset Register */ | ||
477 | + REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */ | ||
478 | + REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ | ||
479 | + REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ | ||
480 | + REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ | ||
481 | + REG_SD_THLDC = 0x100, /* Card Threshold Control */ | ||
482 | + REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ | ||
483 | + REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ | ||
484 | + REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ | ||
485 | + REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */ | ||
486 | + REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */ | ||
487 | + REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */ | ||
488 | + REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */ | ||
489 | + REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */ | ||
490 | + REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */ | ||
491 | + REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */ | ||
492 | + REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */ | ||
493 | + REG_SD_FIFO = 0x200, /* Read/Write FIFO */ | ||
494 | +}; | ||
495 | + | ||
496 | +/* SD Host register flags */ | ||
497 | +enum { | ||
498 | + SD_GCTL_FIFO_AC_MOD = (1 << 31), | ||
499 | + SD_GCTL_DDR_MOD_SEL = (1 << 10), | ||
500 | + SD_GCTL_CD_DBC_ENB = (1 << 8), | ||
501 | + SD_GCTL_DMA_ENB = (1 << 5), | ||
502 | + SD_GCTL_INT_ENB = (1 << 4), | ||
503 | + SD_GCTL_DMA_RST = (1 << 2), | ||
504 | + SD_GCTL_FIFO_RST = (1 << 1), | ||
505 | + SD_GCTL_SOFT_RST = (1 << 0), | ||
506 | +}; | ||
507 | + | ||
508 | +enum { | ||
509 | + SD_CMDR_LOAD = (1 << 31), | ||
510 | + SD_CMDR_CLKCHANGE = (1 << 21), | ||
511 | + SD_CMDR_WRITE = (1 << 10), | ||
512 | + SD_CMDR_AUTOSTOP = (1 << 12), | ||
513 | + SD_CMDR_DATA = (1 << 9), | ||
514 | + SD_CMDR_RESPONSE_LONG = (1 << 7), | ||
515 | + SD_CMDR_RESPONSE = (1 << 6), | ||
516 | + SD_CMDR_CMDID_MASK = (0x3f), | ||
517 | +}; | ||
518 | + | ||
519 | +enum { | ||
520 | + SD_RISR_CARD_REMOVE = (1 << 31), | ||
521 | + SD_RISR_CARD_INSERT = (1 << 30), | ||
522 | + SD_RISR_SDIO_INTR = (1 << 16), | ||
523 | + SD_RISR_AUTOCMD_DONE = (1 << 14), | ||
524 | + SD_RISR_DATA_COMPLETE = (1 << 3), | ||
525 | + SD_RISR_CMD_COMPLETE = (1 << 2), | ||
526 | + SD_RISR_NO_RESPONSE = (1 << 1), | ||
527 | +}; | ||
528 | + | ||
529 | +enum { | ||
530 | + SD_STAR_CARD_PRESENT = (1 << 8), | ||
531 | +}; | ||
532 | + | ||
533 | +enum { | ||
534 | + SD_IDST_INT_SUMMARY = (1 << 8), | ||
535 | + SD_IDST_RECEIVE_IRQ = (1 << 1), | ||
536 | + SD_IDST_TRANSMIT_IRQ = (1 << 0), | ||
537 | + SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8), | ||
538 | + SD_IDST_WR_MASK = (0x3ff), | ||
539 | +}; | ||
540 | + | ||
541 | +/* SD Host register reset values */ | ||
542 | +enum { | ||
543 | + REG_SD_GCTL_RST = 0x00000300, | ||
544 | + REG_SD_CKCR_RST = 0x0, | ||
545 | + REG_SD_TMOR_RST = 0xFFFFFF40, | ||
546 | + REG_SD_BWDR_RST = 0x0, | ||
547 | + REG_SD_BKSR_RST = 0x00000200, | ||
548 | + REG_SD_BYCR_RST = 0x00000200, | ||
549 | + REG_SD_CMDR_RST = 0x0, | ||
550 | + REG_SD_CAGR_RST = 0x0, | ||
551 | + REG_SD_RESP_RST = 0x0, | ||
552 | + REG_SD_IMKR_RST = 0x0, | ||
553 | + REG_SD_MISR_RST = 0x0, | ||
554 | + REG_SD_RISR_RST = 0x0, | ||
555 | + REG_SD_STAR_RST = 0x00000100, | ||
556 | + REG_SD_FWLR_RST = 0x000F0000, | ||
557 | + REG_SD_FUNS_RST = 0x0, | ||
558 | + REG_SD_DBGC_RST = 0x0, | ||
559 | + REG_SD_A12A_RST = 0x0000FFFF, | ||
560 | + REG_SD_NTSR_RST = 0x00000001, | ||
561 | + REG_SD_SDBG_RST = 0x0, | ||
562 | + REG_SD_HWRST_RST = 0x00000001, | ||
563 | + REG_SD_DMAC_RST = 0x0, | ||
564 | + REG_SD_DLBA_RST = 0x0, | ||
565 | + REG_SD_IDST_RST = 0x0, | ||
566 | + REG_SD_IDIE_RST = 0x0, | ||
567 | + REG_SD_THLDC_RST = 0x0, | ||
568 | + REG_SD_DSBD_RST = 0x0, | ||
569 | + REG_SD_RES_CRC_RST = 0x0, | ||
570 | + REG_SD_DATA_CRC_RST = 0x0, | ||
571 | + REG_SD_CRC_STA_RST = 0x0, | ||
572 | + REG_SD_FIFO_RST = 0x0, | ||
573 | +}; | ||
574 | + | ||
575 | +/* Data transfer descriptor for DMA */ | ||
576 | +typedef struct TransferDescriptor { | ||
577 | + uint32_t status; /* Status flags */ | ||
578 | + uint32_t size; /* Data buffer size */ | ||
579 | + uint32_t addr; /* Data buffer address */ | ||
580 | + uint32_t next; /* Physical address of next descriptor */ | ||
581 | +} TransferDescriptor; | ||
582 | + | ||
583 | +/* Data transfer descriptor flags */ | ||
584 | +enum { | ||
585 | + DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */ | ||
586 | + DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */ | ||
587 | + DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */ | ||
588 | + DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */ | ||
589 | + DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */ | ||
590 | + DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */ | ||
591 | + DESC_SIZE_MASK = (0xfffffffc) | ||
592 | +}; | ||
593 | + | ||
594 | +static void allwinner_sdhost_update_irq(AwSdHostState *s) | ||
595 | +{ | 190 | +{ |
596 | + uint32_t irq; | 191 | + if (s->current_el == 0) { |
597 | + | 192 | + unallocated_encoding(s); |
598 | + if (s->global_ctl & SD_GCTL_INT_ENB) { | 193 | + return true; |
599 | + irq = s->irq_status & s->irq_mask; | ||
600 | + } else { | ||
601 | + irq = 0; | ||
602 | + } | 194 | + } |
603 | + | 195 | + gen_a64_update_pc(s, 0); |
604 | + trace_allwinner_sdhost_update_irq(irq); | 196 | + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm))); |
605 | + qemu_set_irq(s->irq, irq); | 197 | + /* Architecture requires ss advance before we do the actual work */ |
198 | + gen_ss_advance(s); | ||
199 | + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3); | ||
200 | + return true; | ||
606 | +} | 201 | +} |
607 | + | 202 | + |
608 | +static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s, | 203 | +static bool trans_BRK(DisasContext *s, arg_i *a) |
609 | + uint32_t bytes) | ||
610 | +{ | 204 | +{ |
611 | + if (s->transfer_cnt > bytes) { | 205 | + gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm)); |
612 | + s->transfer_cnt -= bytes; | 206 | + return true; |
613 | + } else { | ||
614 | + s->transfer_cnt = 0; | ||
615 | + } | ||
616 | + | ||
617 | + if (!s->transfer_cnt) { | ||
618 | + s->irq_status |= SD_RISR_DATA_COMPLETE; | ||
619 | + } | ||
620 | +} | 207 | +} |
621 | + | 208 | + |
622 | +static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted) | 209 | +static bool trans_HLT(DisasContext *s, arg_i *a) |
623 | +{ | ||
624 | + AwSdHostState *s = AW_SDHOST(dev); | ||
625 | + | ||
626 | + trace_allwinner_sdhost_set_inserted(inserted); | ||
627 | + | ||
628 | + if (inserted) { | ||
629 | + s->irq_status |= SD_RISR_CARD_INSERT; | ||
630 | + s->irq_status &= ~SD_RISR_CARD_REMOVE; | ||
631 | + s->status |= SD_STAR_CARD_PRESENT; | ||
632 | + } else { | ||
633 | + s->irq_status &= ~SD_RISR_CARD_INSERT; | ||
634 | + s->irq_status |= SD_RISR_CARD_REMOVE; | ||
635 | + s->status &= ~SD_STAR_CARD_PRESENT; | ||
636 | + } | ||
637 | + | ||
638 | + allwinner_sdhost_update_irq(s); | ||
639 | +} | ||
640 | + | ||
641 | +static void allwinner_sdhost_send_command(AwSdHostState *s) | ||
642 | +{ | ||
643 | + SDRequest request; | ||
644 | + uint8_t resp[16]; | ||
645 | + int rlen; | ||
646 | + | ||
647 | + /* Auto clear load flag */ | ||
648 | + s->command &= ~SD_CMDR_LOAD; | ||
649 | + | ||
650 | + /* Clock change does not actually interact with the SD bus */ | ||
651 | + if (!(s->command & SD_CMDR_CLKCHANGE)) { | ||
652 | + | ||
653 | + /* Prepare request */ | ||
654 | + request.cmd = s->command & SD_CMDR_CMDID_MASK; | ||
655 | + request.arg = s->command_arg; | ||
656 | + | ||
657 | + /* Send request to SD bus */ | ||
658 | + rlen = sdbus_do_command(&s->sdbus, &request, resp); | ||
659 | + if (rlen < 0) { | ||
660 | + goto error; | ||
661 | + } | ||
662 | + | ||
663 | + /* If the command has a response, store it in the response registers */ | ||
664 | + if ((s->command & SD_CMDR_RESPONSE)) { | ||
665 | + if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) { | ||
666 | + s->response[0] = ldl_be_p(&resp[0]); | ||
667 | + s->response[1] = s->response[2] = s->response[3] = 0; | ||
668 | + | ||
669 | + } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) { | ||
670 | + s->response[0] = ldl_be_p(&resp[12]); | ||
671 | + s->response[1] = ldl_be_p(&resp[8]); | ||
672 | + s->response[2] = ldl_be_p(&resp[4]); | ||
673 | + s->response[3] = ldl_be_p(&resp[0]); | ||
674 | + } else { | ||
675 | + goto error; | ||
676 | + } | ||
677 | + } | ||
678 | + } | ||
679 | + | ||
680 | + /* Set interrupt status bits */ | ||
681 | + s->irq_status |= SD_RISR_CMD_COMPLETE; | ||
682 | + return; | ||
683 | + | ||
684 | +error: | ||
685 | + s->irq_status |= SD_RISR_NO_RESPONSE; | ||
686 | +} | ||
687 | + | ||
688 | +static void allwinner_sdhost_auto_stop(AwSdHostState *s) | ||
689 | +{ | 210 | +{ |
690 | + /* | 211 | + /* |
691 | + * The stop command (CMD12) ensures the SD bus | 212 | + * HLT. This has two purposes. |
692 | + * returns to the transfer state. | 213 | + * Architecturally, it is an external halting debug instruction. |
214 | + * Since QEMU doesn't implement external debug, we treat this as | ||
215 | + * it is required for halting debug disabled: it will UNDEF. | ||
216 | + * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | ||
693 | + */ | 217 | + */ |
694 | + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { | 218 | + if (semihosting_enabled(s->current_el == 0) && a->imm == 0xf000) { |
695 | + /* First save current command registers */ | 219 | + gen_exception_internal_insn(s, EXCP_SEMIHOST); |
696 | + uint32_t saved_cmd = s->command; | 220 | + } else { |
697 | + uint32_t saved_arg = s->command_arg; | 221 | + unallocated_encoding(s); |
698 | + | ||
699 | + /* Prepare stop command (CMD12) */ | ||
700 | + s->command &= ~SD_CMDR_CMDID_MASK; | ||
701 | + s->command |= 12; /* CMD12 */ | ||
702 | + s->command_arg = 0; | ||
703 | + | ||
704 | + /* Put the command on SD bus */ | ||
705 | + allwinner_sdhost_send_command(s); | ||
706 | + | ||
707 | + /* Restore command values */ | ||
708 | + s->command = saved_cmd; | ||
709 | + s->command_arg = saved_arg; | ||
710 | + | ||
711 | + /* Set IRQ status bit for automatic stop done */ | ||
712 | + s->irq_status |= SD_RISR_AUTOCMD_DONE; | ||
713 | + } | 222 | + } |
714 | +} | 223 | + return true; |
715 | + | 224 | } |
716 | +static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, | 225 | |
717 | + hwaddr desc_addr, | 226 | /* |
718 | + TransferDescriptor *desc, | 227 | @@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) |
719 | + bool is_write, uint32_t max_bytes) | 228 | static void disas_a64_legacy(DisasContext *s, uint32_t insn) |
720 | +{ | 229 | { |
721 | + AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s); | 230 | switch (extract32(insn, 25, 4)) { |
722 | + uint32_t num_done = 0; | 231 | - case 0xa: case 0xb: /* Branch, exception generation and system insns */ |
723 | + uint32_t num_bytes = max_bytes; | 232 | - disas_b_exc_sys(s, insn); |
724 | + uint8_t buf[1024]; | 233 | - break; |
725 | + | 234 | case 0x4: |
726 | + /* Read descriptor */ | 235 | case 0x6: |
727 | + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); | 236 | case 0xc: |
728 | + if (desc->size == 0) { | ||
729 | + desc->size = klass->max_desc_size; | ||
730 | + } else if (desc->size > klass->max_desc_size) { | ||
731 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size " | ||
732 | + " is out-of-bounds: %" PRIu32 " > %zu", | ||
733 | + __func__, desc->size, klass->max_desc_size); | ||
734 | + desc->size = klass->max_desc_size; | ||
735 | + } | ||
736 | + if (desc->size < num_bytes) { | ||
737 | + num_bytes = desc->size; | ||
738 | + } | ||
739 | + | ||
740 | + trace_allwinner_sdhost_process_desc(desc_addr, desc->size, | ||
741 | + is_write, max_bytes); | ||
742 | + | ||
743 | + while (num_done < num_bytes) { | ||
744 | + /* Try to completely fill the local buffer */ | ||
745 | + uint32_t buf_bytes = num_bytes - num_done; | ||
746 | + if (buf_bytes > sizeof(buf)) { | ||
747 | + buf_bytes = sizeof(buf); | ||
748 | + } | ||
749 | + | ||
750 | + /* Write to SD bus */ | ||
751 | + if (is_write) { | ||
752 | + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done, | ||
753 | + buf, buf_bytes); | ||
754 | + | ||
755 | + for (uint32_t i = 0; i < buf_bytes; i++) { | ||
756 | + sdbus_write_data(&s->sdbus, buf[i]); | ||
757 | + } | ||
758 | + | ||
759 | + /* Read from SD bus */ | ||
760 | + } else { | ||
761 | + for (uint32_t i = 0; i < buf_bytes; i++) { | ||
762 | + buf[i] = sdbus_read_data(&s->sdbus); | ||
763 | + } | ||
764 | + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done, | ||
765 | + buf, buf_bytes); | ||
766 | + } | ||
767 | + num_done += buf_bytes; | ||
768 | + } | ||
769 | + | ||
770 | + /* Clear hold flag and flush descriptor */ | ||
771 | + desc->status &= ~DESC_STATUS_HOLD; | ||
772 | + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); | ||
773 | + | ||
774 | + return num_done; | ||
775 | +} | ||
776 | + | ||
777 | +static void allwinner_sdhost_dma(AwSdHostState *s) | ||
778 | +{ | ||
779 | + TransferDescriptor desc; | ||
780 | + hwaddr desc_addr = s->desc_base; | ||
781 | + bool is_write = (s->command & SD_CMDR_WRITE); | ||
782 | + uint32_t bytes_done = 0; | ||
783 | + | ||
784 | + /* Check if DMA can be performed */ | ||
785 | + if (s->byte_count == 0 || s->block_size == 0 || | ||
786 | + !(s->global_ctl & SD_GCTL_DMA_ENB)) { | ||
787 | + return; | ||
788 | + } | ||
789 | + | ||
790 | + /* | ||
791 | + * For read operations, data must be available on the SD bus | ||
792 | + * If not, it is an error and we should not act at all | ||
793 | + */ | ||
794 | + if (!is_write && !sdbus_data_ready(&s->sdbus)) { | ||
795 | + return; | ||
796 | + } | ||
797 | + | ||
798 | + /* Process the DMA descriptors until all data is copied */ | ||
799 | + while (s->byte_count > 0) { | ||
800 | + bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc, | ||
801 | + is_write, s->byte_count); | ||
802 | + allwinner_sdhost_update_transfer_cnt(s, bytes_done); | ||
803 | + | ||
804 | + if (bytes_done <= s->byte_count) { | ||
805 | + s->byte_count -= bytes_done; | ||
806 | + } else { | ||
807 | + s->byte_count = 0; | ||
808 | + } | ||
809 | + | ||
810 | + if (desc.status & DESC_STATUS_LAST) { | ||
811 | + break; | ||
812 | + } else { | ||
813 | + desc_addr = desc.next; | ||
814 | + } | ||
815 | + } | ||
816 | + | ||
817 | + /* Raise IRQ to signal DMA is completed */ | ||
818 | + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR; | ||
819 | + | ||
820 | + /* Update DMAC bits */ | ||
821 | + s->dmac_status |= SD_IDST_INT_SUMMARY; | ||
822 | + | ||
823 | + if (is_write) { | ||
824 | + s->dmac_status |= SD_IDST_TRANSMIT_IRQ; | ||
825 | + } else { | ||
826 | + s->dmac_status |= SD_IDST_RECEIVE_IRQ; | ||
827 | + } | ||
828 | +} | ||
829 | + | ||
830 | +static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, | ||
831 | + unsigned size) | ||
832 | +{ | ||
833 | + AwSdHostState *s = AW_SDHOST(opaque); | ||
834 | + uint32_t res = 0; | ||
835 | + | ||
836 | + switch (offset) { | ||
837 | + case REG_SD_GCTL: /* Global Control */ | ||
838 | + res = s->global_ctl; | ||
839 | + break; | ||
840 | + case REG_SD_CKCR: /* Clock Control */ | ||
841 | + res = s->clock_ctl; | ||
842 | + break; | ||
843 | + case REG_SD_TMOR: /* Timeout */ | ||
844 | + res = s->timeout; | ||
845 | + break; | ||
846 | + case REG_SD_BWDR: /* Bus Width */ | ||
847 | + res = s->bus_width; | ||
848 | + break; | ||
849 | + case REG_SD_BKSR: /* Block Size */ | ||
850 | + res = s->block_size; | ||
851 | + break; | ||
852 | + case REG_SD_BYCR: /* Byte Count */ | ||
853 | + res = s->byte_count; | ||
854 | + break; | ||
855 | + case REG_SD_CMDR: /* Command */ | ||
856 | + res = s->command; | ||
857 | + break; | ||
858 | + case REG_SD_CAGR: /* Command Argument */ | ||
859 | + res = s->command_arg; | ||
860 | + break; | ||
861 | + case REG_SD_RESP0: /* Response Zero */ | ||
862 | + res = s->response[0]; | ||
863 | + break; | ||
864 | + case REG_SD_RESP1: /* Response One */ | ||
865 | + res = s->response[1]; | ||
866 | + break; | ||
867 | + case REG_SD_RESP2: /* Response Two */ | ||
868 | + res = s->response[2]; | ||
869 | + break; | ||
870 | + case REG_SD_RESP3: /* Response Three */ | ||
871 | + res = s->response[3]; | ||
872 | + break; | ||
873 | + case REG_SD_IMKR: /* Interrupt Mask */ | ||
874 | + res = s->irq_mask; | ||
875 | + break; | ||
876 | + case REG_SD_MISR: /* Masked Interrupt Status */ | ||
877 | + res = s->irq_status & s->irq_mask; | ||
878 | + break; | ||
879 | + case REG_SD_RISR: /* Raw Interrupt Status */ | ||
880 | + res = s->irq_status; | ||
881 | + break; | ||
882 | + case REG_SD_STAR: /* Status */ | ||
883 | + res = s->status; | ||
884 | + break; | ||
885 | + case REG_SD_FWLR: /* FIFO Water Level */ | ||
886 | + res = s->fifo_wlevel; | ||
887 | + break; | ||
888 | + case REG_SD_FUNS: /* FIFO Function Select */ | ||
889 | + res = s->fifo_func_sel; | ||
890 | + break; | ||
891 | + case REG_SD_DBGC: /* Debug Enable */ | ||
892 | + res = s->debug_enable; | ||
893 | + break; | ||
894 | + case REG_SD_A12A: /* Auto command 12 argument */ | ||
895 | + res = s->auto12_arg; | ||
896 | + break; | ||
897 | + case REG_SD_NTSR: /* SD NewTiming Set */ | ||
898 | + res = s->newtiming_set; | ||
899 | + break; | ||
900 | + case REG_SD_SDBG: /* SD newTiming Set Debug */ | ||
901 | + res = s->newtiming_debug; | ||
902 | + break; | ||
903 | + case REG_SD_HWRST: /* Hardware Reset Register */ | ||
904 | + res = s->hardware_rst; | ||
905 | + break; | ||
906 | + case REG_SD_DMAC: /* Internal DMA Controller Control */ | ||
907 | + res = s->dmac; | ||
908 | + break; | ||
909 | + case REG_SD_DLBA: /* Descriptor List Base Address */ | ||
910 | + res = s->desc_base; | ||
911 | + break; | ||
912 | + case REG_SD_IDST: /* Internal DMA Controller Status */ | ||
913 | + res = s->dmac_status; | ||
914 | + break; | ||
915 | + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ | ||
916 | + res = s->dmac_irq; | ||
917 | + break; | ||
918 | + case REG_SD_THLDC: /* Card Threshold Control */ | ||
919 | + res = s->card_threshold; | ||
920 | + break; | ||
921 | + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ | ||
922 | + res = s->startbit_detect; | ||
923 | + break; | ||
924 | + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ | ||
925 | + res = s->response_crc; | ||
926 | + break; | ||
927 | + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ | ||
928 | + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ | ||
929 | + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ | ||
930 | + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ | ||
931 | + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ | ||
932 | + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ | ||
933 | + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ | ||
934 | + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ | ||
935 | + res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; | ||
936 | + break; | ||
937 | + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ | ||
938 | + res = s->status_crc; | ||
939 | + break; | ||
940 | + case REG_SD_FIFO: /* Read/Write FIFO */ | ||
941 | + if (sdbus_data_ready(&s->sdbus)) { | ||
942 | + res = sdbus_read_data(&s->sdbus); | ||
943 | + res |= sdbus_read_data(&s->sdbus) << 8; | ||
944 | + res |= sdbus_read_data(&s->sdbus) << 16; | ||
945 | + res |= sdbus_read_data(&s->sdbus) << 24; | ||
946 | + allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); | ||
947 | + allwinner_sdhost_auto_stop(s); | ||
948 | + allwinner_sdhost_update_irq(s); | ||
949 | + } else { | ||
950 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", | ||
951 | + __func__); | ||
952 | + } | ||
953 | + break; | ||
954 | + default: | ||
955 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" | ||
956 | + HWADDR_PRIx"\n", __func__, offset); | ||
957 | + res = 0; | ||
958 | + break; | ||
959 | + } | ||
960 | + | ||
961 | + trace_allwinner_sdhost_read(offset, res, size); | ||
962 | + return res; | ||
963 | +} | ||
964 | + | ||
965 | +static void allwinner_sdhost_write(void *opaque, hwaddr offset, | ||
966 | + uint64_t value, unsigned size) | ||
967 | +{ | ||
968 | + AwSdHostState *s = AW_SDHOST(opaque); | ||
969 | + | ||
970 | + trace_allwinner_sdhost_write(offset, value, size); | ||
971 | + | ||
972 | + switch (offset) { | ||
973 | + case REG_SD_GCTL: /* Global Control */ | ||
974 | + s->global_ctl = value; | ||
975 | + s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | | ||
976 | + SD_GCTL_SOFT_RST); | ||
977 | + allwinner_sdhost_update_irq(s); | ||
978 | + break; | ||
979 | + case REG_SD_CKCR: /* Clock Control */ | ||
980 | + s->clock_ctl = value; | ||
981 | + break; | ||
982 | + case REG_SD_TMOR: /* Timeout */ | ||
983 | + s->timeout = value; | ||
984 | + break; | ||
985 | + case REG_SD_BWDR: /* Bus Width */ | ||
986 | + s->bus_width = value; | ||
987 | + break; | ||
988 | + case REG_SD_BKSR: /* Block Size */ | ||
989 | + s->block_size = value; | ||
990 | + break; | ||
991 | + case REG_SD_BYCR: /* Byte Count */ | ||
992 | + s->byte_count = value; | ||
993 | + s->transfer_cnt = value; | ||
994 | + break; | ||
995 | + case REG_SD_CMDR: /* Command */ | ||
996 | + s->command = value; | ||
997 | + if (value & SD_CMDR_LOAD) { | ||
998 | + allwinner_sdhost_send_command(s); | ||
999 | + allwinner_sdhost_dma(s); | ||
1000 | + allwinner_sdhost_auto_stop(s); | ||
1001 | + } | ||
1002 | + allwinner_sdhost_update_irq(s); | ||
1003 | + break; | ||
1004 | + case REG_SD_CAGR: /* Command Argument */ | ||
1005 | + s->command_arg = value; | ||
1006 | + break; | ||
1007 | + case REG_SD_RESP0: /* Response Zero */ | ||
1008 | + s->response[0] = value; | ||
1009 | + break; | ||
1010 | + case REG_SD_RESP1: /* Response One */ | ||
1011 | + s->response[1] = value; | ||
1012 | + break; | ||
1013 | + case REG_SD_RESP2: /* Response Two */ | ||
1014 | + s->response[2] = value; | ||
1015 | + break; | ||
1016 | + case REG_SD_RESP3: /* Response Three */ | ||
1017 | + s->response[3] = value; | ||
1018 | + break; | ||
1019 | + case REG_SD_IMKR: /* Interrupt Mask */ | ||
1020 | + s->irq_mask = value; | ||
1021 | + allwinner_sdhost_update_irq(s); | ||
1022 | + break; | ||
1023 | + case REG_SD_MISR: /* Masked Interrupt Status */ | ||
1024 | + case REG_SD_RISR: /* Raw Interrupt Status */ | ||
1025 | + s->irq_status &= ~value; | ||
1026 | + allwinner_sdhost_update_irq(s); | ||
1027 | + break; | ||
1028 | + case REG_SD_STAR: /* Status */ | ||
1029 | + s->status &= ~value; | ||
1030 | + allwinner_sdhost_update_irq(s); | ||
1031 | + break; | ||
1032 | + case REG_SD_FWLR: /* FIFO Water Level */ | ||
1033 | + s->fifo_wlevel = value; | ||
1034 | + break; | ||
1035 | + case REG_SD_FUNS: /* FIFO Function Select */ | ||
1036 | + s->fifo_func_sel = value; | ||
1037 | + break; | ||
1038 | + case REG_SD_DBGC: /* Debug Enable */ | ||
1039 | + s->debug_enable = value; | ||
1040 | + break; | ||
1041 | + case REG_SD_A12A: /* Auto command 12 argument */ | ||
1042 | + s->auto12_arg = value; | ||
1043 | + break; | ||
1044 | + case REG_SD_NTSR: /* SD NewTiming Set */ | ||
1045 | + s->newtiming_set = value; | ||
1046 | + break; | ||
1047 | + case REG_SD_SDBG: /* SD newTiming Set Debug */ | ||
1048 | + s->newtiming_debug = value; | ||
1049 | + break; | ||
1050 | + case REG_SD_HWRST: /* Hardware Reset Register */ | ||
1051 | + s->hardware_rst = value; | ||
1052 | + break; | ||
1053 | + case REG_SD_DMAC: /* Internal DMA Controller Control */ | ||
1054 | + s->dmac = value; | ||
1055 | + allwinner_sdhost_update_irq(s); | ||
1056 | + break; | ||
1057 | + case REG_SD_DLBA: /* Descriptor List Base Address */ | ||
1058 | + s->desc_base = value; | ||
1059 | + break; | ||
1060 | + case REG_SD_IDST: /* Internal DMA Controller Status */ | ||
1061 | + s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); | ||
1062 | + allwinner_sdhost_update_irq(s); | ||
1063 | + break; | ||
1064 | + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ | ||
1065 | + s->dmac_irq = value; | ||
1066 | + allwinner_sdhost_update_irq(s); | ||
1067 | + break; | ||
1068 | + case REG_SD_THLDC: /* Card Threshold Control */ | ||
1069 | + s->card_threshold = value; | ||
1070 | + break; | ||
1071 | + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ | ||
1072 | + s->startbit_detect = value; | ||
1073 | + break; | ||
1074 | + case REG_SD_FIFO: /* Read/Write FIFO */ | ||
1075 | + sdbus_write_data(&s->sdbus, value & 0xff); | ||
1076 | + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); | ||
1077 | + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); | ||
1078 | + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); | ||
1079 | + allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); | ||
1080 | + allwinner_sdhost_auto_stop(s); | ||
1081 | + allwinner_sdhost_update_irq(s); | ||
1082 | + break; | ||
1083 | + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ | ||
1084 | + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ | ||
1085 | + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ | ||
1086 | + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ | ||
1087 | + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ | ||
1088 | + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ | ||
1089 | + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ | ||
1090 | + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ | ||
1091 | + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ | ||
1092 | + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ | ||
1093 | + break; | ||
1094 | + default: | ||
1095 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" | ||
1096 | + HWADDR_PRIx"\n", __func__, offset); | ||
1097 | + break; | ||
1098 | + } | ||
1099 | +} | ||
1100 | + | ||
1101 | +static const MemoryRegionOps allwinner_sdhost_ops = { | ||
1102 | + .read = allwinner_sdhost_read, | ||
1103 | + .write = allwinner_sdhost_write, | ||
1104 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
1105 | + .valid = { | ||
1106 | + .min_access_size = 4, | ||
1107 | + .max_access_size = 4, | ||
1108 | + }, | ||
1109 | + .impl.min_access_size = 4, | ||
1110 | +}; | ||
1111 | + | ||
1112 | +static const VMStateDescription vmstate_allwinner_sdhost = { | ||
1113 | + .name = "allwinner-sdhost", | ||
1114 | + .version_id = 1, | ||
1115 | + .minimum_version_id = 1, | ||
1116 | + .fields = (VMStateField[]) { | ||
1117 | + VMSTATE_UINT32(global_ctl, AwSdHostState), | ||
1118 | + VMSTATE_UINT32(clock_ctl, AwSdHostState), | ||
1119 | + VMSTATE_UINT32(timeout, AwSdHostState), | ||
1120 | + VMSTATE_UINT32(bus_width, AwSdHostState), | ||
1121 | + VMSTATE_UINT32(block_size, AwSdHostState), | ||
1122 | + VMSTATE_UINT32(byte_count, AwSdHostState), | ||
1123 | + VMSTATE_UINT32(transfer_cnt, AwSdHostState), | ||
1124 | + VMSTATE_UINT32(command, AwSdHostState), | ||
1125 | + VMSTATE_UINT32(command_arg, AwSdHostState), | ||
1126 | + VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4), | ||
1127 | + VMSTATE_UINT32(irq_mask, AwSdHostState), | ||
1128 | + VMSTATE_UINT32(irq_status, AwSdHostState), | ||
1129 | + VMSTATE_UINT32(status, AwSdHostState), | ||
1130 | + VMSTATE_UINT32(fifo_wlevel, AwSdHostState), | ||
1131 | + VMSTATE_UINT32(fifo_func_sel, AwSdHostState), | ||
1132 | + VMSTATE_UINT32(debug_enable, AwSdHostState), | ||
1133 | + VMSTATE_UINT32(auto12_arg, AwSdHostState), | ||
1134 | + VMSTATE_UINT32(newtiming_set, AwSdHostState), | ||
1135 | + VMSTATE_UINT32(newtiming_debug, AwSdHostState), | ||
1136 | + VMSTATE_UINT32(hardware_rst, AwSdHostState), | ||
1137 | + VMSTATE_UINT32(dmac, AwSdHostState), | ||
1138 | + VMSTATE_UINT32(desc_base, AwSdHostState), | ||
1139 | + VMSTATE_UINT32(dmac_status, AwSdHostState), | ||
1140 | + VMSTATE_UINT32(dmac_irq, AwSdHostState), | ||
1141 | + VMSTATE_UINT32(card_threshold, AwSdHostState), | ||
1142 | + VMSTATE_UINT32(startbit_detect, AwSdHostState), | ||
1143 | + VMSTATE_UINT32(response_crc, AwSdHostState), | ||
1144 | + VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8), | ||
1145 | + VMSTATE_UINT32(status_crc, AwSdHostState), | ||
1146 | + VMSTATE_END_OF_LIST() | ||
1147 | + } | ||
1148 | +}; | ||
1149 | + | ||
1150 | +static void allwinner_sdhost_init(Object *obj) | ||
1151 | +{ | ||
1152 | + AwSdHostState *s = AW_SDHOST(obj); | ||
1153 | + | ||
1154 | + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
1155 | + TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); | ||
1156 | + | ||
1157 | + memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s, | ||
1158 | + TYPE_AW_SDHOST, 4 * KiB); | ||
1159 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
1160 | + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); | ||
1161 | +} | ||
1162 | + | ||
1163 | +static void allwinner_sdhost_reset(DeviceState *dev) | ||
1164 | +{ | ||
1165 | + AwSdHostState *s = AW_SDHOST(dev); | ||
1166 | + | ||
1167 | + s->global_ctl = REG_SD_GCTL_RST; | ||
1168 | + s->clock_ctl = REG_SD_CKCR_RST; | ||
1169 | + s->timeout = REG_SD_TMOR_RST; | ||
1170 | + s->bus_width = REG_SD_BWDR_RST; | ||
1171 | + s->block_size = REG_SD_BKSR_RST; | ||
1172 | + s->byte_count = REG_SD_BYCR_RST; | ||
1173 | + s->transfer_cnt = 0; | ||
1174 | + | ||
1175 | + s->command = REG_SD_CMDR_RST; | ||
1176 | + s->command_arg = REG_SD_CAGR_RST; | ||
1177 | + | ||
1178 | + for (int i = 0; i < ARRAY_SIZE(s->response); i++) { | ||
1179 | + s->response[i] = REG_SD_RESP_RST; | ||
1180 | + } | ||
1181 | + | ||
1182 | + s->irq_mask = REG_SD_IMKR_RST; | ||
1183 | + s->irq_status = REG_SD_RISR_RST; | ||
1184 | + s->status = REG_SD_STAR_RST; | ||
1185 | + | ||
1186 | + s->fifo_wlevel = REG_SD_FWLR_RST; | ||
1187 | + s->fifo_func_sel = REG_SD_FUNS_RST; | ||
1188 | + s->debug_enable = REG_SD_DBGC_RST; | ||
1189 | + s->auto12_arg = REG_SD_A12A_RST; | ||
1190 | + s->newtiming_set = REG_SD_NTSR_RST; | ||
1191 | + s->newtiming_debug = REG_SD_SDBG_RST; | ||
1192 | + s->hardware_rst = REG_SD_HWRST_RST; | ||
1193 | + s->dmac = REG_SD_DMAC_RST; | ||
1194 | + s->desc_base = REG_SD_DLBA_RST; | ||
1195 | + s->dmac_status = REG_SD_IDST_RST; | ||
1196 | + s->dmac_irq = REG_SD_IDIE_RST; | ||
1197 | + s->card_threshold = REG_SD_THLDC_RST; | ||
1198 | + s->startbit_detect = REG_SD_DSBD_RST; | ||
1199 | + s->response_crc = REG_SD_RES_CRC_RST; | ||
1200 | + | ||
1201 | + for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) { | ||
1202 | + s->data_crc[i] = REG_SD_DATA_CRC_RST; | ||
1203 | + } | ||
1204 | + | ||
1205 | + s->status_crc = REG_SD_CRC_STA_RST; | ||
1206 | +} | ||
1207 | + | ||
1208 | +static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data) | ||
1209 | +{ | ||
1210 | + SDBusClass *sbc = SD_BUS_CLASS(klass); | ||
1211 | + | ||
1212 | + sbc->set_inserted = allwinner_sdhost_set_inserted; | ||
1213 | +} | ||
1214 | + | ||
1215 | +static void allwinner_sdhost_class_init(ObjectClass *klass, void *data) | ||
1216 | +{ | ||
1217 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1218 | + | ||
1219 | + dc->reset = allwinner_sdhost_reset; | ||
1220 | + dc->vmsd = &vmstate_allwinner_sdhost; | ||
1221 | +} | ||
1222 | + | ||
1223 | +static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data) | ||
1224 | +{ | ||
1225 | + AwSdHostClass *sc = AW_SDHOST_CLASS(klass); | ||
1226 | + sc->max_desc_size = 8 * KiB; | ||
1227 | +} | ||
1228 | + | ||
1229 | +static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) | ||
1230 | +{ | ||
1231 | + AwSdHostClass *sc = AW_SDHOST_CLASS(klass); | ||
1232 | + sc->max_desc_size = 64 * KiB; | ||
1233 | +} | ||
1234 | + | ||
1235 | +static TypeInfo allwinner_sdhost_info = { | ||
1236 | + .name = TYPE_AW_SDHOST, | ||
1237 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
1238 | + .instance_init = allwinner_sdhost_init, | ||
1239 | + .instance_size = sizeof(AwSdHostState), | ||
1240 | + .class_init = allwinner_sdhost_class_init, | ||
1241 | + .class_size = sizeof(AwSdHostClass), | ||
1242 | + .abstract = true, | ||
1243 | +}; | ||
1244 | + | ||
1245 | +static const TypeInfo allwinner_sdhost_sun4i_info = { | ||
1246 | + .name = TYPE_AW_SDHOST_SUN4I, | ||
1247 | + .parent = TYPE_AW_SDHOST, | ||
1248 | + .class_init = allwinner_sdhost_sun4i_class_init, | ||
1249 | +}; | ||
1250 | + | ||
1251 | +static const TypeInfo allwinner_sdhost_sun5i_info = { | ||
1252 | + .name = TYPE_AW_SDHOST_SUN5I, | ||
1253 | + .parent = TYPE_AW_SDHOST, | ||
1254 | + .class_init = allwinner_sdhost_sun5i_class_init, | ||
1255 | +}; | ||
1256 | + | ||
1257 | +static const TypeInfo allwinner_sdhost_bus_info = { | ||
1258 | + .name = TYPE_AW_SDHOST_BUS, | ||
1259 | + .parent = TYPE_SD_BUS, | ||
1260 | + .instance_size = sizeof(SDBus), | ||
1261 | + .class_init = allwinner_sdhost_bus_class_init, | ||
1262 | +}; | ||
1263 | + | ||
1264 | +static void allwinner_sdhost_register_types(void) | ||
1265 | +{ | ||
1266 | + type_register_static(&allwinner_sdhost_info); | ||
1267 | + type_register_static(&allwinner_sdhost_sun4i_info); | ||
1268 | + type_register_static(&allwinner_sdhost_sun5i_info); | ||
1269 | + type_register_static(&allwinner_sdhost_bus_info); | ||
1270 | +} | ||
1271 | + | ||
1272 | +type_init(allwinner_sdhost_register_types) | ||
1273 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
1274 | index XXXXXXX..XXXXXXX 100644 | ||
1275 | --- a/hw/arm/Kconfig | ||
1276 | +++ b/hw/arm/Kconfig | ||
1277 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3 | ||
1278 | select UNIMP | ||
1279 | select USB_OHCI | ||
1280 | select USB_EHCI_SYSBUS | ||
1281 | + select SD | ||
1282 | |||
1283 | config RASPI | ||
1284 | bool | ||
1285 | diff --git a/hw/sd/trace-events b/hw/sd/trace-events | ||
1286 | index XXXXXXX..XXXXXXX 100644 | ||
1287 | --- a/hw/sd/trace-events | ||
1288 | +++ b/hw/sd/trace-events | ||
1289 | @@ -XXX,XX +XXX,XX @@ | ||
1290 | # See docs/devel/tracing.txt for syntax documentation. | ||
1291 | |||
1292 | +# allwinner-sdhost.c | ||
1293 | +allwinner_sdhost_set_inserted(bool inserted) "inserted %u" | ||
1294 | +allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32 | ||
1295 | +allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
1296 | +allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
1297 | +allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32 | ||
1298 | + | ||
1299 | # bcm2835_sdhost.c | ||
1300 | bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
1301 | bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
1302 | -- | 237 | -- |
1303 | 2.20.1 | 238 | 2.34.1 |
1304 | |||
1305 | diff view generated by jsdifflib |
1 | A write to the CONTROL register can change our current EL (by | 1 | Convert the instructions in the load/store exclusive (STXR, |
---|---|---|---|
2 | writing to the nPRIV bit). That means that we can't assume | 2 | STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR, |
3 | that s->current_el is still valid in trans_MSR_v7m() when | 3 | LDAR, LDLAR) to decodetree. |
4 | we try to rebuild the hflags. | 4 | |
5 | 5 | Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding | |
6 | Add a new helper rebuild_hflags_m32_newel() which, like the | 6 | in the legacy decoder where we were not checking that the RES1 bits |
7 | existing rebuild_hflags_a32_newel(), recalculates the current | 7 | in the Rs and Rt2 fields were set. |
8 | EL from scratch, and use it in trans_MSR_v7m(). | 8 | |
9 | 9 | The new function ldst_iss_sf() is equivalent to the existing | |
10 | This fixes an assertion about an hflags mismatch when the | 10 | disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field |
11 | guest changes privilege by writing to CONTROL. | 11 | rather than taking an undecoded two-bit opc field and extracting |
12 | 'ext' from it. Once all the loads and stores have been converted | ||
13 | to decodetree disas_ldst_compute_iss_sf() will be unused and | ||
14 | can be deleted. | ||
12 | 15 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20200303174950.3298-4-peter.maydell@linaro.org | 18 | Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org |
16 | --- | 19 | --- |
17 | target/arm/helper.h | 1 + | 20 | target/arm/tcg/a64.decode | 11 +++ |
18 | target/arm/helper.c | 12 ++++++++++++ | 21 | target/arm/tcg/translate-a64.c | 154 ++++++++++++++++++++------------- |
19 | target/arm/translate.c | 7 +++---- | 22 | 2 files changed, 103 insertions(+), 62 deletions(-) |
20 | 3 files changed, 16 insertions(+), 4 deletions(-) | 23 | |
21 | 24 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode | |
22 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/helper.h | 26 | --- a/target/arm/tcg/a64.decode |
25 | +++ b/target/arm/helper.h | 27 | +++ b/target/arm/tcg/a64.decode |
26 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) | 28 | @@ -XXX,XX +XXX,XX @@ HLT 1101 0100 010 ................ 000 00 @i16 |
27 | DEF_HELPER_2(get_user_reg, i32, env, i32) | 29 | # DCPS1 1101 0100 101 ................ 000 01 @i16 |
28 | DEF_HELPER_3(set_user_reg, void, env, i32, i32) | 30 | # DCPS2 1101 0100 101 ................ 000 10 @i16 |
29 | 31 | # DCPS3 1101 0100 101 ................ 000 11 @i16 | |
30 | +DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) | 32 | + |
31 | DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) | 33 | +# Loads and stores |
32 | DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) | 34 | + |
33 | DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) | 35 | +&stxr rn rt rt2 rs sz lasr |
34 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 36 | +&stlr rn rt sz lasr |
37 | +@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr | ||
38 | +@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr | ||
39 | +STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR | ||
40 | +LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR | ||
41 | +STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR | ||
42 | +LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR | ||
43 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/target/arm/helper.c | 45 | --- a/target/arm/tcg/translate-a64.c |
37 | +++ b/target/arm/helper.c | 46 | +++ b/target/arm/tcg/translate-a64.c |
38 | @@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env) | 47 | @@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) |
39 | env->hflags = rebuild_hflags_internal(env); | 48 | return regsize == 64; |
40 | } | 49 | } |
41 | 50 | ||
42 | +/* | 51 | +static bool ldst_iss_sf(int size, bool sign, bool ext) |
43 | + * If we have triggered a EL state change we can't rely on the | 52 | +{ |
44 | + * translator having passed it to us, we need to recompute. | 53 | + |
45 | + */ | 54 | + if (sign) { |
46 | +void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) | 55 | + /* |
47 | +{ | 56 | + * Signed loads are 64 bit results if we are not going to |
48 | + int el = arm_current_el(env); | 57 | + * do a zero-extend from 32 to 64 after the load. |
49 | + int fp_el = fp_exception_el(env, el); | 58 | + * (For a store, sign and ext are always false.) |
50 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | 59 | + */ |
51 | + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | 60 | + return !ext; |
52 | +} | 61 | + } else { |
53 | + | 62 | + /* Unsigned loads/stores work at the specified size */ |
54 | void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) | 63 | + return size == MO_64; |
55 | { | 64 | + } |
56 | int fp_el = fp_exception_el(env, el); | 65 | +} |
57 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 66 | + |
58 | index XXXXXXX..XXXXXXX 100644 | 67 | +static bool trans_STXR(DisasContext *s, arg_stxr *a) |
59 | --- a/target/arm/translate.c | 68 | +{ |
60 | +++ b/target/arm/translate.c | 69 | + if (a->rn == 31) { |
61 | @@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) | 70 | + gen_check_sp_alignment(s); |
62 | 71 | + } | |
63 | static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) | 72 | + if (a->lasr) { |
64 | { | 73 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
65 | - TCGv_i32 addr, reg, el; | 74 | + } |
66 | + TCGv_i32 addr, reg; | 75 | + gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false); |
67 | 76 | + return true; | |
68 | if (!arm_dc_feature(s, ARM_FEATURE_M)) { | 77 | +} |
69 | return false; | 78 | + |
70 | @@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) | 79 | +static bool trans_LDXR(DisasContext *s, arg_stxr *a) |
71 | gen_helper_v7m_msr(cpu_env, addr, reg); | 80 | +{ |
72 | tcg_temp_free_i32(addr); | 81 | + if (a->rn == 31) { |
73 | tcg_temp_free_i32(reg); | 82 | + gen_check_sp_alignment(s); |
74 | - el = tcg_const_i32(s->current_el); | 83 | + } |
75 | - gen_helper_rebuild_hflags_m32(cpu_env, el); | 84 | + gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, false); |
76 | - tcg_temp_free_i32(el); | 85 | + if (a->lasr) { |
77 | + /* If we wrote to CONTROL, the EL might have changed */ | 86 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); |
78 | + gen_helper_rebuild_hflags_m32_newel(cpu_env); | 87 | + } |
79 | gen_lookup_tb(s); | 88 | + return true; |
80 | return true; | 89 | +} |
90 | + | ||
91 | +static bool trans_STLR(DisasContext *s, arg_stlr *a) | ||
92 | +{ | ||
93 | + TCGv_i64 clean_addr; | ||
94 | + MemOp memop; | ||
95 | + bool iss_sf = ldst_iss_sf(a->sz, false, false); | ||
96 | + | ||
97 | + /* | ||
98 | + * StoreLORelease is the same as Store-Release for QEMU, but | ||
99 | + * needs the feature-test. | ||
100 | + */ | ||
101 | + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { | ||
102 | + return false; | ||
103 | + } | ||
104 | + /* Generate ISS for non-exclusive accesses including LASR. */ | ||
105 | + if (a->rn == 31) { | ||
106 | + gen_check_sp_alignment(s); | ||
107 | + } | ||
108 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
109 | + memop = check_ordered_align(s, a->rn, 0, true, a->sz); | ||
110 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), | ||
111 | + true, a->rn != 31, memop); | ||
112 | + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt, | ||
113 | + iss_sf, a->lasr); | ||
114 | + return true; | ||
115 | +} | ||
116 | + | ||
117 | +static bool trans_LDAR(DisasContext *s, arg_stlr *a) | ||
118 | +{ | ||
119 | + TCGv_i64 clean_addr; | ||
120 | + MemOp memop; | ||
121 | + bool iss_sf = ldst_iss_sf(a->sz, false, false); | ||
122 | + | ||
123 | + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | ||
124 | + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { | ||
125 | + return false; | ||
126 | + } | ||
127 | + /* Generate ISS for non-exclusive accesses including LASR. */ | ||
128 | + if (a->rn == 31) { | ||
129 | + gen_check_sp_alignment(s); | ||
130 | + } | ||
131 | + memop = check_ordered_align(s, a->rn, 0, false, a->sz); | ||
132 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), | ||
133 | + false, a->rn != 31, memop); | ||
134 | + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, memop, false, true, | ||
135 | + a->rt, iss_sf, a->lasr); | ||
136 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
137 | + return true; | ||
138 | +} | ||
139 | + | ||
140 | /* Load/store exclusive | ||
141 | * | ||
142 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | ||
143 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
144 | int is_lasr = extract32(insn, 15, 1); | ||
145 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | ||
146 | int size = extract32(insn, 30, 2); | ||
147 | - TCGv_i64 clean_addr; | ||
148 | - MemOp memop; | ||
149 | |||
150 | switch (o2_L_o1_o0) { | ||
151 | - case 0x0: /* STXR */ | ||
152 | - case 0x1: /* STLXR */ | ||
153 | - if (rn == 31) { | ||
154 | - gen_check_sp_alignment(s); | ||
155 | - } | ||
156 | - if (is_lasr) { | ||
157 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
158 | - } | ||
159 | - gen_store_exclusive(s, rs, rt, rt2, rn, size, false); | ||
160 | - return; | ||
161 | - | ||
162 | - case 0x4: /* LDXR */ | ||
163 | - case 0x5: /* LDAXR */ | ||
164 | - if (rn == 31) { | ||
165 | - gen_check_sp_alignment(s); | ||
166 | - } | ||
167 | - gen_load_exclusive(s, rt, rt2, rn, size, false); | ||
168 | - if (is_lasr) { | ||
169 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
170 | - } | ||
171 | - return; | ||
172 | - | ||
173 | - case 0x8: /* STLLR */ | ||
174 | - if (!dc_isar_feature(aa64_lor, s)) { | ||
175 | - break; | ||
176 | - } | ||
177 | - /* StoreLORelease is the same as Store-Release for QEMU. */ | ||
178 | - /* fall through */ | ||
179 | - case 0x9: /* STLR */ | ||
180 | - /* Generate ISS for non-exclusive accesses including LASR. */ | ||
181 | - if (rn == 31) { | ||
182 | - gen_check_sp_alignment(s); | ||
183 | - } | ||
184 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
185 | - memop = check_ordered_align(s, rn, 0, true, size); | ||
186 | - clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
187 | - true, rn != 31, memop); | ||
188 | - do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, | ||
189 | - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
190 | - return; | ||
191 | - | ||
192 | - case 0xc: /* LDLAR */ | ||
193 | - if (!dc_isar_feature(aa64_lor, s)) { | ||
194 | - break; | ||
195 | - } | ||
196 | - /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | ||
197 | - /* fall through */ | ||
198 | - case 0xd: /* LDAR */ | ||
199 | - /* Generate ISS for non-exclusive accesses including LASR. */ | ||
200 | - if (rn == 31) { | ||
201 | - gen_check_sp_alignment(s); | ||
202 | - } | ||
203 | - memop = check_ordered_align(s, rn, 0, false, size); | ||
204 | - clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), | ||
205 | - false, rn != 31, memop); | ||
206 | - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, | ||
207 | - rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
208 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
209 | - return; | ||
210 | - | ||
211 | case 0x2: case 0x3: /* CASP / STXP */ | ||
212 | if (size & 2) { /* STXP / STLXP */ | ||
213 | if (rn == 31) { | ||
214 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
215 | return; | ||
216 | } | ||
217 | break; | ||
218 | + default: | ||
219 | + /* Handled in decodetree */ | ||
220 | + break; | ||
221 | } | ||
222 | unallocated_encoding(s); | ||
81 | } | 223 | } |
82 | -- | 224 | -- |
83 | 2.20.1 | 225 | 2.34.1 |
84 | |||
85 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP), |
---|---|---|---|
2 | compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and | ||
3 | swap (CAS, CASA, CASAL, CASL) instructions to decodetree. | ||
2 | 4 | ||
3 | The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC) | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | which provides 10M/100M/1000M Ethernet connectivity. This commit | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc), | 7 | Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org |
6 | including emulation for the following functionality: | 8 | --- |
9 | target/arm/tcg/a64.decode | 11 +++ | ||
10 | target/arm/tcg/translate-a64.c | 121 ++++++++++++--------------------- | ||
11 | 2 files changed, 53 insertions(+), 79 deletions(-) | ||
7 | 12 | ||
8 | * DMA transfers | 13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
9 | * MII interface | ||
10 | * Transmit CRC calculation | ||
11 | |||
12 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
13 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
14 | Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/net/Makefile.objs | 1 + | ||
18 | include/hw/arm/allwinner-h3.h | 3 + | ||
19 | include/hw/net/allwinner-sun8i-emac.h | 99 +++ | ||
20 | hw/arm/allwinner-h3.c | 16 +- | ||
21 | hw/arm/orangepi.c | 3 + | ||
22 | hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++ | ||
23 | hw/arm/Kconfig | 1 + | ||
24 | hw/net/Kconfig | 3 + | ||
25 | hw/net/trace-events | 10 + | ||
26 | 9 files changed, 1006 insertions(+), 1 deletion(-) | ||
27 | create mode 100644 include/hw/net/allwinner-sun8i-emac.h | ||
28 | create mode 100644 hw/net/allwinner-sun8i-emac.c | ||
29 | |||
30 | diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs | ||
31 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/net/Makefile.objs | 15 | --- a/target/arm/tcg/a64.decode |
33 | +++ b/hw/net/Makefile.objs | 16 | +++ b/target/arm/tcg/a64.decode |
34 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o | 17 | @@ -XXX,XX +XXX,XX @@ HLT 1101 0100 010 ................ 000 00 @i16 |
35 | common-obj-$(CONFIG_MIPSNET) += mipsnet.o | 18 | &stlr rn rt sz lasr |
36 | common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o | 19 | @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr |
37 | common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o | 20 | @stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr |
38 | +common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o | 21 | +%imm1_30_p2 30:1 !function=plus_2 |
39 | common-obj-$(CONFIG_IMX_FEC) += imx_fec.o | 22 | +@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 |
40 | 23 | STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR | |
41 | common-obj-$(CONFIG_CADENCE) += cadence_gem.o | 24 | LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR |
42 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 25 | STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR |
26 | LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR | ||
27 | + | ||
28 | +STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP | ||
29 | +LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP | ||
30 | + | ||
31 | +# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine | ||
32 | +# acquire/release semantics because QEMU's cmpxchg always has those) | ||
33 | +CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 | ||
34 | +# CAS, CASA, CASAL, CASL | ||
35 | +CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 | ||
36 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/include/hw/arm/allwinner-h3.h | 38 | --- a/target/arm/tcg/translate-a64.c |
45 | +++ b/include/hw/arm/allwinner-h3.h | 39 | +++ b/target/arm/tcg/translate-a64.c |
46 | @@ -XXX,XX +XXX,XX @@ | 40 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDAR(DisasContext *s, arg_stlr *a) |
47 | #include "hw/misc/allwinner-h3-sysctrl.h" | 41 | return true; |
48 | #include "hw/misc/allwinner-sid.h" | ||
49 | #include "hw/sd/allwinner-sdhost.h" | ||
50 | +#include "hw/net/allwinner-sun8i-emac.h" | ||
51 | #include "target/arm/cpu.h" | ||
52 | |||
53 | /** | ||
54 | @@ -XXX,XX +XXX,XX @@ enum { | ||
55 | AW_H3_UART1, | ||
56 | AW_H3_UART2, | ||
57 | AW_H3_UART3, | ||
58 | + AW_H3_EMAC, | ||
59 | AW_H3_GIC_DIST, | ||
60 | AW_H3_GIC_CPU, | ||
61 | AW_H3_GIC_HYP, | ||
62 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
63 | AwH3SysCtrlState sysctrl; | ||
64 | AwSidState sid; | ||
65 | AwSdHostState mmc0; | ||
66 | + AwSun8iEmacState emac; | ||
67 | GICState gic; | ||
68 | MemoryRegion sram_a1; | ||
69 | MemoryRegion sram_a2; | ||
70 | diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h | ||
71 | new file mode 100644 | ||
72 | index XXXXXXX..XXXXXXX | ||
73 | --- /dev/null | ||
74 | +++ b/include/hw/net/allwinner-sun8i-emac.h | ||
75 | @@ -XXX,XX +XXX,XX @@ | ||
76 | +/* | ||
77 | + * Allwinner Sun8i Ethernet MAC emulation | ||
78 | + * | ||
79 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
80 | + * | ||
81 | + * This program is free software: you can redistribute it and/or modify | ||
82 | + * it under the terms of the GNU General Public License as published by | ||
83 | + * the Free Software Foundation, either version 2 of the License, or | ||
84 | + * (at your option) any later version. | ||
85 | + * | ||
86 | + * This program is distributed in the hope that it will be useful, | ||
87 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
88 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
89 | + * GNU General Public License for more details. | ||
90 | + * | ||
91 | + * You should have received a copy of the GNU General Public License | ||
92 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
93 | + */ | ||
94 | + | ||
95 | +#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H | ||
96 | +#define HW_NET_ALLWINNER_SUN8I_EMAC_H | ||
97 | + | ||
98 | +#include "qom/object.h" | ||
99 | +#include "net/net.h" | ||
100 | +#include "hw/sysbus.h" | ||
101 | + | ||
102 | +/** | ||
103 | + * Object model | ||
104 | + * @{ | ||
105 | + */ | ||
106 | + | ||
107 | +#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac" | ||
108 | +#define AW_SUN8I_EMAC(obj) \ | ||
109 | + OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC) | ||
110 | + | ||
111 | +/** @} */ | ||
112 | + | ||
113 | +/** | ||
114 | + * Allwinner Sun8i EMAC object instance state | ||
115 | + */ | ||
116 | +typedef struct AwSun8iEmacState { | ||
117 | + /*< private >*/ | ||
118 | + SysBusDevice parent_obj; | ||
119 | + /*< public >*/ | ||
120 | + | ||
121 | + /** Maps I/O registers in physical memory */ | ||
122 | + MemoryRegion iomem; | ||
123 | + | ||
124 | + /** Interrupt output signal to notify CPU */ | ||
125 | + qemu_irq irq; | ||
126 | + | ||
127 | + /** Generic Network Interface Controller (NIC) for networking API */ | ||
128 | + NICState *nic; | ||
129 | + | ||
130 | + /** Generic Network Interface Controller (NIC) configuration */ | ||
131 | + NICConf conf; | ||
132 | + | ||
133 | + /** | ||
134 | + * @name Media Independent Interface (MII) | ||
135 | + * @{ | ||
136 | + */ | ||
137 | + | ||
138 | + uint8_t mii_phy_addr; /**< PHY address */ | ||
139 | + uint32_t mii_cr; /**< Control */ | ||
140 | + uint32_t mii_st; /**< Status */ | ||
141 | + uint32_t mii_adv; /**< Advertised Abilities */ | ||
142 | + | ||
143 | + /** @} */ | ||
144 | + | ||
145 | + /** | ||
146 | + * @name Hardware Registers | ||
147 | + * @{ | ||
148 | + */ | ||
149 | + | ||
150 | + uint32_t basic_ctl0; /**< Basic Control 0 */ | ||
151 | + uint32_t basic_ctl1; /**< Basic Control 1 */ | ||
152 | + uint32_t int_en; /**< Interrupt Enable */ | ||
153 | + uint32_t int_sta; /**< Interrupt Status */ | ||
154 | + uint32_t frm_flt; /**< Receive Frame Filter */ | ||
155 | + | ||
156 | + uint32_t rx_ctl0; /**< Receive Control 0 */ | ||
157 | + uint32_t rx_ctl1; /**< Receive Control 1 */ | ||
158 | + uint32_t rx_desc_head; /**< Receive Descriptor List Address */ | ||
159 | + uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */ | ||
160 | + | ||
161 | + uint32_t tx_ctl0; /**< Transmit Control 0 */ | ||
162 | + uint32_t tx_ctl1; /**< Transmit Control 1 */ | ||
163 | + uint32_t tx_desc_head; /**< Transmit Descriptor List Address */ | ||
164 | + uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */ | ||
165 | + uint32_t tx_flowctl; /**< Transmit Flow Control */ | ||
166 | + | ||
167 | + uint32_t mii_cmd; /**< Management Interface Command */ | ||
168 | + uint32_t mii_data; /**< Management Interface Data */ | ||
169 | + | ||
170 | + /** @} */ | ||
171 | + | ||
172 | +} AwSun8iEmacState; | ||
173 | + | ||
174 | +#endif /* HW_NET_ALLWINNER_SUN8I_H */ | ||
175 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/hw/arm/allwinner-h3.c | ||
178 | +++ b/hw/arm/allwinner-h3.c | ||
179 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
180 | [AW_H3_UART1] = 0x01c28400, | ||
181 | [AW_H3_UART2] = 0x01c28800, | ||
182 | [AW_H3_UART3] = 0x01c28c00, | ||
183 | + [AW_H3_EMAC] = 0x01c30000, | ||
184 | [AW_H3_GIC_DIST] = 0x01c81000, | ||
185 | [AW_H3_GIC_CPU] = 0x01c82000, | ||
186 | [AW_H3_GIC_HYP] = 0x01c84000, | ||
187 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
188 | { "twi1", 0x01c2b000, 1 * KiB }, | ||
189 | { "twi2", 0x01c2b400, 1 * KiB }, | ||
190 | { "scr", 0x01c2c400, 1 * KiB }, | ||
191 | - { "emac", 0x01c30000, 64 * KiB }, | ||
192 | { "gpu", 0x01c40000, 64 * KiB }, | ||
193 | { "hstmr", 0x01c60000, 4 * KiB }, | ||
194 | { "dramcom", 0x01c62000, 4 * KiB }, | ||
195 | @@ -XXX,XX +XXX,XX @@ enum { | ||
196 | AW_H3_GIC_SPI_OHCI2 = 77, | ||
197 | AW_H3_GIC_SPI_EHCI3 = 78, | ||
198 | AW_H3_GIC_SPI_OHCI3 = 79, | ||
199 | + AW_H3_GIC_SPI_EMAC = 82 | ||
200 | }; | ||
201 | |||
202 | /* Allwinner H3 general constants */ | ||
203 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
204 | |||
205 | sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), | ||
206 | TYPE_AW_SDHOST_SUN5I); | ||
207 | + | ||
208 | + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), | ||
209 | + TYPE_AW_SUN8I_EMAC); | ||
210 | } | 42 | } |
211 | 43 | ||
212 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 44 | -/* Load/store exclusive |
213 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 45 | - * |
214 | object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), | 46 | - * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 |
215 | "sd-bus", &error_abort); | 47 | - * +-----+-------------+----+---+----+------+----+-------+------+------+ |
216 | 48 | - * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
217 | + /* EMAC */ | 49 | - * +-----+-------------+----+---+----+------+----+-------+------+------+ |
218 | + if (nd_table[0].used) { | 50 | - * |
219 | + qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC); | 51 | - * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit |
220 | + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); | 52 | - * L: 0 -> store, 1 -> load |
53 | - * o2: 0 -> exclusive, 1 -> not | ||
54 | - * o1: 0 -> single register, 1 -> register pair | ||
55 | - * o0: 1 -> load-acquire/store-release, 0 -> not | ||
56 | - */ | ||
57 | -static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
58 | +static bool trans_STXP(DisasContext *s, arg_stxr *a) | ||
59 | { | ||
60 | - int rt = extract32(insn, 0, 5); | ||
61 | - int rn = extract32(insn, 5, 5); | ||
62 | - int rt2 = extract32(insn, 10, 5); | ||
63 | - int rs = extract32(insn, 16, 5); | ||
64 | - int is_lasr = extract32(insn, 15, 1); | ||
65 | - int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | ||
66 | - int size = extract32(insn, 30, 2); | ||
67 | - | ||
68 | - switch (o2_L_o1_o0) { | ||
69 | - case 0x2: case 0x3: /* CASP / STXP */ | ||
70 | - if (size & 2) { /* STXP / STLXP */ | ||
71 | - if (rn == 31) { | ||
72 | - gen_check_sp_alignment(s); | ||
73 | - } | ||
74 | - if (is_lasr) { | ||
75 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
76 | - } | ||
77 | - gen_store_exclusive(s, rs, rt, rt2, rn, size, true); | ||
78 | - return; | ||
79 | - } | ||
80 | - if (rt2 == 31 | ||
81 | - && ((rt | rs) & 1) == 0 | ||
82 | - && dc_isar_feature(aa64_atomics, s)) { | ||
83 | - /* CASP / CASPL */ | ||
84 | - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | ||
85 | - return; | ||
86 | - } | ||
87 | - break; | ||
88 | - | ||
89 | - case 0x6: case 0x7: /* CASPA / LDXP */ | ||
90 | - if (size & 2) { /* LDXP / LDAXP */ | ||
91 | - if (rn == 31) { | ||
92 | - gen_check_sp_alignment(s); | ||
93 | - } | ||
94 | - gen_load_exclusive(s, rt, rt2, rn, size, true); | ||
95 | - if (is_lasr) { | ||
96 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
97 | - } | ||
98 | - return; | ||
99 | - } | ||
100 | - if (rt2 == 31 | ||
101 | - && ((rt | rs) & 1) == 0 | ||
102 | - && dc_isar_feature(aa64_atomics, s)) { | ||
103 | - /* CASPA / CASPAL */ | ||
104 | - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | ||
105 | - return; | ||
106 | - } | ||
107 | - break; | ||
108 | - | ||
109 | - case 0xa: /* CAS */ | ||
110 | - case 0xb: /* CASL */ | ||
111 | - case 0xe: /* CASA */ | ||
112 | - case 0xf: /* CASAL */ | ||
113 | - if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) { | ||
114 | - gen_compare_and_swap(s, rs, rt, rn, size); | ||
115 | - return; | ||
116 | - } | ||
117 | - break; | ||
118 | - default: | ||
119 | - /* Handled in decodetree */ | ||
120 | - break; | ||
121 | + if (a->rn == 31) { | ||
122 | + gen_check_sp_alignment(s); | ||
123 | } | ||
124 | - unallocated_encoding(s); | ||
125 | + if (a->lasr) { | ||
126 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
221 | + } | 127 | + } |
222 | + qdev_init_nofail(DEVICE(&s->emac)); | 128 | + gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, true); |
223 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]); | 129 | + return true; |
224 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, | ||
225 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC)); | ||
226 | + | ||
227 | /* Universal Serial Bus */ | ||
228 | sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], | ||
229 | qdev_get_gpio_in(DEVICE(&s->gic), | ||
230 | diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c | ||
231 | index XXXXXXX..XXXXXXX 100644 | ||
232 | --- a/hw/arm/orangepi.c | ||
233 | +++ b/hw/arm/orangepi.c | ||
234 | @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) | ||
235 | warn_report("Security Identifier value does not include H3 prefix"); | ||
236 | } | ||
237 | |||
238 | + /* Setup EMAC properties */ | ||
239 | + object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort); | ||
240 | + | ||
241 | /* Mark H3 object realized */ | ||
242 | object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); | ||
243 | |||
244 | diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c | ||
245 | new file mode 100644 | ||
246 | index XXXXXXX..XXXXXXX | ||
247 | --- /dev/null | ||
248 | +++ b/hw/net/allwinner-sun8i-emac.c | ||
249 | @@ -XXX,XX +XXX,XX @@ | ||
250 | +/* | ||
251 | + * Allwinner Sun8i Ethernet MAC emulation | ||
252 | + * | ||
253 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
254 | + * | ||
255 | + * This program is free software: you can redistribute it and/or modify | ||
256 | + * it under the terms of the GNU General Public License as published by | ||
257 | + * the Free Software Foundation, either version 2 of the License, or | ||
258 | + * (at your option) any later version. | ||
259 | + * | ||
260 | + * This program is distributed in the hope that it will be useful, | ||
261 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
262 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
263 | + * GNU General Public License for more details. | ||
264 | + * | ||
265 | + * You should have received a copy of the GNU General Public License | ||
266 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
267 | + */ | ||
268 | + | ||
269 | +#include "qemu/osdep.h" | ||
270 | +#include "qemu/units.h" | ||
271 | +#include "hw/sysbus.h" | ||
272 | +#include "migration/vmstate.h" | ||
273 | +#include "net/net.h" | ||
274 | +#include "hw/irq.h" | ||
275 | +#include "hw/qdev-properties.h" | ||
276 | +#include "qemu/log.h" | ||
277 | +#include "trace.h" | ||
278 | +#include "net/checksum.h" | ||
279 | +#include "qemu/module.h" | ||
280 | +#include "exec/cpu-common.h" | ||
281 | +#include "hw/net/allwinner-sun8i-emac.h" | ||
282 | + | ||
283 | +/* EMAC register offsets */ | ||
284 | +enum { | ||
285 | + REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */ | ||
286 | + REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */ | ||
287 | + REG_INT_STA = 0x0008, /* Interrupt Status */ | ||
288 | + REG_INT_EN = 0x000C, /* Interrupt Enable */ | ||
289 | + REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */ | ||
290 | + REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */ | ||
291 | + REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */ | ||
292 | + REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */ | ||
293 | + REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */ | ||
294 | + REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */ | ||
295 | + REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */ | ||
296 | + REG_FRM_FLT = 0x0038, /* Receive Frame Filter */ | ||
297 | + REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */ | ||
298 | + REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */ | ||
299 | + REG_MII_CMD = 0x0048, /* Management Interface Command */ | ||
300 | + REG_MII_DATA = 0x004C, /* Management Interface Data */ | ||
301 | + REG_ADDR_HIGH = 0x0050, /* MAC Address High */ | ||
302 | + REG_ADDR_LOW = 0x0054, /* MAC Address Low */ | ||
303 | + REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */ | ||
304 | + REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */ | ||
305 | + REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */ | ||
306 | + REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */ | ||
307 | + REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */ | ||
308 | + REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */ | ||
309 | + REG_RGMII_STA = 0x00D0, /* RGMII Status */ | ||
310 | +}; | ||
311 | + | ||
312 | +/* EMAC register flags */ | ||
313 | +enum { | ||
314 | + BASIC_CTL0_100Mbps = (0b11 << 2), | ||
315 | + BASIC_CTL0_FD = (1 << 0), | ||
316 | + BASIC_CTL1_SOFTRST = (1 << 0), | ||
317 | +}; | ||
318 | + | ||
319 | +enum { | ||
320 | + INT_STA_RGMII_LINK = (1 << 16), | ||
321 | + INT_STA_RX_EARLY = (1 << 13), | ||
322 | + INT_STA_RX_OVERFLOW = (1 << 12), | ||
323 | + INT_STA_RX_TIMEOUT = (1 << 11), | ||
324 | + INT_STA_RX_DMA_STOP = (1 << 10), | ||
325 | + INT_STA_RX_BUF_UA = (1 << 9), | ||
326 | + INT_STA_RX = (1 << 8), | ||
327 | + INT_STA_TX_EARLY = (1 << 5), | ||
328 | + INT_STA_TX_UNDERFLOW = (1 << 4), | ||
329 | + INT_STA_TX_TIMEOUT = (1 << 3), | ||
330 | + INT_STA_TX_BUF_UA = (1 << 2), | ||
331 | + INT_STA_TX_DMA_STOP = (1 << 1), | ||
332 | + INT_STA_TX = (1 << 0), | ||
333 | +}; | ||
334 | + | ||
335 | +enum { | ||
336 | + INT_EN_RX_EARLY = (1 << 13), | ||
337 | + INT_EN_RX_OVERFLOW = (1 << 12), | ||
338 | + INT_EN_RX_TIMEOUT = (1 << 11), | ||
339 | + INT_EN_RX_DMA_STOP = (1 << 10), | ||
340 | + INT_EN_RX_BUF_UA = (1 << 9), | ||
341 | + INT_EN_RX = (1 << 8), | ||
342 | + INT_EN_TX_EARLY = (1 << 5), | ||
343 | + INT_EN_TX_UNDERFLOW = (1 << 4), | ||
344 | + INT_EN_TX_TIMEOUT = (1 << 3), | ||
345 | + INT_EN_TX_BUF_UA = (1 << 2), | ||
346 | + INT_EN_TX_DMA_STOP = (1 << 1), | ||
347 | + INT_EN_TX = (1 << 0), | ||
348 | +}; | ||
349 | + | ||
350 | +enum { | ||
351 | + TX_CTL0_TX_EN = (1 << 31), | ||
352 | + TX_CTL1_TX_DMA_START = (1 << 31), | ||
353 | + TX_CTL1_TX_DMA_EN = (1 << 30), | ||
354 | + TX_CTL1_TX_FLUSH = (1 << 0), | ||
355 | +}; | ||
356 | + | ||
357 | +enum { | ||
358 | + RX_CTL0_RX_EN = (1 << 31), | ||
359 | + RX_CTL0_STRIP_FCS = (1 << 28), | ||
360 | + RX_CTL0_CRC_IPV4 = (1 << 27), | ||
361 | +}; | ||
362 | + | ||
363 | +enum { | ||
364 | + RX_CTL1_RX_DMA_START = (1 << 31), | ||
365 | + RX_CTL1_RX_DMA_EN = (1 << 30), | ||
366 | + RX_CTL1_RX_MD = (1 << 1), | ||
367 | +}; | ||
368 | + | ||
369 | +enum { | ||
370 | + RX_FRM_FLT_DIS_ADDR = (1 << 31), | ||
371 | +}; | ||
372 | + | ||
373 | +enum { | ||
374 | + MII_CMD_PHY_ADDR_SHIFT = (12), | ||
375 | + MII_CMD_PHY_ADDR_MASK = (0xf000), | ||
376 | + MII_CMD_PHY_REG_SHIFT = (4), | ||
377 | + MII_CMD_PHY_REG_MASK = (0xf0), | ||
378 | + MII_CMD_PHY_RW = (1 << 1), | ||
379 | + MII_CMD_PHY_BUSY = (1 << 0), | ||
380 | +}; | ||
381 | + | ||
382 | +enum { | ||
383 | + TX_DMA_STA_STOP = (0b000), | ||
384 | + TX_DMA_STA_RUN_FETCH = (0b001), | ||
385 | + TX_DMA_STA_WAIT_STA = (0b010), | ||
386 | +}; | ||
387 | + | ||
388 | +enum { | ||
389 | + RX_DMA_STA_STOP = (0b000), | ||
390 | + RX_DMA_STA_RUN_FETCH = (0b001), | ||
391 | + RX_DMA_STA_WAIT_FRM = (0b011), | ||
392 | +}; | ||
393 | + | ||
394 | +/* EMAC register reset values */ | ||
395 | +enum { | ||
396 | + REG_BASIC_CTL_1_RST = 0x08000000, | ||
397 | +}; | ||
398 | + | ||
399 | +/* EMAC constants */ | ||
400 | +enum { | ||
401 | + AW_SUN8I_EMAC_MIN_PKT_SZ = 64 | ||
402 | +}; | ||
403 | + | ||
404 | +/* Transmit/receive frame descriptor */ | ||
405 | +typedef struct FrameDescriptor { | ||
406 | + uint32_t status; | ||
407 | + uint32_t status2; | ||
408 | + uint32_t addr; | ||
409 | + uint32_t next; | ||
410 | +} FrameDescriptor; | ||
411 | + | ||
412 | +/* Frame descriptor flags */ | ||
413 | +enum { | ||
414 | + DESC_STATUS_CTL = (1 << 31), | ||
415 | + DESC_STATUS2_BUF_SIZE_MASK = (0x7ff), | ||
416 | +}; | ||
417 | + | ||
418 | +/* Transmit frame descriptor flags */ | ||
419 | +enum { | ||
420 | + TX_DESC_STATUS_LENGTH_ERR = (1 << 14), | ||
421 | + TX_DESC_STATUS2_FIRST_DESC = (1 << 29), | ||
422 | + TX_DESC_STATUS2_LAST_DESC = (1 << 30), | ||
423 | + TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27), | ||
424 | +}; | ||
425 | + | ||
426 | +/* Receive frame descriptor flags */ | ||
427 | +enum { | ||
428 | + RX_DESC_STATUS_FIRST_DESC = (1 << 9), | ||
429 | + RX_DESC_STATUS_LAST_DESC = (1 << 8), | ||
430 | + RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000), | ||
431 | + RX_DESC_STATUS_FRM_LEN_SHIFT = (16), | ||
432 | + RX_DESC_STATUS_NO_BUF = (1 << 14), | ||
433 | + RX_DESC_STATUS_HEADER_ERR = (1 << 7), | ||
434 | + RX_DESC_STATUS_LENGTH_ERR = (1 << 4), | ||
435 | + RX_DESC_STATUS_CRC_ERR = (1 << 1), | ||
436 | + RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0), | ||
437 | + RX_DESC_STATUS2_RX_INT_CTL = (1 << 31), | ||
438 | +}; | ||
439 | + | ||
440 | +/* MII register offsets */ | ||
441 | +enum { | ||
442 | + MII_REG_CR = (0x0), /* Control */ | ||
443 | + MII_REG_ST = (0x1), /* Status */ | ||
444 | + MII_REG_ID_HIGH = (0x2), /* Identifier High */ | ||
445 | + MII_REG_ID_LOW = (0x3), /* Identifier Low */ | ||
446 | + MII_REG_ADV = (0x4), /* Advertised abilities */ | ||
447 | + MII_REG_LPA = (0x5), /* Link partner abilities */ | ||
448 | +}; | ||
449 | + | ||
450 | +/* MII register flags */ | ||
451 | +enum { | ||
452 | + MII_REG_CR_RESET = (1 << 15), | ||
453 | + MII_REG_CR_POWERDOWN = (1 << 11), | ||
454 | + MII_REG_CR_10Mbit = (0), | ||
455 | + MII_REG_CR_100Mbit = (1 << 13), | ||
456 | + MII_REG_CR_1000Mbit = (1 << 6), | ||
457 | + MII_REG_CR_AUTO_NEG = (1 << 12), | ||
458 | + MII_REG_CR_AUTO_NEG_RESTART = (1 << 9), | ||
459 | + MII_REG_CR_FULLDUPLEX = (1 << 8), | ||
460 | +}; | ||
461 | + | ||
462 | +enum { | ||
463 | + MII_REG_ST_100BASE_T4 = (1 << 15), | ||
464 | + MII_REG_ST_100BASE_X_FD = (1 << 14), | ||
465 | + MII_REG_ST_100BASE_X_HD = (1 << 13), | ||
466 | + MII_REG_ST_10_FD = (1 << 12), | ||
467 | + MII_REG_ST_10_HD = (1 << 11), | ||
468 | + MII_REG_ST_100BASE_T2_FD = (1 << 10), | ||
469 | + MII_REG_ST_100BASE_T2_HD = (1 << 9), | ||
470 | + MII_REG_ST_AUTONEG_COMPLETE = (1 << 5), | ||
471 | + MII_REG_ST_AUTONEG_AVAIL = (1 << 3), | ||
472 | + MII_REG_ST_LINK_UP = (1 << 2), | ||
473 | +}; | ||
474 | + | ||
475 | +enum { | ||
476 | + MII_REG_LPA_10_HD = (1 << 5), | ||
477 | + MII_REG_LPA_10_FD = (1 << 6), | ||
478 | + MII_REG_LPA_100_HD = (1 << 7), | ||
479 | + MII_REG_LPA_100_FD = (1 << 8), | ||
480 | + MII_REG_LPA_PAUSE = (1 << 10), | ||
481 | + MII_REG_LPA_ASYMPAUSE = (1 << 11), | ||
482 | +}; | ||
483 | + | ||
484 | +/* MII constants */ | ||
485 | +enum { | ||
486 | + MII_PHY_ID_HIGH = 0x0044, | ||
487 | + MII_PHY_ID_LOW = 0x1400, | ||
488 | +}; | ||
489 | + | ||
490 | +static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s, | ||
491 | + bool link_active) | ||
492 | +{ | ||
493 | + if (link_active) { | ||
494 | + s->mii_st |= MII_REG_ST_LINK_UP; | ||
495 | + } else { | ||
496 | + s->mii_st &= ~MII_REG_ST_LINK_UP; | ||
497 | + } | ||
498 | +} | 130 | +} |
499 | + | 131 | + |
500 | +static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s, | 132 | +static bool trans_LDXP(DisasContext *s, arg_stxr *a) |
501 | + bool link_active) | ||
502 | +{ | 133 | +{ |
503 | + s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | | 134 | + if (a->rn == 31) { |
504 | + MII_REG_CR_FULLDUPLEX; | 135 | + gen_check_sp_alignment(s); |
505 | + s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | | 136 | + } |
506 | + MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD | | 137 | + gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, true); |
507 | + MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | | 138 | + if (a->lasr) { |
508 | + MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL; | 139 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); |
509 | + s->mii_adv = 0; | 140 | + } |
510 | + | 141 | + return true; |
511 | + allwinner_sun8i_emac_mii_set_link(s, link_active); | ||
512 | +} | 142 | +} |
513 | + | 143 | + |
514 | +static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s) | 144 | +static bool trans_CASP(DisasContext *s, arg_CASP *a) |
515 | +{ | 145 | +{ |
516 | + uint8_t addr, reg; | 146 | + if (!dc_isar_feature(aa64_atomics, s)) { |
517 | + | 147 | + return false; |
518 | + addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT; | 148 | + } |
519 | + reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT; | 149 | + if (((a->rt | a->rs) & 1) != 0) { |
520 | + | 150 | + return false; |
521 | + if (addr != s->mii_phy_addr) { | ||
522 | + return; | ||
523 | + } | 151 | + } |
524 | + | 152 | + |
525 | + /* Read or write a PHY register? */ | 153 | + gen_compare_and_swap_pair(s, a->rs, a->rt, a->rn, a->sz); |
526 | + if (s->mii_cmd & MII_CMD_PHY_RW) { | 154 | + return true; |
527 | + trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data); | ||
528 | + | ||
529 | + switch (reg) { | ||
530 | + case MII_REG_CR: | ||
531 | + if (s->mii_data & MII_REG_CR_RESET) { | ||
532 | + allwinner_sun8i_emac_mii_reset(s, s->mii_st & | ||
533 | + MII_REG_ST_LINK_UP); | ||
534 | + } else { | ||
535 | + s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET | | ||
536 | + MII_REG_CR_AUTO_NEG_RESTART); | ||
537 | + } | ||
538 | + break; | ||
539 | + case MII_REG_ADV: | ||
540 | + s->mii_adv = s->mii_data; | ||
541 | + break; | ||
542 | + case MII_REG_ID_HIGH: | ||
543 | + case MII_REG_ID_LOW: | ||
544 | + case MII_REG_LPA: | ||
545 | + break; | ||
546 | + default: | ||
547 | + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to " | ||
548 | + "unknown MII register 0x%x\n", reg); | ||
549 | + break; | ||
550 | + } | ||
551 | + } else { | ||
552 | + switch (reg) { | ||
553 | + case MII_REG_CR: | ||
554 | + s->mii_data = s->mii_cr; | ||
555 | + break; | ||
556 | + case MII_REG_ST: | ||
557 | + s->mii_data = s->mii_st; | ||
558 | + break; | ||
559 | + case MII_REG_ID_HIGH: | ||
560 | + s->mii_data = MII_PHY_ID_HIGH; | ||
561 | + break; | ||
562 | + case MII_REG_ID_LOW: | ||
563 | + s->mii_data = MII_PHY_ID_LOW; | ||
564 | + break; | ||
565 | + case MII_REG_ADV: | ||
566 | + s->mii_data = s->mii_adv; | ||
567 | + break; | ||
568 | + case MII_REG_LPA: | ||
569 | + s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD | | ||
570 | + MII_REG_LPA_100_HD | MII_REG_LPA_100_FD | | ||
571 | + MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE; | ||
572 | + break; | ||
573 | + default: | ||
574 | + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to " | ||
575 | + "unknown MII register 0x%x\n", reg); | ||
576 | + s->mii_data = 0; | ||
577 | + break; | ||
578 | + } | ||
579 | + | ||
580 | + trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data); | ||
581 | + } | ||
582 | +} | 155 | +} |
583 | + | 156 | + |
584 | +static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s) | 157 | +static bool trans_CAS(DisasContext *s, arg_CAS *a) |
585 | +{ | 158 | +{ |
586 | + qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0); | 159 | + if (!dc_isar_feature(aa64_atomics, s)) { |
587 | +} | 160 | + return false; |
588 | + | ||
589 | +static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc, | ||
590 | + size_t min_size) | ||
591 | +{ | ||
592 | + uint32_t paddr = desc->next; | ||
593 | + | ||
594 | + cpu_physical_memory_read(paddr, desc, sizeof(*desc)); | ||
595 | + | ||
596 | + if ((desc->status & DESC_STATUS_CTL) && | ||
597 | + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { | ||
598 | + return paddr; | ||
599 | + } else { | ||
600 | + return 0; | ||
601 | + } | 161 | + } |
602 | +} | 162 | + gen_compare_and_swap(s, a->rs, a->rt, a->rn, a->sz); |
603 | + | 163 | + return true; |
604 | +static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc, | 164 | } |
605 | + uint32_t start_addr, | 165 | |
606 | + size_t min_size) | 166 | /* |
607 | +{ | 167 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) |
608 | + uint32_t desc_addr = start_addr; | 168 | static void disas_ldst(DisasContext *s, uint32_t insn) |
609 | + | 169 | { |
610 | + /* Note that the list is a cycle. Last entry points back to the head. */ | 170 | switch (extract32(insn, 24, 6)) { |
611 | + while (desc_addr != 0) { | 171 | - case 0x08: /* Load/store exclusive */ |
612 | + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); | 172 | - disas_ldst_excl(s, insn); |
613 | + | 173 | - break; |
614 | + if ((desc->status & DESC_STATUS_CTL) && | 174 | case 0x18: case 0x1c: /* Load register (literal) */ |
615 | + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { | 175 | disas_ld_lit(s, insn); |
616 | + return desc_addr; | 176 | break; |
617 | + } else if (desc->next == start_addr) { | ||
618 | + break; | ||
619 | + } else { | ||
620 | + desc_addr = desc->next; | ||
621 | + } | ||
622 | + } | ||
623 | + | ||
624 | + return 0; | ||
625 | +} | ||
626 | + | ||
627 | +static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s, | ||
628 | + FrameDescriptor *desc, | ||
629 | + size_t min_size) | ||
630 | +{ | ||
631 | + return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size); | ||
632 | +} | ||
633 | + | ||
634 | +static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s, | ||
635 | + FrameDescriptor *desc, | ||
636 | + size_t min_size) | ||
637 | +{ | ||
638 | + return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size); | ||
639 | +} | ||
640 | + | ||
641 | +static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc, | ||
642 | + uint32_t phys_addr) | ||
643 | +{ | ||
644 | + cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); | ||
645 | +} | ||
646 | + | ||
647 | +static int allwinner_sun8i_emac_can_receive(NetClientState *nc) | ||
648 | +{ | ||
649 | + AwSun8iEmacState *s = qemu_get_nic_opaque(nc); | ||
650 | + FrameDescriptor desc; | ||
651 | + | ||
652 | + return (s->rx_ctl0 & RX_CTL0_RX_EN) && | ||
653 | + (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0); | ||
654 | +} | ||
655 | + | ||
656 | +static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc, | ||
657 | + const uint8_t *buf, | ||
658 | + size_t size) | ||
659 | +{ | ||
660 | + AwSun8iEmacState *s = qemu_get_nic_opaque(nc); | ||
661 | + FrameDescriptor desc; | ||
662 | + size_t bytes_left = size; | ||
663 | + size_t desc_bytes = 0; | ||
664 | + size_t pad_fcs_size = 4; | ||
665 | + size_t padding = 0; | ||
666 | + | ||
667 | + if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { | ||
668 | + return -1; | ||
669 | + } | ||
670 | + | ||
671 | + s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc, | ||
672 | + AW_SUN8I_EMAC_MIN_PKT_SZ); | ||
673 | + if (!s->rx_desc_curr) { | ||
674 | + s->int_sta |= INT_STA_RX_BUF_UA; | ||
675 | + } | ||
676 | + | ||
677 | + /* Keep filling RX descriptors until the whole frame is written */ | ||
678 | + while (s->rx_desc_curr && bytes_left > 0) { | ||
679 | + desc.status &= ~DESC_STATUS_CTL; | ||
680 | + desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK; | ||
681 | + | ||
682 | + if (bytes_left == size) { | ||
683 | + desc.status |= RX_DESC_STATUS_FIRST_DESC; | ||
684 | + } | ||
685 | + | ||
686 | + if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < | ||
687 | + (bytes_left + pad_fcs_size)) { | ||
688 | + desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; | ||
689 | + desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT; | ||
690 | + } else { | ||
691 | + padding = pad_fcs_size; | ||
692 | + if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) { | ||
693 | + padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left); | ||
694 | + } | ||
695 | + | ||
696 | + desc_bytes = (bytes_left); | ||
697 | + desc.status |= RX_DESC_STATUS_LAST_DESC; | ||
698 | + desc.status |= (bytes_left + padding) | ||
699 | + << RX_DESC_STATUS_FRM_LEN_SHIFT; | ||
700 | + } | ||
701 | + | ||
702 | + cpu_physical_memory_write(desc.addr, buf, desc_bytes); | ||
703 | + allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr); | ||
704 | + trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr, | ||
705 | + desc_bytes); | ||
706 | + | ||
707 | + /* Check if frame needs to raise the receive interrupt */ | ||
708 | + if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { | ||
709 | + s->int_sta |= INT_STA_RX; | ||
710 | + } | ||
711 | + | ||
712 | + /* Increment variables */ | ||
713 | + buf += desc_bytes; | ||
714 | + bytes_left -= desc_bytes; | ||
715 | + | ||
716 | + /* Move to the next descriptor */ | ||
717 | + s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64); | ||
718 | + if (!s->rx_desc_curr) { | ||
719 | + /* Not enough buffer space available */ | ||
720 | + s->int_sta |= INT_STA_RX_BUF_UA; | ||
721 | + s->rx_desc_curr = s->rx_desc_head; | ||
722 | + break; | ||
723 | + } | ||
724 | + } | ||
725 | + | ||
726 | + /* Report receive DMA is finished */ | ||
727 | + s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START; | ||
728 | + allwinner_sun8i_emac_update_irq(s); | ||
729 | + | ||
730 | + return size; | ||
731 | +} | ||
732 | + | ||
733 | +static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s) | ||
734 | +{ | ||
735 | + NetClientState *nc = qemu_get_queue(s->nic); | ||
736 | + FrameDescriptor desc; | ||
737 | + size_t bytes = 0; | ||
738 | + size_t packet_bytes = 0; | ||
739 | + size_t transmitted = 0; | ||
740 | + static uint8_t packet_buf[2048]; | ||
741 | + | ||
742 | + s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0); | ||
743 | + | ||
744 | + /* Read all transmit descriptors */ | ||
745 | + while (s->tx_desc_curr != 0) { | ||
746 | + | ||
747 | + /* Read from physical memory into packet buffer */ | ||
748 | + bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; | ||
749 | + if (bytes + packet_bytes > sizeof(packet_buf)) { | ||
750 | + desc.status |= TX_DESC_STATUS_LENGTH_ERR; | ||
751 | + break; | ||
752 | + } | ||
753 | + cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes); | ||
754 | + packet_bytes += bytes; | ||
755 | + desc.status &= ~DESC_STATUS_CTL; | ||
756 | + allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr); | ||
757 | + | ||
758 | + /* After the last descriptor, send the packet */ | ||
759 | + if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { | ||
760 | + if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { | ||
761 | + net_checksum_calculate(packet_buf, packet_bytes); | ||
762 | + } | ||
763 | + | ||
764 | + qemu_send_packet(nc, packet_buf, packet_bytes); | ||
765 | + trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr, | ||
766 | + bytes); | ||
767 | + | ||
768 | + packet_bytes = 0; | ||
769 | + transmitted++; | ||
770 | + } | ||
771 | + s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0); | ||
772 | + } | ||
773 | + | ||
774 | + /* Raise transmit completed interrupt */ | ||
775 | + if (transmitted > 0) { | ||
776 | + s->int_sta |= INT_STA_TX; | ||
777 | + s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START; | ||
778 | + allwinner_sun8i_emac_update_irq(s); | ||
779 | + } | ||
780 | +} | ||
781 | + | ||
782 | +static void allwinner_sun8i_emac_reset(DeviceState *dev) | ||
783 | +{ | ||
784 | + AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); | ||
785 | + NetClientState *nc = qemu_get_queue(s->nic); | ||
786 | + | ||
787 | + trace_allwinner_sun8i_emac_reset(); | ||
788 | + | ||
789 | + s->mii_cmd = 0; | ||
790 | + s->mii_data = 0; | ||
791 | + s->basic_ctl0 = 0; | ||
792 | + s->basic_ctl1 = REG_BASIC_CTL_1_RST; | ||
793 | + s->int_en = 0; | ||
794 | + s->int_sta = 0; | ||
795 | + s->frm_flt = 0; | ||
796 | + s->rx_ctl0 = 0; | ||
797 | + s->rx_ctl1 = RX_CTL1_RX_MD; | ||
798 | + s->rx_desc_head = 0; | ||
799 | + s->rx_desc_curr = 0; | ||
800 | + s->tx_ctl0 = 0; | ||
801 | + s->tx_ctl1 = 0; | ||
802 | + s->tx_desc_head = 0; | ||
803 | + s->tx_desc_curr = 0; | ||
804 | + s->tx_flowctl = 0; | ||
805 | + | ||
806 | + allwinner_sun8i_emac_mii_reset(s, !nc->link_down); | ||
807 | +} | ||
808 | + | ||
809 | +static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, | ||
810 | + unsigned size) | ||
811 | +{ | ||
812 | + AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); | ||
813 | + uint64_t value = 0; | ||
814 | + FrameDescriptor desc; | ||
815 | + | ||
816 | + switch (offset) { | ||
817 | + case REG_BASIC_CTL_0: /* Basic Control 0 */ | ||
818 | + value = s->basic_ctl0; | ||
819 | + break; | ||
820 | + case REG_BASIC_CTL_1: /* Basic Control 1 */ | ||
821 | + value = s->basic_ctl1; | ||
822 | + break; | ||
823 | + case REG_INT_STA: /* Interrupt Status */ | ||
824 | + value = s->int_sta; | ||
825 | + break; | ||
826 | + case REG_INT_EN: /* Interupt Enable */ | ||
827 | + value = s->int_en; | ||
828 | + break; | ||
829 | + case REG_TX_CTL_0: /* Transmit Control 0 */ | ||
830 | + value = s->tx_ctl0; | ||
831 | + break; | ||
832 | + case REG_TX_CTL_1: /* Transmit Control 1 */ | ||
833 | + value = s->tx_ctl1; | ||
834 | + break; | ||
835 | + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ | ||
836 | + value = s->tx_flowctl; | ||
837 | + break; | ||
838 | + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ | ||
839 | + value = s->tx_desc_head; | ||
840 | + break; | ||
841 | + case REG_RX_CTL_0: /* Receive Control 0 */ | ||
842 | + value = s->rx_ctl0; | ||
843 | + break; | ||
844 | + case REG_RX_CTL_1: /* Receive Control 1 */ | ||
845 | + value = s->rx_ctl1; | ||
846 | + break; | ||
847 | + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ | ||
848 | + value = s->rx_desc_head; | ||
849 | + break; | ||
850 | + case REG_FRM_FLT: /* Receive Frame Filter */ | ||
851 | + value = s->frm_flt; | ||
852 | + break; | ||
853 | + case REG_RX_HASH_0: /* Receive Hash Table 0 */ | ||
854 | + case REG_RX_HASH_1: /* Receive Hash Table 1 */ | ||
855 | + break; | ||
856 | + case REG_MII_CMD: /* Management Interface Command */ | ||
857 | + value = s->mii_cmd; | ||
858 | + break; | ||
859 | + case REG_MII_DATA: /* Management Interface Data */ | ||
860 | + value = s->mii_data; | ||
861 | + break; | ||
862 | + case REG_ADDR_HIGH: /* MAC Address High */ | ||
863 | + value = *(((uint32_t *) (s->conf.macaddr.a)) + 1); | ||
864 | + break; | ||
865 | + case REG_ADDR_LOW: /* MAC Address Low */ | ||
866 | + value = *(uint32_t *) (s->conf.macaddr.a); | ||
867 | + break; | ||
868 | + case REG_TX_DMA_STA: /* Transmit DMA Status */ | ||
869 | + break; | ||
870 | + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ | ||
871 | + value = s->tx_desc_curr; | ||
872 | + break; | ||
873 | + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ | ||
874 | + if (s->tx_desc_curr != 0) { | ||
875 | + cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc)); | ||
876 | + value = desc.addr; | ||
877 | + } else { | ||
878 | + value = 0; | ||
879 | + } | ||
880 | + break; | ||
881 | + case REG_RX_DMA_STA: /* Receive DMA Status */ | ||
882 | + break; | ||
883 | + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ | ||
884 | + value = s->rx_desc_curr; | ||
885 | + break; | ||
886 | + case REG_RX_CUR_BUF: /* Receive Current Buffer */ | ||
887 | + if (s->rx_desc_curr != 0) { | ||
888 | + cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc)); | ||
889 | + value = desc.addr; | ||
890 | + } else { | ||
891 | + value = 0; | ||
892 | + } | ||
893 | + break; | ||
894 | + case REG_RGMII_STA: /* RGMII Status */ | ||
895 | + break; | ||
896 | + default: | ||
897 | + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " | ||
898 | + "EMAC register 0x" TARGET_FMT_plx "\n", | ||
899 | + offset); | ||
900 | + } | ||
901 | + | ||
902 | + trace_allwinner_sun8i_emac_read(offset, value); | ||
903 | + return value; | ||
904 | +} | ||
905 | + | ||
906 | +static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset, | ||
907 | + uint64_t value, unsigned size) | ||
908 | +{ | ||
909 | + AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); | ||
910 | + NetClientState *nc = qemu_get_queue(s->nic); | ||
911 | + | ||
912 | + trace_allwinner_sun8i_emac_write(offset, value); | ||
913 | + | ||
914 | + switch (offset) { | ||
915 | + case REG_BASIC_CTL_0: /* Basic Control 0 */ | ||
916 | + s->basic_ctl0 = value; | ||
917 | + break; | ||
918 | + case REG_BASIC_CTL_1: /* Basic Control 1 */ | ||
919 | + if (value & BASIC_CTL1_SOFTRST) { | ||
920 | + allwinner_sun8i_emac_reset(DEVICE(s)); | ||
921 | + value &= ~BASIC_CTL1_SOFTRST; | ||
922 | + } | ||
923 | + s->basic_ctl1 = value; | ||
924 | + if (allwinner_sun8i_emac_can_receive(nc)) { | ||
925 | + qemu_flush_queued_packets(nc); | ||
926 | + } | ||
927 | + break; | ||
928 | + case REG_INT_STA: /* Interrupt Status */ | ||
929 | + s->int_sta &= ~value; | ||
930 | + allwinner_sun8i_emac_update_irq(s); | ||
931 | + break; | ||
932 | + case REG_INT_EN: /* Interrupt Enable */ | ||
933 | + s->int_en = value; | ||
934 | + allwinner_sun8i_emac_update_irq(s); | ||
935 | + break; | ||
936 | + case REG_TX_CTL_0: /* Transmit Control 0 */ | ||
937 | + s->tx_ctl0 = value; | ||
938 | + break; | ||
939 | + case REG_TX_CTL_1: /* Transmit Control 1 */ | ||
940 | + s->tx_ctl1 = value; | ||
941 | + if (value & TX_CTL1_TX_DMA_EN) { | ||
942 | + allwinner_sun8i_emac_transmit(s); | ||
943 | + } | ||
944 | + break; | ||
945 | + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ | ||
946 | + s->tx_flowctl = value; | ||
947 | + break; | ||
948 | + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ | ||
949 | + s->tx_desc_head = value; | ||
950 | + s->tx_desc_curr = value; | ||
951 | + break; | ||
952 | + case REG_RX_CTL_0: /* Receive Control 0 */ | ||
953 | + s->rx_ctl0 = value; | ||
954 | + break; | ||
955 | + case REG_RX_CTL_1: /* Receive Control 1 */ | ||
956 | + s->rx_ctl1 = value | RX_CTL1_RX_MD; | ||
957 | + if ((value & RX_CTL1_RX_DMA_EN) && | ||
958 | + allwinner_sun8i_emac_can_receive(nc)) { | ||
959 | + qemu_flush_queued_packets(nc); | ||
960 | + } | ||
961 | + break; | ||
962 | + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ | ||
963 | + s->rx_desc_head = value; | ||
964 | + s->rx_desc_curr = value; | ||
965 | + break; | ||
966 | + case REG_FRM_FLT: /* Receive Frame Filter */ | ||
967 | + s->frm_flt = value; | ||
968 | + break; | ||
969 | + case REG_RX_HASH_0: /* Receive Hash Table 0 */ | ||
970 | + case REG_RX_HASH_1: /* Receive Hash Table 1 */ | ||
971 | + break; | ||
972 | + case REG_MII_CMD: /* Management Interface Command */ | ||
973 | + s->mii_cmd = value & ~MII_CMD_PHY_BUSY; | ||
974 | + allwinner_sun8i_emac_mii_cmd(s); | ||
975 | + break; | ||
976 | + case REG_MII_DATA: /* Management Interface Data */ | ||
977 | + s->mii_data = value; | ||
978 | + break; | ||
979 | + case REG_ADDR_HIGH: /* MAC Address High */ | ||
980 | + s->conf.macaddr.a[4] = (value & 0xff); | ||
981 | + s->conf.macaddr.a[5] = (value & 0xff00) >> 8; | ||
982 | + break; | ||
983 | + case REG_ADDR_LOW: /* MAC Address Low */ | ||
984 | + s->conf.macaddr.a[0] = (value & 0xff); | ||
985 | + s->conf.macaddr.a[1] = (value & 0xff00) >> 8; | ||
986 | + s->conf.macaddr.a[2] = (value & 0xff0000) >> 16; | ||
987 | + s->conf.macaddr.a[3] = (value & 0xff000000) >> 24; | ||
988 | + break; | ||
989 | + case REG_TX_DMA_STA: /* Transmit DMA Status */ | ||
990 | + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ | ||
991 | + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ | ||
992 | + case REG_RX_DMA_STA: /* Receive DMA Status */ | ||
993 | + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ | ||
994 | + case REG_RX_CUR_BUF: /* Receive Current Buffer */ | ||
995 | + case REG_RGMII_STA: /* RGMII Status */ | ||
996 | + break; | ||
997 | + default: | ||
998 | + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " | ||
999 | + "EMAC register 0x" TARGET_FMT_plx "\n", | ||
1000 | + offset); | ||
1001 | + } | ||
1002 | +} | ||
1003 | + | ||
1004 | +static void allwinner_sun8i_emac_set_link(NetClientState *nc) | ||
1005 | +{ | ||
1006 | + AwSun8iEmacState *s = qemu_get_nic_opaque(nc); | ||
1007 | + | ||
1008 | + trace_allwinner_sun8i_emac_set_link(!nc->link_down); | ||
1009 | + allwinner_sun8i_emac_mii_set_link(s, !nc->link_down); | ||
1010 | +} | ||
1011 | + | ||
1012 | +static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = { | ||
1013 | + .read = allwinner_sun8i_emac_read, | ||
1014 | + .write = allwinner_sun8i_emac_write, | ||
1015 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
1016 | + .valid = { | ||
1017 | + .min_access_size = 4, | ||
1018 | + .max_access_size = 4, | ||
1019 | + }, | ||
1020 | + .impl.min_access_size = 4, | ||
1021 | +}; | ||
1022 | + | ||
1023 | +static NetClientInfo net_allwinner_sun8i_emac_info = { | ||
1024 | + .type = NET_CLIENT_DRIVER_NIC, | ||
1025 | + .size = sizeof(NICState), | ||
1026 | + .can_receive = allwinner_sun8i_emac_can_receive, | ||
1027 | + .receive = allwinner_sun8i_emac_receive, | ||
1028 | + .link_status_changed = allwinner_sun8i_emac_set_link, | ||
1029 | +}; | ||
1030 | + | ||
1031 | +static void allwinner_sun8i_emac_init(Object *obj) | ||
1032 | +{ | ||
1033 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
1034 | + AwSun8iEmacState *s = AW_SUN8I_EMAC(obj); | ||
1035 | + | ||
1036 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops, | ||
1037 | + s, TYPE_AW_SUN8I_EMAC, 64 * KiB); | ||
1038 | + sysbus_init_mmio(sbd, &s->iomem); | ||
1039 | + sysbus_init_irq(sbd, &s->irq); | ||
1040 | +} | ||
1041 | + | ||
1042 | +static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp) | ||
1043 | +{ | ||
1044 | + AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); | ||
1045 | + | ||
1046 | + qemu_macaddr_default_if_unset(&s->conf.macaddr); | ||
1047 | + s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf, | ||
1048 | + object_get_typename(OBJECT(dev)), dev->id, s); | ||
1049 | + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); | ||
1050 | +} | ||
1051 | + | ||
1052 | +static Property allwinner_sun8i_emac_properties[] = { | ||
1053 | + DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf), | ||
1054 | + DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0), | ||
1055 | + DEFINE_PROP_END_OF_LIST(), | ||
1056 | +}; | ||
1057 | + | ||
1058 | +static int allwinner_sun8i_emac_post_load(void *opaque, int version_id) | ||
1059 | +{ | ||
1060 | + AwSun8iEmacState *s = opaque; | ||
1061 | + | ||
1062 | + allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic)); | ||
1063 | + | ||
1064 | + return 0; | ||
1065 | +} | ||
1066 | + | ||
1067 | +static const VMStateDescription vmstate_aw_emac = { | ||
1068 | + .name = "allwinner-sun8i-emac", | ||
1069 | + .version_id = 1, | ||
1070 | + .minimum_version_id = 1, | ||
1071 | + .post_load = allwinner_sun8i_emac_post_load, | ||
1072 | + .fields = (VMStateField[]) { | ||
1073 | + VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState), | ||
1074 | + VMSTATE_UINT32(mii_cmd, AwSun8iEmacState), | ||
1075 | + VMSTATE_UINT32(mii_data, AwSun8iEmacState), | ||
1076 | + VMSTATE_UINT32(mii_cr, AwSun8iEmacState), | ||
1077 | + VMSTATE_UINT32(mii_st, AwSun8iEmacState), | ||
1078 | + VMSTATE_UINT32(mii_adv, AwSun8iEmacState), | ||
1079 | + VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState), | ||
1080 | + VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState), | ||
1081 | + VMSTATE_UINT32(int_en, AwSun8iEmacState), | ||
1082 | + VMSTATE_UINT32(int_sta, AwSun8iEmacState), | ||
1083 | + VMSTATE_UINT32(frm_flt, AwSun8iEmacState), | ||
1084 | + VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState), | ||
1085 | + VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState), | ||
1086 | + VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState), | ||
1087 | + VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState), | ||
1088 | + VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState), | ||
1089 | + VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState), | ||
1090 | + VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState), | ||
1091 | + VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState), | ||
1092 | + VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState), | ||
1093 | + VMSTATE_END_OF_LIST() | ||
1094 | + } | ||
1095 | +}; | ||
1096 | + | ||
1097 | +static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data) | ||
1098 | +{ | ||
1099 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1100 | + | ||
1101 | + dc->realize = allwinner_sun8i_emac_realize; | ||
1102 | + dc->reset = allwinner_sun8i_emac_reset; | ||
1103 | + dc->vmsd = &vmstate_aw_emac; | ||
1104 | + device_class_set_props(dc, allwinner_sun8i_emac_properties); | ||
1105 | +} | ||
1106 | + | ||
1107 | +static const TypeInfo allwinner_sun8i_emac_info = { | ||
1108 | + .name = TYPE_AW_SUN8I_EMAC, | ||
1109 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
1110 | + .instance_size = sizeof(AwSun8iEmacState), | ||
1111 | + .instance_init = allwinner_sun8i_emac_init, | ||
1112 | + .class_init = allwinner_sun8i_emac_class_init, | ||
1113 | +}; | ||
1114 | + | ||
1115 | +static void allwinner_sun8i_emac_register_types(void) | ||
1116 | +{ | ||
1117 | + type_register_static(&allwinner_sun8i_emac_info); | ||
1118 | +} | ||
1119 | + | ||
1120 | +type_init(allwinner_sun8i_emac_register_types) | ||
1121 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
1122 | index XXXXXXX..XXXXXXX 100644 | ||
1123 | --- a/hw/arm/Kconfig | ||
1124 | +++ b/hw/arm/Kconfig | ||
1125 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 | ||
1126 | config ALLWINNER_H3 | ||
1127 | bool | ||
1128 | select ALLWINNER_A10_PIT | ||
1129 | + select ALLWINNER_SUN8I_EMAC | ||
1130 | select SERIAL | ||
1131 | select ARM_TIMER | ||
1132 | select ARM_GIC | ||
1133 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
1134 | index XXXXXXX..XXXXXXX 100644 | ||
1135 | --- a/hw/net/Kconfig | ||
1136 | +++ b/hw/net/Kconfig | ||
1137 | @@ -XXX,XX +XXX,XX @@ config MIPSNET | ||
1138 | config ALLWINNER_EMAC | ||
1139 | bool | ||
1140 | |||
1141 | +config ALLWINNER_SUN8I_EMAC | ||
1142 | + bool | ||
1143 | + | ||
1144 | config IMX_FEC | ||
1145 | bool | ||
1146 | |||
1147 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
1148 | index XXXXXXX..XXXXXXX 100644 | ||
1149 | --- a/hw/net/trace-events | ||
1150 | +++ b/hw/net/trace-events | ||
1151 | @@ -XXX,XX +XXX,XX @@ | ||
1152 | # See docs/devel/tracing.txt for syntax documentation. | ||
1153 | |||
1154 | +# allwinner-sun8i-emac.c | ||
1155 | +allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 | ||
1156 | +allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 | ||
1157 | +allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 | ||
1158 | +allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 | ||
1159 | +allwinner_sun8i_emac_reset(void) "HW reset" | ||
1160 | +allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" | ||
1161 | +allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
1162 | +allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
1163 | + | ||
1164 | # etraxfs_eth.c | ||
1165 | mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x" | ||
1166 | mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x" | ||
1167 | -- | 177 | -- |
1168 | 2.20.1 | 178 | 2.34.1 |
1169 | |||
1170 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Convert the "Load register (literal)" instruction class to |
---|---|---|---|
2 | decodetree. | ||
2 | 3 | ||
3 | Let's move the code which freezes which gic-version to | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | be applied in a dedicated function. We also now set by | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | default the VIRT_GIC_VERSION_NO_SET. This eventually | 6 | Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org |
6 | turns into the legacy v2 choice in the finalize() function. | 7 | --- |
8 | target/arm/tcg/a64.decode | 13 ++++++ | ||
9 | target/arm/tcg/translate-a64.c | 76 ++++++++++------------------------ | ||
10 | 2 files changed, 35 insertions(+), 54 deletions(-) | ||
7 | 11 | ||
8 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
11 | Message-id: 20200311131618.7187-4-eric.auger@redhat.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/arm/virt.h | 1 + | ||
15 | hw/arm/virt.c | 54 ++++++++++++++++++++++++++----------------- | ||
16 | 2 files changed, 34 insertions(+), 21 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/virt.h | 14 | --- a/target/arm/tcg/a64.decode |
21 | +++ b/include/hw/arm/virt.h | 15 | +++ b/target/arm/tcg/a64.decode |
22 | @@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType { | 16 | @@ -XXX,XX +XXX,XX @@ LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP |
23 | VIRT_GIC_VERSION_HOST, | 17 | CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 |
24 | VIRT_GIC_VERSION_2, | 18 | # CAS, CASA, CASAL, CASL |
25 | VIRT_GIC_VERSION_3, | 19 | CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 |
26 | + VIRT_GIC_VERSION_NOSEL, | 20 | + |
27 | } VirtGICType; | 21 | +&ldlit rt imm sz sign |
28 | 22 | +@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 | |
29 | typedef struct MemMapEntry { | 23 | + |
30 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 24 | +LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 |
25 | +LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 | ||
26 | +LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 | ||
27 | +LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 | ||
28 | +LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 | ||
29 | +LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 | ||
30 | + | ||
31 | +# PRFM | ||
32 | +NOP 11 011 0 00 ------------------- ----- | ||
33 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/arm/virt.c | 35 | --- a/target/arm/tcg/translate-a64.c |
33 | +++ b/hw/arm/virt.c | 36 | +++ b/target/arm/tcg/translate-a64.c |
34 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) | 37 | @@ -XXX,XX +XXX,XX @@ static bool trans_CAS(DisasContext *s, arg_CAS *a) |
35 | } | 38 | return true; |
36 | } | 39 | } |
37 | 40 | ||
38 | +/* | 41 | -/* |
39 | + * finalize_gic_version - Determines the final gic_version | 42 | - * Load register (literal) |
40 | + * according to the gic-version property | 43 | - * |
41 | + * | 44 | - * 31 30 29 27 26 25 24 23 5 4 0 |
42 | + * Default GIC type is v2 | 45 | - * +-----+-------+---+-----+-------------------+-------+ |
43 | + */ | 46 | - * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | |
44 | +static void finalize_gic_version(VirtMachineState *vms) | 47 | - * +-----+-------+---+-----+-------------------+-------+ |
45 | +{ | 48 | - * |
46 | + if (vms->gic_version == VIRT_GIC_VERSION_HOST || | 49 | - * V: 1 -> vector (simd/fp) |
47 | + vms->gic_version == VIRT_GIC_VERSION_MAX) { | 50 | - * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, |
48 | + if (!kvm_enabled()) { | 51 | - * 10-> 32 bit signed, 11 -> prefetch |
49 | + if (vms->gic_version == VIRT_GIC_VERSION_HOST) { | 52 | - * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) |
50 | + error_report("gic-version=host requires KVM"); | 53 | - */ |
51 | + exit(1); | 54 | -static void disas_ld_lit(DisasContext *s, uint32_t insn) |
52 | + } else { | 55 | +static bool trans_LD_lit(DisasContext *s, arg_ldlit *a) |
53 | + /* "max": currently means 3 for TCG */ | 56 | { |
54 | + vms->gic_version = VIRT_GIC_VERSION_3; | 57 | - int rt = extract32(insn, 0, 5); |
55 | + } | 58 | - int64_t imm = sextract32(insn, 5, 19) << 2; |
56 | + } else { | 59 | - bool is_vector = extract32(insn, 26, 1); |
57 | + vms->gic_version = kvm_arm_vgic_probe(); | 60 | - int opc = extract32(insn, 30, 2); |
58 | + if (!vms->gic_version) { | 61 | - bool is_signed = false; |
59 | + error_report( | 62 | - int size = 2; |
60 | + "Unable to determine GIC version supported by host"); | 63 | - TCGv_i64 tcg_rt, clean_addr; |
61 | + exit(1); | 64 | + bool iss_sf = ldst_iss_sf(a->sz, a->sign, false); |
62 | + } | 65 | + TCGv_i64 tcg_rt = cpu_reg(s, a->rt); |
63 | + } | 66 | + TCGv_i64 clean_addr = tcg_temp_new_i64(); |
64 | + } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) { | 67 | + MemOp memop = finalize_memop(s, a->sz + a->sign * MO_SIGN); |
65 | + vms->gic_version = VIRT_GIC_VERSION_2; | 68 | + |
66 | + } | 69 | + gen_pc_plus_diff(s, clean_addr, a->imm); |
70 | + do_gpr_ld(s, tcg_rt, clean_addr, memop, | ||
71 | + false, true, a->rt, iss_sf, false); | ||
72 | + return true; | ||
67 | +} | 73 | +} |
68 | + | 74 | + |
69 | static void machvirt_init(MachineState *machine) | 75 | +static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a) |
76 | +{ | ||
77 | + /* Load register (literal), vector version */ | ||
78 | + TCGv_i64 clean_addr; | ||
79 | MemOp memop; | ||
80 | |||
81 | - if (is_vector) { | ||
82 | - if (opc == 3) { | ||
83 | - unallocated_encoding(s); | ||
84 | - return; | ||
85 | - } | ||
86 | - size = 2 + opc; | ||
87 | - if (!fp_access_check(s)) { | ||
88 | - return; | ||
89 | - } | ||
90 | - memop = finalize_memop_asimd(s, size); | ||
91 | - } else { | ||
92 | - if (opc == 3) { | ||
93 | - /* PRFM (literal) : prefetch */ | ||
94 | - return; | ||
95 | - } | ||
96 | - size = 2 + extract32(opc, 0, 1); | ||
97 | - is_signed = extract32(opc, 1, 1); | ||
98 | - memop = finalize_memop(s, size + is_signed * MO_SIGN); | ||
99 | + if (!fp_access_check(s)) { | ||
100 | + return true; | ||
101 | } | ||
102 | - | ||
103 | - tcg_rt = cpu_reg(s, rt); | ||
104 | - | ||
105 | + memop = finalize_memop_asimd(s, a->sz); | ||
106 | clean_addr = tcg_temp_new_i64(); | ||
107 | - gen_pc_plus_diff(s, clean_addr, imm); | ||
108 | - | ||
109 | - if (is_vector) { | ||
110 | - do_fp_ld(s, rt, clean_addr, memop); | ||
111 | - } else { | ||
112 | - /* Only unsigned 32bit loads target 32bit registers. */ | ||
113 | - bool iss_sf = opc != 0; | ||
114 | - do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, false); | ||
115 | - } | ||
116 | + gen_pc_plus_diff(s, clean_addr, a->imm); | ||
117 | + do_fp_ld(s, a->rt, clean_addr, memop); | ||
118 | + return true; | ||
119 | } | ||
120 | |||
121 | /* | ||
122 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
123 | static void disas_ldst(DisasContext *s, uint32_t insn) | ||
70 | { | 124 | { |
71 | VirtMachineState *vms = VIRT_MACHINE(machine); | 125 | switch (extract32(insn, 24, 6)) { |
72 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 126 | - case 0x18: case 0x1c: /* Load register (literal) */ |
73 | /* We can probe only here because during property set | 127 | - disas_ld_lit(s, insn); |
74 | * KVM is not available yet | 128 | - break; |
75 | */ | 129 | case 0x28: case 0x29: |
76 | - if (vms->gic_version == VIRT_GIC_VERSION_HOST || | 130 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ |
77 | - vms->gic_version == VIRT_GIC_VERSION_MAX) { | 131 | disas_ldst_pair(s, insn); |
78 | - if (!kvm_enabled()) { | ||
79 | - if (vms->gic_version == VIRT_GIC_VERSION_HOST) { | ||
80 | - error_report("gic-version=host requires KVM"); | ||
81 | - exit(1); | ||
82 | - } else { | ||
83 | - /* "max": currently means 3 for TCG */ | ||
84 | - vms->gic_version = VIRT_GIC_VERSION_3; | ||
85 | - } | ||
86 | - } else { | ||
87 | - vms->gic_version = kvm_arm_vgic_probe(); | ||
88 | - if (!vms->gic_version) { | ||
89 | - error_report( | ||
90 | - "Unable to determine GIC version supported by host"); | ||
91 | - exit(1); | ||
92 | - } | ||
93 | - } | ||
94 | - } | ||
95 | + finalize_gic_version(vms); | ||
96 | |||
97 | if (!cpu_type_valid(machine->cpu_type)) { | ||
98 | error_report("mach-virt: CPU type %s not supported", machine->cpu_type); | ||
99 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | ||
100 | "Set on/off to enable/disable using " | ||
101 | "physical address space above 32 bits", | ||
102 | NULL); | ||
103 | - /* Default GIC type is v2 */ | ||
104 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
105 | + vms->gic_version = VIRT_GIC_VERSION_NOSEL; | ||
106 | object_property_add_str(obj, "gic-version", virt_get_gic_version, | ||
107 | virt_set_gic_version, NULL); | ||
108 | object_property_set_description(obj, "gic-version", | ||
109 | -- | 132 | -- |
110 | 2.20.1 | 133 | 2.34.1 |
111 | |||
112 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert the load/store register pair insns (LDP, STP, |
---|---|---|---|
2 | LDNP, STNP, LDPSW, STGP) to decodetree. | ||
2 | 3 | ||
3 | Various Allwinner System on Chip designs contain multiple processors | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | that can be configured and reset using the generic CPU Configuration | 5 | Message-id: 20230602155223.2040685-12-peter.maydell@linaro.org |
5 | module interface. This commit adds support for the Allwinner CPU | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | configuration interface which emulates the following features: | 7 | --- |
8 | target/arm/tcg/a64.decode | 61 +++++ | ||
9 | target/arm/tcg/translate-a64.c | 422 ++++++++++++++++----------------- | ||
10 | 2 files changed, 268 insertions(+), 215 deletions(-) | ||
7 | 11 | ||
8 | * CPU reset | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
9 | * CPU status | ||
10 | |||
11 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
12 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
13 | Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/misc/Makefile.objs | 1 + | ||
17 | include/hw/arm/allwinner-h3.h | 3 + | ||
18 | include/hw/misc/allwinner-cpucfg.h | 52 ++++++ | ||
19 | hw/arm/allwinner-h3.c | 9 +- | ||
20 | hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++ | ||
21 | hw/misc/trace-events | 5 + | ||
22 | 6 files changed, 351 insertions(+), 1 deletion(-) | ||
23 | create mode 100644 include/hw/misc/allwinner-cpucfg.h | ||
24 | create mode 100644 hw/misc/allwinner-cpucfg.c | ||
25 | |||
26 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
27 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/misc/Makefile.objs | 14 | --- a/target/arm/tcg/a64.decode |
29 | +++ b/hw/misc/Makefile.objs | 15 | +++ b/target/arm/tcg/a64.decode |
30 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/ | 16 | @@ -XXX,XX +XXX,XX @@ LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 |
31 | common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o | 17 | |
32 | 18 | # PRFM | |
33 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o | 19 | NOP 11 011 0 00 ------------------- ----- |
34 | +obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o | 20 | + |
35 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o | 21 | +&ldstpair rt2 rt rn imm sz sign w p |
36 | common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o | 22 | +@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair |
37 | common-obj-$(CONFIG_NSERIES) += cbus.o | 23 | + |
38 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 24 | +# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches |
25 | +# so we ignore hints about data access patterns, and handle these like | ||
26 | +# plain signed offset. | ||
27 | +STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
28 | +LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
29 | +STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
30 | +LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
31 | +STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
32 | +LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
33 | +STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
34 | +LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
35 | +STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 | ||
36 | +LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 | ||
37 | + | ||
38 | +# STP and LDP: post-indexed | ||
39 | +STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 | ||
40 | +LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 | ||
41 | +LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 | ||
42 | +STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 | ||
43 | +LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 | ||
44 | +STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 | ||
45 | +LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 | ||
46 | +STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 | ||
47 | +LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 | ||
48 | +STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 | ||
49 | +LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 | ||
50 | + | ||
51 | +# STP and LDP: offset | ||
52 | +STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
53 | +LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
54 | +LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 | ||
55 | +STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
56 | +LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
57 | +STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
58 | +LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 | ||
59 | +STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
60 | +LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
61 | +STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 | ||
62 | +LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 | ||
63 | + | ||
64 | +# STP and LDP: pre-indexed | ||
65 | +STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 | ||
66 | +LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 | ||
67 | +LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 | ||
68 | +STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 | ||
69 | +LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 | ||
70 | +STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 | ||
71 | +LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 | ||
72 | +STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 | ||
73 | +LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 | ||
74 | +STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 | ||
75 | +LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 | ||
76 | + | ||
77 | +# STGP: store tag and pair | ||
78 | +STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 | ||
79 | +STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 | ||
80 | +STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 | ||
81 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | 82 | index XXXXXXX..XXXXXXX 100644 |
40 | --- a/include/hw/arm/allwinner-h3.h | 83 | --- a/target/arm/tcg/translate-a64.c |
41 | +++ b/include/hw/arm/allwinner-h3.h | 84 | +++ b/target/arm/tcg/translate-a64.c |
42 | @@ -XXX,XX +XXX,XX @@ | 85 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a) |
43 | #include "hw/timer/allwinner-a10-pit.h" | 86 | return true; |
44 | #include "hw/intc/arm_gic.h" | ||
45 | #include "hw/misc/allwinner-h3-ccu.h" | ||
46 | +#include "hw/misc/allwinner-cpucfg.h" | ||
47 | #include "hw/misc/allwinner-h3-sysctrl.h" | ||
48 | #include "target/arm/cpu.h" | ||
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ enum { | ||
51 | AW_H3_GIC_CPU, | ||
52 | AW_H3_GIC_HYP, | ||
53 | AW_H3_GIC_VCPU, | ||
54 | + AW_H3_CPUCFG, | ||
55 | AW_H3_SDRAM | ||
56 | }; | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
59 | const hwaddr *memmap; | ||
60 | AwA10PITState timer; | ||
61 | AwH3ClockCtlState ccu; | ||
62 | + AwCpuCfgState cpucfg; | ||
63 | AwH3SysCtrlState sysctrl; | ||
64 | GICState gic; | ||
65 | MemoryRegion sram_a1; | ||
66 | diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h | ||
67 | new file mode 100644 | ||
68 | index XXXXXXX..XXXXXXX | ||
69 | --- /dev/null | ||
70 | +++ b/include/hw/misc/allwinner-cpucfg.h | ||
71 | @@ -XXX,XX +XXX,XX @@ | ||
72 | +/* | ||
73 | + * Allwinner CPU Configuration Module emulation | ||
74 | + * | ||
75 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
76 | + * | ||
77 | + * This program is free software: you can redistribute it and/or modify | ||
78 | + * it under the terms of the GNU General Public License as published by | ||
79 | + * the Free Software Foundation, either version 2 of the License, or | ||
80 | + * (at your option) any later version. | ||
81 | + * | ||
82 | + * This program is distributed in the hope that it will be useful, | ||
83 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
84 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
85 | + * GNU General Public License for more details. | ||
86 | + * | ||
87 | + * You should have received a copy of the GNU General Public License | ||
88 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
89 | + */ | ||
90 | + | ||
91 | +#ifndef HW_MISC_ALLWINNER_CPUCFG_H | ||
92 | +#define HW_MISC_ALLWINNER_CPUCFG_H | ||
93 | + | ||
94 | +#include "qom/object.h" | ||
95 | +#include "hw/sysbus.h" | ||
96 | + | ||
97 | +/** | ||
98 | + * Object model | ||
99 | + * @{ | ||
100 | + */ | ||
101 | + | ||
102 | +#define TYPE_AW_CPUCFG "allwinner-cpucfg" | ||
103 | +#define AW_CPUCFG(obj) \ | ||
104 | + OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG) | ||
105 | + | ||
106 | +/** @} */ | ||
107 | + | ||
108 | +/** | ||
109 | + * Allwinner CPU Configuration Module instance state | ||
110 | + */ | ||
111 | +typedef struct AwCpuCfgState { | ||
112 | + /*< private >*/ | ||
113 | + SysBusDevice parent_obj; | ||
114 | + /*< public >*/ | ||
115 | + | ||
116 | + MemoryRegion iomem; | ||
117 | + uint32_t gen_ctrl; | ||
118 | + uint32_t super_standby; | ||
119 | + uint32_t entry_addr; | ||
120 | + | ||
121 | +} AwCpuCfgState; | ||
122 | + | ||
123 | +#endif /* HW_MISC_ALLWINNER_CPUCFG_H */ | ||
124 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
125 | index XXXXXXX..XXXXXXX 100644 | ||
126 | --- a/hw/arm/allwinner-h3.c | ||
127 | +++ b/hw/arm/allwinner-h3.c | ||
128 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
129 | [AW_H3_GIC_CPU] = 0x01c82000, | ||
130 | [AW_H3_GIC_HYP] = 0x01c84000, | ||
131 | [AW_H3_GIC_VCPU] = 0x01c86000, | ||
132 | + [AW_H3_CPUCFG] = 0x01f01c00, | ||
133 | [AW_H3_SDRAM] = 0x40000000 | ||
134 | }; | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
137 | { "r_wdog", 0x01f01000, 1 * KiB }, | ||
138 | { "r_prcm", 0x01f01400, 1 * KiB }, | ||
139 | { "r_twd", 0x01f01800, 1 * KiB }, | ||
140 | - { "r_cpucfg", 0x01f01c00, 1 * KiB }, | ||
141 | { "r_cir-rx", 0x01f02000, 1 * KiB }, | ||
142 | { "r_twi", 0x01f02400, 1 * KiB }, | ||
143 | { "r_uart", 0x01f02800, 1 * KiB }, | ||
144 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
145 | |||
146 | sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl), | ||
147 | TYPE_AW_H3_SYSCTRL); | ||
148 | + | ||
149 | + sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), | ||
150 | + TYPE_AW_CPUCFG); | ||
151 | } | 87 | } |
152 | 88 | ||
153 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 89 | -/* |
154 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 90 | - * LDNP (Load Pair - non-temporal hint) |
155 | qdev_init_nofail(DEVICE(&s->sysctrl)); | 91 | - * LDP (Load Pair - non vector) |
156 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]); | 92 | - * LDPSW (Load Pair Signed Word - non vector) |
157 | 93 | - * STNP (Store Pair - non-temporal hint) | |
158 | + /* CPU Configuration */ | 94 | - * STP (Store Pair - non vector) |
159 | + qdev_init_nofail(DEVICE(&s->cpucfg)); | 95 | - * LDNP (Load Pair of SIMD&FP - non-temporal hint) |
160 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); | 96 | - * LDP (Load Pair of SIMD&FP) |
161 | + | 97 | - * STNP (Store Pair of SIMD&FP - non-temporal hint) |
162 | /* Universal Serial Bus */ | 98 | - * STP (Store Pair of SIMD&FP) |
163 | sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], | 99 | - * |
164 | qdev_get_gpio_in(DEVICE(&s->gic), | 100 | - * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 |
165 | diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c | 101 | - * +-----+-------+---+---+-------+---+-----------------------------+ |
166 | new file mode 100644 | 102 | - * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | |
167 | index XXXXXXX..XXXXXXX | 103 | - * +-----+-------+---+---+-------+---+-------+-------+------+------+ |
168 | --- /dev/null | 104 | - * |
169 | +++ b/hw/misc/allwinner-cpucfg.c | 105 | - * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit |
170 | @@ -XXX,XX +XXX,XX @@ | 106 | - * LDPSW/STGP 01 |
171 | +/* | 107 | - * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit |
172 | + * Allwinner CPU Configuration Module emulation | 108 | - * V: 0 -> GPR, 1 -> Vector |
173 | + * | 109 | - * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, |
174 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | 110 | - * 10 -> signed offset, 11 -> pre-index |
175 | + * | 111 | - * L: 0 -> Store 1 -> Load |
176 | + * This program is free software: you can redistribute it and/or modify | 112 | - * |
177 | + * it under the terms of the GNU General Public License as published by | 113 | - * Rt, Rt2 = GPR or SIMD registers to be stored |
178 | + * the Free Software Foundation, either version 2 of the License, or | 114 | - * Rn = general purpose register containing address |
179 | + * (at your option) any later version. | 115 | - * imm7 = signed offset (multiple of 4 or 8 depending on size) |
180 | + * | 116 | - */ |
181 | + * This program is distributed in the hope that it will be useful, | 117 | -static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
182 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 118 | +static void op_addr_ldstpair_pre(DisasContext *s, arg_ldstpair *a, |
183 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 119 | + TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr, |
184 | + * GNU General Public License for more details. | 120 | + uint64_t offset, bool is_store, MemOp mop) |
185 | + * | 121 | { |
186 | + * You should have received a copy of the GNU General Public License | 122 | - int rt = extract32(insn, 0, 5); |
187 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | 123 | - int rn = extract32(insn, 5, 5); |
188 | + */ | 124 | - int rt2 = extract32(insn, 10, 5); |
189 | + | 125 | - uint64_t offset = sextract64(insn, 15, 7); |
190 | +#include "qemu/osdep.h" | 126 | - int index = extract32(insn, 23, 2); |
191 | +#include "qemu/units.h" | 127 | - bool is_vector = extract32(insn, 26, 1); |
192 | +#include "hw/sysbus.h" | 128 | - bool is_load = extract32(insn, 22, 1); |
193 | +#include "migration/vmstate.h" | 129 | - int opc = extract32(insn, 30, 2); |
194 | +#include "qemu/log.h" | 130 | - bool is_signed = false; |
195 | +#include "qemu/module.h" | 131 | - bool postindex = false; |
196 | +#include "qemu/error-report.h" | 132 | - bool wback = false; |
197 | +#include "qemu/timer.h" | 133 | - bool set_tag = false; |
198 | +#include "hw/core/cpu.h" | 134 | - TCGv_i64 clean_addr, dirty_addr; |
199 | +#include "target/arm/arm-powerctl.h" | 135 | - MemOp mop; |
200 | +#include "target/arm/cpu.h" | 136 | - int size; |
201 | +#include "hw/misc/allwinner-cpucfg.h" | 137 | - |
202 | +#include "trace.h" | 138 | - if (opc == 3) { |
203 | + | 139 | - unallocated_encoding(s); |
204 | +/* CPUCFG register offsets */ | 140 | - return; |
205 | +enum { | 141 | - } |
206 | + REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */ | 142 | - |
207 | + REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */ | 143 | - if (is_vector) { |
208 | + REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */ | 144 | - size = 2 + opc; |
209 | + REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */ | 145 | - } else if (opc == 1 && !is_load) { |
210 | + REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */ | 146 | - /* STGP */ |
211 | + REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */ | 147 | - if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { |
212 | + REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */ | 148 | - unallocated_encoding(s); |
213 | + REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */ | 149 | - return; |
214 | + REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */ | 150 | - } |
215 | + REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */ | 151 | - size = 3; |
216 | + REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */ | 152 | - set_tag = true; |
217 | + REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */ | 153 | - } else { |
218 | + REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */ | 154 | - size = 2 + extract32(opc, 1, 1); |
219 | + REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */ | 155 | - is_signed = extract32(opc, 0, 1); |
220 | + REG_CLK_GATING = 0x0144, /* CPU Clock Gating */ | 156 | - if (!is_load && is_signed) { |
221 | + REG_GEN_CTRL = 0x0184, /* General Control */ | 157 | - unallocated_encoding(s); |
222 | + REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */ | 158 | - return; |
223 | + REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */ | 159 | - } |
224 | + REG_DBG_EXTERN = 0x01E4, /* Debug External */ | 160 | - } |
225 | + REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */ | 161 | - |
226 | + REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */ | 162 | - switch (index) { |
227 | + REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */ | 163 | - case 1: /* post-index */ |
228 | +}; | 164 | - postindex = true; |
229 | + | 165 | - wback = true; |
230 | +/* CPUCFG register flags */ | 166 | - break; |
231 | +enum { | 167 | - case 0: |
232 | + CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)), | 168 | - /* signed offset with "non-temporal" hint. Since we don't emulate |
233 | + CPUX_STATUS_SMP = (1 << 0), | 169 | - * caches we don't care about hints to the cache system about |
234 | + CPU_SYS_RESET_RELEASED = (1 << 0), | 170 | - * data access patterns, and handle this identically to plain |
235 | + CLK_GATING_ENABLE = ((1 << 8) | 0xF), | 171 | - * signed offset. |
236 | +}; | 172 | - */ |
237 | + | 173 | - if (is_signed) { |
238 | +/* CPUCFG register reset values */ | 174 | - /* There is no non-temporal-hint version of LDPSW */ |
239 | +enum { | 175 | - unallocated_encoding(s); |
240 | + REG_CLK_GATING_RST = 0x0000010F, | 176 | - return; |
241 | + REG_GEN_CTRL_RST = 0x00000020, | 177 | - } |
242 | + REG_SUPER_STANDBY_RST = 0x0, | 178 | - postindex = false; |
243 | + REG_CNT64_CTRL_RST = 0x0, | 179 | - break; |
244 | +}; | 180 | - case 2: /* signed offset, rn not updated */ |
245 | + | 181 | - postindex = false; |
246 | +/* CPUCFG constants */ | 182 | - break; |
247 | +enum { | 183 | - case 3: /* pre-index */ |
248 | + CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */ | 184 | - postindex = false; |
249 | +}; | 185 | - wback = true; |
250 | + | 186 | - break; |
251 | +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id) | 187 | - } |
188 | - | ||
189 | - if (is_vector && !fp_access_check(s)) { | ||
190 | - return; | ||
191 | - } | ||
192 | - | ||
193 | - offset <<= (set_tag ? LOG2_TAG_GRANULE : size); | ||
194 | - | ||
195 | - if (rn == 31) { | ||
196 | + if (a->rn == 31) { | ||
197 | gen_check_sp_alignment(s); | ||
198 | } | ||
199 | |||
200 | - dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
201 | - if (!postindex) { | ||
202 | + *dirty_addr = read_cpu_reg_sp(s, a->rn, 1); | ||
203 | + if (!a->p) { | ||
204 | + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); | ||
205 | + } | ||
206 | + | ||
207 | + *clean_addr = gen_mte_checkN(s, *dirty_addr, is_store, | ||
208 | + (a->w || a->rn != 31), 2 << a->sz, mop); | ||
209 | +} | ||
210 | + | ||
211 | +static void op_addr_ldstpair_post(DisasContext *s, arg_ldstpair *a, | ||
212 | + TCGv_i64 dirty_addr, uint64_t offset) | ||
252 | +{ | 213 | +{ |
253 | + int ret; | 214 | + if (a->w) { |
254 | + | 215 | + if (a->p) { |
255 | + trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr); | 216 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
256 | + | 217 | + } |
257 | + ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id)); | 218 | + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); |
258 | + if (!target_cpu) { | ||
259 | + /* | ||
260 | + * Called with a bogus value for cpu_id. Guest error will | ||
261 | + * already have been logged, we can simply return here. | ||
262 | + */ | ||
263 | + return; | ||
264 | + } | ||
265 | + bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64); | ||
266 | + | ||
267 | + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0, | ||
268 | + CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64); | ||
269 | + if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) { | ||
270 | + error_report("%s: failed to bring up CPU %d: err %d", | ||
271 | + __func__, cpu_id, ret); | ||
272 | + return; | ||
273 | + } | 219 | + } |
274 | +} | 220 | +} |
275 | + | 221 | + |
276 | +static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset, | 222 | +static bool trans_STP(DisasContext *s, arg_ldstpair *a) |
277 | + unsigned size) | ||
278 | +{ | 223 | +{ |
279 | + const AwCpuCfgState *s = AW_CPUCFG(opaque); | 224 | + uint64_t offset = a->imm << a->sz; |
280 | + uint64_t val = 0; | 225 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; |
281 | + | 226 | + MemOp mop = finalize_memop(s, a->sz); |
282 | + switch (offset) { | 227 | + |
283 | + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ | 228 | + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop); |
284 | + case REG_CPU_SYS_RST: /* CPU System Reset */ | 229 | + tcg_rt = cpu_reg(s, a->rt); |
285 | + val = CPU_SYS_RESET_RELEASED; | 230 | + tcg_rt2 = cpu_reg(s, a->rt2); |
286 | + break; | 231 | + /* |
287 | + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ | 232 | + * We built mop above for the single logical access -- rebuild it |
288 | + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ | 233 | + * now for the paired operation. |
289 | + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ | 234 | + * |
290 | + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ | 235 | + * With LSE2, non-sign-extending pairs are treated atomically if |
291 | + val = CPUX_RESET_RELEASED; | 236 | + * aligned, and if unaligned one of the pair will be completely |
292 | + break; | 237 | + * within a 16-byte block and that element will be atomic. |
293 | + case REG_CPU0_CTRL: /* CPU#0 Control */ | 238 | + * Otherwise each element is separately atomic. |
294 | + case REG_CPU1_CTRL: /* CPU#1 Control */ | 239 | + * In all cases, issue one operation with the correct atomicity. |
295 | + case REG_CPU2_CTRL: /* CPU#2 Control */ | 240 | + */ |
296 | + case REG_CPU3_CTRL: /* CPU#3 Control */ | 241 | + mop = a->sz + 1; |
297 | + val = 0; | 242 | + if (s->align_mem) { |
298 | + break; | 243 | + mop |= (a->sz == 2 ? MO_ALIGN_4 : MO_ALIGN_8); |
299 | + case REG_CPU0_STATUS: /* CPU#0 Status */ | 244 | + } |
300 | + case REG_CPU1_STATUS: /* CPU#1 Status */ | 245 | + mop = finalize_memop_pair(s, mop); |
301 | + case REG_CPU2_STATUS: /* CPU#2 Status */ | 246 | + if (a->sz == 2) { |
302 | + case REG_CPU3_STATUS: /* CPU#3 Status */ | 247 | + TCGv_i64 tmp = tcg_temp_new_i64(); |
303 | + val = CPUX_STATUS_SMP; | 248 | + |
304 | + break; | 249 | + if (s->be_data == MO_LE) { |
305 | + case REG_CLK_GATING: /* CPU Clock Gating */ | 250 | + tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); |
306 | + val = CLK_GATING_ENABLE; | 251 | + } else { |
307 | + break; | 252 | + tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); |
308 | + case REG_GEN_CTRL: /* General Control */ | 253 | + } |
309 | + val = s->gen_ctrl; | 254 | + tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop); |
310 | + break; | 255 | + } else { |
311 | + case REG_SUPER_STANDBY: /* Super Standby Flag */ | 256 | + TCGv_i128 tmp = tcg_temp_new_i128(); |
312 | + val = s->super_standby; | 257 | + |
313 | + break; | 258 | + if (s->be_data == MO_LE) { |
314 | + case REG_ENTRY_ADDR: /* Reset Entry Address */ | 259 | + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); |
315 | + val = s->entry_addr; | 260 | + } else { |
316 | + break; | 261 | + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); |
317 | + case REG_DBG_EXTERN: /* Debug External */ | 262 | + } |
318 | + case REG_CNT64_CTRL: /* 64-bit Counter Control */ | 263 | + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); |
319 | + case REG_CNT64_LOW: /* 64-bit Counter Low */ | 264 | + } |
320 | + case REG_CNT64_HIGH: /* 64-bit Counter High */ | 265 | + op_addr_ldstpair_post(s, a, dirty_addr, offset); |
321 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n", | 266 | + return true; |
322 | + __func__, (uint32_t)offset); | ||
323 | + break; | ||
324 | + default: | ||
325 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
326 | + __func__, (uint32_t)offset); | ||
327 | + break; | ||
328 | + } | ||
329 | + | ||
330 | + trace_allwinner_cpucfg_read(offset, val, size); | ||
331 | + | ||
332 | + return val; | ||
333 | +} | 267 | +} |
334 | + | 268 | + |
335 | +static void allwinner_cpucfg_write(void *opaque, hwaddr offset, | 269 | +static bool trans_LDP(DisasContext *s, arg_ldstpair *a) |
336 | + uint64_t val, unsigned size) | ||
337 | +{ | 270 | +{ |
338 | + AwCpuCfgState *s = AW_CPUCFG(opaque); | 271 | + uint64_t offset = a->imm << a->sz; |
339 | + | 272 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; |
340 | + trace_allwinner_cpucfg_write(offset, val, size); | 273 | + MemOp mop = finalize_memop(s, a->sz); |
341 | + | 274 | + |
342 | + switch (offset) { | 275 | + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mop); |
343 | + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ | 276 | + tcg_rt = cpu_reg(s, a->rt); |
344 | + case REG_CPU_SYS_RST: /* CPU System Reset */ | 277 | + tcg_rt2 = cpu_reg(s, a->rt2); |
345 | + break; | 278 | + |
346 | + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ | 279 | + /* |
347 | + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ | 280 | + * We built mop above for the single logical access -- rebuild it |
348 | + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ | 281 | + * now for the paired operation. |
349 | + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ | 282 | + * |
350 | + if (val) { | 283 | + * With LSE2, non-sign-extending pairs are treated atomically if |
351 | + allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6); | 284 | + * aligned, and if unaligned one of the pair will be completely |
285 | + * within a 16-byte block and that element will be atomic. | ||
286 | + * Otherwise each element is separately atomic. | ||
287 | + * In all cases, issue one operation with the correct atomicity. | ||
288 | + * | ||
289 | + * This treats sign-extending loads like zero-extending loads, | ||
290 | + * since that reuses the most code below. | ||
291 | + */ | ||
292 | + mop = a->sz + 1; | ||
293 | + if (s->align_mem) { | ||
294 | + mop |= (a->sz == 2 ? MO_ALIGN_4 : MO_ALIGN_8); | ||
295 | + } | ||
296 | + mop = finalize_memop_pair(s, mop); | ||
297 | + if (a->sz == 2) { | ||
298 | + int o2 = s->be_data == MO_LE ? 32 : 0; | ||
299 | + int o1 = o2 ^ 32; | ||
300 | + | ||
301 | + tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop); | ||
302 | + if (a->sign) { | ||
303 | + tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); | ||
304 | + tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); | ||
305 | + } else { | ||
306 | + tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); | ||
307 | + tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); | ||
352 | + } | 308 | + } |
353 | + break; | 309 | + } else { |
354 | + case REG_CPU0_CTRL: /* CPU#0 Control */ | 310 | + TCGv_i128 tmp = tcg_temp_new_i128(); |
355 | + case REG_CPU1_CTRL: /* CPU#1 Control */ | 311 | + |
356 | + case REG_CPU2_CTRL: /* CPU#2 Control */ | 312 | + tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop); |
357 | + case REG_CPU3_CTRL: /* CPU#3 Control */ | 313 | + if (s->be_data == MO_LE) { |
358 | + case REG_CPU0_STATUS: /* CPU#0 Status */ | 314 | + tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); |
359 | + case REG_CPU1_STATUS: /* CPU#1 Status */ | 315 | + } else { |
360 | + case REG_CPU2_STATUS: /* CPU#2 Status */ | 316 | + tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); |
361 | + case REG_CPU3_STATUS: /* CPU#3 Status */ | 317 | + } |
362 | + case REG_CLK_GATING: /* CPU Clock Gating */ | 318 | + } |
363 | + break; | 319 | + op_addr_ldstpair_post(s, a, dirty_addr, offset); |
364 | + case REG_GEN_CTRL: /* General Control */ | 320 | + return true; |
365 | + s->gen_ctrl = val; | ||
366 | + break; | ||
367 | + case REG_SUPER_STANDBY: /* Super Standby Flag */ | ||
368 | + s->super_standby = val; | ||
369 | + break; | ||
370 | + case REG_ENTRY_ADDR: /* Reset Entry Address */ | ||
371 | + s->entry_addr = val; | ||
372 | + break; | ||
373 | + case REG_DBG_EXTERN: /* Debug External */ | ||
374 | + case REG_CNT64_CTRL: /* 64-bit Counter Control */ | ||
375 | + case REG_CNT64_LOW: /* 64-bit Counter Low */ | ||
376 | + case REG_CNT64_HIGH: /* 64-bit Counter High */ | ||
377 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n", | ||
378 | + __func__, (uint32_t)offset); | ||
379 | + break; | ||
380 | + default: | ||
381 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
382 | + __func__, (uint32_t)offset); | ||
383 | + break; | ||
384 | + } | ||
385 | +} | 321 | +} |
386 | + | 322 | + |
387 | +static const MemoryRegionOps allwinner_cpucfg_ops = { | 323 | +static bool trans_STP_v(DisasContext *s, arg_ldstpair *a) |
388 | + .read = allwinner_cpucfg_read, | ||
389 | + .write = allwinner_cpucfg_write, | ||
390 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
391 | + .valid = { | ||
392 | + .min_access_size = 4, | ||
393 | + .max_access_size = 4, | ||
394 | + }, | ||
395 | + .impl.min_access_size = 4, | ||
396 | +}; | ||
397 | + | ||
398 | +static void allwinner_cpucfg_reset(DeviceState *dev) | ||
399 | +{ | 324 | +{ |
400 | + AwCpuCfgState *s = AW_CPUCFG(dev); | 325 | + uint64_t offset = a->imm << a->sz; |
401 | + | 326 | + TCGv_i64 clean_addr, dirty_addr; |
402 | + /* Set default values for registers */ | 327 | + MemOp mop; |
403 | + s->gen_ctrl = REG_GEN_CTRL_RST; | 328 | + |
404 | + s->super_standby = REG_SUPER_STANDBY_RST; | 329 | + if (!fp_access_check(s)) { |
405 | + s->entry_addr = 0; | 330 | + return true; |
331 | + } | ||
332 | + | ||
333 | + /* LSE2 does not merge FP pairs; leave these as separate operations. */ | ||
334 | + mop = finalize_memop_asimd(s, a->sz); | ||
335 | + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop); | ||
336 | + do_fp_st(s, a->rt, clean_addr, mop); | ||
337 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); | ||
338 | + do_fp_st(s, a->rt2, clean_addr, mop); | ||
339 | + op_addr_ldstpair_post(s, a, dirty_addr, offset); | ||
340 | + return true; | ||
406 | +} | 341 | +} |
407 | + | 342 | + |
408 | +static void allwinner_cpucfg_init(Object *obj) | 343 | +static bool trans_LDP_v(DisasContext *s, arg_ldstpair *a) |
409 | +{ | 344 | +{ |
410 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 345 | + uint64_t offset = a->imm << a->sz; |
411 | + AwCpuCfgState *s = AW_CPUCFG(obj); | 346 | + TCGv_i64 clean_addr, dirty_addr; |
412 | + | 347 | + MemOp mop; |
413 | + /* Memory mapping */ | 348 | + |
414 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s, | 349 | + if (!fp_access_check(s)) { |
415 | + TYPE_AW_CPUCFG, 1 * KiB); | 350 | + return true; |
416 | + sysbus_init_mmio(sbd, &s->iomem); | 351 | + } |
352 | + | ||
353 | + /* LSE2 does not merge FP pairs; leave these as separate operations. */ | ||
354 | + mop = finalize_memop_asimd(s, a->sz); | ||
355 | + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mop); | ||
356 | + do_fp_ld(s, a->rt, clean_addr, mop); | ||
357 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); | ||
358 | + do_fp_ld(s, a->rt2, clean_addr, mop); | ||
359 | + op_addr_ldstpair_post(s, a, dirty_addr, offset); | ||
360 | + return true; | ||
417 | +} | 361 | +} |
418 | + | 362 | + |
419 | +static const VMStateDescription allwinner_cpucfg_vmstate = { | 363 | +static bool trans_STGP(DisasContext *s, arg_ldstpair *a) |
420 | + .name = "allwinner-cpucfg", | ||
421 | + .version_id = 1, | ||
422 | + .minimum_version_id = 1, | ||
423 | + .fields = (VMStateField[]) { | ||
424 | + VMSTATE_UINT32(gen_ctrl, AwCpuCfgState), | ||
425 | + VMSTATE_UINT32(super_standby, AwCpuCfgState), | ||
426 | + VMSTATE_UINT32(entry_addr, AwCpuCfgState), | ||
427 | + VMSTATE_END_OF_LIST() | ||
428 | + } | ||
429 | +}; | ||
430 | + | ||
431 | +static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data) | ||
432 | +{ | 364 | +{ |
433 | + DeviceClass *dc = DEVICE_CLASS(klass); | 365 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; |
434 | + | 366 | + uint64_t offset = a->imm << LOG2_TAG_GRANULE; |
435 | + dc->reset = allwinner_cpucfg_reset; | 367 | + MemOp mop; |
436 | + dc->vmsd = &allwinner_cpucfg_vmstate; | 368 | + TCGv_i128 tmp; |
437 | +} | 369 | + |
438 | + | 370 | + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { |
439 | +static const TypeInfo allwinner_cpucfg_info = { | 371 | + return false; |
440 | + .name = TYPE_AW_CPUCFG, | 372 | + } |
441 | + .parent = TYPE_SYS_BUS_DEVICE, | 373 | + |
442 | + .instance_init = allwinner_cpucfg_init, | 374 | + if (a->rn == 31) { |
443 | + .instance_size = sizeof(AwCpuCfgState), | 375 | + gen_check_sp_alignment(s); |
444 | + .class_init = allwinner_cpucfg_class_init, | 376 | + } |
445 | +}; | 377 | + |
446 | + | 378 | + dirty_addr = read_cpu_reg_sp(s, a->rn, 1); |
447 | +static void allwinner_cpucfg_register(void) | 379 | + if (!a->p) { |
448 | +{ | 380 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
449 | + type_register_static(&allwinner_cpucfg_info); | 381 | } |
450 | +} | 382 | |
451 | + | 383 | - if (set_tag) { |
452 | +type_init(allwinner_cpucfg_register) | 384 | - if (!s->ata) { |
453 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | 385 | - /* |
454 | index XXXXXXX..XXXXXXX 100644 | 386 | - * TODO: We could rely on the stores below, at least for |
455 | --- a/hw/misc/trace-events | 387 | - * system mode, if we arrange to add MO_ALIGN_16. |
456 | +++ b/hw/misc/trace-events | 388 | - */ |
457 | @@ -XXX,XX +XXX,XX @@ | 389 | - gen_helper_stg_stub(cpu_env, dirty_addr); |
458 | # See docs/devel/tracing.txt for syntax documentation. | 390 | - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { |
459 | 391 | - gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); | |
460 | +# allwinner-cpucfg.c | 392 | - } else { |
461 | +allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32 | 393 | - gen_helper_stg(cpu_env, dirty_addr, dirty_addr); |
462 | +allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | 394 | - } |
463 | +allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | 395 | - } |
464 | + | 396 | - |
465 | # eccmemctl.c | 397 | - if (is_vector) { |
466 | ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" | 398 | - mop = finalize_memop_asimd(s, size); |
467 | ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" | 399 | - } else { |
400 | - mop = finalize_memop(s, size); | ||
401 | - } | ||
402 | - clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, | ||
403 | - (wback || rn != 31) && !set_tag, | ||
404 | - 2 << size, mop); | ||
405 | - | ||
406 | - if (is_vector) { | ||
407 | - /* LSE2 does not merge FP pairs; leave these as separate operations. */ | ||
408 | - if (is_load) { | ||
409 | - do_fp_ld(s, rt, clean_addr, mop); | ||
410 | - } else { | ||
411 | - do_fp_st(s, rt, clean_addr, mop); | ||
412 | - } | ||
413 | - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
414 | - if (is_load) { | ||
415 | - do_fp_ld(s, rt2, clean_addr, mop); | ||
416 | - } else { | ||
417 | - do_fp_st(s, rt2, clean_addr, mop); | ||
418 | - } | ||
419 | - } else { | ||
420 | - TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
421 | - TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); | ||
422 | - | ||
423 | + if (!s->ata) { | ||
424 | /* | ||
425 | - * We built mop above for the single logical access -- rebuild it | ||
426 | - * now for the paired operation. | ||
427 | - * | ||
428 | - * With LSE2, non-sign-extending pairs are treated atomically if | ||
429 | - * aligned, and if unaligned one of the pair will be completely | ||
430 | - * within a 16-byte block and that element will be atomic. | ||
431 | - * Otherwise each element is separately atomic. | ||
432 | - * In all cases, issue one operation with the correct atomicity. | ||
433 | - * | ||
434 | - * This treats sign-extending loads like zero-extending loads, | ||
435 | - * since that reuses the most code below. | ||
436 | + * TODO: We could rely on the stores below, at least for | ||
437 | + * system mode, if we arrange to add MO_ALIGN_16. | ||
438 | */ | ||
439 | - mop = size + 1; | ||
440 | - if (s->align_mem) { | ||
441 | - mop |= (size == 2 ? MO_ALIGN_4 : MO_ALIGN_8); | ||
442 | - } | ||
443 | - mop = finalize_memop_pair(s, mop); | ||
444 | - | ||
445 | - if (is_load) { | ||
446 | - if (size == 2) { | ||
447 | - int o2 = s->be_data == MO_LE ? 32 : 0; | ||
448 | - int o1 = o2 ^ 32; | ||
449 | - | ||
450 | - tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop); | ||
451 | - if (is_signed) { | ||
452 | - tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); | ||
453 | - tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); | ||
454 | - } else { | ||
455 | - tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); | ||
456 | - tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); | ||
457 | - } | ||
458 | - } else { | ||
459 | - TCGv_i128 tmp = tcg_temp_new_i128(); | ||
460 | - | ||
461 | - tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop); | ||
462 | - if (s->be_data == MO_LE) { | ||
463 | - tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); | ||
464 | - } else { | ||
465 | - tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); | ||
466 | - } | ||
467 | - } | ||
468 | - } else { | ||
469 | - if (size == 2) { | ||
470 | - TCGv_i64 tmp = tcg_temp_new_i64(); | ||
471 | - | ||
472 | - if (s->be_data == MO_LE) { | ||
473 | - tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); | ||
474 | - } else { | ||
475 | - tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); | ||
476 | - } | ||
477 | - tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop); | ||
478 | - } else { | ||
479 | - TCGv_i128 tmp = tcg_temp_new_i128(); | ||
480 | - | ||
481 | - if (s->be_data == MO_LE) { | ||
482 | - tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); | ||
483 | - } else { | ||
484 | - tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); | ||
485 | - } | ||
486 | - tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); | ||
487 | - } | ||
488 | - } | ||
489 | + gen_helper_stg_stub(cpu_env, dirty_addr); | ||
490 | + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | ||
491 | + gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); | ||
492 | + } else { | ||
493 | + gen_helper_stg(cpu_env, dirty_addr, dirty_addr); | ||
494 | } | ||
495 | |||
496 | - if (wback) { | ||
497 | - if (postindex) { | ||
498 | - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
499 | - } | ||
500 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); | ||
501 | + mop = finalize_memop(s, a->sz); | ||
502 | + clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, mop); | ||
503 | + | ||
504 | + tcg_rt = cpu_reg(s, a->rt); | ||
505 | + tcg_rt2 = cpu_reg(s, a->rt2); | ||
506 | + | ||
507 | + assert(a->sz == 3); | ||
508 | + | ||
509 | + tmp = tcg_temp_new_i128(); | ||
510 | + if (s->be_data == MO_LE) { | ||
511 | + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); | ||
512 | + } else { | ||
513 | + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); | ||
514 | } | ||
515 | + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); | ||
516 | + | ||
517 | + op_addr_ldstpair_post(s, a, dirty_addr, offset); | ||
518 | + return true; | ||
519 | } | ||
520 | |||
521 | /* | ||
522 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
523 | static void disas_ldst(DisasContext *s, uint32_t insn) | ||
524 | { | ||
525 | switch (extract32(insn, 24, 6)) { | ||
526 | - case 0x28: case 0x29: | ||
527 | - case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | ||
528 | - disas_ldst_pair(s, insn); | ||
529 | - break; | ||
530 | case 0x38: case 0x39: | ||
531 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | ||
532 | disas_ldst_reg(s, insn); | ||
468 | -- | 533 | -- |
469 | 2.20.1 | 534 | 2.34.1 |
470 | |||
471 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | Convert the load and store instructions which use a 9-bit |
---|---|---|---|
2 | immediate offset to decodetree. | ||
2 | 3 | ||
3 | Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | provided on the command line to available eSDHC controllers. | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/tcg/a64.decode | 69 +++++++++++ | ||
9 | target/arm/tcg/translate-a64.c | 206 ++++++++++++++------------------- | ||
10 | 2 files changed, 153 insertions(+), 122 deletions(-) | ||
5 | 11 | ||
6 | This patch enables booting the imx25-pdk emulation from SD card. | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
7 | |||
8 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
9 | Message-id: 20200310215146.19688-2-linux@roeck-us.net | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | [PMM: made commit subject consistent with other patch] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/arm/fsl-imx25.h | 9 +++++++++ | ||
15 | hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++ | ||
16 | hw/arm/imx25_pdk.c | 16 ++++++++++++++++ | ||
17 | 3 files changed, 57 insertions(+) | ||
18 | |||
19 | diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/arm/fsl-imx25.h | 14 | --- a/target/arm/tcg/a64.decode |
22 | +++ b/include/hw/arm/fsl-imx25.h | 15 | +++ b/target/arm/tcg/a64.decode |
23 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p |
24 | #include "hw/misc/imx_rngc.h" | 17 | STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 |
25 | #include "hw/i2c/imx_i2c.h" | 18 | STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 |
26 | #include "hw/gpio/imx_gpio.h" | 19 | STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 |
27 | +#include "hw/sd/sdhci.h" | 20 | + |
28 | #include "exec/memory.h" | 21 | +# Load/store register (unscaled immediate) |
29 | #include "target/arm/cpu.h" | 22 | +&ldst_imm rt rn imm sz sign w p unpriv ext |
30 | 23 | +@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 | |
31 | @@ -XXX,XX +XXX,XX @@ | 24 | +@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 |
32 | #define FSL_IMX25_NUM_EPITS 2 | 25 | +@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 |
33 | #define FSL_IMX25_NUM_I2CS 3 | 26 | +@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 |
34 | #define FSL_IMX25_NUM_GPIOS 4 | 27 | + |
35 | +#define FSL_IMX25_NUM_ESDHCS 2 | 28 | +STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 |
36 | 29 | +LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 | |
37 | typedef struct FslIMX25State { | 30 | +LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 |
38 | /*< private >*/ | 31 | +LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 |
39 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | 32 | +LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 |
40 | IMXRNGCState rngc; | 33 | +LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 |
41 | IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; | 34 | +LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 |
42 | IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; | 35 | +LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 |
43 | + SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS]; | 36 | +LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 |
44 | MemoryRegion rom[2]; | 37 | +LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 |
45 | MemoryRegion iram; | 38 | + |
46 | MemoryRegion iram_alias; | 39 | +STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 |
47 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | 40 | +LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 |
48 | #define FSL_IMX25_GPIO3_SIZE 0x4000 | 41 | +LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 |
49 | #define FSL_IMX25_RNGC_ADDR 0x53FB0000 | 42 | +LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 |
50 | #define FSL_IMX25_RNGC_SIZE 0x4000 | 43 | +LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 |
51 | +#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000 | 44 | +LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 |
52 | +#define FSL_IMX25_ESDHC1_SIZE 0x4000 | 45 | +LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 |
53 | +#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000 | 46 | +LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 |
54 | +#define FSL_IMX25_ESDHC2_SIZE 0x4000 | 47 | +LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 |
55 | #define FSL_IMX25_GPIO1_ADDR 0x53FCC000 | 48 | +LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 |
56 | #define FSL_IMX25_GPIO1_SIZE 0x4000 | 49 | + |
57 | #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 | 50 | +STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 |
58 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | 51 | +LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 |
59 | #define FSL_IMX25_GPIO2_IRQ 51 | 52 | +LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 |
60 | #define FSL_IMX25_GPIO3_IRQ 16 | 53 | +LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 |
61 | #define FSL_IMX25_GPIO4_IRQ 23 | 54 | +LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 |
62 | +#define FSL_IMX25_ESDHC1_IRQ 9 | 55 | +LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 |
63 | +#define FSL_IMX25_ESDHC2_IRQ 8 | 56 | +LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 |
64 | 57 | +LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 | |
65 | #endif /* FSL_IMX25_H */ | 58 | +LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 |
66 | diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c | 59 | +LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 |
60 | + | ||
61 | +STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 | ||
62 | +LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 | ||
63 | +LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 | ||
64 | +LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 | ||
65 | +LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 | ||
66 | +LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 | ||
67 | +LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 | ||
68 | +LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 | ||
69 | +LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 | ||
70 | +LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 | ||
71 | + | ||
72 | +# PRFM : prefetch memory: a no-op for QEMU | ||
73 | +NOP 11 111 0 00 10 0 --------- 00 ----- ----- | ||
74 | + | ||
75 | +STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 | ||
76 | +STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 | ||
77 | +LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 | ||
78 | +LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 | ||
79 | + | ||
80 | +STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 | ||
81 | +STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 | ||
82 | +LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 | ||
83 | +LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 | ||
84 | + | ||
85 | +STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 | ||
86 | +STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 | ||
87 | +LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 | ||
88 | +LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 | ||
89 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | 90 | index XXXXXXX..XXXXXXX 100644 |
68 | --- a/hw/arm/fsl-imx25.c | 91 | --- a/target/arm/tcg/translate-a64.c |
69 | +++ b/hw/arm/fsl-imx25.c | 92 | +++ b/target/arm/tcg/translate-a64.c |
70 | @@ -XXX,XX +XXX,XX @@ | 93 | @@ -XXX,XX +XXX,XX @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a) |
71 | #include "hw/qdev-properties.h" | 94 | return true; |
72 | #include "chardev/char.h" | 95 | } |
73 | 96 | ||
74 | +#define IMX25_ESDHC_CAPABILITIES 0x07e20000 | 97 | -/* |
75 | + | 98 | - * Load/store (immediate post-indexed) |
76 | static void fsl_imx25_init(Object *obj) | 99 | - * Load/store (immediate pre-indexed) |
100 | - * Load/store (unscaled immediate) | ||
101 | - * | ||
102 | - * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | ||
103 | - * +----+-------+---+-----+-----+---+--------+-----+------+------+ | ||
104 | - * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | ||
105 | - * +----+-------+---+-----+-----+---+--------+-----+------+------+ | ||
106 | - * | ||
107 | - * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | ||
108 | - 10 -> unprivileged | ||
109 | - * V = 0 -> non-vector | ||
110 | - * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | ||
111 | - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | ||
112 | - */ | ||
113 | -static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
114 | - int opc, | ||
115 | - int size, | ||
116 | - int rt, | ||
117 | - bool is_vector) | ||
118 | +static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a, | ||
119 | + TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr, | ||
120 | + uint64_t offset, bool is_store, MemOp mop) | ||
77 | { | 121 | { |
78 | FslIMX25State *s = FSL_IMX25(obj); | 122 | - int rn = extract32(insn, 5, 5); |
79 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj) | 123 | - int imm9 = sextract32(insn, 12, 9); |
80 | sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), | 124 | - int idx = extract32(insn, 10, 2); |
81 | TYPE_IMX_GPIO); | 125 | - bool is_signed = false; |
126 | - bool is_store = false; | ||
127 | - bool is_extended = false; | ||
128 | - bool is_unpriv = (idx == 2); | ||
129 | - bool iss_valid; | ||
130 | - bool post_index; | ||
131 | - bool writeback; | ||
132 | int memidx; | ||
133 | - MemOp memop; | ||
134 | - TCGv_i64 clean_addr, dirty_addr; | ||
135 | |||
136 | - if (is_vector) { | ||
137 | - size |= (opc & 2) << 1; | ||
138 | - if (size > 4 || is_unpriv) { | ||
139 | - unallocated_encoding(s); | ||
140 | - return; | ||
141 | - } | ||
142 | - is_store = ((opc & 1) == 0); | ||
143 | - if (!fp_access_check(s)) { | ||
144 | - return; | ||
145 | - } | ||
146 | - memop = finalize_memop_asimd(s, size); | ||
147 | - } else { | ||
148 | - if (size == 3 && opc == 2) { | ||
149 | - /* PRFM - prefetch */ | ||
150 | - if (idx != 0) { | ||
151 | - unallocated_encoding(s); | ||
152 | - return; | ||
153 | - } | ||
154 | - return; | ||
155 | - } | ||
156 | - if (opc == 3 && size > 1) { | ||
157 | - unallocated_encoding(s); | ||
158 | - return; | ||
159 | - } | ||
160 | - is_store = (opc == 0); | ||
161 | - is_signed = !is_store && extract32(opc, 1, 1); | ||
162 | - is_extended = (size < 3) && extract32(opc, 0, 1); | ||
163 | - memop = finalize_memop(s, size + is_signed * MO_SIGN); | ||
164 | - } | ||
165 | - | ||
166 | - switch (idx) { | ||
167 | - case 0: | ||
168 | - case 2: | ||
169 | - post_index = false; | ||
170 | - writeback = false; | ||
171 | - break; | ||
172 | - case 1: | ||
173 | - post_index = true; | ||
174 | - writeback = true; | ||
175 | - break; | ||
176 | - case 3: | ||
177 | - post_index = false; | ||
178 | - writeback = true; | ||
179 | - break; | ||
180 | - default: | ||
181 | - g_assert_not_reached(); | ||
182 | - } | ||
183 | - | ||
184 | - iss_valid = !is_vector && !writeback; | ||
185 | - | ||
186 | - if (rn == 31) { | ||
187 | + if (a->rn == 31) { | ||
188 | gen_check_sp_alignment(s); | ||
82 | } | 189 | } |
83 | + | 190 | |
84 | + for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { | 191 | - dirty_addr = read_cpu_reg_sp(s, rn, 1); |
85 | + sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]), | 192 | - if (!post_index) { |
86 | + TYPE_IMX_USDHC); | 193 | - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
194 | + *dirty_addr = read_cpu_reg_sp(s, a->rn, 1); | ||
195 | + if (!a->p) { | ||
196 | + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); | ||
197 | } | ||
198 | + memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | ||
199 | + *clean_addr = gen_mte_check1_mmuidx(s, *dirty_addr, is_store, | ||
200 | + a->w || a->rn != 31, | ||
201 | + mop, a->unpriv, memidx); | ||
202 | +} | ||
203 | |||
204 | - memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | ||
205 | - | ||
206 | - clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store, | ||
207 | - writeback || rn != 31, | ||
208 | - memop, is_unpriv, memidx); | ||
209 | - | ||
210 | - if (is_vector) { | ||
211 | - if (is_store) { | ||
212 | - do_fp_st(s, rt, clean_addr, memop); | ||
213 | - } else { | ||
214 | - do_fp_ld(s, rt, clean_addr, memop); | ||
215 | - } | ||
216 | - } else { | ||
217 | - TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
218 | - bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
219 | - | ||
220 | - if (is_store) { | ||
221 | - do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, | ||
222 | - iss_valid, rt, iss_sf, false); | ||
223 | - } else { | ||
224 | - do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, | ||
225 | - is_extended, memidx, | ||
226 | - iss_valid, rt, iss_sf, false); | ||
227 | +static void op_addr_ldst_imm_post(DisasContext *s, arg_ldst_imm *a, | ||
228 | + TCGv_i64 dirty_addr, uint64_t offset) | ||
229 | +{ | ||
230 | + if (a->w) { | ||
231 | + if (a->p) { | ||
232 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
233 | } | ||
234 | + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); | ||
235 | } | ||
236 | +} | ||
237 | |||
238 | - if (writeback) { | ||
239 | - TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | ||
240 | - if (post_index) { | ||
241 | - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); | ||
242 | - } | ||
243 | - tcg_gen_mov_i64(tcg_rn, dirty_addr); | ||
244 | +static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a) | ||
245 | +{ | ||
246 | + bool iss_sf, iss_valid = !a->w; | ||
247 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
248 | + int memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | ||
249 | + MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN); | ||
250 | + | ||
251 | + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop); | ||
252 | + | ||
253 | + tcg_rt = cpu_reg(s, a->rt); | ||
254 | + iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext); | ||
255 | + | ||
256 | + do_gpr_st_memidx(s, tcg_rt, clean_addr, mop, memidx, | ||
257 | + iss_valid, a->rt, iss_sf, false); | ||
258 | + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); | ||
259 | + return true; | ||
260 | +} | ||
261 | + | ||
262 | +static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a) | ||
263 | +{ | ||
264 | + bool iss_sf, iss_valid = !a->w; | ||
265 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
266 | + int memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | ||
267 | + MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN); | ||
268 | + | ||
269 | + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mop); | ||
270 | + | ||
271 | + tcg_rt = cpu_reg(s, a->rt); | ||
272 | + iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext); | ||
273 | + | ||
274 | + do_gpr_ld_memidx(s, tcg_rt, clean_addr, mop, | ||
275 | + a->ext, memidx, iss_valid, a->rt, iss_sf, false); | ||
276 | + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); | ||
277 | + return true; | ||
278 | +} | ||
279 | + | ||
280 | +static bool trans_STR_v_i(DisasContext *s, arg_ldst_imm *a) | ||
281 | +{ | ||
282 | + TCGv_i64 clean_addr, dirty_addr; | ||
283 | + MemOp mop; | ||
284 | + | ||
285 | + if (!fp_access_check(s)) { | ||
286 | + return true; | ||
287 | } | ||
288 | + mop = finalize_memop_asimd(s, a->sz); | ||
289 | + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop); | ||
290 | + do_fp_st(s, a->rt, clean_addr, mop); | ||
291 | + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); | ||
292 | + return true; | ||
293 | +} | ||
294 | + | ||
295 | +static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a) | ||
296 | +{ | ||
297 | + TCGv_i64 clean_addr, dirty_addr; | ||
298 | + MemOp mop; | ||
299 | + | ||
300 | + if (!fp_access_check(s)) { | ||
301 | + return true; | ||
87 | + } | 302 | + } |
303 | + mop = finalize_memop_asimd(s, a->sz); | ||
304 | + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mop); | ||
305 | + do_fp_ld(s, a->rt, clean_addr, mop); | ||
306 | + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); | ||
307 | + return true; | ||
88 | } | 308 | } |
89 | 309 | ||
90 | static void fsl_imx25_realize(DeviceState *dev, Error **errp) | 310 | /* |
91 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) | 311 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
92 | gpio_table[i].irq)); | 312 | switch (extract32(insn, 24, 2)) { |
93 | } | 313 | case 0: |
94 | 314 | if (extract32(insn, 21, 1) == 0) { | |
95 | + /* Initialize all SDHC */ | 315 | - /* Load/store register (unscaled immediate) |
96 | + for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { | 316 | - * Load/store immediate pre/post-indexed |
97 | + static const struct { | 317 | - * Load/store register unprivileged |
98 | + hwaddr addr; | 318 | - */ |
99 | + unsigned int irq; | 319 | - disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
100 | + } esdhc_table[FSL_IMX25_NUM_ESDHCS] = { | 320 | - return; |
101 | + { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ }, | 321 | + break; |
102 | + { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, | 322 | } |
103 | + }; | 323 | switch (extract32(insn, 10, 2)) { |
104 | + | 324 | case 0: |
105 | + object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version", | ||
106 | + &err); | ||
107 | + object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, | ||
108 | + "capareg", &err); | ||
109 | + object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); | ||
110 | + if (err) { | ||
111 | + error_propagate(errp, err); | ||
112 | + return; | ||
113 | + } | ||
114 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); | ||
115 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, | ||
116 | + qdev_get_gpio_in(DEVICE(&s->avic), | ||
117 | + esdhc_table[i].irq)); | ||
118 | + } | ||
119 | + | ||
120 | /* initialize 2 x 16 KB ROM */ | ||
121 | memory_region_init_rom(&s->rom[0], NULL, | ||
122 | "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); | ||
123 | diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c | ||
124 | index XXXXXXX..XXXXXXX 100644 | ||
125 | --- a/hw/arm/imx25_pdk.c | ||
126 | +++ b/hw/arm/imx25_pdk.c | ||
127 | @@ -XXX,XX +XXX,XX @@ | ||
128 | #include "qemu/osdep.h" | ||
129 | #include "qapi/error.h" | ||
130 | #include "cpu.h" | ||
131 | +#include "hw/qdev-properties.h" | ||
132 | #include "hw/arm/fsl-imx25.h" | ||
133 | #include "hw/boards.h" | ||
134 | #include "qemu/error-report.h" | ||
135 | @@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine) | ||
136 | imx25_pdk_binfo.board_id = 1771, | ||
137 | imx25_pdk_binfo.nb_cpus = 1; | ||
138 | |||
139 | + for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { | ||
140 | + BusState *bus; | ||
141 | + DeviceState *carddev; | ||
142 | + DriveInfo *di; | ||
143 | + BlockBackend *blk; | ||
144 | + | ||
145 | + di = drive_get_next(IF_SD); | ||
146 | + blk = di ? blk_by_legacy_dinfo(di) : NULL; | ||
147 | + bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus"); | ||
148 | + carddev = qdev_create(bus, TYPE_SD_CARD); | ||
149 | + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | ||
150 | + object_property_set_bool(OBJECT(carddev), true, | ||
151 | + "realized", &error_fatal); | ||
152 | + } | ||
153 | + | ||
154 | /* | ||
155 | * We test explicitly for qtest here as it is not done (yet?) in | ||
156 | * arm_load_kernel(). Without this the "make check" command would | ||
157 | -- | 325 | -- |
158 | 2.20.1 | 326 | 2.34.1 |
159 | |||
160 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert the LDR and STR instructions which use a 12-bit immediate |
---|---|---|---|
2 | offset to decodetree. We can reuse the existing LDR and STR | ||
3 | trans functions for these. | ||
2 | 4 | ||
3 | The Allwinner H3 is a System on Chip containing four ARM Cortex A7 | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | processor cores. Features and specifications include DDR2/DDR3 memory, | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and | 7 | Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org |
6 | various I/O modules. This commit adds support for the Allwinner H3 | 8 | --- |
7 | System on Chip. | 9 | target/arm/tcg/a64.decode | 25 ++++++++ |
10 | target/arm/tcg/translate-a64.c | 104 +++++---------------------------- | ||
11 | 2 files changed, 41 insertions(+), 88 deletions(-) | ||
8 | 12 | ||
9 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
11 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
12 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/arm/Makefile.objs | 1 + | ||
17 | include/hw/arm/allwinner-h3.h | 106 +++++++++++ | ||
18 | hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++ | ||
19 | MAINTAINERS | 7 + | ||
20 | default-configs/arm-softmmu.mak | 1 + | ||
21 | hw/arm/Kconfig | 8 + | ||
22 | 6 files changed, 450 insertions(+) | ||
23 | create mode 100644 include/hw/arm/allwinner-h3.h | ||
24 | create mode 100644 hw/arm/allwinner-h3.c | ||
25 | |||
26 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
27 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/arm/Makefile.objs | 15 | --- a/target/arm/tcg/a64.decode |
29 | +++ b/hw/arm/Makefile.objs | 16 | +++ b/target/arm/tcg/a64.decode |
30 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o | 17 | @@ -XXX,XX +XXX,XX @@ STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 |
31 | obj-$(CONFIG_OMAP) += omap1.o omap2.o | 18 | STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 |
32 | obj-$(CONFIG_STRONGARM) += strongarm.o | 19 | LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 |
33 | obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o | 20 | LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 |
34 | +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o | 21 | + |
35 | obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o | 22 | +# Load/store with an unsigned 12 bit immediate, which is scaled by the |
36 | obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o | 23 | +# element size. The function gets the sz:imm and returns the scaled immediate. |
37 | obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o | 24 | +%uimm_scaled 10:12 sz:3 !function=uimm_scaled |
38 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 25 | + |
39 | new file mode 100644 | 26 | +@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled |
40 | index XXXXXXX..XXXXXXX | 27 | + |
41 | --- /dev/null | 28 | +STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 |
42 | +++ b/include/hw/arm/allwinner-h3.h | 29 | +LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 |
43 | @@ -XXX,XX +XXX,XX @@ | 30 | +LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 |
31 | +LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 | ||
32 | +LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 | ||
33 | +LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 | ||
34 | +LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 | ||
35 | +LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 | ||
36 | +LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 | ||
37 | +LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 | ||
38 | + | ||
39 | +# PRFM | ||
40 | +NOP 11 111 0 01 10 ------------ ----- ----- | ||
41 | + | ||
42 | +STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 | ||
43 | +STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 | ||
44 | +LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 | ||
45 | +LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 | ||
46 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/tcg/translate-a64.c | ||
49 | +++ b/target/arm/tcg/translate-a64.c | ||
50 | @@ -XXX,XX +XXX,XX @@ enum a64_shift_type { | ||
51 | A64_SHIFT_TYPE_ROR = 3 | ||
52 | }; | ||
53 | |||
44 | +/* | 54 | +/* |
45 | + * Allwinner H3 System on Chip emulation | 55 | + * Helpers for extracting complex instruction fields |
46 | + * | ||
47 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
48 | + * | ||
49 | + * This program is free software: you can redistribute it and/or modify | ||
50 | + * it under the terms of the GNU General Public License as published by | ||
51 | + * the Free Software Foundation, either version 2 of the License, or | ||
52 | + * (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
61 | + */ | 56 | + */ |
62 | + | 57 | + |
63 | +/* | 58 | +/* |
64 | + * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 | 59 | + * For load/store with an unsigned 12 bit immediate scaled by the element |
65 | + * processor cores. Features and specifications include DDR2/DDR3 memory, | 60 | + * size. The input has the immediate field in bits [14:3] and the element |
66 | + * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and | 61 | + * size in [2:0]. |
67 | + * various I/O modules. | ||
68 | + * | ||
69 | + * This implementation is based on the following datasheet: | ||
70 | + * | ||
71 | + * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf | ||
72 | + * | ||
73 | + * The latest datasheet and more info can be found on the Linux Sunxi wiki: | ||
74 | + * | ||
75 | + * https://linux-sunxi.org/H3 | ||
76 | + */ | 62 | + */ |
77 | + | 63 | +static int uimm_scaled(DisasContext *s, int x) |
78 | +#ifndef HW_ARM_ALLWINNER_H3_H | ||
79 | +#define HW_ARM_ALLWINNER_H3_H | ||
80 | + | ||
81 | +#include "qom/object.h" | ||
82 | +#include "hw/arm/boot.h" | ||
83 | +#include "hw/timer/allwinner-a10-pit.h" | ||
84 | +#include "hw/intc/arm_gic.h" | ||
85 | +#include "target/arm/cpu.h" | ||
86 | + | ||
87 | +/** | ||
88 | + * Allwinner H3 device list | ||
89 | + * | ||
90 | + * This enumeration is can be used refer to a particular device in the | ||
91 | + * Allwinner H3 SoC. For example, the physical memory base address for | ||
92 | + * each device can be found in the AwH3State object in the memmap member | ||
93 | + * using the device enum value as index. | ||
94 | + * | ||
95 | + * @see AwH3State | ||
96 | + */ | ||
97 | +enum { | ||
98 | + AW_H3_SRAM_A1, | ||
99 | + AW_H3_SRAM_A2, | ||
100 | + AW_H3_SRAM_C, | ||
101 | + AW_H3_PIT, | ||
102 | + AW_H3_UART0, | ||
103 | + AW_H3_UART1, | ||
104 | + AW_H3_UART2, | ||
105 | + AW_H3_UART3, | ||
106 | + AW_H3_GIC_DIST, | ||
107 | + AW_H3_GIC_CPU, | ||
108 | + AW_H3_GIC_HYP, | ||
109 | + AW_H3_GIC_VCPU, | ||
110 | + AW_H3_SDRAM | ||
111 | +}; | ||
112 | + | ||
113 | +/** Total number of CPU cores in the H3 SoC */ | ||
114 | +#define AW_H3_NUM_CPUS (4) | ||
115 | + | ||
116 | +/** | ||
117 | + * Allwinner H3 object model | ||
118 | + * @{ | ||
119 | + */ | ||
120 | + | ||
121 | +/** Object type for the Allwinner H3 SoC */ | ||
122 | +#define TYPE_AW_H3 "allwinner-h3" | ||
123 | + | ||
124 | +/** Convert input object to Allwinner H3 state object */ | ||
125 | +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) | ||
126 | + | ||
127 | +/** @} */ | ||
128 | + | ||
129 | +/** | ||
130 | + * Allwinner H3 object | ||
131 | + * | ||
132 | + * This struct contains the state of all the devices | ||
133 | + * which are currently emulated by the H3 SoC code. | ||
134 | + */ | ||
135 | +typedef struct AwH3State { | ||
136 | + /*< private >*/ | ||
137 | + DeviceState parent_obj; | ||
138 | + /*< public >*/ | ||
139 | + | ||
140 | + ARMCPU cpus[AW_H3_NUM_CPUS]; | ||
141 | + const hwaddr *memmap; | ||
142 | + AwA10PITState timer; | ||
143 | + GICState gic; | ||
144 | + MemoryRegion sram_a1; | ||
145 | + MemoryRegion sram_a2; | ||
146 | + MemoryRegion sram_c; | ||
147 | +} AwH3State; | ||
148 | + | ||
149 | +#endif /* HW_ARM_ALLWINNER_H3_H */ | ||
150 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
151 | new file mode 100644 | ||
152 | index XXXXXXX..XXXXXXX | ||
153 | --- /dev/null | ||
154 | +++ b/hw/arm/allwinner-h3.c | ||
155 | @@ -XXX,XX +XXX,XX @@ | ||
156 | +/* | ||
157 | + * Allwinner H3 System on Chip emulation | ||
158 | + * | ||
159 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
160 | + * | ||
161 | + * This program is free software: you can redistribute it and/or modify | ||
162 | + * it under the terms of the GNU General Public License as published by | ||
163 | + * the Free Software Foundation, either version 2 of the License, or | ||
164 | + * (at your option) any later version. | ||
165 | + * | ||
166 | + * This program is distributed in the hope that it will be useful, | ||
167 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
168 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
169 | + * GNU General Public License for more details. | ||
170 | + * | ||
171 | + * You should have received a copy of the GNU General Public License | ||
172 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
173 | + */ | ||
174 | + | ||
175 | +#include "qemu/osdep.h" | ||
176 | +#include "exec/address-spaces.h" | ||
177 | +#include "qapi/error.h" | ||
178 | +#include "qemu/error-report.h" | ||
179 | +#include "qemu/module.h" | ||
180 | +#include "qemu/units.h" | ||
181 | +#include "hw/qdev-core.h" | ||
182 | +#include "cpu.h" | ||
183 | +#include "hw/sysbus.h" | ||
184 | +#include "hw/char/serial.h" | ||
185 | +#include "hw/misc/unimp.h" | ||
186 | +#include "sysemu/sysemu.h" | ||
187 | +#include "hw/arm/allwinner-h3.h" | ||
188 | + | ||
189 | +/* Memory map */ | ||
190 | +const hwaddr allwinner_h3_memmap[] = { | ||
191 | + [AW_H3_SRAM_A1] = 0x00000000, | ||
192 | + [AW_H3_SRAM_A2] = 0x00044000, | ||
193 | + [AW_H3_SRAM_C] = 0x00010000, | ||
194 | + [AW_H3_PIT] = 0x01c20c00, | ||
195 | + [AW_H3_UART0] = 0x01c28000, | ||
196 | + [AW_H3_UART1] = 0x01c28400, | ||
197 | + [AW_H3_UART2] = 0x01c28800, | ||
198 | + [AW_H3_UART3] = 0x01c28c00, | ||
199 | + [AW_H3_GIC_DIST] = 0x01c81000, | ||
200 | + [AW_H3_GIC_CPU] = 0x01c82000, | ||
201 | + [AW_H3_GIC_HYP] = 0x01c84000, | ||
202 | + [AW_H3_GIC_VCPU] = 0x01c86000, | ||
203 | + [AW_H3_SDRAM] = 0x40000000 | ||
204 | +}; | ||
205 | + | ||
206 | +/* List of unimplemented devices */ | ||
207 | +struct AwH3Unimplemented { | ||
208 | + const char *device_name; | ||
209 | + hwaddr base; | ||
210 | + hwaddr size; | ||
211 | +} unimplemented[] = { | ||
212 | + { "d-engine", 0x01000000, 4 * MiB }, | ||
213 | + { "d-inter", 0x01400000, 128 * KiB }, | ||
214 | + { "syscon", 0x01c00000, 4 * KiB }, | ||
215 | + { "dma", 0x01c02000, 4 * KiB }, | ||
216 | + { "nfdc", 0x01c03000, 4 * KiB }, | ||
217 | + { "ts", 0x01c06000, 4 * KiB }, | ||
218 | + { "keymem", 0x01c0b000, 4 * KiB }, | ||
219 | + { "lcd0", 0x01c0c000, 4 * KiB }, | ||
220 | + { "lcd1", 0x01c0d000, 4 * KiB }, | ||
221 | + { "ve", 0x01c0e000, 4 * KiB }, | ||
222 | + { "mmc0", 0x01c0f000, 4 * KiB }, | ||
223 | + { "mmc1", 0x01c10000, 4 * KiB }, | ||
224 | + { "mmc2", 0x01c11000, 4 * KiB }, | ||
225 | + { "sid", 0x01c14000, 1 * KiB }, | ||
226 | + { "crypto", 0x01c15000, 4 * KiB }, | ||
227 | + { "msgbox", 0x01c17000, 4 * KiB }, | ||
228 | + { "spinlock", 0x01c18000, 4 * KiB }, | ||
229 | + { "usb0-otg", 0x01c19000, 4 * KiB }, | ||
230 | + { "usb0-phy", 0x01c1a000, 4 * KiB }, | ||
231 | + { "usb1-phy", 0x01c1b000, 4 * KiB }, | ||
232 | + { "usb2-phy", 0x01c1c000, 4 * KiB }, | ||
233 | + { "usb3-phy", 0x01c1d000, 4 * KiB }, | ||
234 | + { "smc", 0x01c1e000, 4 * KiB }, | ||
235 | + { "ccu", 0x01c20000, 1 * KiB }, | ||
236 | + { "pio", 0x01c20800, 1 * KiB }, | ||
237 | + { "owa", 0x01c21000, 1 * KiB }, | ||
238 | + { "pwm", 0x01c21400, 1 * KiB }, | ||
239 | + { "keyadc", 0x01c21800, 1 * KiB }, | ||
240 | + { "pcm0", 0x01c22000, 1 * KiB }, | ||
241 | + { "pcm1", 0x01c22400, 1 * KiB }, | ||
242 | + { "pcm2", 0x01c22800, 1 * KiB }, | ||
243 | + { "audio", 0x01c22c00, 2 * KiB }, | ||
244 | + { "smta", 0x01c23400, 1 * KiB }, | ||
245 | + { "ths", 0x01c25000, 1 * KiB }, | ||
246 | + { "uart0", 0x01c28000, 1 * KiB }, | ||
247 | + { "uart1", 0x01c28400, 1 * KiB }, | ||
248 | + { "uart2", 0x01c28800, 1 * KiB }, | ||
249 | + { "uart3", 0x01c28c00, 1 * KiB }, | ||
250 | + { "twi0", 0x01c2ac00, 1 * KiB }, | ||
251 | + { "twi1", 0x01c2b000, 1 * KiB }, | ||
252 | + { "twi2", 0x01c2b400, 1 * KiB }, | ||
253 | + { "scr", 0x01c2c400, 1 * KiB }, | ||
254 | + { "emac", 0x01c30000, 64 * KiB }, | ||
255 | + { "gpu", 0x01c40000, 64 * KiB }, | ||
256 | + { "hstmr", 0x01c60000, 4 * KiB }, | ||
257 | + { "dramcom", 0x01c62000, 4 * KiB }, | ||
258 | + { "dramctl0", 0x01c63000, 4 * KiB }, | ||
259 | + { "dramphy0", 0x01c65000, 4 * KiB }, | ||
260 | + { "spi0", 0x01c68000, 4 * KiB }, | ||
261 | + { "spi1", 0x01c69000, 4 * KiB }, | ||
262 | + { "csi", 0x01cb0000, 320 * KiB }, | ||
263 | + { "tve", 0x01e00000, 64 * KiB }, | ||
264 | + { "hdmi", 0x01ee0000, 128 * KiB }, | ||
265 | + { "rtc", 0x01f00000, 1 * KiB }, | ||
266 | + { "r_timer", 0x01f00800, 1 * KiB }, | ||
267 | + { "r_intc", 0x01f00c00, 1 * KiB }, | ||
268 | + { "r_wdog", 0x01f01000, 1 * KiB }, | ||
269 | + { "r_prcm", 0x01f01400, 1 * KiB }, | ||
270 | + { "r_twd", 0x01f01800, 1 * KiB }, | ||
271 | + { "r_cpucfg", 0x01f01c00, 1 * KiB }, | ||
272 | + { "r_cir-rx", 0x01f02000, 1 * KiB }, | ||
273 | + { "r_twi", 0x01f02400, 1 * KiB }, | ||
274 | + { "r_uart", 0x01f02800, 1 * KiB }, | ||
275 | + { "r_pio", 0x01f02c00, 1 * KiB }, | ||
276 | + { "r_pwm", 0x01f03800, 1 * KiB }, | ||
277 | + { "core-dbg", 0x3f500000, 128 * KiB }, | ||
278 | + { "tsgen-ro", 0x3f506000, 4 * KiB }, | ||
279 | + { "tsgen-ctl", 0x3f507000, 4 * KiB }, | ||
280 | + { "ddr-mem", 0x40000000, 2 * GiB }, | ||
281 | + { "n-brom", 0xffff0000, 32 * KiB }, | ||
282 | + { "s-brom", 0xffff0000, 64 * KiB } | ||
283 | +}; | ||
284 | + | ||
285 | +/* Per Processor Interrupts */ | ||
286 | +enum { | ||
287 | + AW_H3_GIC_PPI_MAINT = 9, | ||
288 | + AW_H3_GIC_PPI_HYPTIMER = 10, | ||
289 | + AW_H3_GIC_PPI_VIRTTIMER = 11, | ||
290 | + AW_H3_GIC_PPI_SECTIMER = 13, | ||
291 | + AW_H3_GIC_PPI_PHYSTIMER = 14 | ||
292 | +}; | ||
293 | + | ||
294 | +/* Shared Processor Interrupts */ | ||
295 | +enum { | ||
296 | + AW_H3_GIC_SPI_UART0 = 0, | ||
297 | + AW_H3_GIC_SPI_UART1 = 1, | ||
298 | + AW_H3_GIC_SPI_UART2 = 2, | ||
299 | + AW_H3_GIC_SPI_UART3 = 3, | ||
300 | + AW_H3_GIC_SPI_TIMER0 = 18, | ||
301 | + AW_H3_GIC_SPI_TIMER1 = 19, | ||
302 | +}; | ||
303 | + | ||
304 | +/* Allwinner H3 general constants */ | ||
305 | +enum { | ||
306 | + AW_H3_GIC_NUM_SPI = 128 | ||
307 | +}; | ||
308 | + | ||
309 | +static void allwinner_h3_init(Object *obj) | ||
310 | +{ | 64 | +{ |
311 | + AwH3State *s = AW_H3(obj); | 65 | + unsigned imm = x >> 3; |
312 | + | 66 | + unsigned scale = extract32(x, 0, 3); |
313 | + s->memmap = allwinner_h3_memmap; | 67 | + return imm << scale; |
314 | + | ||
315 | + for (int i = 0; i < AW_H3_NUM_CPUS; i++) { | ||
316 | + object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]), | ||
317 | + ARM_CPU_TYPE_NAME("cortex-a7"), | ||
318 | + &error_abort, NULL); | ||
319 | + } | ||
320 | + | ||
321 | + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), | ||
322 | + TYPE_ARM_GIC); | ||
323 | + | ||
324 | + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), | ||
325 | + TYPE_AW_A10_PIT); | ||
326 | + object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), | ||
327 | + "clk0-freq", &error_abort); | ||
328 | + object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), | ||
329 | + "clk1-freq", &error_abort); | ||
330 | +} | 68 | +} |
331 | + | 69 | + |
332 | +static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 70 | /* |
333 | +{ | 71 | * Include the generated decoders. |
334 | + AwH3State *s = AW_H3(dev); | 72 | */ |
335 | + unsigned i; | 73 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
336 | + | 74 | } |
337 | + /* CPUs */ | 75 | } |
338 | + for (i = 0; i < AW_H3_NUM_CPUS; i++) { | 76 | |
339 | + | 77 | -/* |
340 | + /* Provide Power State Coordination Interface */ | 78 | - * Load/store (unsigned immediate) |
341 | + qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", | 79 | - * |
342 | + QEMU_PSCI_CONDUIT_HVC); | 80 | - * 31 30 29 27 26 25 24 23 22 21 10 9 5 |
343 | + | 81 | - * +----+-------+---+-----+-----+------------+-------+------+ |
344 | + /* Disable secondary CPUs */ | 82 | - * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | |
345 | + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", | 83 | - * +----+-------+---+-----+-----+------------+-------+------+ |
346 | + i > 0); | 84 | - * |
347 | + | 85 | - * For non-vector: |
348 | + /* All exception levels required */ | 86 | - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit |
349 | + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); | 87 | - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 |
350 | + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); | 88 | - * For vector: |
351 | + | 89 | - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated |
352 | + /* Mark realized */ | 90 | - * opc<0>: 0 -> store, 1 -> load |
353 | + qdev_init_nofail(DEVICE(&s->cpus[i])); | 91 | - * Rn: base address register (inc SP) |
354 | + } | 92 | - * Rt: target register |
355 | + | 93 | - */ |
356 | + /* Generic Interrupt Controller */ | 94 | -static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
357 | + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + | 95 | - int opc, |
358 | + GIC_INTERNAL); | 96 | - int size, |
359 | + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); | 97 | - int rt, |
360 | + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); | 98 | - bool is_vector) |
361 | + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); | 99 | -{ |
362 | + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); | 100 | - int rn = extract32(insn, 5, 5); |
363 | + qdev_init_nofail(DEVICE(&s->gic)); | 101 | - unsigned int imm12 = extract32(insn, 10, 12); |
364 | + | 102 | - unsigned int offset; |
365 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]); | 103 | - TCGv_i64 clean_addr, dirty_addr; |
366 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]); | 104 | - bool is_store; |
367 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]); | 105 | - bool is_signed = false; |
368 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]); | 106 | - bool is_extended = false; |
369 | + | 107 | - MemOp memop; |
370 | + /* | 108 | - |
371 | + * Wire the outputs from each CPU's generic timer and the GICv3 | 109 | - if (is_vector) { |
372 | + * maintenance interrupt signal to the appropriate GIC PPI inputs, | 110 | - size |= (opc & 2) << 1; |
373 | + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | 111 | - if (size > 4) { |
374 | + */ | 112 | - unallocated_encoding(s); |
375 | + for (i = 0; i < AW_H3_NUM_CPUS; i++) { | 113 | - return; |
376 | + DeviceState *cpudev = DEVICE(&s->cpus[i]); | 114 | - } |
377 | + int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; | 115 | - is_store = !extract32(opc, 0, 1); |
378 | + int irq; | 116 | - if (!fp_access_check(s)) { |
379 | + /* | 117 | - return; |
380 | + * Mapping from the output timer irq lines from the CPU to the | 118 | - } |
381 | + * GIC PPI inputs used for this board. | 119 | - memop = finalize_memop_asimd(s, size); |
382 | + */ | 120 | - } else { |
383 | + const int timer_irq[] = { | 121 | - if (size == 3 && opc == 2) { |
384 | + [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER, | 122 | - /* PRFM - prefetch */ |
385 | + [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER, | 123 | - return; |
386 | + [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER, | 124 | - } |
387 | + [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER, | 125 | - if (opc == 3 && size > 1) { |
388 | + }; | 126 | - unallocated_encoding(s); |
389 | + | 127 | - return; |
390 | + /* Connect CPU timer outputs to GIC PPI inputs */ | 128 | - } |
391 | + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | 129 | - is_store = (opc == 0); |
392 | + qdev_connect_gpio_out(cpudev, irq, | 130 | - is_signed = !is_store && extract32(opc, 1, 1); |
393 | + qdev_get_gpio_in(DEVICE(&s->gic), | 131 | - is_extended = (size < 3) && extract32(opc, 0, 1); |
394 | + ppibase + timer_irq[irq])); | 132 | - memop = finalize_memop(s, size + is_signed * MO_SIGN); |
395 | + } | 133 | - } |
396 | + | 134 | - |
397 | + /* Connect GIC outputs to CPU interrupt inputs */ | 135 | - if (rn == 31) { |
398 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, | 136 | - gen_check_sp_alignment(s); |
399 | + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | 137 | - } |
400 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS, | 138 | - dirty_addr = read_cpu_reg_sp(s, rn, 1); |
401 | + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | 139 | - offset = imm12 << size; |
402 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS), | 140 | - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
403 | + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | 141 | - |
404 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS), | 142 | - clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, memop); |
405 | + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | 143 | - |
406 | + | 144 | - if (is_vector) { |
407 | + /* GIC maintenance signal */ | 145 | - if (is_store) { |
408 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS), | 146 | - do_fp_st(s, rt, clean_addr, memop); |
409 | + qdev_get_gpio_in(DEVICE(&s->gic), | 147 | - } else { |
410 | + ppibase + AW_H3_GIC_PPI_MAINT)); | 148 | - do_fp_ld(s, rt, clean_addr, memop); |
411 | + } | 149 | - } |
412 | + | 150 | - } else { |
413 | + /* Timer */ | 151 | - TCGv_i64 tcg_rt = cpu_reg(s, rt); |
414 | + qdev_init_nofail(DEVICE(&s->timer)); | 152 | - bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
415 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]); | 153 | - if (is_store) { |
416 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, | 154 | - do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false); |
417 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0)); | 155 | - } else { |
418 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, | 156 | - do_gpr_ld(s, tcg_rt, clean_addr, memop, |
419 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1)); | 157 | - is_extended, true, rt, iss_sf, false); |
420 | + | 158 | - } |
421 | + /* SRAM */ | 159 | - } |
422 | + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", | 160 | -} |
423 | + 64 * KiB, &error_abort); | 161 | - |
424 | + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", | 162 | /* Atomic memory operations |
425 | + 32 * KiB, &error_abort); | 163 | * |
426 | + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", | 164 | * 31 30 27 26 24 22 21 16 15 12 10 5 0 |
427 | + 44 * KiB, &error_abort); | 165 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
428 | + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1], | 166 | return; |
429 | + &s->sram_a1); | 167 | } |
430 | + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2], | 168 | break; |
431 | + &s->sram_a2); | 169 | - case 1: |
432 | + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], | 170 | - disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
433 | + &s->sram_c); | 171 | - return; |
434 | + | 172 | } |
435 | + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ | 173 | unallocated_encoding(s); |
436 | + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, | 174 | } |
437 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), | ||
438 | + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); | ||
439 | + /* UART1 */ | ||
440 | + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2, | ||
441 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1), | ||
442 | + 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN); | ||
443 | + /* UART2 */ | ||
444 | + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2, | ||
445 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2), | ||
446 | + 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN); | ||
447 | + /* UART3 */ | ||
448 | + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2, | ||
449 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3), | ||
450 | + 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); | ||
451 | + | ||
452 | + /* Unimplemented devices */ | ||
453 | + for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { | ||
454 | + create_unimplemented_device(unimplemented[i].device_name, | ||
455 | + unimplemented[i].base, | ||
456 | + unimplemented[i].size); | ||
457 | + } | ||
458 | +} | ||
459 | + | ||
460 | +static void allwinner_h3_class_init(ObjectClass *oc, void *data) | ||
461 | +{ | ||
462 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
463 | + | ||
464 | + dc->realize = allwinner_h3_realize; | ||
465 | + /* Reason: uses serial_hd() in realize function */ | ||
466 | + dc->user_creatable = false; | ||
467 | +} | ||
468 | + | ||
469 | +static const TypeInfo allwinner_h3_type_info = { | ||
470 | + .name = TYPE_AW_H3, | ||
471 | + .parent = TYPE_DEVICE, | ||
472 | + .instance_size = sizeof(AwH3State), | ||
473 | + .instance_init = allwinner_h3_init, | ||
474 | + .class_init = allwinner_h3_class_init, | ||
475 | +}; | ||
476 | + | ||
477 | +static void allwinner_h3_register_types(void) | ||
478 | +{ | ||
479 | + type_register_static(&allwinner_h3_type_info); | ||
480 | +} | ||
481 | + | ||
482 | +type_init(allwinner_h3_register_types) | ||
483 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
484 | index XXXXXXX..XXXXXXX 100644 | ||
485 | --- a/MAINTAINERS | ||
486 | +++ b/MAINTAINERS | ||
487 | @@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner* | ||
488 | F: include/hw/*/allwinner* | ||
489 | F: hw/arm/cubieboard.c | ||
490 | |||
491 | +Allwinner-h3 | ||
492 | +M: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
493 | +L: qemu-arm@nongnu.org | ||
494 | +S: Maintained | ||
495 | +F: hw/*/allwinner-h3* | ||
496 | +F: include/hw/*/allwinner-h3* | ||
497 | + | ||
498 | ARM PrimeCell and CMSDK devices | ||
499 | M: Peter Maydell <peter.maydell@linaro.org> | ||
500 | L: qemu-arm@nongnu.org | ||
501 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
502 | index XXXXXXX..XXXXXXX 100644 | ||
503 | --- a/default-configs/arm-softmmu.mak | ||
504 | +++ b/default-configs/arm-softmmu.mak | ||
505 | @@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y | ||
506 | CONFIG_FSL_IMX7=y | ||
507 | CONFIG_FSL_IMX6UL=y | ||
508 | CONFIG_SEMIHOSTING=y | ||
509 | +CONFIG_ALLWINNER_H3=y | ||
510 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
511 | index XXXXXXX..XXXXXXX 100644 | ||
512 | --- a/hw/arm/Kconfig | ||
513 | +++ b/hw/arm/Kconfig | ||
514 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 | ||
515 | select SERIAL | ||
516 | select UNIMP | ||
517 | |||
518 | +config ALLWINNER_H3 | ||
519 | + bool | ||
520 | + select ALLWINNER_A10_PIT | ||
521 | + select SERIAL | ||
522 | + select ARM_TIMER | ||
523 | + select ARM_GIC | ||
524 | + select UNIMP | ||
525 | + | ||
526 | config RASPI | ||
527 | bool | ||
528 | select FRAMEBUFFER | ||
529 | -- | 175 | -- |
530 | 2.20.1 | 176 | 2.34.1 |
531 | |||
532 | diff view generated by jsdifflib |
1 | From: Beata Michalska <beata.michalska@linaro.org> | 1 | Convert the LDR and STR instructions which take a register |
---|---|---|---|
2 | plus register offset to decodetree. | ||
2 | 3 | ||
3 | KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | As such this should be the last step of sync to avoid potential overwriting | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | of whatever changes KVM might have done. | 6 | Message-id: 20230602155223.2040685-15-peter.maydell@linaro.org |
7 | --- | ||
8 | target/arm/tcg/a64.decode | 22 +++++ | ||
9 | target/arm/tcg/translate-a64.c | 173 +++++++++++++++------------------ | ||
10 | 2 files changed, 103 insertions(+), 92 deletions(-) | ||
6 | 11 | ||
7 | Signed-off-by: Beata Michalska <beata.michalska@linaro.org> | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
8 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
9 | Message-id: 20200312003401.29017-2-beata.michalska@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/kvm32.c | 15 ++++++++++----- | ||
13 | target/arm/kvm64.c | 15 ++++++++++----- | ||
14 | 2 files changed, 20 insertions(+), 10 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/kvm32.c | 14 | --- a/target/arm/tcg/a64.decode |
19 | +++ b/target/arm/kvm32.c | 15 | +++ b/target/arm/tcg/a64.decode |
20 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level) | 16 | @@ -XXX,XX +XXX,XX @@ STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext= |
21 | return ret; | 17 | STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 |
22 | } | 18 | LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 |
23 | 19 | LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 | |
24 | - ret = kvm_put_vcpu_events(cpu); | 20 | + |
25 | - if (ret) { | 21 | +# Load/store with register offset |
26 | - return ret; | 22 | +&ldst rm rn rt sign ext sz opt s |
23 | +@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst | ||
24 | +STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 | ||
25 | +LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 | ||
26 | +LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 | ||
27 | +LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 | ||
28 | +LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 | ||
29 | +LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 | ||
30 | +LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 | ||
31 | +LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 | ||
32 | +LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 | ||
33 | +LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 | ||
34 | + | ||
35 | +# PRFM | ||
36 | +NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- | ||
37 | + | ||
38 | +STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 | ||
39 | +STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 | ||
40 | +LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 | ||
41 | +LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 | ||
42 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/tcg/translate-a64.c | ||
45 | +++ b/target/arm/tcg/translate-a64.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a) | ||
47 | return true; | ||
48 | } | ||
49 | |||
50 | -/* | ||
51 | - * Load/store (register offset) | ||
52 | - * | ||
53 | - * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | ||
54 | - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | ||
55 | - * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | ||
56 | - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | ||
57 | - * | ||
58 | - * For non-vector: | ||
59 | - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | ||
60 | - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | ||
61 | - * For vector: | ||
62 | - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | ||
63 | - * opc<0>: 0 -> store, 1 -> load | ||
64 | - * V: 1 -> vector/simd | ||
65 | - * opt: extend encoding (see DecodeRegExtend) | ||
66 | - * S: if S=1 then scale (essentially index by sizeof(size)) | ||
67 | - * Rt: register to transfer into/out of | ||
68 | - * Rn: address register or SP for base | ||
69 | - * Rm: offset register or ZR for offset | ||
70 | - */ | ||
71 | -static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, | ||
72 | - int opc, | ||
73 | - int size, | ||
74 | - int rt, | ||
75 | - bool is_vector) | ||
76 | +static void op_addr_ldst_pre(DisasContext *s, arg_ldst *a, | ||
77 | + TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr, | ||
78 | + bool is_store, MemOp memop) | ||
79 | { | ||
80 | - int rn = extract32(insn, 5, 5); | ||
81 | - int shift = extract32(insn, 12, 1); | ||
82 | - int rm = extract32(insn, 16, 5); | ||
83 | - int opt = extract32(insn, 13, 3); | ||
84 | - bool is_signed = false; | ||
85 | - bool is_store = false; | ||
86 | - bool is_extended = false; | ||
87 | - TCGv_i64 tcg_rm, clean_addr, dirty_addr; | ||
88 | - MemOp memop; | ||
89 | + TCGv_i64 tcg_rm; | ||
90 | |||
91 | - if (extract32(opt, 1, 1) == 0) { | ||
92 | - unallocated_encoding(s); | ||
93 | - return; | ||
27 | - } | 94 | - } |
28 | - | 95 | - |
29 | write_cpustate_to_list(cpu, true); | 96 | - if (is_vector) { |
30 | 97 | - size |= (opc & 2) << 1; | |
31 | if (!write_list_to_kvmstate(cpu, level)) { | 98 | - if (size > 4) { |
32 | return EINVAL; | 99 | - unallocated_encoding(s); |
33 | } | 100 | - return; |
34 | 101 | - } | |
35 | + /* | 102 | - is_store = !extract32(opc, 0, 1); |
36 | + * Setting VCPU events should be triggered after syncing the registers | 103 | - if (!fp_access_check(s)) { |
37 | + * to avoid overwriting potential changes made by KVM upon calling | 104 | - return; |
38 | + * KVM_SET_VCPU_EVENTS ioctl | 105 | - } |
39 | + */ | 106 | - memop = finalize_memop_asimd(s, size); |
40 | + ret = kvm_put_vcpu_events(cpu); | 107 | - } else { |
41 | + if (ret) { | 108 | - if (size == 3 && opc == 2) { |
42 | + return ret; | 109 | - /* PRFM - prefetch */ |
43 | + } | 110 | - return; |
44 | + | 111 | - } |
45 | kvm_arm_sync_mpstate_to_kvm(cpu); | 112 | - if (opc == 3 && size > 1) { |
46 | 113 | - unallocated_encoding(s); | |
47 | return ret; | 114 | - return; |
48 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | 115 | - } |
49 | index XXXXXXX..XXXXXXX 100644 | 116 | - is_store = (opc == 0); |
50 | --- a/target/arm/kvm64.c | 117 | - is_signed = !is_store && extract32(opc, 1, 1); |
51 | +++ b/target/arm/kvm64.c | 118 | - is_extended = (size < 3) && extract32(opc, 0, 1); |
52 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level) | 119 | - memop = finalize_memop(s, size + is_signed * MO_SIGN); |
53 | return ret; | ||
54 | } | ||
55 | |||
56 | - ret = kvm_put_vcpu_events(cpu); | ||
57 | - if (ret) { | ||
58 | - return ret; | ||
59 | - } | 120 | - } |
60 | - | 121 | - |
61 | write_cpustate_to_list(cpu, true); | 122 | - if (rn == 31) { |
62 | 123 | + if (a->rn == 31) { | |
63 | if (!write_list_to_kvmstate(cpu, level)) { | 124 | gen_check_sp_alignment(s); |
64 | return -EINVAL; | ||
65 | } | 125 | } |
66 | 126 | - dirty_addr = read_cpu_reg_sp(s, rn, 1); | |
67 | + /* | 127 | + *dirty_addr = read_cpu_reg_sp(s, a->rn, 1); |
68 | + * Setting VCPU events should be triggered after syncing the registers | 128 | |
69 | + * to avoid overwriting potential changes made by KVM upon calling | 129 | - tcg_rm = read_cpu_reg(s, rm, 1); |
70 | + * KVM_SET_VCPU_EVENTS ioctl | 130 | - ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); |
71 | + */ | 131 | + tcg_rm = read_cpu_reg(s, a->rm, 1); |
72 | + ret = kvm_put_vcpu_events(cpu); | 132 | + ext_and_shift_reg(tcg_rm, tcg_rm, a->opt, a->s ? a->sz : 0); |
73 | + if (ret) { | 133 | |
74 | + return ret; | 134 | - tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
75 | + } | 135 | + tcg_gen_add_i64(*dirty_addr, *dirty_addr, tcg_rm); |
76 | + | 136 | + *clean_addr = gen_mte_check1(s, *dirty_addr, is_store, true, memop); |
77 | kvm_arm_sync_mpstate_to_kvm(cpu); | 137 | +} |
78 | 138 | ||
79 | return ret; | 139 | - clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, memop); |
140 | +static bool trans_LDR(DisasContext *s, arg_ldst *a) | ||
141 | +{ | ||
142 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
143 | + bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext); | ||
144 | + MemOp memop; | ||
145 | |||
146 | - if (is_vector) { | ||
147 | - if (is_store) { | ||
148 | - do_fp_st(s, rt, clean_addr, memop); | ||
149 | - } else { | ||
150 | - do_fp_ld(s, rt, clean_addr, memop); | ||
151 | - } | ||
152 | - } else { | ||
153 | - TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
154 | - bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
155 | - | ||
156 | - if (is_store) { | ||
157 | - do_gpr_st(s, tcg_rt, clean_addr, memop, | ||
158 | - true, rt, iss_sf, false); | ||
159 | - } else { | ||
160 | - do_gpr_ld(s, tcg_rt, clean_addr, memop, | ||
161 | - is_extended, true, rt, iss_sf, false); | ||
162 | - } | ||
163 | + if (extract32(a->opt, 1, 1) == 0) { | ||
164 | + return false; | ||
165 | } | ||
166 | + | ||
167 | + memop = finalize_memop(s, a->sz + a->sign * MO_SIGN); | ||
168 | + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop); | ||
169 | + tcg_rt = cpu_reg(s, a->rt); | ||
170 | + do_gpr_ld(s, tcg_rt, clean_addr, memop, | ||
171 | + a->ext, true, a->rt, iss_sf, false); | ||
172 | + return true; | ||
173 | +} | ||
174 | + | ||
175 | +static bool trans_STR(DisasContext *s, arg_ldst *a) | ||
176 | +{ | ||
177 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
178 | + bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext); | ||
179 | + MemOp memop; | ||
180 | + | ||
181 | + if (extract32(a->opt, 1, 1) == 0) { | ||
182 | + return false; | ||
183 | + } | ||
184 | + | ||
185 | + memop = finalize_memop(s, a->sz); | ||
186 | + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop); | ||
187 | + tcg_rt = cpu_reg(s, a->rt); | ||
188 | + do_gpr_st(s, tcg_rt, clean_addr, memop, true, a->rt, iss_sf, false); | ||
189 | + return true; | ||
190 | +} | ||
191 | + | ||
192 | +static bool trans_LDR_v(DisasContext *s, arg_ldst *a) | ||
193 | +{ | ||
194 | + TCGv_i64 clean_addr, dirty_addr; | ||
195 | + MemOp memop; | ||
196 | + | ||
197 | + if (extract32(a->opt, 1, 1) == 0) { | ||
198 | + return false; | ||
199 | + } | ||
200 | + | ||
201 | + if (!fp_access_check(s)) { | ||
202 | + return true; | ||
203 | + } | ||
204 | + | ||
205 | + memop = finalize_memop_asimd(s, a->sz); | ||
206 | + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop); | ||
207 | + do_fp_ld(s, a->rt, clean_addr, memop); | ||
208 | + return true; | ||
209 | +} | ||
210 | + | ||
211 | +static bool trans_STR_v(DisasContext *s, arg_ldst *a) | ||
212 | +{ | ||
213 | + TCGv_i64 clean_addr, dirty_addr; | ||
214 | + MemOp memop; | ||
215 | + | ||
216 | + if (extract32(a->opt, 1, 1) == 0) { | ||
217 | + return false; | ||
218 | + } | ||
219 | + | ||
220 | + if (!fp_access_check(s)) { | ||
221 | + return true; | ||
222 | + } | ||
223 | + | ||
224 | + memop = finalize_memop_asimd(s, a->sz); | ||
225 | + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop); | ||
226 | + do_fp_st(s, a->rt, clean_addr, memop); | ||
227 | + return true; | ||
228 | } | ||
229 | |||
230 | /* Atomic memory operations | ||
231 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | ||
232 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | ||
233 | { | ||
234 | int rt = extract32(insn, 0, 5); | ||
235 | - int opc = extract32(insn, 22, 2); | ||
236 | bool is_vector = extract32(insn, 26, 1); | ||
237 | int size = extract32(insn, 30, 2); | ||
238 | |||
239 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) | ||
240 | disas_ldst_atomic(s, insn, size, rt, is_vector); | ||
241 | return; | ||
242 | case 2: | ||
243 | - disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); | ||
244 | - return; | ||
245 | + break; | ||
246 | default: | ||
247 | disas_ldst_pac(s, insn, size, rt, is_vector); | ||
248 | return; | ||
80 | -- | 249 | -- |
81 | 2.20.1 | 250 | 2.34.1 |
82 | |||
83 | diff view generated by jsdifflib |
1 | Fix a couple of comment typos. | 1 | Convert the insns in the atomic memory operations group to |
---|---|---|---|
2 | decodetree. | ||
2 | 3 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20200303174950.3298-5-peter.maydell@linaro.org | 6 | Message-id: 20230602155223.2040685-16-peter.maydell@linaro.org |
6 | --- | 7 | --- |
7 | target/arm/helper.c | 2 +- | 8 | target/arm/tcg/a64.decode | 15 ++++ |
8 | target/arm/translate.c | 2 +- | 9 | target/arm/tcg/translate-a64.c | 153 ++++++++++++--------------------- |
9 | 2 files changed, 2 insertions(+), 2 deletions(-) | 10 | 2 files changed, 70 insertions(+), 98 deletions(-) |
10 | 11 | ||
11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/helper.c | 14 | --- a/target/arm/tcg/a64.decode |
14 | +++ b/target/arm/helper.c | 15 | +++ b/target/arm/tcg/a64.decode |
15 | @@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) | 16 | @@ -XXX,XX +XXX,XX @@ STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 |
17 | STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 | ||
18 | LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 | ||
19 | LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 | ||
20 | + | ||
21 | +# Atomic memory operations | ||
22 | +&atomic rs rn rt a r sz | ||
23 | +@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic | ||
24 | +LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic | ||
25 | +LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic | ||
26 | +LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic | ||
27 | +LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic | ||
28 | +LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic | ||
29 | +LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic | ||
30 | +LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic | ||
31 | +LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic | ||
32 | +SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic | ||
33 | + | ||
34 | +LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 | ||
35 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/tcg/translate-a64.c | ||
38 | +++ b/target/arm/tcg/translate-a64.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static bool trans_STR_v(DisasContext *s, arg_ldst *a) | ||
40 | return true; | ||
41 | } | ||
42 | |||
43 | -/* Atomic memory operations | ||
44 | - * | ||
45 | - * 31 30 27 26 24 22 21 16 15 12 10 5 0 | ||
46 | - * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ | ||
47 | - * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | | ||
48 | - * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ | ||
49 | - * | ||
50 | - * Rt: the result register | ||
51 | - * Rn: base address or SP | ||
52 | - * Rs: the source register for the operation | ||
53 | - * V: vector flag (always 0 as of v8.3) | ||
54 | - * A: acquire flag | ||
55 | - * R: release flag | ||
56 | - */ | ||
57 | -static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
58 | - int size, int rt, bool is_vector) | ||
59 | + | ||
60 | +static bool do_atomic_ld(DisasContext *s, arg_atomic *a, AtomicThreeOpFn *fn, | ||
61 | + int sign, bool invert) | ||
62 | { | ||
63 | - int rs = extract32(insn, 16, 5); | ||
64 | - int rn = extract32(insn, 5, 5); | ||
65 | - int o3_opc = extract32(insn, 12, 4); | ||
66 | - bool r = extract32(insn, 22, 1); | ||
67 | - bool a = extract32(insn, 23, 1); | ||
68 | - TCGv_i64 tcg_rs, tcg_rt, clean_addr; | ||
69 | - AtomicThreeOpFn *fn = NULL; | ||
70 | - MemOp mop = size; | ||
71 | + MemOp mop = a->sz | sign; | ||
72 | + TCGv_i64 clean_addr, tcg_rs, tcg_rt; | ||
73 | |||
74 | - if (is_vector || !dc_isar_feature(aa64_atomics, s)) { | ||
75 | - unallocated_encoding(s); | ||
76 | - return; | ||
77 | - } | ||
78 | - switch (o3_opc) { | ||
79 | - case 000: /* LDADD */ | ||
80 | - fn = tcg_gen_atomic_fetch_add_i64; | ||
81 | - break; | ||
82 | - case 001: /* LDCLR */ | ||
83 | - fn = tcg_gen_atomic_fetch_and_i64; | ||
84 | - break; | ||
85 | - case 002: /* LDEOR */ | ||
86 | - fn = tcg_gen_atomic_fetch_xor_i64; | ||
87 | - break; | ||
88 | - case 003: /* LDSET */ | ||
89 | - fn = tcg_gen_atomic_fetch_or_i64; | ||
90 | - break; | ||
91 | - case 004: /* LDSMAX */ | ||
92 | - fn = tcg_gen_atomic_fetch_smax_i64; | ||
93 | - mop |= MO_SIGN; | ||
94 | - break; | ||
95 | - case 005: /* LDSMIN */ | ||
96 | - fn = tcg_gen_atomic_fetch_smin_i64; | ||
97 | - mop |= MO_SIGN; | ||
98 | - break; | ||
99 | - case 006: /* LDUMAX */ | ||
100 | - fn = tcg_gen_atomic_fetch_umax_i64; | ||
101 | - break; | ||
102 | - case 007: /* LDUMIN */ | ||
103 | - fn = tcg_gen_atomic_fetch_umin_i64; | ||
104 | - break; | ||
105 | - case 010: /* SWP */ | ||
106 | - fn = tcg_gen_atomic_xchg_i64; | ||
107 | - break; | ||
108 | - case 014: /* LDAPR, LDAPRH, LDAPRB */ | ||
109 | - if (!dc_isar_feature(aa64_rcpc_8_3, s) || | ||
110 | - rs != 31 || a != 1 || r != 0) { | ||
111 | - unallocated_encoding(s); | ||
112 | - return; | ||
113 | - } | ||
114 | - break; | ||
115 | - default: | ||
116 | - unallocated_encoding(s); | ||
117 | - return; | ||
118 | - } | ||
119 | - | ||
120 | - if (rn == 31) { | ||
121 | + if (a->rn == 31) { | ||
122 | gen_check_sp_alignment(s); | ||
123 | } | ||
124 | - | ||
125 | - mop = check_atomic_align(s, rn, mop); | ||
126 | - clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, mop); | ||
127 | - | ||
128 | - if (o3_opc == 014) { | ||
129 | - /* | ||
130 | - * LDAPR* are a special case because they are a simple load, not a | ||
131 | - * fetch-and-do-something op. | ||
132 | - * The architectural consistency requirements here are weaker than | ||
133 | - * full load-acquire (we only need "load-acquire processor consistent"), | ||
134 | - * but we choose to implement them as full LDAQ. | ||
135 | - */ | ||
136 | - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false, | ||
137 | - true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); | ||
138 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
139 | - return; | ||
140 | - } | ||
141 | - | ||
142 | - tcg_rs = read_cpu_reg(s, rs, true); | ||
143 | - tcg_rt = cpu_reg(s, rt); | ||
144 | - | ||
145 | - if (o3_opc == 1) { /* LDCLR */ | ||
146 | + mop = check_atomic_align(s, a->rn, mop); | ||
147 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, | ||
148 | + a->rn != 31, mop); | ||
149 | + tcg_rs = read_cpu_reg(s, a->rs, true); | ||
150 | + tcg_rt = cpu_reg(s, a->rt); | ||
151 | + if (invert) { | ||
152 | tcg_gen_not_i64(tcg_rs, tcg_rs); | ||
153 | } | ||
154 | - | ||
155 | - /* The tcg atomic primitives are all full barriers. Therefore we | ||
156 | + /* | ||
157 | + * The tcg atomic primitives are all full barriers. Therefore we | ||
158 | * can ignore the Acquire and Release bits of this instruction. | ||
159 | */ | ||
160 | fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); | ||
161 | |||
162 | if (mop & MO_SIGN) { | ||
163 | - switch (size) { | ||
164 | + switch (a->sz) { | ||
165 | case MO_8: | ||
166 | tcg_gen_ext8u_i64(tcg_rt, tcg_rt); | ||
167 | break; | ||
168 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
169 | g_assert_not_reached(); | ||
170 | } | ||
171 | } | ||
172 | + return true; | ||
173 | +} | ||
174 | + | ||
175 | +TRANS_FEAT(LDADD, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_add_i64, 0, false) | ||
176 | +TRANS_FEAT(LDCLR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_and_i64, 0, true) | ||
177 | +TRANS_FEAT(LDEOR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_xor_i64, 0, false) | ||
178 | +TRANS_FEAT(LDSET, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_or_i64, 0, false) | ||
179 | +TRANS_FEAT(LDSMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smax_i64, MO_SIGN, false) | ||
180 | +TRANS_FEAT(LDSMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smin_i64, MO_SIGN, false) | ||
181 | +TRANS_FEAT(LDUMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umax_i64, 0, false) | ||
182 | +TRANS_FEAT(LDUMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umin_i64, 0, false) | ||
183 | +TRANS_FEAT(SWP, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_xchg_i64, 0, false) | ||
184 | + | ||
185 | +static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) | ||
186 | +{ | ||
187 | + bool iss_sf = ldst_iss_sf(a->sz, false, false); | ||
188 | + TCGv_i64 clean_addr; | ||
189 | + MemOp mop; | ||
190 | + | ||
191 | + if (!dc_isar_feature(aa64_atomics, s) || | ||
192 | + !dc_isar_feature(aa64_rcpc_8_3, s)) { | ||
193 | + return false; | ||
194 | + } | ||
195 | + if (a->rn == 31) { | ||
196 | + gen_check_sp_alignment(s); | ||
197 | + } | ||
198 | + mop = check_atomic_align(s, a->rn, a->sz); | ||
199 | + clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, | ||
200 | + a->rn != 31, mop); | ||
201 | + /* | ||
202 | + * LDAPR* are a special case because they are a simple load, not a | ||
203 | + * fetch-and-do-something op. | ||
204 | + * The architectural consistency requirements here are weaker than | ||
205 | + * full load-acquire (we only need "load-acquire processor consistent"), | ||
206 | + * but we choose to implement them as full LDAQ. | ||
207 | + */ | ||
208 | + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, false, | ||
209 | + true, a->rt, iss_sf, true); | ||
210 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
211 | + return true; | ||
212 | } | ||
16 | 213 | ||
17 | /* | 214 | /* |
18 | * If we have triggered a EL state change we can't rely on the | 215 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
19 | - * translator having passed it too us, we need to recompute. | 216 | } |
20 | + * translator having passed it to us, we need to recompute. | 217 | switch (extract32(insn, 10, 2)) { |
21 | */ | 218 | case 0: |
22 | void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | 219 | - disas_ldst_atomic(s, insn, size, rt, is_vector); |
23 | { | 220 | - return; |
24 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 221 | case 2: |
25 | index XXXXXXX..XXXXXXX 100644 | 222 | break; |
26 | --- a/target/arm/translate.c | 223 | default: |
27 | +++ b/target/arm/translate.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) | ||
29 | |||
30 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | ||
31 | /* | ||
32 | - * A write to any coprocessor regiser that ends a TB | ||
33 | + * A write to any coprocessor register that ends a TB | ||
34 | * must rebuild the hflags for the next TB. | ||
35 | */ | ||
36 | TCGv_i32 tcg_el = tcg_const_i32(s->current_el); | ||
37 | -- | 224 | -- |
38 | 2.20.1 | 225 | 2.34.1 |
39 | |||
40 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Convert the instructions in the load/store register (pointer |
---|---|---|---|
2 | authentication) group ot decodetree: LDRAA, LDRAB. | ||
2 | 3 | ||
3 | We plan to introduce yet another value for the gic version (nosel). | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | As we already use exotic values such as 0 and -1, let's introduce | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | a dedicated enum type and let vms->gic_version take this | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | type. | 7 | Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org |
8 | --- | ||
9 | target/arm/tcg/a64.decode | 7 +++ | ||
10 | target/arm/tcg/translate-a64.c | 83 +++++++--------------------------- | ||
11 | 2 files changed, 23 insertions(+), 67 deletions(-) | ||
7 | 12 | ||
8 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 13 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
11 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
12 | Message-id: 20200311131618.7187-3-eric.auger@redhat.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | include/hw/arm/virt.h | 11 +++++++++-- | ||
16 | hw/arm/virt.c | 30 +++++++++++++++--------------- | ||
17 | 2 files changed, 24 insertions(+), 17 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/arm/virt.h | 15 | --- a/target/arm/tcg/a64.decode |
22 | +++ b/include/hw/arm/virt.h | 16 | +++ b/target/arm/tcg/a64.decode |
23 | @@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType { | 17 | @@ -XXX,XX +XXX,XX @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic |
24 | VIRT_IOMMU_VIRTIO, | 18 | SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic |
25 | } VirtIOMMUType; | 19 | |
26 | 20 | LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 | |
27 | +typedef enum VirtGICType { | ||
28 | + VIRT_GIC_VERSION_MAX, | ||
29 | + VIRT_GIC_VERSION_HOST, | ||
30 | + VIRT_GIC_VERSION_2, | ||
31 | + VIRT_GIC_VERSION_3, | ||
32 | +} VirtGICType; | ||
33 | + | 21 | + |
34 | typedef struct MemMapEntry { | 22 | +# Load/store register (pointer authentication) |
35 | hwaddr base; | 23 | + |
36 | hwaddr size; | 24 | +# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous |
37 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 25 | +%ldra_imm 22:s1 12:9 !function=times_2 |
38 | bool highmem_ecam; | 26 | + |
39 | bool its; | 27 | +LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm |
40 | bool virt; | 28 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
41 | - int32_t gic_version; | 29 | index XXXXXXX..XXXXXXX 100644 |
42 | + VirtGICType gic_version; | 30 | --- a/target/arm/tcg/translate-a64.c |
43 | VirtIOMMUType iommu; | 31 | +++ b/target/arm/tcg/translate-a64.c |
44 | uint16_t virtio_iommu_bdf; | 32 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) |
45 | struct arm_boot_info bootinfo; | 33 | return true; |
46 | @@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) | ||
47 | uint32_t redist0_capacity = | ||
48 | vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; | ||
49 | |||
50 | - assert(vms->gic_version == 3); | ||
51 | + assert(vms->gic_version == VIRT_GIC_VERSION_3); | ||
52 | |||
53 | return vms->smp_cpus > redist0_capacity ? 2 : 1; | ||
54 | } | 34 | } |
55 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 35 | |
56 | index XXXXXXX..XXXXXXX 100644 | 36 | -/* |
57 | --- a/hw/arm/virt.c | 37 | - * PAC memory operations |
58 | +++ b/hw/arm/virt.c | 38 | - * |
59 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) | 39 | - * 31 30 27 26 24 22 21 12 11 10 5 0 |
60 | irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; | 40 | - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ |
41 | - * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | | ||
42 | - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | ||
43 | - * | ||
44 | - * Rt: the result register | ||
45 | - * Rn: base address or SP | ||
46 | - * V: vector flag (always 0 as of v8.3) | ||
47 | - * M: clear for key DA, set for key DB | ||
48 | - * W: pre-indexing flag | ||
49 | - * S: sign for imm9. | ||
50 | - */ | ||
51 | -static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
52 | - int size, int rt, bool is_vector) | ||
53 | +static bool trans_LDRA(DisasContext *s, arg_LDRA *a) | ||
54 | { | ||
55 | - int rn = extract32(insn, 5, 5); | ||
56 | - bool is_wback = extract32(insn, 11, 1); | ||
57 | - bool use_key_a = !extract32(insn, 23, 1); | ||
58 | - int offset; | ||
59 | TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
60 | MemOp memop; | ||
61 | |||
62 | - if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | ||
63 | - unallocated_encoding(s); | ||
64 | - return; | ||
65 | + /* Load with pointer authentication */ | ||
66 | + if (!dc_isar_feature(aa64_pauth, s)) { | ||
67 | + return false; | ||
61 | } | 68 | } |
62 | 69 | ||
63 | - if (vms->gic_version == 2) { | 70 | - if (rn == 31) { |
64 | + if (vms->gic_version == VIRT_GIC_VERSION_2) { | 71 | + if (a->rn == 31) { |
65 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | 72 | gen_check_sp_alignment(s); |
66 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | 73 | } |
67 | (1 << vms->smp_cpus) - 1); | 74 | - dirty_addr = read_cpu_reg_sp(s, rn, 1); |
68 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms) | 75 | + dirty_addr = read_cpu_reg_sp(s, a->rn, 1); |
69 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); | 76 | |
70 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); | 77 | if (s->pauth_active) { |
71 | qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); | 78 | - if (use_key_a) { |
72 | - if (vms->gic_version == 3) { | 79 | + if (!a->m) { |
73 | + if (vms->gic_version == VIRT_GIC_VERSION_3) { | 80 | gen_helper_autda(dirty_addr, cpu_env, dirty_addr, |
74 | int nb_redist_regions = virt_gicv3_redist_region_count(vms); | 81 | tcg_constant_i64(0)); |
75 | 82 | } else { | |
76 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | 83 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, |
77 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) | ||
78 | } | 84 | } |
79 | } | 85 | } |
80 | 86 | ||
81 | - if (vms->gic_version == 2) { | 87 | - /* Form the 10-bit signed, scaled offset. */ |
82 | + if (vms->gic_version == VIRT_GIC_VERSION_2) { | 88 | - offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); |
83 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | 89 | - offset = sextract32(offset << size, 0, 10 + size); |
84 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | 90 | - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
85 | (1 << vms->smp_cpus) - 1); | 91 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); |
86 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | 92 | |
87 | * purposes are to make TCG consistent (with 64-bit KVM hosts) | 93 | - memop = finalize_memop(s, size); |
88 | * and to improve SGI efficiency. | 94 | + memop = finalize_memop(s, MO_64); |
89 | */ | 95 | |
90 | - if (vms->gic_version == 3) { | 96 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ |
91 | + if (vms->gic_version == VIRT_GIC_VERSION_3) { | 97 | clean_addr = gen_mte_check1(s, dirty_addr, false, |
92 | clustersz = GICV3_TARGETLIST_BITS; | 98 | - is_wback || rn != 31, memop); |
93 | } else { | 99 | + a->w || a->rn != 31, memop); |
94 | clustersz = GIC_TARGETLIST_BITS; | 100 | |
95 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 101 | - tcg_rt = cpu_reg(s, rt); |
96 | /* We can probe only here because during property set | 102 | + tcg_rt = cpu_reg(s, a->rt); |
97 | * KVM is not available yet | 103 | do_gpr_ld(s, tcg_rt, clean_addr, memop, |
98 | */ | 104 | - /* extend */ false, /* iss_valid */ !is_wback, |
99 | - if (vms->gic_version <= 0) { | 105 | - /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); |
100 | - /* "host" or "max" */ | 106 | + /* extend */ false, /* iss_valid */ !a->w, |
101 | + if (vms->gic_version == VIRT_GIC_VERSION_HOST || | 107 | + /* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false); |
102 | + vms->gic_version == VIRT_GIC_VERSION_MAX) { | 108 | |
103 | if (!kvm_enabled()) { | 109 | - if (is_wback) { |
104 | - if (vms->gic_version == 0) { | 110 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
105 | + if (vms->gic_version == VIRT_GIC_VERSION_HOST) { | 111 | + if (a->w) { |
106 | error_report("gic-version=host requires KVM"); | 112 | + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); |
107 | exit(1); | 113 | } |
108 | } else { | 114 | + return true; |
109 | /* "max": currently means 3 for TCG */ | 115 | } |
110 | - vms->gic_version = 3; | 116 | |
111 | + vms->gic_version = VIRT_GIC_VERSION_3; | 117 | /* |
112 | } | 118 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) |
113 | } else { | 119 | } |
114 | vms->gic_version = kvm_arm_vgic_probe(); | 120 | } |
115 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 121 | |
116 | /* The maximum number of CPUs depends on the GIC version, or on how | 122 | -/* Load/store register (all forms) */ |
117 | * many redistributors we can fit into the memory map. | 123 | -static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
118 | */ | 124 | -{ |
119 | - if (vms->gic_version == 3) { | 125 | - int rt = extract32(insn, 0, 5); |
120 | + if (vms->gic_version == VIRT_GIC_VERSION_3) { | 126 | - bool is_vector = extract32(insn, 26, 1); |
121 | virt_max_cpus = | 127 | - int size = extract32(insn, 30, 2); |
122 | vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; | 128 | - |
123 | virt_max_cpus += | 129 | - switch (extract32(insn, 24, 2)) { |
124 | @@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp) | 130 | - case 0: |
125 | static char *virt_get_gic_version(Object *obj, Error **errp) | 131 | - if (extract32(insn, 21, 1) == 0) { |
132 | - break; | ||
133 | - } | ||
134 | - switch (extract32(insn, 10, 2)) { | ||
135 | - case 0: | ||
136 | - case 2: | ||
137 | - break; | ||
138 | - default: | ||
139 | - disas_ldst_pac(s, insn, size, rt, is_vector); | ||
140 | - return; | ||
141 | - } | ||
142 | - break; | ||
143 | - } | ||
144 | - unallocated_encoding(s); | ||
145 | -} | ||
146 | - | ||
147 | /* AdvSIMD load/store multiple structures | ||
148 | * | ||
149 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | ||
150 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
151 | static void disas_ldst(DisasContext *s, uint32_t insn) | ||
126 | { | 152 | { |
127 | VirtMachineState *vms = VIRT_MACHINE(obj); | 153 | switch (extract32(insn, 24, 6)) { |
128 | - const char *val = vms->gic_version == 3 ? "3" : "2"; | 154 | - case 0x38: case 0x39: |
129 | + const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; | 155 | - case 0x3c: case 0x3d: /* Load/store register (all forms) */ |
130 | 156 | - disas_ldst_reg(s, insn); | |
131 | return g_strdup(val); | 157 | - break; |
132 | } | 158 | case 0x0c: /* AdvSIMD load/store multiple structures */ |
133 | @@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp) | 159 | disas_ldst_multiple_struct(s, insn); |
134 | VirtMachineState *vms = VIRT_MACHINE(obj); | 160 | break; |
135 | |||
136 | if (!strcmp(value, "3")) { | ||
137 | - vms->gic_version = 3; | ||
138 | + vms->gic_version = VIRT_GIC_VERSION_3; | ||
139 | } else if (!strcmp(value, "2")) { | ||
140 | - vms->gic_version = 2; | ||
141 | + vms->gic_version = VIRT_GIC_VERSION_2; | ||
142 | } else if (!strcmp(value, "host")) { | ||
143 | - vms->gic_version = 0; /* Will probe later */ | ||
144 | + vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ | ||
145 | } else if (!strcmp(value, "max")) { | ||
146 | - vms->gic_version = -1; /* Will probe later */ | ||
147 | + vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ | ||
148 | } else { | ||
149 | error_setg(errp, "Invalid gic-version value"); | ||
150 | error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); | ||
151 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | ||
152 | "physical address space above 32 bits", | ||
153 | NULL); | ||
154 | /* Default GIC type is v2 */ | ||
155 | - vms->gic_version = 2; | ||
156 | + vms->gic_version = VIRT_GIC_VERSION_2; | ||
157 | object_property_add_str(obj, "gic-version", virt_get_gic_version, | ||
158 | virt_set_gic_version, NULL); | ||
159 | object_property_set_description(obj, "gic-version", | ||
160 | -- | 161 | -- |
161 | 2.20.1 | 162 | 2.34.1 |
162 | 163 | ||
163 | 164 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Convert the instructions in the LDAPR/STLR (unscaled immediate) |
---|---|---|---|
2 | group to decodetree. | ||
2 | 3 | ||
3 | The Aspeed SMC Controller can operate in different modes : Read, Fast | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Read, Write and User modes. When the User mode is configured, it | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | selects automatically the SPI slave device until the CE_STOP_ACTIVE | 6 | Message-id: 20230602155223.2040685-18-peter.maydell@linaro.org |
6 | bit is set to 1. When any other modes are configured the device is | 7 | --- |
7 | unselected. The HW logic handles the chip select automatically when | 8 | target/arm/tcg/a64.decode | 10 +++ |
8 | the flash is accessed through its AHB window. | 9 | target/arm/tcg/translate-a64.c | 132 ++++++++++++--------------------- |
10 | 2 files changed, 56 insertions(+), 86 deletions(-) | ||
9 | 11 | ||
10 | When configuring the CEx Control Register, the User mode logic to | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
11 | select and unselect the slave is incorrect and data corruption can be | ||
12 | seen on machines using two chips, witherspoon and romulus. | ||
13 | |||
14 | Rework the handler setting the CEx Control Register to fix this issue. | ||
15 | |||
16 | Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)") | ||
17 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
18 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | ||
19 | Message-id: 20200206112645.21275-3-clg@kaod.org | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | --- | ||
22 | hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++---------------- | ||
23 | hw/ssi/trace-events | 1 + | ||
24 | 2 files changed, 24 insertions(+), 16 deletions(-) | ||
25 | |||
26 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/ssi/aspeed_smc.c | 14 | --- a/target/arm/tcg/a64.decode |
29 | +++ b/hw/ssi/aspeed_smc.c | 15 | +++ b/target/arm/tcg/a64.decode |
30 | @@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl) | 16 | @@ -XXX,XX +XXX,XX @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 |
17 | %ldra_imm 22:s1 12:9 !function=times_2 | ||
18 | |||
19 | LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm | ||
20 | + | ||
21 | +&ldapr_stlr_i rn rt imm sz sign ext | ||
22 | +@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i | ||
23 | +STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 | ||
24 | +LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 | ||
25 | +LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 | ||
26 | +LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 | ||
27 | +LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 | ||
28 | +LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 | ||
29 | +LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 | ||
30 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/tcg/translate-a64.c | ||
33 | +++ b/target/arm/tcg/translate-a64.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
31 | } | 35 | } |
32 | } | 36 | } |
33 | 37 | ||
34 | -static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl) | 38 | -/* Update the Sixty-Four bit (SF) registersize. This logic is derived |
35 | +static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) | 39 | +/* |
40 | + * Compute the ISS.SF bit for syndrome information if an exception | ||
41 | + * is taken on a load or store. This indicates whether the instruction | ||
42 | + * is accessing a 32-bit or 64-bit register. This logic is derived | ||
43 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | ||
44 | */ | ||
45 | -static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | ||
46 | -{ | ||
47 | - int opc0 = extract32(opc, 0, 1); | ||
48 | - int regsize; | ||
49 | - | ||
50 | - if (is_signed) { | ||
51 | - regsize = opc0 ? 32 : 64; | ||
52 | - } else { | ||
53 | - regsize = size == 3 ? 64 : 32; | ||
54 | - } | ||
55 | - return regsize == 64; | ||
56 | -} | ||
57 | - | ||
58 | static bool ldst_iss_sf(int size, bool sign, bool ext) | ||
36 | { | 59 | { |
37 | - const AspeedSMCState *s = fl->controller; | 60 | |
38 | + AspeedSMCState *s = fl->controller; | 61 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a) |
39 | 62 | return true; | |
40 | - return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE; | ||
41 | + trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : ""); | ||
42 | + | ||
43 | + qemu_set_irq(s->cs_lines[fl->id], unselect); | ||
44 | } | 63 | } |
45 | 64 | ||
46 | static void aspeed_smc_flash_select(AspeedSMCFlash *fl) | 65 | -/* |
66 | - * LDAPR/STLR (unscaled immediate) | ||
67 | - * | ||
68 | - * 31 30 24 22 21 12 10 5 0 | ||
69 | - * +------+-------------+-----+---+--------+-----+----+-----+ | ||
70 | - * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | | ||
71 | - * +------+-------------+-----+---+--------+-----+----+-----+ | ||
72 | - * | ||
73 | - * Rt: source or destination register | ||
74 | - * Rn: base register | ||
75 | - * imm9: unscaled immediate offset | ||
76 | - * opc: 00: STLUR*, 01/10/11: various LDAPUR* | ||
77 | - * size: size of load/store | ||
78 | - */ | ||
79 | -static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | ||
80 | +static bool trans_LDAPR_i(DisasContext *s, arg_ldapr_stlr_i *a) | ||
47 | { | 81 | { |
48 | - AspeedSMCState *s = fl->controller; | 82 | - int rt = extract32(insn, 0, 5); |
49 | - | 83 | - int rn = extract32(insn, 5, 5); |
50 | - s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE; | 84 | - int offset = sextract32(insn, 12, 9); |
51 | - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); | 85 | - int opc = extract32(insn, 22, 2); |
52 | + aspeed_smc_flash_do_select(fl, false); | 86 | - int size = extract32(insn, 30, 2); |
87 | TCGv_i64 clean_addr, dirty_addr; | ||
88 | - bool is_store = false; | ||
89 | - bool extend = false; | ||
90 | - bool iss_sf; | ||
91 | - MemOp mop = size; | ||
92 | + MemOp mop = a->sz | (a->sign ? MO_SIGN : 0); | ||
93 | + bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext); | ||
94 | |||
95 | if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | ||
96 | - unallocated_encoding(s); | ||
97 | - return; | ||
98 | + return false; | ||
99 | } | ||
100 | |||
101 | - switch (opc) { | ||
102 | - case 0: /* STLURB */ | ||
103 | - is_store = true; | ||
104 | - break; | ||
105 | - case 1: /* LDAPUR* */ | ||
106 | - break; | ||
107 | - case 2: /* LDAPURS* 64-bit variant */ | ||
108 | - if (size == 3) { | ||
109 | - unallocated_encoding(s); | ||
110 | - return; | ||
111 | - } | ||
112 | - mop |= MO_SIGN; | ||
113 | - break; | ||
114 | - case 3: /* LDAPURS* 32-bit variant */ | ||
115 | - if (size > 1) { | ||
116 | - unallocated_encoding(s); | ||
117 | - return; | ||
118 | - } | ||
119 | - mop |= MO_SIGN; | ||
120 | - extend = true; /* zero-extend 32->64 after signed load */ | ||
121 | - break; | ||
122 | - default: | ||
123 | - g_assert_not_reached(); | ||
124 | - } | ||
125 | - | ||
126 | - iss_sf = disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) != 0, opc); | ||
127 | - | ||
128 | - if (rn == 31) { | ||
129 | + if (a->rn == 31) { | ||
130 | gen_check_sp_alignment(s); | ||
131 | } | ||
132 | |||
133 | - mop = check_ordered_align(s, rn, offset, is_store, mop); | ||
134 | - | ||
135 | - dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
136 | - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
137 | + mop = check_ordered_align(s, a->rn, a->imm, false, mop); | ||
138 | + dirty_addr = read_cpu_reg_sp(s, a->rn, 1); | ||
139 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); | ||
140 | clean_addr = clean_data_tbi(s, dirty_addr); | ||
141 | |||
142 | - if (is_store) { | ||
143 | - /* Store-Release semantics */ | ||
144 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
145 | - do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, true); | ||
146 | - } else { | ||
147 | - /* | ||
148 | - * Load-AcquirePC semantics; we implement as the slightly more | ||
149 | - * restrictive Load-Acquire. | ||
150 | - */ | ||
151 | - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, | ||
152 | - extend, true, rt, iss_sf, true); | ||
153 | - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
154 | + /* | ||
155 | + * Load-AcquirePC semantics; we implement as the slightly more | ||
156 | + * restrictive Load-Acquire. | ||
157 | + */ | ||
158 | + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, a->ext, true, | ||
159 | + a->rt, iss_sf, true); | ||
160 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
161 | + return true; | ||
162 | +} | ||
163 | + | ||
164 | +static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a) | ||
165 | +{ | ||
166 | + TCGv_i64 clean_addr, dirty_addr; | ||
167 | + MemOp mop = a->sz; | ||
168 | + bool iss_sf = ldst_iss_sf(a->sz, a->sign, a->ext); | ||
169 | + | ||
170 | + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | ||
171 | + return false; | ||
172 | } | ||
173 | + | ||
174 | + /* TODO: ARMv8.4-LSE SCTLR.nAA */ | ||
175 | + | ||
176 | + if (a->rn == 31) { | ||
177 | + gen_check_sp_alignment(s); | ||
178 | + } | ||
179 | + | ||
180 | + mop = check_ordered_align(s, a->rn, a->imm, true, mop); | ||
181 | + dirty_addr = read_cpu_reg_sp(s, a->rn, 1); | ||
182 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); | ||
183 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
184 | + | ||
185 | + /* Store-Release semantics */ | ||
186 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
187 | + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, mop, true, a->rt, iss_sf, true); | ||
188 | + return true; | ||
53 | } | 189 | } |
54 | 190 | ||
55 | static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) | 191 | /* AdvSIMD load/store multiple structures |
56 | { | 192 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn) |
57 | - AspeedSMCState *s = fl->controller; | 193 | case 0x19: |
58 | - | 194 | if (extract32(insn, 21, 1) != 0) { |
59 | - s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE; | 195 | disas_ldst_tag(s, insn); |
60 | - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); | 196 | - } else if (extract32(insn, 10, 2) == 0) { |
61 | + aspeed_smc_flash_do_select(fl, true); | 197 | - disas_ldst_ldapr_stlr(s, insn); |
62 | } | 198 | } else { |
63 | 199 | unallocated_encoding(s); | |
64 | static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, | 200 | } |
65 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = { | ||
66 | }, | ||
67 | }; | ||
68 | |||
69 | -static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl) | ||
70 | +static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) | ||
71 | { | ||
72 | AspeedSMCState *s = fl->controller; | ||
73 | + bool unselect; | ||
74 | |||
75 | - s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START; | ||
76 | + /* User mode selects the CS, other modes unselect */ | ||
77 | + unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE; | ||
78 | |||
79 | - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); | ||
80 | + /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ | ||
81 | + if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) && | ||
82 | + value & CTRL_CE_STOP_ACTIVE) { | ||
83 | + unselect = true; | ||
84 | + } | ||
85 | + | ||
86 | + s->regs[s->r_ctrl0 + fl->id] = value; | ||
87 | + | ||
88 | + s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; | ||
89 | + | ||
90 | + aspeed_smc_flash_do_select(fl, unselect); | ||
91 | } | ||
92 | |||
93 | static void aspeed_smc_reset(DeviceState *d) | ||
94 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, | ||
95 | s->regs[addr] = value; | ||
96 | } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { | ||
97 | int cs = addr - s->r_ctrl0; | ||
98 | - s->regs[addr] = value; | ||
99 | - aspeed_smc_flash_update_cs(&s->flashes[cs]); | ||
100 | + aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); | ||
101 | } else if (addr >= R_SEG_ADDR0 && | ||
102 | addr < R_SEG_ADDR0 + s->ctrl->max_slaves) { | ||
103 | int cs = addr - R_SEG_ADDR0; | ||
104 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/hw/ssi/trace-events | ||
107 | +++ b/hw/ssi/trace-events | ||
108 | @@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int | ||
109 | aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 | ||
110 | aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" | ||
111 | aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 | ||
112 | +aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" | ||
113 | -- | 201 | -- |
114 | 2.20.1 | 202 | 2.34.1 |
115 | |||
116 | diff view generated by jsdifflib |
1 | Some of an M-profile CPU's cached hflags state depends on state that's | 1 | Convert the instructions in the ASIMD load/store multiple structures |
---|---|---|---|
2 | in our NVIC object. We already do an hflags rebuild when the NVIC | 2 | instruction classes to decodetree. |
3 | registers are written, but we also need to do this on NVIC reset, | ||
4 | because there's no guarantee that this will happen before the | ||
5 | CPU reset. | ||
6 | |||
7 | This fixes an assertion due to mismatched hflags which happens if | ||
8 | the CPU is reset from inside a HardFault handler. | ||
9 | 3 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20200303174950.3298-2-peter.maydell@linaro.org | 6 | Message-id: 20230602155223.2040685-19-peter.maydell@linaro.org |
13 | --- | 7 | --- |
14 | hw/intc/armv7m_nvic.c | 6 ++++++ | 8 | target/arm/tcg/a64.decode | 20 +++ |
15 | 1 file changed, 6 insertions(+) | 9 | target/arm/tcg/translate-a64.c | 222 ++++++++++++++++----------------- |
10 | 2 files changed, 131 insertions(+), 111 deletions(-) | ||
16 | 11 | ||
17 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
18 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/intc/armv7m_nvic.c | 14 | --- a/target/arm/tcg/a64.decode |
20 | +++ b/hw/intc/armv7m_nvic.c | 15 | +++ b/target/arm/tcg/a64.decode |
21 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev) | 16 | @@ -XXX,XX +XXX,XX @@ LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext |
22 | s->itns[i] = true; | 17 | LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 |
18 | LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 | ||
19 | LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 | ||
20 | + | ||
21 | +# Load/store multiple structures | ||
22 | +# The 4-bit opcode in [15:12] encodes repeat count and structure elements | ||
23 | +&ldst_mult rm rn rt sz q p rpt selem | ||
24 | +@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult | ||
25 | +ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 | ||
26 | +ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 | ||
27 | +ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 | ||
28 | +ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 | ||
29 | +ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 | ||
30 | +ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 | ||
31 | +ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 | ||
32 | + | ||
33 | +LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 | ||
34 | +LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 | ||
35 | +LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 | ||
36 | +LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 | ||
37 | +LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 | ||
38 | +LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 | ||
39 | +LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 | ||
40 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/tcg/translate-a64.c | ||
43 | +++ b/target/arm/tcg/translate-a64.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a) | ||
45 | return true; | ||
46 | } | ||
47 | |||
48 | -/* AdvSIMD load/store multiple structures | ||
49 | - * | ||
50 | - * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | ||
51 | - * +---+---+---------------+---+-------------+--------+------+------+------+ | ||
52 | - * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | ||
53 | - * +---+---+---------------+---+-------------+--------+------+------+------+ | ||
54 | - * | ||
55 | - * AdvSIMD load/store multiple structures (post-indexed) | ||
56 | - * | ||
57 | - * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | ||
58 | - * +---+---+---------------+---+---+---------+--------+------+------+------+ | ||
59 | - * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | ||
60 | - * +---+---+---------------+---+---+---------+--------+------+------+------+ | ||
61 | - * | ||
62 | - * Rt: first (or only) SIMD&FP register to be transferred | ||
63 | - * Rn: base address or SP | ||
64 | - * Rm (post-index only): post-index register (when !31) or size dependent #imm | ||
65 | - */ | ||
66 | -static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
67 | +static bool trans_LD_mult(DisasContext *s, arg_ldst_mult *a) | ||
68 | { | ||
69 | - int rt = extract32(insn, 0, 5); | ||
70 | - int rn = extract32(insn, 5, 5); | ||
71 | - int rm = extract32(insn, 16, 5); | ||
72 | - int size = extract32(insn, 10, 2); | ||
73 | - int opcode = extract32(insn, 12, 4); | ||
74 | - bool is_store = !extract32(insn, 22, 1); | ||
75 | - bool is_postidx = extract32(insn, 23, 1); | ||
76 | - bool is_q = extract32(insn, 30, 1); | ||
77 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | ||
78 | MemOp endian, align, mop; | ||
79 | |||
80 | int total; /* total bytes */ | ||
81 | int elements; /* elements per vector */ | ||
82 | - int rpt; /* num iterations */ | ||
83 | - int selem; /* structure elements */ | ||
84 | int r; | ||
85 | + int size = a->sz; | ||
86 | |||
87 | - if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | ||
88 | - unallocated_encoding(s); | ||
89 | - return; | ||
90 | + if (!a->p && a->rm != 0) { | ||
91 | + /* For non-postindexed accesses the Rm field must be 0 */ | ||
92 | + return false; | ||
93 | } | ||
94 | - | ||
95 | - if (!is_postidx && rm != 0) { | ||
96 | - unallocated_encoding(s); | ||
97 | - return; | ||
98 | + if (size == 3 && !a->q && a->selem != 1) { | ||
99 | + return false; | ||
100 | } | ||
101 | - | ||
102 | - /* From the shared decode logic */ | ||
103 | - switch (opcode) { | ||
104 | - case 0x0: | ||
105 | - rpt = 1; | ||
106 | - selem = 4; | ||
107 | - break; | ||
108 | - case 0x2: | ||
109 | - rpt = 4; | ||
110 | - selem = 1; | ||
111 | - break; | ||
112 | - case 0x4: | ||
113 | - rpt = 1; | ||
114 | - selem = 3; | ||
115 | - break; | ||
116 | - case 0x6: | ||
117 | - rpt = 3; | ||
118 | - selem = 1; | ||
119 | - break; | ||
120 | - case 0x7: | ||
121 | - rpt = 1; | ||
122 | - selem = 1; | ||
123 | - break; | ||
124 | - case 0x8: | ||
125 | - rpt = 1; | ||
126 | - selem = 2; | ||
127 | - break; | ||
128 | - case 0xa: | ||
129 | - rpt = 2; | ||
130 | - selem = 1; | ||
131 | - break; | ||
132 | - default: | ||
133 | - unallocated_encoding(s); | ||
134 | - return; | ||
135 | - } | ||
136 | - | ||
137 | - if (size == 3 && !is_q && selem != 1) { | ||
138 | - /* reserved */ | ||
139 | - unallocated_encoding(s); | ||
140 | - return; | ||
141 | - } | ||
142 | - | ||
143 | if (!fp_access_check(s)) { | ||
144 | - return; | ||
145 | + return true; | ||
146 | } | ||
147 | |||
148 | - if (rn == 31) { | ||
149 | + if (a->rn == 31) { | ||
150 | gen_check_sp_alignment(s); | ||
151 | } | ||
152 | |||
153 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
154 | endian = MO_LE; | ||
155 | } | ||
156 | |||
157 | - total = rpt * selem * (is_q ? 16 : 8); | ||
158 | - tcg_rn = cpu_reg_sp(s, rn); | ||
159 | + total = a->rpt * a->selem * (a->q ? 16 : 8); | ||
160 | + tcg_rn = cpu_reg_sp(s, a->rn); | ||
161 | |||
162 | /* | ||
163 | * Issue the MTE check vs the logical repeat count, before we | ||
164 | * promote consecutive little-endian elements below. | ||
165 | */ | ||
166 | - clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, | ||
167 | - total, finalize_memop_asimd(s, size)); | ||
168 | + clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, total, | ||
169 | + finalize_memop_asimd(s, size)); | ||
170 | |||
171 | /* | ||
172 | * Consecutive little-endian elements from a single register | ||
173 | * can be promoted to a larger little-endian operation. | ||
174 | */ | ||
175 | align = MO_ALIGN; | ||
176 | - if (selem == 1 && endian == MO_LE) { | ||
177 | + if (a->selem == 1 && endian == MO_LE) { | ||
178 | align = pow2_align(size); | ||
179 | size = 3; | ||
180 | } | ||
181 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
182 | } | ||
183 | mop = endian | size | align; | ||
184 | |||
185 | - elements = (is_q ? 16 : 8) >> size; | ||
186 | + elements = (a->q ? 16 : 8) >> size; | ||
187 | tcg_ebytes = tcg_constant_i64(1 << size); | ||
188 | - for (r = 0; r < rpt; r++) { | ||
189 | + for (r = 0; r < a->rpt; r++) { | ||
190 | int e; | ||
191 | for (e = 0; e < elements; e++) { | ||
192 | int xs; | ||
193 | - for (xs = 0; xs < selem; xs++) { | ||
194 | - int tt = (rt + r + xs) % 32; | ||
195 | - if (is_store) { | ||
196 | - do_vec_st(s, tt, e, clean_addr, mop); | ||
197 | - } else { | ||
198 | - do_vec_ld(s, tt, e, clean_addr, mop); | ||
199 | - } | ||
200 | + for (xs = 0; xs < a->selem; xs++) { | ||
201 | + int tt = (a->rt + r + xs) % 32; | ||
202 | + do_vec_ld(s, tt, e, clean_addr, mop); | ||
203 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
204 | } | ||
23 | } | 205 | } |
24 | } | 206 | } |
25 | + | 207 | |
208 | - if (!is_store) { | ||
209 | - /* For non-quad operations, setting a slice of the low | ||
210 | - * 64 bits of the register clears the high 64 bits (in | ||
211 | - * the ARM ARM pseudocode this is implicit in the fact | ||
212 | - * that 'rval' is a 64 bit wide variable). | ||
213 | - * For quad operations, we might still need to zero the | ||
214 | - * high bits of SVE. | ||
215 | - */ | ||
216 | - for (r = 0; r < rpt * selem; r++) { | ||
217 | - int tt = (rt + r) % 32; | ||
218 | - clear_vec_high(s, is_q, tt); | ||
26 | + /* | 219 | + /* |
27 | + * We updated state that affects the CPU's MMUidx and thus its hflags; | 220 | + * For non-quad operations, setting a slice of the low 64 bits of |
28 | + * and we can't guarantee that we run before the CPU reset function. | 221 | + * the register clears the high 64 bits (in the ARM ARM pseudocode |
222 | + * this is implicit in the fact that 'rval' is a 64 bit wide | ||
223 | + * variable). For quad operations, we might still need to zero | ||
224 | + * the high bits of SVE. | ||
29 | + */ | 225 | + */ |
30 | + arm_rebuild_hflags(&s->cpu->env); | 226 | + for (r = 0; r < a->rpt * a->selem; r++) { |
227 | + int tt = (a->rt + r) % 32; | ||
228 | + clear_vec_high(s, a->q, tt); | ||
229 | + } | ||
230 | + | ||
231 | + if (a->p) { | ||
232 | + if (a->rm == 31) { | ||
233 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); | ||
234 | + } else { | ||
235 | + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); | ||
236 | + } | ||
237 | + } | ||
238 | + return true; | ||
239 | +} | ||
240 | + | ||
241 | +static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a) | ||
242 | +{ | ||
243 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | ||
244 | + MemOp endian, align, mop; | ||
245 | + | ||
246 | + int total; /* total bytes */ | ||
247 | + int elements; /* elements per vector */ | ||
248 | + int r; | ||
249 | + int size = a->sz; | ||
250 | + | ||
251 | + if (!a->p && a->rm != 0) { | ||
252 | + /* For non-postindexed accesses the Rm field must be 0 */ | ||
253 | + return false; | ||
254 | + } | ||
255 | + if (size == 3 && !a->q && a->selem != 1) { | ||
256 | + return false; | ||
257 | + } | ||
258 | + if (!fp_access_check(s)) { | ||
259 | + return true; | ||
260 | + } | ||
261 | + | ||
262 | + if (a->rn == 31) { | ||
263 | + gen_check_sp_alignment(s); | ||
264 | + } | ||
265 | + | ||
266 | + /* For our purposes, bytes are always little-endian. */ | ||
267 | + endian = s->be_data; | ||
268 | + if (size == 0) { | ||
269 | + endian = MO_LE; | ||
270 | + } | ||
271 | + | ||
272 | + total = a->rpt * a->selem * (a->q ? 16 : 8); | ||
273 | + tcg_rn = cpu_reg_sp(s, a->rn); | ||
274 | + | ||
275 | + /* | ||
276 | + * Issue the MTE check vs the logical repeat count, before we | ||
277 | + * promote consecutive little-endian elements below. | ||
278 | + */ | ||
279 | + clean_addr = gen_mte_checkN(s, tcg_rn, true, a->p || a->rn != 31, total, | ||
280 | + finalize_memop_asimd(s, size)); | ||
281 | + | ||
282 | + /* | ||
283 | + * Consecutive little-endian elements from a single register | ||
284 | + * can be promoted to a larger little-endian operation. | ||
285 | + */ | ||
286 | + align = MO_ALIGN; | ||
287 | + if (a->selem == 1 && endian == MO_LE) { | ||
288 | + align = pow2_align(size); | ||
289 | + size = 3; | ||
290 | + } | ||
291 | + if (!s->align_mem) { | ||
292 | + align = 0; | ||
293 | + } | ||
294 | + mop = endian | size | align; | ||
295 | + | ||
296 | + elements = (a->q ? 16 : 8) >> size; | ||
297 | + tcg_ebytes = tcg_constant_i64(1 << size); | ||
298 | + for (r = 0; r < a->rpt; r++) { | ||
299 | + int e; | ||
300 | + for (e = 0; e < elements; e++) { | ||
301 | + int xs; | ||
302 | + for (xs = 0; xs < a->selem; xs++) { | ||
303 | + int tt = (a->rt + r + xs) % 32; | ||
304 | + do_vec_st(s, tt, e, clean_addr, mop); | ||
305 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
306 | + } | ||
307 | } | ||
308 | } | ||
309 | |||
310 | - if (is_postidx) { | ||
311 | - if (rm == 31) { | ||
312 | + if (a->p) { | ||
313 | + if (a->rm == 31) { | ||
314 | tcg_gen_addi_i64(tcg_rn, tcg_rn, total); | ||
315 | } else { | ||
316 | - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | ||
317 | + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); | ||
318 | } | ||
319 | } | ||
320 | + return true; | ||
31 | } | 321 | } |
32 | 322 | ||
33 | static void nvic_systick_trigger(void *opaque, int n, int level) | 323 | /* AdvSIMD load/store single structure |
324 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
325 | static void disas_ldst(DisasContext *s, uint32_t insn) | ||
326 | { | ||
327 | switch (extract32(insn, 24, 6)) { | ||
328 | - case 0x0c: /* AdvSIMD load/store multiple structures */ | ||
329 | - disas_ldst_multiple_struct(s, insn); | ||
330 | - break; | ||
331 | case 0x0d: /* AdvSIMD load/store single structure */ | ||
332 | disas_ldst_single_struct(s, insn); | ||
333 | break; | ||
34 | -- | 334 | -- |
35 | 2.20.1 | 335 | 2.34.1 |
36 | |||
37 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert the ASIMD load/store single structure insns to decodetree. |
---|---|---|---|
2 | 2 | ||
3 | In the Allwinner H3 SoC the SDRAM controller is responsible | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | for interfacing with the external Synchronous Dynamic Random | 4 | Message-id: 20230602155223.2040685-20-peter.maydell@linaro.org |
5 | Access Memory (SDRAM). Types of memory that the SDRAM controller | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | supports are DDR2/DDR3 and capacities of up to 2GiB. This commit | 6 | --- |
7 | adds emulation support of the Allwinner H3 SDRAM controller. | 7 | target/arm/tcg/a64.decode | 34 +++++ |
8 | target/arm/tcg/translate-a64.c | 219 +++++++++++++++------------------ | ||
9 | 2 files changed, 136 insertions(+), 117 deletions(-) | ||
8 | 10 | ||
9 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 11 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/misc/Makefile.objs | 1 + | ||
15 | include/hw/arm/allwinner-h3.h | 5 + | ||
16 | include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++ | ||
17 | hw/arm/allwinner-h3.c | 19 +- | ||
18 | hw/arm/orangepi.c | 6 + | ||
19 | hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++ | ||
20 | hw/misc/trace-events | 10 + | ||
21 | 7 files changed, 502 insertions(+), 3 deletions(-) | ||
22 | create mode 100644 include/hw/misc/allwinner-h3-dramc.h | ||
23 | create mode 100644 hw/misc/allwinner-h3-dramc.c | ||
24 | |||
25 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
26 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/misc/Makefile.objs | 13 | --- a/target/arm/tcg/a64.decode |
28 | +++ b/hw/misc/Makefile.objs | 14 | +++ b/target/arm/tcg/a64.decode |
29 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o | 15 | @@ -XXX,XX +XXX,XX @@ LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 sele |
30 | 16 | LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 | |
31 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o | 17 | LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 |
32 | obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o | 18 | LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 |
33 | +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o | 19 | + |
34 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o | 20 | +# Load/store single structure |
35 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o | 21 | +&ldst_single rm rn rt p selem index scale |
36 | common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o | 22 | + |
37 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 23 | +%ldst_single_selem 13:1 21:1 !function=plus_1 |
24 | + | ||
25 | +%ldst_single_index_b 30:1 10:3 | ||
26 | +%ldst_single_index_h 30:1 11:2 | ||
27 | +%ldst_single_index_s 30:1 12:1 | ||
28 | + | ||
29 | +@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ | ||
30 | + &ldst_single scale=0 selem=%ldst_single_selem \ | ||
31 | + index=%ldst_single_index_b | ||
32 | +@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ | ||
33 | + &ldst_single scale=1 selem=%ldst_single_selem \ | ||
34 | + index=%ldst_single_index_h | ||
35 | +@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ | ||
36 | + &ldst_single scale=2 selem=%ldst_single_selem \ | ||
37 | + index=%ldst_single_index_s | ||
38 | +@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ | ||
39 | + &ldst_single scale=3 selem=%ldst_single_selem | ||
40 | + | ||
41 | +ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b | ||
42 | +ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h | ||
43 | +ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s | ||
44 | +ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d | ||
45 | + | ||
46 | +LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b | ||
47 | +LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h | ||
48 | +LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s | ||
49 | +LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d | ||
50 | + | ||
51 | +# Replicating load case | ||
52 | +LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem | ||
53 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/include/hw/arm/allwinner-h3.h | 55 | --- a/target/arm/tcg/translate-a64.c |
40 | +++ b/include/hw/arm/allwinner-h3.h | 56 | +++ b/target/arm/tcg/translate-a64.c |
41 | @@ -XXX,XX +XXX,XX @@ | 57 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a) |
42 | #include "hw/intc/arm_gic.h" | 58 | return true; |
43 | #include "hw/misc/allwinner-h3-ccu.h" | ||
44 | #include "hw/misc/allwinner-cpucfg.h" | ||
45 | +#include "hw/misc/allwinner-h3-dramc.h" | ||
46 | #include "hw/misc/allwinner-h3-sysctrl.h" | ||
47 | #include "hw/misc/allwinner-sid.h" | ||
48 | #include "hw/sd/allwinner-sdhost.h" | ||
49 | @@ -XXX,XX +XXX,XX @@ enum { | ||
50 | AW_H3_UART2, | ||
51 | AW_H3_UART3, | ||
52 | AW_H3_EMAC, | ||
53 | + AW_H3_DRAMCOM, | ||
54 | + AW_H3_DRAMCTL, | ||
55 | + AW_H3_DRAMPHY, | ||
56 | AW_H3_GIC_DIST, | ||
57 | AW_H3_GIC_CPU, | ||
58 | AW_H3_GIC_HYP, | ||
59 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
60 | AwA10PITState timer; | ||
61 | AwH3ClockCtlState ccu; | ||
62 | AwCpuCfgState cpucfg; | ||
63 | + AwH3DramCtlState dramc; | ||
64 | AwH3SysCtrlState sysctrl; | ||
65 | AwSidState sid; | ||
66 | AwSdHostState mmc0; | ||
67 | diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h | ||
68 | new file mode 100644 | ||
69 | index XXXXXXX..XXXXXXX | ||
70 | --- /dev/null | ||
71 | +++ b/include/hw/misc/allwinner-h3-dramc.h | ||
72 | @@ -XXX,XX +XXX,XX @@ | ||
73 | +/* | ||
74 | + * Allwinner H3 SDRAM Controller emulation | ||
75 | + * | ||
76 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
77 | + * | ||
78 | + * This program is free software: you can redistribute it and/or modify | ||
79 | + * it under the terms of the GNU General Public License as published by | ||
80 | + * the Free Software Foundation, either version 2 of the License, or | ||
81 | + * (at your option) any later version. | ||
82 | + * | ||
83 | + * This program is distributed in the hope that it will be useful, | ||
84 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
85 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
86 | + * GNU General Public License for more details. | ||
87 | + * | ||
88 | + * You should have received a copy of the GNU General Public License | ||
89 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
90 | + */ | ||
91 | + | ||
92 | +#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H | ||
93 | +#define HW_MISC_ALLWINNER_H3_DRAMC_H | ||
94 | + | ||
95 | +#include "qom/object.h" | ||
96 | +#include "hw/sysbus.h" | ||
97 | +#include "exec/hwaddr.h" | ||
98 | + | ||
99 | +/** | ||
100 | + * Constants | ||
101 | + * @{ | ||
102 | + */ | ||
103 | + | ||
104 | +/** Highest register address used by DRAMCOM module */ | ||
105 | +#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804) | ||
106 | + | ||
107 | +/** Total number of known DRAMCOM registers */ | ||
108 | +#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \ | ||
109 | + sizeof(uint32_t)) | ||
110 | + | ||
111 | +/** Highest register address used by DRAMCTL module */ | ||
112 | +#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c) | ||
113 | + | ||
114 | +/** Total number of known DRAMCTL registers */ | ||
115 | +#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \ | ||
116 | + sizeof(uint32_t)) | ||
117 | + | ||
118 | +/** Highest register address used by DRAMPHY module */ | ||
119 | +#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4) | ||
120 | + | ||
121 | +/** Total number of known DRAMPHY registers */ | ||
122 | +#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \ | ||
123 | + sizeof(uint32_t)) | ||
124 | + | ||
125 | +/** @} */ | ||
126 | + | ||
127 | +/** | ||
128 | + * Object model | ||
129 | + * @{ | ||
130 | + */ | ||
131 | + | ||
132 | +#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc" | ||
133 | +#define AW_H3_DRAMC(obj) \ | ||
134 | + OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC) | ||
135 | + | ||
136 | +/** @} */ | ||
137 | + | ||
138 | +/** | ||
139 | + * Allwinner H3 SDRAM Controller object instance state. | ||
140 | + */ | ||
141 | +typedef struct AwH3DramCtlState { | ||
142 | + /*< private >*/ | ||
143 | + SysBusDevice parent_obj; | ||
144 | + /*< public >*/ | ||
145 | + | ||
146 | + /** Physical base address for start of RAM */ | ||
147 | + hwaddr ram_addr; | ||
148 | + | ||
149 | + /** Total RAM size in megabytes */ | ||
150 | + uint32_t ram_size; | ||
151 | + | ||
152 | + /** | ||
153 | + * @name Memory Regions | ||
154 | + * @{ | ||
155 | + */ | ||
156 | + | ||
157 | + MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */ | ||
158 | + MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */ | ||
159 | + MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */ | ||
160 | + MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */ | ||
161 | + MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */ | ||
162 | + | ||
163 | + /** @} */ | ||
164 | + | ||
165 | + /** | ||
166 | + * @name Hardware Registers | ||
167 | + * @{ | ||
168 | + */ | ||
169 | + | ||
170 | + uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */ | ||
171 | + uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */ | ||
172 | + uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */ | ||
173 | + | ||
174 | + /** @} */ | ||
175 | + | ||
176 | +} AwH3DramCtlState; | ||
177 | + | ||
178 | +#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */ | ||
179 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
180 | index XXXXXXX..XXXXXXX 100644 | ||
181 | --- a/hw/arm/allwinner-h3.c | ||
182 | +++ b/hw/arm/allwinner-h3.c | ||
183 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
184 | [AW_H3_UART2] = 0x01c28800, | ||
185 | [AW_H3_UART3] = 0x01c28c00, | ||
186 | [AW_H3_EMAC] = 0x01c30000, | ||
187 | + [AW_H3_DRAMCOM] = 0x01c62000, | ||
188 | + [AW_H3_DRAMCTL] = 0x01c63000, | ||
189 | + [AW_H3_DRAMPHY] = 0x01c65000, | ||
190 | [AW_H3_GIC_DIST] = 0x01c81000, | ||
191 | [AW_H3_GIC_CPU] = 0x01c82000, | ||
192 | [AW_H3_GIC_HYP] = 0x01c84000, | ||
193 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
194 | { "scr", 0x01c2c400, 1 * KiB }, | ||
195 | { "gpu", 0x01c40000, 64 * KiB }, | ||
196 | { "hstmr", 0x01c60000, 4 * KiB }, | ||
197 | - { "dramcom", 0x01c62000, 4 * KiB }, | ||
198 | - { "dramctl0", 0x01c63000, 4 * KiB }, | ||
199 | - { "dramphy0", 0x01c65000, 4 * KiB }, | ||
200 | { "spi0", 0x01c68000, 4 * KiB }, | ||
201 | { "spi1", 0x01c69000, 4 * KiB }, | ||
202 | { "csi", 0x01cb0000, 320 * KiB }, | ||
203 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
204 | |||
205 | sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), | ||
206 | TYPE_AW_SUN8I_EMAC); | ||
207 | + | ||
208 | + sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc), | ||
209 | + TYPE_AW_H3_DRAMC); | ||
210 | + object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc), | ||
211 | + "ram-addr", &error_abort); | ||
212 | + object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc), | ||
213 | + "ram-size", &error_abort); | ||
214 | } | 59 | } |
215 | 60 | ||
216 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 61 | -/* AdvSIMD load/store single structure |
217 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 62 | - * |
218 | qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3), | 63 | - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 |
219 | 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); | 64 | - * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
220 | 65 | - * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
221 | + /* DRAMC */ | 66 | - * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
222 | + qdev_init_nofail(DEVICE(&s->dramc)); | 67 | - * |
223 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]); | 68 | - * AdvSIMD load/store single structure (post-indexed) |
224 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]); | 69 | - * |
225 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]); | 70 | - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 |
226 | + | 71 | - * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
227 | /* Unimplemented devices */ | 72 | - * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | |
228 | for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { | 73 | - * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
229 | create_unimplemented_device(unimplemented[i].device_name, | 74 | - * |
230 | diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c | 75 | - * Rt: first (or only) SIMD&FP register to be transferred |
231 | index XXXXXXX..XXXXXXX 100644 | 76 | - * Rn: base address or SP |
232 | --- a/hw/arm/orangepi.c | 77 | - * Rm (post-index only): post-index register (when !31) or size dependent #imm |
233 | +++ b/hw/arm/orangepi.c | 78 | - * index = encoded in Q:S:size dependent on size |
234 | @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) | 79 | - * |
235 | /* Setup EMAC properties */ | 80 | - * lane_size = encoded in R, opc |
236 | object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort); | 81 | - * transfer width = encoded in opc, S, size |
237 | 82 | - */ | |
238 | + /* DRAMC */ | 83 | -static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
239 | + object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM], | 84 | +static bool trans_ST_single(DisasContext *s, arg_ldst_single *a) |
240 | + "ram-addr", &error_abort); | 85 | { |
241 | + object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size", | 86 | - int rt = extract32(insn, 0, 5); |
242 | + &error_abort); | 87 | - int rn = extract32(insn, 5, 5); |
243 | + | 88 | - int rm = extract32(insn, 16, 5); |
244 | /* Mark H3 object realized */ | 89 | - int size = extract32(insn, 10, 2); |
245 | object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); | 90 | - int S = extract32(insn, 12, 1); |
246 | 91 | - int opc = extract32(insn, 13, 3); | |
247 | diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c | 92 | - int R = extract32(insn, 21, 1); |
248 | new file mode 100644 | 93 | - int is_load = extract32(insn, 22, 1); |
249 | index XXXXXXX..XXXXXXX | 94 | - int is_postidx = extract32(insn, 23, 1); |
250 | --- /dev/null | 95 | - int is_q = extract32(insn, 30, 1); |
251 | +++ b/hw/misc/allwinner-h3-dramc.c | 96 | - |
252 | @@ -XXX,XX +XXX,XX @@ | 97 | - int scale = extract32(opc, 1, 2); |
253 | +/* | 98 | - int selem = (extract32(opc, 0, 1) << 1 | R) + 1; |
254 | + * Allwinner H3 SDRAM Controller emulation | 99 | - bool replicate = false; |
255 | + * | 100 | - int index = is_q << 3 | S << 2 | size; |
256 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | 101 | - int xs, total; |
257 | + * | 102 | + int xs, total, rt; |
258 | + * This program is free software: you can redistribute it and/or modify | 103 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
259 | + * it under the terms of the GNU General Public License as published by | 104 | MemOp mop; |
260 | + * the Free Software Foundation, either version 2 of the License, or | 105 | |
261 | + * (at your option) any later version. | 106 | - if (extract32(insn, 31, 1)) { |
262 | + * | 107 | - unallocated_encoding(s); |
263 | + * This program is distributed in the hope that it will be useful, | 108 | - return; |
264 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 109 | + if (!a->p && a->rm != 0) { |
265 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 110 | + return false; |
266 | + * GNU General Public License for more details. | 111 | } |
267 | + * | 112 | - if (!is_postidx && rm != 0) { |
268 | + * You should have received a copy of the GNU General Public License | 113 | - unallocated_encoding(s); |
269 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | 114 | - return; |
270 | + */ | 115 | - } |
271 | + | 116 | - |
272 | +#include "qemu/osdep.h" | 117 | - switch (scale) { |
273 | +#include "qemu/units.h" | 118 | - case 3: |
274 | +#include "qemu/error-report.h" | 119 | - if (!is_load || S) { |
275 | +#include "hw/sysbus.h" | 120 | - unallocated_encoding(s); |
276 | +#include "migration/vmstate.h" | 121 | - return; |
277 | +#include "qemu/log.h" | 122 | - } |
278 | +#include "qemu/module.h" | 123 | - scale = size; |
279 | +#include "exec/address-spaces.h" | 124 | - replicate = true; |
280 | +#include "hw/qdev-properties.h" | 125 | - break; |
281 | +#include "qapi/error.h" | 126 | - case 0: |
282 | +#include "hw/misc/allwinner-h3-dramc.h" | 127 | - break; |
283 | +#include "trace.h" | 128 | - case 1: |
284 | + | 129 | - if (extract32(size, 0, 1)) { |
285 | +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) | 130 | - unallocated_encoding(s); |
286 | + | 131 | - return; |
287 | +/* DRAMCOM register offsets */ | 132 | - } |
288 | +enum { | 133 | - index >>= 1; |
289 | + REG_DRAMCOM_CR = 0x0000, /* Control Register */ | 134 | - break; |
290 | +}; | 135 | - case 2: |
291 | + | 136 | - if (extract32(size, 1, 1)) { |
292 | +/* DRAMCTL register offsets */ | 137 | - unallocated_encoding(s); |
293 | +enum { | 138 | - return; |
294 | + REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */ | 139 | - } |
295 | + REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */ | 140 | - if (!extract32(size, 0, 1)) { |
296 | + REG_DRAMCTL_STATR = 0x0018, /* Status Register */ | 141 | - index >>= 2; |
297 | +}; | 142 | - } else { |
298 | + | 143 | - if (S) { |
299 | +/* DRAMCTL register flags */ | 144 | - unallocated_encoding(s); |
300 | +enum { | 145 | - return; |
301 | + REG_DRAMCTL_PGSR_INITDONE = (1 << 0), | 146 | - } |
302 | +}; | 147 | - index >>= 3; |
303 | + | 148 | - scale = 3; |
304 | +enum { | 149 | - } |
305 | + REG_DRAMCTL_STATR_ACTIVE = (1 << 0), | 150 | - break; |
306 | +}; | 151 | - default: |
307 | + | 152 | - g_assert_not_reached(); |
308 | +static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits, | 153 | - } |
309 | + uint8_t bank_bits, uint16_t page_size) | 154 | - |
155 | if (!fp_access_check(s)) { | ||
156 | - return; | ||
157 | + return true; | ||
158 | } | ||
159 | |||
160 | - if (rn == 31) { | ||
161 | + if (a->rn == 31) { | ||
162 | gen_check_sp_alignment(s); | ||
163 | } | ||
164 | |||
165 | - total = selem << scale; | ||
166 | - tcg_rn = cpu_reg_sp(s, rn); | ||
167 | + total = a->selem << a->scale; | ||
168 | + tcg_rn = cpu_reg_sp(s, a->rn); | ||
169 | |||
170 | - mop = finalize_memop_asimd(s, scale); | ||
171 | - | ||
172 | - clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, | ||
173 | + mop = finalize_memop_asimd(s, a->scale); | ||
174 | + clean_addr = gen_mte_checkN(s, tcg_rn, true, a->p || a->rn != 31, | ||
175 | total, mop); | ||
176 | |||
177 | - tcg_ebytes = tcg_constant_i64(1 << scale); | ||
178 | - for (xs = 0; xs < selem; xs++) { | ||
179 | - if (replicate) { | ||
180 | - /* Load and replicate to all elements */ | ||
181 | - TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | ||
182 | - | ||
183 | - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); | ||
184 | - tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), | ||
185 | - (is_q + 1) * 8, vec_full_reg_size(s), | ||
186 | - tcg_tmp); | ||
187 | - } else { | ||
188 | - /* Load/store one element per register */ | ||
189 | - if (is_load) { | ||
190 | - do_vec_ld(s, rt, index, clean_addr, mop); | ||
191 | - } else { | ||
192 | - do_vec_st(s, rt, index, clean_addr, mop); | ||
193 | - } | ||
194 | - } | ||
195 | + tcg_ebytes = tcg_constant_i64(1 << a->scale); | ||
196 | + for (xs = 0, rt = a->rt; xs < a->selem; xs++, rt = (rt + 1) % 32) { | ||
197 | + do_vec_st(s, rt, a->index, clean_addr, mop); | ||
198 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
199 | - rt = (rt + 1) % 32; | ||
200 | } | ||
201 | |||
202 | - if (is_postidx) { | ||
203 | - if (rm == 31) { | ||
204 | + if (a->p) { | ||
205 | + if (a->rm == 31) { | ||
206 | tcg_gen_addi_i64(tcg_rn, tcg_rn, total); | ||
207 | } else { | ||
208 | - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | ||
209 | + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); | ||
210 | } | ||
211 | } | ||
212 | + return true; | ||
213 | +} | ||
214 | + | ||
215 | +static bool trans_LD_single(DisasContext *s, arg_ldst_single *a) | ||
310 | +{ | 216 | +{ |
311 | + /* | 217 | + int xs, total, rt; |
312 | + * This function simulates row addressing behavior when bootloader | 218 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
313 | + * software attempts to detect the amount of available SDRAM. In U-Boot | 219 | + MemOp mop; |
314 | + * the controller is configured with the widest row addressing available. | 220 | + |
315 | + * Then a pattern is written to RAM at an offset on the row boundary size. | 221 | + if (!a->p && a->rm != 0) { |
316 | + * If the value read back equals the value read back from the | 222 | + return false; |
317 | + * start of RAM, the bootloader knows the amount of row bits. | 223 | + } |
318 | + * | 224 | + if (!fp_access_check(s)) { |
319 | + * This function inserts a mirrored memory region when the configured row | 225 | + return true; |
320 | + * bits are not matching the actual emulated memory, to simulate the | 226 | + } |
321 | + * same behavior on hardware as expected by the bootloader. | 227 | + |
322 | + */ | 228 | + if (a->rn == 31) { |
323 | + uint8_t row_bits_actual = 0; | 229 | + gen_check_sp_alignment(s); |
324 | + | 230 | + } |
325 | + /* Calculate the actual row bits using the ram_size property */ | 231 | + |
326 | + for (uint8_t i = 8; i < 12; i++) { | 232 | + total = a->selem << a->scale; |
327 | + if (1 << i == s->ram_size) { | 233 | + tcg_rn = cpu_reg_sp(s, a->rn); |
328 | + row_bits_actual = i + 3; | 234 | + |
329 | + break; | 235 | + mop = finalize_memop_asimd(s, a->scale); |
236 | + clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, | ||
237 | + total, mop); | ||
238 | + | ||
239 | + tcg_ebytes = tcg_constant_i64(1 << a->scale); | ||
240 | + for (xs = 0, rt = a->rt; xs < a->selem; xs++, rt = (rt + 1) % 32) { | ||
241 | + do_vec_ld(s, rt, a->index, clean_addr, mop); | ||
242 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
243 | + } | ||
244 | + | ||
245 | + if (a->p) { | ||
246 | + if (a->rm == 31) { | ||
247 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); | ||
248 | + } else { | ||
249 | + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); | ||
330 | + } | 250 | + } |
331 | + } | 251 | + } |
332 | + | 252 | + return true; |
333 | + if (s->ram_size == (1 << (row_bits - 3))) { | ||
334 | + /* When row bits is the expected value, remove the mirror */ | ||
335 | + memory_region_set_enabled(&s->row_mirror_alias, false); | ||
336 | + trace_allwinner_h3_dramc_rowmirror_disable(); | ||
337 | + | ||
338 | + } else if (row_bits_actual) { | ||
339 | + /* Row bits not matching ram_size, install the rows mirror */ | ||
340 | + hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual + | ||
341 | + bank_bits)) * page_size); | ||
342 | + | ||
343 | + memory_region_set_enabled(&s->row_mirror_alias, true); | ||
344 | + memory_region_set_address(&s->row_mirror_alias, row_mirror); | ||
345 | + | ||
346 | + trace_allwinner_h3_dramc_rowmirror_enable(row_mirror); | ||
347 | + } | ||
348 | +} | 253 | +} |
349 | + | 254 | + |
350 | +static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset, | 255 | +static bool trans_LD_single_repl(DisasContext *s, arg_LD_single_repl *a) |
351 | + unsigned size) | ||
352 | +{ | 256 | +{ |
353 | + const AwH3DramCtlState *s = AW_H3_DRAMC(opaque); | 257 | + int xs, total, rt; |
354 | + const uint32_t idx = REG_INDEX(offset); | 258 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
355 | + | 259 | + MemOp mop; |
356 | + if (idx >= AW_H3_DRAMCOM_REGS_NUM) { | 260 | + |
357 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | 261 | + if (!a->p && a->rm != 0) { |
358 | + __func__, (uint32_t)offset); | 262 | + return false; |
359 | + return 0; | 263 | + } |
360 | + } | 264 | + if (!fp_access_check(s)) { |
361 | + | 265 | + return true; |
362 | + trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size); | 266 | + } |
363 | + | 267 | + |
364 | + return s->dramcom[idx]; | 268 | + if (a->rn == 31) { |
365 | +} | 269 | + gen_check_sp_alignment(s); |
366 | + | 270 | + } |
367 | +static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset, | 271 | + |
368 | + uint64_t val, unsigned size) | 272 | + total = a->selem << a->scale; |
369 | +{ | 273 | + tcg_rn = cpu_reg_sp(s, a->rn); |
370 | + AwH3DramCtlState *s = AW_H3_DRAMC(opaque); | 274 | + |
371 | + const uint32_t idx = REG_INDEX(offset); | 275 | + mop = finalize_memop_asimd(s, a->scale); |
372 | + | 276 | + clean_addr = gen_mte_checkN(s, tcg_rn, false, a->p || a->rn != 31, |
373 | + trace_allwinner_h3_dramcom_write(offset, val, size); | 277 | + total, mop); |
374 | + | 278 | + |
375 | + if (idx >= AW_H3_DRAMCOM_REGS_NUM) { | 279 | + tcg_ebytes = tcg_constant_i64(1 << a->scale); |
376 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | 280 | + for (xs = 0, rt = a->rt; xs < a->selem; xs++, rt = (rt + 1) % 32) { |
377 | + __func__, (uint32_t)offset); | 281 | + /* Load and replicate to all elements */ |
378 | + return; | 282 | + TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
379 | + } | 283 | + |
380 | + | 284 | + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); |
381 | + switch (offset) { | 285 | + tcg_gen_gvec_dup_i64(a->scale, vec_full_reg_offset(s, rt), |
382 | + case REG_DRAMCOM_CR: /* Control Register */ | 286 | + (a->q + 1) * 8, vec_full_reg_size(s), tcg_tmp); |
383 | + allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1, | 287 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
384 | + ((val >> 2) & 0x1) + 2, | 288 | + } |
385 | + 1 << (((val >> 8) & 0xf) + 3)); | 289 | + |
386 | + break; | 290 | + if (a->p) { |
387 | + default: | 291 | + if (a->rm == 31) { |
388 | + break; | 292 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); |
389 | + }; | 293 | + } else { |
390 | + | 294 | + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); |
391 | + s->dramcom[idx] = (uint32_t) val; | ||
392 | +} | ||
393 | + | ||
394 | +static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset, | ||
395 | + unsigned size) | ||
396 | +{ | ||
397 | + const AwH3DramCtlState *s = AW_H3_DRAMC(opaque); | ||
398 | + const uint32_t idx = REG_INDEX(offset); | ||
399 | + | ||
400 | + if (idx >= AW_H3_DRAMCTL_REGS_NUM) { | ||
401 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
402 | + __func__, (uint32_t)offset); | ||
403 | + return 0; | ||
404 | + } | ||
405 | + | ||
406 | + trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size); | ||
407 | + | ||
408 | + return s->dramctl[idx]; | ||
409 | +} | ||
410 | + | ||
411 | +static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset, | ||
412 | + uint64_t val, unsigned size) | ||
413 | +{ | ||
414 | + AwH3DramCtlState *s = AW_H3_DRAMC(opaque); | ||
415 | + const uint32_t idx = REG_INDEX(offset); | ||
416 | + | ||
417 | + trace_allwinner_h3_dramctl_write(offset, val, size); | ||
418 | + | ||
419 | + if (idx >= AW_H3_DRAMCTL_REGS_NUM) { | ||
420 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
421 | + __func__, (uint32_t)offset); | ||
422 | + return; | ||
423 | + } | ||
424 | + | ||
425 | + switch (offset) { | ||
426 | + case REG_DRAMCTL_PIR: /* PHY Initialization Register */ | ||
427 | + s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE; | ||
428 | + s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE; | ||
429 | + break; | ||
430 | + default: | ||
431 | + break; | ||
432 | + } | ||
433 | + | ||
434 | + s->dramctl[idx] = (uint32_t) val; | ||
435 | +} | ||
436 | + | ||
437 | +static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset, | ||
438 | + unsigned size) | ||
439 | +{ | ||
440 | + const AwH3DramCtlState *s = AW_H3_DRAMC(opaque); | ||
441 | + const uint32_t idx = REG_INDEX(offset); | ||
442 | + | ||
443 | + if (idx >= AW_H3_DRAMPHY_REGS_NUM) { | ||
444 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
445 | + __func__, (uint32_t)offset); | ||
446 | + return 0; | ||
447 | + } | ||
448 | + | ||
449 | + trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size); | ||
450 | + | ||
451 | + return s->dramphy[idx]; | ||
452 | +} | ||
453 | + | ||
454 | +static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset, | ||
455 | + uint64_t val, unsigned size) | ||
456 | +{ | ||
457 | + AwH3DramCtlState *s = AW_H3_DRAMC(opaque); | ||
458 | + const uint32_t idx = REG_INDEX(offset); | ||
459 | + | ||
460 | + trace_allwinner_h3_dramphy_write(offset, val, size); | ||
461 | + | ||
462 | + if (idx >= AW_H3_DRAMPHY_REGS_NUM) { | ||
463 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
464 | + __func__, (uint32_t)offset); | ||
465 | + return; | ||
466 | + } | ||
467 | + | ||
468 | + s->dramphy[idx] = (uint32_t) val; | ||
469 | +} | ||
470 | + | ||
471 | +static const MemoryRegionOps allwinner_h3_dramcom_ops = { | ||
472 | + .read = allwinner_h3_dramcom_read, | ||
473 | + .write = allwinner_h3_dramcom_write, | ||
474 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
475 | + .valid = { | ||
476 | + .min_access_size = 4, | ||
477 | + .max_access_size = 4, | ||
478 | + }, | ||
479 | + .impl.min_access_size = 4, | ||
480 | +}; | ||
481 | + | ||
482 | +static const MemoryRegionOps allwinner_h3_dramctl_ops = { | ||
483 | + .read = allwinner_h3_dramctl_read, | ||
484 | + .write = allwinner_h3_dramctl_write, | ||
485 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
486 | + .valid = { | ||
487 | + .min_access_size = 4, | ||
488 | + .max_access_size = 4, | ||
489 | + }, | ||
490 | + .impl.min_access_size = 4, | ||
491 | +}; | ||
492 | + | ||
493 | +static const MemoryRegionOps allwinner_h3_dramphy_ops = { | ||
494 | + .read = allwinner_h3_dramphy_read, | ||
495 | + .write = allwinner_h3_dramphy_write, | ||
496 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
497 | + .valid = { | ||
498 | + .min_access_size = 4, | ||
499 | + .max_access_size = 4, | ||
500 | + }, | ||
501 | + .impl.min_access_size = 4, | ||
502 | +}; | ||
503 | + | ||
504 | +static void allwinner_h3_dramc_reset(DeviceState *dev) | ||
505 | +{ | ||
506 | + AwH3DramCtlState *s = AW_H3_DRAMC(dev); | ||
507 | + | ||
508 | + /* Set default values for registers */ | ||
509 | + memset(&s->dramcom, 0, sizeof(s->dramcom)); | ||
510 | + memset(&s->dramctl, 0, sizeof(s->dramctl)); | ||
511 | + memset(&s->dramphy, 0, sizeof(s->dramphy)); | ||
512 | +} | ||
513 | + | ||
514 | +static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp) | ||
515 | +{ | ||
516 | + AwH3DramCtlState *s = AW_H3_DRAMC(dev); | ||
517 | + | ||
518 | + /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */ | ||
519 | + for (uint8_t i = 8; i < 13; i++) { | ||
520 | + if (1 << i == s->ram_size) { | ||
521 | + break; | ||
522 | + } else if (i == 12) { | ||
523 | + error_report("%s: ram-size %u MiB is not supported", | ||
524 | + __func__, s->ram_size); | ||
525 | + exit(1); | ||
526 | + } | 295 | + } |
527 | + } | 296 | + } |
528 | + | 297 | + return true; |
529 | + /* Setup row mirror mappings */ | 298 | } |
530 | + memory_region_init_ram(&s->row_mirror, OBJECT(s), | 299 | |
531 | + "allwinner-h3-dramc.row-mirror", | 300 | /* |
532 | + 4 * KiB, &error_abort); | 301 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) |
533 | + memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr, | 302 | static void disas_ldst(DisasContext *s, uint32_t insn) |
534 | + &s->row_mirror, 10); | 303 | { |
535 | + | 304 | switch (extract32(insn, 24, 6)) { |
536 | + memory_region_init_alias(&s->row_mirror_alias, OBJECT(s), | 305 | - case 0x0d: /* AdvSIMD load/store single structure */ |
537 | + "allwinner-h3-dramc.row-mirror-alias", | 306 | - disas_ldst_single_struct(s, insn); |
538 | + &s->row_mirror, 0, 4 * KiB); | 307 | - break; |
539 | + memory_region_add_subregion_overlap(get_system_memory(), | 308 | case 0x19: |
540 | + s->ram_addr + 1 * MiB, | 309 | if (extract32(insn, 21, 1) != 0) { |
541 | + &s->row_mirror_alias, 10); | 310 | disas_ldst_tag(s, insn); |
542 | + memory_region_set_enabled(&s->row_mirror_alias, false); | ||
543 | +} | ||
544 | + | ||
545 | +static void allwinner_h3_dramc_init(Object *obj) | ||
546 | +{ | ||
547 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
548 | + AwH3DramCtlState *s = AW_H3_DRAMC(obj); | ||
549 | + | ||
550 | + /* DRAMCOM registers */ | ||
551 | + memory_region_init_io(&s->dramcom_iomem, OBJECT(s), | ||
552 | + &allwinner_h3_dramcom_ops, s, | ||
553 | + TYPE_AW_H3_DRAMC, 4 * KiB); | ||
554 | + sysbus_init_mmio(sbd, &s->dramcom_iomem); | ||
555 | + | ||
556 | + /* DRAMCTL registers */ | ||
557 | + memory_region_init_io(&s->dramctl_iomem, OBJECT(s), | ||
558 | + &allwinner_h3_dramctl_ops, s, | ||
559 | + TYPE_AW_H3_DRAMC, 4 * KiB); | ||
560 | + sysbus_init_mmio(sbd, &s->dramctl_iomem); | ||
561 | + | ||
562 | + /* DRAMPHY registers */ | ||
563 | + memory_region_init_io(&s->dramphy_iomem, OBJECT(s), | ||
564 | + &allwinner_h3_dramphy_ops, s, | ||
565 | + TYPE_AW_H3_DRAMC, 4 * KiB); | ||
566 | + sysbus_init_mmio(sbd, &s->dramphy_iomem); | ||
567 | +} | ||
568 | + | ||
569 | +static Property allwinner_h3_dramc_properties[] = { | ||
570 | + DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0), | ||
571 | + DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB), | ||
572 | + DEFINE_PROP_END_OF_LIST() | ||
573 | +}; | ||
574 | + | ||
575 | +static const VMStateDescription allwinner_h3_dramc_vmstate = { | ||
576 | + .name = "allwinner-h3-dramc", | ||
577 | + .version_id = 1, | ||
578 | + .minimum_version_id = 1, | ||
579 | + .fields = (VMStateField[]) { | ||
580 | + VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM), | ||
581 | + VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM), | ||
582 | + VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM), | ||
583 | + VMSTATE_END_OF_LIST() | ||
584 | + } | ||
585 | +}; | ||
586 | + | ||
587 | +static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data) | ||
588 | +{ | ||
589 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
590 | + | ||
591 | + dc->reset = allwinner_h3_dramc_reset; | ||
592 | + dc->vmsd = &allwinner_h3_dramc_vmstate; | ||
593 | + dc->realize = allwinner_h3_dramc_realize; | ||
594 | + device_class_set_props(dc, allwinner_h3_dramc_properties); | ||
595 | +} | ||
596 | + | ||
597 | +static const TypeInfo allwinner_h3_dramc_info = { | ||
598 | + .name = TYPE_AW_H3_DRAMC, | ||
599 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
600 | + .instance_init = allwinner_h3_dramc_init, | ||
601 | + .instance_size = sizeof(AwH3DramCtlState), | ||
602 | + .class_init = allwinner_h3_dramc_class_init, | ||
603 | +}; | ||
604 | + | ||
605 | +static void allwinner_h3_dramc_register(void) | ||
606 | +{ | ||
607 | + type_register_static(&allwinner_h3_dramc_info); | ||
608 | +} | ||
609 | + | ||
610 | +type_init(allwinner_h3_dramc_register) | ||
611 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
612 | index XXXXXXX..XXXXXXX 100644 | ||
613 | --- a/hw/misc/trace-events | ||
614 | +++ b/hw/misc/trace-events | ||
615 | @@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad | ||
616 | allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
617 | allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
618 | |||
619 | +# allwinner-h3-dramc.c | ||
620 | +allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" | ||
621 | +allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 | ||
622 | +allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
623 | +allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
624 | +allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
625 | +allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
626 | +allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
627 | +allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
628 | + | ||
629 | # allwinner-sid.c | ||
630 | allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
631 | allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
632 | -- | 311 | -- |
633 | 2.20.1 | 312 | 2.34.1 |
634 | |||
635 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | Convert the instructions in the load/store memory tags instruction |
---|---|---|---|
2 | group to decodetree. | ||
2 | 3 | ||
3 | The Allwinner H3 System on Chip has an System Control | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | module that provides system wide generic controls and | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | device information. This commit adds support for the | 6 | Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org |
6 | Allwinner H3 System Control module. | 7 | --- |
8 | target/arm/tcg/a64.decode | 25 +++ | ||
9 | target/arm/tcg/translate-a64.c | 360 ++++++++++++++++----------------- | ||
10 | 2 files changed, 199 insertions(+), 186 deletions(-) | ||
7 | 11 | ||
8 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 12 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
12 | Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/misc/Makefile.objs | 1 + | ||
16 | include/hw/arm/allwinner-h3.h | 3 + | ||
17 | include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++ | ||
18 | hw/arm/allwinner-h3.c | 9 +- | ||
19 | hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++ | ||
20 | 5 files changed, 219 insertions(+), 1 deletion(-) | ||
21 | create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h | ||
22 | create mode 100644 hw/misc/allwinner-h3-sysctrl.c | ||
23 | |||
24 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
25 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/misc/Makefile.objs | 14 | --- a/target/arm/tcg/a64.decode |
27 | +++ b/hw/misc/Makefile.objs | 15 | +++ b/target/arm/tcg/a64.decode |
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/ | 16 | @@ -XXX,XX +XXX,XX @@ LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d |
29 | common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o | 17 | |
30 | 18 | # Replicating load case | |
31 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o | 19 | LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem |
32 | +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o | 20 | + |
33 | common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o | 21 | +%tag_offset 12:s9 !function=scale_by_log2_tag_granule |
34 | common-obj-$(CONFIG_NSERIES) += cbus.o | 22 | +&ldst_tag rn rt imm p w |
35 | common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o | 23 | +@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset |
36 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 24 | +@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 |
25 | + | ||
26 | +STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 | ||
27 | +STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 | ||
28 | +STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 | ||
29 | +STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 | ||
30 | + | ||
31 | +LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 | ||
32 | +STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 | ||
33 | +STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 | ||
34 | +STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 | ||
35 | + | ||
36 | +STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 | ||
37 | +ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 | ||
38 | +ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 | ||
39 | +ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 | ||
40 | + | ||
41 | +LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 | ||
42 | +STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 | ||
43 | +STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 | ||
44 | +STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 | ||
45 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/include/hw/arm/allwinner-h3.h | 47 | --- a/target/arm/tcg/translate-a64.c |
39 | +++ b/include/hw/arm/allwinner-h3.h | 48 | +++ b/target/arm/tcg/translate-a64.c |
40 | @@ -XXX,XX +XXX,XX @@ | 49 | @@ -XXX,XX +XXX,XX @@ static int uimm_scaled(DisasContext *s, int x) |
41 | #include "hw/timer/allwinner-a10-pit.h" | 50 | return imm << scale; |
42 | #include "hw/intc/arm_gic.h" | ||
43 | #include "hw/misc/allwinner-h3-ccu.h" | ||
44 | +#include "hw/misc/allwinner-h3-sysctrl.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | |||
47 | /** | ||
48 | @@ -XXX,XX +XXX,XX @@ enum { | ||
49 | AW_H3_SRAM_A1, | ||
50 | AW_H3_SRAM_A2, | ||
51 | AW_H3_SRAM_C, | ||
52 | + AW_H3_SYSCTRL, | ||
53 | AW_H3_EHCI0, | ||
54 | AW_H3_OHCI0, | ||
55 | AW_H3_EHCI1, | ||
56 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
57 | const hwaddr *memmap; | ||
58 | AwA10PITState timer; | ||
59 | AwH3ClockCtlState ccu; | ||
60 | + AwH3SysCtrlState sysctrl; | ||
61 | GICState gic; | ||
62 | MemoryRegion sram_a1; | ||
63 | MemoryRegion sram_a2; | ||
64 | diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h | ||
65 | new file mode 100644 | ||
66 | index XXXXXXX..XXXXXXX | ||
67 | --- /dev/null | ||
68 | +++ b/include/hw/misc/allwinner-h3-sysctrl.h | ||
69 | @@ -XXX,XX +XXX,XX @@ | ||
70 | +/* | ||
71 | + * Allwinner H3 System Control emulation | ||
72 | + * | ||
73 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
74 | + * | ||
75 | + * This program is free software: you can redistribute it and/or modify | ||
76 | + * it under the terms of the GNU General Public License as published by | ||
77 | + * the Free Software Foundation, either version 2 of the License, or | ||
78 | + * (at your option) any later version. | ||
79 | + * | ||
80 | + * This program is distributed in the hope that it will be useful, | ||
81 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
82 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
83 | + * GNU General Public License for more details. | ||
84 | + * | ||
85 | + * You should have received a copy of the GNU General Public License | ||
86 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
87 | + */ | ||
88 | + | ||
89 | +#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H | ||
90 | +#define HW_MISC_ALLWINNER_H3_SYSCTRL_H | ||
91 | + | ||
92 | +#include "qom/object.h" | ||
93 | +#include "hw/sysbus.h" | ||
94 | + | ||
95 | +/** | ||
96 | + * @name Constants | ||
97 | + * @{ | ||
98 | + */ | ||
99 | + | ||
100 | +/** Highest register address used by System Control device */ | ||
101 | +#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30) | ||
102 | + | ||
103 | +/** Total number of known registers */ | ||
104 | +#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \ | ||
105 | + sizeof(uint32_t)) + 1) | ||
106 | + | ||
107 | +/** @} */ | ||
108 | + | ||
109 | +/** | ||
110 | + * @name Object model | ||
111 | + * @{ | ||
112 | + */ | ||
113 | + | ||
114 | +#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl" | ||
115 | +#define AW_H3_SYSCTRL(obj) \ | ||
116 | + OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL) | ||
117 | + | ||
118 | +/** @} */ | ||
119 | + | ||
120 | +/** | ||
121 | + * Allwinner H3 System Control object instance state | ||
122 | + */ | ||
123 | +typedef struct AwH3SysCtrlState { | ||
124 | + /*< private >*/ | ||
125 | + SysBusDevice parent_obj; | ||
126 | + /*< public >*/ | ||
127 | + | ||
128 | + /** Maps I/O registers in physical memory */ | ||
129 | + MemoryRegion iomem; | ||
130 | + | ||
131 | + /** Array of hardware registers */ | ||
132 | + uint32_t regs[AW_H3_SYSCTRL_REGS_NUM]; | ||
133 | + | ||
134 | +} AwH3SysCtrlState; | ||
135 | + | ||
136 | +#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */ | ||
137 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
138 | index XXXXXXX..XXXXXXX 100644 | ||
139 | --- a/hw/arm/allwinner-h3.c | ||
140 | +++ b/hw/arm/allwinner-h3.c | ||
141 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
142 | [AW_H3_SRAM_A1] = 0x00000000, | ||
143 | [AW_H3_SRAM_A2] = 0x00044000, | ||
144 | [AW_H3_SRAM_C] = 0x00010000, | ||
145 | + [AW_H3_SYSCTRL] = 0x01c00000, | ||
146 | [AW_H3_EHCI0] = 0x01c1a000, | ||
147 | [AW_H3_OHCI0] = 0x01c1a400, | ||
148 | [AW_H3_EHCI1] = 0x01c1b000, | ||
149 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
150 | } unimplemented[] = { | ||
151 | { "d-engine", 0x01000000, 4 * MiB }, | ||
152 | { "d-inter", 0x01400000, 128 * KiB }, | ||
153 | - { "syscon", 0x01c00000, 4 * KiB }, | ||
154 | { "dma", 0x01c02000, 4 * KiB }, | ||
155 | { "nfdc", 0x01c03000, 4 * KiB }, | ||
156 | { "ts", 0x01c06000, 4 * KiB }, | ||
157 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
158 | |||
159 | sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), | ||
160 | TYPE_AW_H3_CCU); | ||
161 | + | ||
162 | + sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl), | ||
163 | + TYPE_AW_H3_SYSCTRL); | ||
164 | } | 51 | } |
165 | 52 | ||
166 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 53 | +/* For load/store memory tags: scale offset by LOG2_TAG_GRANULE */ |
167 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 54 | +static int scale_by_log2_tag_granule(DisasContext *s, int x) |
168 | qdev_init_nofail(DEVICE(&s->ccu)); | ||
169 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); | ||
170 | |||
171 | + /* System Control */ | ||
172 | + qdev_init_nofail(DEVICE(&s->sysctrl)); | ||
173 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]); | ||
174 | + | ||
175 | /* Universal Serial Bus */ | ||
176 | sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], | ||
177 | qdev_get_gpio_in(DEVICE(&s->gic), | ||
178 | diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c | ||
179 | new file mode 100644 | ||
180 | index XXXXXXX..XXXXXXX | ||
181 | --- /dev/null | ||
182 | +++ b/hw/misc/allwinner-h3-sysctrl.c | ||
183 | @@ -XXX,XX +XXX,XX @@ | ||
184 | +/* | ||
185 | + * Allwinner H3 System Control emulation | ||
186 | + * | ||
187 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
188 | + * | ||
189 | + * This program is free software: you can redistribute it and/or modify | ||
190 | + * it under the terms of the GNU General Public License as published by | ||
191 | + * the Free Software Foundation, either version 2 of the License, or | ||
192 | + * (at your option) any later version. | ||
193 | + * | ||
194 | + * This program is distributed in the hope that it will be useful, | ||
195 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
196 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
197 | + * GNU General Public License for more details. | ||
198 | + * | ||
199 | + * You should have received a copy of the GNU General Public License | ||
200 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
201 | + */ | ||
202 | + | ||
203 | +#include "qemu/osdep.h" | ||
204 | +#include "qemu/units.h" | ||
205 | +#include "hw/sysbus.h" | ||
206 | +#include "migration/vmstate.h" | ||
207 | +#include "qemu/log.h" | ||
208 | +#include "qemu/module.h" | ||
209 | +#include "hw/misc/allwinner-h3-sysctrl.h" | ||
210 | + | ||
211 | +/* System Control register offsets */ | ||
212 | +enum { | ||
213 | + REG_VER = 0x24, /* Version */ | ||
214 | + REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */ | ||
215 | +}; | ||
216 | + | ||
217 | +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) | ||
218 | + | ||
219 | +/* System Control register reset values */ | ||
220 | +enum { | ||
221 | + REG_VER_RST = 0x0, | ||
222 | + REG_EMAC_PHY_CLK_RST = 0x58000, | ||
223 | +}; | ||
224 | + | ||
225 | +static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset, | ||
226 | + unsigned size) | ||
227 | +{ | 55 | +{ |
228 | + const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque); | 56 | + return x << LOG2_TAG_GRANULE; |
229 | + const uint32_t idx = REG_INDEX(offset); | ||
230 | + | ||
231 | + if (idx >= AW_H3_SYSCTRL_REGS_NUM) { | ||
232 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
233 | + __func__, (uint32_t)offset); | ||
234 | + return 0; | ||
235 | + } | ||
236 | + | ||
237 | + return s->regs[idx]; | ||
238 | +} | 57 | +} |
239 | + | 58 | + |
240 | +static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset, | 59 | /* |
241 | + uint64_t val, unsigned size) | 60 | * Include the generated decoders. |
61 | */ | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD_single_repl(DisasContext *s, arg_LD_single_repl *a) | ||
63 | return true; | ||
64 | } | ||
65 | |||
66 | -/* | ||
67 | - * Load/Store memory tags | ||
68 | - * | ||
69 | - * 31 30 29 24 22 21 12 10 5 0 | ||
70 | - * +-----+-------------+-----+---+------+-----+------+------+ | ||
71 | - * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | | ||
72 | - * +-----+-------------+-----+---+------+-----+------+------+ | ||
73 | - */ | ||
74 | -static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
75 | +static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a) | ||
76 | { | ||
77 | - int rt = extract32(insn, 0, 5); | ||
78 | - int rn = extract32(insn, 5, 5); | ||
79 | - uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; | ||
80 | - int op2 = extract32(insn, 10, 2); | ||
81 | - int op1 = extract32(insn, 22, 2); | ||
82 | - bool is_load = false, is_pair = false, is_zero = false, is_mult = false; | ||
83 | - int index = 0; | ||
84 | TCGv_i64 addr, clean_addr, tcg_rt; | ||
85 | + int size = 4 << s->dcz_blocksize; | ||
86 | |||
87 | - /* We checked insn bits [29:24,21] in the caller. */ | ||
88 | - if (extract32(insn, 30, 2) != 3) { | ||
89 | - goto do_unallocated; | ||
90 | + if (!dc_isar_feature(aa64_mte, s)) { | ||
91 | + return false; | ||
92 | + } | ||
93 | + if (s->current_el == 0) { | ||
94 | + return false; | ||
95 | } | ||
96 | |||
97 | - /* | ||
98 | - * @index is a tri-state variable which has 3 states: | ||
99 | - * < 0 : post-index, writeback | ||
100 | - * = 0 : signed offset | ||
101 | - * > 0 : pre-index, writeback | ||
102 | - */ | ||
103 | - switch (op1) { | ||
104 | - case 0: | ||
105 | - if (op2 != 0) { | ||
106 | - /* STG */ | ||
107 | - index = op2 - 2; | ||
108 | - } else { | ||
109 | - /* STZGM */ | ||
110 | - if (s->current_el == 0 || offset != 0) { | ||
111 | - goto do_unallocated; | ||
112 | - } | ||
113 | - is_mult = is_zero = true; | ||
114 | - } | ||
115 | - break; | ||
116 | - case 1: | ||
117 | - if (op2 != 0) { | ||
118 | - /* STZG */ | ||
119 | - is_zero = true; | ||
120 | - index = op2 - 2; | ||
121 | - } else { | ||
122 | - /* LDG */ | ||
123 | - is_load = true; | ||
124 | - } | ||
125 | - break; | ||
126 | - case 2: | ||
127 | - if (op2 != 0) { | ||
128 | - /* ST2G */ | ||
129 | - is_pair = true; | ||
130 | - index = op2 - 2; | ||
131 | - } else { | ||
132 | - /* STGM */ | ||
133 | - if (s->current_el == 0 || offset != 0) { | ||
134 | - goto do_unallocated; | ||
135 | - } | ||
136 | - is_mult = true; | ||
137 | - } | ||
138 | - break; | ||
139 | - case 3: | ||
140 | - if (op2 != 0) { | ||
141 | - /* STZ2G */ | ||
142 | - is_pair = is_zero = true; | ||
143 | - index = op2 - 2; | ||
144 | - } else { | ||
145 | - /* LDGM */ | ||
146 | - if (s->current_el == 0 || offset != 0) { | ||
147 | - goto do_unallocated; | ||
148 | - } | ||
149 | - is_mult = is_load = true; | ||
150 | - } | ||
151 | - break; | ||
152 | - | ||
153 | - default: | ||
154 | - do_unallocated: | ||
155 | - unallocated_encoding(s); | ||
156 | - return; | ||
157 | - } | ||
158 | - | ||
159 | - if (is_mult | ||
160 | - ? !dc_isar_feature(aa64_mte, s) | ||
161 | - : !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
162 | - goto do_unallocated; | ||
163 | - } | ||
164 | - | ||
165 | - if (rn == 31) { | ||
166 | + if (a->rn == 31) { | ||
167 | gen_check_sp_alignment(s); | ||
168 | } | ||
169 | |||
170 | - addr = read_cpu_reg_sp(s, rn, true); | ||
171 | - if (index >= 0) { | ||
172 | + addr = read_cpu_reg_sp(s, a->rn, true); | ||
173 | + tcg_gen_addi_i64(addr, addr, a->imm); | ||
174 | + tcg_rt = cpu_reg(s, a->rt); | ||
175 | + | ||
176 | + if (s->ata) { | ||
177 | + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); | ||
178 | + } | ||
179 | + /* | ||
180 | + * The non-tags portion of STZGM is mostly like DC_ZVA, | ||
181 | + * except the alignment happens before the access. | ||
182 | + */ | ||
183 | + clean_addr = clean_data_tbi(s, addr); | ||
184 | + tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
185 | + gen_helper_dc_zva(cpu_env, clean_addr); | ||
186 | + return true; | ||
187 | +} | ||
188 | + | ||
189 | +static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) | ||
242 | +{ | 190 | +{ |
243 | + AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque); | 191 | + TCGv_i64 addr, clean_addr, tcg_rt; |
244 | + const uint32_t idx = REG_INDEX(offset); | 192 | + |
245 | + | 193 | + if (!dc_isar_feature(aa64_mte, s)) { |
246 | + if (idx >= AW_H3_SYSCTRL_REGS_NUM) { | 194 | + return false; |
247 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | 195 | + } |
248 | + __func__, (uint32_t)offset); | 196 | + if (s->current_el == 0) { |
249 | + return; | 197 | + return false; |
250 | + } | 198 | + } |
251 | + | 199 | + |
252 | + switch (offset) { | 200 | + if (a->rn == 31) { |
253 | + case REG_VER: /* Version */ | 201 | + gen_check_sp_alignment(s); |
254 | + break; | 202 | + } |
255 | + default: | 203 | + |
256 | + s->regs[idx] = (uint32_t) val; | 204 | + addr = read_cpu_reg_sp(s, a->rn, true); |
257 | + break; | 205 | + tcg_gen_addi_i64(addr, addr, a->imm); |
258 | + } | 206 | + tcg_rt = cpu_reg(s, a->rt); |
207 | + | ||
208 | + if (s->ata) { | ||
209 | + gen_helper_stgm(cpu_env, addr, tcg_rt); | ||
210 | + } else { | ||
211 | + MMUAccessType acc = MMU_DATA_STORE; | ||
212 | + int size = 4 << GMID_EL1_BS; | ||
213 | + | ||
214 | + clean_addr = clean_data_tbi(s, addr); | ||
215 | + tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
216 | + gen_probe_access(s, clean_addr, acc, size); | ||
217 | + } | ||
218 | + return true; | ||
259 | +} | 219 | +} |
260 | + | 220 | + |
261 | +static const MemoryRegionOps allwinner_h3_sysctrl_ops = { | 221 | +static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) |
262 | + .read = allwinner_h3_sysctrl_read, | ||
263 | + .write = allwinner_h3_sysctrl_write, | ||
264 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
265 | + .valid = { | ||
266 | + .min_access_size = 4, | ||
267 | + .max_access_size = 4, | ||
268 | + }, | ||
269 | + .impl.min_access_size = 4, | ||
270 | +}; | ||
271 | + | ||
272 | +static void allwinner_h3_sysctrl_reset(DeviceState *dev) | ||
273 | +{ | 222 | +{ |
274 | + AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev); | 223 | + TCGv_i64 addr, clean_addr, tcg_rt; |
275 | + | 224 | + |
276 | + /* Set default values for registers */ | 225 | + if (!dc_isar_feature(aa64_mte, s)) { |
277 | + s->regs[REG_INDEX(REG_VER)] = REG_VER_RST; | 226 | + return false; |
278 | + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST; | 227 | + } |
228 | + if (s->current_el == 0) { | ||
229 | + return false; | ||
230 | + } | ||
231 | + | ||
232 | + if (a->rn == 31) { | ||
233 | + gen_check_sp_alignment(s); | ||
234 | + } | ||
235 | + | ||
236 | + addr = read_cpu_reg_sp(s, a->rn, true); | ||
237 | + tcg_gen_addi_i64(addr, addr, a->imm); | ||
238 | + tcg_rt = cpu_reg(s, a->rt); | ||
239 | + | ||
240 | + if (s->ata) { | ||
241 | + gen_helper_ldgm(tcg_rt, cpu_env, addr); | ||
242 | + } else { | ||
243 | + MMUAccessType acc = MMU_DATA_LOAD; | ||
244 | + int size = 4 << GMID_EL1_BS; | ||
245 | + | ||
246 | + clean_addr = clean_data_tbi(s, addr); | ||
247 | + tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
248 | + gen_probe_access(s, clean_addr, acc, size); | ||
249 | + /* The result tags are zeros. */ | ||
250 | + tcg_gen_movi_i64(tcg_rt, 0); | ||
251 | + } | ||
252 | + return true; | ||
279 | +} | 253 | +} |
280 | + | 254 | + |
281 | +static void allwinner_h3_sysctrl_init(Object *obj) | 255 | +static bool trans_LDG(DisasContext *s, arg_ldst_tag *a) |
282 | +{ | 256 | +{ |
283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 257 | + TCGv_i64 addr, clean_addr, tcg_rt; |
284 | + AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj); | 258 | + |
285 | + | 259 | + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { |
286 | + /* Memory mapping */ | 260 | + return false; |
287 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s, | 261 | + } |
288 | + TYPE_AW_H3_SYSCTRL, 4 * KiB); | 262 | + |
289 | + sysbus_init_mmio(sbd, &s->iomem); | 263 | + if (a->rn == 31) { |
264 | + gen_check_sp_alignment(s); | ||
265 | + } | ||
266 | + | ||
267 | + addr = read_cpu_reg_sp(s, a->rn, true); | ||
268 | + if (!a->p) { | ||
269 | /* pre-index or signed offset */ | ||
270 | - tcg_gen_addi_i64(addr, addr, offset); | ||
271 | + tcg_gen_addi_i64(addr, addr, a->imm); | ||
272 | } | ||
273 | |||
274 | - if (is_mult) { | ||
275 | - tcg_rt = cpu_reg(s, rt); | ||
276 | + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); | ||
277 | + tcg_rt = cpu_reg(s, a->rt); | ||
278 | + if (s->ata) { | ||
279 | + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); | ||
280 | + } else { | ||
281 | + /* | ||
282 | + * Tag access disabled: we must check for aborts on the load | ||
283 | + * load from [rn+offset], and then insert a 0 tag into rt. | ||
284 | + */ | ||
285 | + clean_addr = clean_data_tbi(s, addr); | ||
286 | + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); | ||
287 | + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); | ||
288 | + } | ||
289 | |||
290 | - if (is_zero) { | ||
291 | - int size = 4 << s->dcz_blocksize; | ||
292 | - | ||
293 | - if (s->ata) { | ||
294 | - gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); | ||
295 | - } | ||
296 | - /* | ||
297 | - * The non-tags portion of STZGM is mostly like DC_ZVA, | ||
298 | - * except the alignment happens before the access. | ||
299 | - */ | ||
300 | - clean_addr = clean_data_tbi(s, addr); | ||
301 | - tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
302 | - gen_helper_dc_zva(cpu_env, clean_addr); | ||
303 | - } else if (s->ata) { | ||
304 | - if (is_load) { | ||
305 | - gen_helper_ldgm(tcg_rt, cpu_env, addr); | ||
306 | - } else { | ||
307 | - gen_helper_stgm(cpu_env, addr, tcg_rt); | ||
308 | - } | ||
309 | - } else { | ||
310 | - MMUAccessType acc = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; | ||
311 | - int size = 4 << GMID_EL1_BS; | ||
312 | - | ||
313 | - clean_addr = clean_data_tbi(s, addr); | ||
314 | - tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
315 | - gen_probe_access(s, clean_addr, acc, size); | ||
316 | - | ||
317 | - if (is_load) { | ||
318 | - /* The result tags are zeros. */ | ||
319 | - tcg_gen_movi_i64(tcg_rt, 0); | ||
320 | - } | ||
321 | + if (a->w) { | ||
322 | + /* pre-index or post-index */ | ||
323 | + if (a->p) { | ||
324 | + /* post-index */ | ||
325 | + tcg_gen_addi_i64(addr, addr, a->imm); | ||
326 | } | ||
327 | - return; | ||
328 | + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); | ||
329 | + } | ||
330 | + return true; | ||
290 | +} | 331 | +} |
291 | + | 332 | + |
292 | +static const VMStateDescription allwinner_h3_sysctrl_vmstate = { | 333 | +static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is_pair) |
293 | + .name = "allwinner-h3-sysctrl", | ||
294 | + .version_id = 1, | ||
295 | + .minimum_version_id = 1, | ||
296 | + .fields = (VMStateField[]) { | ||
297 | + VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM), | ||
298 | + VMSTATE_END_OF_LIST() | ||
299 | + } | ||
300 | +}; | ||
301 | + | ||
302 | +static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data) | ||
303 | +{ | 334 | +{ |
304 | + DeviceClass *dc = DEVICE_CLASS(klass); | 335 | + TCGv_i64 addr, tcg_rt; |
305 | + | 336 | + |
306 | + dc->reset = allwinner_h3_sysctrl_reset; | 337 | + if (a->rn == 31) { |
307 | + dc->vmsd = &allwinner_h3_sysctrl_vmstate; | 338 | + gen_check_sp_alignment(s); |
308 | +} | 339 | } |
309 | + | 340 | |
310 | +static const TypeInfo allwinner_h3_sysctrl_info = { | 341 | - if (is_load) { |
311 | + .name = TYPE_AW_H3_SYSCTRL, | 342 | - tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); |
312 | + .parent = TYPE_SYS_BUS_DEVICE, | 343 | - tcg_rt = cpu_reg(s, rt); |
313 | + .instance_init = allwinner_h3_sysctrl_init, | 344 | - if (s->ata) { |
314 | + .instance_size = sizeof(AwH3SysCtrlState), | 345 | - gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); |
315 | + .class_init = allwinner_h3_sysctrl_class_init, | 346 | + addr = read_cpu_reg_sp(s, a->rn, true); |
316 | +}; | 347 | + if (!a->p) { |
317 | + | 348 | + /* pre-index or signed offset */ |
318 | +static void allwinner_h3_sysctrl_register(void) | 349 | + tcg_gen_addi_i64(addr, addr, a->imm); |
319 | +{ | 350 | + } |
320 | + type_register_static(&allwinner_h3_sysctrl_info); | 351 | + tcg_rt = cpu_reg_sp(s, a->rt); |
321 | +} | 352 | + if (!s->ata) { |
322 | + | 353 | + /* |
323 | +type_init(allwinner_h3_sysctrl_register) | 354 | + * For STG and ST2G, we need to check alignment and probe memory. |
355 | + * TODO: For STZG and STZ2G, we could rely on the stores below, | ||
356 | + * at least for system mode; user-only won't enforce alignment. | ||
357 | + */ | ||
358 | + if (is_pair) { | ||
359 | + gen_helper_st2g_stub(cpu_env, addr); | ||
360 | } else { | ||
361 | - /* | ||
362 | - * Tag access disabled: we must check for aborts on the load | ||
363 | - * load from [rn+offset], and then insert a 0 tag into rt. | ||
364 | - */ | ||
365 | - clean_addr = clean_data_tbi(s, addr); | ||
366 | - gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); | ||
367 | - gen_address_with_allocation_tag0(tcg_rt, tcg_rt); | ||
368 | + gen_helper_stg_stub(cpu_env, addr); | ||
369 | + } | ||
370 | + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | ||
371 | + if (is_pair) { | ||
372 | + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); | ||
373 | + } else { | ||
374 | + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); | ||
375 | } | ||
376 | } else { | ||
377 | - tcg_rt = cpu_reg_sp(s, rt); | ||
378 | - if (!s->ata) { | ||
379 | - /* | ||
380 | - * For STG and ST2G, we need to check alignment and probe memory. | ||
381 | - * TODO: For STZG and STZ2G, we could rely on the stores below, | ||
382 | - * at least for system mode; user-only won't enforce alignment. | ||
383 | - */ | ||
384 | - if (is_pair) { | ||
385 | - gen_helper_st2g_stub(cpu_env, addr); | ||
386 | - } else { | ||
387 | - gen_helper_stg_stub(cpu_env, addr); | ||
388 | - } | ||
389 | - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | ||
390 | - if (is_pair) { | ||
391 | - gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); | ||
392 | - } else { | ||
393 | - gen_helper_stg_parallel(cpu_env, addr, tcg_rt); | ||
394 | - } | ||
395 | + if (is_pair) { | ||
396 | + gen_helper_st2g(cpu_env, addr, tcg_rt); | ||
397 | } else { | ||
398 | - if (is_pair) { | ||
399 | - gen_helper_st2g(cpu_env, addr, tcg_rt); | ||
400 | - } else { | ||
401 | - gen_helper_stg(cpu_env, addr, tcg_rt); | ||
402 | - } | ||
403 | + gen_helper_stg(cpu_env, addr, tcg_rt); | ||
404 | } | ||
405 | } | ||
406 | |||
407 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
408 | } | ||
409 | } | ||
410 | |||
411 | - if (index != 0) { | ||
412 | + if (a->w) { | ||
413 | /* pre-index or post-index */ | ||
414 | - if (index < 0) { | ||
415 | + if (a->p) { | ||
416 | /* post-index */ | ||
417 | - tcg_gen_addi_i64(addr, addr, offset); | ||
418 | + tcg_gen_addi_i64(addr, addr, a->imm); | ||
419 | } | ||
420 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); | ||
421 | + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); | ||
422 | } | ||
423 | + return true; | ||
424 | } | ||
425 | |||
426 | -/* Loads and stores */ | ||
427 | -static void disas_ldst(DisasContext *s, uint32_t insn) | ||
428 | -{ | ||
429 | - switch (extract32(insn, 24, 6)) { | ||
430 | - case 0x19: | ||
431 | - if (extract32(insn, 21, 1) != 0) { | ||
432 | - disas_ldst_tag(s, insn); | ||
433 | - } else { | ||
434 | - unallocated_encoding(s); | ||
435 | - } | ||
436 | - break; | ||
437 | - default: | ||
438 | - unallocated_encoding(s); | ||
439 | - break; | ||
440 | - } | ||
441 | -} | ||
442 | +TRANS_FEAT(STG, aa64_mte_insn_reg, do_STG, a, false, false) | ||
443 | +TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false) | ||
444 | +TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true) | ||
445 | +TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true) | ||
446 | |||
447 | typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); | ||
448 | |||
449 | @@ -XXX,XX +XXX,XX @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | ||
450 | static void disas_a64_legacy(DisasContext *s, uint32_t insn) | ||
451 | { | ||
452 | switch (extract32(insn, 25, 4)) { | ||
453 | - case 0x4: | ||
454 | - case 0x6: | ||
455 | - case 0xc: | ||
456 | - case 0xe: /* Loads and stores */ | ||
457 | - disas_ldst(s, insn); | ||
458 | - break; | ||
459 | case 0x5: | ||
460 | case 0xd: /* Data processing - register */ | ||
461 | disas_data_proc_reg(s, insn); | ||
324 | -- | 462 | -- |
325 | 2.20.1 | 463 | 2.34.1 |
326 | |||
327 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner |
---|---|---|---|
2 | A10 PIC model; however in the process we introduced a regression. | ||
3 | This is because the old code was robust against the incoming 'level' | ||
4 | argument being something other than 0 or 1, whereas the new code was | ||
5 | not. | ||
2 | 6 | ||
3 | Mention 'max' value in the gic-version property description. | 7 | In particular, the allwinner-sdhost code treats its IRQ line |
8 | as 0-vs-non-0 rather than 0-vs-1, so when the SD controller | ||
9 | set its IRQ line for any reason other than transmit the | ||
10 | interrupt controller would ignore it. The observed effect | ||
11 | was a guest timeout when rebooting the guest kernel. | ||
4 | 12 | ||
5 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 13 | Handle level values other than 0 or 1, to restore the old |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | behaviour. |
7 | Reviewed-by: Andrew Jones <drjones@redhat.com> | 15 | |
8 | Message-id: 20200311131618.7187-2-eric.auger@redhat.com | 16 | Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()") |
17 | Cc: qemu-stable@nongnu.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
20 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
21 | Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org | ||
10 | --- | 22 | --- |
11 | hw/arm/virt.c | 3 ++- | 23 | hw/intc/allwinner-a10-pic.c | 2 +- |
12 | 1 file changed, 2 insertions(+), 1 deletion(-) | 24 | 1 file changed, 1 insertion(+), 1 deletion(-) |
13 | 25 | ||
14 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 26 | diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c |
15 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/virt.c | 28 | --- a/hw/intc/allwinner-a10-pic.c |
17 | +++ b/hw/arm/virt.c | 29 | +++ b/hw/intc/allwinner-a10-pic.c |
18 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | 30 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level) |
19 | virt_set_gic_version, NULL); | 31 | AwA10PICState *s = opaque; |
20 | object_property_set_description(obj, "gic-version", | 32 | uint32_t *pending_reg = &s->irq_pending[irq / 32]; |
21 | "Set GIC version. " | 33 | |
22 | - "Valid values are 2, 3 and host", NULL); | 34 | - *pending_reg = deposit32(*pending_reg, irq % 32, 1, level); |
23 | + "Valid values are 2, 3, host and max", | 35 | + *pending_reg = deposit32(*pending_reg, irq % 32, 1, !!level); |
24 | + NULL); | 36 | aw_a10_pic_update(s); |
25 | 37 | } | |
26 | vms->highmem_ecam = !vmc->no_highmem_ecam; | ||
27 | 38 | ||
28 | -- | 39 | -- |
29 | 2.20.1 | 40 | 2.34.1 |
30 | 41 | ||
31 | 42 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | QEMU allows qemu_irq lines to transfer arbitrary integers. However |
---|---|---|---|
2 | the convention is that for a simple IRQ line the values transferred | ||
3 | are always 0 and 1. The A10 SD controller device instead assumes a | ||
4 | 0-vs-non-0 convention, which happens to work with the interrupt | ||
5 | controller it is wired up to. | ||
2 | 6 | ||
3 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | Coerce the value to boolean to follow our usual convention. |
4 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | 8 | |
5 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | Message-id: 20200206112645.21275-2-clg@kaod.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
12 | Message-id: 20230606104609.3692557-3-peter.maydell@linaro.org | ||
9 | --- | 13 | --- |
10 | Makefile.objs | 1 + | 14 | hw/sd/allwinner-sdhost.c | 2 +- |
11 | hw/ssi/aspeed_smc.c | 17 +++++++++++++++++ | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | hw/ssi/trace-events | 9 +++++++++ | ||
13 | 3 files changed, 27 insertions(+) | ||
14 | create mode 100644 hw/ssi/trace-events | ||
15 | 16 | ||
16 | diff --git a/Makefile.objs b/Makefile.objs | 17 | diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/Makefile.objs | 19 | --- a/hw/sd/allwinner-sdhost.c |
19 | +++ b/Makefile.objs | 20 | +++ b/hw/sd/allwinner-sdhost.c |
20 | @@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi | 21 | @@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_update_irq(AwSdHostState *s) |
21 | trace-events-subdirs += hw/sd | ||
22 | trace-events-subdirs += hw/sparc | ||
23 | trace-events-subdirs += hw/sparc64 | ||
24 | +trace-events-subdirs += hw/ssi | ||
25 | trace-events-subdirs += hw/timer | ||
26 | trace-events-subdirs += hw/tpm | ||
27 | trace-events-subdirs += hw/usb | ||
28 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/ssi/aspeed_smc.c | ||
31 | +++ b/hw/ssi/aspeed_smc.c | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | #include "qapi/error.h" | ||
34 | #include "exec/address-spaces.h" | ||
35 | #include "qemu/units.h" | ||
36 | +#include "trace.h" | ||
37 | |||
38 | #include "hw/irq.h" | ||
39 | #include "hw/qdev-properties.h" | ||
40 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | ||
41 | |||
42 | s->ctrl->reg_to_segment(s, new, &seg); | ||
43 | |||
44 | + trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); | ||
45 | + | ||
46 | /* The start address of CS0 is read-only */ | ||
47 | if (cs == 0 && seg.addr != s->ctrl->flash_window_base) { | ||
48 | qemu_log_mask(LOG_GUEST_ERROR, | ||
49 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) | ||
50 | __func__, aspeed_smc_flash_mode(fl)); | ||
51 | } | 22 | } |
52 | 23 | ||
53 | + trace_aspeed_smc_flash_read(fl->id, addr, size, ret, | 24 | trace_allwinner_sdhost_update_irq(irq); |
54 | + aspeed_smc_flash_mode(fl)); | 25 | - qemu_set_irq(s->irq, irq); |
55 | return ret; | 26 | + qemu_set_irq(s->irq, !!irq); |
56 | } | 27 | } |
57 | 28 | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, | 29 | static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s, |
59 | AspeedSMCState *s = fl->controller; | ||
60 | uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3; | ||
61 | |||
62 | + trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies, | ||
63 | + (uint8_t) data & 0xff); | ||
64 | + | ||
65 | if (s->snoop_index == SNOOP_OFF) { | ||
66 | return false; /* Do nothing */ | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, | ||
69 | AspeedSMCState *s = fl->controller; | ||
70 | int i; | ||
71 | |||
72 | + trace_aspeed_smc_flash_write(fl->id, addr, size, data, | ||
73 | + aspeed_smc_flash_mode(fl)); | ||
74 | + | ||
75 | if (!aspeed_smc_is_writable(fl)) { | ||
76 | qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%" | ||
77 | HWADDR_PRIx "\n", __func__, addr); | ||
78 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) | ||
79 | (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || | ||
80 | (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || | ||
81 | (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { | ||
82 | + | ||
83 | + trace_aspeed_smc_read(addr, size, s->regs[addr]); | ||
84 | + | ||
85 | return s->regs[addr]; | ||
86 | } else { | ||
87 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", | ||
88 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) | ||
89 | __func__, s->regs[R_DMA_FLASH_ADDR]); | ||
90 | return; | ||
91 | } | ||
92 | + trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); | ||
93 | |||
94 | /* | ||
95 | * When the DMA is on-going, the DMA registers are updated | ||
96 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, | ||
97 | |||
98 | addr >>= 2; | ||
99 | |||
100 | + trace_aspeed_smc_write(addr, size, data); | ||
101 | + | ||
102 | if (addr == s->r_conf || | ||
103 | (addr >= s->r_timings && | ||
104 | addr < s->r_timings + s->ctrl->nregs_timings) || | ||
105 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
106 | new file mode 100644 | ||
107 | index XXXXXXX..XXXXXXX | ||
108 | --- /dev/null | ||
109 | +++ b/hw/ssi/trace-events | ||
110 | @@ -XXX,XX +XXX,XX @@ | ||
111 | +# aspeed_smc.c | ||
112 | + | ||
113 | +aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]" | ||
114 | +aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d" | ||
115 | +aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x" | ||
116 | +aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d" | ||
117 | +aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 | ||
118 | +aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" | ||
119 | +aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 | ||
120 | -- | 30 | -- |
121 | 2.20.1 | 31 | 2.34.1 |
122 | 32 | ||
123 | 33 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | The nrf51_timer has a free-running counter which we implement using |
---|---|---|---|
2 | the pattern of using two fields (update_counter_ns, counter) to track | ||
3 | the last point at which we calculated the counter value, and the | ||
4 | counter value at that time. Then we can find the current counter | ||
5 | value by converting the difference in wall-clock time between then | ||
6 | and now to a tick count that we need to add to the counter value. | ||
2 | 7 | ||
3 | The Security Identifier device found in various Allwinner System on Chip | 8 | Unfortunately the nrf51_timer's implementation of this has a bug |
4 | designs gives applications a per-board unique identifier. This commit | 9 | which means it loses time every time update_counter() is called. |
5 | adds support for the Allwinner Security Identifier using a 128-bit | 10 | After updating s->counter it always sets s->update_counter_ns to |
6 | UUID value as input. | 11 | 'now', even though the actual point when s->counter hit the new value |
12 | will be some point in the past (half a tick, say). In the worst case | ||
13 | (guest code in a tight loop reading the counter, icount mode) the | ||
14 | counter is continually queried less than a tick after it was last | ||
15 | read, so s->counter never advances but s->update_counter_ns does, and | ||
16 | the guest never makes forward progress. | ||
7 | 17 | ||
8 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 18 | The fix for this is to only advance update_counter_ns to the |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 19 | timestamp of the last tick, not all the way to 'now'. (This is the |
10 | Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com | 20 | pattern used in hw/misc/mps2-fpgaio.c's counter.) |
21 | |||
22 | Cc: qemu-stable@nongnu.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
25 | Message-id: 20230606134917.3782215-1-peter.maydell@linaro.org | ||
12 | --- | 26 | --- |
13 | hw/misc/Makefile.objs | 1 + | 27 | hw/timer/nrf51_timer.c | 7 ++++++- |
14 | include/hw/arm/allwinner-h3.h | 3 + | 28 | 1 file changed, 6 insertions(+), 1 deletion(-) |
15 | include/hw/misc/allwinner-sid.h | 60 ++++++++++++ | ||
16 | hw/arm/allwinner-h3.c | 11 ++- | ||
17 | hw/arm/orangepi.c | 8 ++ | ||
18 | hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++ | ||
19 | hw/misc/trace-events | 4 + | ||
20 | 7 files changed, 254 insertions(+), 1 deletion(-) | ||
21 | create mode 100644 include/hw/misc/allwinner-sid.h | ||
22 | create mode 100644 hw/misc/allwinner-sid.c | ||
23 | 29 | ||
24 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 30 | diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c |
25 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/misc/Makefile.objs | 32 | --- a/hw/timer/nrf51_timer.c |
27 | +++ b/hw/misc/Makefile.objs | 33 | +++ b/hw/timer/nrf51_timer.c |
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o | 34 | @@ -XXX,XX +XXX,XX @@ static uint32_t update_counter(NRF51TimerState *s, int64_t now) |
29 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o | 35 | uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns); |
30 | obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o | 36 | |
31 | common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o | 37 | s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]); |
32 | +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o | 38 | - s->update_counter_ns = now; |
33 | common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o | 39 | + /* |
34 | common-obj-$(CONFIG_NSERIES) += cbus.o | 40 | + * Only advance the sync time to the timestamp of the last tick, |
35 | common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o | 41 | + * not all the way to 'now', so we don't lose time if we do |
36 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 42 | + * multiple resyncs in a single tick. |
37 | index XXXXXXX..XXXXXXX 100644 | 43 | + */ |
38 | --- a/include/hw/arm/allwinner-h3.h | 44 | + s->update_counter_ns += ticks_to_ns(s, ticks); |
39 | +++ b/include/hw/arm/allwinner-h3.h | 45 | return ticks; |
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | #include "hw/misc/allwinner-h3-ccu.h" | ||
42 | #include "hw/misc/allwinner-cpucfg.h" | ||
43 | #include "hw/misc/allwinner-h3-sysctrl.h" | ||
44 | +#include "hw/misc/allwinner-sid.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | |||
47 | /** | ||
48 | @@ -XXX,XX +XXX,XX @@ enum { | ||
49 | AW_H3_SRAM_A2, | ||
50 | AW_H3_SRAM_C, | ||
51 | AW_H3_SYSCTRL, | ||
52 | + AW_H3_SID, | ||
53 | AW_H3_EHCI0, | ||
54 | AW_H3_OHCI0, | ||
55 | AW_H3_EHCI1, | ||
56 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
57 | AwH3ClockCtlState ccu; | ||
58 | AwCpuCfgState cpucfg; | ||
59 | AwH3SysCtrlState sysctrl; | ||
60 | + AwSidState sid; | ||
61 | GICState gic; | ||
62 | MemoryRegion sram_a1; | ||
63 | MemoryRegion sram_a2; | ||
64 | diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h | ||
65 | new file mode 100644 | ||
66 | index XXXXXXX..XXXXXXX | ||
67 | --- /dev/null | ||
68 | +++ b/include/hw/misc/allwinner-sid.h | ||
69 | @@ -XXX,XX +XXX,XX @@ | ||
70 | +/* | ||
71 | + * Allwinner Security ID emulation | ||
72 | + * | ||
73 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
74 | + * | ||
75 | + * This program is free software: you can redistribute it and/or modify | ||
76 | + * it under the terms of the GNU General Public License as published by | ||
77 | + * the Free Software Foundation, either version 2 of the License, or | ||
78 | + * (at your option) any later version. | ||
79 | + * | ||
80 | + * This program is distributed in the hope that it will be useful, | ||
81 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
82 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
83 | + * GNU General Public License for more details. | ||
84 | + * | ||
85 | + * You should have received a copy of the GNU General Public License | ||
86 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
87 | + */ | ||
88 | + | ||
89 | +#ifndef HW_MISC_ALLWINNER_SID_H | ||
90 | +#define HW_MISC_ALLWINNER_SID_H | ||
91 | + | ||
92 | +#include "qom/object.h" | ||
93 | +#include "hw/sysbus.h" | ||
94 | +#include "qemu/uuid.h" | ||
95 | + | ||
96 | +/** | ||
97 | + * Object model | ||
98 | + * @{ | ||
99 | + */ | ||
100 | + | ||
101 | +#define TYPE_AW_SID "allwinner-sid" | ||
102 | +#define AW_SID(obj) \ | ||
103 | + OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID) | ||
104 | + | ||
105 | +/** @} */ | ||
106 | + | ||
107 | +/** | ||
108 | + * Allwinner Security ID object instance state | ||
109 | + */ | ||
110 | +typedef struct AwSidState { | ||
111 | + /*< private >*/ | ||
112 | + SysBusDevice parent_obj; | ||
113 | + /*< public >*/ | ||
114 | + | ||
115 | + /** Maps I/O registers in physical memory */ | ||
116 | + MemoryRegion iomem; | ||
117 | + | ||
118 | + /** Control register defines how and what to read */ | ||
119 | + uint32_t control; | ||
120 | + | ||
121 | + /** RdKey register contains the data retrieved by the device */ | ||
122 | + uint32_t rdkey; | ||
123 | + | ||
124 | + /** Stores the emulated device identifier */ | ||
125 | + QemuUUID identifier; | ||
126 | + | ||
127 | +} AwSidState; | ||
128 | + | ||
129 | +#endif /* HW_MISC_ALLWINNER_SID_H */ | ||
130 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
131 | index XXXXXXX..XXXXXXX 100644 | ||
132 | --- a/hw/arm/allwinner-h3.c | ||
133 | +++ b/hw/arm/allwinner-h3.c | ||
134 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
135 | [AW_H3_SRAM_A2] = 0x00044000, | ||
136 | [AW_H3_SRAM_C] = 0x00010000, | ||
137 | [AW_H3_SYSCTRL] = 0x01c00000, | ||
138 | + [AW_H3_SID] = 0x01c14000, | ||
139 | [AW_H3_EHCI0] = 0x01c1a000, | ||
140 | [AW_H3_OHCI0] = 0x01c1a400, | ||
141 | [AW_H3_EHCI1] = 0x01c1b000, | ||
142 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
143 | { "mmc0", 0x01c0f000, 4 * KiB }, | ||
144 | { "mmc1", 0x01c10000, 4 * KiB }, | ||
145 | { "mmc2", 0x01c11000, 4 * KiB }, | ||
146 | - { "sid", 0x01c14000, 1 * KiB }, | ||
147 | { "crypto", 0x01c15000, 4 * KiB }, | ||
148 | { "msgbox", 0x01c17000, 4 * KiB }, | ||
149 | { "spinlock", 0x01c18000, 4 * KiB }, | ||
150 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
151 | |||
152 | sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), | ||
153 | TYPE_AW_CPUCFG); | ||
154 | + | ||
155 | + sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), | ||
156 | + TYPE_AW_SID); | ||
157 | + object_property_add_alias(obj, "identifier", OBJECT(&s->sid), | ||
158 | + "identifier", &error_abort); | ||
159 | } | 46 | } |
160 | 47 | ||
161 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
162 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
163 | qdev_init_nofail(DEVICE(&s->cpucfg)); | ||
164 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); | ||
165 | |||
166 | + /* Security Identifier */ | ||
167 | + qdev_init_nofail(DEVICE(&s->sid)); | ||
168 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); | ||
169 | + | ||
170 | /* Universal Serial Bus */ | ||
171 | sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], | ||
172 | qdev_get_gpio_in(DEVICE(&s->gic), | ||
173 | diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c | ||
174 | index XXXXXXX..XXXXXXX 100644 | ||
175 | --- a/hw/arm/orangepi.c | ||
176 | +++ b/hw/arm/orangepi.c | ||
177 | @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) | ||
178 | object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq", | ||
179 | &error_abort); | ||
180 | |||
181 | + /* Setup SID properties. Currently using a default fixed SID identifier. */ | ||
182 | + if (qemu_uuid_is_null(&h3->sid.identifier)) { | ||
183 | + qdev_prop_set_string(DEVICE(h3), "identifier", | ||
184 | + "02c00081-1111-2222-3333-000044556677"); | ||
185 | + } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) { | ||
186 | + warn_report("Security Identifier value does not include H3 prefix"); | ||
187 | + } | ||
188 | + | ||
189 | /* Mark H3 object realized */ | ||
190 | object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); | ||
191 | |||
192 | diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c | ||
193 | new file mode 100644 | ||
194 | index XXXXXXX..XXXXXXX | ||
195 | --- /dev/null | ||
196 | +++ b/hw/misc/allwinner-sid.c | ||
197 | @@ -XXX,XX +XXX,XX @@ | ||
198 | +/* | ||
199 | + * Allwinner Security ID emulation | ||
200 | + * | ||
201 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
202 | + * | ||
203 | + * This program is free software: you can redistribute it and/or modify | ||
204 | + * it under the terms of the GNU General Public License as published by | ||
205 | + * the Free Software Foundation, either version 2 of the License, or | ||
206 | + * (at your option) any later version. | ||
207 | + * | ||
208 | + * This program is distributed in the hope that it will be useful, | ||
209 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
210 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
211 | + * GNU General Public License for more details. | ||
212 | + * | ||
213 | + * You should have received a copy of the GNU General Public License | ||
214 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
215 | + */ | ||
216 | + | ||
217 | +#include "qemu/osdep.h" | ||
218 | +#include "qemu/units.h" | ||
219 | +#include "hw/sysbus.h" | ||
220 | +#include "migration/vmstate.h" | ||
221 | +#include "qemu/log.h" | ||
222 | +#include "qemu/module.h" | ||
223 | +#include "qemu/guest-random.h" | ||
224 | +#include "qapi/error.h" | ||
225 | +#include "hw/qdev-properties.h" | ||
226 | +#include "hw/misc/allwinner-sid.h" | ||
227 | +#include "trace.h" | ||
228 | + | ||
229 | +/* SID register offsets */ | ||
230 | +enum { | ||
231 | + REG_PRCTL = 0x40, /* Control */ | ||
232 | + REG_RDKEY = 0x60, /* Read Key */ | ||
233 | +}; | ||
234 | + | ||
235 | +/* SID register flags */ | ||
236 | +enum { | ||
237 | + REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */ | ||
238 | + REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */ | ||
239 | +}; | ||
240 | + | ||
241 | +static uint64_t allwinner_sid_read(void *opaque, hwaddr offset, | ||
242 | + unsigned size) | ||
243 | +{ | ||
244 | + const AwSidState *s = AW_SID(opaque); | ||
245 | + uint64_t val = 0; | ||
246 | + | ||
247 | + switch (offset) { | ||
248 | + case REG_PRCTL: /* Control */ | ||
249 | + val = s->control; | ||
250 | + break; | ||
251 | + case REG_RDKEY: /* Read Key */ | ||
252 | + val = s->rdkey; | ||
253 | + break; | ||
254 | + default: | ||
255 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
256 | + __func__, (uint32_t)offset); | ||
257 | + return 0; | ||
258 | + } | ||
259 | + | ||
260 | + trace_allwinner_sid_read(offset, val, size); | ||
261 | + | ||
262 | + return val; | ||
263 | +} | ||
264 | + | ||
265 | +static void allwinner_sid_write(void *opaque, hwaddr offset, | ||
266 | + uint64_t val, unsigned size) | ||
267 | +{ | ||
268 | + AwSidState *s = AW_SID(opaque); | ||
269 | + | ||
270 | + trace_allwinner_sid_write(offset, val, size); | ||
271 | + | ||
272 | + switch (offset) { | ||
273 | + case REG_PRCTL: /* Control */ | ||
274 | + s->control = val; | ||
275 | + | ||
276 | + if ((s->control & REG_PRCTL_OP_LOCK) && | ||
277 | + (s->control & REG_PRCTL_WRITE)) { | ||
278 | + uint32_t id = s->control >> 16; | ||
279 | + | ||
280 | + if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) { | ||
281 | + s->rdkey = ldl_be_p(&s->identifier.data[id]); | ||
282 | + } | ||
283 | + } | ||
284 | + s->control &= ~REG_PRCTL_WRITE; | ||
285 | + break; | ||
286 | + case REG_RDKEY: /* Read Key */ | ||
287 | + break; | ||
288 | + default: | ||
289 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
290 | + __func__, (uint32_t)offset); | ||
291 | + break; | ||
292 | + } | ||
293 | +} | ||
294 | + | ||
295 | +static const MemoryRegionOps allwinner_sid_ops = { | ||
296 | + .read = allwinner_sid_read, | ||
297 | + .write = allwinner_sid_write, | ||
298 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
299 | + .valid = { | ||
300 | + .min_access_size = 4, | ||
301 | + .max_access_size = 4, | ||
302 | + }, | ||
303 | + .impl.min_access_size = 4, | ||
304 | +}; | ||
305 | + | ||
306 | +static void allwinner_sid_reset(DeviceState *dev) | ||
307 | +{ | ||
308 | + AwSidState *s = AW_SID(dev); | ||
309 | + | ||
310 | + /* Set default values for registers */ | ||
311 | + s->control = 0; | ||
312 | + s->rdkey = 0; | ||
313 | +} | ||
314 | + | ||
315 | +static void allwinner_sid_init(Object *obj) | ||
316 | +{ | ||
317 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
318 | + AwSidState *s = AW_SID(obj); | ||
319 | + | ||
320 | + /* Memory mapping */ | ||
321 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s, | ||
322 | + TYPE_AW_SID, 1 * KiB); | ||
323 | + sysbus_init_mmio(sbd, &s->iomem); | ||
324 | +} | ||
325 | + | ||
326 | +static Property allwinner_sid_properties[] = { | ||
327 | + DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier), | ||
328 | + DEFINE_PROP_END_OF_LIST() | ||
329 | +}; | ||
330 | + | ||
331 | +static const VMStateDescription allwinner_sid_vmstate = { | ||
332 | + .name = "allwinner-sid", | ||
333 | + .version_id = 1, | ||
334 | + .minimum_version_id = 1, | ||
335 | + .fields = (VMStateField[]) { | ||
336 | + VMSTATE_UINT32(control, AwSidState), | ||
337 | + VMSTATE_UINT32(rdkey, AwSidState), | ||
338 | + VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1), | ||
339 | + VMSTATE_END_OF_LIST() | ||
340 | + } | ||
341 | +}; | ||
342 | + | ||
343 | +static void allwinner_sid_class_init(ObjectClass *klass, void *data) | ||
344 | +{ | ||
345 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
346 | + | ||
347 | + dc->reset = allwinner_sid_reset; | ||
348 | + dc->vmsd = &allwinner_sid_vmstate; | ||
349 | + device_class_set_props(dc, allwinner_sid_properties); | ||
350 | +} | ||
351 | + | ||
352 | +static const TypeInfo allwinner_sid_info = { | ||
353 | + .name = TYPE_AW_SID, | ||
354 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
355 | + .instance_init = allwinner_sid_init, | ||
356 | + .instance_size = sizeof(AwSidState), | ||
357 | + .class_init = allwinner_sid_class_init, | ||
358 | +}; | ||
359 | + | ||
360 | +static void allwinner_sid_register(void) | ||
361 | +{ | ||
362 | + type_register_static(&allwinner_sid_info); | ||
363 | +} | ||
364 | + | ||
365 | +type_init(allwinner_sid_register) | ||
366 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
367 | index XXXXXXX..XXXXXXX 100644 | ||
368 | --- a/hw/misc/trace-events | ||
369 | +++ b/hw/misc/trace-events | ||
370 | @@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad | ||
371 | allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
372 | allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
373 | |||
374 | +# allwinner-sid.c | ||
375 | +allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
376 | +allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 | ||
377 | + | ||
378 | # eccmemctl.c | ||
379 | ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" | ||
380 | ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" | ||
381 | -- | 48 | -- |
382 | 2.20.1 | 49 | 2.34.1 |
383 | |||
384 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The Allwinner H3 System on Chip contains multiple USB 2.0 bus | 3 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
4 | connections which provide software access using the Enhanced | 4 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
5 | Host Controller Interface (EHCI) and Open Host Controller | 5 | Message-id: 20230607092112.655098-1-marcin.juszkiewicz@linaro.org |
6 | Interface (OHCI) interfaces. This commit adds support for | ||
7 | both interfaces in the Allwinner H3 System on Chip. | ||
8 | |||
9 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
10 | Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
12 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
13 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
14 | Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 7 | --- |
17 | hw/usb/hcd-ehci.h | 1 + | 8 | hw/arm/Kconfig | 1 + |
18 | include/hw/arm/allwinner-h3.h | 8 +++++++ | 9 | 1 file changed, 1 insertion(+) |
19 | hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++ | ||
20 | hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++ | ||
21 | hw/arm/Kconfig | 2 ++ | ||
22 | 5 files changed, 72 insertions(+) | ||
23 | 10 | ||
24 | diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/usb/hcd-ehci.h | ||
27 | +++ b/hw/usb/hcd-ehci.h | ||
28 | @@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState { | ||
29 | #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" | ||
30 | #define TYPE_PLATFORM_EHCI "platform-ehci-usb" | ||
31 | #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" | ||
32 | +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" | ||
33 | #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" | ||
34 | #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" | ||
35 | #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" | ||
36 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/include/hw/arm/allwinner-h3.h | ||
39 | +++ b/include/hw/arm/allwinner-h3.h | ||
40 | @@ -XXX,XX +XXX,XX @@ enum { | ||
41 | AW_H3_SRAM_A1, | ||
42 | AW_H3_SRAM_A2, | ||
43 | AW_H3_SRAM_C, | ||
44 | + AW_H3_EHCI0, | ||
45 | + AW_H3_OHCI0, | ||
46 | + AW_H3_EHCI1, | ||
47 | + AW_H3_OHCI1, | ||
48 | + AW_H3_EHCI2, | ||
49 | + AW_H3_OHCI2, | ||
50 | + AW_H3_EHCI3, | ||
51 | + AW_H3_OHCI3, | ||
52 | AW_H3_CCU, | ||
53 | AW_H3_PIT, | ||
54 | AW_H3_UART0, | ||
55 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/hw/arm/allwinner-h3.c | ||
58 | +++ b/hw/arm/allwinner-h3.c | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | #include "hw/sysbus.h" | ||
61 | #include "hw/char/serial.h" | ||
62 | #include "hw/misc/unimp.h" | ||
63 | +#include "hw/usb/hcd-ehci.h" | ||
64 | #include "sysemu/sysemu.h" | ||
65 | #include "hw/arm/allwinner-h3.h" | ||
66 | |||
67 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
68 | [AW_H3_SRAM_A1] = 0x00000000, | ||
69 | [AW_H3_SRAM_A2] = 0x00044000, | ||
70 | [AW_H3_SRAM_C] = 0x00010000, | ||
71 | + [AW_H3_EHCI0] = 0x01c1a000, | ||
72 | + [AW_H3_OHCI0] = 0x01c1a400, | ||
73 | + [AW_H3_EHCI1] = 0x01c1b000, | ||
74 | + [AW_H3_OHCI1] = 0x01c1b400, | ||
75 | + [AW_H3_EHCI2] = 0x01c1c000, | ||
76 | + [AW_H3_OHCI2] = 0x01c1c400, | ||
77 | + [AW_H3_EHCI3] = 0x01c1d000, | ||
78 | + [AW_H3_OHCI3] = 0x01c1d400, | ||
79 | [AW_H3_CCU] = 0x01c20000, | ||
80 | [AW_H3_PIT] = 0x01c20c00, | ||
81 | [AW_H3_UART0] = 0x01c28000, | ||
82 | @@ -XXX,XX +XXX,XX @@ enum { | ||
83 | AW_H3_GIC_SPI_UART3 = 3, | ||
84 | AW_H3_GIC_SPI_TIMER0 = 18, | ||
85 | AW_H3_GIC_SPI_TIMER1 = 19, | ||
86 | + AW_H3_GIC_SPI_EHCI0 = 72, | ||
87 | + AW_H3_GIC_SPI_OHCI0 = 73, | ||
88 | + AW_H3_GIC_SPI_EHCI1 = 74, | ||
89 | + AW_H3_GIC_SPI_OHCI1 = 75, | ||
90 | + AW_H3_GIC_SPI_EHCI2 = 76, | ||
91 | + AW_H3_GIC_SPI_OHCI2 = 77, | ||
92 | + AW_H3_GIC_SPI_EHCI3 = 78, | ||
93 | + AW_H3_GIC_SPI_OHCI3 = 79, | ||
94 | }; | ||
95 | |||
96 | /* Allwinner H3 general constants */ | ||
97 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
98 | qdev_init_nofail(DEVICE(&s->ccu)); | ||
99 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); | ||
100 | |||
101 | + /* Universal Serial Bus */ | ||
102 | + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], | ||
103 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
104 | + AW_H3_GIC_SPI_EHCI0)); | ||
105 | + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1], | ||
106 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
107 | + AW_H3_GIC_SPI_EHCI1)); | ||
108 | + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2], | ||
109 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
110 | + AW_H3_GIC_SPI_EHCI2)); | ||
111 | + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3], | ||
112 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
113 | + AW_H3_GIC_SPI_EHCI3)); | ||
114 | + | ||
115 | + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0], | ||
116 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
117 | + AW_H3_GIC_SPI_OHCI0)); | ||
118 | + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1], | ||
119 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
120 | + AW_H3_GIC_SPI_OHCI1)); | ||
121 | + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2], | ||
122 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
123 | + AW_H3_GIC_SPI_OHCI2)); | ||
124 | + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3], | ||
125 | + qdev_get_gpio_in(DEVICE(&s->gic), | ||
126 | + AW_H3_GIC_SPI_OHCI3)); | ||
127 | + | ||
128 | /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ | ||
129 | serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, | ||
130 | qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), | ||
131 | diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/hw/usb/hcd-ehci-sysbus.c | ||
134 | +++ b/hw/usb/hcd-ehci-sysbus.c | ||
135 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = { | ||
136 | .class_init = ehci_exynos4210_class_init, | ||
137 | }; | ||
138 | |||
139 | +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) | ||
140 | +{ | ||
141 | + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); | ||
142 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
143 | + | ||
144 | + sec->capsbase = 0x0; | ||
145 | + sec->opregbase = 0x10; | ||
146 | + set_bit(DEVICE_CATEGORY_USB, dc->categories); | ||
147 | +} | ||
148 | + | ||
149 | +static const TypeInfo ehci_aw_h3_type_info = { | ||
150 | + .name = TYPE_AW_H3_EHCI, | ||
151 | + .parent = TYPE_SYS_BUS_EHCI, | ||
152 | + .class_init = ehci_aw_h3_class_init, | ||
153 | +}; | ||
154 | + | ||
155 | static void ehci_tegra2_class_init(ObjectClass *oc, void *data) | ||
156 | { | ||
157 | SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); | ||
158 | @@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void) | ||
159 | type_register_static(&ehci_type_info); | ||
160 | type_register_static(&ehci_platform_type_info); | ||
161 | type_register_static(&ehci_exynos4210_type_info); | ||
162 | + type_register_static(&ehci_aw_h3_type_info); | ||
163 | type_register_static(&ehci_tegra2_type_info); | ||
164 | type_register_static(&ehci_ppc4xx_type_info); | ||
165 | type_register_static(&ehci_fusbh200_type_info); | ||
166 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 11 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
167 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
168 | --- a/hw/arm/Kconfig | 13 | --- a/hw/arm/Kconfig |
169 | +++ b/hw/arm/Kconfig | 14 | +++ b/hw/arm/Kconfig |
170 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3 | 15 | @@ -XXX,XX +XXX,XX @@ config SBSA_REF |
171 | select ARM_TIMER | 16 | select PL061 # GPIO |
172 | select ARM_GIC | 17 | select USB_EHCI_SYSBUS |
173 | select UNIMP | 18 | select WDT_SBSA |
174 | + select USB_OHCI | 19 | + select BOCHS_DISPLAY |
175 | + select USB_EHCI_SYSBUS | 20 | |
176 | 21 | config SABRELITE | |
177 | config RASPI | ||
178 | bool | 22 | bool |
179 | -- | 23 | -- |
180 | 2.20.1 | 24 | 2.34.1 |
181 | |||
182 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Martin Kaiser <martin@kaiser.cx> |
---|---|---|---|
2 | 2 | ||
3 | We must include the tag in the FAR_ELx register when raising | 3 | The Linux kernel added a flood check for RX data recently in commit |
4 | an addressing exception. Which means that we should not clear | 4 | 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This |
5 | out the tag during translation. | 5 | check uses the wake bit in the UART status register 2. The wake bit |
6 | indicates that the receiver detected a start bit on the RX line. If the | ||
7 | kernel sees a number of RX interrupts without the wake bit being set, it | ||
8 | treats this as spurious data and resets the UART port. imx_serial does | ||
9 | never set the wake bit and triggers the kernel's flood check. | ||
6 | 10 | ||
7 | We cannot at present comply with this for user mode, so we | 11 | This patch adds support for the wake bit. wake is set when we receive a |
8 | retain the clean_data_tbi function for the moment, though it | 12 | new character (it's not set for break events). It seems that wake is |
9 | no longer does what it says on the tin for system mode. This | 13 | cleared by the kernel driver, the hardware does not have to clear it |
10 | function is to be replaced with MTE, so don't worry about the | 14 | automatically after data was read. |
11 | slight misnaming. | ||
12 | 15 | ||
13 | Buglink: https://bugs.launchpad.net/qemu/+bug/1867072 | 16 | The wake bit can be configured as an interrupt source. Support this |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 17 | mechanism as well. |
15 | Message-id: 20200308012946.16303-3-richard.henderson@linaro.org | 18 | |
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
21 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
22 | Signed-off-by: Martin Kaiser <martin@kaiser.cx> | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 24 | --- |
19 | target/arm/translate-a64.c | 11 +++++++++++ | 25 | include/hw/char/imx_serial.h | 1 + |
20 | 1 file changed, 11 insertions(+) | 26 | hw/char/imx_serial.c | 5 ++++- |
27 | 2 files changed, 5 insertions(+), 1 deletion(-) | ||
21 | 28 | ||
22 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 29 | diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h |
23 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/translate-a64.c | 31 | --- a/include/hw/char/imx_serial.h |
25 | +++ b/target/arm/translate-a64.c | 32 | +++ b/include/hw/char/imx_serial.h |
26 | @@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | 33 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) |
27 | static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | 34 | |
35 | #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ | ||
36 | #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ | ||
37 | +#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ | ||
38 | |||
39 | #define UTS1_TXEMPTY (1<<6) | ||
40 | #define UTS1_RXEMPTY (1<<5) | ||
41 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/hw/char/imx_serial.c | ||
44 | +++ b/hw/char/imx_serial.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s) | ||
46 | * TCEN and TXDC are both bit 3 | ||
47 | * RDR and DREN are both bit 0 | ||
48 | */ | ||
49 | - mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN); | ||
50 | + mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN); | ||
51 | |||
52 | usr2 = s->usr2 & mask; | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static void imx_put_data(void *opaque, uint32_t value) | ||
55 | |||
56 | static void imx_receive(void *opaque, const uint8_t *buf, int size) | ||
28 | { | 57 | { |
29 | TCGv_i64 clean = new_tmp_a64(s); | 58 | + IMXSerialState *s = (IMXSerialState *)opaque; |
30 | + /* | 59 | + |
31 | + * In order to get the correct value in the FAR_ELx register, | 60 | + s->usr2 |= USR2_WAKE; |
32 | + * we must present the memory subsystem with the "dirty" address | 61 | imx_put_data(opaque, *buf); |
33 | + * including the TBI. In system mode we can make this work via | ||
34 | + * the TLB, dropping the TBI during translation. But for user-only | ||
35 | + * mode we don't have that option, and must remove the top byte now. | ||
36 | + */ | ||
37 | +#ifdef CONFIG_USER_ONLY | ||
38 | gen_top_byte_ignore(s, clean, addr, s->tbid); | ||
39 | +#else | ||
40 | + tcg_gen_mov_i64(clean, addr); | ||
41 | +#endif | ||
42 | return clean; | ||
43 | } | 62 | } |
44 | 63 | ||
45 | -- | 64 | -- |
46 | 2.20.1 | 65 | 2.34.1 |
47 | 66 | ||
48 | 67 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We fail to validate the upper bits of a virtual address on a | 3 | We plan to add more hardware information into DeviceTree to limit amount |
4 | translation disabled regime, as per AArch64.TranslateAddressS1Off. | 4 | of hardcoded values in firmware. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
7 | Message-id: 20200308012946.16303-2-richard.henderson@linaro.org | 7 | Message-id: 20230531171834.236569-1-marcin.juszkiewicz@linaro.org |
8 | [PMM: fix format nits, add text about platform version fields from | ||
9 | a comment in the C source file] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 12 | --- |
11 | target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++- | 13 | docs/system/arm/sbsa.rst | 38 +++++++++++++++++++++++++++++++------- |
12 | 1 file changed, 34 insertions(+), 1 deletion(-) | 14 | 1 file changed, 31 insertions(+), 7 deletions(-) |
13 | 15 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 18 | --- a/docs/system/arm/sbsa.rst |
17 | +++ b/target/arm/helper.c | 19 | +++ b/docs/system/arm/sbsa.rst |
18 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | 20 | @@ -XXX,XX +XXX,XX @@ any real hardware the ``sbsa-ref`` board intends to look like real |
19 | /* Definitely a real MMU, not an MPU */ | 21 | hardware. The `Server Base System Architecture |
20 | 22 | <https://developer.arm.com/documentation/den0029/latest>`_ defines a | |
21 | if (regime_translation_disabled(env, mmu_idx)) { | 23 | minimum base line of hardware support and importantly how the firmware |
22 | - /* MMU disabled. */ | 24 | -reports that to any operating system. It is a static system that |
23 | + /* | 25 | -reports a very minimal DT to the firmware for non-discoverable |
24 | + * MMU disabled. S1 addresses within aa64 translation regimes are | 26 | -information about components affected by the qemu command line (i.e. |
25 | + * still checked for bounds -- see AArch64.TranslateAddressS1Off. | 27 | -cpus and memory). As a result it must have a firmware specifically |
26 | + */ | 28 | -built to expect a certain hardware layout (as you would in a real |
27 | + if (mmu_idx != ARMMMUIdx_Stage2) { | 29 | -machine). |
28 | + int r_el = regime_el(env, mmu_idx); | 30 | +reports that to any operating system. |
29 | + if (arm_el_is_aa64(env, r_el)) { | 31 | |
30 | + int pamax = arm_pamax(env_archcpu(env)); | 32 | It is intended to be a machine for developing firmware and testing |
31 | + uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; | 33 | standards compliance with operating systems. |
32 | + int addrtop, tbi; | 34 | @@ -XXX,XX +XXX,XX @@ standards compliance with operating systems. |
35 | Supported devices | ||
36 | """"""""""""""""" | ||
37 | |||
38 | -The sbsa-ref board supports: | ||
39 | +The ``sbsa-ref`` board supports: | ||
40 | |||
41 | - A configurable number of AArch64 CPUs | ||
42 | - GIC version 3 | ||
43 | @@ -XXX,XX +XXX,XX @@ The sbsa-ref board supports: | ||
44 | - Bochs display adapter on PCIe bus | ||
45 | - A generic SBSA watchdog device | ||
46 | |||
33 | + | 47 | + |
34 | + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | 48 | +Board to firmware interface |
35 | + if (access_type == MMU_INST_FETCH) { | 49 | +""""""""""""""""""""""""""" |
36 | + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | ||
37 | + } | ||
38 | + tbi = (tbi >> extract64(address, 55, 1)) & 1; | ||
39 | + addrtop = (tbi ? 55 : 63); | ||
40 | + | 50 | + |
41 | + if (extract64(address, pamax, addrtop - pamax + 1) != 0) { | 51 | +``sbsa-ref`` is a static system that reports a very minimal devicetree to the |
42 | + fi->type = ARMFault_AddressSize; | 52 | +firmware for non-discoverable information about system components. This |
43 | + fi->level = 0; | 53 | +includes both internal hardware and parts affected by the qemu command line |
44 | + fi->stage2 = false; | 54 | +(i.e. CPUs and memory). As a result it must have a firmware specifically built |
45 | + return 1; | 55 | +to expect a certain hardware layout (as you would in a real machine). |
46 | + } | ||
47 | + | 56 | + |
48 | + /* | 57 | +DeviceTree information |
49 | + * When TBI is disabled, we've just validated that all of the | 58 | +'''''''''''''''''''''' |
50 | + * bits above PAMax are zero, so logically we only need to | 59 | + |
51 | + * clear the top byte for TBI. But it's clearer to follow | 60 | +The devicetree provided by the board model to the firmware is not intended |
52 | + * the pseudocode set of addrdesc.paddress. | 61 | +to be a complete compliant DT. It currently reports: |
53 | + */ | 62 | + |
54 | + address = extract64(address, 0, 52); | 63 | + - CPUs |
55 | + } | 64 | + - memory |
56 | + } | 65 | + - platform version |
57 | *phys_ptr = address; | 66 | + - GIC addresses |
58 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | 67 | + |
59 | *page_size = TARGET_PAGE_SIZE; | 68 | +The platform version is only for informing platform firmware about |
69 | +what kind of ``sbsa-ref`` board it is running on. It is neither | ||
70 | +a QEMU versioned machine type nor a reflection of the level of the | ||
71 | +SBSA/SystemReady SR support provided. | ||
72 | + | ||
73 | +The ``machine-version-major`` value is updated when changes breaking | ||
74 | +fw compatibility are introduced. The ``machine-version-minor`` value | ||
75 | +is updated when features are added that don't break fw compatibility. | ||
60 | -- | 76 | -- |
61 | 2.20.1 | 77 | 2.34.1 |
62 | |||
63 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | From: Sergey Kambalin <sergey.kambalin@auriga.com> |
---|---|---|---|
2 | 2 | ||
3 | The Clock Control Unit is responsible for clock signal generation, | 3 | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> |
4 | configuration and distribution in the Allwinner H3 System on Chip. | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | This commit adds support for the Clock Control Unit which emulates | 5 | Acked-by: Richard Henderson <richard.henderson@linaro.org> |
6 | a simple read/write register interface. | 6 | Message-id: 20230612223456.33824-2-philmd@linaro.org |
7 | 7 | Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> | |
8 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 8 | [PMD: Split from bigger patch: 1/4] |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
12 | Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 11 | --- |
15 | hw/misc/Makefile.objs | 1 + | 12 | include/hw/misc/raspberrypi-fw-defs.h | 163 ++++++++++++++++++++++++++ |
16 | include/hw/arm/allwinner-h3.h | 3 + | 13 | 1 file changed, 163 insertions(+) |
17 | include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++ | 14 | create mode 100644 include/hw/misc/raspberrypi-fw-defs.h |
18 | hw/arm/allwinner-h3.c | 9 +- | ||
19 | hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++ | ||
20 | 5 files changed, 320 insertions(+), 1 deletion(-) | ||
21 | create mode 100644 include/hw/misc/allwinner-h3-ccu.h | ||
22 | create mode 100644 hw/misc/allwinner-h3-ccu.c | ||
23 | 15 | ||
24 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 16 | diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/misc/raspberrypi-fw-defs.h |
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/misc/Makefile.objs | ||
27 | +++ b/hw/misc/Makefile.objs | ||
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/ | ||
29 | |||
30 | common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o | ||
31 | |||
32 | +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o | ||
33 | common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o | ||
34 | common-obj-$(CONFIG_NSERIES) += cbus.o | ||
35 | common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o | ||
36 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/include/hw/arm/allwinner-h3.h | ||
39 | +++ b/include/hw/arm/allwinner-h3.h | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | #include "hw/arm/boot.h" | ||
42 | #include "hw/timer/allwinner-a10-pit.h" | ||
43 | #include "hw/intc/arm_gic.h" | ||
44 | +#include "hw/misc/allwinner-h3-ccu.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | |||
47 | /** | ||
48 | @@ -XXX,XX +XXX,XX @@ enum { | ||
49 | AW_H3_SRAM_A1, | ||
50 | AW_H3_SRAM_A2, | ||
51 | AW_H3_SRAM_C, | ||
52 | + AW_H3_CCU, | ||
53 | AW_H3_PIT, | ||
54 | AW_H3_UART0, | ||
55 | AW_H3_UART1, | ||
56 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
57 | ARMCPU cpus[AW_H3_NUM_CPUS]; | ||
58 | const hwaddr *memmap; | ||
59 | AwA10PITState timer; | ||
60 | + AwH3ClockCtlState ccu; | ||
61 | GICState gic; | ||
62 | MemoryRegion sram_a1; | ||
63 | MemoryRegion sram_a2; | ||
64 | diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h | ||
65 | new file mode 100644 | 17 | new file mode 100644 |
66 | index XXXXXXX..XXXXXXX | 18 | index XXXXXXX..XXXXXXX |
67 | --- /dev/null | 19 | --- /dev/null |
68 | +++ b/include/hw/misc/allwinner-h3-ccu.h | 20 | +++ b/include/hw/misc/raspberrypi-fw-defs.h |
69 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ |
70 | +/* | 22 | +/* |
71 | + * Allwinner H3 Clock Control Unit emulation | 23 | + * Raspberry Pi firmware definitions |
72 | + * | 24 | + * |
73 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | 25 | + * Copyright (C) 2022 Auriga LLC, based on Linux kernel |
26 | + * `include/soc/bcm2835/raspberrypi-firmware.h` (Copyright © 2015 Broadcom) | ||
74 | + * | 27 | + * |
75 | + * This program is free software: you can redistribute it and/or modify | 28 | + * SPDX-License-Identifier: GPL-2.0-or-later |
76 | + * it under the terms of the GNU General Public License as published by | ||
77 | + * the Free Software Foundation, either version 2 of the License, or | ||
78 | + * (at your option) any later version. | ||
79 | + * | ||
80 | + * This program is distributed in the hope that it will be useful, | ||
81 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
82 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
83 | + * GNU General Public License for more details. | ||
84 | + * | ||
85 | + * You should have received a copy of the GNU General Public License | ||
86 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
87 | + */ | 29 | + */ |
88 | + | 30 | + |
89 | +#ifndef HW_MISC_ALLWINNER_H3_CCU_H | 31 | +#ifndef INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ |
90 | +#define HW_MISC_ALLWINNER_H3_CCU_H | 32 | +#define INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ |
91 | + | ||
92 | +#include "qom/object.h" | ||
93 | +#include "hw/sysbus.h" | ||
94 | + | ||
95 | +/** | ||
96 | + * @name Constants | ||
97 | + * @{ | ||
98 | + */ | ||
99 | + | ||
100 | +/** Size of register I/O address space used by CCU device */ | ||
101 | +#define AW_H3_CCU_IOSIZE (0x400) | ||
102 | + | ||
103 | +/** Total number of known registers */ | ||
104 | +#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t)) | ||
105 | + | ||
106 | +/** @} */ | ||
107 | + | ||
108 | +/** | ||
109 | + * @name Object model | ||
110 | + * @{ | ||
111 | + */ | ||
112 | + | ||
113 | +#define TYPE_AW_H3_CCU "allwinner-h3-ccu" | ||
114 | +#define AW_H3_CCU(obj) \ | ||
115 | + OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU) | ||
116 | + | ||
117 | +/** @} */ | ||
118 | + | ||
119 | +/** | ||
120 | + * Allwinner H3 CCU object instance state. | ||
121 | + */ | ||
122 | +typedef struct AwH3ClockCtlState { | ||
123 | + /*< private >*/ | ||
124 | + SysBusDevice parent_obj; | ||
125 | + /*< public >*/ | ||
126 | + | ||
127 | + /** Maps I/O registers in physical memory */ | ||
128 | + MemoryRegion iomem; | ||
129 | + | ||
130 | + /** Array of hardware registers */ | ||
131 | + uint32_t regs[AW_H3_CCU_REGS_NUM]; | ||
132 | + | ||
133 | +} AwH3ClockCtlState; | ||
134 | + | ||
135 | +#endif /* HW_MISC_ALLWINNER_H3_CCU_H */ | ||
136 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
137 | index XXXXXXX..XXXXXXX 100644 | ||
138 | --- a/hw/arm/allwinner-h3.c | ||
139 | +++ b/hw/arm/allwinner-h3.c | ||
140 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
141 | [AW_H3_SRAM_A1] = 0x00000000, | ||
142 | [AW_H3_SRAM_A2] = 0x00044000, | ||
143 | [AW_H3_SRAM_C] = 0x00010000, | ||
144 | + [AW_H3_CCU] = 0x01c20000, | ||
145 | [AW_H3_PIT] = 0x01c20c00, | ||
146 | [AW_H3_UART0] = 0x01c28000, | ||
147 | [AW_H3_UART1] = 0x01c28400, | ||
148 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
149 | { "usb2-phy", 0x01c1c000, 4 * KiB }, | ||
150 | { "usb3-phy", 0x01c1d000, 4 * KiB }, | ||
151 | { "smc", 0x01c1e000, 4 * KiB }, | ||
152 | - { "ccu", 0x01c20000, 1 * KiB }, | ||
153 | { "pio", 0x01c20800, 1 * KiB }, | ||
154 | { "owa", 0x01c21000, 1 * KiB }, | ||
155 | { "pwm", 0x01c21400, 1 * KiB }, | ||
156 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
157 | "clk0-freq", &error_abort); | ||
158 | object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), | ||
159 | "clk1-freq", &error_abort); | ||
160 | + | ||
161 | + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), | ||
162 | + TYPE_AW_H3_CCU); | ||
163 | } | ||
164 | |||
165 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
166 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
167 | memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], | ||
168 | &s->sram_c); | ||
169 | |||
170 | + /* Clock Control Unit */ | ||
171 | + qdev_init_nofail(DEVICE(&s->ccu)); | ||
172 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); | ||
173 | + | ||
174 | /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ | ||
175 | serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, | ||
176 | qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), | ||
177 | diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c | ||
178 | new file mode 100644 | ||
179 | index XXXXXXX..XXXXXXX | ||
180 | --- /dev/null | ||
181 | +++ b/hw/misc/allwinner-h3-ccu.c | ||
182 | @@ -XXX,XX +XXX,XX @@ | ||
183 | +/* | ||
184 | + * Allwinner H3 Clock Control Unit emulation | ||
185 | + * | ||
186 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
187 | + * | ||
188 | + * This program is free software: you can redistribute it and/or modify | ||
189 | + * it under the terms of the GNU General Public License as published by | ||
190 | + * the Free Software Foundation, either version 2 of the License, or | ||
191 | + * (at your option) any later version. | ||
192 | + * | ||
193 | + * This program is distributed in the hope that it will be useful, | ||
194 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
195 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
196 | + * GNU General Public License for more details. | ||
197 | + * | ||
198 | + * You should have received a copy of the GNU General Public License | ||
199 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
200 | + */ | ||
201 | + | 33 | + |
202 | +#include "qemu/osdep.h" | 34 | +#include "qemu/osdep.h" |
203 | +#include "qemu/units.h" | ||
204 | +#include "hw/sysbus.h" | ||
205 | +#include "migration/vmstate.h" | ||
206 | +#include "qemu/log.h" | ||
207 | +#include "qemu/module.h" | ||
208 | +#include "hw/misc/allwinner-h3-ccu.h" | ||
209 | + | 35 | + |
210 | +/* CCU register offsets */ | 36 | +enum rpi_firmware_property_tag { |
211 | +enum { | 37 | + RPI_FWREQ_PROPERTY_END = 0, |
212 | + REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */ | 38 | + RPI_FWREQ_GET_FIRMWARE_REVISION = 0x00000001, |
213 | + REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */ | 39 | + RPI_FWREQ_GET_FIRMWARE_VARIANT = 0x00000002, |
214 | + REG_PLL_VIDEO = 0x0010, /* PLL Video Control */ | 40 | + RPI_FWREQ_GET_FIRMWARE_HASH = 0x00000003, |
215 | + REG_PLL_VE = 0x0018, /* PLL VE Control */ | 41 | + |
216 | + REG_PLL_DDR = 0x0020, /* PLL DDR Control */ | 42 | + RPI_FWREQ_SET_CURSOR_INFO = 0x00008010, |
217 | + REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */ | 43 | + RPI_FWREQ_SET_CURSOR_STATE = 0x00008011, |
218 | + REG_PLL_GPU = 0x0038, /* PLL GPU Control */ | 44 | + |
219 | + REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */ | 45 | + RPI_FWREQ_GET_BOARD_MODEL = 0x00010001, |
220 | + REG_PLL_DE = 0x0048, /* PLL Display Engine Control */ | 46 | + RPI_FWREQ_GET_BOARD_REVISION = 0x00010002, |
221 | + REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */ | 47 | + RPI_FWREQ_GET_BOARD_MAC_ADDRESS = 0x00010003, |
222 | + REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */ | 48 | + RPI_FWREQ_GET_BOARD_SERIAL = 0x00010004, |
223 | + REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */ | 49 | + RPI_FWREQ_GET_ARM_MEMORY = 0x00010005, |
224 | + REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */ | 50 | + RPI_FWREQ_GET_VC_MEMORY = 0x00010006, |
225 | + REG_MBUS = 0x00FC, /* MBUS Reset */ | 51 | + RPI_FWREQ_GET_CLOCKS = 0x00010007, |
226 | + REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */ | 52 | + RPI_FWREQ_GET_POWER_STATE = 0x00020001, |
227 | + REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */ | 53 | + RPI_FWREQ_GET_TIMING = 0x00020002, |
228 | + REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */ | 54 | + RPI_FWREQ_SET_POWER_STATE = 0x00028001, |
229 | + REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */ | 55 | + RPI_FWREQ_GET_CLOCK_STATE = 0x00030001, |
230 | + REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */ | 56 | + RPI_FWREQ_GET_CLOCK_RATE = 0x00030002, |
231 | + REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */ | 57 | + RPI_FWREQ_GET_VOLTAGE = 0x00030003, |
232 | + REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */ | 58 | + RPI_FWREQ_GET_MAX_CLOCK_RATE = 0x00030004, |
233 | + REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */ | 59 | + RPI_FWREQ_GET_MAX_VOLTAGE = 0x00030005, |
234 | + REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */ | 60 | + RPI_FWREQ_GET_TEMPERATURE = 0x00030006, |
235 | + REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */ | 61 | + RPI_FWREQ_GET_MIN_CLOCK_RATE = 0x00030007, |
236 | + REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */ | 62 | + RPI_FWREQ_GET_MIN_VOLTAGE = 0x00030008, |
237 | + REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */ | 63 | + RPI_FWREQ_GET_TURBO = 0x00030009, |
238 | + REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */ | 64 | + RPI_FWREQ_GET_MAX_TEMPERATURE = 0x0003000a, |
65 | + RPI_FWREQ_GET_STC = 0x0003000b, | ||
66 | + RPI_FWREQ_ALLOCATE_MEMORY = 0x0003000c, | ||
67 | + RPI_FWREQ_LOCK_MEMORY = 0x0003000d, | ||
68 | + RPI_FWREQ_UNLOCK_MEMORY = 0x0003000e, | ||
69 | + RPI_FWREQ_RELEASE_MEMORY = 0x0003000f, | ||
70 | + RPI_FWREQ_EXECUTE_CODE = 0x00030010, | ||
71 | + RPI_FWREQ_EXECUTE_QPU = 0x00030011, | ||
72 | + RPI_FWREQ_SET_ENABLE_QPU = 0x00030012, | ||
73 | + RPI_FWREQ_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014, | ||
74 | + RPI_FWREQ_GET_EDID_BLOCK = 0x00030020, | ||
75 | + RPI_FWREQ_GET_CUSTOMER_OTP = 0x00030021, | ||
76 | + RPI_FWREQ_GET_EDID_BLOCK_DISPLAY = 0x00030023, | ||
77 | + RPI_FWREQ_GET_DOMAIN_STATE = 0x00030030, | ||
78 | + RPI_FWREQ_GET_THROTTLED = 0x00030046, | ||
79 | + RPI_FWREQ_GET_CLOCK_MEASURED = 0x00030047, | ||
80 | + RPI_FWREQ_NOTIFY_REBOOT = 0x00030048, | ||
81 | + RPI_FWREQ_SET_CLOCK_STATE = 0x00038001, | ||
82 | + RPI_FWREQ_SET_CLOCK_RATE = 0x00038002, | ||
83 | + RPI_FWREQ_SET_VOLTAGE = 0x00038003, | ||
84 | + RPI_FWREQ_SET_MAX_CLOCK_RATE = 0x00038004, | ||
85 | + RPI_FWREQ_SET_MIN_CLOCK_RATE = 0x00038007, | ||
86 | + RPI_FWREQ_SET_TURBO = 0x00038009, | ||
87 | + RPI_FWREQ_SET_CUSTOMER_OTP = 0x00038021, | ||
88 | + RPI_FWREQ_SET_DOMAIN_STATE = 0x00038030, | ||
89 | + RPI_FWREQ_GET_GPIO_STATE = 0x00030041, | ||
90 | + RPI_FWREQ_SET_GPIO_STATE = 0x00038041, | ||
91 | + RPI_FWREQ_SET_SDHOST_CLOCK = 0x00038042, | ||
92 | + RPI_FWREQ_GET_GPIO_CONFIG = 0x00030043, | ||
93 | + RPI_FWREQ_SET_GPIO_CONFIG = 0x00038043, | ||
94 | + RPI_FWREQ_GET_PERIPH_REG = 0x00030045, | ||
95 | + RPI_FWREQ_SET_PERIPH_REG = 0x00038045, | ||
96 | + RPI_FWREQ_GET_POE_HAT_VAL = 0x00030049, | ||
97 | + RPI_FWREQ_SET_POE_HAT_VAL = 0x00038049, | ||
98 | + RPI_FWREQ_SET_POE_HAT_VAL_OLD = 0x00030050, | ||
99 | + RPI_FWREQ_NOTIFY_XHCI_RESET = 0x00030058, | ||
100 | + RPI_FWREQ_GET_REBOOT_FLAGS = 0x00030064, | ||
101 | + RPI_FWREQ_SET_REBOOT_FLAGS = 0x00038064, | ||
102 | + RPI_FWREQ_NOTIFY_DISPLAY_DONE = 0x00030066, | ||
103 | + | ||
104 | + /* Dispmanx TAGS */ | ||
105 | + RPI_FWREQ_FRAMEBUFFER_ALLOCATE = 0x00040001, | ||
106 | + RPI_FWREQ_FRAMEBUFFER_BLANK = 0x00040002, | ||
107 | + RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, | ||
108 | + RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, | ||
109 | + RPI_FWREQ_FRAMEBUFFER_GET_DEPTH = 0x00040005, | ||
110 | + RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006, | ||
111 | + RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007, | ||
112 | + RPI_FWREQ_FRAMEBUFFER_GET_PITCH = 0x00040008, | ||
113 | + RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009, | ||
114 | + RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a, | ||
115 | + RPI_FWREQ_FRAMEBUFFER_GET_PALETTE = 0x0004000b, | ||
116 | + RPI_FWREQ_FRAMEBUFFER_GET_LAYER = 0x0004000c, | ||
117 | + RPI_FWREQ_FRAMEBUFFER_GET_TRANSFORM = 0x0004000d, | ||
118 | + RPI_FWREQ_FRAMEBUFFER_GET_VSYNC = 0x0004000e, | ||
119 | + RPI_FWREQ_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f, | ||
120 | + RPI_FWREQ_FRAMEBUFFER_GET_GPIOVIRTBUF = 0x00040010, | ||
121 | + RPI_FWREQ_FRAMEBUFFER_RELEASE = 0x00048001, | ||
122 | + RPI_FWREQ_FRAMEBUFFER_GET_DISPLAY_ID = 0x00040016, | ||
123 | + RPI_FWREQ_FRAMEBUFFER_SET_DISPLAY_NUM = 0x00048013, | ||
124 | + RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS = 0x00040013, | ||
125 | + RPI_FWREQ_FRAMEBUFFER_GET_DISPLAY_SETTINGS = 0x00040014, | ||
126 | + RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, | ||
127 | + RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, | ||
128 | + RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH = 0x00044005, | ||
129 | + RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006, | ||
130 | + RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007, | ||
131 | + RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009, | ||
132 | + RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a, | ||
133 | + RPI_FWREQ_FRAMEBUFFER_TEST_PALETTE = 0x0004400b, | ||
134 | + RPI_FWREQ_FRAMEBUFFER_TEST_LAYER = 0x0004400c, | ||
135 | + RPI_FWREQ_FRAMEBUFFER_TEST_TRANSFORM = 0x0004400d, | ||
136 | + RPI_FWREQ_FRAMEBUFFER_TEST_VSYNC = 0x0004400e, | ||
137 | + RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, | ||
138 | + RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, | ||
139 | + RPI_FWREQ_FRAMEBUFFER_SET_DEPTH = 0x00048005, | ||
140 | + RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006, | ||
141 | + RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007, | ||
142 | + RPI_FWREQ_FRAMEBUFFER_SET_PITCH = 0x00048008, | ||
143 | + RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009, | ||
144 | + RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a, | ||
145 | + RPI_FWREQ_FRAMEBUFFER_SET_PALETTE = 0x0004800b, | ||
146 | + | ||
147 | + RPI_FWREQ_FRAMEBUFFER_SET_TOUCHBUF = 0x0004801f, | ||
148 | + RPI_FWREQ_FRAMEBUFFER_SET_GPIOVIRTBUF = 0x00048020, | ||
149 | + RPI_FWREQ_FRAMEBUFFER_SET_VSYNC = 0x0004800e, | ||
150 | + RPI_FWREQ_FRAMEBUFFER_SET_LAYER = 0x0004800c, | ||
151 | + RPI_FWREQ_FRAMEBUFFER_SET_TRANSFORM = 0x0004800d, | ||
152 | + RPI_FWREQ_FRAMEBUFFER_SET_BACKLIGHT = 0x0004800f, | ||
153 | + | ||
154 | + RPI_FWREQ_VCHIQ_INIT = 0x00048010, | ||
155 | + | ||
156 | + RPI_FWREQ_SET_PLANE = 0x00048015, | ||
157 | + RPI_FWREQ_GET_DISPLAY_TIMING = 0x00040017, | ||
158 | + RPI_FWREQ_SET_TIMING = 0x00048017, | ||
159 | + RPI_FWREQ_GET_DISPLAY_CFG = 0x00040018, | ||
160 | + RPI_FWREQ_SET_DISPLAY_POWER = 0x00048019, | ||
161 | + RPI_FWREQ_GET_COMMAND_LINE = 0x00050001, | ||
162 | + RPI_FWREQ_GET_DMA_CHANNELS = 0x00060001, | ||
239 | +}; | 163 | +}; |
240 | + | 164 | + |
241 | +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) | 165 | +enum rpi_firmware_clk_id { |
242 | + | 166 | + RPI_FIRMWARE_EMMC_CLK_ID = 1, |
243 | +/* CCU register flags */ | 167 | + RPI_FIRMWARE_UART_CLK_ID, |
244 | +enum { | 168 | + RPI_FIRMWARE_ARM_CLK_ID, |
245 | + REG_DRAM_CFG_UPDATE = (1 << 16), | 169 | + RPI_FIRMWARE_CORE_CLK_ID, |
170 | + RPI_FIRMWARE_V3D_CLK_ID, | ||
171 | + RPI_FIRMWARE_H264_CLK_ID, | ||
172 | + RPI_FIRMWARE_ISP_CLK_ID, | ||
173 | + RPI_FIRMWARE_SDRAM_CLK_ID, | ||
174 | + RPI_FIRMWARE_PIXEL_CLK_ID, | ||
175 | + RPI_FIRMWARE_PWM_CLK_ID, | ||
176 | + RPI_FIRMWARE_HEVC_CLK_ID, | ||
177 | + RPI_FIRMWARE_EMMC2_CLK_ID, | ||
178 | + RPI_FIRMWARE_M2MC_CLK_ID, | ||
179 | + RPI_FIRMWARE_PIXEL_BVB_CLK_ID, | ||
180 | + RPI_FIRMWARE_VEC_CLK_ID, | ||
181 | + RPI_FIRMWARE_NUM_CLK_ID, | ||
246 | +}; | 182 | +}; |
247 | + | 183 | + |
248 | +enum { | 184 | +#endif /* INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ */ |
249 | + REG_PLL_ENABLE = (1 << 31), | ||
250 | + REG_PLL_LOCK = (1 << 28), | ||
251 | +}; | ||
252 | + | ||
253 | + | ||
254 | +/* CCU register reset values */ | ||
255 | +enum { | ||
256 | + REG_PLL_CPUX_RST = 0x00001000, | ||
257 | + REG_PLL_AUDIO_RST = 0x00035514, | ||
258 | + REG_PLL_VIDEO_RST = 0x03006207, | ||
259 | + REG_PLL_VE_RST = 0x03006207, | ||
260 | + REG_PLL_DDR_RST = 0x00001000, | ||
261 | + REG_PLL_PERIPH0_RST = 0x00041811, | ||
262 | + REG_PLL_GPU_RST = 0x03006207, | ||
263 | + REG_PLL_PERIPH1_RST = 0x00041811, | ||
264 | + REG_PLL_DE_RST = 0x03006207, | ||
265 | + REG_CPUX_AXI_RST = 0x00010000, | ||
266 | + REG_APB1_RST = 0x00001010, | ||
267 | + REG_APB2_RST = 0x01000000, | ||
268 | + REG_DRAM_CFG_RST = 0x00000000, | ||
269 | + REG_MBUS_RST = 0x80000000, | ||
270 | + REG_PLL_TIME0_RST = 0x000000FF, | ||
271 | + REG_PLL_TIME1_RST = 0x000000FF, | ||
272 | + REG_PLL_CPUX_BIAS_RST = 0x08100200, | ||
273 | + REG_PLL_AUDIO_BIAS_RST = 0x10100000, | ||
274 | + REG_PLL_VIDEO_BIAS_RST = 0x10100000, | ||
275 | + REG_PLL_VE_BIAS_RST = 0x10100000, | ||
276 | + REG_PLL_DDR_BIAS_RST = 0x81104000, | ||
277 | + REG_PLL_PERIPH0_BIAS_RST = 0x10100010, | ||
278 | + REG_PLL_GPU_BIAS_RST = 0x10100000, | ||
279 | + REG_PLL_PERIPH1_BIAS_RST = 0x10100010, | ||
280 | + REG_PLL_DE_BIAS_RST = 0x10100000, | ||
281 | + REG_PLL_CPUX_TUNING_RST = 0x0A101000, | ||
282 | + REG_PLL_DDR_TUNING_RST = 0x14880000, | ||
283 | +}; | ||
284 | + | ||
285 | +static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset, | ||
286 | + unsigned size) | ||
287 | +{ | ||
288 | + const AwH3ClockCtlState *s = AW_H3_CCU(opaque); | ||
289 | + const uint32_t idx = REG_INDEX(offset); | ||
290 | + | ||
291 | + switch (offset) { | ||
292 | + case 0x308 ... AW_H3_CCU_IOSIZE: | ||
293 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
294 | + __func__, (uint32_t)offset); | ||
295 | + return 0; | ||
296 | + } | ||
297 | + | ||
298 | + return s->regs[idx]; | ||
299 | +} | ||
300 | + | ||
301 | +static void allwinner_h3_ccu_write(void *opaque, hwaddr offset, | ||
302 | + uint64_t val, unsigned size) | ||
303 | +{ | ||
304 | + AwH3ClockCtlState *s = AW_H3_CCU(opaque); | ||
305 | + const uint32_t idx = REG_INDEX(offset); | ||
306 | + | ||
307 | + switch (offset) { | ||
308 | + case REG_DRAM_CFG: /* DRAM Configuration */ | ||
309 | + val &= ~REG_DRAM_CFG_UPDATE; | ||
310 | + break; | ||
311 | + case REG_PLL_CPUX: /* PLL CPUX Control */ | ||
312 | + case REG_PLL_AUDIO: /* PLL Audio Control */ | ||
313 | + case REG_PLL_VIDEO: /* PLL Video Control */ | ||
314 | + case REG_PLL_VE: /* PLL VE Control */ | ||
315 | + case REG_PLL_DDR: /* PLL DDR Control */ | ||
316 | + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ | ||
317 | + case REG_PLL_GPU: /* PLL GPU Control */ | ||
318 | + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ | ||
319 | + case REG_PLL_DE: /* PLL Display Engine Control */ | ||
320 | + if (val & REG_PLL_ENABLE) { | ||
321 | + val |= REG_PLL_LOCK; | ||
322 | + } | ||
323 | + break; | ||
324 | + case 0x308 ... AW_H3_CCU_IOSIZE: | ||
325 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
326 | + __func__, (uint32_t)offset); | ||
327 | + break; | ||
328 | + default: | ||
329 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", | ||
330 | + __func__, (uint32_t)offset); | ||
331 | + break; | ||
332 | + } | ||
333 | + | ||
334 | + s->regs[idx] = (uint32_t) val; | ||
335 | +} | ||
336 | + | ||
337 | +static const MemoryRegionOps allwinner_h3_ccu_ops = { | ||
338 | + .read = allwinner_h3_ccu_read, | ||
339 | + .write = allwinner_h3_ccu_write, | ||
340 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
341 | + .valid = { | ||
342 | + .min_access_size = 4, | ||
343 | + .max_access_size = 4, | ||
344 | + }, | ||
345 | + .impl.min_access_size = 4, | ||
346 | +}; | ||
347 | + | ||
348 | +static void allwinner_h3_ccu_reset(DeviceState *dev) | ||
349 | +{ | ||
350 | + AwH3ClockCtlState *s = AW_H3_CCU(dev); | ||
351 | + | ||
352 | + /* Set default values for registers */ | ||
353 | + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; | ||
354 | + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; | ||
355 | + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; | ||
356 | + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; | ||
357 | + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; | ||
358 | + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; | ||
359 | + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; | ||
360 | + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; | ||
361 | + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; | ||
362 | + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; | ||
363 | + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; | ||
364 | + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; | ||
365 | + s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST; | ||
366 | + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; | ||
367 | + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; | ||
368 | + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; | ||
369 | + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; | ||
370 | + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; | ||
371 | + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; | ||
372 | + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; | ||
373 | + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; | ||
374 | + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; | ||
375 | + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; | ||
376 | + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; | ||
377 | + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; | ||
378 | + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; | ||
379 | + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; | ||
380 | +} | ||
381 | + | ||
382 | +static void allwinner_h3_ccu_init(Object *obj) | ||
383 | +{ | ||
384 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
385 | + AwH3ClockCtlState *s = AW_H3_CCU(obj); | ||
386 | + | ||
387 | + /* Memory mapping */ | ||
388 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s, | ||
389 | + TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE); | ||
390 | + sysbus_init_mmio(sbd, &s->iomem); | ||
391 | +} | ||
392 | + | ||
393 | +static const VMStateDescription allwinner_h3_ccu_vmstate = { | ||
394 | + .name = "allwinner-h3-ccu", | ||
395 | + .version_id = 1, | ||
396 | + .minimum_version_id = 1, | ||
397 | + .fields = (VMStateField[]) { | ||
398 | + VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM), | ||
399 | + VMSTATE_END_OF_LIST() | ||
400 | + } | ||
401 | +}; | ||
402 | + | ||
403 | +static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data) | ||
404 | +{ | ||
405 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
406 | + | ||
407 | + dc->reset = allwinner_h3_ccu_reset; | ||
408 | + dc->vmsd = &allwinner_h3_ccu_vmstate; | ||
409 | +} | ||
410 | + | ||
411 | +static const TypeInfo allwinner_h3_ccu_info = { | ||
412 | + .name = TYPE_AW_H3_CCU, | ||
413 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
414 | + .instance_init = allwinner_h3_ccu_init, | ||
415 | + .instance_size = sizeof(AwH3ClockCtlState), | ||
416 | + .class_init = allwinner_h3_ccu_class_init, | ||
417 | +}; | ||
418 | + | ||
419 | +static void allwinner_h3_ccu_register(void) | ||
420 | +{ | ||
421 | + type_register_static(&allwinner_h3_ccu_info); | ||
422 | +} | ||
423 | + | ||
424 | +type_init(allwinner_h3_ccu_register) | ||
425 | -- | 185 | -- |
426 | 2.20.1 | 186 | 2.34.1 |
427 | 187 | ||
428 | 188 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Sergey Kambalin <sergey.kambalin@auriga.com> |
---|---|---|---|
2 | 2 | ||
3 | The kernel image and DeviceTree blob are built by the Armbian | 3 | Replace magic property values by a proper definition, |
4 | project (based on Debian): | 4 | removing redundant comments. |
5 | https://www.armbian.com/orange-pi-pc/ | 5 | |
6 | 6 | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> | |
7 | The SD image is from the kernelci.org project: | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | https://kernelci.org/faq/#the-code | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | 9 | Message-id: 20230612223456.33824-3-philmd@linaro.org | |
10 | If ARM is a target being built, "make check-acceptance" will | 10 | Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> |
11 | automatically include this test by the use of the "arch:arm" tags. | 11 | [PMD: Split from bigger patch: 2/4] |
12 | 12 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
13 | Alternatively, this test can be run using: | ||
14 | |||
15 | $ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py | ||
16 | console: Uncompressing Linux... done, booting the kernel. | ||
17 | console: Booting Linux on physical CPU 0x0 | ||
18 | console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 | ||
19 | console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d | ||
20 | [...] | ||
21 | console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0) | ||
22 | console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2 | ||
23 | console: sunxi-mmc 1c0f000.mmc: Got CD GPIO | ||
24 | console: ledtrig-cpu: registered to indicate activity on CPUs | ||
25 | console: hidraw: raw HID events driver (C) Jiri Kosina | ||
26 | console: usbcore: registered new interface driver usbhid | ||
27 | console: usbhid: USB HID core driver | ||
28 | console: Initializing XFRM netlink socket | ||
29 | console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB | ||
30 | console: NET: Registered protocol family 10 | ||
31 | console: mmc0: host does not support reading read-only switch, assuming write-enable | ||
32 | console: mmc0: Problem switching card into high-speed mode! | ||
33 | console: mmc0: new SD card at address 4567 | ||
34 | console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB | ||
35 | [...] | ||
36 | console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem | ||
37 | console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null) | ||
38 | console: VFS: Mounted root (ext2 filesystem) on device 179:0. | ||
39 | console: Run /sbin/init as init process | ||
40 | console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl | ||
41 | console: Starting syslogd: OK | ||
42 | console: Starting klogd: OK | ||
43 | console: Populating /dev using udev: udevd[203]: starting version 3.2.7 | ||
44 | console: /bin/sh: can't access tty; job control turned off | ||
45 | console: cat /proc/partitions | ||
46 | console: / # cat /proc/partitions | ||
47 | console: major minor #blocks name | ||
48 | console: 1 0 4096 ram0 | ||
49 | console: 1 1 4096 ram1 | ||
50 | console: 1 2 4096 ram2 | ||
51 | console: 1 3 4096 ram3 | ||
52 | console: 179 0 61440 mmcblk0 | ||
53 | console: reboot | ||
54 | console: / # reboot | ||
55 | console: umount: devtmpfs busy - remounted read-only | ||
56 | console: EXT4-fs (mmcblk0): re-mounted. Opts: (null) | ||
57 | console: The system is going down NOW! | ||
58 | console: Sent SIGTERM to all processes | ||
59 | console: Sent SIGKILL to all processes | ||
60 | console: Requesting system reboot | ||
61 | console: reboot: Restarting system | ||
62 | JOB TIME : 68.64 s | ||
63 | |||
64 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
65 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
66 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
67 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
68 | Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com | ||
69 | [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] | ||
70 | [NL: extend test with ethernet device checks] | ||
71 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
72 | --- | 14 | --- |
73 | tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++ | 15 | hw/misc/bcm2835_property.c | 101 +++++++++++++++++++------------------ |
74 | 1 file changed, 47 insertions(+) | 16 | 1 file changed, 51 insertions(+), 50 deletions(-) |
75 | 17 | ||
76 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | 18 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c |
77 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
78 | --- a/tests/acceptance/boot_linux_console.py | 20 | --- a/hw/misc/bcm2835_property.c |
79 | +++ b/tests/acceptance/boot_linux_console.py | 21 | +++ b/hw/misc/bcm2835_property.c |
80 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | 22 | @@ -XXX,XX +XXX,XX @@ |
81 | exec_command_and_wait_for_pattern(self, 'reboot', | 23 | #include "migration/vmstate.h" |
82 | 'reboot: Restarting system') | 24 | #include "hw/irq.h" |
83 | 25 | #include "hw/misc/bcm2835_mbox_defs.h" | |
84 | + def test_arm_orangepi_sd(self): | 26 | +#include "hw/misc/raspberrypi-fw-defs.h" |
85 | + """ | 27 | #include "sysemu/dma.h" |
86 | + :avocado: tags=arch:arm | 28 | #include "qemu/log.h" |
87 | + :avocado: tags=machine:orangepi-pc | 29 | #include "qemu/module.h" |
88 | + """ | 30 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) |
89 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | 31 | /* @(value + 8) : Request/response indicator */ |
90 | + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') | 32 | resplen = 0; |
91 | + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' | 33 | switch (tag) { |
92 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | 34 | - case 0x00000000: /* End tag */ |
93 | + kernel_path = self.extract_from_deb(deb_path, | 35 | + case RPI_FWREQ_PROPERTY_END: |
94 | + '/boot/vmlinuz-4.20.7-sunxi') | 36 | break; |
95 | + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' | 37 | - case 0x00000001: /* Get firmware revision */ |
96 | + dtb_path = self.extract_from_deb(deb_path, dtb_path) | 38 | + case RPI_FWREQ_GET_FIRMWARE_REVISION: |
97 | + rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' | 39 | stl_le_phys(&s->dma_as, value + 12, 346337); |
98 | + 'kci-2019.02/armel/base/rootfs.ext2.xz') | 40 | resplen = 4; |
99 | + rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061' | 41 | break; |
100 | + rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash) | 42 | - case 0x00010001: /* Get board model */ |
101 | + rootfs_path = os.path.join(self.workdir, 'rootfs.cpio') | 43 | + case RPI_FWREQ_GET_BOARD_MODEL: |
102 | + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) | 44 | qemu_log_mask(LOG_UNIMP, |
103 | + | 45 | "bcm2835_property: 0x%08x get board model NYI\n", |
104 | + self.vm.set_console() | 46 | tag); |
105 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | 47 | resplen = 4; |
106 | + 'console=ttyS0,115200 ' | 48 | break; |
107 | + 'root=/dev/mmcblk0 rootwait rw ' | 49 | - case 0x00010002: /* Get board revision */ |
108 | + 'panic=-1 noreboot') | 50 | + case RPI_FWREQ_GET_BOARD_REVISION: |
109 | + self.vm.add_args('-kernel', kernel_path, | 51 | stl_le_phys(&s->dma_as, value + 12, s->board_rev); |
110 | + '-dtb', dtb_path, | 52 | resplen = 4; |
111 | + '-drive', 'file=' + rootfs_path + ',if=sd,format=raw', | 53 | break; |
112 | + '-append', kernel_command_line, | 54 | - case 0x00010003: /* Get board MAC address */ |
113 | + '-no-reboot') | 55 | + case RPI_FWREQ_GET_BOARD_MAC_ADDRESS: |
114 | + self.vm.launch() | 56 | resplen = sizeof(s->macaddr.a); |
115 | + shell_ready = "/bin/sh: can't access tty; job control turned off" | 57 | dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen, |
116 | + self.wait_for_console_pattern(shell_ready) | 58 | MEMTXATTRS_UNSPECIFIED); |
117 | + | 59 | break; |
118 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | 60 | - case 0x00010004: /* Get board serial */ |
119 | + 'Allwinner sun8i Family') | 61 | + case RPI_FWREQ_GET_BOARD_SERIAL: |
120 | + exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', | 62 | qemu_log_mask(LOG_UNIMP, |
121 | + 'mmcblk0') | 63 | "bcm2835_property: 0x%08x get board serial NYI\n", |
122 | + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up', | 64 | tag); |
123 | + 'eth0: Link is Up') | 65 | resplen = 8; |
124 | + exec_command_and_wait_for_pattern(self, 'udhcpc eth0', | 66 | break; |
125 | + 'udhcpc: lease of 10.0.2.15 obtained') | 67 | - case 0x00010005: /* Get ARM memory */ |
126 | + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2', | 68 | + case RPI_FWREQ_GET_ARM_MEMORY: |
127 | + '3 packets transmitted, 3 packets received, 0% packet loss') | 69 | /* base */ |
128 | + exec_command_and_wait_for_pattern(self, 'reboot', | 70 | stl_le_phys(&s->dma_as, value + 12, 0); |
129 | + 'reboot: Restarting system') | 71 | /* size */ |
130 | + | 72 | stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_base); |
131 | def test_s390x_s390_ccw_virtio(self): | 73 | resplen = 8; |
132 | """ | 74 | break; |
133 | :avocado: tags=arch:s390x | 75 | - case 0x00010006: /* Get VC memory */ |
76 | + case RPI_FWREQ_GET_VC_MEMORY: | ||
77 | /* base */ | ||
78 | stl_le_phys(&s->dma_as, value + 12, s->fbdev->vcram_base); | ||
79 | /* size */ | ||
80 | stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_size); | ||
81 | resplen = 8; | ||
82 | break; | ||
83 | - case 0x00028001: /* Set power state */ | ||
84 | + case RPI_FWREQ_SET_POWER_STATE: | ||
85 | /* Assume that whatever device they asked for exists, | ||
86 | * and we'll just claim we set it to the desired state | ||
87 | */ | ||
88 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
89 | |||
90 | /* Clocks */ | ||
91 | |||
92 | - case 0x00030001: /* Get clock state */ | ||
93 | + case RPI_FWREQ_GET_CLOCK_STATE: | ||
94 | stl_le_phys(&s->dma_as, value + 16, 0x1); | ||
95 | resplen = 8; | ||
96 | break; | ||
97 | |||
98 | - case 0x00038001: /* Set clock state */ | ||
99 | + case RPI_FWREQ_SET_CLOCK_STATE: | ||
100 | qemu_log_mask(LOG_UNIMP, | ||
101 | "bcm2835_property: 0x%08x set clock state NYI\n", | ||
102 | tag); | ||
103 | resplen = 8; | ||
104 | break; | ||
105 | |||
106 | - case 0x00030002: /* Get clock rate */ | ||
107 | - case 0x00030004: /* Get max clock rate */ | ||
108 | - case 0x00030007: /* Get min clock rate */ | ||
109 | + case RPI_FWREQ_GET_CLOCK_RATE: | ||
110 | + case RPI_FWREQ_GET_MAX_CLOCK_RATE: | ||
111 | + case RPI_FWREQ_GET_MIN_CLOCK_RATE: | ||
112 | switch (ldl_le_phys(&s->dma_as, value + 12)) { | ||
113 | - case 1: /* EMMC */ | ||
114 | + case RPI_FIRMWARE_EMMC_CLK_ID: | ||
115 | stl_le_phys(&s->dma_as, value + 16, 50000000); | ||
116 | break; | ||
117 | - case 2: /* UART */ | ||
118 | + case RPI_FIRMWARE_UART_CLK_ID: | ||
119 | stl_le_phys(&s->dma_as, value + 16, 3000000); | ||
120 | break; | ||
121 | default: | ||
122 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
123 | resplen = 8; | ||
124 | break; | ||
125 | |||
126 | - case 0x00038002: /* Set clock rate */ | ||
127 | - case 0x00038004: /* Set max clock rate */ | ||
128 | - case 0x00038007: /* Set min clock rate */ | ||
129 | + case RPI_FWREQ_SET_CLOCK_RATE: | ||
130 | + case RPI_FWREQ_SET_MAX_CLOCK_RATE: | ||
131 | + case RPI_FWREQ_SET_MIN_CLOCK_RATE: | ||
132 | qemu_log_mask(LOG_UNIMP, | ||
133 | "bcm2835_property: 0x%08x set clock rate NYI\n", | ||
134 | tag); | ||
135 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
136 | |||
137 | /* Temperature */ | ||
138 | |||
139 | - case 0x00030006: /* Get temperature */ | ||
140 | + case RPI_FWREQ_GET_TEMPERATURE: | ||
141 | stl_le_phys(&s->dma_as, value + 16, 25000); | ||
142 | resplen = 8; | ||
143 | break; | ||
144 | |||
145 | - case 0x0003000A: /* Get max temperature */ | ||
146 | + case RPI_FWREQ_GET_MAX_TEMPERATURE: | ||
147 | stl_le_phys(&s->dma_as, value + 16, 99000); | ||
148 | resplen = 8; | ||
149 | break; | ||
150 | |||
151 | /* Frame buffer */ | ||
152 | |||
153 | - case 0x00040001: /* Allocate buffer */ | ||
154 | + case RPI_FWREQ_FRAMEBUFFER_ALLOCATE: | ||
155 | stl_le_phys(&s->dma_as, value + 12, fbconfig.base); | ||
156 | stl_le_phys(&s->dma_as, value + 16, | ||
157 | bcm2835_fb_get_size(&fbconfig)); | ||
158 | resplen = 8; | ||
159 | break; | ||
160 | - case 0x00048001: /* Release buffer */ | ||
161 | + case RPI_FWREQ_FRAMEBUFFER_RELEASE: | ||
162 | resplen = 0; | ||
163 | break; | ||
164 | - case 0x00040002: /* Blank screen */ | ||
165 | + case RPI_FWREQ_FRAMEBUFFER_BLANK: | ||
166 | resplen = 4; | ||
167 | break; | ||
168 | - case 0x00044003: /* Test physical display width/height */ | ||
169 | - case 0x00044004: /* Test virtual display width/height */ | ||
170 | + case RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT: | ||
171 | + case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT: | ||
172 | resplen = 8; | ||
173 | break; | ||
174 | - case 0x00048003: /* Set physical display width/height */ | ||
175 | + case RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT: | ||
176 | fbconfig.xres = ldl_le_phys(&s->dma_as, value + 12); | ||
177 | fbconfig.yres = ldl_le_phys(&s->dma_as, value + 16); | ||
178 | bcm2835_fb_validate_config(&fbconfig); | ||
179 | fbconfig_updated = true; | ||
180 | /* fall through */ | ||
181 | - case 0x00040003: /* Get physical display width/height */ | ||
182 | + case RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT: | ||
183 | stl_le_phys(&s->dma_as, value + 12, fbconfig.xres); | ||
184 | stl_le_phys(&s->dma_as, value + 16, fbconfig.yres); | ||
185 | resplen = 8; | ||
186 | break; | ||
187 | - case 0x00048004: /* Set virtual display width/height */ | ||
188 | + case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT: | ||
189 | fbconfig.xres_virtual = ldl_le_phys(&s->dma_as, value + 12); | ||
190 | fbconfig.yres_virtual = ldl_le_phys(&s->dma_as, value + 16); | ||
191 | bcm2835_fb_validate_config(&fbconfig); | ||
192 | fbconfig_updated = true; | ||
193 | /* fall through */ | ||
194 | - case 0x00040004: /* Get virtual display width/height */ | ||
195 | + case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT: | ||
196 | stl_le_phys(&s->dma_as, value + 12, fbconfig.xres_virtual); | ||
197 | stl_le_phys(&s->dma_as, value + 16, fbconfig.yres_virtual); | ||
198 | resplen = 8; | ||
199 | break; | ||
200 | - case 0x00044005: /* Test depth */ | ||
201 | + case RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH: | ||
202 | resplen = 4; | ||
203 | break; | ||
204 | - case 0x00048005: /* Set depth */ | ||
205 | + case RPI_FWREQ_FRAMEBUFFER_SET_DEPTH: | ||
206 | fbconfig.bpp = ldl_le_phys(&s->dma_as, value + 12); | ||
207 | bcm2835_fb_validate_config(&fbconfig); | ||
208 | fbconfig_updated = true; | ||
209 | /* fall through */ | ||
210 | - case 0x00040005: /* Get depth */ | ||
211 | + case RPI_FWREQ_FRAMEBUFFER_GET_DEPTH: | ||
212 | stl_le_phys(&s->dma_as, value + 12, fbconfig.bpp); | ||
213 | resplen = 4; | ||
214 | break; | ||
215 | - case 0x00044006: /* Test pixel order */ | ||
216 | + case RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER: | ||
217 | resplen = 4; | ||
218 | break; | ||
219 | - case 0x00048006: /* Set pixel order */ | ||
220 | + case RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER: | ||
221 | fbconfig.pixo = ldl_le_phys(&s->dma_as, value + 12); | ||
222 | bcm2835_fb_validate_config(&fbconfig); | ||
223 | fbconfig_updated = true; | ||
224 | /* fall through */ | ||
225 | - case 0x00040006: /* Get pixel order */ | ||
226 | + case RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER: | ||
227 | stl_le_phys(&s->dma_as, value + 12, fbconfig.pixo); | ||
228 | resplen = 4; | ||
229 | break; | ||
230 | - case 0x00044007: /* Test pixel alpha */ | ||
231 | + case RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE: | ||
232 | resplen = 4; | ||
233 | break; | ||
234 | - case 0x00048007: /* Set alpha */ | ||
235 | + case RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE: | ||
236 | fbconfig.alpha = ldl_le_phys(&s->dma_as, value + 12); | ||
237 | bcm2835_fb_validate_config(&fbconfig); | ||
238 | fbconfig_updated = true; | ||
239 | /* fall through */ | ||
240 | - case 0x00040007: /* Get alpha */ | ||
241 | + case RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE: | ||
242 | stl_le_phys(&s->dma_as, value + 12, fbconfig.alpha); | ||
243 | resplen = 4; | ||
244 | break; | ||
245 | - case 0x00040008: /* Get pitch */ | ||
246 | + case RPI_FWREQ_FRAMEBUFFER_GET_PITCH: | ||
247 | stl_le_phys(&s->dma_as, value + 12, | ||
248 | bcm2835_fb_get_pitch(&fbconfig)); | ||
249 | resplen = 4; | ||
250 | break; | ||
251 | - case 0x00044009: /* Test virtual offset */ | ||
252 | + case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET: | ||
253 | resplen = 8; | ||
254 | break; | ||
255 | - case 0x00048009: /* Set virtual offset */ | ||
256 | + case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET: | ||
257 | fbconfig.xoffset = ldl_le_phys(&s->dma_as, value + 12); | ||
258 | fbconfig.yoffset = ldl_le_phys(&s->dma_as, value + 16); | ||
259 | bcm2835_fb_validate_config(&fbconfig); | ||
260 | fbconfig_updated = true; | ||
261 | /* fall through */ | ||
262 | - case 0x00040009: /* Get virtual offset */ | ||
263 | + case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET: | ||
264 | stl_le_phys(&s->dma_as, value + 12, fbconfig.xoffset); | ||
265 | stl_le_phys(&s->dma_as, value + 16, fbconfig.yoffset); | ||
266 | resplen = 8; | ||
267 | break; | ||
268 | - case 0x0004000a: /* Get/Test/Set overscan */ | ||
269 | - case 0x0004400a: | ||
270 | - case 0x0004800a: | ||
271 | + case RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN: | ||
272 | + case RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN: | ||
273 | + case RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN: | ||
274 | stl_le_phys(&s->dma_as, value + 12, 0); | ||
275 | stl_le_phys(&s->dma_as, value + 16, 0); | ||
276 | stl_le_phys(&s->dma_as, value + 20, 0); | ||
277 | stl_le_phys(&s->dma_as, value + 24, 0); | ||
278 | resplen = 16; | ||
279 | break; | ||
280 | - case 0x0004800b: /* Set palette */ | ||
281 | + case RPI_FWREQ_FRAMEBUFFER_SET_PALETTE: | ||
282 | offset = ldl_le_phys(&s->dma_as, value + 12); | ||
283 | length = ldl_le_phys(&s->dma_as, value + 16); | ||
284 | n = 0; | ||
285 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
286 | stl_le_phys(&s->dma_as, value + 12, 0); | ||
287 | resplen = 4; | ||
288 | break; | ||
289 | - case 0x00040013: /* Get number of displays */ | ||
290 | + case RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS: | ||
291 | stl_le_phys(&s->dma_as, value + 12, 1); | ||
292 | resplen = 4; | ||
293 | break; | ||
294 | |||
295 | - case 0x00060001: /* Get DMA channels */ | ||
296 | + case RPI_FWREQ_GET_DMA_CHANNELS: | ||
297 | /* channels 2-5 */ | ||
298 | stl_le_phys(&s->dma_as, value + 12, 0x003C); | ||
299 | resplen = 4; | ||
300 | break; | ||
301 | |||
302 | - case 0x00050001: /* Get command line */ | ||
303 | + case RPI_FWREQ_GET_COMMAND_LINE: | ||
304 | /* | ||
305 | * We follow the firmware behaviour: no NUL terminator is | ||
306 | * written to the buffer, and if the buffer is too short | ||
134 | -- | 307 | -- |
135 | 2.20.1 | 308 | 2.34.1 |
136 | 309 | ||
137 | 310 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Sergey Kambalin <sergey.kambalin@auriga.com> |
---|---|---|---|
2 | 2 | ||
3 | This test boots a Linux kernel on a OrangePi PC board and verify | 3 | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> |
4 | the serial output is working. | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
6 | The kernel image and DeviceTree blob are built by the Armbian | 6 | Message-id: 20230612223456.33824-4-philmd@linaro.org |
7 | project (based on Debian): | 7 | Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> |
8 | https://www.armbian.com/orange-pi-pc/ | 8 | [PMD: Split from bigger patch: 4/4] |
9 | 9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
10 | The cpio image used comes from the linux-build-test project: | ||
11 | https://github.com/groeck/linux-build-test | ||
12 | |||
13 | If ARM is a target being built, "make check-acceptance" will | ||
14 | automatically include this test by the use of the "arch:arm" tags. | ||
15 | |||
16 | Alternatively, this test can be run using: | ||
17 | |||
18 | $ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py | ||
19 | console: Uncompressing Linux... done, booting the kernel. | ||
20 | console: Booting Linux on physical CPU 0x0 | ||
21 | console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 | ||
22 | console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d | ||
23 | console: CPU: div instructions available: patching division code | ||
24 | console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
25 | console: OF: fdt: Machine model: Xunlong Orange Pi PC | ||
26 | [...] | ||
27 | console: Trying to unpack rootfs image as initramfs... | ||
28 | console: Freeing initrd memory: 3256K | ||
29 | console: Freeing unused kernel memory: 1024K | ||
30 | console: Run /init as init process | ||
31 | console: mount: mounting devtmpfs on /dev failed: Device or resource busy | ||
32 | console: Starting logging: OK | ||
33 | console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read) | ||
34 | console: done. | ||
35 | console: Starting network: OK | ||
36 | console: Found console ttyS0 | ||
37 | console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 | ||
38 | console: Boot successful. | ||
39 | console: cat /proc/cpuinfo | ||
40 | console: / # cat /proc/cpuinfo | ||
41 | console: processor : 0 | ||
42 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
43 | console: BogoMIPS : 125.00 | ||
44 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
45 | console: CPU implementer : 0x41 | ||
46 | console: CPU architecture: 7 | ||
47 | console: CPU variant : 0x0 | ||
48 | console: CPU part : 0xc07 | ||
49 | console: CPU revision : 5 | ||
50 | [...] | ||
51 | console: processor : 3 | ||
52 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
53 | console: BogoMIPS : 125.00 | ||
54 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
55 | console: CPU implementer : 0x41 | ||
56 | console: CPU architecture: 7 | ||
57 | console: CPU variant : 0x0 | ||
58 | console: CPU part : 0xc07 | ||
59 | console: CPU revision : 5 | ||
60 | console: Hardware : Allwinner sun8i Family | ||
61 | console: Revision : 0000 | ||
62 | console: Serial : 0000000000000000 | ||
63 | console: cat /proc/iomem | ||
64 | console: / # cat /proc/iomem | ||
65 | console: 01000000-010fffff : clock@1000000 | ||
66 | console: 01c00000-01c00fff : system-control@1c00000 | ||
67 | console: 01c02000-01c02fff : dma-controller@1c02000 | ||
68 | [...] | ||
69 | console: reboot | ||
70 | console: / # reboot | ||
71 | console: / # Found console ttyS0 | ||
72 | console: Stopping network: OK | ||
73 | console: hrtimer: interrupt took 21852064 ns | ||
74 | console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read) | ||
75 | console: done. | ||
76 | console: Stopping logging: OK | ||
77 | console: umount: devtmpfs busy - remounted read-only | ||
78 | console: umount: can't unmount /: Invalid argument | ||
79 | console: The system is going down NOW! | ||
80 | console: Sent SIGTERM to all processes | ||
81 | console: Sent SIGKILL to all processes | ||
82 | console: Requesting system reboot | ||
83 | console: reboot: Restarting system | ||
84 | PASS (48.32 s) | ||
85 | JOB TIME : 49.16 s | ||
86 | |||
87 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
88 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
89 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
90 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
91 | Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com | ||
92 | [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] | ||
93 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
94 | --- | 11 | --- |
95 | tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++ | 12 | include/hw/arm/raspi_platform.h | 5 +++++ |
96 | 1 file changed, 40 insertions(+) | 13 | hw/misc/bcm2835_property.c | 8 +++++--- |
14 | 2 files changed, 10 insertions(+), 3 deletions(-) | ||
97 | 15 | ||
98 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | 16 | diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h |
99 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
100 | --- a/tests/acceptance/boot_linux_console.py | 18 | --- a/include/hw/arm/raspi_platform.h |
101 | +++ b/tests/acceptance/boot_linux_console.py | 19 | +++ b/include/hw/arm/raspi_platform.h |
102 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | 20 | @@ -XXX,XX +XXX,XX @@ |
103 | console_pattern = 'Kernel command line: %s' % kernel_command_line | 21 | #define INTERRUPT_ILLEGAL_TYPE0 6 |
104 | self.wait_for_console_pattern(console_pattern) | 22 | #define INTERRUPT_ILLEGAL_TYPE1 7 |
105 | 23 | ||
106 | + def test_arm_orangepi_initrd(self): | 24 | +/* Clock rates */ |
107 | + """ | 25 | +#define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 |
108 | + :avocado: tags=arch:arm | 26 | +#define RPI_FIRMWARE_UART_CLK_RATE 3000000 |
109 | + :avocado: tags=machine:orangepi-pc | 27 | +#define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 |
110 | + """ | ||
111 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
112 | + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') | ||
113 | + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' | ||
114 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
115 | + kernel_path = self.extract_from_deb(deb_path, | ||
116 | + '/boot/vmlinuz-4.20.7-sunxi') | ||
117 | + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
118 | + dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
119 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
120 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
121 | + 'arm/rootfs-armv7a.cpio.gz') | ||
122 | + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' | ||
123 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) | ||
124 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') | ||
125 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) | ||
126 | + | 28 | + |
127 | + self.vm.set_console() | 29 | #endif |
128 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | 30 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c |
129 | + 'console=ttyS0,115200 ' | 31 | index XXXXXXX..XXXXXXX 100644 |
130 | + 'panic=-1 noreboot') | 32 | --- a/hw/misc/bcm2835_property.c |
131 | + self.vm.add_args('-kernel', kernel_path, | 33 | +++ b/hw/misc/bcm2835_property.c |
132 | + '-dtb', dtb_path, | 34 | @@ -XXX,XX +XXX,XX @@ |
133 | + '-initrd', initrd_path, | 35 | #include "qemu/log.h" |
134 | + '-append', kernel_command_line, | 36 | #include "qemu/module.h" |
135 | + '-no-reboot') | 37 | #include "trace.h" |
136 | + self.vm.launch() | 38 | +#include "hw/arm/raspi_platform.h" |
137 | + self.wait_for_console_pattern('Boot successful.') | 39 | |
138 | + | 40 | /* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */ |
139 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | 41 | |
140 | + 'Allwinner sun8i Family') | 42 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) |
141 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | 43 | case RPI_FWREQ_GET_MIN_CLOCK_RATE: |
142 | + 'system-control@1c00000') | 44 | switch (ldl_le_phys(&s->dma_as, value + 12)) { |
143 | + exec_command_and_wait_for_pattern(self, 'reboot', | 45 | case RPI_FIRMWARE_EMMC_CLK_ID: |
144 | + 'reboot: Restarting system') | 46 | - stl_le_phys(&s->dma_as, value + 16, 50000000); |
145 | + | 47 | + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_EMMC_CLK_RATE); |
146 | def test_s390x_s390_ccw_virtio(self): | 48 | break; |
147 | """ | 49 | case RPI_FIRMWARE_UART_CLK_ID: |
148 | :avocado: tags=arch:s390x | 50 | - stl_le_phys(&s->dma_as, value + 16, 3000000); |
51 | + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE); | ||
52 | break; | ||
53 | default: | ||
54 | - stl_le_phys(&s->dma_as, value + 16, 700000000); | ||
55 | + stl_le_phys(&s->dma_as, value + 16, | ||
56 | + RPI_FIRMWARE_DEFAULT_CLK_RATE); | ||
57 | break; | ||
58 | } | ||
59 | resplen = 8; | ||
149 | -- | 60 | -- |
150 | 2.20.1 | 61 | 2.34.1 |
151 | 62 | ||
152 | 63 | diff view generated by jsdifflib |
1 | From: Igor Mammedov <imammedo@redhat.com> | 1 | From: Sergey Kambalin <sergey.kambalin@auriga.com> |
---|---|---|---|
2 | 2 | ||
3 | SOC object returned by object_new() is leaked in current code. | 3 | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> |
4 | Set SOC parent explicitly to board and then unref to SOC object | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | to make sure that refererence returned by object_new() is taken | 5 | Message-id: 20230612223456.33824-5-philmd@linaro.org |
6 | care of. | 6 | Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> |
7 | 7 | [PMD: Split from bigger patch: 3/4] | |
8 | The SOC object will be kept alive by its parent (machine) and | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | will be automatically freed when MachineState is destroyed. | 9 | [PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE |
10 | 10 | really being SoC-specific] | |
11 | Signed-off-by: Igor Mammedov <imammedo@redhat.com> | ||
12 | Reported-by: Andrew Jones <drjones@redhat.com> | ||
13 | Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
14 | Message-id: 20200303091254.22373-1-imammedo@redhat.com | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 13 | --- |
18 | hw/arm/cubieboard.c | 3 +++ | 14 | include/hw/arm/raspi_platform.h | 5 +++++ |
19 | 1 file changed, 3 insertions(+) | 15 | hw/misc/bcm2835_property.c | 3 +++ |
16 | 2 files changed, 8 insertions(+) | ||
20 | 17 | ||
21 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 18 | diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h |
22 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/cubieboard.c | 20 | --- a/include/hw/arm/raspi_platform.h |
24 | +++ b/hw/arm/cubieboard.c | 21 | +++ b/include/hw/arm/raspi_platform.h |
25 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | 22 | @@ -XXX,XX +XXX,XX @@ |
26 | } | 23 | /* Clock rates */ |
27 | 24 | #define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 | |
28 | a10 = AW_A10(object_new(TYPE_AW_A10)); | 25 | #define RPI_FIRMWARE_UART_CLK_RATE 3000000 |
29 | + object_property_add_child(OBJECT(machine), "soc", OBJECT(a10), | 26 | +/* |
30 | + &error_abort); | 27 | + * TODO: this is really SoC-specific; we might want to |
31 | + object_unref(OBJECT(a10)); | 28 | + * set it per-SoC if it turns out any guests care. |
32 | 29 | + */ | |
33 | object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err); | 30 | +#define RPI_FIRMWARE_CORE_CLK_RATE 350000000 |
34 | if (err != NULL) { | 31 | #define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 |
32 | |||
33 | #endif | ||
34 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/misc/bcm2835_property.c | ||
37 | +++ b/hw/misc/bcm2835_property.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) | ||
39 | case RPI_FIRMWARE_UART_CLK_ID: | ||
40 | stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE); | ||
41 | break; | ||
42 | + case RPI_FIRMWARE_CORE_CLK_ID: | ||
43 | + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_RATE); | ||
44 | + break; | ||
45 | default: | ||
46 | stl_le_phys(&s->dma_as, value + 16, | ||
47 | RPI_FIRMWARE_DEFAULT_CLK_RATE); | ||
35 | -- | 48 | -- |
36 | 2.20.1 | 49 | 2.34.1 |
37 | 50 | ||
38 | 51 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
2 | 1 | ||
3 | The Xunlong Orange Pi PC is an Allwinner H3 System on Chip | ||
4 | based embedded computer with mainline support in both U-Boot | ||
5 | and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, | ||
6 | 1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and | ||
7 | various other I/O. This commit add support for the Xunlong | ||
8 | Orange Pi PC machine. | ||
9 | |||
10 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
11 | Tested-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
12 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
14 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
15 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
16 | Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | hw/arm/Makefile.objs | 2 +- | ||
20 | hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ | ||
21 | MAINTAINERS | 1 + | ||
22 | 3 files changed, 94 insertions(+), 1 deletion(-) | ||
23 | create mode 100644 hw/arm/orangepi.c | ||
24 | |||
25 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/hw/arm/Makefile.objs | ||
28 | +++ b/hw/arm/Makefile.objs | ||
29 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o | ||
30 | obj-$(CONFIG_OMAP) += omap1.o omap2.o | ||
31 | obj-$(CONFIG_STRONGARM) += strongarm.o | ||
32 | obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o | ||
33 | -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o | ||
34 | +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o | ||
35 | obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o | ||
36 | obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o | ||
37 | obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o | ||
38 | diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c | ||
39 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | ||
41 | --- /dev/null | ||
42 | +++ b/hw/arm/orangepi.c | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +/* | ||
45 | + * Orange Pi emulation | ||
46 | + * | ||
47 | + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | ||
48 | + * | ||
49 | + * This program is free software: you can redistribute it and/or modify | ||
50 | + * it under the terms of the GNU General Public License as published by | ||
51 | + * the Free Software Foundation, either version 2 of the License, or | ||
52 | + * (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
61 | + */ | ||
62 | + | ||
63 | +#include "qemu/osdep.h" | ||
64 | +#include "qemu/units.h" | ||
65 | +#include "exec/address-spaces.h" | ||
66 | +#include "qapi/error.h" | ||
67 | +#include "cpu.h" | ||
68 | +#include "hw/sysbus.h" | ||
69 | +#include "hw/boards.h" | ||
70 | +#include "hw/qdev-properties.h" | ||
71 | +#include "hw/arm/allwinner-h3.h" | ||
72 | +#include "sysemu/sysemu.h" | ||
73 | + | ||
74 | +static struct arm_boot_info orangepi_binfo = { | ||
75 | + .nb_cpus = AW_H3_NUM_CPUS, | ||
76 | +}; | ||
77 | + | ||
78 | +static void orangepi_init(MachineState *machine) | ||
79 | +{ | ||
80 | + AwH3State *h3; | ||
81 | + | ||
82 | + /* BIOS is not supported by this board */ | ||
83 | + if (bios_name) { | ||
84 | + error_report("BIOS not supported for this machine"); | ||
85 | + exit(1); | ||
86 | + } | ||
87 | + | ||
88 | + /* This board has fixed size RAM */ | ||
89 | + if (machine->ram_size != 1 * GiB) { | ||
90 | + error_report("This machine can only be used with 1GiB of RAM"); | ||
91 | + exit(1); | ||
92 | + } | ||
93 | + | ||
94 | + /* Only allow Cortex-A7 for this board */ | ||
95 | + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { | ||
96 | + error_report("This board can only be used with cortex-a7 CPU"); | ||
97 | + exit(1); | ||
98 | + } | ||
99 | + | ||
100 | + h3 = AW_H3(object_new(TYPE_AW_H3)); | ||
101 | + object_property_add_child(OBJECT(machine), "soc", OBJECT(h3), | ||
102 | + &error_abort); | ||
103 | + object_unref(OBJECT(h3)); | ||
104 | + | ||
105 | + /* Setup timer properties */ | ||
106 | + object_property_set_int(OBJECT(h3), 32768, "clk0-freq", | ||
107 | + &error_abort); | ||
108 | + object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq", | ||
109 | + &error_abort); | ||
110 | + | ||
111 | + /* Mark H3 object realized */ | ||
112 | + object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); | ||
113 | + | ||
114 | + /* SDRAM */ | ||
115 | + memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], | ||
116 | + machine->ram); | ||
117 | + | ||
118 | + orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM]; | ||
119 | + orangepi_binfo.ram_size = machine->ram_size; | ||
120 | + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); | ||
121 | +} | ||
122 | + | ||
123 | +static void orangepi_machine_init(MachineClass *mc) | ||
124 | +{ | ||
125 | + mc->desc = "Orange Pi PC"; | ||
126 | + mc->init = orangepi_init; | ||
127 | + mc->min_cpus = AW_H3_NUM_CPUS; | ||
128 | + mc->max_cpus = AW_H3_NUM_CPUS; | ||
129 | + mc->default_cpus = AW_H3_NUM_CPUS; | ||
130 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); | ||
131 | + mc->default_ram_size = 1 * GiB; | ||
132 | + mc->default_ram_id = "orangepi.ram"; | ||
133 | +} | ||
134 | + | ||
135 | +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) | ||
136 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
137 | index XXXXXXX..XXXXXXX 100644 | ||
138 | --- a/MAINTAINERS | ||
139 | +++ b/MAINTAINERS | ||
140 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
141 | S: Maintained | ||
142 | F: hw/*/allwinner-h3* | ||
143 | F: include/hw/*/allwinner-h3* | ||
144 | +F: hw/arm/orangepi.c | ||
145 | |||
146 | ARM PrimeCell and CMSDK devices | ||
147 | M: Peter Maydell <peter.maydell@linaro.org> | ||
148 | -- | ||
149 | 2.20.1 | ||
150 | |||
151 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
2 | 1 | ||
3 | A real Allwinner H3 SoC contains a Boot ROM which is the | ||
4 | first code that runs right after the SoC is powered on. | ||
5 | The Boot ROM is responsible for loading user code (e.g. a bootloader) | ||
6 | from any of the supported external devices and writing the downloaded | ||
7 | code to internal SRAM. After loading the SoC begins executing the code | ||
8 | written to SRAM. | ||
9 | |||
10 | This commits adds emulation of the Boot ROM firmware setup functionality | ||
11 | by loading user code from SD card in the A1 SRAM. While the A1 SRAM is | ||
12 | 64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects | ||
13 | sizes larger than 32KiB. For reference, this behaviour is documented | ||
14 | by the Linux Sunxi project wiki at: | ||
15 | |||
16 | https://linux-sunxi.org/BROM#U-Boot_SPL_limitations | ||
17 | |||
18 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
19 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
20 | Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++ | ||
24 | hw/arm/allwinner-h3.c | 17 +++++++++++++++++ | ||
25 | hw/arm/orangepi.c | 5 +++++ | ||
26 | 3 files changed, 43 insertions(+) | ||
27 | |||
28 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/include/hw/arm/allwinner-h3.h | ||
31 | +++ b/include/hw/arm/allwinner-h3.h | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | #include "hw/sd/allwinner-sdhost.h" | ||
34 | #include "hw/net/allwinner-sun8i-emac.h" | ||
35 | #include "target/arm/cpu.h" | ||
36 | +#include "sysemu/block-backend.h" | ||
37 | |||
38 | /** | ||
39 | * Allwinner H3 device list | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { | ||
41 | MemoryRegion sram_c; | ||
42 | } AwH3State; | ||
43 | |||
44 | +/** | ||
45 | + * Emulate Boot ROM firmware setup functionality. | ||
46 | + * | ||
47 | + * A real Allwinner H3 SoC contains a Boot ROM | ||
48 | + * which is the first code that runs right after | ||
49 | + * the SoC is powered on. The Boot ROM is responsible | ||
50 | + * for loading user code (e.g. a bootloader) from any | ||
51 | + * of the supported external devices and writing the | ||
52 | + * downloaded code to internal SRAM. After loading the SoC | ||
53 | + * begins executing the code written to SRAM. | ||
54 | + * | ||
55 | + * This function emulates the Boot ROM by copying 32 KiB | ||
56 | + * of data from the given block device and writes it to | ||
57 | + * the start of the first internal SRAM memory. | ||
58 | + * | ||
59 | + * @s: Allwinner H3 state object pointer | ||
60 | + * @blk: Block backend device object pointer | ||
61 | + */ | ||
62 | +void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk); | ||
63 | + | ||
64 | #endif /* HW_ARM_ALLWINNER_H3_H */ | ||
65 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/hw/arm/allwinner-h3.c | ||
68 | +++ b/hw/arm/allwinner-h3.c | ||
69 | @@ -XXX,XX +XXX,XX @@ | ||
70 | #include "hw/char/serial.h" | ||
71 | #include "hw/misc/unimp.h" | ||
72 | #include "hw/usb/hcd-ehci.h" | ||
73 | +#include "hw/loader.h" | ||
74 | #include "sysemu/sysemu.h" | ||
75 | #include "hw/arm/allwinner-h3.h" | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ enum { | ||
78 | AW_H3_GIC_NUM_SPI = 128 | ||
79 | }; | ||
80 | |||
81 | +void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk) | ||
82 | +{ | ||
83 | + const int64_t rom_size = 32 * KiB; | ||
84 | + g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size); | ||
85 | + | ||
86 | + if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) { | ||
87 | + error_setg(&error_fatal, "%s: failed to read BlockBackend data", | ||
88 | + __func__); | ||
89 | + return; | ||
90 | + } | ||
91 | + | ||
92 | + rom_add_blob("allwinner-h3.bootrom", buffer, rom_size, | ||
93 | + rom_size, s->memmap[AW_H3_SRAM_A1], | ||
94 | + NULL, NULL, NULL, NULL, false); | ||
95 | +} | ||
96 | + | ||
97 | static void allwinner_h3_init(Object *obj) | ||
98 | { | ||
99 | AwH3State *s = AW_H3(obj); | ||
100 | diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/hw/arm/orangepi.c | ||
103 | +++ b/hw/arm/orangepi.c | ||
104 | @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) | ||
105 | memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], | ||
106 | machine->ram); | ||
107 | |||
108 | + /* Load target kernel or start using BootROM */ | ||
109 | + if (!machine->kernel_filename && blk_is_available(blk)) { | ||
110 | + /* Use Boot ROM to copy data from SD card to SRAM */ | ||
111 | + allwinner_h3_bootrom_setup(h3, blk); | ||
112 | + } | ||
113 | orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM]; | ||
114 | orangepi_binfo.ram_size = machine->ram_size; | ||
115 | arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); | ||
116 | -- | ||
117 | 2.20.1 | ||
118 | |||
119 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | This test boots a Linux kernel on a OrangePi PC board and verify | ||
4 | the serial output is working. | ||
5 | |||
6 | The kernel image and DeviceTree blob are built by the Armbian | ||
7 | project (based on Debian): | ||
8 | https://www.armbian.com/orange-pi-pc/ | ||
9 | |||
10 | If ARM is a target being built, "make check-acceptance" will | ||
11 | automatically include this test by the use of the "arch:arm" tags. | ||
12 | |||
13 | Alternatively, this test can be run using: | ||
14 | |||
15 | $ make check-venv | ||
16 | $ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py | ||
17 | JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a | ||
18 | JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log | ||
19 | (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi: | ||
20 | console: Uncompressing Linux... done, booting the kernel. | ||
21 | console: Booting Linux on physical CPU 0x0 | ||
22 | console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 | ||
23 | console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d | ||
24 | console: CPU: div instructions available: patching division code | ||
25 | console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
26 | console: OF: fdt: Machine model: Xunlong Orange Pi PC | ||
27 | console: Memory policy: Data cache writealloc | ||
28 | console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000' | ||
29 | console: cma: Failed to reserve 128 MiB | ||
30 | console: psci: probing for conduit method from DT. | ||
31 | console: psci: PSCIv0.2 detected in firmware. | ||
32 | console: psci: Using standard PSCI v0.2 function IDs | ||
33 | console: psci: Trusted OS migration not required | ||
34 | console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0 | ||
35 | console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728 | ||
36 | console: Built 1 zonelists, mobility grouping on. Total pages: 32480 | ||
37 | console: Kernel command line: printk.time=0 console=ttyS0,115200 | ||
38 | PASS (8.59 s) | ||
39 | JOB TIME : 8.81 s | ||
40 | |||
41 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
42 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
43 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
44 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
45 | Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com | ||
46 | [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] | ||
47 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
48 | --- | ||
49 | tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++ | ||
50 | 1 file changed, 25 insertions(+) | ||
51 | |||
52 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/tests/acceptance/boot_linux_console.py | ||
55 | +++ b/tests/acceptance/boot_linux_console.py | ||
56 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | ||
57 | exec_command_and_wait_for_pattern(self, 'reboot', | ||
58 | 'reboot: Restarting system') | ||
59 | |||
60 | + def test_arm_orangepi(self): | ||
61 | + """ | ||
62 | + :avocado: tags=arch:arm | ||
63 | + :avocado: tags=machine:orangepi-pc | ||
64 | + """ | ||
65 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
66 | + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') | ||
67 | + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' | ||
68 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
69 | + kernel_path = self.extract_from_deb(deb_path, | ||
70 | + '/boot/vmlinuz-4.20.7-sunxi') | ||
71 | + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
72 | + dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
73 | + | ||
74 | + self.vm.set_console() | ||
75 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | ||
76 | + 'console=ttyS0,115200n8 ' | ||
77 | + 'earlycon=uart,mmio32,0x1c28000') | ||
78 | + self.vm.add_args('-kernel', kernel_path, | ||
79 | + '-dtb', dtb_path, | ||
80 | + '-append', kernel_command_line) | ||
81 | + self.vm.launch() | ||
82 | + console_pattern = 'Kernel command line: %s' % kernel_command_line | ||
83 | + self.wait_for_console_pattern(console_pattern) | ||
84 | + | ||
85 | def test_s390x_s390_ccw_virtio(self): | ||
86 | """ | ||
87 | :avocado: tags=arch:s390x | ||
88 | -- | ||
89 | 2.20.1 | ||
90 | |||
91 | diff view generated by jsdifflib |