1
arm queue; dunno if this will be the last before softfreeze
1
Nothing too exciting in this lot :-)
2
or not, but anyway probably the last large one. New orangepi-pc
3
board model is the big item here.
4
2
5
thanks
3
The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9:
6
-- PMM
7
4
8
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
5
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request' into staging (2021-09-29 21:20:49 +0100)
9
10
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
11
6
12
are available in the Git repository at:
7
are available in the Git repository at:
13
8
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210930
15
10
16
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
11
for you to fetch changes up to 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b:
17
12
18
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
13
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 (2021-09-30 13:44:13 +0100)
19
14
20
----------------------------------------------------------------
15
----------------------------------------------------------------
21
target-arm queue:
16
target-arm queue:
22
* Fix various bugs that might result in an assert() due to
17
* allwinner-h3: Switch to SMC as PSCI conduit
23
incorrect hflags for M-profile CPUs
18
* arm: tcg: Adhere to SMCCC 1.3 section 5.2
24
* Fix Aspeed SMC Controller user-mode select handling
19
* xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices
25
* Report correct (with-tag) address in fault address register
20
* gdbstub related code cleanups
26
when TBI is enabled
21
* Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
27
* cubieboard: make sure SOC object isn't leaked
22
* Use _init vs _new convention in bus creation function names
28
* fsl-imx25: Wire up eSDHC controllers
23
* sabrelite: Connect SPI flash CS line to GPIO3_19
29
* fsl-imx25: Wire up USB controllers
30
* New board model: orangepi-pc (OrangePi PC)
31
* ARM/KVM: if user doesn't select GIC version and the
32
host kernel can only provide GICv3, use that, rather
33
than defaulting to "fail because GICv2 isn't possible"
34
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
35
24
36
----------------------------------------------------------------
25
----------------------------------------------------------------
37
Beata Michalska (1):
26
Alexander Graf (2):
38
target/arm: kvm: Inject events at the last stage of sync
27
allwinner-h3: Switch to SMC as PSCI conduit
28
arm: tcg: Adhere to SMCCC 1.3 section 5.2
39
29
40
Cédric Le Goater (2):
30
Peter Maydell (10):
41
aspeed/smc: Add some tracing
31
configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
42
aspeed/smc: Fix User mode select/unselect scheme
32
target/arm: Fix coding style issues in gdbstub code in helper.c
33
target/arm: Move gdbstub related code out of helper.c
34
target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
35
scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
36
ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
37
pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
38
qbus: Rename qbus_create_inplace() to qbus_init()
39
qbus: Rename qbus_create() to qbus_new()
40
ide: Rename ide_bus_new() to ide_bus_init()
43
41
44
Eric Auger (6):
42
Tong Ho (9):
45
hw/arm/virt: Document 'max' value in gic-version property description
43
hw/nvram: Introduce Xilinx eFuse QOM
46
hw/arm/virt: Introduce VirtGICType enum type
44
hw/nvram: Introduce Xilinx Versal eFuse device
47
hw/arm/virt: Introduce finalize_gic_version()
45
hw/nvram: Introduce Xilinx ZynqMP eFuse device
48
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
46
hw/nvram: Introduce Xilinx battery-backed ram
49
hw/arm/virt: kvm: Restructure finalize_gic_version()
47
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
50
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
48
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
49
hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
50
hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
51
docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
51
52
52
Guenter Roeck (2):
53
Xuzhou Cheng (1):
53
hw/arm/fsl-imx25: Wire up eSDHC controllers
54
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
54
hw/arm/fsl-imx25: Wire up USB controllers
55
55
56
Igor Mammedov (1):
56
docs/system/arm/xlnx-versal-virt.rst | 49 ++
57
hw/arm/cubieboard: make sure SOC object isn't leaked
57
configs/targets/aarch64-linux-user.mak | 2 +-
58
configs/targets/aarch64-softmmu.mak | 2 +-
59
configs/targets/aarch64_be-linux-user.mak | 2 +-
60
configs/targets/arm-linux-user.mak | 2 +-
61
configs/targets/arm-softmmu.mak | 2 +-
62
configs/targets/armeb-linux-user.mak | 2 +-
63
include/hw/arm/xlnx-versal.h | 15 +
64
include/hw/arm/xlnx-zynqmp.h | 5 +
65
include/hw/ide/internal.h | 4 +-
66
include/hw/ipack/ipack.h | 8 +-
67
include/hw/nvram/xlnx-bbram.h | 54 ++
68
include/hw/nvram/xlnx-efuse.h | 132 +++++
69
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
70
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
71
include/hw/pci/pci.h | 10 +-
72
include/hw/qdev-core.h | 6 +-
73
include/hw/scsi/scsi.h | 30 +-
74
target/arm/internals.h | 7 +
75
hw/arm/allwinner-h3.c | 2 +-
76
hw/arm/sabrelite.c | 2 +-
77
hw/arm/xlnx-versal-virt.c | 88 +++
78
hw/arm/xlnx-versal.c | 57 ++
79
hw/arm/xlnx-zcu102.c | 30 ++
80
hw/arm/xlnx-zynqmp.c | 49 ++
81
hw/audio/intel-hda.c | 2 +-
82
hw/block/fdc.c | 2 +-
83
hw/block/swim.c | 3 +-
84
hw/char/virtio-serial-bus.c | 4 +-
85
hw/core/bus.c | 13 +-
86
hw/core/sysbus.c | 10 +-
87
hw/gpio/bcm2835_gpio.c | 3 +-
88
hw/hyperv/vmbus.c | 2 +-
89
hw/i2c/core.c | 2 +-
90
hw/ide/ahci.c | 2 +-
91
hw/ide/cmd646.c | 2 +-
92
hw/ide/isa.c | 2 +-
93
hw/ide/macio.c | 2 +-
94
hw/ide/microdrive.c | 2 +-
95
hw/ide/mmio.c | 2 +-
96
hw/ide/piix.c | 2 +-
97
hw/ide/qdev.c | 4 +-
98
hw/ide/sii3112.c | 2 +-
99
hw/ide/via.c | 2 +-
100
hw/ipack/ipack.c | 10 +-
101
hw/ipack/tpci200.c | 4 +-
102
hw/isa/isa-bus.c | 2 +-
103
hw/misc/auxbus.c | 2 +-
104
hw/misc/mac_via.c | 4 +-
105
hw/misc/macio/cuda.c | 4 +-
106
hw/misc/macio/macio.c | 4 +-
107
hw/misc/macio/pmu.c | 4 +-
108
hw/nubus/nubus-bridge.c | 2 +-
109
hw/nvme/ctrl.c | 4 +-
110
hw/nvme/subsys.c | 3 +-
111
hw/nvram/xlnx-bbram.c | 545 +++++++++++++++++++
112
hw/nvram/xlnx-efuse-crc.c | 119 +++++
113
hw/nvram/xlnx-efuse.c | 280 ++++++++++
114
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
115
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
116
hw/nvram/xlnx-zynqmp-efuse.c | 855 ++++++++++++++++++++++++++++++
117
hw/pci-host/raven.c | 4 +-
118
hw/pci-host/versatile.c | 6 +-
119
hw/pci/pci.c | 30 +-
120
hw/pci/pci_bridge.c | 4 +-
121
hw/ppc/spapr_vio.c | 2 +-
122
hw/s390x/ap-bridge.c | 2 +-
123
hw/s390x/css-bridge.c | 2 +-
124
hw/s390x/event-facility.c | 4 +-
125
hw/s390x/s390-pci-bus.c | 2 +-
126
hw/s390x/virtio-ccw.c | 3 +-
127
hw/scsi/esp-pci.c | 2 +-
128
hw/scsi/esp.c | 2 +-
129
hw/scsi/lsi53c895a.c | 2 +-
130
hw/scsi/megasas.c | 3 +-
131
hw/scsi/mptsas.c | 2 +-
132
hw/scsi/scsi-bus.c | 6 +-
133
hw/scsi/spapr_vscsi.c | 3 +-
134
hw/scsi/virtio-scsi.c | 4 +-
135
hw/scsi/vmw_pvscsi.c | 3 +-
136
hw/sd/allwinner-sdhost.c | 4 +-
137
hw/sd/bcm2835_sdhost.c | 4 +-
138
hw/sd/pl181.c | 3 +-
139
hw/sd/pxa2xx_mmci.c | 4 +-
140
hw/sd/sdhci.c | 3 +-
141
hw/sd/ssi-sd.c | 3 +-
142
hw/ssi/ssi.c | 2 +-
143
hw/usb/bus.c | 2 +-
144
hw/usb/dev-smartcard-reader.c | 3 +-
145
hw/usb/dev-storage-bot.c | 3 +-
146
hw/usb/dev-storage-classic.c | 4 +-
147
hw/usb/dev-uas.c | 3 +-
148
hw/virtio/virtio-mmio.c | 3 +-
149
hw/virtio/virtio-pci.c | 3 +-
150
hw/xen/xen-bus.c | 2 +-
151
hw/xen/xen-legacy-backend.c | 2 +-
152
target/arm/gdbstub.c | 154 ++++++
153
target/arm/gdbstub64.c | 140 +++++
154
target/arm/helper.c | 262 ---------
155
target/arm/psci.c | 35 +-
156
gdb-xml/arm-neon.xml | 2 -
157
gdb-xml/arm-vfp-sysregs.xml | 17 +
158
gdb-xml/arm-vfp.xml | 2 -
159
gdb-xml/arm-vfp3.xml | 2 -
160
hw/Kconfig | 2 +
161
hw/arm/Kconfig | 2 +
162
hw/nvram/Kconfig | 19 +
163
hw/nvram/meson.build | 8 +
164
108 files changed, 3806 insertions(+), 447 deletions(-)
165
create mode 100644 include/hw/nvram/xlnx-bbram.h
166
create mode 100644 include/hw/nvram/xlnx-efuse.h
167
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
168
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
169
create mode 100644 hw/nvram/xlnx-bbram.c
170
create mode 100644 hw/nvram/xlnx-efuse-crc.c
171
create mode 100644 hw/nvram/xlnx-efuse.c
172
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
173
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
174
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
175
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
58
176
59
Niek Linnenbank (13):
60
hw/arm: add Allwinner H3 System-on-Chip
61
hw/arm: add Xunlong Orange Pi PC machine
62
hw/arm/allwinner-h3: add Clock Control Unit
63
hw/arm/allwinner-h3: add USB host controller
64
hw/arm/allwinner-h3: add System Control module
65
hw/arm/allwinner: add CPU Configuration module
66
hw/arm/allwinner: add Security Identifier device
67
hw/arm/allwinner: add SD/MMC host controller
68
hw/arm/allwinner-h3: add EMAC ethernet device
69
hw/arm/allwinner-h3: add Boot ROM support
70
hw/arm/allwinner-h3: add SDRAM controller device
71
hw/arm/allwinner: add RTC device support
72
docs: add Orange Pi PC document
73
74
Peter Maydell (4):
75
hw/intc/armv7m_nvic: Rebuild hflags on reset
76
target/arm: Update hflags in trans_CPS_v7m()
77
target/arm: Recalculate hflags correctly after writes to CONTROL
78
target/arm: Fix some comment typos
79
80
Philippe Mathieu-Daudé (5):
81
tests/boot_linux_console: Add a quick test for the OrangePi PC board
82
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
83
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
84
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
85
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
86
87
Richard Henderson (2):
88
target/arm: Check addresses for disabled regimes
89
target/arm: Disable clean_data_tbi for system mode
90
91
Makefile.objs | 1 +
92
hw/arm/Makefile.objs | 1 +
93
hw/misc/Makefile.objs | 5 +
94
hw/net/Makefile.objs | 1 +
95
hw/rtc/Makefile.objs | 1 +
96
hw/sd/Makefile.objs | 1 +
97
hw/usb/hcd-ehci.h | 1 +
98
include/hw/arm/allwinner-a10.h | 4 +
99
include/hw/arm/allwinner-h3.h | 161 ++++++
100
include/hw/arm/fsl-imx25.h | 18 +
101
include/hw/arm/virt.h | 12 +-
102
include/hw/misc/allwinner-cpucfg.h | 52 ++
103
include/hw/misc/allwinner-h3-ccu.h | 66 +++
104
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
105
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
106
include/hw/misc/allwinner-sid.h | 60 +++
107
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
108
include/hw/rtc/allwinner-rtc.h | 134 +++++
109
include/hw/sd/allwinner-sdhost.h | 135 +++++
110
target/arm/helper.h | 1 +
111
target/arm/kvm_arm.h | 3 +
112
hw/arm/allwinner-a10.c | 19 +
113
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
114
hw/arm/cubieboard.c | 18 +
115
hw/arm/fsl-imx25.c | 56 +++
116
hw/arm/imx25_pdk.c | 16 +
117
hw/arm/orangepi.c | 130 +++++
118
hw/arm/virt.c | 145 ++++--
119
hw/intc/armv7m_nvic.c | 6 +
120
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
121
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
122
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
123
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
124
hw/misc/allwinner-sid.c | 168 +++++++
125
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
126
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
127
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
128
hw/ssi/aspeed_smc.c | 56 ++-
129
hw/usb/hcd-ehci-sysbus.c | 17 +
130
target/arm/helper.c | 49 +-
131
target/arm/kvm.c | 14 +-
132
target/arm/kvm32.c | 15 +-
133
target/arm/kvm64.c | 15 +-
134
target/arm/translate-a64.c | 11 +
135
target/arm/translate.c | 14 +-
136
MAINTAINERS | 9 +
137
default-configs/arm-softmmu.mak | 1 +
138
docs/system/arm/orangepi.rst | 253 ++++++++++
139
docs/system/target-arm.rst | 2 +
140
hw/arm/Kconfig | 12 +
141
hw/misc/trace-events | 19 +
142
hw/net/Kconfig | 3 +
143
hw/net/trace-events | 10 +
144
hw/rtc/trace-events | 4 +
145
hw/sd/trace-events | 7 +
146
hw/ssi/trace-events | 10 +
147
tests/acceptance/boot_linux_console.py | 230 +++++++++
148
57 files changed, 5787 insertions(+), 74 deletions(-)
149
create mode 100644 include/hw/arm/allwinner-h3.h
150
create mode 100644 include/hw/misc/allwinner-cpucfg.h
151
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
152
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
153
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
154
create mode 100644 include/hw/misc/allwinner-sid.h
155
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
156
create mode 100644 include/hw/rtc/allwinner-rtc.h
157
create mode 100644 include/hw/sd/allwinner-sdhost.h
158
create mode 100644 hw/arm/allwinner-h3.c
159
create mode 100644 hw/arm/orangepi.c
160
create mode 100644 hw/misc/allwinner-cpucfg.c
161
create mode 100644 hw/misc/allwinner-h3-ccu.c
162
create mode 100644 hw/misc/allwinner-h3-dramc.c
163
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
164
create mode 100644 hw/misc/allwinner-sid.c
165
create mode 100644 hw/net/allwinner-sun8i-emac.c
166
create mode 100644 hw/rtc/allwinner-rtc.c
167
create mode 100644 hw/sd/allwinner-sdhost.c
168
create mode 100644 docs/system/arm/orangepi.rst
169
create mode 100644 hw/ssi/trace-events
170
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
A real Allwinner H3 SoC contains a Boot ROM which is the
3
The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.
4
first code that runs right after the SoC is powered on.
4
However, today we are configuring QEMU to use HVC as PSCI conduit.
5
The Boot ROM is responsible for loading user code (e.g. a bootloader)
6
from any of the supported external devices and writing the downloaded
7
code to internal SRAM. After loading the SoC begins executing the code
8
written to SRAM.
9
5
10
This commits adds emulation of the Boot ROM firmware setup functionality
6
That means HVC calls get trapped into QEMU instead of the guest's own
11
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
7
emulated CPU and thus break the guest's ability to execute virtualization.
12
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
13
sizes larger than 32KiB. For reference, this behaviour is documented
14
by the Linux Sunxi project wiki at:
15
8
16
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
9
Fix this by moving to SMC as conduit, freeing up HYP completely to the VM.
17
10
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Signed-off-by: Alexander Graf <agraf@csgraf.de>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20210920203931.66527-1-agraf@csgraf.de
20
Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com
13
Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")
14
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
19
---
23
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
20
hw/arm/allwinner-h3.c | 2 +-
24
hw/arm/allwinner-h3.c | 17 +++++++++++++++++
21
1 file changed, 1 insertion(+), 1 deletion(-)
25
hw/arm/orangepi.c | 5 +++++
26
3 files changed, 43 insertions(+)
27
22
28
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-h3.h
31
+++ b/include/hw/arm/allwinner-h3.h
32
@@ -XXX,XX +XXX,XX @@
33
#include "hw/sd/allwinner-sdhost.h"
34
#include "hw/net/allwinner-sun8i-emac.h"
35
#include "target/arm/cpu.h"
36
+#include "sysemu/block-backend.h"
37
38
/**
39
* Allwinner H3 device list
40
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
41
MemoryRegion sram_c;
42
} AwH3State;
43
44
+/**
45
+ * Emulate Boot ROM firmware setup functionality.
46
+ *
47
+ * A real Allwinner H3 SoC contains a Boot ROM
48
+ * which is the first code that runs right after
49
+ * the SoC is powered on. The Boot ROM is responsible
50
+ * for loading user code (e.g. a bootloader) from any
51
+ * of the supported external devices and writing the
52
+ * downloaded code to internal SRAM. After loading the SoC
53
+ * begins executing the code written to SRAM.
54
+ *
55
+ * This function emulates the Boot ROM by copying 32 KiB
56
+ * of data from the given block device and writes it to
57
+ * the start of the first internal SRAM memory.
58
+ *
59
+ * @s: Allwinner H3 state object pointer
60
+ * @blk: Block backend device object pointer
61
+ */
62
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
63
+
64
#endif /* HW_ARM_ALLWINNER_H3_H */
65
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
23
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
66
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/allwinner-h3.c
25
--- a/hw/arm/allwinner-h3.c
68
+++ b/hw/arm/allwinner-h3.c
26
+++ b/hw/arm/allwinner-h3.c
69
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
70
#include "hw/char/serial.h"
28
71
#include "hw/misc/unimp.h"
29
/* Provide Power State Coordination Interface */
72
#include "hw/usb/hcd-ehci.h"
30
qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
73
+#include "hw/loader.h"
31
- QEMU_PSCI_CONDUIT_HVC);
74
#include "sysemu/sysemu.h"
32
+ QEMU_PSCI_CONDUIT_SMC);
75
#include "hw/arm/allwinner-h3.h"
33
76
34
/* Disable secondary CPUs */
77
@@ -XXX,XX +XXX,XX @@ enum {
35
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
78
AW_H3_GIC_NUM_SPI = 128
79
};
80
81
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
82
+{
83
+ const int64_t rom_size = 32 * KiB;
84
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
85
+
86
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
87
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
88
+ __func__);
89
+ return;
90
+ }
91
+
92
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
93
+ rom_size, s->memmap[AW_H3_SRAM_A1],
94
+ NULL, NULL, NULL, NULL, false);
95
+}
96
+
97
static void allwinner_h3_init(Object *obj)
98
{
99
AwH3State *s = AW_H3(obj);
100
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/orangepi.c
103
+++ b/hw/arm/orangepi.c
104
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
105
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
106
machine->ram);
107
108
+ /* Load target kernel or start using BootROM */
109
+ if (!machine->kernel_filename && blk_is_available(blk)) {
110
+ /* Use Boot ROM to copy data from SD card to SRAM */
111
+ allwinner_h3_bootrom_setup(h3, blk);
112
+ }
113
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
114
orangepi_binfo.ram_size = machine->ram_size;
115
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
116
--
36
--
117
2.20.1
37
2.20.1
118
38
119
39
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
i.MX25 supports two USB controllers. Let's wire them up.
3
The SMCCC 1.3 spec section 5.2 says
4
4
5
With this patch, imx25-pdk can boot from both USB ports.
5
The Unknown SMC Function Identifier is a sign-extended value of (-1)
6
that is returned in the R0, W0 or X0 registers. An implementation must
7
return this error code when it receives:
6
8
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
* An SMC or HVC call with an unknown Function Identifier
8
Message-id: 20200310215146.19688-3-linux@roeck-us.net
10
* An SMC or HVC call for a removed Function Identifier
11
* An SMC64/HVC64 call from AArch32 state
12
13
To comply with these statements, let's always return -1 when we encounter
14
an unknown HVC or SMC call.
15
16
Signed-off-by: Alexander Graf <agraf@csgraf.de>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
19
---
12
include/hw/arm/fsl-imx25.h | 9 +++++++++
20
target/arm/psci.c | 35 ++++++-----------------------------
13
hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++
21
1 file changed, 6 insertions(+), 29 deletions(-)
14
2 files changed, 33 insertions(+)
15
22
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
23
diff --git a/target/arm/psci.c b/target/arm/psci.c
17
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
25
--- a/target/arm/psci.c
19
+++ b/include/hw/arm/fsl-imx25.h
26
+++ b/target/arm/psci.c
20
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@
21
#include "hw/i2c/imx_i2c.h"
28
22
#include "hw/gpio/imx_gpio.h"
29
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
23
#include "hw/sd/sdhci.h"
30
{
24
+#include "hw/usb/chipidea.h"
31
- /* Return true if the r0/x0 value indicates a PSCI call and
25
#include "exec/memory.h"
32
- * the exception type matches the configured PSCI conduit. This is
26
#include "target/arm/cpu.h"
33
- * called before the SMC/HVC instruction is executed, to decide whether
27
34
- * we should treat it as a PSCI call or with the architecturally
28
@@ -XXX,XX +XXX,XX @@
35
+ /*
29
#define FSL_IMX25_NUM_I2CS 3
36
+ * Return true if the exception type matches the configured PSCI conduit.
30
#define FSL_IMX25_NUM_GPIOS 4
37
+ * This is called before the SMC/HVC instruction is executed, to decide
31
#define FSL_IMX25_NUM_ESDHCS 2
38
+ * whether we should treat it as a PSCI call or with the architecturally
32
+#define FSL_IMX25_NUM_USBS 2
39
* defined behaviour for an SMC or HVC (which might be UNDEF or trap
33
40
* to EL2 or to EL3).
34
typedef struct FslIMX25State {
41
*/
35
/*< private >*/
42
- CPUARMState *env = &cpu->env;
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
43
- uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
37
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
44
38
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
45
switch (excp_type) {
39
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
46
case EXCP_HVC:
40
+ ChipideaState usb[FSL_IMX25_NUM_USBS];
47
@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
41
MemoryRegion rom[2];
48
return false;
42
MemoryRegion iram;
43
MemoryRegion iram_alias;
44
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
45
#define FSL_IMX25_GPIO1_SIZE 0x4000
46
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
47
#define FSL_IMX25_GPIO2_SIZE 0x4000
48
+#define FSL_IMX25_USB1_ADDR 0x53FF4000
49
+#define FSL_IMX25_USB1_SIZE 0x0200
50
+#define FSL_IMX25_USB2_ADDR 0x53FF4400
51
+#define FSL_IMX25_USB2_SIZE 0x0200
52
#define FSL_IMX25_AVIC_ADDR 0x68000000
53
#define FSL_IMX25_AVIC_SIZE 0x4000
54
#define FSL_IMX25_IRAM_ADDR 0x78000000
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
56
#define FSL_IMX25_GPIO4_IRQ 23
57
#define FSL_IMX25_ESDHC1_IRQ 9
58
#define FSL_IMX25_ESDHC2_IRQ 8
59
+#define FSL_IMX25_USB1_IRQ 37
60
+#define FSL_IMX25_USB2_IRQ 35
61
62
#endif /* FSL_IMX25_H */
63
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/fsl-imx25.c
66
+++ b/hw/arm/fsl-imx25.c
67
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
68
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
69
TYPE_IMX_USDHC);
70
}
49
}
71
+
50
72
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
51
- switch (param) {
73
+ sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
52
- case QEMU_PSCI_0_2_FN_PSCI_VERSION:
74
+ TYPE_CHIPIDEA);
53
- case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
75
+ }
54
- case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
76
+
55
- case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
56
- case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
57
- case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
58
- case QEMU_PSCI_0_1_FN_CPU_ON:
59
- case QEMU_PSCI_0_2_FN_CPU_ON:
60
- case QEMU_PSCI_0_2_FN64_CPU_ON:
61
- case QEMU_PSCI_0_1_FN_CPU_OFF:
62
- case QEMU_PSCI_0_2_FN_CPU_OFF:
63
- case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
64
- case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
65
- case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
66
- case QEMU_PSCI_0_1_FN_MIGRATE:
67
- case QEMU_PSCI_0_2_FN_MIGRATE:
68
- return true;
69
- default:
70
- return false;
71
- }
72
+ return true;
77
}
73
}
78
74
79
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
75
void arm_handle_psci_call(ARMCPU *cpu)
80
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
76
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
81
esdhc_table[i].irq));
77
break;
78
case QEMU_PSCI_0_1_FN_MIGRATE:
79
case QEMU_PSCI_0_2_FN_MIGRATE:
80
+ default:
81
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
82
break;
83
- default:
84
- g_assert_not_reached();
82
}
85
}
83
86
84
+ /* USB */
87
err:
85
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
86
+ static const struct {
87
+ hwaddr addr;
88
+ unsigned int irq;
89
+ } usb_table[FSL_IMX25_NUM_USBS] = {
90
+ { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
91
+ { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
92
+ };
93
+
94
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
95
+ &error_abort);
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
97
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
98
+ qdev_get_gpio_in(DEVICE(&s->avic),
99
+ usb_table[i].irq));
100
+ }
101
+
102
/* initialize 2 x 16 KB ROM */
103
memory_region_init_rom(&s->rom[0], NULL,
104
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
105
--
88
--
106
2.20.1
89
2.20.1
107
90
108
91
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
3
This introduces the QOM for Xilinx eFuse, an one-time
4
for non-volatile system date and time keeping. This commit adds a generic
4
field-programmable storage bit array.
5
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
6
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
7
The following RTC functionality and features are implemented:
8
5
9
* Year-Month-Day read/write
6
The actual mmio interface to the array varies by device
10
* Hour-Minute-Second read/write
7
families and will be provided in different change-sets.
11
* General Purpose storage
12
8
13
The following boards are extended with the RTC device:
9
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
14
11
15
* Cubieboard (hw/arm/cubieboard.c)
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
16
* Orange Pi PC (hw/arm/orangepi.c)
13
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
17
14
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
18
---
23
hw/rtc/Makefile.objs | 1 +
19
include/hw/nvram/xlnx-efuse.h | 132 ++++++++++++++++
24
include/hw/arm/allwinner-a10.h | 2 +
20
hw/nvram/xlnx-efuse-crc.c | 119 +++++++++++++++
25
include/hw/arm/allwinner-h3.h | 3 +
21
hw/nvram/xlnx-efuse.c | 280 ++++++++++++++++++++++++++++++++++
26
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
22
hw/nvram/Kconfig | 7 +
27
hw/arm/allwinner-a10.c | 8 +
23
hw/nvram/meson.build | 2 +
28
hw/arm/allwinner-h3.c | 9 +-
24
5 files changed, 540 insertions(+)
29
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
25
create mode 100644 include/hw/nvram/xlnx-efuse.h
30
hw/rtc/trace-events | 4 +
26
create mode 100644 hw/nvram/xlnx-efuse-crc.c
31
8 files changed, 571 insertions(+), 1 deletion(-)
27
create mode 100644 hw/nvram/xlnx-efuse.c
32
create mode 100644 include/hw/rtc/allwinner-rtc.h
33
create mode 100644 hw/rtc/allwinner-rtc.c
34
28
35
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
29
diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/rtc/Makefile.objs
38
+++ b/hw/rtc/Makefile.objs
39
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
40
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
41
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o
42
common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o
43
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o
44
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/arm/allwinner-a10.h
47
+++ b/include/hw/arm/allwinner-a10.h
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/ide/ahci.h"
50
#include "hw/usb/hcd-ohci.h"
51
#include "hw/usb/hcd-ehci.h"
52
+#include "hw/rtc/allwinner-rtc.h"
53
54
#include "target/arm/cpu.h"
55
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
57
AwEmacState emac;
58
AllwinnerAHCIState sata;
59
AwSdHostState mmc0;
60
+ AwRtcState rtc;
61
MemoryRegion sram_a;
62
EHCISysBusState ehci[AW_A10_NUM_USB];
63
OHCISysBusState ohci[AW_A10_NUM_USB];
64
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/include/hw/arm/allwinner-h3.h
67
+++ b/include/hw/arm/allwinner-h3.h
68
@@ -XXX,XX +XXX,XX @@
69
#include "hw/misc/allwinner-sid.h"
70
#include "hw/sd/allwinner-sdhost.h"
71
#include "hw/net/allwinner-sun8i-emac.h"
72
+#include "hw/rtc/allwinner-rtc.h"
73
#include "target/arm/cpu.h"
74
#include "sysemu/block-backend.h"
75
76
@@ -XXX,XX +XXX,XX @@ enum {
77
AW_H3_GIC_CPU,
78
AW_H3_GIC_HYP,
79
AW_H3_GIC_VCPU,
80
+ AW_H3_RTC,
81
AW_H3_CPUCFG,
82
AW_H3_SDRAM
83
};
84
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
85
AwSidState sid;
86
AwSdHostState mmc0;
87
AwSun8iEmacState emac;
88
+ AwRtcState rtc;
89
GICState gic;
90
MemoryRegion sram_a1;
91
MemoryRegion sram_a2;
92
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
93
new file mode 100644
30
new file mode 100644
94
index XXXXXXX..XXXXXXX
31
index XXXXXXX..XXXXXXX
95
--- /dev/null
32
--- /dev/null
96
+++ b/include/hw/rtc/allwinner-rtc.h
33
+++ b/include/hw/nvram/xlnx-efuse.h
97
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@
98
+/*
35
+/*
99
+ * Allwinner Real Time Clock emulation
36
+ * QEMU model of the Xilinx eFuse core
100
+ *
37
+ *
101
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
38
+ * Copyright (c) 2015 Xilinx Inc.
102
+ *
39
+ *
103
+ * This program is free software: you can redistribute it and/or modify
40
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
104
+ * it under the terms of the GNU General Public License as published by
41
+ *
105
+ * the Free Software Foundation, either version 2 of the License, or
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
106
+ * (at your option) any later version.
43
+ * of this software and associated documentation files (the "Software"), to deal
107
+ *
44
+ * in the Software without restriction, including without limitation the rights
108
+ * This program is distributed in the hope that it will be useful,
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
109
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
46
+ * copies of the Software, and to permit persons to whom the Software is
110
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47
+ * furnished to do so, subject to the following conditions:
111
+ * GNU General Public License for more details.
48
+ *
112
+ *
49
+ * The above copyright notice and this permission notice shall be included in
113
+ * You should have received a copy of the GNU General Public License
50
+ * all copies or substantial portions of the Software.
114
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
51
+ *
115
+ */
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
116
+
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
117
+#ifndef HW_MISC_ALLWINNER_RTC_H
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
118
+#define HW_MISC_ALLWINNER_RTC_H
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
119
+
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
120
+#include "qom/object.h"
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
121
+#include "hw/sysbus.h"
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#ifndef XLNX_EFUSE_H
62
+#define XLNX_EFUSE_H
63
+
64
+#include "sysemu/block-backend.h"
65
+#include "hw/qdev-core.h"
66
+
67
+#define TYPE_XLNX_EFUSE "xlnx,efuse"
68
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE);
69
+
70
+struct XlnxEFuse {
71
+ DeviceState parent_obj;
72
+ BlockBackend *blk;
73
+ bool blk_ro;
74
+ uint32_t *fuse32;
75
+
76
+ DeviceState *dev;
77
+
78
+ bool init_tbits;
79
+
80
+ uint8_t efuse_nr;
81
+ uint32_t efuse_size;
82
+
83
+ uint32_t *ro_bits;
84
+ uint32_t ro_bits_cnt;
85
+};
122
+
86
+
123
+/**
87
+/**
124
+ * Constants
88
+ * xlnx_efuse_calc_crc:
125
+ * @{
89
+ * @data: an array of 32-bit words for which the CRC should be computed
126
+ */
90
+ * @u32_cnt: the array size in number of 32-bit words
127
+
91
+ * @zpads: the number of 32-bit zeros prepended to @data before computation
128
+/** Highest register address used by RTC device */
92
+ *
129
+#define AW_RTC_REGS_MAXADDR (0x200)
93
+ * This function is used to compute the CRC for an array of 32-bit words,
130
+
94
+ * using a Xilinx-specific data padding.
131
+/** Total number of known registers */
95
+ *
132
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
96
+ * Returns: the computed 32-bit CRC
133
+
97
+ */
134
+/** @} */
98
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
99
+ unsigned zpads);
135
+
100
+
136
+/**
101
+/**
137
+ * Object model types
102
+ * xlnx_efuse_get_bit:
138
+ * @{
103
+ * @s: the efuse object
139
+ */
104
+ * @bit: the efuse bit-address to read the data
140
+
105
+ *
141
+/** Generic Allwinner RTC device (abstract) */
106
+ * Returns: the bit, 0 or 1, at @bit of object @s
142
+#define TYPE_AW_RTC "allwinner-rtc"
107
+ */
143
+
108
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit);
144
+/** Allwinner RTC sun4i family (A10, A12) */
145
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
146
+
147
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
148
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
149
+
150
+/** Allwinner RTC sun7i family (A20) */
151
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
152
+
153
+/** @} */
154
+
109
+
155
+/**
110
+/**
156
+ * Object model macros
111
+ * xlnx_efuse_set_bit:
157
+ * @{
112
+ * @s: the efuse object
158
+ */
113
+ * @bit: the efuse bit-address to be written a value of 1
159
+
114
+ *
160
+#define AW_RTC(obj) \
115
+ * Returns: true on success, false on failure
161
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
116
+ */
162
+#define AW_RTC_CLASS(klass) \
117
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit);
163
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
164
+#define AW_RTC_GET_CLASS(obj) \
165
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
166
+
167
+/** @} */
168
+
118
+
169
+/**
119
+/**
170
+ * Allwinner RTC per-object instance state.
120
+ * xlnx_efuse_k256_check:
171
+ */
121
+ * @s: the efuse object
172
+typedef struct AwRtcState {
122
+ * @crc: the 32-bit CRC to be compared with
173
+ /*< private >*/
123
+ * @start: the efuse bit-address (which must be multiple of 32) of the
174
+ SysBusDevice parent_obj;
124
+ * start of a 256-bit array
175
+ /*< public >*/
125
+ *
176
+
126
+ * This function computes the CRC of a 256-bit array starting at @start
177
+ /**
127
+ * then compares to the given @crc
178
+ * Actual year represented by the device when year counter is zero
128
+ *
179
+ *
129
+ * Returns: true of @crc == computed, false otherwise
180
+ * Can be overridden by the user using the corresponding 'base-year'
130
+ */
181
+ * property. The base year used by the target OS driver can vary, for
131
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start);
182
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
183
+ */
184
+ int base_year;
185
+
186
+ /** Maps I/O registers in physical memory */
187
+ MemoryRegion iomem;
188
+
189
+ /** Array of hardware registers */
190
+ uint32_t regs[AW_RTC_REGS_NUM];
191
+
192
+} AwRtcState;
193
+
132
+
194
+/**
133
+/**
195
+ * Allwinner RTC class-level struct.
134
+ * xlnx_efuse_tbits_check:
196
+ *
135
+ * @s: the efuse object
197
+ * This struct is filled by each sunxi device specific code
136
+ *
198
+ * such that the generic code can use this struct to support
137
+ * This function inspects a number of efuse bits at specific addresses
199
+ * all devices.
138
+ * to see if they match a validation pattern. Each pattern is a group
200
+ */
139
+ * of 4 bits, and there are 3 groups.
201
+typedef struct AwRtcClass {
140
+ *
202
+ /*< private >*/
141
+ * Returns: a 3-bit mask, where a bit of '1' means the corresponding
203
+ SysBusDeviceClass parent_class;
142
+ * group has a valid pattern.
204
+ /*< public >*/
143
+ */
205
+
144
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s);
206
+ /** Defines device specific register map */
145
+
207
+ const uint8_t *regmap;
146
+/**
208
+
147
+ * xlnx_efuse_get_row:
209
+ /** Size of the regmap in bytes */
148
+ * @s: the efuse object
210
+ size_t regmap_size;
149
+ * @bit: the efuse bit address for which a 32-bit value is read
211
+
150
+ *
212
+ /**
151
+ * Returns: the entire 32 bits of the efuse, starting at a bit
213
+ * Read device specific register
152
+ * address that is multiple of 32 and contains the bit at @bit
214
+ *
153
+ */
215
+ * @offset: register offset to read
154
+static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit)
216
+ * @return true if register read successful, false otherwise
155
+{
217
+ */
156
+ if (!(s->fuse32)) {
218
+ bool (*read)(AwRtcState *s, uint32_t offset);
157
+ return 0;
219
+
158
+ } else {
220
+ /**
159
+ unsigned int row_idx = bit / 32;
221
+ * Write device specific register
160
+
222
+ *
161
+ assert(row_idx < (s->efuse_size * s->efuse_nr / 32));
223
+ * @offset: register offset to write
162
+ return s->fuse32[row_idx];
224
+ * @data: value to set in register
163
+ }
225
+ * @return true if register write successful, false otherwise
164
+}
226
+ */
165
+
227
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
166
+#endif
228
+
167
diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c
229
+} AwRtcClass;
230
+
231
+#endif /* HW_MISC_ALLWINNER_RTC_H */
232
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/arm/allwinner-a10.c
235
+++ b/hw/arm/allwinner-a10.c
236
@@ -XXX,XX +XXX,XX @@
237
#define AW_A10_EHCI_BASE 0x01c14000
238
#define AW_A10_OHCI_BASE 0x01c14400
239
#define AW_A10_SATA_BASE 0x01c18000
240
+#define AW_A10_RTC_BASE 0x01c20d00
241
242
static void aw_a10_init(Object *obj)
243
{
244
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
245
246
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
247
TYPE_AW_SDHOST_SUN4I);
248
+
249
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
250
+ TYPE_AW_RTC_SUN4I);
251
}
252
253
static void aw_a10_realize(DeviceState *dev, Error **errp)
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
255
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
256
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
257
"sd-bus", &error_abort);
258
+
259
+ /* RTC */
260
+ qdev_init_nofail(DEVICE(&s->rtc));
261
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
262
}
263
264
static void aw_a10_class_init(ObjectClass *oc, void *data)
265
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
266
index XXXXXXX..XXXXXXX 100644
267
--- a/hw/arm/allwinner-h3.c
268
+++ b/hw/arm/allwinner-h3.c
269
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
270
[AW_H3_GIC_CPU] = 0x01c82000,
271
[AW_H3_GIC_HYP] = 0x01c84000,
272
[AW_H3_GIC_VCPU] = 0x01c86000,
273
+ [AW_H3_RTC] = 0x01f00000,
274
[AW_H3_CPUCFG] = 0x01f01c00,
275
[AW_H3_SDRAM] = 0x40000000
276
};
277
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
278
{ "csi", 0x01cb0000, 320 * KiB },
279
{ "tve", 0x01e00000, 64 * KiB },
280
{ "hdmi", 0x01ee0000, 128 * KiB },
281
- { "rtc", 0x01f00000, 1 * KiB },
282
{ "r_timer", 0x01f00800, 1 * KiB },
283
{ "r_intc", 0x01f00c00, 1 * KiB },
284
{ "r_wdog", 0x01f01000, 1 * KiB },
285
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
286
"ram-addr", &error_abort);
287
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
288
"ram-size", &error_abort);
289
+
290
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
291
+ TYPE_AW_RTC_SUN6I);
292
}
293
294
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
295
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
296
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
297
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
298
299
+ /* RTC */
300
+ qdev_init_nofail(DEVICE(&s->rtc));
301
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
302
+
303
/* Unimplemented devices */
304
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
305
create_unimplemented_device(unimplemented[i].device_name,
306
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
307
new file mode 100644
168
new file mode 100644
308
index XXXXXXX..XXXXXXX
169
index XXXXXXX..XXXXXXX
309
--- /dev/null
170
--- /dev/null
310
+++ b/hw/rtc/allwinner-rtc.c
171
+++ b/hw/nvram/xlnx-efuse-crc.c
311
@@ -XXX,XX +XXX,XX @@
172
@@ -XXX,XX +XXX,XX @@
312
+/*
173
+/*
313
+ * Allwinner Real Time Clock emulation
174
+ * Xilinx eFuse/bbram CRC calculator
314
+ *
175
+ *
315
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
176
+ * Copyright (c) 2021 Xilinx Inc.
316
+ *
177
+ *
317
+ * This program is free software: you can redistribute it and/or modify
178
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
318
+ * it under the terms of the GNU General Public License as published by
179
+ * of this software and associated documentation files (the "Software"), to deal
319
+ * the Free Software Foundation, either version 2 of the License, or
180
+ * in the Software without restriction, including without limitation the rights
320
+ * (at your option) any later version.
181
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
321
+ *
182
+ * copies of the Software, and to permit persons to whom the Software is
322
+ * This program is distributed in the hope that it will be useful,
183
+ * furnished to do so, subject to the following conditions:
323
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
184
+ *
324
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
185
+ * The above copyright notice and this permission notice shall be included in
325
+ * GNU General Public License for more details.
186
+ * all copies or substantial portions of the Software.
326
+ *
187
+ *
327
+ * You should have received a copy of the GNU General Public License
188
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
328
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
189
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
329
+ */
190
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
330
+
191
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
192
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
193
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
194
+ * THE SOFTWARE.
195
+ */
331
+#include "qemu/osdep.h"
196
+#include "qemu/osdep.h"
332
+#include "qemu/units.h"
197
+#include "hw/nvram/xlnx-efuse.h"
333
+#include "hw/sysbus.h"
198
+
334
+#include "migration/vmstate.h"
199
+static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data,
200
+ uint32_t addr)
201
+{
202
+ /* A table for 7-bit slicing */
203
+ static const uint32_t crc_tab[128] = {
204
+ 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8,
205
+ 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27,
206
+ 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087,
207
+ 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848,
208
+ 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936,
209
+ 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9,
210
+ 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59,
211
+ 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696,
212
+ 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54,
213
+ 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b,
214
+ 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b,
215
+ 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4,
216
+ 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a,
217
+ 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45,
218
+ 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5,
219
+ 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a,
220
+ 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90,
221
+ 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f,
222
+ 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff,
223
+ 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330,
224
+ 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e,
225
+ 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81,
226
+ 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521,
227
+ 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee,
228
+ 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c,
229
+ 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3,
230
+ 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643,
231
+ 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c,
232
+ 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2,
233
+ 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d,
234
+ 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d,
235
+ 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052
236
+ };
237
+
238
+ /*
239
+ * eFuse calculation is shown here:
240
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496
241
+ *
242
+ * Each u32 word is appended a 5-bit value, for a total of 37 bits; see:
243
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356
244
+ */
245
+ uint32_t crc = prev_crc;
246
+ const unsigned rshf = 7;
247
+ const uint32_t im = (1 << rshf) - 1;
248
+ const uint32_t rm = (1 << (32 - rshf)) - 1;
249
+ const uint32_t i2 = (1 << 2) - 1;
250
+ const uint32_t r2 = (1 << 30) - 1;
251
+
252
+ unsigned j;
253
+ uint32_t i, r;
254
+ uint64_t w;
255
+
256
+ w = (uint64_t)(addr) << 32;
257
+ w |= data;
258
+
259
+ /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */
260
+ for (j = 0; j < 5; j++) {
261
+ r = rm & (crc >> rshf);
262
+ i = im & (crc ^ w);
263
+ crc = crc_tab[i] ^ r;
264
+
265
+ w >>= rshf;
266
+ }
267
+
268
+ /* Feed the remaining 2 bits */
269
+ r = r2 & (crc >> 2);
270
+ i = i2 & (crc ^ w);
271
+ crc = crc_tab[i << (rshf - 2)] ^ r;
272
+
273
+ return crc;
274
+}
275
+
276
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
277
+ unsigned zpads)
278
+{
279
+ uint32_t crc = 0;
280
+ unsigned index;
281
+
282
+ for (index = zpads; index; index--) {
283
+ crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt));
284
+ }
285
+
286
+ for (index = u32_cnt; index; index--) {
287
+ crc = xlnx_efuse_u37_crc(crc, data[index - 1], index);
288
+ }
289
+
290
+ return crc;
291
+}
292
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
293
new file mode 100644
294
index XXXXXXX..XXXXXXX
295
--- /dev/null
296
+++ b/hw/nvram/xlnx-efuse.c
297
@@ -XXX,XX +XXX,XX @@
298
+/*
299
+ * QEMU model of the EFUSE eFuse
300
+ *
301
+ * Copyright (c) 2015 Xilinx Inc.
302
+ *
303
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
304
+ *
305
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
306
+ * of this software and associated documentation files (the "Software"), to deal
307
+ * in the Software without restriction, including without limitation the rights
308
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
309
+ * copies of the Software, and to permit persons to whom the Software is
310
+ * furnished to do so, subject to the following conditions:
311
+ *
312
+ * The above copyright notice and this permission notice shall be included in
313
+ * all copies or substantial portions of the Software.
314
+ *
315
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
316
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
317
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
318
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
319
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
320
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
321
+ * THE SOFTWARE.
322
+ */
323
+
324
+#include "qemu/osdep.h"
325
+#include "hw/nvram/xlnx-efuse.h"
326
+
327
+#include "qemu/error-report.h"
335
+#include "qemu/log.h"
328
+#include "qemu/log.h"
336
+#include "qemu/module.h"
329
+#include "qapi/error.h"
337
+#include "qemu-common.h"
330
+#include "sysemu/blockdev.h"
338
+#include "hw/qdev-properties.h"
331
+#include "hw/qdev-properties.h"
339
+#include "hw/rtc/allwinner-rtc.h"
332
+#include "hw/qdev-properties-system.h"
340
+#include "trace.h"
333
+
341
+
334
+#define TBIT0_OFFSET 28
342
+/* RTC registers */
335
+#define TBIT1_OFFSET 29
343
+enum {
336
+#define TBIT2_OFFSET 30
344
+ REG_LOSC = 1, /* Low Oscillator Control */
337
+#define TBIT3_OFFSET 31
345
+ REG_YYMMDD, /* RTC Year-Month-Day */
338
+#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET)
346
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
339
+#define TBITS_MASK (0x0FU << TBIT0_OFFSET)
347
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
340
+
348
+ REG_ALARM1_EN, /* Alarm1 Enable */
341
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit)
349
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
342
+{
350
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
343
+ bool b = s->fuse32[bit / 32] & (1 << (bit % 32));
351
+ REG_GP0, /* General Purpose Register 0 */
344
+ return b;
352
+ REG_GP1, /* General Purpose Register 1 */
345
+}
353
+ REG_GP2, /* General Purpose Register 2 */
346
+
354
+ REG_GP3, /* General Purpose Register 3 */
347
+static int efuse_bytes(XlnxEFuse *s)
355
+
348
+{
356
+ /* sun4i registers */
349
+ return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4);
357
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
350
+}
358
+ REG_CPUCFG, /* CPU Configuration Register */
351
+
359
+
352
+static int efuse_bdrv_read(XlnxEFuse *s, Error **errp)
360
+ /* sun6i registers */
353
+{
361
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
354
+ uint32_t *ram = s->fuse32;
362
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
355
+ int nr = efuse_bytes(s);
363
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
356
+
364
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
357
+ if (!s->blk) {
365
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
358
+ return 0;
366
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
359
+ }
367
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
360
+
368
+ REG_ALARM_CONFIG, /* Alarm Config */
361
+ s->blk_ro = !blk_supports_write_perm(s->blk);
369
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
362
+ if (!s->blk_ro) {
370
+ REG_GP4, /* General Purpose Register 4 */
363
+ int rc;
371
+ REG_GP5, /* General Purpose Register 5 */
364
+
372
+ REG_GP6, /* General Purpose Register 6 */
365
+ rc = blk_set_perm(s->blk,
373
+ REG_GP7, /* General Purpose Register 7 */
366
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
374
+ REG_RTC_DBG, /* RTC Debug Register */
367
+ BLK_PERM_ALL, NULL);
375
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
368
+ if (rc) {
376
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
369
+ s->blk_ro = true;
377
+ REG_IC_CHARA, /* IC Characteristics Register */
370
+ }
371
+ }
372
+ if (s->blk_ro) {
373
+ warn_report("%s: Skip saving updates to read-only eFUSE backstore.",
374
+ blk_name(s->blk));
375
+ }
376
+
377
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
378
+ error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.",
379
+ blk_name(s->blk), nr);
380
+ return -1;
381
+ }
382
+
383
+ /* Convert from little-endian backstore for each 32-bit row */
384
+ nr /= 4;
385
+ while (nr--) {
386
+ ram[nr] = le32_to_cpu(ram[nr]);
387
+ }
388
+
389
+ return 0;
390
+}
391
+
392
+static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit)
393
+{
394
+ unsigned int row_offset;
395
+ uint32_t le32;
396
+
397
+ if (!s->blk || s->blk_ro) {
398
+ return; /* Silent on read-only backend to avoid message flood */
399
+ }
400
+
401
+ /* Backstore is always in little-endian */
402
+ le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit));
403
+
404
+ row_offset = (bit / 32) * 4;
405
+ if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) {
406
+ error_report("%s: Failed to write offset %u of eFUSE backstore.",
407
+ blk_name(s->blk), row_offset);
408
+ }
409
+}
410
+
411
+static int efuse_ro_bits_cmp(const void *a, const void *b)
412
+{
413
+ uint32_t i = *(const uint32_t *)a;
414
+ uint32_t j = *(const uint32_t *)b;
415
+
416
+ return (i > j) - (i < j);
417
+}
418
+
419
+static void efuse_ro_bits_sort(XlnxEFuse *s)
420
+{
421
+ uint32_t *ary = s->ro_bits;
422
+ const uint32_t cnt = s->ro_bits_cnt;
423
+
424
+ if (ary && cnt > 1) {
425
+ qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp);
426
+ }
427
+}
428
+
429
+static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
430
+{
431
+ const uint32_t *ary = s->ro_bits;
432
+ const uint32_t cnt = s->ro_bits_cnt;
433
+
434
+ if (!ary || !cnt) {
435
+ return false;
436
+ }
437
+
438
+ return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL;
439
+}
440
+
441
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
442
+{
443
+ if (efuse_ro_bits_find(s, bit)) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
445
+ "Ignored setting of readonly efuse bit<%u,%u>!\n",
446
+ object_get_canonical_path(OBJECT(s)),
447
+ (bit / 32), (bit % 32));
448
+ return false;
449
+ }
450
+
451
+ s->fuse32[bit / 32] |= 1 << (bit % 32);
452
+ efuse_bdrv_sync(s, bit);
453
+ return true;
454
+}
455
+
456
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start)
457
+{
458
+ uint32_t calc;
459
+
460
+ /* A key always occupies multiple of whole rows */
461
+ assert((start % 32) == 0);
462
+
463
+ calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0);
464
+ return calc == crc;
465
+}
466
+
467
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s)
468
+{
469
+ int nr;
470
+ uint32_t check = 0;
471
+
472
+ for (nr = s->efuse_nr; nr-- > 0; ) {
473
+ int efuse_start_row_num = (s->efuse_size * nr) / 32;
474
+ uint32_t data = s->fuse32[efuse_start_row_num];
475
+
476
+ /*
477
+ * If the option is on, auto-init blank T-bits.
478
+ * (non-blank will still be reported as '0' in the check, e.g.,
479
+ * for error-injection tests)
480
+ */
481
+ if ((data & TBITS_MASK) == 0 && s->init_tbits) {
482
+ data |= TBITS_PATTERN;
483
+
484
+ s->fuse32[efuse_start_row_num] = data;
485
+ efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET));
486
+ }
487
+
488
+ check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN);
489
+ }
490
+
491
+ return check;
492
+}
493
+
494
+static void efuse_realize(DeviceState *dev, Error **errp)
495
+{
496
+ XlnxEFuse *s = XLNX_EFUSE(dev);
497
+
498
+ /* Sort readonly-list for bsearch lookup */
499
+ efuse_ro_bits_sort(s);
500
+
501
+ if ((s->efuse_size % 32) != 0) {
502
+ error_setg(errp,
503
+ "%s.efuse-size: %u: property value not multiple of 32.",
504
+ object_get_canonical_path(OBJECT(dev)), s->efuse_size);
505
+ return;
506
+ }
507
+
508
+ s->fuse32 = g_malloc0(efuse_bytes(s));
509
+ if (efuse_bdrv_read(s, errp)) {
510
+ g_free(s->fuse32);
511
+ }
512
+}
513
+
514
+static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name,
515
+ void *opaque, Error **errp)
516
+{
517
+ DeviceState *dev = DEVICE(obj);
518
+
519
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
520
+
521
+ /* Fill initial data if backend is attached after realized */
522
+ if (dev->realized) {
523
+ efuse_bdrv_read(XLNX_EFUSE(obj), errp);
524
+ }
525
+}
526
+
527
+static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name,
528
+ void *opaque, Error **errp)
529
+{
530
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
531
+}
532
+
533
+static void efuse_prop_release_drive(Object *obj, const char *name,
534
+ void *opaque)
535
+{
536
+ qdev_prop_drive.release(obj, name, opaque);
537
+}
538
+
539
+static const PropertyInfo efuse_prop_drive = {
540
+ .name = "str",
541
+ .description = "Node name or ID of a block device to use as eFUSE backend",
542
+ .realized_set_allowed = true,
543
+ .get = efuse_prop_get_drive,
544
+ .set = efuse_prop_set_drive,
545
+ .release = efuse_prop_release_drive,
378
+};
546
+};
379
+
547
+
380
+/* RTC register flags */
548
+static Property efuse_properties[] = {
381
+enum {
549
+ DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *),
382
+ REG_LOSC_YMD = (1 << 7),
550
+ DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3),
383
+ REG_LOSC_HMS = (1 << 8),
551
+ DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32),
384
+};
552
+ DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true),
385
+
553
+ DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits,
386
+/* RTC sun4i register map (offset to name) */
554
+ qdev_prop_uint32, uint32_t),
387
+const uint8_t allwinner_rtc_sun4i_regmap[] = {
388
+ [0x0000] = REG_LOSC,
389
+ [0x0004] = REG_YYMMDD,
390
+ [0x0008] = REG_HHMMSS,
391
+ [0x000C] = REG_ALARM1_DDHHMMSS,
392
+ [0x0010] = REG_ALARM1_WKHHMMSS,
393
+ [0x0014] = REG_ALARM1_EN,
394
+ [0x0018] = REG_ALARM1_IRQ_EN,
395
+ [0x001C] = REG_ALARM1_IRQ_STA,
396
+ [0x0020] = REG_GP0,
397
+ [0x0024] = REG_GP1,
398
+ [0x0028] = REG_GP2,
399
+ [0x002C] = REG_GP3,
400
+ [0x003C] = REG_CPUCFG,
401
+};
402
+
403
+/* RTC sun6i register map (offset to name) */
404
+const uint8_t allwinner_rtc_sun6i_regmap[] = {
405
+ [0x0000] = REG_LOSC,
406
+ [0x0004] = REG_LOSC_AUTOSTA,
407
+ [0x0008] = REG_INT_OSC_PRE,
408
+ [0x0010] = REG_YYMMDD,
409
+ [0x0014] = REG_HHMMSS,
410
+ [0x0020] = REG_ALARM0_COUNTER,
411
+ [0x0024] = REG_ALARM0_CUR_VLU,
412
+ [0x0028] = REG_ALARM0_ENABLE,
413
+ [0x002C] = REG_ALARM0_IRQ_EN,
414
+ [0x0030] = REG_ALARM0_IRQ_STA,
415
+ [0x0040] = REG_ALARM1_WKHHMMSS,
416
+ [0x0044] = REG_ALARM1_EN,
417
+ [0x0048] = REG_ALARM1_IRQ_EN,
418
+ [0x004C] = REG_ALARM1_IRQ_STA,
419
+ [0x0050] = REG_ALARM_CONFIG,
420
+ [0x0060] = REG_LOSC_OUT_GATING,
421
+ [0x0100] = REG_GP0,
422
+ [0x0104] = REG_GP1,
423
+ [0x0108] = REG_GP2,
424
+ [0x010C] = REG_GP3,
425
+ [0x0110] = REG_GP4,
426
+ [0x0114] = REG_GP5,
427
+ [0x0118] = REG_GP6,
428
+ [0x011C] = REG_GP7,
429
+ [0x0170] = REG_RTC_DBG,
430
+ [0x0180] = REG_GPL_HOLD_OUT,
431
+ [0x0190] = REG_VDD_RTC,
432
+ [0x01F0] = REG_IC_CHARA,
433
+};
434
+
435
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
436
+{
437
+ /* no sun4i specific registers currently implemented */
438
+ return false;
439
+}
440
+
441
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
442
+ uint32_t data)
443
+{
444
+ /* no sun4i specific registers currently implemented */
445
+ return false;
446
+}
447
+
448
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
449
+{
450
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
451
+
452
+ switch (c->regmap[offset]) {
453
+ case REG_GP4: /* General Purpose Register 4 */
454
+ case REG_GP5: /* General Purpose Register 5 */
455
+ case REG_GP6: /* General Purpose Register 6 */
456
+ case REG_GP7: /* General Purpose Register 7 */
457
+ return true;
458
+ default:
459
+ break;
460
+ }
461
+ return false;
462
+}
463
+
464
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
465
+ uint32_t data)
466
+{
467
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
468
+
469
+ switch (c->regmap[offset]) {
470
+ case REG_GP4: /* General Purpose Register 4 */
471
+ case REG_GP5: /* General Purpose Register 5 */
472
+ case REG_GP6: /* General Purpose Register 6 */
473
+ case REG_GP7: /* General Purpose Register 7 */
474
+ return true;
475
+ default:
476
+ break;
477
+ }
478
+ return false;
479
+}
480
+
481
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
482
+ unsigned size)
483
+{
484
+ AwRtcState *s = AW_RTC(opaque);
485
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
486
+ uint64_t val = 0;
487
+
488
+ if (offset >= c->regmap_size) {
489
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
490
+ __func__, (uint32_t)offset);
491
+ return 0;
492
+ }
493
+
494
+ if (!c->regmap[offset]) {
495
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
496
+ __func__, (uint32_t)offset);
497
+ return 0;
498
+ }
499
+
500
+ switch (c->regmap[offset]) {
501
+ case REG_LOSC: /* Low Oscillator Control */
502
+ val = s->regs[REG_LOSC];
503
+ s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
504
+ break;
505
+ case REG_YYMMDD: /* RTC Year-Month-Day */
506
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
507
+ case REG_GP0: /* General Purpose Register 0 */
508
+ case REG_GP1: /* General Purpose Register 1 */
509
+ case REG_GP2: /* General Purpose Register 2 */
510
+ case REG_GP3: /* General Purpose Register 3 */
511
+ val = s->regs[c->regmap[offset]];
512
+ break;
513
+ default:
514
+ if (!c->read(s, offset)) {
515
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
516
+ __func__, (uint32_t)offset);
517
+ }
518
+ val = s->regs[c->regmap[offset]];
519
+ break;
520
+ }
521
+
522
+ trace_allwinner_rtc_read(offset, val);
523
+ return val;
524
+}
525
+
526
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
527
+ uint64_t val, unsigned size)
528
+{
529
+ AwRtcState *s = AW_RTC(opaque);
530
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
531
+
532
+ if (offset >= c->regmap_size) {
533
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
534
+ __func__, (uint32_t)offset);
535
+ return;
536
+ }
537
+
538
+ if (!c->regmap[offset]) {
539
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
540
+ __func__, (uint32_t)offset);
541
+ return;
542
+ }
543
+
544
+ trace_allwinner_rtc_write(offset, val);
545
+
546
+ switch (c->regmap[offset]) {
547
+ case REG_YYMMDD: /* RTC Year-Month-Day */
548
+ s->regs[REG_YYMMDD] = val;
549
+ s->regs[REG_LOSC] |= REG_LOSC_YMD;
550
+ break;
551
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
552
+ s->regs[REG_HHMMSS] = val;
553
+ s->regs[REG_LOSC] |= REG_LOSC_HMS;
554
+ break;
555
+ case REG_GP0: /* General Purpose Register 0 */
556
+ case REG_GP1: /* General Purpose Register 1 */
557
+ case REG_GP2: /* General Purpose Register 2 */
558
+ case REG_GP3: /* General Purpose Register 3 */
559
+ s->regs[c->regmap[offset]] = val;
560
+ break;
561
+ default:
562
+ if (!c->write(s, offset, val)) {
563
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
564
+ __func__, (uint32_t)offset);
565
+ }
566
+ break;
567
+ }
568
+}
569
+
570
+static const MemoryRegionOps allwinner_rtc_ops = {
571
+ .read = allwinner_rtc_read,
572
+ .write = allwinner_rtc_write,
573
+ .endianness = DEVICE_NATIVE_ENDIAN,
574
+ .valid = {
575
+ .min_access_size = 4,
576
+ .max_access_size = 4,
577
+ },
578
+ .impl.min_access_size = 4,
579
+};
580
+
581
+static void allwinner_rtc_reset(DeviceState *dev)
582
+{
583
+ AwRtcState *s = AW_RTC(dev);
584
+ struct tm now;
585
+
586
+ /* Clear registers */
587
+ memset(s->regs, 0, sizeof(s->regs));
588
+
589
+ /* Get current datetime */
590
+ qemu_get_timedate(&now, 0);
591
+
592
+ /* Set RTC with current datetime */
593
+ if (s->base_year > 1900) {
594
+ s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
595
+ ((now.tm_mon + 1) << 8) |
596
+ now.tm_mday;
597
+ s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
598
+ (now.tm_hour << 16) |
599
+ (now.tm_min << 8) |
600
+ now.tm_sec;
601
+ }
602
+}
603
+
604
+static void allwinner_rtc_init(Object *obj)
605
+{
606
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
607
+ AwRtcState *s = AW_RTC(obj);
608
+
609
+ /* Memory mapping */
610
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
611
+ TYPE_AW_RTC, 1 * KiB);
612
+ sysbus_init_mmio(sbd, &s->iomem);
613
+}
614
+
615
+static const VMStateDescription allwinner_rtc_vmstate = {
616
+ .name = "allwinner-rtc",
617
+ .version_id = 1,
618
+ .minimum_version_id = 1,
619
+ .fields = (VMStateField[]) {
620
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
621
+ VMSTATE_END_OF_LIST()
622
+ }
623
+};
624
+
625
+static Property allwinner_rtc_properties[] = {
626
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
627
+ DEFINE_PROP_END_OF_LIST(),
555
+ DEFINE_PROP_END_OF_LIST(),
628
+};
556
+};
629
+
557
+
630
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
558
+static void efuse_class_init(ObjectClass *klass, void *data)
631
+{
559
+{
632
+ DeviceClass *dc = DEVICE_CLASS(klass);
560
+ DeviceClass *dc = DEVICE_CLASS(klass);
633
+
561
+
634
+ dc->reset = allwinner_rtc_reset;
562
+ dc->realize = efuse_realize;
635
+ dc->vmsd = &allwinner_rtc_vmstate;
563
+ device_class_set_props(dc, efuse_properties);
636
+ device_class_set_props(dc, allwinner_rtc_properties);
564
+}
637
+}
565
+
638
+
566
+static const TypeInfo efuse_info = {
639
+static void allwinner_rtc_sun4i_init(Object *obj)
567
+ .name = TYPE_XLNX_EFUSE,
640
+{
568
+ .parent = TYPE_DEVICE,
641
+ AwRtcState *s = AW_RTC(obj);
569
+ .instance_size = sizeof(XlnxEFuse),
642
+ s->base_year = 2010;
570
+ .class_init = efuse_class_init,
643
+}
644
+
645
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
646
+{
647
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
648
+
649
+ arc->regmap = allwinner_rtc_sun4i_regmap;
650
+ arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
651
+ arc->read = allwinner_rtc_sun4i_read;
652
+ arc->write = allwinner_rtc_sun4i_write;
653
+}
654
+
655
+static void allwinner_rtc_sun6i_init(Object *obj)
656
+{
657
+ AwRtcState *s = AW_RTC(obj);
658
+ s->base_year = 1970;
659
+}
660
+
661
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
662
+{
663
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
664
+
665
+ arc->regmap = allwinner_rtc_sun6i_regmap;
666
+ arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
667
+ arc->read = allwinner_rtc_sun6i_read;
668
+ arc->write = allwinner_rtc_sun6i_write;
669
+}
670
+
671
+static void allwinner_rtc_sun7i_init(Object *obj)
672
+{
673
+ AwRtcState *s = AW_RTC(obj);
674
+ s->base_year = 1970;
675
+}
676
+
677
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
678
+{
679
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
680
+ allwinner_rtc_sun4i_class_init(klass, arc);
681
+}
682
+
683
+static const TypeInfo allwinner_rtc_info = {
684
+ .name = TYPE_AW_RTC,
685
+ .parent = TYPE_SYS_BUS_DEVICE,
686
+ .instance_init = allwinner_rtc_init,
687
+ .instance_size = sizeof(AwRtcState),
688
+ .class_init = allwinner_rtc_class_init,
689
+ .class_size = sizeof(AwRtcClass),
690
+ .abstract = true,
691
+};
571
+};
692
+
572
+
693
+static const TypeInfo allwinner_rtc_sun4i_info = {
573
+static void efuse_register_types(void)
694
+ .name = TYPE_AW_RTC_SUN4I,
574
+{
695
+ .parent = TYPE_AW_RTC,
575
+ type_register_static(&efuse_info);
696
+ .class_init = allwinner_rtc_sun4i_class_init,
576
+}
697
+ .instance_init = allwinner_rtc_sun4i_init,
577
+type_init(efuse_register_types)
698
+};
578
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
699
+
700
+static const TypeInfo allwinner_rtc_sun6i_info = {
701
+ .name = TYPE_AW_RTC_SUN6I,
702
+ .parent = TYPE_AW_RTC,
703
+ .class_init = allwinner_rtc_sun6i_class_init,
704
+ .instance_init = allwinner_rtc_sun6i_init,
705
+};
706
+
707
+static const TypeInfo allwinner_rtc_sun7i_info = {
708
+ .name = TYPE_AW_RTC_SUN7I,
709
+ .parent = TYPE_AW_RTC,
710
+ .class_init = allwinner_rtc_sun7i_class_init,
711
+ .instance_init = allwinner_rtc_sun7i_init,
712
+};
713
+
714
+static void allwinner_rtc_register(void)
715
+{
716
+ type_register_static(&allwinner_rtc_info);
717
+ type_register_static(&allwinner_rtc_sun4i_info);
718
+ type_register_static(&allwinner_rtc_sun6i_info);
719
+ type_register_static(&allwinner_rtc_sun7i_info);
720
+}
721
+
722
+type_init(allwinner_rtc_register)
723
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
724
index XXXXXXX..XXXXXXX 100644
579
index XXXXXXX..XXXXXXX 100644
725
--- a/hw/rtc/trace-events
580
--- a/hw/nvram/Kconfig
726
+++ b/hw/rtc/trace-events
581
+++ b/hw/nvram/Kconfig
727
@@ -XXX,XX +XXX,XX @@
582
@@ -XXX,XX +XXX,XX @@ config NMC93XX_EEPROM
728
# See docs/devel/tracing.txt for syntax documentation.
583
729
584
config CHRP_NVRAM
730
+# allwinner-rtc.c
585
bool
731
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
586
+
732
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
587
+config XLNX_EFUSE_CRC
733
+
588
+ bool
734
# sun4v-rtc.c
589
+
735
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
590
+config XLNX_EFUSE
736
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
591
+ bool
592
+ select XLNX_EFUSE_CRC
593
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
594
index XXXXXXX..XXXXXXX 100644
595
--- a/hw/nvram/meson.build
596
+++ b/hw/nvram/meson.build
597
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
598
softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
599
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
600
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
601
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
602
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
603
604
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
737
--
605
--
738
2.20.1
606
2.20.1
739
607
740
608
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
The Allwinner H3 System on Chip has an System Control
3
This implements the Xilinx Versal eFuse, an one-time
4
module that provides system wide generic controls and
4
field-programmable non-volatile storage device. There is
5
device information. This commit adds support for the
5
only one such device in the Xilinx Versal product family.
6
Allwinner H3 System Control module.
7
6
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
7
This device has two separate mmio interfaces, a controller
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
and a flatten readback.
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
The controller provides interfaces for field-programming,
12
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
11
configuration, control, and status.
12
13
The flatten readback is a cache to provide a byte-accessible
14
read-only interface to efficiently read efuse array.
15
16
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
17
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
18
19
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
21
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
22
Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
25
---
15
hw/misc/Makefile.objs | 1 +
26
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
16
include/hw/arm/allwinner-h3.h | 3 +
27
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
17
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
28
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
29
hw/nvram/Kconfig | 4 +
19
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
30
hw/nvram/meson.build | 3 +
20
5 files changed, 219 insertions(+), 1 deletion(-)
31
5 files changed, 972 insertions(+)
21
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
32
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
22
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
33
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
34
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
23
35
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
36
diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
27
+++ b/hw/misc/Makefile.objs
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
29
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
30
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/timer/allwinner-a10-pit.h"
42
#include "hw/intc/arm_gic.h"
43
#include "hw/misc/allwinner-h3-ccu.h"
44
+#include "hw/misc/allwinner-h3-sysctrl.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_SYSCTRL,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
const hwaddr *memmap;
58
AwA10PITState timer;
59
AwH3ClockCtlState ccu;
60
+ AwH3SysCtrlState sysctrl;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
65
new file mode 100644
37
new file mode 100644
66
index XXXXXXX..XXXXXXX
38
index XXXXXXX..XXXXXXX
67
--- /dev/null
39
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
40
+++ b/include/hw/nvram/xlnx-versal-efuse.h
69
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
70
+/*
42
+/*
71
+ * Allwinner H3 System Control emulation
43
+ * Copyright (c) 2020 Xilinx Inc.
72
+ *
44
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
45
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
74
+ *
46
+ * of this software and associated documentation files (the "Software"), to deal
75
+ * This program is free software: you can redistribute it and/or modify
47
+ * in the Software without restriction, including without limitation the rights
76
+ * it under the terms of the GNU General Public License as published by
48
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
77
+ * the Free Software Foundation, either version 2 of the License, or
49
+ * copies of the Software, and to permit persons to whom the Software is
78
+ * (at your option) any later version.
50
+ * furnished to do so, subject to the following conditions:
79
+ *
51
+ *
80
+ * This program is distributed in the hope that it will be useful,
52
+ * The above copyright notice and this permission notice shall be included in
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
53
+ * all copies or substantial portions of the Software.
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
54
+ *
83
+ * GNU General Public License for more details.
55
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
84
+ *
56
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
85
+ * You should have received a copy of the GNU General Public License
57
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
58
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
59
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
60
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
61
+ * THE SOFTWARE.
87
+ */
62
+ */
88
+
63
+#ifndef XLNX_VERSAL_EFUSE_H
89
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
64
+#define XLNX_VERSAL_EFUSE_H
90
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
65
+
91
+
66
+#include "hw/irq.h"
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
67
+#include "hw/sysbus.h"
68
+#include "hw/register.h"
69
+#include "hw/nvram/xlnx-efuse.h"
70
+
71
+#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1)
72
+
73
+#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse"
74
+#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache"
75
+
76
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL);
77
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE);
78
+
79
+struct XlnxVersalEFuseCtrl {
80
+ SysBusDevice parent_obj;
81
+ qemu_irq irq_efuse_imr;
82
+
83
+ XlnxEFuse *efuse;
84
+
85
+ void *extra_pg0_lock_spec; /* Opaque property */
86
+ uint32_t extra_pg0_lock_n16;
87
+
88
+ uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
89
+ RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
90
+};
91
+
92
+struct XlnxVersalEFuseCache {
93
+ SysBusDevice parent_obj;
94
+ MemoryRegion iomem;
95
+
96
+ XlnxEFuse *efuse;
97
+};
94
+
98
+
95
+/**
99
+/**
96
+ * @name Constants
100
+ * xlnx_versal_efuse_read_row:
97
+ * @{
101
+ * @s: the efuse object
102
+ * @bit: the bit-address within the 32-bit row to be read
103
+ * @denied: if non-NULL, to receive true if the row is write-only
104
+ *
105
+ * Returns: the 32-bit word containing address @bit; 0 if @denies is true
98
+ */
106
+ */
99
+
107
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied);
100
+/** Highest register address used by System Control device */
108
+
101
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
109
+#endif
102
+
110
diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c
103
+/** Total number of known registers */
104
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
105
+ sizeof(uint32_t)) + 1)
106
+
107
+/** @} */
108
+
109
+/**
110
+ * @name Object model
111
+ * @{
112
+ */
113
+
114
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
115
+#define AW_H3_SYSCTRL(obj) \
116
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
117
+
118
+/** @} */
119
+
120
+/**
121
+ * Allwinner H3 System Control object instance state
122
+ */
123
+typedef struct AwH3SysCtrlState {
124
+ /*< private >*/
125
+ SysBusDevice parent_obj;
126
+ /*< public >*/
127
+
128
+ /** Maps I/O registers in physical memory */
129
+ MemoryRegion iomem;
130
+
131
+ /** Array of hardware registers */
132
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
133
+
134
+} AwH3SysCtrlState;
135
+
136
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
137
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/hw/arm/allwinner-h3.c
140
+++ b/hw/arm/allwinner-h3.c
141
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
142
[AW_H3_SRAM_A1] = 0x00000000,
143
[AW_H3_SRAM_A2] = 0x00044000,
144
[AW_H3_SRAM_C] = 0x00010000,
145
+ [AW_H3_SYSCTRL] = 0x01c00000,
146
[AW_H3_EHCI0] = 0x01c1a000,
147
[AW_H3_OHCI0] = 0x01c1a400,
148
[AW_H3_EHCI1] = 0x01c1b000,
149
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
150
} unimplemented[] = {
151
{ "d-engine", 0x01000000, 4 * MiB },
152
{ "d-inter", 0x01400000, 128 * KiB },
153
- { "syscon", 0x01c00000, 4 * KiB },
154
{ "dma", 0x01c02000, 4 * KiB },
155
{ "nfdc", 0x01c03000, 4 * KiB },
156
{ "ts", 0x01c06000, 4 * KiB },
157
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
158
159
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
160
TYPE_AW_H3_CCU);
161
+
162
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
163
+ TYPE_AW_H3_SYSCTRL);
164
}
165
166
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
168
qdev_init_nofail(DEVICE(&s->ccu));
169
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
170
171
+ /* System Control */
172
+ qdev_init_nofail(DEVICE(&s->sysctrl));
173
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
174
+
175
/* Universal Serial Bus */
176
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
177
qdev_get_gpio_in(DEVICE(&s->gic),
178
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
179
new file mode 100644
111
new file mode 100644
180
index XXXXXXX..XXXXXXX
112
index XXXXXXX..XXXXXXX
181
--- /dev/null
113
--- /dev/null
182
+++ b/hw/misc/allwinner-h3-sysctrl.c
114
+++ b/hw/nvram/xlnx-versal-efuse-cache.c
183
@@ -XXX,XX +XXX,XX @@
115
@@ -XXX,XX +XXX,XX @@
184
+/*
116
+/*
185
+ * Allwinner H3 System Control emulation
117
+ * QEMU model of the EFuse_Cache
186
+ *
118
+ *
187
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
119
+ * Copyright (c) 2017 Xilinx Inc.
188
+ *
120
+ *
189
+ * This program is free software: you can redistribute it and/or modify
121
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
190
+ * it under the terms of the GNU General Public License as published by
122
+ * of this software and associated documentation files (the "Software"), to deal
191
+ * the Free Software Foundation, either version 2 of the License, or
123
+ * in the Software without restriction, including without limitation the rights
192
+ * (at your option) any later version.
124
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
193
+ *
125
+ * copies of the Software, and to permit persons to whom the Software is
194
+ * This program is distributed in the hope that it will be useful,
126
+ * furnished to do so, subject to the following conditions:
195
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
127
+ *
196
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
128
+ * The above copyright notice and this permission notice shall be included in
197
+ * GNU General Public License for more details.
129
+ * all copies or substantial portions of the Software.
198
+ *
130
+ *
199
+ * You should have received a copy of the GNU General Public License
131
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
200
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
132
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
133
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
134
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
135
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
136
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
137
+ * THE SOFTWARE.
201
+ */
138
+ */
202
+
139
+
203
+#include "qemu/osdep.h"
140
+#include "qemu/osdep.h"
204
+#include "qemu/units.h"
141
+#include "hw/nvram/xlnx-versal-efuse.h"
205
+#include "hw/sysbus.h"
142
+
143
+#include "qemu/log.h"
144
+#include "hw/qdev-properties.h"
145
+
146
+#define MR_SIZE 0xC00
147
+
148
+static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size)
149
+{
150
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque);
151
+ unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32);
152
+ unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32);
153
+
154
+ uint64_t ret;
155
+
156
+ assert(w0 == w1 || (w0 + 32) == w1);
157
+
158
+ ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL);
159
+ if (w0 < w1) {
160
+ ret <<= 32;
161
+ ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL);
162
+ }
163
+
164
+ /* If 'addr' unaligned, the guest is always assumed to be little-endian. */
165
+ addr &= 3;
166
+ if (addr) {
167
+ ret >>= 8 * addr;
168
+ }
169
+
170
+ return ret;
171
+}
172
+
173
+static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value,
174
+ unsigned size)
175
+{
176
+ /* No Register Writes allowed */
177
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only",
178
+ __func__);
179
+}
180
+
181
+static const MemoryRegionOps efuse_cache_ops = {
182
+ .read = efuse_cache_read,
183
+ .write = efuse_cache_write,
184
+ .endianness = DEVICE_LITTLE_ENDIAN,
185
+ .valid = {
186
+ .min_access_size = 1,
187
+ .max_access_size = 4,
188
+ },
189
+};
190
+
191
+static void efuse_cache_init(Object *obj)
192
+{
193
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj);
194
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
195
+
196
+ memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s,
197
+ TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE);
198
+ sysbus_init_mmio(sbd, &s->iomem);
199
+}
200
+
201
+static Property efuse_cache_props[] = {
202
+ DEFINE_PROP_LINK("efuse",
203
+ XlnxVersalEFuseCache, efuse,
204
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
205
+
206
+ DEFINE_PROP_END_OF_LIST(),
207
+};
208
+
209
+static void efuse_cache_class_init(ObjectClass *klass, void *data)
210
+{
211
+ DeviceClass *dc = DEVICE_CLASS(klass);
212
+
213
+ device_class_set_props(dc, efuse_cache_props);
214
+}
215
+
216
+static const TypeInfo efuse_cache_info = {
217
+ .name = TYPE_XLNX_VERSAL_EFUSE_CACHE,
218
+ .parent = TYPE_SYS_BUS_DEVICE,
219
+ .instance_size = sizeof(XlnxVersalEFuseCache),
220
+ .class_init = efuse_cache_class_init,
221
+ .instance_init = efuse_cache_init,
222
+};
223
+
224
+static void efuse_cache_register_types(void)
225
+{
226
+ type_register_static(&efuse_cache_info);
227
+}
228
+
229
+type_init(efuse_cache_register_types)
230
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
231
new file mode 100644
232
index XXXXXXX..XXXXXXX
233
--- /dev/null
234
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
235
@@ -XXX,XX +XXX,XX @@
236
+/*
237
+ * QEMU model of the Versal eFuse controller
238
+ *
239
+ * Copyright (c) 2020 Xilinx Inc.
240
+ *
241
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
242
+ * of this software and associated documentation files (the "Software"), to deal
243
+ * in the Software without restriction, including without limitation the rights
244
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
245
+ * copies of the Software, and to permit persons to whom the Software is
246
+ * furnished to do so, subject to the following conditions:
247
+ *
248
+ * The above copyright notice and this permission notice shall be included in
249
+ * all copies or substantial portions of the Software.
250
+ *
251
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
252
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
253
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
254
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
255
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
256
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
257
+ * THE SOFTWARE.
258
+ */
259
+
260
+#include "qemu/osdep.h"
261
+#include "hw/nvram/xlnx-versal-efuse.h"
262
+
263
+#include "qemu/log.h"
264
+#include "qapi/error.h"
206
+#include "migration/vmstate.h"
265
+#include "migration/vmstate.h"
207
+#include "qemu/log.h"
266
+#include "hw/qdev-properties.h"
208
+#include "qemu/module.h"
267
+
209
+#include "hw/misc/allwinner-h3-sysctrl.h"
268
+#ifndef XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG
210
+
269
+#define XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG 0
211
+/* System Control register offsets */
270
+#endif
212
+enum {
271
+
213
+ REG_VER = 0x24, /* Version */
272
+REG32(WR_LOCK, 0x0)
214
+ REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
273
+ FIELD(WR_LOCK, LOCK, 0, 16)
215
+};
274
+REG32(CFG, 0x4)
216
+
275
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
217
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
276
+ FIELD(CFG, MARGIN_RD, 2, 1)
218
+
277
+ FIELD(CFG, PGM_EN, 1, 1)
219
+/* System Control register reset values */
278
+REG32(STATUS, 0x8)
220
+enum {
279
+ FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1)
221
+ REG_VER_RST = 0x0,
280
+ FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1)
222
+ REG_EMAC_PHY_CLK_RST = 0x58000,
281
+ FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1)
223
+};
282
+ FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
224
+
283
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
225
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
284
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
226
+ unsigned size)
285
+ FIELD(STATUS, CACHE_DONE, 5, 1)
227
+{
286
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
228
+ const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
287
+ FIELD(STATUS, EFUSE_2_TBIT, 2, 1)
229
+ const uint32_t idx = REG_INDEX(offset);
288
+ FIELD(STATUS, EFUSE_1_TBIT, 1, 1)
230
+
289
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
231
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
290
+REG32(EFUSE_PGM_ADDR, 0xc)
232
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
291
+ FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4)
233
+ __func__, (uint32_t)offset);
292
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
234
+ return 0;
293
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
235
+ }
294
+REG32(EFUSE_RD_ADDR, 0x10)
236
+
295
+ FIELD(EFUSE_RD_ADDR, PAGE, 13, 4)
237
+ return s->regs[idx];
296
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
238
+}
297
+REG32(EFUSE_RD_DATA, 0x14)
239
+
298
+REG32(TPGM, 0x18)
240
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
299
+ FIELD(TPGM, VALUE, 0, 16)
241
+ uint64_t val, unsigned size)
300
+REG32(TRD, 0x1c)
242
+{
301
+ FIELD(TRD, VALUE, 0, 8)
243
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
302
+REG32(TSU_H_PS, 0x20)
244
+ const uint32_t idx = REG_INDEX(offset);
303
+ FIELD(TSU_H_PS, VALUE, 0, 8)
245
+
304
+REG32(TSU_H_PS_CS, 0x24)
246
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
305
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
247
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
306
+REG32(TRDM, 0x28)
248
+ __func__, (uint32_t)offset);
307
+ FIELD(TRDM, VALUE, 0, 8)
308
+REG32(TSU_H_CS, 0x2c)
309
+ FIELD(TSU_H_CS, VALUE, 0, 8)
310
+REG32(EFUSE_ISR, 0x30)
311
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
312
+ FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1)
313
+ FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1)
314
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1)
315
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1)
316
+ FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1)
317
+ FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1)
318
+ FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1)
319
+ FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1)
320
+ FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1)
321
+ FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1)
322
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
323
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
324
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
325
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
326
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
327
+REG32(EFUSE_IMR, 0x34)
328
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
329
+ FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1)
330
+ FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1)
331
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1)
332
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1)
333
+ FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1)
334
+ FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1)
335
+ FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1)
336
+ FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1)
337
+ FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1)
338
+ FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1)
339
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
340
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
341
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
342
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
343
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
344
+REG32(EFUSE_IER, 0x38)
345
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
346
+ FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1)
347
+ FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1)
348
+ FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1)
349
+ FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1)
350
+ FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1)
351
+ FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1)
352
+ FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1)
353
+ FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1)
354
+ FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1)
355
+ FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1)
356
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
357
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
358
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
359
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
360
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
361
+REG32(EFUSE_IDR, 0x3c)
362
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
363
+ FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1)
364
+ FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1)
365
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1)
366
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1)
367
+ FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1)
368
+ FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1)
369
+ FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1)
370
+ FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1)
371
+ FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1)
372
+ FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1)
373
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
374
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
375
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
376
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
377
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
378
+REG32(EFUSE_CACHE_LOAD, 0x40)
379
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
380
+REG32(EFUSE_PGM_LOCK, 0x44)
381
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
382
+REG32(EFUSE_AES_CRC, 0x48)
383
+REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c)
384
+REG32(EFUSE_AES_USR_KEY1_CRC, 0x50)
385
+REG32(EFUSE_PD, 0x54)
386
+REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60)
387
+REG32(EFUSE_TEST_CTRL, 0x100)
388
+
389
+#define R_MAX (R_EFUSE_TEST_CTRL + 1)
390
+
391
+#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D)
392
+
393
+/*
394
+ * eFuse layout references:
395
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h
396
+ */
397
+#define BIT_POS_OF(A_) \
398
+ ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \
399
+ R_EFUSE_PGM_ADDR_COLUMN_MASK)))
400
+
401
+#define BIT_POS(R_, C_) \
402
+ ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \
403
+ & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \
404
+ | \
405
+ (R_EFUSE_PGM_ADDR_COLUMN_MASK \
406
+ & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT))))
407
+
408
+#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28))
409
+
410
+#define EFUSE_ANCHOR_ROW (0)
411
+#define EFUSE_ANCHOR_3_COL (27)
412
+#define EFUSE_ANCHOR_1_COL (1)
413
+
414
+#define EFUSE_AES_KEY_START BIT_POS(12, 0)
415
+#define EFUSE_AES_KEY_END BIT_POS(19, 31)
416
+#define EFUSE_USER_KEY_0_START BIT_POS(20, 0)
417
+#define EFUSE_USER_KEY_0_END BIT_POS(27, 31)
418
+#define EFUSE_USER_KEY_1_START BIT_POS(28, 0)
419
+#define EFUSE_USER_KEY_1_END BIT_POS(35, 31)
420
+
421
+#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START
422
+#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END
423
+
424
+#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31)
425
+#define EFUSE_PPK0_WR_LK BIT_POS(43, 6)
426
+#define EFUSE_PPK1_WR_LK BIT_POS(43, 7)
427
+#define EFUSE_PPK2_WR_LK BIT_POS(43, 8)
428
+#define EFUSE_AES_WR_LK BIT_POS(43, 11)
429
+#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13)
430
+#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15)
431
+#define EFUSE_PUF_SYN_LK BIT_POS(43, 16)
432
+#define EFUSE_DNA_WR_LK BIT_POS(43, 27)
433
+#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28)
434
+
435
+#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0)
436
+#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31)
437
+
438
+#define EFUSE_PUF_PAGE (2)
439
+#define EFUSE_PUF_SYN_START BIT_POS(129, 0)
440
+#define EFUSE_PUF_SYN_END BIT_POS(255, 27)
441
+
442
+#define EFUSE_KEY_CRC_LK_ROW (43)
443
+#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10))
444
+#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12)
445
+#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14)
446
+
447
+/*
448
+ * A handy macro to return value of an array element,
449
+ * or a specific default if given index is out of bound.
450
+ */
451
+#define ARRAY_GET(A_, I_, D_) \
452
+ ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_))
453
+
454
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs));
455
+
456
+typedef struct XlnxEFuseLkSpec {
457
+ uint16_t row;
458
+ uint16_t lk_bit;
459
+} XlnxEFuseLkSpec;
460
+
461
+static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s)
462
+{
463
+ bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR];
464
+ qemu_set_irq(s->irq_efuse_imr, pending);
465
+}
466
+
467
+static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
470
+ efuse_imr_update_irq(s);
471
+}
472
+
473
+static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
474
+{
475
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
476
+ uint32_t val = val64;
477
+
478
+ s->regs[R_EFUSE_IMR] &= ~val;
479
+ efuse_imr_update_irq(s);
480
+ return 0;
481
+}
482
+
483
+static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
484
+{
485
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
486
+ uint32_t val = val64;
487
+
488
+ s->regs[R_EFUSE_IMR] |= val;
489
+ efuse_imr_update_irq(s);
490
+ return 0;
491
+}
492
+
493
+static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s)
494
+{
495
+ uint32_t check = xlnx_efuse_tbits_check(s->efuse);
496
+ uint32_t val = s->regs[R_STATUS];
497
+
498
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
499
+ val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1)));
500
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2)));
501
+
502
+ s->regs[R_STATUS] = val;
503
+}
504
+
505
+static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s)
506
+{
507
+ unsigned page;
508
+
509
+ if (!s->efuse || !s->efuse->init_tbits) {
249
+ return;
510
+ return;
250
+ }
511
+ }
251
+
512
+
252
+ switch (offset) {
513
+ for (page = 0; page < s->efuse->efuse_nr; page++) {
253
+ case REG_VER: /* Version */
514
+ uint32_t row = 0, bit;
515
+
516
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page);
517
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW);
518
+
519
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL);
520
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
521
+ xlnx_efuse_set_bit(s->efuse, bit);
522
+ }
523
+
524
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL);
525
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
526
+ xlnx_efuse_set_bit(s->efuse, bit);
527
+ }
528
+ }
529
+}
530
+
531
+static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc,
532
+ uint32_t pass_mask, uint32_t done_mask,
533
+ unsigned first, uint32_t lk_mask)
534
+{
535
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
536
+ uint32_t r, lk_bits;
537
+
538
+ /*
539
+ * To start, assume both DONE and PASS, and clear PASS by xor
540
+ * if CRC-check fails or CRC-check disabled by lock fuse.
541
+ */
542
+ r = s->regs[R_STATUS] | done_mask | pass_mask;
543
+
544
+ lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask;
545
+ if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) {
546
+ pass_mask = 0;
547
+ }
548
+
549
+ s->regs[R_STATUS] = r ^ pass_mask;
550
+}
551
+
552
+static void efuse_data_sync(XlnxVersalEFuseCtrl *s)
553
+{
554
+ efuse_status_tbits_sync(s);
555
+}
556
+
557
+static int efuse_lk_spec_cmp(const void *a, const void *b)
558
+{
559
+ uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row;
560
+ uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row;
561
+
562
+ return (r1 > r2) - (r1 < r2);
563
+}
564
+
565
+static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s)
566
+{
567
+ XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
568
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
569
+ const uint32_t sz = sizeof(ary[0]);
570
+ const uint32_t cnt = n8 / sz;
571
+
572
+ if (ary && cnt) {
573
+ qsort(ary, cnt, sz, efuse_lk_spec_cmp);
574
+ }
575
+}
576
+
577
+static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row)
578
+{
579
+ const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
580
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
581
+ const uint32_t sz = sizeof(ary[0]);
582
+ const uint32_t cnt = n8 / sz;
583
+ const XlnxEFuseLkSpec *item = NULL;
584
+
585
+ if (ary && cnt) {
586
+ XlnxEFuseLkSpec k = { .row = row, };
587
+
588
+ item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp);
589
+ }
590
+
591
+ return item ? item->lk_bit : 0;
592
+}
593
+
594
+static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit)
595
+{
596
+ /* Hard-coded locks */
597
+ static const uint16_t pg0_hard_lock[] = {
598
+ [4] = EFUSE_GLITCH_DET_WR_LK,
599
+ [37] = EFUSE_BOOT_ENV_WR_LK,
600
+
601
+ [8 ... 11] = EFUSE_DNA_WR_LK,
602
+ [12 ... 19] = EFUSE_AES_WR_LK,
603
+ [20 ... 27] = EFUSE_USER_KEY_0_WR_LK,
604
+ [28 ... 35] = EFUSE_USER_KEY_1_WR_LK,
605
+ [64 ... 71] = EFUSE_PPK0_WR_LK,
606
+ [72 ... 79] = EFUSE_PPK1_WR_LK,
607
+ [80 ... 87] = EFUSE_PPK2_WR_LK,
608
+ };
609
+
610
+ uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW);
611
+ uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0);
612
+
613
+ return lk_bit ? lk_bit : efuse_lk_spec_find(s, row);
614
+}
615
+
616
+static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit)
617
+{
618
+
619
+ unsigned int lock = 1;
620
+
621
+ /* Global lock */
622
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
623
+ goto ret_lock;
624
+ }
625
+
626
+ /* Row lock */
627
+ switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) {
628
+ case 0:
629
+ if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) &&
630
+ bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) {
631
+ goto ret_lock;
632
+ }
633
+
634
+ lock = efuse_bit_locked(s, bit);
635
+ break;
636
+ case EFUSE_PUF_PAGE:
637
+ if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) {
638
+ lock = 0;
639
+ goto ret_lock;
640
+ }
641
+
642
+ lock = EFUSE_PUF_SYN_LK;
254
+ break;
643
+ break;
255
+ default:
644
+ default:
256
+ s->regs[idx] = (uint32_t) val;
645
+ lock = 0;
257
+ break;
646
+ goto ret_lock;
258
+ }
647
+ }
259
+}
648
+
260
+
649
+ /* Row lock by an efuse bit */
261
+static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
650
+ if (lock) {
262
+ .read = allwinner_h3_sysctrl_read,
651
+ lock = xlnx_efuse_get_bit(s->efuse, lock);
263
+ .write = allwinner_h3_sysctrl_write,
652
+ }
264
+ .endianness = DEVICE_NATIVE_ENDIAN,
653
+
654
+ ret_lock:
655
+ return lock != 0;
656
+}
657
+
658
+static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
659
+{
660
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
661
+ unsigned bit = val64;
662
+ bool ok = false;
663
+
664
+ /* Always zero out PGM_ADDR because it is write-only */
665
+ s->regs[R_EFUSE_PGM_ADDR] = 0;
666
+
667
+ /*
668
+ * Indicate error if bit is write-protected (or read-only
669
+ * as guarded by efuse_set_bit()).
670
+ *
671
+ * Keep it simple by not modeling program timing.
672
+ *
673
+ * Note: model must NEVER clear the PGM_ERROR bit; it is
674
+ * up to guest to do so (or by reset).
675
+ */
676
+ if (efuse_pgm_locked(s, bit)) {
677
+ qemu_log_mask(LOG_GUEST_ERROR,
678
+ "%s: Denied setting of efuse<%u, %u, %u>\n",
679
+ object_get_canonical_path(OBJECT(s)),
680
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE),
681
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW),
682
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN));
683
+ } else if (xlnx_efuse_set_bit(s->efuse, bit)) {
684
+ ok = true;
685
+ if (EFUSE_TBIT_POS(bit)) {
686
+ efuse_status_tbits_sync(s);
687
+ }
688
+ }
689
+
690
+ if (!ok) {
691
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
692
+ }
693
+
694
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
695
+ efuse_imr_update_irq(s);
696
+}
697
+
698
+static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
699
+{
700
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
701
+ unsigned bit = val64;
702
+ bool denied;
703
+
704
+ /* Always zero out RD_ADDR because it is write-only */
705
+ s->regs[R_EFUSE_RD_ADDR] = 0;
706
+
707
+ /*
708
+ * Indicate error if row is read-blocked.
709
+ *
710
+ * Note: model must NEVER clear the RD_ERROR bit; it is
711
+ * up to guest to do so (or by reset).
712
+ */
713
+ s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,
714
+ bit, &denied);
715
+ if (denied) {
716
+ qemu_log_mask(LOG_GUEST_ERROR,
717
+ "%s: Denied reading of efuse<%u, %u>\n",
718
+ object_get_canonical_path(OBJECT(s)),
719
+ FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE),
720
+ FIELD_EX32(bit, EFUSE_RD_ADDR, ROW));
721
+
722
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
723
+ }
724
+
725
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
726
+ efuse_imr_update_irq(s);
727
+ return;
728
+}
729
+
730
+static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64)
731
+{
732
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
733
+
734
+ if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
735
+ efuse_data_sync(s);
736
+
737
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
738
+ efuse_imr_update_irq(s);
739
+ }
740
+
741
+ return 0;
742
+}
743
+
744
+static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64)
745
+{
746
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
747
+
748
+ /* Ignore all other bits */
749
+ val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK);
750
+
751
+ /* Once the bit is written 1, only reset will clear it to 0 */
752
+ val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK);
753
+
754
+ return val64;
755
+}
756
+
757
+static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
758
+{
759
+ efuse_key_crc_check(reg, val64,
760
+ R_STATUS_AES_CRC_PASS_MASK,
761
+ R_STATUS_AES_CRC_DONE_MASK,
762
+ EFUSE_AES_KEY_START,
763
+ EFUSE_AES_KEY_CRC_LK_MASK);
764
+}
765
+
766
+static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64)
767
+{
768
+ efuse_key_crc_check(reg, val64,
769
+ R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK,
770
+ R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK,
771
+ EFUSE_USER_KEY_0_START,
772
+ EFUSE_USER_KEY_0_CRC_LK_MASK);
773
+}
774
+
775
+static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64)
776
+{
777
+ efuse_key_crc_check(reg, val64,
778
+ R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK,
779
+ R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK,
780
+ EFUSE_USER_KEY_1_START,
781
+ EFUSE_USER_KEY_1_CRC_LK_MASK);
782
+}
783
+
784
+static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
785
+{
786
+ return val != R_WR_LOCK_UNLOCK_PASSCODE;
787
+}
788
+
789
+static const RegisterAccessInfo efuse_ctrl_regs_info[] = {
790
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
791
+ .reset = 0x1,
792
+ .pre_write = efuse_wr_lock_prew,
793
+ },{ .name = "CFG", .addr = A_CFG,
794
+ .rsvd = 0x9,
795
+ },{ .name = "STATUS", .addr = A_STATUS,
796
+ .rsvd = 0x8,
797
+ .ro = 0xfff,
798
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
799
+ .post_write = efuse_pgm_addr_postw,
800
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
801
+ .rsvd = 0x1f,
802
+ .post_write = efuse_rd_addr_postw,
803
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
804
+ .ro = 0xffffffff,
805
+ },{ .name = "TPGM", .addr = A_TPGM,
806
+ },{ .name = "TRD", .addr = A_TRD,
807
+ .reset = 0x19,
808
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
809
+ .reset = 0xff,
810
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
811
+ .reset = 0x11,
812
+ },{ .name = "TRDM", .addr = A_TRDM,
813
+ .reset = 0x3a,
814
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
815
+ .reset = 0x16,
816
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
817
+ .rsvd = 0x7fff8000,
818
+ .w1c = 0x80007fff,
819
+ .post_write = efuse_isr_postw,
820
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
821
+ .reset = 0x80007fff,
822
+ .rsvd = 0x7fff8000,
823
+ .ro = 0xffffffff,
824
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
825
+ .rsvd = 0x7fff8000,
826
+ .pre_write = efuse_ier_prew,
827
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
828
+ .rsvd = 0x7fff8000,
829
+ .pre_write = efuse_idr_prew,
830
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
831
+ .pre_write = efuse_cache_load_prew,
832
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
833
+ .pre_write = efuse_pgm_lock_prew,
834
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
835
+ .post_write = efuse_aes_crc_postw,
836
+ },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC,
837
+ .post_write = efuse_aes_u0_crc_postw,
838
+ },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC,
839
+ .post_write = efuse_aes_u1_crc_postw,
840
+ },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD,
841
+ .ro = 0xfffffffe,
842
+ },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP,
843
+ },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL,
844
+ .reset = 0x8,
845
+ }
846
+};
847
+
848
+static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,
849
+ uint64_t data, unsigned size)
850
+{
851
+ RegisterInfoArray *reg_array = opaque;
852
+ XlnxVersalEFuseCtrl *s;
853
+ Object *dev;
854
+
855
+ assert(reg_array != NULL);
856
+
857
+ dev = reg_array->mem.owner;
858
+ assert(dev);
859
+
860
+ s = XLNX_VERSAL_EFUSE_CTRL(dev);
861
+
862
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
863
+ qemu_log_mask(LOG_GUEST_ERROR,
864
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
865
+ object_get_canonical_path(OBJECT(s)), (long)addr);
866
+ } else {
867
+ register_write_memory(opaque, addr, data, size);
868
+ }
869
+}
870
+
871
+static void efuse_ctrl_register_reset(RegisterInfo *reg)
872
+{
873
+ if (!reg->data || !reg->access) {
874
+ return;
875
+ }
876
+
877
+ /* Reset must not trigger some registers' writers */
878
+ switch (reg->access->addr) {
879
+ case A_EFUSE_AES_CRC:
880
+ case A_EFUSE_AES_USR_KEY0_CRC:
881
+ case A_EFUSE_AES_USR_KEY1_CRC:
882
+ *(uint32_t *)reg->data = reg->access->reset;
883
+ return;
884
+ }
885
+
886
+ register_reset(reg);
887
+}
888
+
889
+static void efuse_ctrl_reset(DeviceState *dev)
890
+{
891
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
892
+ unsigned int i;
893
+
894
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
895
+ efuse_ctrl_register_reset(&s->regs_info[i]);
896
+ }
897
+
898
+ efuse_anchor_bits_check(s);
899
+ efuse_data_sync(s);
900
+ efuse_imr_update_irq(s);
901
+}
902
+
903
+static const MemoryRegionOps efuse_ctrl_ops = {
904
+ .read = register_read_memory,
905
+ .write = efuse_ctrl_reg_write,
906
+ .endianness = DEVICE_LITTLE_ENDIAN,
265
+ .valid = {
907
+ .valid = {
266
+ .min_access_size = 4,
908
+ .min_access_size = 4,
267
+ .max_access_size = 4,
909
+ .max_access_size = 4,
268
+ },
910
+ },
269
+ .impl.min_access_size = 4,
270
+};
911
+};
271
+
912
+
272
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
913
+static void efuse_ctrl_realize(DeviceState *dev, Error **errp)
273
+{
914
+{
274
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
915
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
275
+
916
+ const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2;
276
+ /* Set default values for registers */
917
+
277
+ s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
918
+ if (!s->efuse) {
278
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
919
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
279
+}
920
+ object_get_canonical_path(OBJECT(dev)));
280
+
921
+ return;
281
+static void allwinner_h3_sysctrl_init(Object *obj)
922
+ }
282
+{
923
+
924
+ /* Sort property-defined pgm-locks for bsearch lookup */
925
+ if ((s->extra_pg0_lock_n16 % lks_sz) != 0) {
926
+ error_setg(errp,
927
+ "%s.pg0-lock: array property item-count not multiple of %u",
928
+ object_get_canonical_path(OBJECT(dev)), lks_sz);
929
+ return;
930
+ }
931
+
932
+ efuse_lk_spec_sort(s);
933
+}
934
+
935
+static void efuse_ctrl_init(Object *obj)
936
+{
937
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
283
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
938
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
284
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
939
+ RegisterInfoArray *reg_array;
285
+
940
+
286
+ /* Memory mapping */
941
+ reg_array =
287
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
942
+ register_init_block32(DEVICE(obj), efuse_ctrl_regs_info,
288
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
943
+ ARRAY_SIZE(efuse_ctrl_regs_info),
289
+ sysbus_init_mmio(sbd, &s->iomem);
944
+ s->regs_info, s->regs,
290
+}
945
+ &efuse_ctrl_ops,
291
+
946
+ XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG,
292
+static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
947
+ R_MAX * 4);
293
+ .name = "allwinner-h3-sysctrl",
948
+
949
+ sysbus_init_mmio(sbd, &reg_array->mem);
950
+ sysbus_init_irq(sbd, &s->irq_efuse_imr);
951
+}
952
+
953
+static const VMStateDescription vmstate_efuse_ctrl = {
954
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
294
+ .version_id = 1,
955
+ .version_id = 1,
295
+ .minimum_version_id = 1,
956
+ .minimum_version_id = 1,
296
+ .fields = (VMStateField[]) {
957
+ .fields = (VMStateField[]) {
297
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
958
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX),
298
+ VMSTATE_END_OF_LIST()
959
+ VMSTATE_END_OF_LIST(),
299
+ }
960
+ }
300
+};
961
+};
301
+
962
+
302
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
963
+static Property efuse_ctrl_props[] = {
964
+ DEFINE_PROP_LINK("efuse",
965
+ XlnxVersalEFuseCtrl, efuse,
966
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
967
+ DEFINE_PROP_ARRAY("pg0-lock",
968
+ XlnxVersalEFuseCtrl, extra_pg0_lock_n16,
969
+ extra_pg0_lock_spec, qdev_prop_uint16, uint16_t),
970
+
971
+ DEFINE_PROP_END_OF_LIST(),
972
+};
973
+
974
+static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
303
+{
975
+{
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
976
+ DeviceClass *dc = DEVICE_CLASS(klass);
305
+
977
+
306
+ dc->reset = allwinner_h3_sysctrl_reset;
978
+ dc->reset = efuse_ctrl_reset;
307
+ dc->vmsd = &allwinner_h3_sysctrl_vmstate;
979
+ dc->realize = efuse_ctrl_realize;
308
+}
980
+ dc->vmsd = &vmstate_efuse_ctrl;
309
+
981
+ device_class_set_props(dc, efuse_ctrl_props);
310
+static const TypeInfo allwinner_h3_sysctrl_info = {
982
+}
311
+ .name = TYPE_AW_H3_SYSCTRL,
983
+
984
+static const TypeInfo efuse_ctrl_info = {
985
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
312
+ .parent = TYPE_SYS_BUS_DEVICE,
986
+ .parent = TYPE_SYS_BUS_DEVICE,
313
+ .instance_init = allwinner_h3_sysctrl_init,
987
+ .instance_size = sizeof(XlnxVersalEFuseCtrl),
314
+ .instance_size = sizeof(AwH3SysCtrlState),
988
+ .class_init = efuse_ctrl_class_init,
315
+ .class_init = allwinner_h3_sysctrl_class_init,
989
+ .instance_init = efuse_ctrl_init,
316
+};
990
+};
317
+
991
+
318
+static void allwinner_h3_sysctrl_register(void)
992
+static void efuse_ctrl_register_types(void)
319
+{
993
+{
320
+ type_register_static(&allwinner_h3_sysctrl_info);
994
+ type_register_static(&efuse_ctrl_info);
321
+}
995
+}
322
+
996
+
323
+type_init(allwinner_h3_sysctrl_register)
997
+type_init(efuse_ctrl_register_types)
998
+
999
+/*
1000
+ * Retrieve a row, with unreadable bits returned as 0.
1001
+ */
1002
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *efuse,
1003
+ uint32_t bit, bool *denied)
1004
+{
1005
+ bool dummy;
1006
+
1007
+ if (!denied) {
1008
+ denied = &dummy;
1009
+ }
1010
+
1011
+ if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) {
1012
+ *denied = true;
1013
+ return 0;
1014
+ }
1015
+
1016
+ *denied = false;
1017
+ return xlnx_efuse_get_row(efuse, bit);
1018
+}
1019
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
1020
index XXXXXXX..XXXXXXX 100644
1021
--- a/hw/nvram/Kconfig
1022
+++ b/hw/nvram/Kconfig
1023
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_CRC
1024
config XLNX_EFUSE
1025
bool
1026
select XLNX_EFUSE_CRC
1027
+
1028
+config XLNX_EFUSE_VERSAL
1029
+ bool
1030
+ select XLNX_EFUSE
1031
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
1032
index XXXXXXX..XXXXXXX 100644
1033
--- a/hw/nvram/meson.build
1034
+++ b/hw/nvram/meson.build
1035
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
1036
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
1037
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
1038
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
1039
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
1040
+ 'xlnx-versal-efuse-cache.c',
1041
+ 'xlnx-versal-efuse-ctrl.c'))
1042
1043
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
324
--
1044
--
325
2.20.1
1045
2.20.1
326
1046
327
1047
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
Various Allwinner System on Chip designs contain multiple processors
3
This implements the Xilinx ZynqMP eFuse, an one-time
4
that can be configured and reset using the generic CPU Configuration
4
field-programmable non-volatile storage device. There is
5
module interface. This commit adds support for the Allwinner CPU
5
only one such device in the Xilinx ZynqMP product family.
6
configuration interface which emulates the following features:
7
6
8
* CPU reset
7
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
* CPU status
8
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
10
9
11
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
13
Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com
12
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
13
Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
---
16
hw/misc/Makefile.objs | 1 +
17
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
17
include/hw/arm/allwinner-h3.h | 3 +
18
hw/nvram/xlnx-zynqmp-efuse.c | 855 +++++++++++++++++++++++++++
18
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
19
hw/nvram/Kconfig | 4 +
19
hw/arm/allwinner-h3.c | 9 +-
20
hw/nvram/meson.build | 2 +
20
hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++
21
4 files changed, 905 insertions(+)
21
hw/misc/trace-events | 5 +
22
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
22
6 files changed, 351 insertions(+), 1 deletion(-)
23
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
23
create mode 100644 include/hw/misc/allwinner-cpucfg.h
24
create mode 100644 hw/misc/allwinner-cpucfg.c
25
24
26
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
25
diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/misc/Makefile.objs
29
+++ b/hw/misc/Makefile.objs
30
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
31
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
32
33
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
37
common-obj-$(CONFIG_NSERIES) += cbus.o
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/allwinner-h3.h
41
+++ b/include/hw/arm/allwinner-h3.h
42
@@ -XXX,XX +XXX,XX @@
43
#include "hw/timer/allwinner-a10-pit.h"
44
#include "hw/intc/arm_gic.h"
45
#include "hw/misc/allwinner-h3-ccu.h"
46
+#include "hw/misc/allwinner-cpucfg.h"
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "target/arm/cpu.h"
49
50
@@ -XXX,XX +XXX,XX @@ enum {
51
AW_H3_GIC_CPU,
52
AW_H3_GIC_HYP,
53
AW_H3_GIC_VCPU,
54
+ AW_H3_CPUCFG,
55
AW_H3_SDRAM
56
};
57
58
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
59
const hwaddr *memmap;
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
+ AwCpuCfgState cpucfg;
63
AwH3SysCtrlState sysctrl;
64
GICState gic;
65
MemoryRegion sram_a1;
66
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h
67
new file mode 100644
26
new file mode 100644
68
index XXXXXXX..XXXXXXX
27
index XXXXXXX..XXXXXXX
69
--- /dev/null
28
--- /dev/null
70
+++ b/include/hw/misc/allwinner-cpucfg.h
29
+++ b/include/hw/nvram/xlnx-zynqmp-efuse.h
71
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@
72
+/*
31
+/*
73
+ * Allwinner CPU Configuration Module emulation
32
+ * Copyright (c) 2021 Xilinx Inc.
74
+ *
33
+ *
75
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
34
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
35
+ * of this software and associated documentation files (the "Software"), to deal
36
+ * in the Software without restriction, including without limitation the rights
37
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38
+ * copies of the Software, and to permit persons to whom the Software is
39
+ * furnished to do so, subject to the following conditions:
76
+ *
40
+ *
77
+ * This program is free software: you can redistribute it and/or modify
41
+ * The above copyright notice and this permission notice shall be included in
78
+ * it under the terms of the GNU General Public License as published by
42
+ * all copies or substantial portions of the Software.
79
+ * the Free Software Foundation, either version 2 of the License, or
80
+ * (at your option) any later version.
81
+ *
43
+ *
82
+ * This program is distributed in the hope that it will be useful,
44
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
83
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
45
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
84
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
85
+ * GNU General Public License for more details.
47
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
86
+ *
48
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
87
+ * You should have received a copy of the GNU General Public License
49
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
88
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
50
+ * THE SOFTWARE.
89
+ */
51
+ */
90
+
52
+#ifndef XLNX_ZYNQMP_EFUSE_H
91
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
53
+#define XLNX_ZYNQMP_EFUSE_H
92
+#define HW_MISC_ALLWINNER_CPUCFG_H
54
+
93
+
55
+#include "hw/irq.h"
94
+#include "qom/object.h"
95
+#include "hw/sysbus.h"
56
+#include "hw/sysbus.h"
96
+
57
+#include "hw/register.h"
97
+/**
58
+#include "hw/nvram/xlnx-efuse.h"
98
+ * Object model
59
+
99
+ * @{
60
+#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1)
100
+ */
61
+
101
+
62
+#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse"
102
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
63
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE);
103
+#define AW_CPUCFG(obj) \
64
+
104
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
65
+struct XlnxZynqMPEFuse {
105
+
106
+/** @} */
107
+
108
+/**
109
+ * Allwinner CPU Configuration Module instance state
110
+ */
111
+typedef struct AwCpuCfgState {
112
+ /*< private >*/
113
+ SysBusDevice parent_obj;
66
+ SysBusDevice parent_obj;
114
+ /*< public >*/
67
+ qemu_irq irq;
115
+
68
+
116
+ MemoryRegion iomem;
69
+ XlnxEFuse *efuse;
117
+ uint32_t gen_ctrl;
70
+ uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX];
118
+ uint32_t super_standby;
71
+ RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX];
119
+ uint32_t entry_addr;
72
+};
120
+
73
+
121
+} AwCpuCfgState;
74
+#endif
122
+
75
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
123
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
124
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/arm/allwinner-h3.c
127
+++ b/hw/arm/allwinner-h3.c
128
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
129
[AW_H3_GIC_CPU] = 0x01c82000,
130
[AW_H3_GIC_HYP] = 0x01c84000,
131
[AW_H3_GIC_VCPU] = 0x01c86000,
132
+ [AW_H3_CPUCFG] = 0x01f01c00,
133
[AW_H3_SDRAM] = 0x40000000
134
};
135
136
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
137
{ "r_wdog", 0x01f01000, 1 * KiB },
138
{ "r_prcm", 0x01f01400, 1 * KiB },
139
{ "r_twd", 0x01f01800, 1 * KiB },
140
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
141
{ "r_cir-rx", 0x01f02000, 1 * KiB },
142
{ "r_twi", 0x01f02400, 1 * KiB },
143
{ "r_uart", 0x01f02800, 1 * KiB },
144
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
145
146
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
147
TYPE_AW_H3_SYSCTRL);
148
+
149
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
150
+ TYPE_AW_CPUCFG);
151
}
152
153
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
154
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
155
qdev_init_nofail(DEVICE(&s->sysctrl));
156
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
157
158
+ /* CPU Configuration */
159
+ qdev_init_nofail(DEVICE(&s->cpucfg));
160
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
161
+
162
/* Universal Serial Bus */
163
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
164
qdev_get_gpio_in(DEVICE(&s->gic),
165
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
166
new file mode 100644
76
new file mode 100644
167
index XXXXXXX..XXXXXXX
77
index XXXXXXX..XXXXXXX
168
--- /dev/null
78
--- /dev/null
169
+++ b/hw/misc/allwinner-cpucfg.c
79
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
170
@@ -XXX,XX +XXX,XX @@
80
@@ -XXX,XX +XXX,XX @@
171
+/*
81
+/*
172
+ * Allwinner CPU Configuration Module emulation
82
+ * QEMU model of the ZynqMP eFuse
173
+ *
83
+ *
174
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
84
+ * Copyright (c) 2015 Xilinx Inc.
175
+ *
85
+ *
176
+ * This program is free software: you can redistribute it and/or modify
86
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
177
+ * it under the terms of the GNU General Public License as published by
178
+ * the Free Software Foundation, either version 2 of the License, or
179
+ * (at your option) any later version.
180
+ *
87
+ *
181
+ * This program is distributed in the hope that it will be useful,
88
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
182
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
89
+ * of this software and associated documentation files (the "Software"), to deal
183
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
90
+ * in the Software without restriction, including without limitation the rights
184
+ * GNU General Public License for more details.
91
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
92
+ * copies of the Software, and to permit persons to whom the Software is
93
+ * furnished to do so, subject to the following conditions:
185
+ *
94
+ *
186
+ * You should have received a copy of the GNU General Public License
95
+ * The above copyright notice and this permission notice shall be included in
187
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
96
+ * all copies or substantial portions of the Software.
97
+ *
98
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
99
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
100
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
101
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
102
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
103
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
104
+ * THE SOFTWARE.
188
+ */
105
+ */
189
+
106
+
190
+#include "qemu/osdep.h"
107
+#include "qemu/osdep.h"
191
+#include "qemu/units.h"
108
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
192
+#include "hw/sysbus.h"
109
+
110
+#include "qemu/log.h"
111
+#include "qapi/error.h"
193
+#include "migration/vmstate.h"
112
+#include "migration/vmstate.h"
194
+#include "qemu/log.h"
113
+#include "hw/qdev-properties.h"
195
+#include "qemu/module.h"
114
+
196
+#include "qemu/error-report.h"
115
+#ifndef ZYNQMP_EFUSE_ERR_DEBUG
197
+#include "qemu/timer.h"
116
+#define ZYNQMP_EFUSE_ERR_DEBUG 0
198
+#include "hw/core/cpu.h"
117
+#endif
199
+#include "target/arm/arm-powerctl.h"
118
+
200
+#include "target/arm/cpu.h"
119
+REG32(WR_LOCK, 0x0)
201
+#include "hw/misc/allwinner-cpucfg.h"
120
+ FIELD(WR_LOCK, LOCK, 0, 16)
202
+#include "trace.h"
121
+REG32(CFG, 0x4)
203
+
122
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
204
+/* CPUCFG register offsets */
123
+ FIELD(CFG, MARGIN_RD, 2, 2)
205
+enum {
124
+ FIELD(CFG, PGM_EN, 1, 1)
206
+ REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
125
+ FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
207
+ REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
126
+REG32(STATUS, 0x8)
208
+ REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
127
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
209
+ REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
128
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
210
+ REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
129
+ FIELD(STATUS, CACHE_DONE, 5, 1)
211
+ REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
130
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
212
+ REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
131
+ FIELD(STATUS, EFUSE_3_TBIT, 2, 1)
213
+ REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
132
+ FIELD(STATUS, EFUSE_2_TBIT, 1, 1)
214
+ REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
133
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
215
+ REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
134
+REG32(EFUSE_PGM_ADDR, 0xc)
216
+ REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
135
+ FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
217
+ REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
136
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 6)
218
+ REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
137
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
219
+ REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
138
+REG32(EFUSE_RD_ADDR, 0x10)
220
+ REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
139
+ FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
221
+ REG_GEN_CTRL = 0x0184, /* General Control */
140
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 6)
222
+ REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */
141
+REG32(EFUSE_RD_DATA, 0x14)
223
+ REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */
142
+REG32(TPGM, 0x18)
224
+ REG_DBG_EXTERN = 0x01E4, /* Debug External */
143
+ FIELD(TPGM, VALUE, 0, 16)
225
+ REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
144
+REG32(TRD, 0x1c)
226
+ REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
145
+ FIELD(TRD, VALUE, 0, 8)
227
+ REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
146
+REG32(TSU_H_PS, 0x20)
228
+};
147
+ FIELD(TSU_H_PS, VALUE, 0, 8)
229
+
148
+REG32(TSU_H_PS_CS, 0x24)
230
+/* CPUCFG register flags */
149
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
231
+enum {
150
+REG32(TSU_H_CS, 0x2c)
232
+ CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)),
151
+ FIELD(TSU_H_CS, VALUE, 0, 4)
233
+ CPUX_STATUS_SMP = (1 << 0),
152
+REG32(EFUSE_ISR, 0x30)
234
+ CPU_SYS_RESET_RELEASED = (1 << 0),
153
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
235
+ CLK_GATING_ENABLE = ((1 << 8) | 0xF),
154
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
236
+};
155
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
237
+
156
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
238
+/* CPUCFG register reset values */
157
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
239
+enum {
158
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
240
+ REG_CLK_GATING_RST = 0x0000010F,
159
+REG32(EFUSE_IMR, 0x34)
241
+ REG_GEN_CTRL_RST = 0x00000020,
160
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
242
+ REG_SUPER_STANDBY_RST = 0x0,
161
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
243
+ REG_CNT64_CTRL_RST = 0x0,
162
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
244
+};
163
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
245
+
164
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
246
+/* CPUCFG constants */
165
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
247
+enum {
166
+REG32(EFUSE_IER, 0x38)
248
+ CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
167
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
249
+};
168
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
250
+
169
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
251
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
170
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
252
+{
171
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
253
+ int ret;
172
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
254
+
173
+REG32(EFUSE_IDR, 0x3c)
255
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
174
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
256
+
175
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
257
+ ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
176
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
258
+ if (!target_cpu) {
177
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
259
+ /*
178
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
260
+ * Called with a bogus value for cpu_id. Guest error will
179
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
261
+ * already have been logged, we can simply return here.
180
+REG32(EFUSE_CACHE_LOAD, 0x40)
262
+ */
181
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
182
+REG32(EFUSE_PGM_LOCK, 0x44)
183
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
184
+REG32(EFUSE_AES_CRC, 0x48)
185
+REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
186
+ FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1)
187
+REG32(DNA_0, 0x100c)
188
+REG32(DNA_1, 0x1010)
189
+REG32(DNA_2, 0x1014)
190
+REG32(IPDISABLE, 0x1018)
191
+ FIELD(IPDISABLE, VCU_DIS, 8, 1)
192
+ FIELD(IPDISABLE, GPU_DIS, 5, 1)
193
+ FIELD(IPDISABLE, APU3_DIS, 3, 1)
194
+ FIELD(IPDISABLE, APU2_DIS, 2, 1)
195
+ FIELD(IPDISABLE, APU1_DIS, 1, 1)
196
+ FIELD(IPDISABLE, APU0_DIS, 0, 1)
197
+REG32(SYSOSC_CTRL, 0x101c)
198
+ FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
199
+REG32(USER_0, 0x1020)
200
+REG32(USER_1, 0x1024)
201
+REG32(USER_2, 0x1028)
202
+REG32(USER_3, 0x102c)
203
+REG32(USER_4, 0x1030)
204
+REG32(USER_5, 0x1034)
205
+REG32(USER_6, 0x1038)
206
+REG32(USER_7, 0x103c)
207
+REG32(MISC_USER_CTRL, 0x1040)
208
+ FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1)
209
+ FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1)
210
+ FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1)
211
+ FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1)
212
+ FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1)
213
+ FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1)
214
+ FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1)
215
+ FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1)
216
+ FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1)
217
+ FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1)
218
+ FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
219
+REG32(ROM_RSVD, 0x1044)
220
+ FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
221
+REG32(PUF_CHASH, 0x1050)
222
+REG32(PUF_MISC, 0x1054)
223
+ FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
224
+ FIELD(PUF_MISC, SYN_WRLK, 30, 1)
225
+ FIELD(PUF_MISC, SYN_INVLD, 29, 1)
226
+ FIELD(PUF_MISC, TEST2_DIS, 28, 1)
227
+ FIELD(PUF_MISC, UNUSED27, 27, 1)
228
+ FIELD(PUF_MISC, UNUSED26, 26, 1)
229
+ FIELD(PUF_MISC, UNUSED25, 25, 1)
230
+ FIELD(PUF_MISC, UNUSED24, 24, 1)
231
+ FIELD(PUF_MISC, AUX, 0, 24)
232
+REG32(SEC_CTRL, 0x1058)
233
+ FIELD(SEC_CTRL, PPK1_INVLD, 30, 2)
234
+ FIELD(SEC_CTRL, PPK1_WRLK, 29, 1)
235
+ FIELD(SEC_CTRL, PPK0_INVLD, 27, 2)
236
+ FIELD(SEC_CTRL, PPK0_WRLK, 26, 1)
237
+ FIELD(SEC_CTRL, RSA_EN, 11, 15)
238
+ FIELD(SEC_CTRL, SEC_LOCK, 10, 1)
239
+ FIELD(SEC_CTRL, PROG_GATE_2, 9, 1)
240
+ FIELD(SEC_CTRL, PROG_GATE_1, 8, 1)
241
+ FIELD(SEC_CTRL, PROG_GATE_0, 7, 1)
242
+ FIELD(SEC_CTRL, DFT_DIS, 6, 1)
243
+ FIELD(SEC_CTRL, JTAG_DIS, 5, 1)
244
+ FIELD(SEC_CTRL, ERROR_DIS, 4, 1)
245
+ FIELD(SEC_CTRL, BBRAM_DIS, 3, 1)
246
+ FIELD(SEC_CTRL, ENC_ONLY, 2, 1)
247
+ FIELD(SEC_CTRL, AES_WRLK, 1, 1)
248
+ FIELD(SEC_CTRL, AES_RDLK, 0, 1)
249
+REG32(SPK_ID, 0x105c)
250
+REG32(PPK0_0, 0x10a0)
251
+REG32(PPK0_1, 0x10a4)
252
+REG32(PPK0_2, 0x10a8)
253
+REG32(PPK0_3, 0x10ac)
254
+REG32(PPK0_4, 0x10b0)
255
+REG32(PPK0_5, 0x10b4)
256
+REG32(PPK0_6, 0x10b8)
257
+REG32(PPK0_7, 0x10bc)
258
+REG32(PPK0_8, 0x10c0)
259
+REG32(PPK0_9, 0x10c4)
260
+REG32(PPK0_10, 0x10c8)
261
+REG32(PPK0_11, 0x10cc)
262
+REG32(PPK1_0, 0x10d0)
263
+REG32(PPK1_1, 0x10d4)
264
+REG32(PPK1_2, 0x10d8)
265
+REG32(PPK1_3, 0x10dc)
266
+REG32(PPK1_4, 0x10e0)
267
+REG32(PPK1_5, 0x10e4)
268
+REG32(PPK1_6, 0x10e8)
269
+REG32(PPK1_7, 0x10ec)
270
+REG32(PPK1_8, 0x10f0)
271
+REG32(PPK1_9, 0x10f4)
272
+REG32(PPK1_10, 0x10f8)
273
+REG32(PPK1_11, 0x10fc)
274
+
275
+#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN)
276
+#define R_MAX (R_PPK1_11 + 1)
277
+
278
+/* #define EFUSE_XOSC 26 */
279
+
280
+/*
281
+ * eFUSE layout references:
282
+ * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
283
+ */
284
+#define EFUSE_AES_RDLK BIT_POS(22, 0)
285
+#define EFUSE_AES_WRLK BIT_POS(22, 1)
286
+#define EFUSE_ENC_ONLY BIT_POS(22, 2)
287
+#define EFUSE_BBRAM_DIS BIT_POS(22, 3)
288
+#define EFUSE_ERROR_DIS BIT_POS(22, 4)
289
+#define EFUSE_JTAG_DIS BIT_POS(22, 5)
290
+#define EFUSE_DFT_DIS BIT_POS(22, 6)
291
+#define EFUSE_PROG_GATE_0 BIT_POS(22, 7)
292
+#define EFUSE_PROG_GATE_1 BIT_POS(22, 7)
293
+#define EFUSE_PROG_GATE_2 BIT_POS(22, 9)
294
+#define EFUSE_SEC_LOCK BIT_POS(22, 10)
295
+#define EFUSE_RSA_EN BIT_POS(22, 11)
296
+#define EFUSE_RSA_EN14 BIT_POS(22, 25)
297
+#define EFUSE_PPK0_WRLK BIT_POS(22, 26)
298
+#define EFUSE_PPK0_INVLD BIT_POS(22, 27)
299
+#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28)
300
+#define EFUSE_PPK1_WRLK BIT_POS(22, 29)
301
+#define EFUSE_PPK1_INVLD BIT_POS(22, 30)
302
+#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
303
+
304
+/* Areas. */
305
+#define EFUSE_TRIM_START BIT_POS(1, 0)
306
+#define EFUSE_TRIM_END BIT_POS(1, 30)
307
+#define EFUSE_DNA_START BIT_POS(3, 0)
308
+#define EFUSE_DNA_END BIT_POS(5, 31)
309
+#define EFUSE_AES_START BIT_POS(24, 0)
310
+#define EFUSE_AES_END BIT_POS(31, 31)
311
+#define EFUSE_ROM_START BIT_POS(17, 0)
312
+#define EFUSE_ROM_END BIT_POS(17, 31)
313
+#define EFUSE_IPDIS_START BIT_POS(6, 0)
314
+#define EFUSE_IPDIS_END BIT_POS(6, 31)
315
+#define EFUSE_USER_START BIT_POS(8, 0)
316
+#define EFUSE_USER_END BIT_POS(15, 31)
317
+#define EFUSE_BISR_START BIT_POS(32, 0)
318
+#define EFUSE_BISR_END BIT_POS(39, 31)
319
+
320
+#define EFUSE_USER_CTRL_START BIT_POS(16, 0)
321
+#define EFUSE_USER_CTRL_END BIT_POS(16, 16)
322
+#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
323
+
324
+#define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
325
+#define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
326
+#define EFUSE_PUF_MISC_START BIT_POS(21, 0)
327
+#define EFUSE_PUF_MISC_END BIT_POS(21, 31)
328
+#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30)
329
+
330
+#define EFUSE_SPK_START BIT_POS(23, 0)
331
+#define EFUSE_SPK_END BIT_POS(23, 31)
332
+
333
+#define EFUSE_PPK0_START BIT_POS(40, 0)
334
+#define EFUSE_PPK0_END BIT_POS(51, 31)
335
+#define EFUSE_PPK1_START BIT_POS(52, 0)
336
+#define EFUSE_PPK1_END BIT_POS(63, 31)
337
+
338
+#define EFUSE_CACHE_FLD(s, reg, field) \
339
+ ARRAY_FIELD_DP32((s)->regs, reg, field, \
340
+ (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
341
+ >> (EFUSE_ ## field % 32)))
342
+
343
+#define EFUSE_CACHE_BIT(s, reg, field) \
344
+ ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
345
+ EFUSE_ ## field))
346
+
347
+#define FBIT_UNKNOWN (~0)
348
+
349
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
350
+
351
+static void update_tbit_status(XlnxZynqMPEFuse *s)
352
+{
353
+ unsigned int check = xlnx_efuse_tbits_check(s->efuse);
354
+ uint32_t val = s->regs[R_STATUS];
355
+
356
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
357
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1)));
358
+ val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2)));
359
+
360
+ s->regs[R_STATUS] = val;
361
+}
362
+
363
+/* Update the u32 array from efuse bits. Slow but simple approach. */
364
+static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start,
365
+ unsigned int f_start, unsigned int f_end,
366
+ unsigned int f_written)
367
+{
368
+ uint32_t *u32 = &s->regs[r_start];
369
+ unsigned int fbit, wbits = 0, u32_off = 0;
370
+
371
+ /* Avoid working on bits that are not relevant. */
372
+ if (f_written != FBIT_UNKNOWN
373
+ && (f_written < f_start || f_written > f_end)) {
263
+ return;
374
+ return;
264
+ }
375
+ }
265
+ bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
376
+
266
+
377
+ for (fbit = f_start; fbit <= f_end; fbit++, wbits++) {
267
+ ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
378
+ if (wbits == 32) {
268
+ CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64);
379
+ /* Update the key offset. */
269
+ if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
380
+ u32_off += 1;
270
+ error_report("%s: failed to bring up CPU %d: err %d",
381
+ wbits = 0;
271
+ __func__, cpu_id, ret);
382
+ }
383
+ u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits;
384
+ }
385
+}
386
+
387
+/*
388
+ * Keep the syncs in bit order so we can bail out for the
389
+ * slower ones.
390
+ */
391
+static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit)
392
+{
393
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK);
394
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK);
395
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY);
396
+ EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS);
397
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS);
398
+ EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS);
399
+ EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS);
400
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0);
401
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1);
402
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2);
403
+ EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK);
404
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK);
405
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK);
406
+
407
+ EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN);
408
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD);
409
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD);
410
+
411
+ /* Update the tbits. */
412
+ update_tbit_status(s);
413
+
414
+ /* Sync the various areas. */
415
+ s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse,
416
+ EFUSE_USER_CTRL_START)
417
+ & EFUSE_USER_CTRL_MASK;
418
+ s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START);
419
+ s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START);
420
+
421
+ cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit);
422
+
423
+ if (bit < EFUSE_AES_START) {
272
+ return;
424
+ return;
273
+ }
425
+ }
274
+}
426
+
275
+
427
+ cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit);
276
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
428
+ cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit);
277
+ unsigned size)
429
+ cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit);
278
+{
430
+ cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit);
279
+ const AwCpuCfgState *s = AW_CPUCFG(opaque);
431
+ cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit);
280
+ uint64_t val = 0;
432
+ cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit);
281
+
433
+}
282
+ switch (offset) {
434
+
283
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
435
+static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s)
284
+ case REG_CPU_SYS_RST: /* CPU System Reset */
436
+{
285
+ val = CPU_SYS_RESET_RELEASED;
437
+ bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR];
438
+ qemu_set_irq(s->irq, pending);
439
+}
440
+
441
+static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
442
+{
443
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
444
+ zynqmp_efuse_update_irq(s);
445
+}
446
+
447
+static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
448
+{
449
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
450
+ uint32_t val = val64;
451
+
452
+ s->regs[R_EFUSE_IMR] |= val;
453
+ zynqmp_efuse_update_irq(s);
454
+ return 0;
455
+}
456
+
457
+static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
458
+{
459
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
460
+ uint32_t val = val64;
461
+
462
+ s->regs[R_EFUSE_IMR] &= ~val;
463
+ zynqmp_efuse_update_irq(s);
464
+ return 0;
465
+}
466
+
467
+static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
470
+ unsigned bit = val64;
471
+ unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE);
472
+ bool puf_prot = false;
473
+ const char *errmsg = NULL;
474
+
475
+ /* Allow only valid array, and adjust for skipped array 1 */
476
+ switch (page) {
477
+ case 0:
286
+ break;
478
+ break;
287
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
479
+ case 2 ... 3:
288
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
480
+ bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1);
289
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
481
+ puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK);
290
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
291
+ val = CPUX_RESET_RELEASED;
292
+ break;
293
+ case REG_CPU0_CTRL: /* CPU#0 Control */
294
+ case REG_CPU1_CTRL: /* CPU#1 Control */
295
+ case REG_CPU2_CTRL: /* CPU#2 Control */
296
+ case REG_CPU3_CTRL: /* CPU#3 Control */
297
+ val = 0;
298
+ break;
299
+ case REG_CPU0_STATUS: /* CPU#0 Status */
300
+ case REG_CPU1_STATUS: /* CPU#1 Status */
301
+ case REG_CPU2_STATUS: /* CPU#2 Status */
302
+ case REG_CPU3_STATUS: /* CPU#3 Status */
303
+ val = CPUX_STATUS_SMP;
304
+ break;
305
+ case REG_CLK_GATING: /* CPU Clock Gating */
306
+ val = CLK_GATING_ENABLE;
307
+ break;
308
+ case REG_GEN_CTRL: /* General Control */
309
+ val = s->gen_ctrl;
310
+ break;
311
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
312
+ val = s->super_standby;
313
+ break;
314
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
315
+ val = s->entry_addr;
316
+ break;
317
+ case REG_DBG_EXTERN: /* Debug External */
318
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
319
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
320
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
321
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
322
+ __func__, (uint32_t)offset);
323
+ break;
482
+ break;
324
+ default:
483
+ default:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
484
+ errmsg = "Invalid address";
326
+ __func__, (uint32_t)offset);
485
+ goto pgm_done;
327
+ break;
486
+ }
328
+ }
487
+
329
+
488
+ if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) {
330
+ trace_allwinner_cpucfg_read(offset, val, size);
489
+ errmsg = "Array write-locked";
331
+
490
+ goto pgm_done;
332
+ return val;
491
+ }
333
+}
492
+
334
+
493
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
335
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
494
+ errmsg = "Array pgm-disabled";
336
+ uint64_t val, unsigned size)
495
+ goto pgm_done;
337
+{
496
+ }
338
+ AwCpuCfgState *s = AW_CPUCFG(opaque);
497
+
339
+
498
+ if (puf_prot) {
340
+ trace_allwinner_cpucfg_write(offset, val, size);
499
+ errmsg = "PUF_HD-store write-locked";
341
+
500
+ goto pgm_done;
342
+ switch (offset) {
501
+ }
343
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
502
+
344
+ case REG_CPU_SYS_RST: /* CPU System Reset */
503
+ if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK)
345
+ break;
504
+ && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) {
346
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
505
+ errmsg = "AES key-store Write-locked";
347
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
506
+ goto pgm_done;
348
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
507
+ }
349
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
508
+
350
+ if (val) {
509
+ if (!xlnx_efuse_set_bit(s->efuse, bit)) {
351
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6);
510
+ errmsg = "Write failed";
511
+ }
512
+
513
+ pgm_done:
514
+ if (!errmsg) {
515
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
516
+ } else {
517
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
518
+ qemu_log_mask(LOG_GUEST_ERROR,
519
+ "%s - eFuse write error: %s; addr=0x%x\n",
520
+ object_get_canonical_path(OBJECT(s)),
521
+ errmsg, (unsigned)val64);
522
+ }
523
+
524
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
525
+ zynqmp_efuse_update_irq(s);
526
+}
527
+
528
+static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
529
+{
530
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
531
+
532
+ /*
533
+ * Grant reads only to allowed bits; reference sources:
534
+ * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow()
535
+ * 2/ UG1085, v2.0, table 12-13
536
+ * (note: enumerates the masks as <first, last> per described in
537
+ * references to avoid mental translation).
538
+ */
539
+#define COL_MASK(L_, H_) \
540
+ ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_))))
541
+
542
+ static const uint32_t ary0_col_mask[] = {
543
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */
544
+ [0] = COL_MASK(28, 31),
545
+
546
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */
547
+ [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31),
548
+ [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31),
549
+ [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31),
550
+ [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31),
551
+
552
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */
553
+ [16] = COL_MASK(0, 7) | COL_MASK(10, 16),
554
+
555
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */
556
+ [17] = COL_MASK(0, 2),
557
+
558
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */
559
+ [20] = COL_MASK(0, 31),
560
+
561
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */
562
+ [21] = COL_MASK(0, 23) | COL_MASK(29, 31),
563
+
564
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */
565
+ [22] = COL_MASK(0, 31),
566
+
567
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */
568
+ [23] = COL_MASK(0, 31),
569
+
570
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */
571
+ [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31),
572
+ [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31),
573
+ [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31),
574
+ [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31),
575
+ [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31),
576
+ [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31),
577
+
578
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */
579
+ [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31),
580
+ [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31),
581
+ [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31),
582
+ [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31),
583
+ [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31),
584
+ [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31),
585
+ };
586
+
587
+ uint32_t col_mask = COL_MASK(0, 31);
588
+#undef COL_MASK
589
+
590
+ uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR];
591
+ uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE);
592
+ uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW);
593
+
594
+ switch (efuse_ary) {
595
+ case 0: /* Various */
596
+ if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) {
597
+ goto denied;
598
+ }
599
+
600
+ col_mask = ary0_col_mask[efuse_row];
601
+ if (!col_mask) {
602
+ goto denied;
352
+ }
603
+ }
353
+ break;
604
+ break;
354
+ case REG_CPU0_CTRL: /* CPU#0 Control */
605
+ case 2: /* PUF helper data, adjust for skipped array 1 */
355
+ case REG_CPU1_CTRL: /* CPU#1 Control */
606
+ case 3:
356
+ case REG_CPU2_CTRL: /* CPU#2 Control */
607
+ val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1);
357
+ case REG_CPU3_CTRL: /* CPU#3 Control */
358
+ case REG_CPU0_STATUS: /* CPU#0 Status */
359
+ case REG_CPU1_STATUS: /* CPU#1 Status */
360
+ case REG_CPU2_STATUS: /* CPU#2 Status */
361
+ case REG_CPU3_STATUS: /* CPU#3 Status */
362
+ case REG_CLK_GATING: /* CPU Clock Gating */
363
+ break;
364
+ case REG_GEN_CTRL: /* General Control */
365
+ s->gen_ctrl = val;
366
+ break;
367
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
368
+ s->super_standby = val;
369
+ break;
370
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
371
+ s->entry_addr = val;
372
+ break;
373
+ case REG_DBG_EXTERN: /* Debug External */
374
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
375
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
376
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
377
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
378
+ __func__, (uint32_t)offset);
379
+ break;
608
+ break;
380
+ default:
609
+ default:
381
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
610
+ goto denied;
382
+ __func__, (uint32_t)offset);
611
+ }
383
+ break;
612
+
384
+ }
613
+ s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask;
385
+}
614
+
386
+
615
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0);
387
+static const MemoryRegionOps allwinner_cpucfg_ops = {
616
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
388
+ .read = allwinner_cpucfg_read,
617
+ zynqmp_efuse_update_irq(s);
389
+ .write = allwinner_cpucfg_write,
618
+ return;
390
+ .endianness = DEVICE_NATIVE_ENDIAN,
619
+
620
+ denied:
621
+ qemu_log_mask(LOG_GUEST_ERROR,
622
+ "%s: Denied efuse read from array %u, row %u\n",
623
+ object_get_canonical_path(OBJECT(s)),
624
+ efuse_ary, efuse_row);
625
+
626
+ s->regs[R_EFUSE_RD_DATA] = 0;
627
+
628
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
629
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0);
630
+ zynqmp_efuse_update_irq(s);
631
+}
632
+
633
+static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
634
+{
635
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
636
+ bool ok;
637
+
638
+ ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START);
639
+
640
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0));
641
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1);
642
+
643
+ s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */
644
+}
645
+
646
+static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg,
647
+ uint64_t valu64)
648
+{
649
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
650
+
651
+ if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
652
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
653
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
654
+ zynqmp_efuse_update_irq(s);
655
+ }
656
+
657
+ return 0;
658
+}
659
+
660
+static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
661
+{
662
+ return val == 0xDF0D ? 0 : 1;
663
+}
664
+
665
+static RegisterAccessInfo zynqmp_efuse_regs_info[] = {
666
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
667
+ .reset = 0x1,
668
+ .pre_write = zynqmp_efuse_wr_lock_prew,
669
+ },{ .name = "CFG", .addr = A_CFG,
670
+ },{ .name = "STATUS", .addr = A_STATUS,
671
+ .rsvd = 0x8,
672
+ .ro = 0xff,
673
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
674
+ .post_write = zynqmp_efuse_pgm_addr_postw
675
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
676
+ .rsvd = 0x1f,
677
+ .post_write = zynqmp_efuse_rd_addr_postw,
678
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
679
+ .ro = 0xffffffff,
680
+ },{ .name = "TPGM", .addr = A_TPGM,
681
+ },{ .name = "TRD", .addr = A_TRD,
682
+ .reset = 0x1b,
683
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
684
+ .reset = 0xff,
685
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
686
+ .reset = 0xb,
687
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
688
+ .reset = 0x7,
689
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
690
+ .rsvd = 0x7fffffe0,
691
+ .w1c = 0x8000001f,
692
+ .post_write = zynqmp_efuse_isr_postw,
693
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
694
+ .reset = 0x8000001f,
695
+ .rsvd = 0x7fffffe0,
696
+ .ro = 0xffffffff,
697
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
698
+ .rsvd = 0x7fffffe0,
699
+ .pre_write = zynqmp_efuse_ier_prew,
700
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
701
+ .rsvd = 0x7fffffe0,
702
+ .pre_write = zynqmp_efuse_idr_prew,
703
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
704
+ .pre_write = zynqmp_efuse_cache_load_prew,
705
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
706
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
707
+ .post_write = zynqmp_efuse_aes_crc_postw,
708
+ },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN,
709
+ .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK,
710
+ },{ .name = "DNA_0", .addr = A_DNA_0,
711
+ .ro = 0xffffffff,
712
+ },{ .name = "DNA_1", .addr = A_DNA_1,
713
+ .ro = 0xffffffff,
714
+ },{ .name = "DNA_2", .addr = A_DNA_2,
715
+ .ro = 0xffffffff,
716
+ },{ .name = "IPDISABLE", .addr = A_IPDISABLE,
717
+ .ro = 0xffffffff,
718
+ },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL,
719
+ .ro = 0xffffffff,
720
+ },{ .name = "USER_0", .addr = A_USER_0,
721
+ .ro = 0xffffffff,
722
+ },{ .name = "USER_1", .addr = A_USER_1,
723
+ .ro = 0xffffffff,
724
+ },{ .name = "USER_2", .addr = A_USER_2,
725
+ .ro = 0xffffffff,
726
+ },{ .name = "USER_3", .addr = A_USER_3,
727
+ .ro = 0xffffffff,
728
+ },{ .name = "USER_4", .addr = A_USER_4,
729
+ .ro = 0xffffffff,
730
+ },{ .name = "USER_5", .addr = A_USER_5,
731
+ .ro = 0xffffffff,
732
+ },{ .name = "USER_6", .addr = A_USER_6,
733
+ .ro = 0xffffffff,
734
+ },{ .name = "USER_7", .addr = A_USER_7,
735
+ .ro = 0xffffffff,
736
+ },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL,
737
+ .ro = 0xffffffff,
738
+ },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD,
739
+ .ro = 0xffffffff,
740
+ },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH,
741
+ .ro = 0xffffffff,
742
+ },{ .name = "PUF_MISC", .addr = A_PUF_MISC,
743
+ .ro = 0xffffffff,
744
+ },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL,
745
+ .ro = 0xffffffff,
746
+ },{ .name = "SPK_ID", .addr = A_SPK_ID,
747
+ .ro = 0xffffffff,
748
+ },{ .name = "PPK0_0", .addr = A_PPK0_0,
749
+ .ro = 0xffffffff,
750
+ },{ .name = "PPK0_1", .addr = A_PPK0_1,
751
+ .ro = 0xffffffff,
752
+ },{ .name = "PPK0_2", .addr = A_PPK0_2,
753
+ .ro = 0xffffffff,
754
+ },{ .name = "PPK0_3", .addr = A_PPK0_3,
755
+ .ro = 0xffffffff,
756
+ },{ .name = "PPK0_4", .addr = A_PPK0_4,
757
+ .ro = 0xffffffff,
758
+ },{ .name = "PPK0_5", .addr = A_PPK0_5,
759
+ .ro = 0xffffffff,
760
+ },{ .name = "PPK0_6", .addr = A_PPK0_6,
761
+ .ro = 0xffffffff,
762
+ },{ .name = "PPK0_7", .addr = A_PPK0_7,
763
+ .ro = 0xffffffff,
764
+ },{ .name = "PPK0_8", .addr = A_PPK0_8,
765
+ .ro = 0xffffffff,
766
+ },{ .name = "PPK0_9", .addr = A_PPK0_9,
767
+ .ro = 0xffffffff,
768
+ },{ .name = "PPK0_10", .addr = A_PPK0_10,
769
+ .ro = 0xffffffff,
770
+ },{ .name = "PPK0_11", .addr = A_PPK0_11,
771
+ .ro = 0xffffffff,
772
+ },{ .name = "PPK1_0", .addr = A_PPK1_0,
773
+ .ro = 0xffffffff,
774
+ },{ .name = "PPK1_1", .addr = A_PPK1_1,
775
+ .ro = 0xffffffff,
776
+ },{ .name = "PPK1_2", .addr = A_PPK1_2,
777
+ .ro = 0xffffffff,
778
+ },{ .name = "PPK1_3", .addr = A_PPK1_3,
779
+ .ro = 0xffffffff,
780
+ },{ .name = "PPK1_4", .addr = A_PPK1_4,
781
+ .ro = 0xffffffff,
782
+ },{ .name = "PPK1_5", .addr = A_PPK1_5,
783
+ .ro = 0xffffffff,
784
+ },{ .name = "PPK1_6", .addr = A_PPK1_6,
785
+ .ro = 0xffffffff,
786
+ },{ .name = "PPK1_7", .addr = A_PPK1_7,
787
+ .ro = 0xffffffff,
788
+ },{ .name = "PPK1_8", .addr = A_PPK1_8,
789
+ .ro = 0xffffffff,
790
+ },{ .name = "PPK1_9", .addr = A_PPK1_9,
791
+ .ro = 0xffffffff,
792
+ },{ .name = "PPK1_10", .addr = A_PPK1_10,
793
+ .ro = 0xffffffff,
794
+ },{ .name = "PPK1_11", .addr = A_PPK1_11,
795
+ .ro = 0xffffffff,
796
+ }
797
+};
798
+
799
+static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,
800
+ uint64_t data, unsigned size)
801
+{
802
+ RegisterInfoArray *reg_array = opaque;
803
+ XlnxZynqMPEFuse *s;
804
+ Object *dev;
805
+
806
+ assert(reg_array != NULL);
807
+
808
+ dev = reg_array->mem.owner;
809
+ assert(dev);
810
+
811
+ s = XLNX_ZYNQMP_EFUSE(dev);
812
+
813
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
814
+ qemu_log_mask(LOG_GUEST_ERROR,
815
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
816
+ object_get_canonical_path(OBJECT(s)), (long)addr);
817
+ } else {
818
+ register_write_memory(opaque, addr, data, size);
819
+ }
820
+}
821
+
822
+static const MemoryRegionOps zynqmp_efuse_ops = {
823
+ .read = register_read_memory,
824
+ .write = zynqmp_efuse_reg_write,
825
+ .endianness = DEVICE_LITTLE_ENDIAN,
391
+ .valid = {
826
+ .valid = {
392
+ .min_access_size = 4,
827
+ .min_access_size = 4,
393
+ .max_access_size = 4,
828
+ .max_access_size = 4,
394
+ },
829
+ },
395
+ .impl.min_access_size = 4,
396
+};
830
+};
397
+
831
+
398
+static void allwinner_cpucfg_reset(DeviceState *dev)
832
+static void zynqmp_efuse_register_reset(RegisterInfo *reg)
399
+{
833
+{
400
+ AwCpuCfgState *s = AW_CPUCFG(dev);
834
+ if (!reg->data || !reg->access) {
401
+
835
+ return;
402
+ /* Set default values for registers */
836
+ }
403
+ s->gen_ctrl = REG_GEN_CTRL_RST;
837
+
404
+ s->super_standby = REG_SUPER_STANDBY_RST;
838
+ /* Reset must not trigger some registers' writers */
405
+ s->entry_addr = 0;
839
+ switch (reg->access->addr) {
406
+}
840
+ case A_EFUSE_AES_CRC:
407
+
841
+ *(uint32_t *)reg->data = reg->access->reset;
408
+static void allwinner_cpucfg_init(Object *obj)
842
+ return;
409
+{
843
+ }
844
+
845
+ register_reset(reg);
846
+}
847
+
848
+static void zynqmp_efuse_reset(DeviceState *dev)
849
+{
850
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
851
+ unsigned int i;
852
+
853
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
854
+ zynqmp_efuse_register_reset(&s->regs_info[i]);
855
+ }
856
+
857
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
858
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
859
+ zynqmp_efuse_update_irq(s);
860
+}
861
+
862
+static void zynqmp_efuse_realize(DeviceState *dev, Error **errp)
863
+{
864
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
865
+
866
+ if (!s->efuse) {
867
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
868
+ object_get_canonical_path(OBJECT(dev)));
869
+ return;
870
+ }
871
+
872
+ s->efuse->dev = dev;
873
+}
874
+
875
+static void zynqmp_efuse_init(Object *obj)
876
+{
877
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
410
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
878
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
411
+ AwCpuCfgState *s = AW_CPUCFG(obj);
879
+ RegisterInfoArray *reg_array;
412
+
880
+
413
+ /* Memory mapping */
881
+ reg_array =
414
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
882
+ register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info,
415
+ TYPE_AW_CPUCFG, 1 * KiB);
883
+ ARRAY_SIZE(zynqmp_efuse_regs_info),
416
+ sysbus_init_mmio(sbd, &s->iomem);
884
+ s->regs_info, s->regs,
417
+}
885
+ &zynqmp_efuse_ops,
418
+
886
+ ZYNQMP_EFUSE_ERR_DEBUG,
419
+static const VMStateDescription allwinner_cpucfg_vmstate = {
887
+ R_MAX * 4);
420
+ .name = "allwinner-cpucfg",
888
+
889
+ sysbus_init_mmio(sbd, &reg_array->mem);
890
+ sysbus_init_irq(sbd, &s->irq);
891
+}
892
+
893
+static const VMStateDescription vmstate_efuse = {
894
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
421
+ .version_id = 1,
895
+ .version_id = 1,
422
+ .minimum_version_id = 1,
896
+ .minimum_version_id = 1,
423
+ .fields = (VMStateField[]) {
897
+ .fields = (VMStateField[]) {
424
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
898
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX),
425
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
899
+ VMSTATE_END_OF_LIST(),
426
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
427
+ VMSTATE_END_OF_LIST()
428
+ }
900
+ }
429
+};
901
+};
430
+
902
+
431
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
903
+static Property zynqmp_efuse_props[] = {
904
+ DEFINE_PROP_LINK("efuse",
905
+ XlnxZynqMPEFuse, efuse,
906
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
907
+
908
+ DEFINE_PROP_END_OF_LIST(),
909
+};
910
+
911
+static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
432
+{
912
+{
433
+ DeviceClass *dc = DEVICE_CLASS(klass);
913
+ DeviceClass *dc = DEVICE_CLASS(klass);
434
+
914
+
435
+ dc->reset = allwinner_cpucfg_reset;
915
+ dc->reset = zynqmp_efuse_reset;
436
+ dc->vmsd = &allwinner_cpucfg_vmstate;
916
+ dc->realize = zynqmp_efuse_realize;
437
+}
917
+ dc->vmsd = &vmstate_efuse;
438
+
918
+ device_class_set_props(dc, zynqmp_efuse_props);
439
+static const TypeInfo allwinner_cpucfg_info = {
919
+}
440
+ .name = TYPE_AW_CPUCFG,
920
+
921
+
922
+static const TypeInfo efuse_info = {
923
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
441
+ .parent = TYPE_SYS_BUS_DEVICE,
924
+ .parent = TYPE_SYS_BUS_DEVICE,
442
+ .instance_init = allwinner_cpucfg_init,
925
+ .instance_size = sizeof(XlnxZynqMPEFuse),
443
+ .instance_size = sizeof(AwCpuCfgState),
926
+ .class_init = zynqmp_efuse_class_init,
444
+ .class_init = allwinner_cpucfg_class_init,
927
+ .instance_init = zynqmp_efuse_init,
445
+};
928
+};
446
+
929
+
447
+static void allwinner_cpucfg_register(void)
930
+static void efuse_register_types(void)
448
+{
931
+{
449
+ type_register_static(&allwinner_cpucfg_info);
932
+ type_register_static(&efuse_info);
450
+}
933
+}
451
+
934
+
452
+type_init(allwinner_cpucfg_register)
935
+type_init(efuse_register_types)
453
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
936
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
454
index XXXXXXX..XXXXXXX 100644
937
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/misc/trace-events
938
--- a/hw/nvram/Kconfig
456
+++ b/hw/misc/trace-events
939
+++ b/hw/nvram/Kconfig
457
@@ -XXX,XX +XXX,XX @@
940
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE
458
# See docs/devel/tracing.txt for syntax documentation.
941
config XLNX_EFUSE_VERSAL
459
942
bool
460
+# allwinner-cpucfg.c
943
select XLNX_EFUSE
461
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32
944
+
462
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
945
+config XLNX_EFUSE_ZYNQMP
463
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
946
+ bool
464
+
947
+ select XLNX_EFUSE
465
# eccmemctl.c
948
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
466
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
949
index XXXXXXX..XXXXXXX 100644
467
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
950
--- a/hw/nvram/meson.build
951
+++ b/hw/nvram/meson.build
952
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
953
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
954
'xlnx-versal-efuse-cache.c',
955
'xlnx-versal-efuse-ctrl.c'))
956
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
957
+ 'xlnx-zynqmp-efuse.c'))
958
959
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
468
--
960
--
469
2.20.1
961
2.20.1
470
962
471
963
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
In the Allwinner H3 SoC the SDRAM controller is responsible
3
This device is present in Versal and ZynqMP product
4
for interfacing with the external Synchronous Dynamic Random
4
families to store a 256-bit encryption key.
5
Access Memory (SDRAM). Types of memory that the SDRAM controller
6
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
7
adds emulation support of the Allwinner H3 SDRAM controller.
8
5
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
8
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
12
Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
15
---
14
hw/misc/Makefile.objs | 1 +
16
include/hw/nvram/xlnx-bbram.h | 54 ++++
15
include/hw/arm/allwinner-h3.h | 5 +
17
hw/nvram/xlnx-bbram.c | 545 ++++++++++++++++++++++++++++++++++
16
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
18
hw/nvram/Kconfig | 4 +
17
hw/arm/allwinner-h3.c | 19 +-
19
hw/nvram/meson.build | 1 +
18
hw/arm/orangepi.c | 6 +
20
4 files changed, 604 insertions(+)
19
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
21
create mode 100644 include/hw/nvram/xlnx-bbram.h
20
hw/misc/trace-events | 10 +
22
create mode 100644 hw/nvram/xlnx-bbram.c
21
7 files changed, 502 insertions(+), 3 deletions(-)
22
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
23
create mode 100644 hw/misc/allwinner-h3-dramc.c
24
23
25
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
24
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/misc/Makefile.objs
28
+++ b/hw/misc/Makefile.objs
29
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
30
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
32
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
33
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o
34
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
37
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/arm/allwinner-h3.h
40
+++ b/include/hw/arm/allwinner-h3.h
41
@@ -XXX,XX +XXX,XX @@
42
#include "hw/intc/arm_gic.h"
43
#include "hw/misc/allwinner-h3-ccu.h"
44
#include "hw/misc/allwinner-cpucfg.h"
45
+#include "hw/misc/allwinner-h3-dramc.h"
46
#include "hw/misc/allwinner-h3-sysctrl.h"
47
#include "hw/misc/allwinner-sid.h"
48
#include "hw/sd/allwinner-sdhost.h"
49
@@ -XXX,XX +XXX,XX @@ enum {
50
AW_H3_UART2,
51
AW_H3_UART3,
52
AW_H3_EMAC,
53
+ AW_H3_DRAMCOM,
54
+ AW_H3_DRAMCTL,
55
+ AW_H3_DRAMPHY,
56
AW_H3_GIC_DIST,
57
AW_H3_GIC_CPU,
58
AW_H3_GIC_HYP,
59
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
AwCpuCfgState cpucfg;
63
+ AwH3DramCtlState dramc;
64
AwH3SysCtrlState sysctrl;
65
AwSidState sid;
66
AwSdHostState mmc0;
67
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h
68
new file mode 100644
25
new file mode 100644
69
index XXXXXXX..XXXXXXX
26
index XXXXXXX..XXXXXXX
70
--- /dev/null
27
--- /dev/null
71
+++ b/include/hw/misc/allwinner-h3-dramc.h
28
+++ b/include/hw/nvram/xlnx-bbram.h
72
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@
73
+/*
30
+/*
74
+ * Allwinner H3 SDRAM Controller emulation
31
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
75
+ *
32
+ *
76
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
33
+ * Copyright (c) 2015-2021 Xilinx Inc.
77
+ *
34
+ *
78
+ * This program is free software: you can redistribute it and/or modify
35
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
79
+ * it under the terms of the GNU General Public License as published by
36
+ *
80
+ * the Free Software Foundation, either version 2 of the License, or
37
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
81
+ * (at your option) any later version.
38
+ * of this software and associated documentation files (the "Software"), to deal
82
+ *
39
+ * in the Software without restriction, including without limitation the rights
83
+ * This program is distributed in the hope that it will be useful,
40
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
84
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41
+ * copies of the Software, and to permit persons to whom the Software is
85
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42
+ * furnished to do so, subject to the following conditions:
86
+ * GNU General Public License for more details.
43
+ *
87
+ *
44
+ * The above copyright notice and this permission notice shall be included in
88
+ * You should have received a copy of the GNU General Public License
45
+ * all copies or substantial portions of the Software.
89
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
46
+ *
47
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
51
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
52
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
53
+ * THE SOFTWARE.
90
+ */
54
+ */
91
+
55
+#ifndef XLNX_BBRAM_H
92
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
56
+#define XLNX_BBRAM_H
93
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
57
+
94
+
58
+#include "sysemu/block-backend.h"
95
+#include "qom/object.h"
59
+#include "hw/qdev-core.h"
60
+#include "hw/irq.h"
96
+#include "hw/sysbus.h"
61
+#include "hw/sysbus.h"
97
+#include "exec/hwaddr.h"
62
+#include "hw/register.h"
98
+
63
+
99
+/**
64
+#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
100
+ * Constants
65
+
101
+ * @{
66
+#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
102
+ */
67
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
103
+
68
+
104
+/** Highest register address used by DRAMCOM module */
69
+struct XlnxBBRam {
105
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
106
+
107
+/** Total number of known DRAMCOM registers */
108
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
109
+ sizeof(uint32_t))
110
+
111
+/** Highest register address used by DRAMCTL module */
112
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
113
+
114
+/** Total number of known DRAMCTL registers */
115
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
116
+ sizeof(uint32_t))
117
+
118
+/** Highest register address used by DRAMPHY module */
119
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
120
+
121
+/** Total number of known DRAMPHY registers */
122
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
123
+ sizeof(uint32_t))
124
+
125
+/** @} */
126
+
127
+/**
128
+ * Object model
129
+ * @{
130
+ */
131
+
132
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
133
+#define AW_H3_DRAMC(obj) \
134
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
135
+
136
+/** @} */
137
+
138
+/**
139
+ * Allwinner H3 SDRAM Controller object instance state.
140
+ */
141
+typedef struct AwH3DramCtlState {
142
+ /*< private >*/
143
+ SysBusDevice parent_obj;
70
+ SysBusDevice parent_obj;
144
+ /*< public >*/
71
+ qemu_irq irq_bbram;
145
+
72
+
146
+ /** Physical base address for start of RAM */
73
+ BlockBackend *blk;
147
+ hwaddr ram_addr;
74
+
148
+
75
+ uint32_t crc_zpads;
149
+ /** Total RAM size in megabytes */
76
+ bool bbram8_wo;
150
+ uint32_t ram_size;
77
+ bool blk_ro;
151
+
78
+
152
+ /**
79
+ uint32_t regs[RMAX_XLNX_BBRAM];
153
+ * @name Memory Regions
80
+ RegisterInfo regs_info[RMAX_XLNX_BBRAM];
154
+ * @{
81
+};
155
+ */
82
+
156
+
83
+#endif
157
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
84
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
158
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
159
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
160
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
161
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
162
+
163
+ /** @} */
164
+
165
+ /**
166
+ * @name Hardware Registers
167
+ * @{
168
+ */
169
+
170
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
171
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
172
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
173
+
174
+ /** @} */
175
+
176
+} AwH3DramCtlState;
177
+
178
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
179
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/hw/arm/allwinner-h3.c
182
+++ b/hw/arm/allwinner-h3.c
183
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
184
[AW_H3_UART2] = 0x01c28800,
185
[AW_H3_UART3] = 0x01c28c00,
186
[AW_H3_EMAC] = 0x01c30000,
187
+ [AW_H3_DRAMCOM] = 0x01c62000,
188
+ [AW_H3_DRAMCTL] = 0x01c63000,
189
+ [AW_H3_DRAMPHY] = 0x01c65000,
190
[AW_H3_GIC_DIST] = 0x01c81000,
191
[AW_H3_GIC_CPU] = 0x01c82000,
192
[AW_H3_GIC_HYP] = 0x01c84000,
193
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
194
{ "scr", 0x01c2c400, 1 * KiB },
195
{ "gpu", 0x01c40000, 64 * KiB },
196
{ "hstmr", 0x01c60000, 4 * KiB },
197
- { "dramcom", 0x01c62000, 4 * KiB },
198
- { "dramctl0", 0x01c63000, 4 * KiB },
199
- { "dramphy0", 0x01c65000, 4 * KiB },
200
{ "spi0", 0x01c68000, 4 * KiB },
201
{ "spi1", 0x01c69000, 4 * KiB },
202
{ "csi", 0x01cb0000, 320 * KiB },
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
206
TYPE_AW_SUN8I_EMAC);
207
+
208
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
209
+ TYPE_AW_H3_DRAMC);
210
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
211
+ "ram-addr", &error_abort);
212
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
213
+ "ram-size", &error_abort);
214
}
215
216
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
217
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
218
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
219
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
220
221
+ /* DRAMC */
222
+ qdev_init_nofail(DEVICE(&s->dramc));
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
224
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
225
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
226
+
227
/* Unimplemented devices */
228
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
229
create_unimplemented_device(unimplemented[i].device_name,
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
/* Setup EMAC properties */
236
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
237
238
+ /* DRAMC */
239
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
240
+ "ram-addr", &error_abort);
241
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",
242
+ &error_abort);
243
+
244
/* Mark H3 object realized */
245
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
246
247
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
248
new file mode 100644
85
new file mode 100644
249
index XXXXXXX..XXXXXXX
86
index XXXXXXX..XXXXXXX
250
--- /dev/null
87
--- /dev/null
251
+++ b/hw/misc/allwinner-h3-dramc.c
88
+++ b/hw/nvram/xlnx-bbram.c
252
@@ -XXX,XX +XXX,XX @@
89
@@ -XXX,XX +XXX,XX @@
253
+/*
90
+/*
254
+ * Allwinner H3 SDRAM Controller emulation
91
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
255
+ *
92
+ *
256
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
93
+ * Copyright (c) 2014-2021 Xilinx Inc.
257
+ *
94
+ *
258
+ * This program is free software: you can redistribute it and/or modify
95
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
259
+ * it under the terms of the GNU General Public License as published by
96
+ * of this software and associated documentation files (the "Software"), to deal
260
+ * the Free Software Foundation, either version 2 of the License, or
97
+ * in the Software without restriction, including without limitation the rights
261
+ * (at your option) any later version.
98
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
262
+ *
99
+ * copies of the Software, and to permit persons to whom the Software is
263
+ * This program is distributed in the hope that it will be useful,
100
+ * furnished to do so, subject to the following conditions:
264
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
101
+ *
265
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
102
+ * The above copyright notice and this permission notice shall be included in
266
+ * GNU General Public License for more details.
103
+ * all copies or substantial portions of the Software.
267
+ *
104
+ *
268
+ * You should have received a copy of the GNU General Public License
105
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
269
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
106
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
107
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
108
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
109
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
110
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
111
+ * THE SOFTWARE.
270
+ */
112
+ */
271
+
113
+
272
+#include "qemu/osdep.h"
114
+#include "qemu/osdep.h"
273
+#include "qemu/units.h"
115
+#include "hw/nvram/xlnx-bbram.h"
116
+
274
+#include "qemu/error-report.h"
117
+#include "qemu/error-report.h"
275
+#include "hw/sysbus.h"
118
+#include "qemu/log.h"
119
+#include "qapi/error.h"
120
+#include "sysemu/blockdev.h"
276
+#include "migration/vmstate.h"
121
+#include "migration/vmstate.h"
277
+#include "qemu/log.h"
278
+#include "qemu/module.h"
279
+#include "exec/address-spaces.h"
280
+#include "hw/qdev-properties.h"
122
+#include "hw/qdev-properties.h"
281
+#include "qapi/error.h"
123
+#include "hw/qdev-properties-system.h"
282
+#include "hw/misc/allwinner-h3-dramc.h"
124
+#include "hw/nvram/xlnx-efuse.h"
283
+#include "trace.h"
125
+
284
+
126
+#ifndef XLNX_BBRAM_ERR_DEBUG
285
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
127
+#define XLNX_BBRAM_ERR_DEBUG 0
286
+
128
+#endif
287
+/* DRAMCOM register offsets */
129
+
288
+enum {
130
+REG32(BBRAM_STATUS, 0x0)
289
+ REG_DRAMCOM_CR = 0x0000, /* Control Register */
131
+ FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1)
132
+ FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1)
133
+ FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1)
134
+ FIELD(BBRAM_STATUS, PGM_MODE, 0, 1)
135
+REG32(BBRAM_CTRL, 0x4)
136
+ FIELD(BBRAM_CTRL, ZEROIZE, 0, 1)
137
+REG32(PGM_MODE, 0x8)
138
+REG32(BBRAM_AES_CRC, 0xc)
139
+REG32(BBRAM_0, 0x10)
140
+REG32(BBRAM_1, 0x14)
141
+REG32(BBRAM_2, 0x18)
142
+REG32(BBRAM_3, 0x1c)
143
+REG32(BBRAM_4, 0x20)
144
+REG32(BBRAM_5, 0x24)
145
+REG32(BBRAM_6, 0x28)
146
+REG32(BBRAM_7, 0x2c)
147
+REG32(BBRAM_8, 0x30)
148
+REG32(BBRAM_SLVERR, 0x34)
149
+ FIELD(BBRAM_SLVERR, ENABLE, 0, 1)
150
+REG32(BBRAM_ISR, 0x38)
151
+ FIELD(BBRAM_ISR, APB_SLVERR, 0, 1)
152
+REG32(BBRAM_IMR, 0x3c)
153
+ FIELD(BBRAM_IMR, APB_SLVERR, 0, 1)
154
+REG32(BBRAM_IER, 0x40)
155
+ FIELD(BBRAM_IER, APB_SLVERR, 0, 1)
156
+REG32(BBRAM_IDR, 0x44)
157
+ FIELD(BBRAM_IDR, APB_SLVERR, 0, 1)
158
+REG32(BBRAM_MSW_LOCK, 0x4c)
159
+ FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
160
+
161
+#define R_MAX (R_BBRAM_MSW_LOCK + 1)
162
+
163
+#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
164
+
165
+#define BBRAM_PGM_MAGIC 0x757bdf0d
166
+
167
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
168
+
169
+static bool bbram_msw_locked(XlnxBBRam *s)
170
+{
171
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;
172
+}
173
+
174
+static bool bbram_pgm_enabled(XlnxBBRam *s)
175
+{
176
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;
177
+}
178
+
179
+static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
180
+{
181
+ Error *errp;
182
+
183
+ error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
184
+ blk_name(s->blk), detail);
185
+ error_report("%s", error_get_pretty(errp));
186
+ error_free(errp);
187
+
188
+ g_free(detail);
189
+}
190
+
191
+static void bbram_bdrv_read(XlnxBBRam *s, Error **errp)
192
+{
193
+ uint32_t *ram = &s->regs[R_BBRAM_0];
194
+ int nr = RAM_MAX;
195
+
196
+ if (!s->blk) {
197
+ return;
198
+ }
199
+
200
+ s->blk_ro = !blk_supports_write_perm(s->blk);
201
+ if (!s->blk_ro) {
202
+ int rc;
203
+
204
+ rc = blk_set_perm(s->blk,
205
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
206
+ BLK_PERM_ALL, NULL);
207
+ if (rc) {
208
+ s->blk_ro = true;
209
+ }
210
+ }
211
+ if (s->blk_ro) {
212
+ warn_report("%s: Skip saving updates to read-only BBRAM backstore.",
213
+ blk_name(s->blk));
214
+ }
215
+
216
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
217
+ error_setg(errp,
218
+ "%s: Failed to read %u bytes from BBRAM backstore.",
219
+ blk_name(s->blk), nr);
220
+ return;
221
+ }
222
+
223
+ /* Convert from little-endian backstore for each 32-bit word */
224
+ nr /= 4;
225
+ while (nr--) {
226
+ ram[nr] = le32_to_cpu(ram[nr]);
227
+ }
228
+}
229
+
230
+static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr)
231
+{
232
+ uint32_t le32;
233
+ unsigned offset;
234
+ int rc;
235
+
236
+ assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8);
237
+
238
+ /* Backstore is always in little-endian */
239
+ le32 = cpu_to_le32(s->regs[hwaddr / 4]);
240
+
241
+ /* Update zeroized flag */
242
+ if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {
243
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);
244
+ }
245
+
246
+ if (!s->blk || s->blk_ro) {
247
+ return;
248
+ }
249
+
250
+ offset = hwaddr - A_BBRAM_0;
251
+ rc = blk_pwrite(s->blk, offset, &le32, 4, 0);
252
+ if (rc < 0) {
253
+ bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset));
254
+ }
255
+}
256
+
257
+static void bbram_bdrv_zero(XlnxBBRam *s)
258
+{
259
+ int rc;
260
+
261
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);
262
+
263
+ if (!s->blk || s->blk_ro) {
264
+ return;
265
+ }
266
+
267
+ rc = blk_make_zero(s->blk, 0);
268
+ if (rc < 0) {
269
+ bbram_bdrv_error(s, rc, g_strdup("zeroizing"));
270
+ }
271
+
272
+ /* Restore bbram8 if it is non-zero */
273
+ if (s->regs[R_BBRAM_8]) {
274
+ bbram_bdrv_sync(s, A_BBRAM_8);
275
+ }
276
+}
277
+
278
+static void bbram_zeroize(XlnxBBRam *s)
279
+{
280
+ int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */
281
+
282
+ memset(&s->regs[R_BBRAM_0], 0, nr);
283
+ bbram_bdrv_zero(s);
284
+}
285
+
286
+static void bbram_update_irq(XlnxBBRam *s)
287
+{
288
+ bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];
289
+
290
+ qemu_set_irq(s->irq_bbram, pending);
291
+}
292
+
293
+static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64)
294
+{
295
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
296
+ uint32_t val = val64;
297
+
298
+ if (val & R_BBRAM_CTRL_ZEROIZE_MASK) {
299
+ bbram_zeroize(s);
300
+ /* The bit is self clearing */
301
+ s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;
302
+ }
303
+}
304
+
305
+static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64)
306
+{
307
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
308
+ uint32_t val = val64;
309
+
310
+ if (val == BBRAM_PGM_MAGIC) {
311
+ bbram_zeroize(s);
312
+
313
+ /* The status bit is cleared only by POR */
314
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);
315
+ }
316
+}
317
+
318
+static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
319
+{
320
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
321
+ uint32_t calc_crc;
322
+
323
+ if (!bbram_pgm_enabled(s)) {
324
+ /* We are not in programming mode, don't do anything */
325
+ return;
326
+ }
327
+
328
+ /* Perform the AES integrity check */
329
+ s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;
330
+
331
+ /*
332
+ * Set check status.
333
+ *
334
+ * ZynqMP BBRAM check has a zero-u32 prepended; see:
335
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311
336
+ */
337
+ calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],
338
+ (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);
339
+
340
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,
341
+ (s->regs[R_BBRAM_AES_CRC] == calc_crc));
342
+}
343
+
344
+static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64)
345
+{
346
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
347
+ uint32_t original_data = *(uint32_t *) reg->data;
348
+
349
+ if (bbram_pgm_enabled(s)) {
350
+ return val64;
351
+ } else {
352
+ /* We are not in programming mode, don't do anything */
353
+ qemu_log_mask(LOG_GUEST_ERROR,
354
+ "Not in programming mode, dropping the write\n");
355
+ return original_data;
356
+ }
357
+}
358
+
359
+static void bbram_key_postw(RegisterInfo *reg, uint64_t val64)
360
+{
361
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
362
+
363
+ bbram_bdrv_sync(s, reg->access->addr);
364
+}
365
+
366
+static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val)
367
+{
368
+ return 0;
369
+}
370
+
371
+static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val)
372
+{
373
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
374
+
375
+ return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;
376
+}
377
+
378
+static bool bbram_r8_readonly(XlnxBBRam *s)
379
+{
380
+ return !bbram_pgm_enabled(s) || bbram_msw_locked(s);
381
+}
382
+
383
+static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64)
384
+{
385
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
386
+
387
+ if (bbram_r8_readonly(s)) {
388
+ val64 = *(uint32_t *)reg->data;
389
+ }
390
+
391
+ return val64;
392
+}
393
+
394
+static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64)
395
+{
396
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
397
+
398
+ if (!bbram_r8_readonly(s)) {
399
+ bbram_bdrv_sync(s, A_BBRAM_8);
400
+ }
401
+}
402
+
403
+static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64)
404
+{
405
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
406
+
407
+ /* Never lock if bbram8 is wo; and, only POR can clear the lock */
408
+ if (s->bbram8_wo) {
409
+ val64 = 0;
410
+ } else {
411
+ val64 |= s->regs[R_BBRAM_MSW_LOCK];
412
+ }
413
+
414
+ return val64;
415
+}
416
+
417
+static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64)
418
+{
419
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
420
+
421
+ bbram_update_irq(s);
422
+}
423
+
424
+static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64)
425
+{
426
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
427
+ uint32_t val = val64;
428
+
429
+ s->regs[R_BBRAM_IMR] &= ~val;
430
+ bbram_update_irq(s);
431
+ return 0;
432
+}
433
+
434
+static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64)
435
+{
436
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
437
+ uint32_t val = val64;
438
+
439
+ s->regs[R_BBRAM_IMR] |= val;
440
+ bbram_update_irq(s);
441
+ return 0;
442
+}
443
+
444
+static RegisterAccessInfo bbram_ctrl_regs_info[] = {
445
+ { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS,
446
+ .rsvd = 0xee,
447
+ .ro = 0x3ff,
448
+ },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL,
449
+ .post_write = bbram_ctrl_postw,
450
+ },{ .name = "PGM_MODE", .addr = A_PGM_MODE,
451
+ .post_write = bbram_pgm_mode_postw,
452
+ },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC,
453
+ .post_write = bbram_aes_crc_postw,
454
+ .post_read = bbram_wo_postr,
455
+ },{ .name = "BBRAM_0", .addr = A_BBRAM_0,
456
+ .pre_write = bbram_key_prew,
457
+ .post_write = bbram_key_postw,
458
+ .post_read = bbram_wo_postr,
459
+ },{ .name = "BBRAM_1", .addr = A_BBRAM_1,
460
+ .pre_write = bbram_key_prew,
461
+ .post_write = bbram_key_postw,
462
+ .post_read = bbram_wo_postr,
463
+ },{ .name = "BBRAM_2", .addr = A_BBRAM_2,
464
+ .pre_write = bbram_key_prew,
465
+ .post_write = bbram_key_postw,
466
+ .post_read = bbram_wo_postr,
467
+ },{ .name = "BBRAM_3", .addr = A_BBRAM_3,
468
+ .pre_write = bbram_key_prew,
469
+ .post_write = bbram_key_postw,
470
+ .post_read = bbram_wo_postr,
471
+ },{ .name = "BBRAM_4", .addr = A_BBRAM_4,
472
+ .pre_write = bbram_key_prew,
473
+ .post_write = bbram_key_postw,
474
+ .post_read = bbram_wo_postr,
475
+ },{ .name = "BBRAM_5", .addr = A_BBRAM_5,
476
+ .pre_write = bbram_key_prew,
477
+ .post_write = bbram_key_postw,
478
+ .post_read = bbram_wo_postr,
479
+ },{ .name = "BBRAM_6", .addr = A_BBRAM_6,
480
+ .pre_write = bbram_key_prew,
481
+ .post_write = bbram_key_postw,
482
+ .post_read = bbram_wo_postr,
483
+ },{ .name = "BBRAM_7", .addr = A_BBRAM_7,
484
+ .pre_write = bbram_key_prew,
485
+ .post_write = bbram_key_postw,
486
+ .post_read = bbram_wo_postr,
487
+ },{ .name = "BBRAM_8", .addr = A_BBRAM_8,
488
+ .pre_write = bbram_r8_prew,
489
+ .post_write = bbram_r8_postw,
490
+ .post_read = bbram_r8_postr,
491
+ },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR,
492
+ .rsvd = ~1,
493
+ },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR,
494
+ .w1c = 0x1,
495
+ .post_write = bbram_isr_postw,
496
+ },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR,
497
+ .ro = 0x1,
498
+ },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER,
499
+ .pre_write = bbram_ier_prew,
500
+ },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR,
501
+ .pre_write = bbram_idr_prew,
502
+ },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK,
503
+ .pre_write = bbram_msw_lock_prew,
504
+ .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK,
505
+ }
290
+};
506
+};
291
+
507
+
292
+/* DRAMCTL register offsets */
508
+static void bbram_ctrl_reset(DeviceState *dev)
293
+enum {
509
+{
294
+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
510
+ XlnxBBRam *s = XLNX_BBRAM(dev);
295
+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
511
+ unsigned int i;
296
+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */
512
+
297
+};
513
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
298
+
514
+ if (i < R_BBRAM_0 || i > R_BBRAM_8) {
299
+/* DRAMCTL register flags */
515
+ register_reset(&s->regs_info[i]);
300
+enum {
301
+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
302
+};
303
+
304
+enum {
305
+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
306
+};
307
+
308
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
309
+ uint8_t bank_bits, uint16_t page_size)
310
+{
311
+ /*
312
+ * This function simulates row addressing behavior when bootloader
313
+ * software attempts to detect the amount of available SDRAM. In U-Boot
314
+ * the controller is configured with the widest row addressing available.
315
+ * Then a pattern is written to RAM at an offset on the row boundary size.
316
+ * If the value read back equals the value read back from the
317
+ * start of RAM, the bootloader knows the amount of row bits.
318
+ *
319
+ * This function inserts a mirrored memory region when the configured row
320
+ * bits are not matching the actual emulated memory, to simulate the
321
+ * same behavior on hardware as expected by the bootloader.
322
+ */
323
+ uint8_t row_bits_actual = 0;
324
+
325
+ /* Calculate the actual row bits using the ram_size property */
326
+ for (uint8_t i = 8; i < 12; i++) {
327
+ if (1 << i == s->ram_size) {
328
+ row_bits_actual = i + 3;
329
+ break;
330
+ }
516
+ }
331
+ }
517
+ }
332
+
518
+
333
+ if (s->ram_size == (1 << (row_bits - 3))) {
519
+ bbram_update_irq(s);
334
+ /* When row bits is the expected value, remove the mirror */
520
+}
335
+ memory_region_set_enabled(&s->row_mirror_alias, false);
521
+
336
+ trace_allwinner_h3_dramc_rowmirror_disable();
522
+static const MemoryRegionOps bbram_ctrl_ops = {
337
+
523
+ .read = register_read_memory,
338
+ } else if (row_bits_actual) {
524
+ .write = register_write_memory,
339
+ /* Row bits not matching ram_size, install the rows mirror */
525
+ .endianness = DEVICE_LITTLE_ENDIAN,
340
+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
341
+ bank_bits)) * page_size);
342
+
343
+ memory_region_set_enabled(&s->row_mirror_alias, true);
344
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
345
+
346
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
347
+ }
348
+}
349
+
350
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
351
+ unsigned size)
352
+{
353
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
354
+ const uint32_t idx = REG_INDEX(offset);
355
+
356
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
357
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
358
+ __func__, (uint32_t)offset);
359
+ return 0;
360
+ }
361
+
362
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
363
+
364
+ return s->dramcom[idx];
365
+}
366
+
367
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
368
+ uint64_t val, unsigned size)
369
+{
370
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
371
+ const uint32_t idx = REG_INDEX(offset);
372
+
373
+ trace_allwinner_h3_dramcom_write(offset, val, size);
374
+
375
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
376
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
377
+ __func__, (uint32_t)offset);
378
+ return;
379
+ }
380
+
381
+ switch (offset) {
382
+ case REG_DRAMCOM_CR: /* Control Register */
383
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
384
+ ((val >> 2) & 0x1) + 2,
385
+ 1 << (((val >> 8) & 0xf) + 3));
386
+ break;
387
+ default:
388
+ break;
389
+ };
390
+
391
+ s->dramcom[idx] = (uint32_t) val;
392
+}
393
+
394
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
395
+ unsigned size)
396
+{
397
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
398
+ const uint32_t idx = REG_INDEX(offset);
399
+
400
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
401
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
402
+ __func__, (uint32_t)offset);
403
+ return 0;
404
+ }
405
+
406
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
407
+
408
+ return s->dramctl[idx];
409
+}
410
+
411
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
412
+ uint64_t val, unsigned size)
413
+{
414
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
415
+ const uint32_t idx = REG_INDEX(offset);
416
+
417
+ trace_allwinner_h3_dramctl_write(offset, val, size);
418
+
419
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
420
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
421
+ __func__, (uint32_t)offset);
422
+ return;
423
+ }
424
+
425
+ switch (offset) {
426
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
427
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
428
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
429
+ break;
430
+ default:
431
+ break;
432
+ }
433
+
434
+ s->dramctl[idx] = (uint32_t) val;
435
+}
436
+
437
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
438
+ unsigned size)
439
+{
440
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
441
+ const uint32_t idx = REG_INDEX(offset);
442
+
443
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
445
+ __func__, (uint32_t)offset);
446
+ return 0;
447
+ }
448
+
449
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
450
+
451
+ return s->dramphy[idx];
452
+}
453
+
454
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
455
+ uint64_t val, unsigned size)
456
+{
457
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
458
+ const uint32_t idx = REG_INDEX(offset);
459
+
460
+ trace_allwinner_h3_dramphy_write(offset, val, size);
461
+
462
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
463
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
464
+ __func__, (uint32_t)offset);
465
+ return;
466
+ }
467
+
468
+ s->dramphy[idx] = (uint32_t) val;
469
+}
470
+
471
+static const MemoryRegionOps allwinner_h3_dramcom_ops = {
472
+ .read = allwinner_h3_dramcom_read,
473
+ .write = allwinner_h3_dramcom_write,
474
+ .endianness = DEVICE_NATIVE_ENDIAN,
475
+ .valid = {
526
+ .valid = {
476
+ .min_access_size = 4,
527
+ .min_access_size = 4,
477
+ .max_access_size = 4,
528
+ .max_access_size = 4,
478
+ },
529
+ },
479
+ .impl.min_access_size = 4,
480
+};
530
+};
481
+
531
+
482
+static const MemoryRegionOps allwinner_h3_dramctl_ops = {
532
+static void bbram_ctrl_realize(DeviceState *dev, Error **errp)
483
+ .read = allwinner_h3_dramctl_read,
533
+{
484
+ .write = allwinner_h3_dramctl_write,
534
+ XlnxBBRam *s = XLNX_BBRAM(dev);
485
+ .endianness = DEVICE_NATIVE_ENDIAN,
535
+
486
+ .valid = {
536
+ if (s->crc_zpads) {
487
+ .min_access_size = 4,
537
+ s->bbram8_wo = true;
488
+ .max_access_size = 4,
538
+ }
489
+ },
539
+
490
+ .impl.min_access_size = 4,
540
+ bbram_bdrv_read(s, errp);
541
+}
542
+
543
+static void bbram_ctrl_init(Object *obj)
544
+{
545
+ XlnxBBRam *s = XLNX_BBRAM(obj);
546
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
547
+ RegisterInfoArray *reg_array;
548
+
549
+ reg_array =
550
+ register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
551
+ ARRAY_SIZE(bbram_ctrl_regs_info),
552
+ s->regs_info, s->regs,
553
+ &bbram_ctrl_ops,
554
+ XLNX_BBRAM_ERR_DEBUG,
555
+ R_MAX * 4);
556
+
557
+ sysbus_init_mmio(sbd, &reg_array->mem);
558
+ sysbus_init_irq(sbd, &s->irq_bbram);
559
+}
560
+
561
+static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name,
562
+ void *opaque, Error **errp)
563
+{
564
+ DeviceState *dev = DEVICE(obj);
565
+
566
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
567
+
568
+ /* Fill initial data if backend is attached after realized */
569
+ if (dev->realized) {
570
+ bbram_bdrv_read(XLNX_BBRAM(obj), errp);
571
+ }
572
+}
573
+
574
+static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name,
575
+ void *opaque, Error **errp)
576
+{
577
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
578
+}
579
+
580
+static void bbram_prop_release_drive(Object *obj, const char *name,
581
+ void *opaque)
582
+{
583
+ qdev_prop_drive.release(obj, name, opaque);
584
+}
585
+
586
+static const PropertyInfo bbram_prop_drive = {
587
+ .name = "str",
588
+ .description = "Node name or ID of a block device to use as BBRAM backend",
589
+ .realized_set_allowed = true,
590
+ .get = bbram_prop_get_drive,
591
+ .set = bbram_prop_set_drive,
592
+ .release = bbram_prop_release_drive,
491
+};
593
+};
492
+
594
+
493
+static const MemoryRegionOps allwinner_h3_dramphy_ops = {
595
+static const VMStateDescription vmstate_bbram_ctrl = {
494
+ .read = allwinner_h3_dramphy_read,
596
+ .name = TYPE_XLNX_BBRAM,
495
+ .write = allwinner_h3_dramphy_write,
496
+ .endianness = DEVICE_NATIVE_ENDIAN,
497
+ .valid = {
498
+ .min_access_size = 4,
499
+ .max_access_size = 4,
500
+ },
501
+ .impl.min_access_size = 4,
502
+};
503
+
504
+static void allwinner_h3_dramc_reset(DeviceState *dev)
505
+{
506
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
507
+
508
+ /* Set default values for registers */
509
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
510
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
511
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
512
+}
513
+
514
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
515
+{
516
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
517
+
518
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
519
+ for (uint8_t i = 8; i < 13; i++) {
520
+ if (1 << i == s->ram_size) {
521
+ break;
522
+ } else if (i == 12) {
523
+ error_report("%s: ram-size %u MiB is not supported",
524
+ __func__, s->ram_size);
525
+ exit(1);
526
+ }
527
+ }
528
+
529
+ /* Setup row mirror mappings */
530
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
531
+ "allwinner-h3-dramc.row-mirror",
532
+ 4 * KiB, &error_abort);
533
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
534
+ &s->row_mirror, 10);
535
+
536
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
537
+ "allwinner-h3-dramc.row-mirror-alias",
538
+ &s->row_mirror, 0, 4 * KiB);
539
+ memory_region_add_subregion_overlap(get_system_memory(),
540
+ s->ram_addr + 1 * MiB,
541
+ &s->row_mirror_alias, 10);
542
+ memory_region_set_enabled(&s->row_mirror_alias, false);
543
+}
544
+
545
+static void allwinner_h3_dramc_init(Object *obj)
546
+{
547
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
548
+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);
549
+
550
+ /* DRAMCOM registers */
551
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
552
+ &allwinner_h3_dramcom_ops, s,
553
+ TYPE_AW_H3_DRAMC, 4 * KiB);
554
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
555
+
556
+ /* DRAMCTL registers */
557
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
558
+ &allwinner_h3_dramctl_ops, s,
559
+ TYPE_AW_H3_DRAMC, 4 * KiB);
560
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
561
+
562
+ /* DRAMPHY registers */
563
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
564
+ &allwinner_h3_dramphy_ops, s,
565
+ TYPE_AW_H3_DRAMC, 4 * KiB);
566
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
567
+}
568
+
569
+static Property allwinner_h3_dramc_properties[] = {
570
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
571
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
572
+ DEFINE_PROP_END_OF_LIST()
573
+};
574
+
575
+static const VMStateDescription allwinner_h3_dramc_vmstate = {
576
+ .name = "allwinner-h3-dramc",
577
+ .version_id = 1,
597
+ .version_id = 1,
578
+ .minimum_version_id = 1,
598
+ .minimum_version_id = 1,
579
+ .fields = (VMStateField[]) {
599
+ .fields = (VMStateField[]) {
580
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
600
+ VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX),
581
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
601
+ VMSTATE_END_OF_LIST(),
582
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
583
+ VMSTATE_END_OF_LIST()
584
+ }
602
+ }
585
+};
603
+};
586
+
604
+
587
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
605
+static Property bbram_ctrl_props[] = {
606
+ DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *),
607
+ DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
608
+ DEFINE_PROP_END_OF_LIST(),
609
+};
610
+
611
+static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
588
+{
612
+{
589
+ DeviceClass *dc = DEVICE_CLASS(klass);
613
+ DeviceClass *dc = DEVICE_CLASS(klass);
590
+
614
+
591
+ dc->reset = allwinner_h3_dramc_reset;
615
+ dc->reset = bbram_ctrl_reset;
592
+ dc->vmsd = &allwinner_h3_dramc_vmstate;
616
+ dc->realize = bbram_ctrl_realize;
593
+ dc->realize = allwinner_h3_dramc_realize;
617
+ dc->vmsd = &vmstate_bbram_ctrl;
594
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
618
+ device_class_set_props(dc, bbram_ctrl_props);
595
+}
619
+}
596
+
620
+
597
+static const TypeInfo allwinner_h3_dramc_info = {
621
+static const TypeInfo bbram_ctrl_info = {
598
+ .name = TYPE_AW_H3_DRAMC,
622
+ .name = TYPE_XLNX_BBRAM,
599
+ .parent = TYPE_SYS_BUS_DEVICE,
623
+ .parent = TYPE_SYS_BUS_DEVICE,
600
+ .instance_init = allwinner_h3_dramc_init,
624
+ .instance_size = sizeof(XlnxBBRam),
601
+ .instance_size = sizeof(AwH3DramCtlState),
625
+ .class_init = bbram_ctrl_class_init,
602
+ .class_init = allwinner_h3_dramc_class_init,
626
+ .instance_init = bbram_ctrl_init,
603
+};
627
+};
604
+
628
+
605
+static void allwinner_h3_dramc_register(void)
629
+static void bbram_ctrl_register_types(void)
606
+{
630
+{
607
+ type_register_static(&allwinner_h3_dramc_info);
631
+ type_register_static(&bbram_ctrl_info);
608
+}
632
+}
609
+
633
+
610
+type_init(allwinner_h3_dramc_register)
634
+type_init(bbram_ctrl_register_types)
611
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
635
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
612
index XXXXXXX..XXXXXXX 100644
636
index XXXXXXX..XXXXXXX 100644
613
--- a/hw/misc/trace-events
637
--- a/hw/nvram/Kconfig
614
+++ b/hw/misc/trace-events
638
+++ b/hw/nvram/Kconfig
615
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
639
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_VERSAL
616
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
640
config XLNX_EFUSE_ZYNQMP
617
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
641
bool
618
642
select XLNX_EFUSE
619
+# allwinner-h3-dramc.c
643
+
620
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
644
+config XLNX_BBRAM
621
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
645
+ bool
622
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
646
+ select XLNX_EFUSE_CRC
623
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
647
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
624
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
648
index XXXXXXX..XXXXXXX 100644
625
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
649
--- a/hw/nvram/meson.build
626
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
650
+++ b/hw/nvram/meson.build
627
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
651
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
628
+
652
'xlnx-versal-efuse-ctrl.c'))
629
# allwinner-sid.c
653
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
630
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
654
'xlnx-zynqmp-efuse.c'))
631
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
655
+softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
656
657
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
632
--
658
--
633
2.20.1
659
2.20.1
634
660
635
661
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
3
Connect the support for Versal Battery-Backed RAM (BBRAM)
4
processor cores. Features and specifications include DDR2/DDR3 memory,
5
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
6
various I/O modules. This commit adds support for the Allwinner H3
7
System on Chip.
8
4
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
5
The command argument:
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
-drive if=pflash,index=0,...
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Can be used to optionally connect the bbram to a backend
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
storage, such that field-programmed values in one
13
Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
19
---
16
hw/arm/Makefile.objs | 1 +
20
include/hw/arm/xlnx-versal.h | 5 +++++
17
include/hw/arm/allwinner-h3.h | 106 +++++++++++
21
hw/arm/xlnx-versal-virt.c | 36 ++++++++++++++++++++++++++++++++++++
18
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
22
hw/arm/xlnx-versal.c | 18 ++++++++++++++++++
19
MAINTAINERS | 7 +
23
hw/arm/Kconfig | 1 +
20
default-configs/arm-softmmu.mak | 1 +
24
4 files changed, 60 insertions(+)
21
hw/arm/Kconfig | 8 +
22
6 files changed, 450 insertions(+)
23
create mode 100644 include/hw/arm/allwinner-h3.h
24
create mode 100644 hw/arm/allwinner-h3.c
25
25
26
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
26
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
27
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/Makefile.objs
28
--- a/include/hw/arm/xlnx-versal.h
29
+++ b/hw/arm/Makefile.objs
29
+++ b/include/hw/arm/xlnx-versal.h
30
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
31
obj-$(CONFIG_OMAP) += omap1.o omap2.o
32
obj-$(CONFIG_STRONGARM) += strongarm.o
33
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
39
new file mode 100644
40
index XXXXXXX..XXXXXXX
41
--- /dev/null
42
+++ b/include/hw/arm/allwinner-h3.h
43
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@
44
+/*
31
#include "qom/object.h"
45
+ * Allwinner H3 System on Chip emulation
32
#include "hw/usb/xlnx-usb-subsystem.h"
46
+ *
33
#include "hw/misc/xlnx-versal-xramc.h"
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
34
+#include "hw/nvram/xlnx-bbram.h"
48
+ *
35
49
+ * This program is free software: you can redistribute it and/or modify
36
#define TYPE_XLNX_VERSAL "xlnx-versal"
50
+ * it under the terms of the GNU General Public License as published by
37
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
51
+ * the Free Software Foundation, either version 2 of the License, or
38
@@ -XXX,XX +XXX,XX @@ struct Versal {
52
+ * (at your option) any later version.
39
} iou;
53
+ *
40
54
+ * This program is distributed in the hope that it will be useful,
41
XlnxZynqMPRTC rtc;
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
42
+ XlnxBBRam bbram;
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43
} pmc;
57
+ * GNU General Public License for more details.
44
58
+ *
45
struct {
59
+ * You should have received a copy of the GNU General Public License
46
@@ -XXX,XX +XXX,XX @@ struct Versal {
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
47
#define VERSAL_GEM1_WAKE_IRQ_0 59
61
+ */
48
#define VERSAL_ADMA_IRQ_0 60
49
#define VERSAL_XRAM_IRQ_0 79
50
+#define VERSAL_BBRAM_APB_IRQ_0 121
51
#define VERSAL_RTC_APB_ERR_IRQ 121
52
#define VERSAL_SD0_IRQ_0 126
53
#define VERSAL_RTC_ALARM_IRQ 142
54
@@ -XXX,XX +XXX,XX @@ struct Versal {
55
56
#define MM_PMC_SD0 0xf1040000U
57
#define MM_PMC_SD0_SIZE 0x10000
58
+#define MM_PMC_BBRAM_CTRL 0xf11f0000
59
+#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
60
#define MM_PMC_CRP 0xf1260000U
61
#define MM_PMC_CRP_SIZE 0x10000
62
#define MM_PMC_RTC 0xf12a0000
63
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/xlnx-versal-virt.c
66
+++ b/hw/arm/xlnx-versal-virt.c
67
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(VersalVirt *s)
68
g_free(name);
69
}
70
71
+static void fdt_add_bbram_node(VersalVirt *s)
72
+{
73
+ const char compat[] = TYPE_XLNX_BBRAM;
74
+ const char interrupt_names[] = "bbram-error";
75
+ char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL);
62
+
76
+
63
+/*
77
+ qemu_fdt_add_subnode(s->fdt, name);
64
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
65
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
66
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
67
+ * various I/O modules.
68
+ *
69
+ * This implementation is based on the following datasheet:
70
+ *
71
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
72
+ *
73
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
74
+ *
75
+ * https://linux-sunxi.org/H3
76
+ */
77
+
78
+
78
+#ifndef HW_ARM_ALLWINNER_H3_H
79
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
79
+#define HW_ARM_ALLWINNER_H3_H
80
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
80
+
81
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
81
+#include "qom/object.h"
82
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
82
+#include "hw/arm/boot.h"
83
+ interrupt_names, sizeof(interrupt_names));
83
+#include "hw/timer/allwinner-a10-pit.h"
84
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
84
+#include "hw/intc/arm_gic.h"
85
+ 2, MM_PMC_BBRAM_CTRL,
85
+#include "target/arm/cpu.h"
86
+ 2, MM_PMC_BBRAM_CTRL_SIZE);
86
+
87
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
87
+/**
88
+ g_free(name);
88
+ * Allwinner H3 device list
89
+ *
90
+ * This enumeration is can be used refer to a particular device in the
91
+ * Allwinner H3 SoC. For example, the physical memory base address for
92
+ * each device can be found in the AwH3State object in the memmap member
93
+ * using the device enum value as index.
94
+ *
95
+ * @see AwH3State
96
+ */
97
+enum {
98
+ AW_H3_SRAM_A1,
99
+ AW_H3_SRAM_A2,
100
+ AW_H3_SRAM_C,
101
+ AW_H3_PIT,
102
+ AW_H3_UART0,
103
+ AW_H3_UART1,
104
+ AW_H3_UART2,
105
+ AW_H3_UART3,
106
+ AW_H3_GIC_DIST,
107
+ AW_H3_GIC_CPU,
108
+ AW_H3_GIC_HYP,
109
+ AW_H3_GIC_VCPU,
110
+ AW_H3_SDRAM
111
+};
112
+
113
+/** Total number of CPU cores in the H3 SoC */
114
+#define AW_H3_NUM_CPUS (4)
115
+
116
+/**
117
+ * Allwinner H3 object model
118
+ * @{
119
+ */
120
+
121
+/** Object type for the Allwinner H3 SoC */
122
+#define TYPE_AW_H3 "allwinner-h3"
123
+
124
+/** Convert input object to Allwinner H3 state object */
125
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
126
+
127
+/** @} */
128
+
129
+/**
130
+ * Allwinner H3 object
131
+ *
132
+ * This struct contains the state of all the devices
133
+ * which are currently emulated by the H3 SoC code.
134
+ */
135
+typedef struct AwH3State {
136
+ /*< private >*/
137
+ DeviceState parent_obj;
138
+ /*< public >*/
139
+
140
+ ARMCPU cpus[AW_H3_NUM_CPUS];
141
+ const hwaddr *memmap;
142
+ AwA10PITState timer;
143
+ GICState gic;
144
+ MemoryRegion sram_a1;
145
+ MemoryRegion sram_a2;
146
+ MemoryRegion sram_c;
147
+} AwH3State;
148
+
149
+#endif /* HW_ARM_ALLWINNER_H3_H */
150
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
151
new file mode 100644
152
index XXXXXXX..XXXXXXX
153
--- /dev/null
154
+++ b/hw/arm/allwinner-h3.c
155
@@ -XXX,XX +XXX,XX @@
156
+/*
157
+ * Allwinner H3 System on Chip emulation
158
+ *
159
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
160
+ *
161
+ * This program is free software: you can redistribute it and/or modify
162
+ * it under the terms of the GNU General Public License as published by
163
+ * the Free Software Foundation, either version 2 of the License, or
164
+ * (at your option) any later version.
165
+ *
166
+ * This program is distributed in the hope that it will be useful,
167
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
168
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
169
+ * GNU General Public License for more details.
170
+ *
171
+ * You should have received a copy of the GNU General Public License
172
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
173
+ */
174
+
175
+#include "qemu/osdep.h"
176
+#include "exec/address-spaces.h"
177
+#include "qapi/error.h"
178
+#include "qemu/error-report.h"
179
+#include "qemu/module.h"
180
+#include "qemu/units.h"
181
+#include "hw/qdev-core.h"
182
+#include "cpu.h"
183
+#include "hw/sysbus.h"
184
+#include "hw/char/serial.h"
185
+#include "hw/misc/unimp.h"
186
+#include "sysemu/sysemu.h"
187
+#include "hw/arm/allwinner-h3.h"
188
+
189
+/* Memory map */
190
+const hwaddr allwinner_h3_memmap[] = {
191
+ [AW_H3_SRAM_A1] = 0x00000000,
192
+ [AW_H3_SRAM_A2] = 0x00044000,
193
+ [AW_H3_SRAM_C] = 0x00010000,
194
+ [AW_H3_PIT] = 0x01c20c00,
195
+ [AW_H3_UART0] = 0x01c28000,
196
+ [AW_H3_UART1] = 0x01c28400,
197
+ [AW_H3_UART2] = 0x01c28800,
198
+ [AW_H3_UART3] = 0x01c28c00,
199
+ [AW_H3_GIC_DIST] = 0x01c81000,
200
+ [AW_H3_GIC_CPU] = 0x01c82000,
201
+ [AW_H3_GIC_HYP] = 0x01c84000,
202
+ [AW_H3_GIC_VCPU] = 0x01c86000,
203
+ [AW_H3_SDRAM] = 0x40000000
204
+};
205
+
206
+/* List of unimplemented devices */
207
+struct AwH3Unimplemented {
208
+ const char *device_name;
209
+ hwaddr base;
210
+ hwaddr size;
211
+} unimplemented[] = {
212
+ { "d-engine", 0x01000000, 4 * MiB },
213
+ { "d-inter", 0x01400000, 128 * KiB },
214
+ { "syscon", 0x01c00000, 4 * KiB },
215
+ { "dma", 0x01c02000, 4 * KiB },
216
+ { "nfdc", 0x01c03000, 4 * KiB },
217
+ { "ts", 0x01c06000, 4 * KiB },
218
+ { "keymem", 0x01c0b000, 4 * KiB },
219
+ { "lcd0", 0x01c0c000, 4 * KiB },
220
+ { "lcd1", 0x01c0d000, 4 * KiB },
221
+ { "ve", 0x01c0e000, 4 * KiB },
222
+ { "mmc0", 0x01c0f000, 4 * KiB },
223
+ { "mmc1", 0x01c10000, 4 * KiB },
224
+ { "mmc2", 0x01c11000, 4 * KiB },
225
+ { "sid", 0x01c14000, 1 * KiB },
226
+ { "crypto", 0x01c15000, 4 * KiB },
227
+ { "msgbox", 0x01c17000, 4 * KiB },
228
+ { "spinlock", 0x01c18000, 4 * KiB },
229
+ { "usb0-otg", 0x01c19000, 4 * KiB },
230
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
231
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
232
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
233
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
234
+ { "smc", 0x01c1e000, 4 * KiB },
235
+ { "ccu", 0x01c20000, 1 * KiB },
236
+ { "pio", 0x01c20800, 1 * KiB },
237
+ { "owa", 0x01c21000, 1 * KiB },
238
+ { "pwm", 0x01c21400, 1 * KiB },
239
+ { "keyadc", 0x01c21800, 1 * KiB },
240
+ { "pcm0", 0x01c22000, 1 * KiB },
241
+ { "pcm1", 0x01c22400, 1 * KiB },
242
+ { "pcm2", 0x01c22800, 1 * KiB },
243
+ { "audio", 0x01c22c00, 2 * KiB },
244
+ { "smta", 0x01c23400, 1 * KiB },
245
+ { "ths", 0x01c25000, 1 * KiB },
246
+ { "uart0", 0x01c28000, 1 * KiB },
247
+ { "uart1", 0x01c28400, 1 * KiB },
248
+ { "uart2", 0x01c28800, 1 * KiB },
249
+ { "uart3", 0x01c28c00, 1 * KiB },
250
+ { "twi0", 0x01c2ac00, 1 * KiB },
251
+ { "twi1", 0x01c2b000, 1 * KiB },
252
+ { "twi2", 0x01c2b400, 1 * KiB },
253
+ { "scr", 0x01c2c400, 1 * KiB },
254
+ { "emac", 0x01c30000, 64 * KiB },
255
+ { "gpu", 0x01c40000, 64 * KiB },
256
+ { "hstmr", 0x01c60000, 4 * KiB },
257
+ { "dramcom", 0x01c62000, 4 * KiB },
258
+ { "dramctl0", 0x01c63000, 4 * KiB },
259
+ { "dramphy0", 0x01c65000, 4 * KiB },
260
+ { "spi0", 0x01c68000, 4 * KiB },
261
+ { "spi1", 0x01c69000, 4 * KiB },
262
+ { "csi", 0x01cb0000, 320 * KiB },
263
+ { "tve", 0x01e00000, 64 * KiB },
264
+ { "hdmi", 0x01ee0000, 128 * KiB },
265
+ { "rtc", 0x01f00000, 1 * KiB },
266
+ { "r_timer", 0x01f00800, 1 * KiB },
267
+ { "r_intc", 0x01f00c00, 1 * KiB },
268
+ { "r_wdog", 0x01f01000, 1 * KiB },
269
+ { "r_prcm", 0x01f01400, 1 * KiB },
270
+ { "r_twd", 0x01f01800, 1 * KiB },
271
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
272
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
273
+ { "r_twi", 0x01f02400, 1 * KiB },
274
+ { "r_uart", 0x01f02800, 1 * KiB },
275
+ { "r_pio", 0x01f02c00, 1 * KiB },
276
+ { "r_pwm", 0x01f03800, 1 * KiB },
277
+ { "core-dbg", 0x3f500000, 128 * KiB },
278
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
279
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
280
+ { "ddr-mem", 0x40000000, 2 * GiB },
281
+ { "n-brom", 0xffff0000, 32 * KiB },
282
+ { "s-brom", 0xffff0000, 64 * KiB }
283
+};
284
+
285
+/* Per Processor Interrupts */
286
+enum {
287
+ AW_H3_GIC_PPI_MAINT = 9,
288
+ AW_H3_GIC_PPI_HYPTIMER = 10,
289
+ AW_H3_GIC_PPI_VIRTTIMER = 11,
290
+ AW_H3_GIC_PPI_SECTIMER = 13,
291
+ AW_H3_GIC_PPI_PHYSTIMER = 14
292
+};
293
+
294
+/* Shared Processor Interrupts */
295
+enum {
296
+ AW_H3_GIC_SPI_UART0 = 0,
297
+ AW_H3_GIC_SPI_UART1 = 1,
298
+ AW_H3_GIC_SPI_UART2 = 2,
299
+ AW_H3_GIC_SPI_UART3 = 3,
300
+ AW_H3_GIC_SPI_TIMER0 = 18,
301
+ AW_H3_GIC_SPI_TIMER1 = 19,
302
+};
303
+
304
+/* Allwinner H3 general constants */
305
+enum {
306
+ AW_H3_GIC_NUM_SPI = 128
307
+};
308
+
309
+static void allwinner_h3_init(Object *obj)
310
+{
311
+ AwH3State *s = AW_H3(obj);
312
+
313
+ s->memmap = allwinner_h3_memmap;
314
+
315
+ for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
316
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
317
+ ARM_CPU_TYPE_NAME("cortex-a7"),
318
+ &error_abort, NULL);
319
+ }
320
+
321
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
322
+ TYPE_ARM_GIC);
323
+
324
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
325
+ TYPE_AW_A10_PIT);
326
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
327
+ "clk0-freq", &error_abort);
328
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
329
+ "clk1-freq", &error_abort);
330
+}
89
+}
331
+
90
+
332
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
91
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
92
{
93
Error *err = NULL;
94
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
95
}
96
}
97
98
+static void bbram_attach_drive(XlnxBBRam *dev)
333
+{
99
+{
334
+ AwH3State *s = AW_H3(dev);
100
+ DriveInfo *dinfo;
335
+ unsigned i;
101
+ BlockBackend *blk;
336
+
102
+
337
+ /* CPUs */
103
+ dinfo = drive_get_by_index(IF_PFLASH, 0);
338
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
104
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
339
+
105
+ if (blk) {
340
+ /* Provide Power State Coordination Interface */
106
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
341
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
342
+ QEMU_PSCI_CONDUIT_HVC);
343
+
344
+ /* Disable secondary CPUs */
345
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
346
+ i > 0);
347
+
348
+ /* All exception levels required */
349
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
350
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
351
+
352
+ /* Mark realized */
353
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
354
+ }
355
+
356
+ /* Generic Interrupt Controller */
357
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
358
+ GIC_INTERNAL);
359
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
360
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
361
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
362
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
363
+ qdev_init_nofail(DEVICE(&s->gic));
364
+
365
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
366
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
367
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
368
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
369
+
370
+ /*
371
+ * Wire the outputs from each CPU's generic timer and the GICv3
372
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
373
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
374
+ */
375
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
376
+ DeviceState *cpudev = DEVICE(&s->cpus[i]);
377
+ int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
378
+ int irq;
379
+ /*
380
+ * Mapping from the output timer irq lines from the CPU to the
381
+ * GIC PPI inputs used for this board.
382
+ */
383
+ const int timer_irq[] = {
384
+ [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
385
+ [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
386
+ [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
387
+ [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
388
+ };
389
+
390
+ /* Connect CPU timer outputs to GIC PPI inputs */
391
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
392
+ qdev_connect_gpio_out(cpudev, irq,
393
+ qdev_get_gpio_in(DEVICE(&s->gic),
394
+ ppibase + timer_irq[irq]));
395
+ }
396
+
397
+ /* Connect GIC outputs to CPU interrupt inputs */
398
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
399
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
400
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
401
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
402
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
403
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
404
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
405
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
406
+
407
+ /* GIC maintenance signal */
408
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
409
+ qdev_get_gpio_in(DEVICE(&s->gic),
410
+ ppibase + AW_H3_GIC_PPI_MAINT));
411
+ }
412
+
413
+ /* Timer */
414
+ qdev_init_nofail(DEVICE(&s->timer));
415
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
416
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
417
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
418
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
419
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
420
+
421
+ /* SRAM */
422
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
423
+ 64 * KiB, &error_abort);
424
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
425
+ 32 * KiB, &error_abort);
426
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
427
+ 44 * KiB, &error_abort);
428
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
429
+ &s->sram_a1);
430
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
431
+ &s->sram_a2);
432
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
433
+ &s->sram_c);
434
+
435
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
436
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
437
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
438
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
439
+ /* UART1 */
440
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
441
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
442
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
443
+ /* UART2 */
444
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
445
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
446
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
447
+ /* UART3 */
448
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
449
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
450
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
451
+
452
+ /* Unimplemented devices */
453
+ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
454
+ create_unimplemented_device(unimplemented[i].device_name,
455
+ unimplemented[i].base,
456
+ unimplemented[i].size);
457
+ }
107
+ }
458
+}
108
+}
459
+
109
+
460
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
110
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
111
{
112
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
113
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
114
fdt_add_usb_xhci_nodes(s);
115
fdt_add_sd_nodes(s);
116
fdt_add_rtc_node(s);
117
+ fdt_add_bbram_node(s);
118
fdt_add_cpu_nodes(s, psci_conduit);
119
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
120
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
121
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
122
memory_region_add_subregion_overlap(get_system_memory(),
123
0, &s->soc.fpd.apu.mr, 0);
124
125
+ /* Attach bbram backend, if given */
126
+ bbram_attach_drive(&s->soc.pmc.bbram);
127
+
128
/* Plugin SD cards. */
129
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
130
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
131
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/arm/xlnx-versal.c
134
+++ b/hw/arm/xlnx-versal.c
135
@@ -XXX,XX +XXX,XX @@ static void versal_create_xrams(Versal *s, qemu_irq *pic)
136
}
137
}
138
139
+static void versal_create_bbram(Versal *s, qemu_irq *pic)
461
+{
140
+{
462
+ DeviceClass *dc = DEVICE_CLASS(oc);
141
+ SysBusDevice *sbd;
463
+
142
+
464
+ dc->realize = allwinner_h3_realize;
143
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
465
+ /* Reason: uses serial_hd() in realize function */
144
+ sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
466
+ dc->user_creatable = false;
145
+ &error_fatal,
146
+ "crc-zpads", "0",
147
+ NULL);
148
+ sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
149
+
150
+ sysbus_realize(sbd, &error_fatal);
151
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
152
+ sysbus_mmio_get_region(sbd, 0));
153
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
467
+}
154
+}
468
+
155
+
469
+static const TypeInfo allwinner_h3_type_info = {
156
/* This takes the board allocated linear DDR memory and creates aliases
470
+ .name = TYPE_AW_H3,
157
* for each split DDR range/aperture on the Versal address map.
471
+ .parent = TYPE_DEVICE,
158
*/
472
+ .instance_size = sizeof(AwH3State),
159
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
473
+ .instance_init = allwinner_h3_init,
160
versal_create_sds(s, pic);
474
+ .class_init = allwinner_h3_class_init,
161
versal_create_rtc(s, pic);
475
+};
162
versal_create_xrams(s, pic);
476
+
163
+ versal_create_bbram(s, pic);
477
+static void allwinner_h3_register_types(void)
164
versal_map_ddr(s);
478
+{
165
versal_unimp(s);
479
+ type_register_static(&allwinner_h3_type_info);
166
480
+}
481
+
482
+type_init(allwinner_h3_register_types)
483
diff --git a/MAINTAINERS b/MAINTAINERS
484
index XXXXXXX..XXXXXXX 100644
485
--- a/MAINTAINERS
486
+++ b/MAINTAINERS
487
@@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner*
488
F: include/hw/*/allwinner*
489
F: hw/arm/cubieboard.c
490
491
+Allwinner-h3
492
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
493
+L: qemu-arm@nongnu.org
494
+S: Maintained
495
+F: hw/*/allwinner-h3*
496
+F: include/hw/*/allwinner-h3*
497
+
498
ARM PrimeCell and CMSDK devices
499
M: Peter Maydell <peter.maydell@linaro.org>
500
L: qemu-arm@nongnu.org
501
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
502
index XXXXXXX..XXXXXXX 100644
503
--- a/default-configs/arm-softmmu.mak
504
+++ b/default-configs/arm-softmmu.mak
505
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y
506
CONFIG_FSL_IMX7=y
507
CONFIG_FSL_IMX6UL=y
508
CONFIG_SEMIHOSTING=y
509
+CONFIG_ALLWINNER_H3=y
510
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
167
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
511
index XXXXXXX..XXXXXXX 100644
168
index XXXXXXX..XXXXXXX 100644
512
--- a/hw/arm/Kconfig
169
--- a/hw/arm/Kconfig
513
+++ b/hw/arm/Kconfig
170
+++ b/hw/arm/Kconfig
514
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
171
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
515
select SERIAL
172
select XLNX_ZDMA
516
select UNIMP
173
select XLNX_ZYNQMP
517
174
select OR_IRQ
518
+config ALLWINNER_H3
175
+ select XLNX_BBRAM
519
+ bool
176
520
+ select ALLWINNER_A10_PIT
177
config NPCM7XX
521
+ select SERIAL
522
+ select ARM_TIMER
523
+ select ARM_GIC
524
+ select UNIMP
525
+
526
config RASPI
527
bool
178
bool
528
select FRAMEBUFFER
529
--
179
--
530
2.20.1
180
2.20.1
531
181
532
182
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
3
Connect the support for Versal eFUSE one-time field-programmable
4
which provides 10M/100M/1000M Ethernet connectivity. This commit
4
bit array.
5
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
5
6
including emulation for the following functionality:
6
The command argument:
7
7
-drive if=pflash,index=1,...
8
* DMA transfers
8
Can be used to optionally connect the bit array to a
9
* MII interface
9
backend storage, such that field-programmed values
10
* Transmit CRC calculation
10
in one invocation can be made available to next
11
11
invocation.
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
The backend storage must be a seekable binary file, and
14
Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com
14
its size must be 3072 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
21
---
17
hw/net/Makefile.objs | 1 +
22
include/hw/arm/xlnx-versal.h | 10 +++++++
18
include/hw/arm/allwinner-h3.h | 3 +
23
hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++
19
include/hw/net/allwinner-sun8i-emac.h | 99 +++
24
hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++
20
hw/arm/allwinner-h3.c | 16 +-
25
hw/arm/Kconfig | 1 +
21
hw/arm/orangepi.c | 3 +
26
4 files changed, 102 insertions(+)
22
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
27
23
hw/arm/Kconfig | 1 +
28
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
24
hw/net/Kconfig | 3 +
29
index XXXXXXX..XXXXXXX 100644
25
hw/net/trace-events | 10 +
30
--- a/include/hw/arm/xlnx-versal.h
26
9 files changed, 1006 insertions(+), 1 deletion(-)
31
+++ b/include/hw/arm/xlnx-versal.h
27
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
28
create mode 100644 hw/net/allwinner-sun8i-emac.c
29
30
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/net/Makefile.objs
33
+++ b/hw/net/Makefile.objs
34
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
35
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
36
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
37
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
38
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
39
common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
40
41
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
42
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/include/hw/arm/allwinner-h3.h
45
+++ b/include/hw/arm/allwinner-h3.h
46
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
47
#include "hw/misc/allwinner-h3-sysctrl.h"
33
#include "hw/usb/xlnx-usb-subsystem.h"
48
#include "hw/misc/allwinner-sid.h"
34
#include "hw/misc/xlnx-versal-xramc.h"
49
#include "hw/sd/allwinner-sdhost.h"
35
#include "hw/nvram/xlnx-bbram.h"
50
+#include "hw/net/allwinner-sun8i-emac.h"
36
+#include "hw/nvram/xlnx-versal-efuse.h"
51
#include "target/arm/cpu.h"
37
52
38
#define TYPE_XLNX_VERSAL "xlnx-versal"
53
/**
39
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
54
@@ -XXX,XX +XXX,XX @@ enum {
40
@@ -XXX,XX +XXX,XX @@ struct Versal {
55
AW_H3_UART1,
41
56
AW_H3_UART2,
42
XlnxZynqMPRTC rtc;
57
AW_H3_UART3,
43
XlnxBBRam bbram;
58
+ AW_H3_EMAC,
44
+ XlnxEFuse efuse;
59
AW_H3_GIC_DIST,
45
+ XlnxVersalEFuseCtrl efuse_ctrl;
60
AW_H3_GIC_CPU,
46
+ XlnxVersalEFuseCache efuse_cache;
61
AW_H3_GIC_HYP,
47
} pmc;
62
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
48
63
AwH3SysCtrlState sysctrl;
49
struct {
64
AwSidState sid;
50
@@ -XXX,XX +XXX,XX @@ struct Versal {
65
AwSdHostState mmc0;
51
#define VERSAL_BBRAM_APB_IRQ_0 121
66
+ AwSun8iEmacState emac;
52
#define VERSAL_RTC_APB_ERR_IRQ 121
67
GICState gic;
53
#define VERSAL_SD0_IRQ_0 126
68
MemoryRegion sram_a1;
54
+#define VERSAL_EFUSE_IRQ 139
69
MemoryRegion sram_a2;
55
#define VERSAL_RTC_ALARM_IRQ 142
70
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
56
#define VERSAL_RTC_SECONDS_IRQ 143
71
new file mode 100644
57
72
index XXXXXXX..XXXXXXX
58
@@ -XXX,XX +XXX,XX @@ struct Versal {
73
--- /dev/null
59
#define MM_PMC_SD0_SIZE 0x10000
74
+++ b/include/hw/net/allwinner-sun8i-emac.h
60
#define MM_PMC_BBRAM_CTRL 0xf11f0000
75
@@ -XXX,XX +XXX,XX @@
61
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
76
+/*
62
+#define MM_PMC_EFUSE_CTRL 0xf1240000
77
+ * Allwinner Sun8i Ethernet MAC emulation
63
+#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
78
+ *
64
+#define MM_PMC_EFUSE_CACHE 0xf1250000
79
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
65
+#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
80
+ *
66
+
81
+ * This program is free software: you can redistribute it and/or modify
67
#define MM_PMC_CRP 0xf1260000U
82
+ * it under the terms of the GNU General Public License as published by
68
#define MM_PMC_CRP_SIZE 0x10000
83
+ * the Free Software Foundation, either version 2 of the License, or
69
#define MM_PMC_RTC 0xf12a0000
84
+ * (at your option) any later version.
70
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
85
+ *
71
index XXXXXXX..XXXXXXX 100644
86
+ * This program is distributed in the hope that it will be useful,
72
--- a/hw/arm/xlnx-versal-virt.c
87
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
73
+++ b/hw/arm/xlnx-versal-virt.c
88
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
74
@@ -XXX,XX +XXX,XX @@ static void fdt_add_bbram_node(VersalVirt *s)
89
+ * GNU General Public License for more details.
75
g_free(name);
90
+ *
91
+ * You should have received a copy of the GNU General Public License
92
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
93
+ */
94
+
95
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
96
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
97
+
98
+#include "qom/object.h"
99
+#include "net/net.h"
100
+#include "hw/sysbus.h"
101
+
102
+/**
103
+ * Object model
104
+ * @{
105
+ */
106
+
107
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
108
+#define AW_SUN8I_EMAC(obj) \
109
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
110
+
111
+/** @} */
112
+
113
+/**
114
+ * Allwinner Sun8i EMAC object instance state
115
+ */
116
+typedef struct AwSun8iEmacState {
117
+ /*< private >*/
118
+ SysBusDevice parent_obj;
119
+ /*< public >*/
120
+
121
+ /** Maps I/O registers in physical memory */
122
+ MemoryRegion iomem;
123
+
124
+ /** Interrupt output signal to notify CPU */
125
+ qemu_irq irq;
126
+
127
+ /** Generic Network Interface Controller (NIC) for networking API */
128
+ NICState *nic;
129
+
130
+ /** Generic Network Interface Controller (NIC) configuration */
131
+ NICConf conf;
132
+
133
+ /**
134
+ * @name Media Independent Interface (MII)
135
+ * @{
136
+ */
137
+
138
+ uint8_t mii_phy_addr; /**< PHY address */
139
+ uint32_t mii_cr; /**< Control */
140
+ uint32_t mii_st; /**< Status */
141
+ uint32_t mii_adv; /**< Advertised Abilities */
142
+
143
+ /** @} */
144
+
145
+ /**
146
+ * @name Hardware Registers
147
+ * @{
148
+ */
149
+
150
+ uint32_t basic_ctl0; /**< Basic Control 0 */
151
+ uint32_t basic_ctl1; /**< Basic Control 1 */
152
+ uint32_t int_en; /**< Interrupt Enable */
153
+ uint32_t int_sta; /**< Interrupt Status */
154
+ uint32_t frm_flt; /**< Receive Frame Filter */
155
+
156
+ uint32_t rx_ctl0; /**< Receive Control 0 */
157
+ uint32_t rx_ctl1; /**< Receive Control 1 */
158
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
159
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
160
+
161
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
162
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
163
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
164
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
165
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
166
+
167
+ uint32_t mii_cmd; /**< Management Interface Command */
168
+ uint32_t mii_data; /**< Management Interface Data */
169
+
170
+ /** @} */
171
+
172
+} AwSun8iEmacState;
173
+
174
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
175
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/arm/allwinner-h3.c
178
+++ b/hw/arm/allwinner-h3.c
179
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
180
[AW_H3_UART1] = 0x01c28400,
181
[AW_H3_UART2] = 0x01c28800,
182
[AW_H3_UART3] = 0x01c28c00,
183
+ [AW_H3_EMAC] = 0x01c30000,
184
[AW_H3_GIC_DIST] = 0x01c81000,
185
[AW_H3_GIC_CPU] = 0x01c82000,
186
[AW_H3_GIC_HYP] = 0x01c84000,
187
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
188
{ "twi1", 0x01c2b000, 1 * KiB },
189
{ "twi2", 0x01c2b400, 1 * KiB },
190
{ "scr", 0x01c2c400, 1 * KiB },
191
- { "emac", 0x01c30000, 64 * KiB },
192
{ "gpu", 0x01c40000, 64 * KiB },
193
{ "hstmr", 0x01c60000, 4 * KiB },
194
{ "dramcom", 0x01c62000, 4 * KiB },
195
@@ -XXX,XX +XXX,XX @@ enum {
196
AW_H3_GIC_SPI_OHCI2 = 77,
197
AW_H3_GIC_SPI_EHCI3 = 78,
198
AW_H3_GIC_SPI_OHCI3 = 79,
199
+ AW_H3_GIC_SPI_EMAC = 82
200
};
201
202
/* Allwinner H3 general constants */
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
206
TYPE_AW_SDHOST_SUN5I);
207
+
208
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
209
+ TYPE_AW_SUN8I_EMAC);
210
}
76
}
211
77
212
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
78
+static void fdt_add_efuse_ctrl_node(VersalVirt *s)
213
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
79
+{
214
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
80
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL;
215
"sd-bus", &error_abort);
81
+ const char interrupt_names[] = "pmc_efuse";
216
82
+ char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL);
217
+ /* EMAC */
83
+
218
+ if (nd_table[0].used) {
84
+ qemu_fdt_add_subnode(s->fdt, name);
219
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
85
+
220
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
86
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
87
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ,
88
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
89
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
90
+ interrupt_names, sizeof(interrupt_names));
91
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
92
+ 2, MM_PMC_EFUSE_CTRL,
93
+ 2, MM_PMC_EFUSE_CTRL_SIZE);
94
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
95
+ g_free(name);
96
+}
97
+
98
+static void fdt_add_efuse_cache_node(VersalVirt *s)
99
+{
100
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE;
101
+ char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x",
102
+ MM_PMC_EFUSE_CACHE);
103
+
104
+ qemu_fdt_add_subnode(s->fdt, name);
105
+
106
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
107
+ 2, MM_PMC_EFUSE_CACHE,
108
+ 2, MM_PMC_EFUSE_CACHE_SIZE);
109
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
110
+ g_free(name);
111
+}
112
+
113
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
114
{
115
Error *err = NULL;
116
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
117
}
118
}
119
120
+static void efuse_attach_drive(XlnxEFuse *dev)
121
+{
122
+ DriveInfo *dinfo;
123
+ BlockBackend *blk;
124
+
125
+ dinfo = drive_get_by_index(IF_PFLASH, 1);
126
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
127
+ if (blk) {
128
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
221
+ }
129
+ }
222
+ qdev_init_nofail(DEVICE(&s->emac));
130
+}
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
131
+
224
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
132
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
225
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
133
{
226
+
134
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
227
/* Universal Serial Bus */
135
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
228
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
136
fdt_add_sd_nodes(s);
229
qdev_get_gpio_in(DEVICE(&s->gic),
137
fdt_add_rtc_node(s);
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
138
fdt_add_bbram_node(s);
231
index XXXXXXX..XXXXXXX 100644
139
+ fdt_add_efuse_ctrl_node(s);
232
--- a/hw/arm/orangepi.c
140
+ fdt_add_efuse_cache_node(s);
233
+++ b/hw/arm/orangepi.c
141
fdt_add_cpu_nodes(s, psci_conduit);
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
142
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
235
warn_report("Security Identifier value does not include H3 prefix");
143
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
236
}
144
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
237
145
/* Attach bbram backend, if given */
238
+ /* Setup EMAC properties */
146
bbram_attach_drive(&s->soc.pmc.bbram);
239
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
147
240
+
148
+ /* Attach efuse backend, if given */
241
/* Mark H3 object realized */
149
+ efuse_attach_drive(&s->soc.pmc.efuse);
242
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
150
+
243
151
/* Plugin SD cards. */
244
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
152
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
245
new file mode 100644
153
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
246
index XXXXXXX..XXXXXXX
154
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
247
--- /dev/null
155
index XXXXXXX..XXXXXXX 100644
248
+++ b/hw/net/allwinner-sun8i-emac.c
156
--- a/hw/arm/xlnx-versal.c
249
@@ -XXX,XX +XXX,XX @@
157
+++ b/hw/arm/xlnx-versal.c
250
+/*
158
@@ -XXX,XX +XXX,XX @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
251
+ * Allwinner Sun8i Ethernet MAC emulation
159
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
252
+ *
160
}
253
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
161
254
+ *
162
+static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
255
+ * This program is free software: you can redistribute it and/or modify
163
+{
256
+ * it under the terms of the GNU General Public License as published by
164
+ SysBusDevice *part = SYS_BUS_DEVICE(dev);
257
+ * the Free Software Foundation, either version 2 of the License, or
165
+
258
+ * (at your option) any later version.
166
+ object_property_set_link(OBJECT(part), "efuse",
259
+ *
167
+ OBJECT(&s->pmc.efuse), &error_abort);
260
+ * This program is distributed in the hope that it will be useful,
168
+
261
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
169
+ sysbus_realize(part, &error_abort);
262
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
170
+ memory_region_add_subregion(&s->mr_ps, base,
263
+ * GNU General Public License for more details.
171
+ sysbus_mmio_get_region(part, 0));
264
+ *
172
+}
265
+ * You should have received a copy of the GNU General Public License
173
+
266
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
174
+static void versal_create_efuse(Versal *s, qemu_irq *pic)
267
+ */
175
+{
268
+
176
+ Object *bits = OBJECT(&s->pmc.efuse);
269
+#include "qemu/osdep.h"
177
+ Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
270
+#include "qemu/units.h"
178
+ Object *cache = OBJECT(&s->pmc.efuse_cache);
271
+#include "hw/sysbus.h"
179
+
272
+#include "migration/vmstate.h"
180
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
273
+#include "net/net.h"
181
+ TYPE_XLNX_VERSAL_EFUSE_CTRL);
274
+#include "hw/irq.h"
182
+
275
+#include "hw/qdev-properties.h"
183
+ object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
276
+#include "qemu/log.h"
184
+ TYPE_XLNX_VERSAL_EFUSE_CACHE);
277
+#include "trace.h"
185
+
278
+#include "net/checksum.h"
186
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
279
+#include "qemu/module.h"
187
+ sizeof(s->pmc.efuse),
280
+#include "exec/cpu-common.h"
188
+ TYPE_XLNX_EFUSE, &error_abort,
281
+#include "hw/net/allwinner-sun8i-emac.h"
189
+ "efuse-nr", "3",
282
+
190
+ "efuse-size", "8192",
283
+/* EMAC register offsets */
191
+ NULL);
284
+enum {
192
+
285
+ REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */
193
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
286
+ REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */
194
+ versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
287
+ REG_INT_STA = 0x0008, /* Interrupt Status */
195
+ versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
288
+ REG_INT_EN = 0x000C, /* Interrupt Enable */
196
+
289
+ REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
197
+ sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
290
+ REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
198
+}
291
+ REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
199
+
292
+ REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
200
/* This takes the board allocated linear DDR memory and creates aliases
293
+ REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
201
* for each split DDR range/aperture on the Versal address map.
294
+ REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
202
*/
295
+ REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
203
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
296
+ REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
204
versal_create_rtc(s, pic);
297
+ REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
205
versal_create_xrams(s, pic);
298
+ REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
206
versal_create_bbram(s, pic);
299
+ REG_MII_CMD = 0x0048, /* Management Interface Command */
207
+ versal_create_efuse(s, pic);
300
+ REG_MII_DATA = 0x004C, /* Management Interface Data */
208
versal_map_ddr(s);
301
+ REG_ADDR_HIGH = 0x0050, /* MAC Address High */
209
versal_unimp(s);
302
+ REG_ADDR_LOW = 0x0054, /* MAC Address Low */
210
303
+ REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
304
+ REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
305
+ REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
306
+ REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
307
+ REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
308
+ REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
309
+ REG_RGMII_STA = 0x00D0, /* RGMII Status */
310
+};
311
+
312
+/* EMAC register flags */
313
+enum {
314
+ BASIC_CTL0_100Mbps = (0b11 << 2),
315
+ BASIC_CTL0_FD = (1 << 0),
316
+ BASIC_CTL1_SOFTRST = (1 << 0),
317
+};
318
+
319
+enum {
320
+ INT_STA_RGMII_LINK = (1 << 16),
321
+ INT_STA_RX_EARLY = (1 << 13),
322
+ INT_STA_RX_OVERFLOW = (1 << 12),
323
+ INT_STA_RX_TIMEOUT = (1 << 11),
324
+ INT_STA_RX_DMA_STOP = (1 << 10),
325
+ INT_STA_RX_BUF_UA = (1 << 9),
326
+ INT_STA_RX = (1 << 8),
327
+ INT_STA_TX_EARLY = (1 << 5),
328
+ INT_STA_TX_UNDERFLOW = (1 << 4),
329
+ INT_STA_TX_TIMEOUT = (1 << 3),
330
+ INT_STA_TX_BUF_UA = (1 << 2),
331
+ INT_STA_TX_DMA_STOP = (1 << 1),
332
+ INT_STA_TX = (1 << 0),
333
+};
334
+
335
+enum {
336
+ INT_EN_RX_EARLY = (1 << 13),
337
+ INT_EN_RX_OVERFLOW = (1 << 12),
338
+ INT_EN_RX_TIMEOUT = (1 << 11),
339
+ INT_EN_RX_DMA_STOP = (1 << 10),
340
+ INT_EN_RX_BUF_UA = (1 << 9),
341
+ INT_EN_RX = (1 << 8),
342
+ INT_EN_TX_EARLY = (1 << 5),
343
+ INT_EN_TX_UNDERFLOW = (1 << 4),
344
+ INT_EN_TX_TIMEOUT = (1 << 3),
345
+ INT_EN_TX_BUF_UA = (1 << 2),
346
+ INT_EN_TX_DMA_STOP = (1 << 1),
347
+ INT_EN_TX = (1 << 0),
348
+};
349
+
350
+enum {
351
+ TX_CTL0_TX_EN = (1 << 31),
352
+ TX_CTL1_TX_DMA_START = (1 << 31),
353
+ TX_CTL1_TX_DMA_EN = (1 << 30),
354
+ TX_CTL1_TX_FLUSH = (1 << 0),
355
+};
356
+
357
+enum {
358
+ RX_CTL0_RX_EN = (1 << 31),
359
+ RX_CTL0_STRIP_FCS = (1 << 28),
360
+ RX_CTL0_CRC_IPV4 = (1 << 27),
361
+};
362
+
363
+enum {
364
+ RX_CTL1_RX_DMA_START = (1 << 31),
365
+ RX_CTL1_RX_DMA_EN = (1 << 30),
366
+ RX_CTL1_RX_MD = (1 << 1),
367
+};
368
+
369
+enum {
370
+ RX_FRM_FLT_DIS_ADDR = (1 << 31),
371
+};
372
+
373
+enum {
374
+ MII_CMD_PHY_ADDR_SHIFT = (12),
375
+ MII_CMD_PHY_ADDR_MASK = (0xf000),
376
+ MII_CMD_PHY_REG_SHIFT = (4),
377
+ MII_CMD_PHY_REG_MASK = (0xf0),
378
+ MII_CMD_PHY_RW = (1 << 1),
379
+ MII_CMD_PHY_BUSY = (1 << 0),
380
+};
381
+
382
+enum {
383
+ TX_DMA_STA_STOP = (0b000),
384
+ TX_DMA_STA_RUN_FETCH = (0b001),
385
+ TX_DMA_STA_WAIT_STA = (0b010),
386
+};
387
+
388
+enum {
389
+ RX_DMA_STA_STOP = (0b000),
390
+ RX_DMA_STA_RUN_FETCH = (0b001),
391
+ RX_DMA_STA_WAIT_FRM = (0b011),
392
+};
393
+
394
+/* EMAC register reset values */
395
+enum {
396
+ REG_BASIC_CTL_1_RST = 0x08000000,
397
+};
398
+
399
+/* EMAC constants */
400
+enum {
401
+ AW_SUN8I_EMAC_MIN_PKT_SZ = 64
402
+};
403
+
404
+/* Transmit/receive frame descriptor */
405
+typedef struct FrameDescriptor {
406
+ uint32_t status;
407
+ uint32_t status2;
408
+ uint32_t addr;
409
+ uint32_t next;
410
+} FrameDescriptor;
411
+
412
+/* Frame descriptor flags */
413
+enum {
414
+ DESC_STATUS_CTL = (1 << 31),
415
+ DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
416
+};
417
+
418
+/* Transmit frame descriptor flags */
419
+enum {
420
+ TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
421
+ TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
422
+ TX_DESC_STATUS2_LAST_DESC = (1 << 30),
423
+ TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
424
+};
425
+
426
+/* Receive frame descriptor flags */
427
+enum {
428
+ RX_DESC_STATUS_FIRST_DESC = (1 << 9),
429
+ RX_DESC_STATUS_LAST_DESC = (1 << 8),
430
+ RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
431
+ RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
432
+ RX_DESC_STATUS_NO_BUF = (1 << 14),
433
+ RX_DESC_STATUS_HEADER_ERR = (1 << 7),
434
+ RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
435
+ RX_DESC_STATUS_CRC_ERR = (1 << 1),
436
+ RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
437
+ RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
438
+};
439
+
440
+/* MII register offsets */
441
+enum {
442
+ MII_REG_CR = (0x0), /* Control */
443
+ MII_REG_ST = (0x1), /* Status */
444
+ MII_REG_ID_HIGH = (0x2), /* Identifier High */
445
+ MII_REG_ID_LOW = (0x3), /* Identifier Low */
446
+ MII_REG_ADV = (0x4), /* Advertised abilities */
447
+ MII_REG_LPA = (0x5), /* Link partner abilities */
448
+};
449
+
450
+/* MII register flags */
451
+enum {
452
+ MII_REG_CR_RESET = (1 << 15),
453
+ MII_REG_CR_POWERDOWN = (1 << 11),
454
+ MII_REG_CR_10Mbit = (0),
455
+ MII_REG_CR_100Mbit = (1 << 13),
456
+ MII_REG_CR_1000Mbit = (1 << 6),
457
+ MII_REG_CR_AUTO_NEG = (1 << 12),
458
+ MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
459
+ MII_REG_CR_FULLDUPLEX = (1 << 8),
460
+};
461
+
462
+enum {
463
+ MII_REG_ST_100BASE_T4 = (1 << 15),
464
+ MII_REG_ST_100BASE_X_FD = (1 << 14),
465
+ MII_REG_ST_100BASE_X_HD = (1 << 13),
466
+ MII_REG_ST_10_FD = (1 << 12),
467
+ MII_REG_ST_10_HD = (1 << 11),
468
+ MII_REG_ST_100BASE_T2_FD = (1 << 10),
469
+ MII_REG_ST_100BASE_T2_HD = (1 << 9),
470
+ MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
471
+ MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
472
+ MII_REG_ST_LINK_UP = (1 << 2),
473
+};
474
+
475
+enum {
476
+ MII_REG_LPA_10_HD = (1 << 5),
477
+ MII_REG_LPA_10_FD = (1 << 6),
478
+ MII_REG_LPA_100_HD = (1 << 7),
479
+ MII_REG_LPA_100_FD = (1 << 8),
480
+ MII_REG_LPA_PAUSE = (1 << 10),
481
+ MII_REG_LPA_ASYMPAUSE = (1 << 11),
482
+};
483
+
484
+/* MII constants */
485
+enum {
486
+ MII_PHY_ID_HIGH = 0x0044,
487
+ MII_PHY_ID_LOW = 0x1400,
488
+};
489
+
490
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
491
+ bool link_active)
492
+{
493
+ if (link_active) {
494
+ s->mii_st |= MII_REG_ST_LINK_UP;
495
+ } else {
496
+ s->mii_st &= ~MII_REG_ST_LINK_UP;
497
+ }
498
+}
499
+
500
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
501
+ bool link_active)
502
+{
503
+ s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
504
+ MII_REG_CR_FULLDUPLEX;
505
+ s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
506
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
507
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
508
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
509
+ s->mii_adv = 0;
510
+
511
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
512
+}
513
+
514
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
515
+{
516
+ uint8_t addr, reg;
517
+
518
+ addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
519
+ reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
520
+
521
+ if (addr != s->mii_phy_addr) {
522
+ return;
523
+ }
524
+
525
+ /* Read or write a PHY register? */
526
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
527
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
528
+
529
+ switch (reg) {
530
+ case MII_REG_CR:
531
+ if (s->mii_data & MII_REG_CR_RESET) {
532
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
533
+ MII_REG_ST_LINK_UP);
534
+ } else {
535
+ s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
536
+ MII_REG_CR_AUTO_NEG_RESTART);
537
+ }
538
+ break;
539
+ case MII_REG_ADV:
540
+ s->mii_adv = s->mii_data;
541
+ break;
542
+ case MII_REG_ID_HIGH:
543
+ case MII_REG_ID_LOW:
544
+ case MII_REG_LPA:
545
+ break;
546
+ default:
547
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
548
+ "unknown MII register 0x%x\n", reg);
549
+ break;
550
+ }
551
+ } else {
552
+ switch (reg) {
553
+ case MII_REG_CR:
554
+ s->mii_data = s->mii_cr;
555
+ break;
556
+ case MII_REG_ST:
557
+ s->mii_data = s->mii_st;
558
+ break;
559
+ case MII_REG_ID_HIGH:
560
+ s->mii_data = MII_PHY_ID_HIGH;
561
+ break;
562
+ case MII_REG_ID_LOW:
563
+ s->mii_data = MII_PHY_ID_LOW;
564
+ break;
565
+ case MII_REG_ADV:
566
+ s->mii_data = s->mii_adv;
567
+ break;
568
+ case MII_REG_LPA:
569
+ s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
570
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
571
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
572
+ break;
573
+ default:
574
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
575
+ "unknown MII register 0x%x\n", reg);
576
+ s->mii_data = 0;
577
+ break;
578
+ }
579
+
580
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
581
+ }
582
+}
583
+
584
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
585
+{
586
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
587
+}
588
+
589
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
590
+ size_t min_size)
591
+{
592
+ uint32_t paddr = desc->next;
593
+
594
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
595
+
596
+ if ((desc->status & DESC_STATUS_CTL) &&
597
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
598
+ return paddr;
599
+ } else {
600
+ return 0;
601
+ }
602
+}
603
+
604
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
605
+ uint32_t start_addr,
606
+ size_t min_size)
607
+{
608
+ uint32_t desc_addr = start_addr;
609
+
610
+ /* Note that the list is a cycle. Last entry points back to the head. */
611
+ while (desc_addr != 0) {
612
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
613
+
614
+ if ((desc->status & DESC_STATUS_CTL) &&
615
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
616
+ return desc_addr;
617
+ } else if (desc->next == start_addr) {
618
+ break;
619
+ } else {
620
+ desc_addr = desc->next;
621
+ }
622
+ }
623
+
624
+ return 0;
625
+}
626
+
627
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
628
+ FrameDescriptor *desc,
629
+ size_t min_size)
630
+{
631
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
632
+}
633
+
634
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
635
+ FrameDescriptor *desc,
636
+ size_t min_size)
637
+{
638
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
639
+}
640
+
641
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
642
+ uint32_t phys_addr)
643
+{
644
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
645
+}
646
+
647
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
648
+{
649
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
650
+ FrameDescriptor desc;
651
+
652
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
653
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
654
+}
655
+
656
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
657
+ const uint8_t *buf,
658
+ size_t size)
659
+{
660
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
661
+ FrameDescriptor desc;
662
+ size_t bytes_left = size;
663
+ size_t desc_bytes = 0;
664
+ size_t pad_fcs_size = 4;
665
+ size_t padding = 0;
666
+
667
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
668
+ return -1;
669
+ }
670
+
671
+ s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
672
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
673
+ if (!s->rx_desc_curr) {
674
+ s->int_sta |= INT_STA_RX_BUF_UA;
675
+ }
676
+
677
+ /* Keep filling RX descriptors until the whole frame is written */
678
+ while (s->rx_desc_curr && bytes_left > 0) {
679
+ desc.status &= ~DESC_STATUS_CTL;
680
+ desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
681
+
682
+ if (bytes_left == size) {
683
+ desc.status |= RX_DESC_STATUS_FIRST_DESC;
684
+ }
685
+
686
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
687
+ (bytes_left + pad_fcs_size)) {
688
+ desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
689
+ desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
690
+ } else {
691
+ padding = pad_fcs_size;
692
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
693
+ padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
694
+ }
695
+
696
+ desc_bytes = (bytes_left);
697
+ desc.status |= RX_DESC_STATUS_LAST_DESC;
698
+ desc.status |= (bytes_left + padding)
699
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
700
+ }
701
+
702
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
703
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
704
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
705
+ desc_bytes);
706
+
707
+ /* Check if frame needs to raise the receive interrupt */
708
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
709
+ s->int_sta |= INT_STA_RX;
710
+ }
711
+
712
+ /* Increment variables */
713
+ buf += desc_bytes;
714
+ bytes_left -= desc_bytes;
715
+
716
+ /* Move to the next descriptor */
717
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
718
+ if (!s->rx_desc_curr) {
719
+ /* Not enough buffer space available */
720
+ s->int_sta |= INT_STA_RX_BUF_UA;
721
+ s->rx_desc_curr = s->rx_desc_head;
722
+ break;
723
+ }
724
+ }
725
+
726
+ /* Report receive DMA is finished */
727
+ s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
728
+ allwinner_sun8i_emac_update_irq(s);
729
+
730
+ return size;
731
+}
732
+
733
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
734
+{
735
+ NetClientState *nc = qemu_get_queue(s->nic);
736
+ FrameDescriptor desc;
737
+ size_t bytes = 0;
738
+ size_t packet_bytes = 0;
739
+ size_t transmitted = 0;
740
+ static uint8_t packet_buf[2048];
741
+
742
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
743
+
744
+ /* Read all transmit descriptors */
745
+ while (s->tx_desc_curr != 0) {
746
+
747
+ /* Read from physical memory into packet buffer */
748
+ bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
749
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
750
+ desc.status |= TX_DESC_STATUS_LENGTH_ERR;
751
+ break;
752
+ }
753
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
754
+ packet_bytes += bytes;
755
+ desc.status &= ~DESC_STATUS_CTL;
756
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
757
+
758
+ /* After the last descriptor, send the packet */
759
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
760
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
761
+ net_checksum_calculate(packet_buf, packet_bytes);
762
+ }
763
+
764
+ qemu_send_packet(nc, packet_buf, packet_bytes);
765
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
766
+ bytes);
767
+
768
+ packet_bytes = 0;
769
+ transmitted++;
770
+ }
771
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
772
+ }
773
+
774
+ /* Raise transmit completed interrupt */
775
+ if (transmitted > 0) {
776
+ s->int_sta |= INT_STA_TX;
777
+ s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
778
+ allwinner_sun8i_emac_update_irq(s);
779
+ }
780
+}
781
+
782
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
783
+{
784
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
785
+ NetClientState *nc = qemu_get_queue(s->nic);
786
+
787
+ trace_allwinner_sun8i_emac_reset();
788
+
789
+ s->mii_cmd = 0;
790
+ s->mii_data = 0;
791
+ s->basic_ctl0 = 0;
792
+ s->basic_ctl1 = REG_BASIC_CTL_1_RST;
793
+ s->int_en = 0;
794
+ s->int_sta = 0;
795
+ s->frm_flt = 0;
796
+ s->rx_ctl0 = 0;
797
+ s->rx_ctl1 = RX_CTL1_RX_MD;
798
+ s->rx_desc_head = 0;
799
+ s->rx_desc_curr = 0;
800
+ s->tx_ctl0 = 0;
801
+ s->tx_ctl1 = 0;
802
+ s->tx_desc_head = 0;
803
+ s->tx_desc_curr = 0;
804
+ s->tx_flowctl = 0;
805
+
806
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
807
+}
808
+
809
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
810
+ unsigned size)
811
+{
812
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
813
+ uint64_t value = 0;
814
+ FrameDescriptor desc;
815
+
816
+ switch (offset) {
817
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
818
+ value = s->basic_ctl0;
819
+ break;
820
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
821
+ value = s->basic_ctl1;
822
+ break;
823
+ case REG_INT_STA: /* Interrupt Status */
824
+ value = s->int_sta;
825
+ break;
826
+ case REG_INT_EN: /* Interupt Enable */
827
+ value = s->int_en;
828
+ break;
829
+ case REG_TX_CTL_0: /* Transmit Control 0 */
830
+ value = s->tx_ctl0;
831
+ break;
832
+ case REG_TX_CTL_1: /* Transmit Control 1 */
833
+ value = s->tx_ctl1;
834
+ break;
835
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
836
+ value = s->tx_flowctl;
837
+ break;
838
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
839
+ value = s->tx_desc_head;
840
+ break;
841
+ case REG_RX_CTL_0: /* Receive Control 0 */
842
+ value = s->rx_ctl0;
843
+ break;
844
+ case REG_RX_CTL_1: /* Receive Control 1 */
845
+ value = s->rx_ctl1;
846
+ break;
847
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
848
+ value = s->rx_desc_head;
849
+ break;
850
+ case REG_FRM_FLT: /* Receive Frame Filter */
851
+ value = s->frm_flt;
852
+ break;
853
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
854
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
855
+ break;
856
+ case REG_MII_CMD: /* Management Interface Command */
857
+ value = s->mii_cmd;
858
+ break;
859
+ case REG_MII_DATA: /* Management Interface Data */
860
+ value = s->mii_data;
861
+ break;
862
+ case REG_ADDR_HIGH: /* MAC Address High */
863
+ value = *(((uint32_t *) (s->conf.macaddr.a)) + 1);
864
+ break;
865
+ case REG_ADDR_LOW: /* MAC Address Low */
866
+ value = *(uint32_t *) (s->conf.macaddr.a);
867
+ break;
868
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
869
+ break;
870
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
871
+ value = s->tx_desc_curr;
872
+ break;
873
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
874
+ if (s->tx_desc_curr != 0) {
875
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
876
+ value = desc.addr;
877
+ } else {
878
+ value = 0;
879
+ }
880
+ break;
881
+ case REG_RX_DMA_STA: /* Receive DMA Status */
882
+ break;
883
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
884
+ value = s->rx_desc_curr;
885
+ break;
886
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
887
+ if (s->rx_desc_curr != 0) {
888
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
889
+ value = desc.addr;
890
+ } else {
891
+ value = 0;
892
+ }
893
+ break;
894
+ case REG_RGMII_STA: /* RGMII Status */
895
+ break;
896
+ default:
897
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
898
+ "EMAC register 0x" TARGET_FMT_plx "\n",
899
+ offset);
900
+ }
901
+
902
+ trace_allwinner_sun8i_emac_read(offset, value);
903
+ return value;
904
+}
905
+
906
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
907
+ uint64_t value, unsigned size)
908
+{
909
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
910
+ NetClientState *nc = qemu_get_queue(s->nic);
911
+
912
+ trace_allwinner_sun8i_emac_write(offset, value);
913
+
914
+ switch (offset) {
915
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
916
+ s->basic_ctl0 = value;
917
+ break;
918
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
919
+ if (value & BASIC_CTL1_SOFTRST) {
920
+ allwinner_sun8i_emac_reset(DEVICE(s));
921
+ value &= ~BASIC_CTL1_SOFTRST;
922
+ }
923
+ s->basic_ctl1 = value;
924
+ if (allwinner_sun8i_emac_can_receive(nc)) {
925
+ qemu_flush_queued_packets(nc);
926
+ }
927
+ break;
928
+ case REG_INT_STA: /* Interrupt Status */
929
+ s->int_sta &= ~value;
930
+ allwinner_sun8i_emac_update_irq(s);
931
+ break;
932
+ case REG_INT_EN: /* Interrupt Enable */
933
+ s->int_en = value;
934
+ allwinner_sun8i_emac_update_irq(s);
935
+ break;
936
+ case REG_TX_CTL_0: /* Transmit Control 0 */
937
+ s->tx_ctl0 = value;
938
+ break;
939
+ case REG_TX_CTL_1: /* Transmit Control 1 */
940
+ s->tx_ctl1 = value;
941
+ if (value & TX_CTL1_TX_DMA_EN) {
942
+ allwinner_sun8i_emac_transmit(s);
943
+ }
944
+ break;
945
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
946
+ s->tx_flowctl = value;
947
+ break;
948
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
949
+ s->tx_desc_head = value;
950
+ s->tx_desc_curr = value;
951
+ break;
952
+ case REG_RX_CTL_0: /* Receive Control 0 */
953
+ s->rx_ctl0 = value;
954
+ break;
955
+ case REG_RX_CTL_1: /* Receive Control 1 */
956
+ s->rx_ctl1 = value | RX_CTL1_RX_MD;
957
+ if ((value & RX_CTL1_RX_DMA_EN) &&
958
+ allwinner_sun8i_emac_can_receive(nc)) {
959
+ qemu_flush_queued_packets(nc);
960
+ }
961
+ break;
962
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
963
+ s->rx_desc_head = value;
964
+ s->rx_desc_curr = value;
965
+ break;
966
+ case REG_FRM_FLT: /* Receive Frame Filter */
967
+ s->frm_flt = value;
968
+ break;
969
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
970
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
971
+ break;
972
+ case REG_MII_CMD: /* Management Interface Command */
973
+ s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
974
+ allwinner_sun8i_emac_mii_cmd(s);
975
+ break;
976
+ case REG_MII_DATA: /* Management Interface Data */
977
+ s->mii_data = value;
978
+ break;
979
+ case REG_ADDR_HIGH: /* MAC Address High */
980
+ s->conf.macaddr.a[4] = (value & 0xff);
981
+ s->conf.macaddr.a[5] = (value & 0xff00) >> 8;
982
+ break;
983
+ case REG_ADDR_LOW: /* MAC Address Low */
984
+ s->conf.macaddr.a[0] = (value & 0xff);
985
+ s->conf.macaddr.a[1] = (value & 0xff00) >> 8;
986
+ s->conf.macaddr.a[2] = (value & 0xff0000) >> 16;
987
+ s->conf.macaddr.a[3] = (value & 0xff000000) >> 24;
988
+ break;
989
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
990
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
991
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
992
+ case REG_RX_DMA_STA: /* Receive DMA Status */
993
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
994
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
995
+ case REG_RGMII_STA: /* RGMII Status */
996
+ break;
997
+ default:
998
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
999
+ "EMAC register 0x" TARGET_FMT_plx "\n",
1000
+ offset);
1001
+ }
1002
+}
1003
+
1004
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
1005
+{
1006
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
1007
+
1008
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
1009
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
1010
+}
1011
+
1012
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
1013
+ .read = allwinner_sun8i_emac_read,
1014
+ .write = allwinner_sun8i_emac_write,
1015
+ .endianness = DEVICE_NATIVE_ENDIAN,
1016
+ .valid = {
1017
+ .min_access_size = 4,
1018
+ .max_access_size = 4,
1019
+ },
1020
+ .impl.min_access_size = 4,
1021
+};
1022
+
1023
+static NetClientInfo net_allwinner_sun8i_emac_info = {
1024
+ .type = NET_CLIENT_DRIVER_NIC,
1025
+ .size = sizeof(NICState),
1026
+ .can_receive = allwinner_sun8i_emac_can_receive,
1027
+ .receive = allwinner_sun8i_emac_receive,
1028
+ .link_status_changed = allwinner_sun8i_emac_set_link,
1029
+};
1030
+
1031
+static void allwinner_sun8i_emac_init(Object *obj)
1032
+{
1033
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1034
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
1035
+
1036
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
1037
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
1038
+ sysbus_init_mmio(sbd, &s->iomem);
1039
+ sysbus_init_irq(sbd, &s->irq);
1040
+}
1041
+
1042
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
1043
+{
1044
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
1045
+
1046
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
1047
+ s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
1048
+ object_get_typename(OBJECT(dev)), dev->id, s);
1049
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1050
+}
1051
+
1052
+static Property allwinner_sun8i_emac_properties[] = {
1053
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
1054
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
1055
+ DEFINE_PROP_END_OF_LIST(),
1056
+};
1057
+
1058
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
1059
+{
1060
+ AwSun8iEmacState *s = opaque;
1061
+
1062
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
1063
+
1064
+ return 0;
1065
+}
1066
+
1067
+static const VMStateDescription vmstate_aw_emac = {
1068
+ .name = "allwinner-sun8i-emac",
1069
+ .version_id = 1,
1070
+ .minimum_version_id = 1,
1071
+ .post_load = allwinner_sun8i_emac_post_load,
1072
+ .fields = (VMStateField[]) {
1073
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
1074
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
1075
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
1076
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
1077
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
1078
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
1079
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
1080
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
1081
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
1082
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
1083
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
1084
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
1085
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
1086
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
1087
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
1088
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
1089
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
1090
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
1091
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
1092
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
1093
+ VMSTATE_END_OF_LIST()
1094
+ }
1095
+};
1096
+
1097
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
1098
+{
1099
+ DeviceClass *dc = DEVICE_CLASS(klass);
1100
+
1101
+ dc->realize = allwinner_sun8i_emac_realize;
1102
+ dc->reset = allwinner_sun8i_emac_reset;
1103
+ dc->vmsd = &vmstate_aw_emac;
1104
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
1105
+}
1106
+
1107
+static const TypeInfo allwinner_sun8i_emac_info = {
1108
+ .name = TYPE_AW_SUN8I_EMAC,
1109
+ .parent = TYPE_SYS_BUS_DEVICE,
1110
+ .instance_size = sizeof(AwSun8iEmacState),
1111
+ .instance_init = allwinner_sun8i_emac_init,
1112
+ .class_init = allwinner_sun8i_emac_class_init,
1113
+};
1114
+
1115
+static void allwinner_sun8i_emac_register_types(void)
1116
+{
1117
+ type_register_static(&allwinner_sun8i_emac_info);
1118
+}
1119
+
1120
+type_init(allwinner_sun8i_emac_register_types)
1121
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1122
index XXXXXXX..XXXXXXX 100644
212
index XXXXXXX..XXXXXXX 100644
1123
--- a/hw/arm/Kconfig
213
--- a/hw/arm/Kconfig
1124
+++ b/hw/arm/Kconfig
214
+++ b/hw/arm/Kconfig
1125
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
215
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
1126
config ALLWINNER_H3
216
select XLNX_ZYNQMP
217
select OR_IRQ
218
select XLNX_BBRAM
219
+ select XLNX_EFUSE_VERSAL
220
221
config NPCM7XX
1127
bool
222
bool
1128
select ALLWINNER_A10_PIT
1129
+ select ALLWINNER_SUN8I_EMAC
1130
select SERIAL
1131
select ARM_TIMER
1132
select ARM_GIC
1133
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/hw/net/Kconfig
1136
+++ b/hw/net/Kconfig
1137
@@ -XXX,XX +XXX,XX @@ config MIPSNET
1138
config ALLWINNER_EMAC
1139
bool
1140
1141
+config ALLWINNER_SUN8I_EMAC
1142
+ bool
1143
+
1144
config IMX_FEC
1145
bool
1146
1147
diff --git a/hw/net/trace-events b/hw/net/trace-events
1148
index XXXXXXX..XXXXXXX 100644
1149
--- a/hw/net/trace-events
1150
+++ b/hw/net/trace-events
1151
@@ -XXX,XX +XXX,XX @@
1152
# See docs/devel/tracing.txt for syntax documentation.
1153
1154
+# allwinner-sun8i-emac.c
1155
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
1156
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
1157
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1158
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1159
+allwinner_sun8i_emac_reset(void) "HW reset"
1160
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
1161
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
1162
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
1163
+
1164
# etraxfs_eth.c
1165
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
1166
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
1167
--
223
--
1168
2.20.1
224
2.20.1
1169
225
1170
226
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
The Security Identifier device found in various Allwinner System on Chip
3
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
4
designs gives applications a per-board unique identifier. This commit
5
adds support for the Allwinner Security Identifier using a 128-bit
6
UUID value as input.
7
4
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
5
The command argument:
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
-drive if=pflash,index=2,...
10
Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com
7
Can be used to optionally connect the bbram to a backend
8
storage, such that field-programmed values in one
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
19
---
13
hw/misc/Makefile.objs | 1 +
20
include/hw/arm/xlnx-zynqmp.h | 2 ++
14
include/hw/arm/allwinner-h3.h | 3 +
21
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
15
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
22
hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
16
hw/arm/allwinner-h3.c | 11 ++-
23
hw/Kconfig | 1 +
17
hw/arm/orangepi.c | 8 ++
24
4 files changed, 38 insertions(+)
18
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
19
hw/misc/trace-events | 4 +
20
7 files changed, 254 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-sid.h
22
create mode 100644 hw/misc/allwinner-sid.c
23
25
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
26
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
25
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
28
--- a/include/hw/arm/xlnx-zynqmp.h
27
+++ b/hw/misc/Makefile.objs
29
+++ b/include/hw/arm/xlnx-zynqmp.h
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
30
@@ -XXX,XX +XXX,XX @@
29
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
31
#include "qom/object.h"
30
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
32
#include "net/can_emu.h"
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
33
#include "hw/dma/xlnx_csu_dma.h"
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
34
+#include "hw/nvram/xlnx-bbram.h"
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
35
34
common-obj-$(CONFIG_NSERIES) += cbus.o
36
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
37
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
38
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
39
40
MemoryRegion *ddr_ram;
41
MemoryRegion ddr_ram_low, ddr_ram_high;
42
+ XlnxBBRam bbram;
43
44
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
45
46
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
37
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
48
--- a/hw/arm/xlnx-zcu102.c
39
+++ b/include/hw/arm/allwinner-h3.h
49
+++ b/hw/arm/xlnx-zcu102.c
40
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
41
#include "hw/misc/allwinner-h3-ccu.h"
51
}
42
#include "hw/misc/allwinner-cpucfg.h"
52
}
43
#include "hw/misc/allwinner-h3-sysctrl.h"
53
44
+#include "hw/misc/allwinner-sid.h"
54
+static void bbram_attach_drive(XlnxBBRam *dev)
45
#include "target/arm/cpu.h"
55
+{
46
56
+ DriveInfo *dinfo;
47
/**
57
+ BlockBackend *blk;
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A2,
50
AW_H3_SRAM_C,
51
AW_H3_SYSCTRL,
52
+ AW_H3_SID,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
AwH3ClockCtlState ccu;
58
AwCpuCfgState cpucfg;
59
AwH3SysCtrlState sysctrl;
60
+ AwSidState sid;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-sid.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner Security ID emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
58
+
89
+#ifndef HW_MISC_ALLWINNER_SID_H
59
+ dinfo = drive_get_by_index(IF_PFLASH, 2);
90
+#define HW_MISC_ALLWINNER_SID_H
60
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
91
+
61
+ if (blk) {
92
+#include "qom/object.h"
62
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
93
+#include "hw/sysbus.h"
94
+#include "qemu/uuid.h"
95
+
96
+/**
97
+ * Object model
98
+ * @{
99
+ */
100
+
101
+#define TYPE_AW_SID "allwinner-sid"
102
+#define AW_SID(obj) \
103
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
104
+
105
+/** @} */
106
+
107
+/**
108
+ * Allwinner Security ID object instance state
109
+ */
110
+typedef struct AwSidState {
111
+ /*< private >*/
112
+ SysBusDevice parent_obj;
113
+ /*< public >*/
114
+
115
+ /** Maps I/O registers in physical memory */
116
+ MemoryRegion iomem;
117
+
118
+ /** Control register defines how and what to read */
119
+ uint32_t control;
120
+
121
+ /** RdKey register contains the data retrieved by the device */
122
+ uint32_t rdkey;
123
+
124
+ /** Stores the emulated device identifier */
125
+ QemuUUID identifier;
126
+
127
+} AwSidState;
128
+
129
+#endif /* HW_MISC_ALLWINNER_SID_H */
130
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/arm/allwinner-h3.c
133
+++ b/hw/arm/allwinner-h3.c
134
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
135
[AW_H3_SRAM_A2] = 0x00044000,
136
[AW_H3_SRAM_C] = 0x00010000,
137
[AW_H3_SYSCTRL] = 0x01c00000,
138
+ [AW_H3_SID] = 0x01c14000,
139
[AW_H3_EHCI0] = 0x01c1a000,
140
[AW_H3_OHCI0] = 0x01c1a400,
141
[AW_H3_EHCI1] = 0x01c1b000,
142
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
143
{ "mmc0", 0x01c0f000, 4 * KiB },
144
{ "mmc1", 0x01c10000, 4 * KiB },
145
{ "mmc2", 0x01c11000, 4 * KiB },
146
- { "sid", 0x01c14000, 1 * KiB },
147
{ "crypto", 0x01c15000, 4 * KiB },
148
{ "msgbox", 0x01c17000, 4 * KiB },
149
{ "spinlock", 0x01c18000, 4 * KiB },
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
151
152
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
153
TYPE_AW_CPUCFG);
154
+
155
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
156
+ TYPE_AW_SID);
157
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
158
+ "identifier", &error_abort);
159
}
160
161
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
162
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
163
qdev_init_nofail(DEVICE(&s->cpucfg));
164
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
165
166
+ /* Security Identifier */
167
+ qdev_init_nofail(DEVICE(&s->sid));
168
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
169
+
170
/* Universal Serial Bus */
171
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
172
qdev_get_gpio_in(DEVICE(&s->gic),
173
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/orangepi.c
176
+++ b/hw/arm/orangepi.c
177
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
178
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
179
&error_abort);
180
181
+ /* Setup SID properties. Currently using a default fixed SID identifier. */
182
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
183
+ qdev_prop_set_string(DEVICE(h3), "identifier",
184
+ "02c00081-1111-2222-3333-000044556677");
185
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) {
186
+ warn_report("Security Identifier value does not include H3 prefix");
187
+ }
188
+
189
/* Mark H3 object realized */
190
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
191
192
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
193
new file mode 100644
194
index XXXXXXX..XXXXXXX
195
--- /dev/null
196
+++ b/hw/misc/allwinner-sid.c
197
@@ -XXX,XX +XXX,XX @@
198
+/*
199
+ * Allwinner Security ID emulation
200
+ *
201
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
202
+ *
203
+ * This program is free software: you can redistribute it and/or modify
204
+ * it under the terms of the GNU General Public License as published by
205
+ * the Free Software Foundation, either version 2 of the License, or
206
+ * (at your option) any later version.
207
+ *
208
+ * This program is distributed in the hope that it will be useful,
209
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
210
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
211
+ * GNU General Public License for more details.
212
+ *
213
+ * You should have received a copy of the GNU General Public License
214
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
215
+ */
216
+
217
+#include "qemu/osdep.h"
218
+#include "qemu/units.h"
219
+#include "hw/sysbus.h"
220
+#include "migration/vmstate.h"
221
+#include "qemu/log.h"
222
+#include "qemu/module.h"
223
+#include "qemu/guest-random.h"
224
+#include "qapi/error.h"
225
+#include "hw/qdev-properties.h"
226
+#include "hw/misc/allwinner-sid.h"
227
+#include "trace.h"
228
+
229
+/* SID register offsets */
230
+enum {
231
+ REG_PRCTL = 0x40, /* Control */
232
+ REG_RDKEY = 0x60, /* Read Key */
233
+};
234
+
235
+/* SID register flags */
236
+enum {
237
+ REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */
238
+ REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */
239
+};
240
+
241
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
242
+ unsigned size)
243
+{
244
+ const AwSidState *s = AW_SID(opaque);
245
+ uint64_t val = 0;
246
+
247
+ switch (offset) {
248
+ case REG_PRCTL: /* Control */
249
+ val = s->control;
250
+ break;
251
+ case REG_RDKEY: /* Read Key */
252
+ val = s->rdkey;
253
+ break;
254
+ default:
255
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
256
+ __func__, (uint32_t)offset);
257
+ return 0;
258
+ }
259
+
260
+ trace_allwinner_sid_read(offset, val, size);
261
+
262
+ return val;
263
+}
264
+
265
+static void allwinner_sid_write(void *opaque, hwaddr offset,
266
+ uint64_t val, unsigned size)
267
+{
268
+ AwSidState *s = AW_SID(opaque);
269
+
270
+ trace_allwinner_sid_write(offset, val, size);
271
+
272
+ switch (offset) {
273
+ case REG_PRCTL: /* Control */
274
+ s->control = val;
275
+
276
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
277
+ (s->control & REG_PRCTL_WRITE)) {
278
+ uint32_t id = s->control >> 16;
279
+
280
+ if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) {
281
+ s->rdkey = ldl_be_p(&s->identifier.data[id]);
282
+ }
283
+ }
284
+ s->control &= ~REG_PRCTL_WRITE;
285
+ break;
286
+ case REG_RDKEY: /* Read Key */
287
+ break;
288
+ default:
289
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
290
+ __func__, (uint32_t)offset);
291
+ break;
292
+ }
63
+ }
293
+}
64
+}
294
+
65
+
295
+static const MemoryRegionOps allwinner_sid_ops = {
66
static void xlnx_zcu102_init(MachineState *machine)
296
+ .read = allwinner_sid_read,
67
{
297
+ .write = allwinner_sid_write,
68
XlnxZCU102 *s = ZCU102_MACHINE(machine);
298
+ .endianness = DEVICE_NATIVE_ENDIAN,
69
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
299
+ .valid = {
70
300
+ .min_access_size = 4,
71
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
301
+ .max_access_size = 4,
72
302
+ },
73
+ /* Attach bbram backend, if given */
303
+ .impl.min_access_size = 4,
74
+ bbram_attach_drive(&s->soc.bbram);
304
+};
305
+
75
+
306
+static void allwinner_sid_reset(DeviceState *dev)
76
/* Create and plug in the SD cards */
77
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
78
BusState *bus;
79
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/xlnx-zynqmp.c
82
+++ b/hw/arm/xlnx-zynqmp.c
83
@@ -XXX,XX +XXX,XX @@
84
#define RTC_ADDR 0xffa60000
85
#define RTC_IRQ 26
86
87
+#define BBRAM_ADDR 0xffcd0000
88
+#define BBRAM_IRQ 11
89
+
90
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
91
92
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
93
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
94
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
95
}
96
97
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
307
+{
98
+{
308
+ AwSidState *s = AW_SID(dev);
99
+ SysBusDevice *sbd;
309
+
100
+
310
+ /* Set default values for registers */
101
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
311
+ s->control = 0;
102
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
312
+ s->rdkey = 0;
103
+ &error_fatal,
104
+ "crc-zpads", "1",
105
+ NULL);
106
+ sbd = SYS_BUS_DEVICE(&s->bbram);
107
+
108
+ sysbus_realize(sbd, &error_fatal);
109
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
110
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
313
+}
111
+}
314
+
112
+
315
+static void allwinner_sid_init(Object *obj)
113
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
316
+{
114
{
317
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
115
static const struct UnimpInfo {
318
+ AwSidState *s = AW_SID(obj);
116
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
319
+
117
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
320
+ /* Memory mapping */
118
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
321
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
119
322
+ TYPE_AW_SID, 1 * KiB);
120
+ xlnx_zynqmp_create_bbram(s, gic_spi);
323
+ sysbus_init_mmio(sbd, &s->iomem);
121
xlnx_zynqmp_create_unimp_mmio(s);
324
+}
122
325
+
123
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
326
+static Property allwinner_sid_properties[] = {
124
diff --git a/hw/Kconfig b/hw/Kconfig
327
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
328
+ DEFINE_PROP_END_OF_LIST()
329
+};
330
+
331
+static const VMStateDescription allwinner_sid_vmstate = {
332
+ .name = "allwinner-sid",
333
+ .version_id = 1,
334
+ .minimum_version_id = 1,
335
+ .fields = (VMStateField[]) {
336
+ VMSTATE_UINT32(control, AwSidState),
337
+ VMSTATE_UINT32(rdkey, AwSidState),
338
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1),
339
+ VMSTATE_END_OF_LIST()
340
+ }
341
+};
342
+
343
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
344
+{
345
+ DeviceClass *dc = DEVICE_CLASS(klass);
346
+
347
+ dc->reset = allwinner_sid_reset;
348
+ dc->vmsd = &allwinner_sid_vmstate;
349
+ device_class_set_props(dc, allwinner_sid_properties);
350
+}
351
+
352
+static const TypeInfo allwinner_sid_info = {
353
+ .name = TYPE_AW_SID,
354
+ .parent = TYPE_SYS_BUS_DEVICE,
355
+ .instance_init = allwinner_sid_init,
356
+ .instance_size = sizeof(AwSidState),
357
+ .class_init = allwinner_sid_class_init,
358
+};
359
+
360
+static void allwinner_sid_register(void)
361
+{
362
+ type_register_static(&allwinner_sid_info);
363
+}
364
+
365
+type_init(allwinner_sid_register)
366
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
367
index XXXXXXX..XXXXXXX 100644
125
index XXXXXXX..XXXXXXX 100644
368
--- a/hw/misc/trace-events
126
--- a/hw/Kconfig
369
+++ b/hw/misc/trace-events
127
+++ b/hw/Kconfig
370
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
128
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
371
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
129
select REGISTER
372
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
130
select CAN_BUS
373
131
select PTIMER
374
+# allwinner-sid.c
132
+ select XLNX_BBRAM
375
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
376
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
377
+
378
# eccmemctl.c
379
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
380
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
381
--
133
--
382
2.20.1
134
2.20.1
383
135
384
136
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
Let's move the code which freezes which gic-version to
3
Connect the support for ZynqMP eFUSE one-time field-programmable
4
be applied in a dedicated function. We also now set by
4
bit array.
5
default the VIRT_GIC_VERSION_NO_SET. This eventually
6
turns into the legacy v2 choice in the finalize() function.
7
5
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
The command argument:
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
-drive if=pflash,index=3,...
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Can be used to optionally connect the bit array to a
11
Message-id: 20200311131618.7187-4-eric.auger@redhat.com
9
backend storage, such that field-programmed values
10
in one invocation can be made available to next
11
invocation.
12
13
The backend storage must be a seekable binary file, and
14
its size must be 768 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
21
---
14
include/hw/arm/virt.h | 1 +
22
include/hw/arm/xlnx-zynqmp.h | 3 +++
15
hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------
23
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
16
2 files changed, 34 insertions(+), 21 deletions(-)
24
hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++
25
hw/Kconfig | 1 +
26
4 files changed, 48 insertions(+)
17
27
18
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
28
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
19
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/virt.h
30
--- a/include/hw/arm/xlnx-zynqmp.h
21
+++ b/include/hw/arm/virt.h
31
+++ b/include/hw/arm/xlnx-zynqmp.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType {
32
@@ -XXX,XX +XXX,XX @@
23
VIRT_GIC_VERSION_HOST,
33
#include "net/can_emu.h"
24
VIRT_GIC_VERSION_2,
34
#include "hw/dma/xlnx_csu_dma.h"
25
VIRT_GIC_VERSION_3,
35
#include "hw/nvram/xlnx-bbram.h"
26
+ VIRT_GIC_VERSION_NOSEL,
36
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
27
} VirtGICType;
37
28
38
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
29
typedef struct MemMapEntry {
39
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
30
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
40
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
41
MemoryRegion *ddr_ram;
42
MemoryRegion ddr_ram_low, ddr_ram_high;
43
XlnxBBRam bbram;
44
+ XlnxEFuse efuse;
45
+ XlnxZynqMPEFuse efuse_ctrl;
46
47
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
48
49
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
31
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/virt.c
51
--- a/hw/arm/xlnx-zcu102.c
33
+++ b/hw/arm/virt.c
52
+++ b/hw/arm/xlnx-zcu102.c
34
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
53
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
35
}
54
}
36
}
55
}
37
56
38
+/*
57
+static void efuse_attach_drive(XlnxEFuse *dev)
39
+ * finalize_gic_version - Determines the final gic_version
40
+ * according to the gic-version property
41
+ *
42
+ * Default GIC type is v2
43
+ */
44
+static void finalize_gic_version(VirtMachineState *vms)
45
+{
58
+{
46
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
59
+ DriveInfo *dinfo;
47
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
60
+ BlockBackend *blk;
48
+ if (!kvm_enabled()) {
61
+
49
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
62
+ dinfo = drive_get_by_index(IF_PFLASH, 3);
50
+ error_report("gic-version=host requires KVM");
63
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
51
+ exit(1);
64
+ if (blk) {
52
+ } else {
65
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
53
+ /* "max": currently means 3 for TCG */
54
+ vms->gic_version = VIRT_GIC_VERSION_3;
55
+ }
56
+ } else {
57
+ vms->gic_version = kvm_arm_vgic_probe();
58
+ if (!vms->gic_version) {
59
+ error_report(
60
+ "Unable to determine GIC version supported by host");
61
+ exit(1);
62
+ }
63
+ }
64
+ } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
65
+ vms->gic_version = VIRT_GIC_VERSION_2;
66
+ }
66
+ }
67
+}
67
+}
68
+
68
+
69
static void machvirt_init(MachineState *machine)
69
static void xlnx_zcu102_init(MachineState *machine)
70
{
70
{
71
VirtMachineState *vms = VIRT_MACHINE(machine);
71
XlnxZCU102 *s = ZCU102_MACHINE(machine);
72
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
72
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
73
/* We can probe only here because during property set
73
/* Attach bbram backend, if given */
74
* KVM is not available yet
74
bbram_attach_drive(&s->soc.bbram);
75
*/
75
76
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
76
+ /* Attach efuse backend, if given */
77
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
77
+ efuse_attach_drive(&s->soc.efuse);
78
- if (!kvm_enabled()) {
78
+
79
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
79
/* Create and plug in the SD cards */
80
- error_report("gic-version=host requires KVM");
80
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
81
- exit(1);
81
BusState *bus;
82
- } else {
82
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
83
- /* "max": currently means 3 for TCG */
83
index XXXXXXX..XXXXXXX 100644
84
- vms->gic_version = VIRT_GIC_VERSION_3;
84
--- a/hw/arm/xlnx-zynqmp.c
85
- }
85
+++ b/hw/arm/xlnx-zynqmp.c
86
- } else {
86
@@ -XXX,XX +XXX,XX @@
87
- vms->gic_version = kvm_arm_vgic_probe();
87
#define BBRAM_ADDR 0xffcd0000
88
- if (!vms->gic_version) {
88
#define BBRAM_IRQ 11
89
- error_report(
89
90
- "Unable to determine GIC version supported by host");
90
+#define EFUSE_ADDR 0xffcc0000
91
- exit(1);
91
+#define EFUSE_IRQ 87
92
- }
92
+
93
- }
93
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
94
- }
94
95
+ finalize_gic_version(vms);
95
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
96
96
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
97
if (!cpu_type_valid(machine->cpu_type)) {
97
sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
98
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
98
}
99
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
99
100
"Set on/off to enable/disable using "
100
+static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
101
"physical address space above 32 bits",
101
+{
102
NULL);
102
+ Object *bits = OBJECT(&s->efuse);
103
- /* Default GIC type is v2 */
103
+ Object *ctrl = OBJECT(&s->efuse_ctrl);
104
- vms->gic_version = VIRT_GIC_VERSION_2;
104
+ SysBusDevice *sbd;
105
+ vms->gic_version = VIRT_GIC_VERSION_NOSEL;
105
+
106
object_property_add_str(obj, "gic-version", virt_get_gic_version,
106
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
107
virt_set_gic_version, NULL);
107
+ TYPE_XLNX_ZYNQMP_EFUSE);
108
object_property_set_description(obj, "gic-version",
108
+
109
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
110
+ sizeof(s->efuse),
111
+ TYPE_XLNX_EFUSE, &error_abort,
112
+ "efuse-nr", "3",
113
+ "efuse-size", "2048",
114
+ NULL);
115
+
116
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
117
+ object_property_set_link(ctrl, "efuse", bits, &error_abort);
118
+
119
+ sbd = SYS_BUS_DEVICE(ctrl);
120
+ sysbus_realize(sbd, &error_abort);
121
+ sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
122
+ sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
123
+}
124
+
125
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
126
{
127
static const struct UnimpInfo {
128
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
129
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
130
131
xlnx_zynqmp_create_bbram(s, gic_spi);
132
+ xlnx_zynqmp_create_efuse(s, gic_spi);
133
xlnx_zynqmp_create_unimp_mmio(s);
134
135
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
136
diff --git a/hw/Kconfig b/hw/Kconfig
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/Kconfig
139
+++ b/hw/Kconfig
140
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
141
select CAN_BUS
142
select PTIMER
143
select XLNX_BBRAM
144
+ select XLNX_EFUSE_ZYNQMP
109
--
145
--
110
2.20.1
146
2.20.1
111
147
112
148
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
The Xunlong Orange Pi PC machine is a functional ARM machine
3
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
4
based on the Allwinner H3 System-on-Chip. It supports mainline
4
document.
5
Linux, U-Boot, NetBSD and is covered by acceptance tests.
6
5
7
This commit adds a documentation text file with a description
6
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
8
of the machine and instructions for the user.
7
Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com
9
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com
13
[PMM: moved file into docs/system/arm to match the reorg
14
of the arm target part of the docs; tweaked heading to
15
match other boards]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
10
---
18
MAINTAINERS | 1 +
11
docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++
19
docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++
12
1 file changed, 49 insertions(+)
20
docs/system/target-arm.rst | 2 +
21
3 files changed, 256 insertions(+)
22
create mode 100644 docs/system/arm/orangepi.rst
23
13
24
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
16
--- a/docs/system/arm/xlnx-versal-virt.rst
27
+++ b/MAINTAINERS
17
+++ b/docs/system/arm/xlnx-versal-virt.rst
28
@@ -XXX,XX +XXX,XX @@ S: Maintained
18
@@ -XXX,XX +XXX,XX @@ Implemented devices:
29
F: hw/*/allwinner-h3*
19
- OCM (256KB of On Chip Memory)
30
F: include/hw/*/allwinner-h3*
20
- XRAM (4MB of on chip Accelerator RAM)
31
F: hw/arm/orangepi.c
21
- DDR memory
32
+F: docs/system/orangepi.rst
22
+- BBRAM (36 bytes of Battery-backed RAM)
33
23
+- eFUSE (3072 bytes of one-time field-programmable bit array)
34
ARM PrimeCell and CMSDK devices
24
35
M: Peter Maydell <peter.maydell@linaro.org>
25
QEMU does not yet model any other devices, including the PL and the AI Engine.
36
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
26
37
new file mode 100644
27
@@ -XXX,XX +XXX,XX @@ Run the following at the U-Boot prompt:
38
index XXXXXXX..XXXXXXX
28
fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
39
--- /dev/null
29
booti 30000000 - 20000000
40
+++ b/docs/system/arm/orangepi.rst
30
41
@@ -XXX,XX +XXX,XX @@
31
+BBRAM File Backend
42
+Orange Pi PC (``orangepi-pc``)
32
+""""""""""""""""""
43
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
33
+BBRAM can have an optional file backend, which must be a seekable
34
+binary file with a size of 36 bytes or larger. A file with all
35
+binary 0s is a 'blank'.
44
+
36
+
45
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
37
+To add a file-backend for the BBRAM:
46
+based embedded computer with mainline support in both U-Boot
47
+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
48
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
49
+various other I/O.
50
+
51
+Supported devices
52
+"""""""""""""""""
53
+
54
+The Orange Pi PC machine supports the following devices:
55
+
56
+ * SMP (Quad Core Cortex-A7)
57
+ * Generic Interrupt Controller configuration
58
+ * SRAM mappings
59
+ * SDRAM controller
60
+ * Real Time Clock
61
+ * Timer device (re-used from Allwinner A10)
62
+ * UART
63
+ * SD/MMC storage controller
64
+ * EMAC ethernet
65
+ * USB 2.0 interfaces
66
+ * Clock Control Unit
67
+ * System Control module
68
+ * Security Identifier device
69
+
70
+Limitations
71
+"""""""""""
72
+
73
+Currently, Orange Pi PC does *not* support the following features:
74
+
75
+- Graphical output via HDMI, GPU and/or the Display Engine
76
+- Audio output
77
+- Hardware Watchdog
78
+
79
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
80
+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``
81
+
82
+Boot options
83
+""""""""""""
84
+
85
+The Orange Pi PC machine can start using the standard -kernel functionality
86
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC
87
+machine can also emulate the BootROM which is present on an actual Allwinner H3
88
+based SoC, which loads the bootloader from a SD card, specified via the -sd argument
89
+to qemu-system-arm.
90
+
91
+Machine-specific options
92
+""""""""""""""""""""""""
93
+
94
+The following machine-specific options are supported:
95
+
96
+- allwinner-rtc.base-year=YYYY
97
+
98
+ The Allwinner RTC device is automatically created by the Orange Pi PC machine
99
+ and uses a default base year value which can be overridden using the 'base-year' property.
100
+ The base year is the actual represented year when the RTC year value is zero.
101
+ This option can be used in case the target operating system driver uses a different
102
+ base year value. The minimum value for the base year is 1900.
103
+
104
+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff
105
+
106
+ The Security Identifier value can be read by the guest.
107
+ For example, U-Boot uses it to determine a unique MAC address.
108
+
109
+The above machine-specific options can be specified in qemu-system-arm
110
+via the '-global' argument, for example:
111
+
38
+
112
+.. code-block:: bash
39
+.. code-block:: bash
113
+
40
+
114
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
41
+ -drive if=pflash,index=0,file=versal-bbram.bin,format=raw
115
+ -global allwinner-rtc.base-year=2000
116
+
42
+
117
+Running mainline Linux
43
+To use a different index value, N, from default of 0, add:
118
+""""""""""""""""""""""
119
+
120
+Mainline Linux kernels from 4.19 up to latest master are known to work.
121
+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,
122
+simply configure the kernel using the sunxi_defconfig configuration:
123
+
44
+
124
+.. code-block:: bash
45
+.. code-block:: bash
125
+
46
+
126
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper
47
+ -global xlnx,bbram-ctrl.drive-index=N
127
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig
128
+
48
+
129
+To be able to use USB storage, you need to manually enable the corresponding
49
+eFUSE File Backend
130
+configuration item. Start the kconfig configuration tool:
50
+""""""""""""""""""
51
+eFUSE can have an optional file backend, which must be a seekable
52
+binary file with a size of 3072 bytes or larger. A file with all
53
+binary 0s is a 'blank'.
54
+
55
+To add a file-backend for the eFUSE:
131
+
56
+
132
+.. code-block:: bash
57
+.. code-block:: bash
133
+
58
+
134
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig
59
+ -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
135
+
60
+
136
+Navigate to the following item, enable it and save your configuration:
61
+To use a different index value, N, from default of 1, add:
137
+
138
+ Device Drivers > USB support > USB Mass Storage support
139
+
140
+Build the Linux kernel with:
141
+
62
+
142
+.. code-block:: bash
63
+.. code-block:: bash
143
+
64
+
144
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make
65
+ -global xlnx,efuse.drive-index=N
145
+
66
+
146
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:
67
+.. warning::
68
+ In actual physical Versal, BBRAM and eFUSE contain sensitive data.
69
+ The QEMU device models do **not** encrypt nor obfuscate any data
70
+ when holding them in models' memory or when writing them to their
71
+ file backends.
147
+
72
+
148
+.. code-block:: bash
73
+ Thus, a file backend should be used with caution, and 'format=luks'
74
+ is highly recommended (albeit with usage complexity).
149
+
75
+
150
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
76
+ Better yet, do not use actual product data when running guest image
151
+ -kernel /path/to/linux/arch/arm/boot/zImage \
77
+ on this Xilinx Versal Virt board.
152
+ -append 'console=ttyS0,115200' \
153
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
154
+
155
+Orange Pi PC images
156
+"""""""""""""""""""
157
+
158
+Note that the mainline kernel does not have a root filesystem. You may provide it
159
+with an official Orange Pi PC image from the official website:
160
+
161
+ http://www.orangepi.org/downloadresources/
162
+
163
+Another possibility is to run an Armbian image for Orange Pi PC which
164
+can be downloaded from:
165
+
166
+ https://www.armbian.com/orange-pi-pc/
167
+
168
+Alternatively, you can also choose to build you own image with buildroot
169
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.
170
+
171
+You can choose to attach the selected image either as an SD card or as USB mass storage.
172
+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd
173
+argument and provide the proper root= kernel parameter:
174
+
175
+.. code-block:: bash
176
+
177
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
178
+ -kernel /path/to/linux/arch/arm/boot/zImage \
179
+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \
180
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
181
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
182
+
183
+To attach the image as an USB mass storage device to the machine,
184
+simply append to the command:
185
+
186
+.. code-block:: bash
187
+
188
+ -drive if=none,id=stick,file=myimage.img \
189
+ -device usb-storage,bus=usb-bus.0,drive=stick
190
+
191
+Instead of providing a custom Linux kernel via the -kernel command you may also
192
+choose to let the Orange Pi PC machine load the bootloader from SD card, just like
193
+a real board would do using the BootROM. Simply pass the selected image via the -sd
194
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
195
+
196
+.. code-block:: bash
197
+
198
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
199
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
200
+
201
+Note that both the official Orange Pi PC images and Armbian images start
202
+a lot of userland programs via systemd. Depending on the host hardware and OS,
203
+they may be slow to emulate, especially due to emulating the 4 cores.
204
+To help reduce the performance slow down due to emulating the 4 cores, you can
205
+give the following kernel parameters via U-Boot (or via -append):
206
+
207
+.. code-block:: bash
208
+
209
+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'
210
+
211
+Running U-Boot
212
+""""""""""""""
213
+
214
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
215
+using similar commands as describe above for Linux. Note that it is recommended
216
+for development/testing to select the following configuration setting in U-Boot:
217
+
218
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
219
+
220
+To start U-Boot using the Orange Pi PC machine, provide the
221
+u-boot binary to the -kernel argument:
222
+
223
+.. code-block:: bash
224
+
225
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
226
+ -kernel /path/to/uboot/u-boot -sd disk.img
227
+
228
+Use the following U-boot commands to load and boot a Linux kernel from SD card:
229
+
230
+.. code-block:: bash
231
+
232
+ => setenv bootargs console=ttyS0,115200
233
+ => ext2load mmc 0 0x42000000 zImage
234
+ => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
235
+ => bootz 0x42000000 - 0x43000000
236
+
237
+Running NetBSD
238
+""""""""""""""
239
+
240
+The NetBSD operating system also includes support for Allwinner H3 based boards,
241
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC
242
+board and provides a fully working system with serial console, networking and storage.
243
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
244
+
245
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz
246
+
247
+The image requires manually installing U-Boot in the image. Build U-Boot with
248
+the orangepi_pc_defconfig configuration as described in the previous section.
249
+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:
250
+
251
+.. code-block:: bash
252
+
253
+ $ gunzip armv7.img.gz
254
+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc
255
+
256
+Finally, before starting the machine the SD image must be extended such
257
+that the NetBSD kernel will not conclude the NetBSD partition is larger than
258
+the emulated SD card:
259
+
260
+.. code-block:: bash
261
+
262
+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img
263
+
264
+Start the machine using the following command:
265
+
266
+.. code-block:: bash
267
+
268
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
269
+ -sd armv7.img -global allwinner-rtc.base-year=2000
270
+
271
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
272
+and set the following environment variables before booting:
273
+
274
+.. code-block:: bash
275
+
276
+ => setenv bootargs root=ld0a
277
+ => setenv kernel netbsd-GENERIC.ub
278
+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
279
+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'
280
+
281
+Optionally you may save the environment variables to SD card with 'saveenv'.
282
+To continue booting simply give the 'boot' command and NetBSD boots.
283
+
284
+Orange Pi PC acceptance tests
285
+"""""""""""""""""""""""""""""
286
+
287
+The Orange Pi PC machine has several acceptance tests included.
288
+To run the whole set of tests, build QEMU from source and simply
289
+provide the following command:
290
+
291
+.. code-block:: bash
292
+
293
+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \
294
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
295
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
296
index XXXXXXX..XXXXXXX 100644
297
--- a/docs/system/target-arm.rst
298
+++ b/docs/system/target-arm.rst
299
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
300
``qemu-system-aarch64 --machine help``.
301
302
.. toctree::
303
+ :maxdepth: 1
304
305
arm/integratorcp
306
arm/versatile
307
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
308
arm/stellaris
309
arm/musicpal
310
arm/sx1
311
+ arm/orangepi
312
313
Arm CPU features
314
================
315
--
78
--
316
2.20.1
79
2.20.1
317
80
318
81
diff view generated by jsdifflib
1
Fix a couple of comment typos.
1
The aarch64-linux QEMU usermode binaries can never run 32-bit
2
code, so they do not need to include the GDB XML for it.
3
(arm_cpu_register_gdb_regs_for_features() will not use these
4
XML files if the CPU has ARM_FEATURE_AARCH64, so we will not
5
advertise to gdb that we have them.)
2
6
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200303174950.3298-5-peter.maydell@linaro.org
9
Message-id: 20210921162901.17508-2-peter.maydell@linaro.org
6
---
10
---
7
target/arm/helper.c | 2 +-
11
configs/targets/aarch64-linux-user.mak | 2 +-
8
target/arm/translate.c | 2 +-
12
configs/targets/aarch64_be-linux-user.mak | 2 +-
9
2 files changed, 2 insertions(+), 2 deletions(-)
13
2 files changed, 2 insertions(+), 2 deletions(-)
10
14
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
17
--- a/configs/targets/aarch64-linux-user.mak
14
+++ b/target/arm/helper.c
18
+++ b/configs/targets/aarch64-linux-user.mak
15
@@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
19
@@ -XXX,XX +XXX,XX @@
16
20
TARGET_ARCH=aarch64
17
/*
21
TARGET_BASE_ARCH=arm
18
* If we have triggered a EL state change we can't rely on the
22
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
19
- * translator having passed it too us, we need to recompute.
23
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
20
+ * translator having passed it to us, we need to recompute.
24
TARGET_HAS_BFLT=y
21
*/
25
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
22
void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
26
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
23
{
24
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate.c
28
--- a/configs/targets/aarch64_be-linux-user.mak
27
+++ b/target/arm/translate.c
29
+++ b/configs/targets/aarch64_be-linux-user.mak
28
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
30
@@ -XXX,XX +XXX,XX @@
29
31
TARGET_ARCH=aarch64
30
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
32
TARGET_BASE_ARCH=arm
31
/*
33
TARGET_WORDS_BIGENDIAN=y
32
- * A write to any coprocessor regiser that ends a TB
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
33
+ * A write to any coprocessor register that ends a TB
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
34
* must rebuild the hflags for the next TB.
36
TARGET_HAS_BFLT=y
35
*/
37
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
36
TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
37
--
38
--
38
2.20.1
39
2.20.1
39
40
40
41
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We're going to move this code to a different file; fix the coding
2
style first so checkpatch doesn't complain. This includes deleting
3
the spurious 'break' statements after returns in the
4
vfp_gdb_get_reg() function.
2
5
3
We fail to validate the upper bits of a virtual address on a
4
translation disabled regime, as per AArch64.TranslateAddressS1Off.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200308012946.16303-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210921162901.17508-3-peter.maydell@linaro.org
10
---
10
---
11
target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++-
11
target/arm/helper.c | 23 ++++++++++++++++-------
12
1 file changed, 34 insertions(+), 1 deletion(-)
12
1 file changed, 16 insertions(+), 7 deletions(-)
13
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
18
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
19
/* Definitely a real MMU, not an MPU */
19
}
20
20
}
21
if (regime_translation_disabled(env, mmu_idx)) {
21
switch (reg - nregs) {
22
- /* MMU disabled. */
22
- case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
23
+ /*
23
- case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
24
+ * MMU disabled. S1 addresses within aa64 translation regimes are
24
- case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
25
+ * still checked for bounds -- see AArch64.TranslateAddressS1Off.
25
+ case 0:
26
+ */
26
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
27
+ if (mmu_idx != ARMMMUIdx_Stage2) {
27
+ case 1:
28
+ int r_el = regime_el(env, mmu_idx);
28
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
29
+ if (arm_el_is_aa64(env, r_el)) {
29
+ case 2:
30
+ int pamax = arm_pamax(env_archcpu(env));
30
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
31
+ uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
31
}
32
+ int addrtop, tbi;
32
return 0;
33
+
33
}
34
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
34
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
35
+ if (access_type == MMU_INST_FETCH) {
35
}
36
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
36
}
37
+ }
37
switch (reg - nregs) {
38
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
38
- case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
39
+ addrtop = (tbi ? 55 : 63);
39
- case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
40
+
40
- case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
41
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
41
+ case 0:
42
+ fi->type = ARMFault_AddressSize;
42
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
43
+ fi->level = 0;
43
+ return 4;
44
+ fi->stage2 = false;
44
+ case 1:
45
+ return 1;
45
+ vfp_set_fpscr(env, ldl_p(buf));
46
+ }
46
+ return 4;
47
+
47
+ case 2:
48
+ /*
48
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
49
+ * When TBI is disabled, we've just validated that all of the
49
+ return 4;
50
+ * bits above PAMax are zero, so logically we only need to
50
}
51
+ * clear the top byte for TBI. But it's clearer to follow
51
return 0;
52
+ * the pseudocode set of addrdesc.paddress.
52
}
53
+ */
53
@@ -XXX,XX +XXX,XX @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
54
+ address = extract64(address, 0, 52);
54
return gdb_get_reg32(buf, vfp_get_fpsr(env));
55
+ }
55
case 33:
56
+ }
56
/* FPCR */
57
*phys_ptr = address;
57
- return gdb_get_reg32(buf,vfp_get_fpcr(env));
58
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
58
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
59
*page_size = TARGET_PAGE_SIZE;
59
default:
60
return 0;
61
}
60
--
62
--
61
2.20.1
63
2.20.1
62
64
63
65
diff view generated by jsdifflib
1
A write to the CONTROL register can change our current EL (by
1
Currently helper.c includes some code which is part of the arm
2
writing to the nPRIV bit). That means that we can't assume
2
target's gdbstub support. This code has a better home: in gdbstub.c
3
that s->current_el is still valid in trans_MSR_v7m() when
3
and gdbstub64.c. Move it there.
4
we try to rebuild the hflags.
5
4
6
Add a new helper rebuild_hflags_m32_newel() which, like the
5
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
7
existing rebuild_hflags_a32_newel(), recalculates the current
6
into gdbstub64.c, this means that they're now compiled only for
8
EL from scratch, and use it in trans_MSR_v7m().
7
TARGET_AARCH64 rather than always. That is the only case when they
9
8
would ever be used, but it does mean that the ifdef in
10
This fixes an assertion about an hflags mismatch when the
9
arm_cpu_register_gdb_regs_for_features() needs to be adjusted to
11
guest changes privilege by writing to CONTROL.
10
match.
12
11
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200303174950.3298-4-peter.maydell@linaro.org
15
Message-id: 20210921162901.17508-4-peter.maydell@linaro.org
16
---
16
---
17
target/arm/helper.h | 1 +
17
target/arm/internals.h | 7 ++
18
target/arm/helper.c | 12 ++++++++++++
18
target/arm/gdbstub.c | 130 ++++++++++++++++++++
19
target/arm/translate.c | 7 +++----
19
target/arm/gdbstub64.c | 140 +++++++++++++++++++++
20
3 files changed, 16 insertions(+), 4 deletions(-)
20
target/arm/helper.c | 271 -----------------------------------------
21
4 files changed, 277 insertions(+), 271 deletions(-)
21
22
22
diff --git a/target/arm/helper.h b/target/arm/helper.h
23
diff --git a/target/arm/internals.h b/target/arm/internals.h
23
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.h
25
--- a/target/arm/internals.h
25
+++ b/target/arm/helper.h
26
+++ b/target/arm/internals.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
27
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
27
DEF_HELPER_2(get_user_reg, i32, env, i32)
28
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
28
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
29
}
29
30
30
+DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env)
31
+#ifdef TARGET_AARCH64
31
DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
32
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
32
DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
33
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
33
DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
34
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
35
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
36
+#endif
37
+
38
#endif
39
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/gdbstub.c
42
+++ b/target/arm/gdbstub.c
43
@@ -XXX,XX +XXX,XX @@
44
*/
45
#include "qemu/osdep.h"
46
#include "cpu.h"
47
+#include "internals.h"
48
#include "exec/gdbstub.h"
49
50
typedef struct RegisterSysregXmlParam {
51
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
52
return 0;
53
}
54
55
+static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
56
+{
57
+ ARMCPU *cpu = env_archcpu(env);
58
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
59
+
60
+ /* VFP data registers are always little-endian. */
61
+ if (reg < nregs) {
62
+ return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
63
+ }
64
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
65
+ /* Aliases for Q regs. */
66
+ nregs += 16;
67
+ if (reg < nregs) {
68
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
69
+ return gdb_get_reg128(buf, q[0], q[1]);
70
+ }
71
+ }
72
+ switch (reg - nregs) {
73
+ case 0:
74
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
75
+ case 1:
76
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
77
+ case 2:
78
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
79
+ }
80
+ return 0;
81
+}
82
+
83
+static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
84
+{
85
+ ARMCPU *cpu = env_archcpu(env);
86
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
87
+
88
+ if (reg < nregs) {
89
+ *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
90
+ return 8;
91
+ }
92
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
93
+ nregs += 16;
94
+ if (reg < nregs) {
95
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
96
+ q[0] = ldq_le_p(buf);
97
+ q[1] = ldq_le_p(buf + 8);
98
+ return 16;
99
+ }
100
+ }
101
+ switch (reg - nregs) {
102
+ case 0:
103
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
104
+ return 4;
105
+ case 1:
106
+ vfp_set_fpscr(env, ldl_p(buf));
107
+ return 4;
108
+ case 2:
109
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
110
+ return 4;
111
+ }
112
+ return 0;
113
+}
114
+
115
+/**
116
+ * arm_get/set_gdb_*: get/set a gdb register
117
+ * @env: the CPU state
118
+ * @buf: a buffer to copy to/from
119
+ * @reg: register number (offset from start of group)
120
+ *
121
+ * We return the number of bytes copied
122
+ */
123
+
124
+static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
125
+{
126
+ ARMCPU *cpu = env_archcpu(env);
127
+ const ARMCPRegInfo *ri;
128
+ uint32_t key;
129
+
130
+ key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
131
+ ri = get_arm_cp_reginfo(cpu->cp_regs, key);
132
+ if (ri) {
133
+ if (cpreg_field_is_64bit(ri)) {
134
+ return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
135
+ } else {
136
+ return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
137
+ }
138
+ }
139
+ return 0;
140
+}
141
+
142
+static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
143
+{
144
+ return 0;
145
+}
146
+
147
static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
148
ARMCPRegInfo *ri, uint32_t ri_key,
149
int bitsize, int regnum)
150
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
151
}
152
return NULL;
153
}
154
+
155
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
156
+{
157
+ CPUState *cs = CPU(cpu);
158
+ CPUARMState *env = &cpu->env;
159
+
160
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
161
+ /*
162
+ * The lower part of each SVE register aliases to the FPU
163
+ * registers so we don't need to include both.
164
+ */
165
+#ifdef TARGET_AARCH64
166
+ if (isar_feature_aa64_sve(&cpu->isar)) {
167
+ gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
168
+ arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
169
+ "sve-registers.xml", 0);
170
+ } else {
171
+ gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
172
+ aarch64_fpu_gdb_set_reg,
173
+ 34, "aarch64-fpu.xml", 0);
174
+ }
175
+#endif
176
+ } else if (arm_feature(env, ARM_FEATURE_NEON)) {
177
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
178
+ 51, "arm-neon.xml", 0);
179
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
180
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
181
+ 35, "arm-vfp3.xml", 0);
182
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
183
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
184
+ 19, "arm-vfp.xml", 0);
185
+ }
186
+ gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
187
+ arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
188
+ "system-registers.xml", 0);
189
+
190
+}
191
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
192
index XXXXXXX..XXXXXXX 100644
193
--- a/target/arm/gdbstub64.c
194
+++ b/target/arm/gdbstub64.c
195
@@ -XXX,XX +XXX,XX @@
196
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
197
*/
198
#include "qemu/osdep.h"
199
+#include "qemu/log.h"
200
#include "cpu.h"
201
+#include "internals.h"
202
#include "exec/gdbstub.h"
203
204
int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
205
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
206
/* Unknown register. */
207
return 0;
208
}
209
+
210
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
211
+{
212
+ switch (reg) {
213
+ case 0 ... 31:
214
+ {
215
+ /* 128 bit FP register - quads are in LE order */
216
+ uint64_t *q = aa64_vfp_qreg(env, reg);
217
+ return gdb_get_reg128(buf, q[1], q[0]);
218
+ }
219
+ case 32:
220
+ /* FPSR */
221
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
222
+ case 33:
223
+ /* FPCR */
224
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
225
+ default:
226
+ return 0;
227
+ }
228
+}
229
+
230
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
231
+{
232
+ switch (reg) {
233
+ case 0 ... 31:
234
+ /* 128 bit FP register */
235
+ {
236
+ uint64_t *q = aa64_vfp_qreg(env, reg);
237
+ q[0] = ldq_le_p(buf);
238
+ q[1] = ldq_le_p(buf + 8);
239
+ return 16;
240
+ }
241
+ case 32:
242
+ /* FPSR */
243
+ vfp_set_fpsr(env, ldl_p(buf));
244
+ return 4;
245
+ case 33:
246
+ /* FPCR */
247
+ vfp_set_fpcr(env, ldl_p(buf));
248
+ return 4;
249
+ default:
250
+ return 0;
251
+ }
252
+}
253
+
254
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
255
+{
256
+ ARMCPU *cpu = env_archcpu(env);
257
+
258
+ switch (reg) {
259
+ /* The first 32 registers are the zregs */
260
+ case 0 ... 31:
261
+ {
262
+ int vq, len = 0;
263
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
264
+ len += gdb_get_reg128(buf,
265
+ env->vfp.zregs[reg].d[vq * 2 + 1],
266
+ env->vfp.zregs[reg].d[vq * 2]);
267
+ }
268
+ return len;
269
+ }
270
+ case 32:
271
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
272
+ case 33:
273
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
274
+ /* then 16 predicates and the ffr */
275
+ case 34 ... 50:
276
+ {
277
+ int preg = reg - 34;
278
+ int vq, len = 0;
279
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
280
+ len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
281
+ }
282
+ return len;
283
+ }
284
+ case 51:
285
+ {
286
+ /*
287
+ * We report in Vector Granules (VG) which is 64bit in a Z reg
288
+ * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
289
+ */
290
+ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
291
+ return gdb_get_reg64(buf, vq * 2);
292
+ }
293
+ default:
294
+ /* gdbstub asked for something out our range */
295
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
296
+ break;
297
+ }
298
+
299
+ return 0;
300
+}
301
+
302
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
303
+{
304
+ ARMCPU *cpu = env_archcpu(env);
305
+
306
+ /* The first 32 registers are the zregs */
307
+ switch (reg) {
308
+ /* The first 32 registers are the zregs */
309
+ case 0 ... 31:
310
+ {
311
+ int vq, len = 0;
312
+ uint64_t *p = (uint64_t *) buf;
313
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
314
+ env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
315
+ env->vfp.zregs[reg].d[vq * 2] = *p++;
316
+ len += 16;
317
+ }
318
+ return len;
319
+ }
320
+ case 32:
321
+ vfp_set_fpsr(env, *(uint32_t *)buf);
322
+ return 4;
323
+ case 33:
324
+ vfp_set_fpcr(env, *(uint32_t *)buf);
325
+ return 4;
326
+ case 34 ... 50:
327
+ {
328
+ int preg = reg - 34;
329
+ int vq, len = 0;
330
+ uint64_t *p = (uint64_t *) buf;
331
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
332
+ env->vfp.pregs[preg].p[vq / 4] = *p++;
333
+ len += 8;
334
+ }
335
+ return len;
336
+ }
337
+ case 51:
338
+ /* cannot set vg via gdbstub */
339
+ return 0;
340
+ default:
341
+ /* gdbstub asked for something out our range */
342
+ break;
343
+ }
344
+
345
+ return 0;
346
+}
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
347
diff --git a/target/arm/helper.c b/target/arm/helper.c
35
index XXXXXXX..XXXXXXX 100644
348
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
349
--- a/target/arm/helper.c
37
+++ b/target/arm/helper.c
350
+++ b/target/arm/helper.c
38
@@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env)
351
@@ -XXX,XX +XXX,XX @@
39
env->hflags = rebuild_hflags_internal(env);
352
#include "trace.h"
353
#include "cpu.h"
354
#include "internals.h"
355
-#include "exec/gdbstub.h"
356
#include "exec/helper-proto.h"
357
#include "qemu/host-utils.h"
358
#include "qemu/main-loop.h"
359
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
360
static void switch_mode(CPUARMState *env, int mode);
361
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
362
363
-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
364
-{
365
- ARMCPU *cpu = env_archcpu(env);
366
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
367
-
368
- /* VFP data registers are always little-endian. */
369
- if (reg < nregs) {
370
- return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
371
- }
372
- if (arm_feature(env, ARM_FEATURE_NEON)) {
373
- /* Aliases for Q regs. */
374
- nregs += 16;
375
- if (reg < nregs) {
376
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
377
- return gdb_get_reg128(buf, q[0], q[1]);
378
- }
379
- }
380
- switch (reg - nregs) {
381
- case 0:
382
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
383
- case 1:
384
- return gdb_get_reg32(buf, vfp_get_fpscr(env));
385
- case 2:
386
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
387
- }
388
- return 0;
389
-}
390
-
391
-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
392
-{
393
- ARMCPU *cpu = env_archcpu(env);
394
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
395
-
396
- if (reg < nregs) {
397
- *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
398
- return 8;
399
- }
400
- if (arm_feature(env, ARM_FEATURE_NEON)) {
401
- nregs += 16;
402
- if (reg < nregs) {
403
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
404
- q[0] = ldq_le_p(buf);
405
- q[1] = ldq_le_p(buf + 8);
406
- return 16;
407
- }
408
- }
409
- switch (reg - nregs) {
410
- case 0:
411
- env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
412
- return 4;
413
- case 1:
414
- vfp_set_fpscr(env, ldl_p(buf));
415
- return 4;
416
- case 2:
417
- env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
418
- return 4;
419
- }
420
- return 0;
421
-}
422
-
423
-static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
424
-{
425
- switch (reg) {
426
- case 0 ... 31:
427
- {
428
- /* 128 bit FP register - quads are in LE order */
429
- uint64_t *q = aa64_vfp_qreg(env, reg);
430
- return gdb_get_reg128(buf, q[1], q[0]);
431
- }
432
- case 32:
433
- /* FPSR */
434
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
435
- case 33:
436
- /* FPCR */
437
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
438
- default:
439
- return 0;
440
- }
441
-}
442
-
443
-static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
444
-{
445
- switch (reg) {
446
- case 0 ... 31:
447
- /* 128 bit FP register */
448
- {
449
- uint64_t *q = aa64_vfp_qreg(env, reg);
450
- q[0] = ldq_le_p(buf);
451
- q[1] = ldq_le_p(buf + 8);
452
- return 16;
453
- }
454
- case 32:
455
- /* FPSR */
456
- vfp_set_fpsr(env, ldl_p(buf));
457
- return 4;
458
- case 33:
459
- /* FPCR */
460
- vfp_set_fpcr(env, ldl_p(buf));
461
- return 4;
462
- default:
463
- return 0;
464
- }
465
-}
466
-
467
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
468
{
469
assert(ri->fieldoffset);
470
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
471
}
40
}
472
}
41
473
42
+/*
474
-/**
43
+ * If we have triggered a EL state change we can't rely on the
475
- * arm_get/set_gdb_*: get/set a gdb register
44
+ * translator having passed it to us, we need to recompute.
476
- * @env: the CPU state
45
+ */
477
- * @buf: a buffer to copy to/from
46
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
478
- * @reg: register number (offset from start of group)
47
+{
479
- *
48
+ int el = arm_current_el(env);
480
- * We return the number of bytes copied
49
+ int fp_el = fp_exception_el(env, el);
481
- */
50
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
482
-
51
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
483
-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
52
+}
484
-{
53
+
485
- ARMCPU *cpu = env_archcpu(env);
54
void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
486
- const ARMCPRegInfo *ri;
487
- uint32_t key;
488
-
489
- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
490
- ri = get_arm_cp_reginfo(cpu->cp_regs, key);
491
- if (ri) {
492
- if (cpreg_field_is_64bit(ri)) {
493
- return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
494
- } else {
495
- return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
496
- }
497
- }
498
- return 0;
499
-}
500
-
501
-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
502
-{
503
- return 0;
504
-}
505
-
506
-#ifdef TARGET_AARCH64
507
-static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
508
-{
509
- ARMCPU *cpu = env_archcpu(env);
510
-
511
- switch (reg) {
512
- /* The first 32 registers are the zregs */
513
- case 0 ... 31:
514
- {
515
- int vq, len = 0;
516
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
517
- len += gdb_get_reg128(buf,
518
- env->vfp.zregs[reg].d[vq * 2 + 1],
519
- env->vfp.zregs[reg].d[vq * 2]);
520
- }
521
- return len;
522
- }
523
- case 32:
524
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
525
- case 33:
526
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
527
- /* then 16 predicates and the ffr */
528
- case 34 ... 50:
529
- {
530
- int preg = reg - 34;
531
- int vq, len = 0;
532
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
533
- len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
534
- }
535
- return len;
536
- }
537
- case 51:
538
- {
539
- /*
540
- * We report in Vector Granules (VG) which is 64bit in a Z reg
541
- * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
542
- */
543
- int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
544
- return gdb_get_reg64(buf, vq * 2);
545
- }
546
- default:
547
- /* gdbstub asked for something out our range */
548
- qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
549
- break;
550
- }
551
-
552
- return 0;
553
-}
554
-
555
-static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
556
-{
557
- ARMCPU *cpu = env_archcpu(env);
558
-
559
- /* The first 32 registers are the zregs */
560
- switch (reg) {
561
- /* The first 32 registers are the zregs */
562
- case 0 ... 31:
563
- {
564
- int vq, len = 0;
565
- uint64_t *p = (uint64_t *) buf;
566
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
567
- env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
568
- env->vfp.zregs[reg].d[vq * 2] = *p++;
569
- len += 16;
570
- }
571
- return len;
572
- }
573
- case 32:
574
- vfp_set_fpsr(env, *(uint32_t *)buf);
575
- return 4;
576
- case 33:
577
- vfp_set_fpcr(env, *(uint32_t *)buf);
578
- return 4;
579
- case 34 ... 50:
580
- {
581
- int preg = reg - 34;
582
- int vq, len = 0;
583
- uint64_t *p = (uint64_t *) buf;
584
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
585
- env->vfp.pregs[preg].p[vq / 4] = *p++;
586
- len += 8;
587
- }
588
- return len;
589
- }
590
- case 51:
591
- /* cannot set vg via gdbstub */
592
- return 0;
593
- default:
594
- /* gdbstub asked for something out our range */
595
- break;
596
- }
597
-
598
- return 0;
599
-}
600
-#endif /* TARGET_AARCH64 */
601
-
602
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
55
{
603
{
56
int fp_el = fp_exception_el(env, el);
604
/* Return true if the regdef would cause an assertion if you called
57
diff --git a/target/arm/translate.c b/target/arm/translate.c
605
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
58
index XXXXXXX..XXXXXXX 100644
606
#endif
59
--- a/target/arm/translate.c
607
}
60
+++ b/target/arm/translate.c
608
61
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
609
-void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
62
610
-{
63
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
611
- CPUState *cs = CPU(cpu);
612
- CPUARMState *env = &cpu->env;
613
-
614
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
615
- /*
616
- * The lower part of each SVE register aliases to the FPU
617
- * registers so we don't need to include both.
618
- */
619
-#ifdef TARGET_AARCH64
620
- if (isar_feature_aa64_sve(&cpu->isar)) {
621
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
622
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
623
- "sve-registers.xml", 0);
624
- } else
625
-#endif
626
- {
627
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
628
- aarch64_fpu_gdb_set_reg,
629
- 34, "aarch64-fpu.xml", 0);
630
- }
631
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
632
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
633
- 51, "arm-neon.xml", 0);
634
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
635
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
636
- 35, "arm-vfp3.xml", 0);
637
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
638
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
639
- 19, "arm-vfp.xml", 0);
640
- }
641
- gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
642
- arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
643
- "system-registers.xml", 0);
644
-
645
-}
646
-
647
/* Sort alphabetically by type name, except for "any". */
648
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
64
{
649
{
65
- TCGv_i32 addr, reg, el;
66
+ TCGv_i32 addr, reg;
67
68
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
69
return false;
70
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
71
gen_helper_v7m_msr(cpu_env, addr, reg);
72
tcg_temp_free_i32(addr);
73
tcg_temp_free_i32(reg);
74
- el = tcg_const_i32(s->current_el);
75
- gen_helper_rebuild_hflags_m32(cpu_env, el);
76
- tcg_temp_free_i32(el);
77
+ /* If we wrote to CONTROL, the EL might have changed */
78
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
79
gen_lookup_tb(s);
80
return true;
81
}
82
--
650
--
83
2.20.1
651
2.20.1
84
652
85
653
diff view generated by jsdifflib
1
Some of an M-profile CPU's cached hflags state depends on state that's
1
Currently we send VFP XML which includes D0..D15 or D0..D31, plus
2
in our NVIC object. We already do an hflags rebuild when the NVIC
2
FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its
3
registers are written, but we also need to do this on NVIC reset,
3
definition of this XML feature does not include FPSID or FPEXC. In
4
because there's no guarantee that this will happen before the
4
particular, for M-profile cores there are no FPSID or FPEXC
5
CPU reset.
5
registers, so advertising those is wrong.
6
6
7
This fixes an assertion due to mismatched hflags which happens if
7
Move FPSID and FPEXC into their own bit of XML which we only send for
8
the CPU is reset from inside a HardFault handler.
8
A and R profile cores. This brings our definition of the XML
9
org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for
10
non-Neon cores...) and means we don't claim to have FPSID and FPEXC
11
on M-profile.
12
13
(It seems unlikely to me that any gdbstub users really care about
14
being able to look at FPEXC and FPSID; but we've supplied them to gdb
15
for a decade and it's not hard to keep doing so.)
9
16
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200303174950.3298-2-peter.maydell@linaro.org
19
Message-id: 20210921162901.17508-5-peter.maydell@linaro.org
13
---
20
---
14
hw/intc/armv7m_nvic.c | 6 ++++++
21
configs/targets/aarch64-softmmu.mak | 2 +-
15
1 file changed, 6 insertions(+)
22
configs/targets/arm-linux-user.mak | 2 +-
16
23
configs/targets/arm-softmmu.mak | 2 +-
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
24
configs/targets/armeb-linux-user.mak | 2 +-
18
index XXXXXXX..XXXXXXX 100644
25
target/arm/gdbstub.c | 56 ++++++++++++++++++++--------
19
--- a/hw/intc/armv7m_nvic.c
26
gdb-xml/arm-neon.xml | 2 -
20
+++ b/hw/intc/armv7m_nvic.c
27
gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++
21
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
28
gdb-xml/arm-vfp.xml | 2 -
22
s->itns[i] = true;
29
gdb-xml/arm-vfp3.xml | 2 -
30
9 files changed, 61 insertions(+), 26 deletions(-)
31
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
32
33
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
34
index XXXXXXX..XXXXXXX 100644
35
--- a/configs/targets/aarch64-softmmu.mak
36
+++ b/configs/targets/aarch64-softmmu.mak
37
@@ -XXX,XX +XXX,XX @@
38
TARGET_ARCH=aarch64
39
TARGET_BASE_ARCH=arm
40
TARGET_SUPPORTS_MTTCG=y
41
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
42
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
43
TARGET_NEED_FDT=y
44
diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak
45
index XXXXXXX..XXXXXXX 100644
46
--- a/configs/targets/arm-linux-user.mak
47
+++ b/configs/targets/arm-linux-user.mak
48
@@ -XXX,XX +XXX,XX @@
49
TARGET_ARCH=arm
50
TARGET_SYSTBL_ABI=common,oabi
51
TARGET_SYSTBL=syscall.tbl
52
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
53
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
54
TARGET_HAS_BFLT=y
55
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
56
diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak
57
index XXXXXXX..XXXXXXX 100644
58
--- a/configs/targets/arm-softmmu.mak
59
+++ b/configs/targets/arm-softmmu.mak
60
@@ -XXX,XX +XXX,XX @@
61
TARGET_ARCH=arm
62
TARGET_SUPPORTS_MTTCG=y
63
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
64
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
65
TARGET_NEED_FDT=y
66
diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak
67
index XXXXXXX..XXXXXXX 100644
68
--- a/configs/targets/armeb-linux-user.mak
69
+++ b/configs/targets/armeb-linux-user.mak
70
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=arm
71
TARGET_SYSTBL_ABI=common,oabi
72
TARGET_SYSTBL=syscall.tbl
73
TARGET_WORDS_BIGENDIAN=y
74
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
75
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
76
TARGET_HAS_BFLT=y
77
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
78
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/gdbstub.c
81
+++ b/target/arm/gdbstub.c
82
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
83
}
84
switch (reg - nregs) {
85
case 0:
86
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
87
- case 1:
88
return gdb_get_reg32(buf, vfp_get_fpscr(env));
89
- case 2:
90
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
91
}
92
return 0;
93
}
94
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
23
}
95
}
24
}
96
}
25
+
97
switch (reg - nregs) {
26
+ /*
98
+ case 0:
27
+ * We updated state that affects the CPU's MMUidx and thus its hflags;
99
+ vfp_set_fpscr(env, ldl_p(buf));
28
+ * and we can't guarantee that we run before the CPU reset function.
100
+ return 4;
29
+ */
101
+ }
30
+ arm_rebuild_hflags(&s->cpu->env);
102
+ return 0;
31
}
103
+}
32
104
+
33
static void nvic_systick_trigger(void *opaque, int n, int level)
105
+static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
106
+{
107
+ switch (reg) {
108
+ case 0:
109
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
110
+ case 1:
111
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
112
+ }
113
+ return 0;
114
+}
115
+
116
+static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
117
+{
118
+ switch (reg) {
119
case 0:
120
env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
121
return 4;
122
case 1:
123
- vfp_set_fpscr(env, ldl_p(buf));
124
- return 4;
125
- case 2:
126
env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
127
return 4;
128
}
129
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
130
34, "aarch64-fpu.xml", 0);
131
}
132
#endif
133
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
134
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
135
- 51, "arm-neon.xml", 0);
136
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
137
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
138
- 35, "arm-vfp3.xml", 0);
139
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
140
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
141
- 19, "arm-vfp.xml", 0);
142
+ } else {
143
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
144
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
145
+ 49, "arm-neon.xml", 0);
146
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
147
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
148
+ 33, "arm-vfp3.xml", 0);
149
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
150
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
151
+ 17, "arm-vfp.xml", 0);
152
+ }
153
+ if (!arm_feature(env, ARM_FEATURE_M)) {
154
+ /*
155
+ * A and R profile have FP sysregs FPEXC and FPSID that we
156
+ * expose to gdb.
157
+ */
158
+ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
159
+ 2, "arm-vfp-sysregs.xml", 0);
160
+ }
161
}
162
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
163
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
164
diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml
165
index XXXXXXX..XXXXXXX 100644
166
--- a/gdb-xml/arm-neon.xml
167
+++ b/gdb-xml/arm-neon.xml
168
@@ -XXX,XX +XXX,XX @@
169
<reg name="q14" bitsize="128" type="neon_q"/>
170
<reg name="q15" bitsize="128" type="neon_q"/>
171
172
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
173
<reg name="fpscr" bitsize="32" type="int" group="float"/>
174
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
175
</feature>
176
diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml
177
new file mode 100644
178
index XXXXXXX..XXXXXXX
179
--- /dev/null
180
+++ b/gdb-xml/arm-vfp-sysregs.xml
181
@@ -XXX,XX +XXX,XX @@
182
+<?xml version="1.0"?>
183
+<!-- Copyright (C) 2021 Linaro Ltd.
184
+
185
+ Copying and distribution of this file, with or without modification,
186
+ are permitted in any medium without royalty provided the copyright
187
+ notice and this notice are preserved.
188
+
189
+ These are A/R profile VFP system registers. Debugger users probably
190
+ don't really care about these, but because we used to (incorrectly)
191
+ provide them to gdb in the org.gnu.gdb.arm.vfp XML we continue
192
+ to do so via this separate XML.
193
+ -->
194
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
195
+<feature name="org.qemu.gdb.arm.vfp-sysregs">
196
+ <reg name="fpsid" bitsize="32" type="int" group="float"/>
197
+ <reg name="fpexc" bitsize="32" type="int" group="float"/>
198
+</feature>
199
diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml
200
index XXXXXXX..XXXXXXX 100644
201
--- a/gdb-xml/arm-vfp.xml
202
+++ b/gdb-xml/arm-vfp.xml
203
@@ -XXX,XX +XXX,XX @@
204
<reg name="d14" bitsize="64" type="float"/>
205
<reg name="d15" bitsize="64" type="float"/>
206
207
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
208
<reg name="fpscr" bitsize="32" type="int" group="float"/>
209
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
210
</feature>
211
diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml
212
index XXXXXXX..XXXXXXX 100644
213
--- a/gdb-xml/arm-vfp3.xml
214
+++ b/gdb-xml/arm-vfp3.xml
215
@@ -XXX,XX +XXX,XX @@
216
<reg name="d30" bitsize="64" type="float"/>
217
<reg name="d31" bitsize="64" type="float"/>
218
219
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
220
<reg name="fpscr" bitsize="32" type="int" group="float"/>
221
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
222
</feature>
34
--
223
--
35
2.20.1
224
2.20.1
36
225
37
226
diff view generated by jsdifflib
Deleted patch
1
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
2
(it changes the NegPri bit). We update the hflags after calls
3
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
4
in trans_CPS_v7m().
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200303174950.3298-3-peter.maydell@linaro.org
9
---
10
target/arm/translate.c | 5 ++++-
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
18
19
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
20
{
21
- TCGv_i32 tmp, addr;
22
+ TCGv_i32 tmp, addr, el;
23
24
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
25
return false;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
27
gen_helper_v7m_msr(cpu_env, addr, tmp);
28
tcg_temp_free_i32(addr);
29
}
30
+ el = tcg_const_i32(s->current_el);
31
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
32
+ tcg_temp_free_i32(el);
33
tcg_temp_free_i32(tmp);
34
gen_lookup_tb(s);
35
return true;
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
1
From: Beata Michalska <beata.michalska@linaro.org>
1
The function scsi_bus_new() creates a new SCSI bus; callers can
2
2
either pass in a name argument to specify the name of the new bus, or
3
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
3
they can pass in NULL to allow the bus to be given an automatically
4
As such this should be the last step of sync to avoid potential overwriting
4
generated unique name. Almost all callers want to use the
5
of whatever changes KVM might have done.
5
autogenerated name; the only exception is the virtio-scsi device.
6
6
7
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
7
Taking a name argument that should almost always be NULL is an
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
easy-to-misuse API design -- it encourages callers to think perhaps
9
Message-id: 20200312003401.29017-2-beata.michalska@linaro.org
9
they should pass in some standard name like "scsi" or "scsi-bus". We
10
don't do this anywhere for SCSI, but we do (incorrectly) do it for
11
other bus types such as i2c.
12
13
The function name also implies that it will return a newly allocated
14
object, when it in fact does in-place allocation. We more commonly
15
name such functions foo_init(), with foo_new() being the
16
allocate-and-return variant.
17
18
Replace all the scsi_bus_new() callsites with either:
19
* scsi_bus_init() for the usual case where the caller wants
20
an autogenerated bus name
21
* scsi_bus_init_named() for the rare case where the caller
22
needs to specify the bus name
23
24
and document that for the _named() version it's then the caller's
25
responsibility to think about uniqueness of bus names.
26
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
30
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
31
Message-id: 20210923121153.23754-2-peter.maydell@linaro.org
11
---
32
---
12
target/arm/kvm32.c | 15 ++++++++++-----
33
include/hw/scsi/scsi.h | 30 ++++++++++++++++++++++++++++--
13
target/arm/kvm64.c | 15 ++++++++++-----
34
hw/scsi/esp-pci.c | 2 +-
14
2 files changed, 20 insertions(+), 10 deletions(-)
35
hw/scsi/esp.c | 2 +-
15
36
hw/scsi/lsi53c895a.c | 2 +-
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
37
hw/scsi/megasas.c | 3 +--
17
index XXXXXXX..XXXXXXX 100644
38
hw/scsi/mptsas.c | 2 +-
18
--- a/target/arm/kvm32.c
39
hw/scsi/scsi-bus.c | 4 ++--
19
+++ b/target/arm/kvm32.c
40
hw/scsi/spapr_vscsi.c | 3 +--
20
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
41
hw/scsi/virtio-scsi.c | 4 ++--
21
return ret;
42
hw/scsi/vmw_pvscsi.c | 3 +--
43
hw/usb/dev-storage-bot.c | 3 +--
44
hw/usb/dev-storage-classic.c | 4 ++--
45
hw/usb/dev-uas.c | 3 +--
46
13 files changed, 43 insertions(+), 22 deletions(-)
47
48
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/scsi/scsi.h
51
+++ b/include/hw/scsi/scsi.h
52
@@ -XXX,XX +XXX,XX @@ struct SCSIBus {
53
const SCSIBusInfo *info;
54
};
55
56
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
57
- const SCSIBusInfo *info, const char *bus_name);
58
+/**
59
+ * scsi_bus_init_named: Initialize a SCSI bus with the specified name
60
+ * @bus: SCSIBus object to initialize
61
+ * @bus_size: size of @bus object
62
+ * @host: Device which owns the bus (generally the SCSI controller)
63
+ * @info: structure defining callbacks etc for the controller
64
+ * @bus_name: Name to use for this bus
65
+ *
66
+ * This in-place initializes @bus as a new SCSI bus with a name
67
+ * provided by the caller. It is the caller's responsibility to make
68
+ * sure that name does not clash with the name of any other bus in the
69
+ * system. Unless you need the new bus to have a specific name, you
70
+ * should use scsi_bus_new() instead.
71
+ */
72
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
73
+ const SCSIBusInfo *info, const char *bus_name);
74
+
75
+/**
76
+ * scsi_bus_init: Initialize a SCSI bus
77
+ *
78
+ * This in-place-initializes @bus as a new SCSI bus and gives it
79
+ * an automatically generated unique name.
80
+ */
81
+static inline void scsi_bus_init(SCSIBus *bus, size_t bus_size,
82
+ DeviceState *host, const SCSIBusInfo *info)
83
+{
84
+ scsi_bus_init_named(bus, bus_size, host, info, NULL);
85
+}
86
87
static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d)
88
{
89
diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/scsi/esp-pci.c
92
+++ b/hw/scsi/esp-pci.c
93
@@ -XXX,XX +XXX,XX @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
94
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
95
s->irq = pci_allocate_irq(dev);
96
97
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
98
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
99
}
100
101
static void esp_pci_scsi_exit(PCIDevice *d)
102
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/scsi/esp.c
105
+++ b/hw/scsi/esp.c
106
@@ -XXX,XX +XXX,XX @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp)
107
108
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
109
110
- scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
111
+ scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info);
112
}
113
114
static void sysbus_esp_hard_reset(DeviceState *dev)
115
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/scsi/lsi53c895a.c
118
+++ b/hw/scsi/lsi53c895a.c
119
@@ -XXX,XX +XXX,XX @@ static void lsi_scsi_realize(PCIDevice *dev, Error **errp)
120
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
121
QTAILQ_INIT(&s->queue);
122
123
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL);
124
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info);
125
}
126
127
static void lsi_scsi_exit(PCIDevice *dev)
128
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/scsi/megasas.c
131
+++ b/hw/scsi/megasas.c
132
@@ -XXX,XX +XXX,XX @@ static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
133
s->frames[i].state = s;
22
}
134
}
23
135
24
- ret = kvm_put_vcpu_events(cpu);
136
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
25
- if (ret) {
137
- &megasas_scsi_info, NULL);
26
- return ret;
138
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
27
- }
139
}
28
-
140
29
write_cpustate_to_list(cpu, true);
141
static Property megasas_properties_gen1[] = {
30
142
diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
31
if (!write_list_to_kvmstate(cpu, level)) {
143
index XXXXXXX..XXXXXXX 100644
32
return EINVAL;
144
--- a/hw/scsi/mptsas.c
145
+++ b/hw/scsi/mptsas.c
146
@@ -XXX,XX +XXX,XX @@ static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
147
148
s->request_bh = qemu_bh_new(mptsas_fetch_requests, s);
149
150
- scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL);
151
+ scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info);
152
}
153
154
static void mptsas_scsi_uninit(PCIDevice *dev)
155
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/scsi/scsi-bus.c
158
+++ b/hw/scsi/scsi-bus.c
159
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
160
}
161
162
/* Create a scsi bus, and attach devices to it. */
163
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
164
- const SCSIBusInfo *info, const char *bus_name)
165
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
166
+ const SCSIBusInfo *info, const char *bus_name)
167
{
168
qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
169
bus->busnr = next_scsi_bus++;
170
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/scsi/spapr_vscsi.c
173
+++ b/hw/scsi/spapr_vscsi.c
174
@@ -XXX,XX +XXX,XX @@ static void spapr_vscsi_realize(SpaprVioDevice *dev, Error **errp)
175
176
dev->crq.SendFunc = vscsi_do_crq;
177
178
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
179
- &vscsi_scsi_info, NULL);
180
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &vscsi_scsi_info);
181
182
/* ibmvscsi SCSI bus does not allow hotplug. */
183
qbus_set_hotplug_handler(BUS(&s->bus), NULL);
184
diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/scsi/virtio-scsi.c
187
+++ b/hw/scsi/virtio-scsi.c
188
@@ -XXX,XX +XXX,XX @@ static void virtio_scsi_device_realize(DeviceState *dev, Error **errp)
189
return;
33
}
190
}
34
191
35
+ /*
192
- scsi_bus_new(&s->bus, sizeof(s->bus), dev,
36
+ * Setting VCPU events should be triggered after syncing the registers
193
- &virtio_scsi_scsi_info, vdev->bus_name);
37
+ * to avoid overwriting potential changes made by KVM upon calling
194
+ scsi_bus_init_named(&s->bus, sizeof(s->bus), dev,
38
+ * KVM_SET_VCPU_EVENTS ioctl
195
+ &virtio_scsi_scsi_info, vdev->bus_name);
39
+ */
196
/* override default SCSI bus hotplug-handler, with virtio-scsi's one */
40
+ ret = kvm_put_vcpu_events(cpu);
197
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
41
+ if (ret) {
198
42
+ return ret;
199
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
43
+ }
200
index XXXXXXX..XXXXXXX 100644
44
+
201
--- a/hw/scsi/vmw_pvscsi.c
45
kvm_arm_sync_mpstate_to_kvm(cpu);
202
+++ b/hw/scsi/vmw_pvscsi.c
46
203
@@ -XXX,XX +XXX,XX @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
47
return ret;
204
48
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
205
s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
49
index XXXXXXX..XXXXXXX 100644
206
50
--- a/target/arm/kvm64.c
207
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
51
+++ b/target/arm/kvm64.c
208
- &pvscsi_scsi_info, NULL);
52
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
209
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info);
53
return ret;
210
/* override default SCSI bus hotplug-handler, with pvscsi's one */
211
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
212
pvscsi_reset_state(s);
213
diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/usb/dev-storage-bot.c
216
+++ b/hw/usb/dev-storage-bot.c
217
@@ -XXX,XX +XXX,XX @@ static void usb_msd_bot_realize(USBDevice *dev, Error **errp)
218
s->dev.auto_attach = 0;
54
}
219
}
55
220
56
- ret = kvm_put_vcpu_events(cpu);
221
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
57
- if (ret) {
222
- &usb_msd_scsi_info_bot, NULL);
58
- return ret;
223
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &usb_msd_scsi_info_bot);
59
- }
224
usb_msd_handle_reset(dev);
60
-
225
}
61
write_cpustate_to_list(cpu, true);
226
62
227
diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c
63
if (!write_list_to_kvmstate(cpu, level)) {
228
index XXXXXXX..XXXXXXX 100644
64
return -EINVAL;
229
--- a/hw/usb/dev-storage-classic.c
65
}
230
+++ b/hw/usb/dev-storage-classic.c
66
231
@@ -XXX,XX +XXX,XX @@ static void usb_msd_storage_realize(USBDevice *dev, Error **errp)
67
+ /*
232
usb_desc_create_serial(dev);
68
+ * Setting VCPU events should be triggered after syncing the registers
233
usb_desc_init(dev);
69
+ * to avoid overwriting potential changes made by KVM upon calling
234
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
70
+ * KVM_SET_VCPU_EVENTS ioctl
235
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
71
+ */
236
- &usb_msd_scsi_info_storage, NULL);
72
+ ret = kvm_put_vcpu_events(cpu);
237
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev),
73
+ if (ret) {
238
+ &usb_msd_scsi_info_storage);
74
+ return ret;
239
scsi_dev = scsi_bus_legacy_add_drive(&s->bus, blk, 0, !!s->removable,
75
+ }
240
s->conf.bootindex, s->conf.share_rw,
76
+
241
s->conf.rerror, s->conf.werror,
77
kvm_arm_sync_mpstate_to_kvm(cpu);
242
diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c
78
243
index XXXXXXX..XXXXXXX 100644
79
return ret;
244
--- a/hw/usb/dev-uas.c
245
+++ b/hw/usb/dev-uas.c
246
@@ -XXX,XX +XXX,XX @@ static void usb_uas_realize(USBDevice *dev, Error **errp)
247
uas->status_bh = qemu_bh_new(usb_uas_send_status_bh, uas);
248
249
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
250
- scsi_bus_new(&uas->bus, sizeof(uas->bus), DEVICE(dev),
251
- &usb_uas_scsi_info, NULL);
252
+ scsi_bus_init(&uas->bus, sizeof(uas->bus), DEVICE(dev), &usb_uas_scsi_info);
253
}
254
255
static const VMStateDescription vmstate_usb_uas = {
80
--
256
--
81
2.20.1
257
2.20.1
82
258
83
259
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to
2
line with a "_init for in-place init, _new for allocate-and-return"
3
convention. Drop the 'name' argument, because the only caller does
4
not pass in a name. If a future caller does need to specify the bus
5
name, we should create an ipack_bus_init_named() function at that
6
point.
2
7
3
Convert kvm_arm_vgic_probe() so that it returns a
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
bitmap of supported in-kernel emulation VGIC versions instead
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
of the max version: at the moment values can be v2 and v3.
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
6
This allows to expose the case where the host GICv3 also
11
Message-id: 20210923121153.23754-3-peter.maydell@linaro.org
7
supports GICv2 emulation. This will be useful to choose the
12
---
8
default version in KVM accelerated mode.
13
include/hw/ipack/ipack.h | 8 ++++----
14
hw/ipack/ipack.c | 10 +++++-----
15
hw/ipack/tpci200.c | 4 ++--
16
3 files changed, 11 insertions(+), 11 deletions(-)
9
17
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
18
diff --git a/include/hw/ipack/ipack.h b/include/hw/ipack/ipack.h
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20200311131618.7187-5-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/kvm_arm.h | 3 +++
17
hw/arm/virt.c | 11 +++++++++--
18
target/arm/kvm.c | 14 ++++++++------
19
3 files changed, 20 insertions(+), 8 deletions(-)
20
21
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
22
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/kvm_arm.h
20
--- a/include/hw/ipack/ipack.h
24
+++ b/target/arm/kvm_arm.h
21
+++ b/include/hw/ipack/ipack.h
25
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ipack_device;
26
#include "exec/memory.h"
23
VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice)
27
#include "qemu/error-report.h"
24
28
25
IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot);
29
+#define KVM_ARM_VGIC_V2 (1 << 0)
26
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
30
+#define KVM_ARM_VGIC_V3 (1 << 1)
27
- DeviceState *parent,
31
+
28
- const char *name, uint8_t n_slots,
32
/**
29
- qemu_irq_handler handler);
33
* kvm_arm_vcpu_init:
30
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
34
* @cs: CPUState
31
+ DeviceState *parent,
35
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
32
+ uint8_t n_slots,
33
+ qemu_irq_handler handler);
34
35
#endif
36
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
36
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/virt.c
38
--- a/hw/ipack/ipack.c
38
+++ b/hw/arm/virt.c
39
+++ b/hw/ipack/ipack.c
39
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
40
@@ -XXX,XX +XXX,XX @@ IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot)
40
vms->gic_version = VIRT_GIC_VERSION_3;
41
return NULL;
41
}
42
}
42
} else {
43
43
- vms->gic_version = kvm_arm_vgic_probe();
44
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
44
- if (!vms->gic_version) {
45
- DeviceState *parent,
45
+ int probe_bitmap = kvm_arm_vgic_probe();
46
- const char *name, uint8_t n_slots,
46
+
47
- qemu_irq_handler handler)
47
+ if (!probe_bitmap) {
48
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
48
error_report(
49
+ DeviceState *parent,
49
"Unable to determine GIC version supported by host");
50
+ uint8_t n_slots,
50
exit(1);
51
+ qemu_irq_handler handler)
51
+ } else {
52
{
52
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
53
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, name);
53
+ vms->gic_version = VIRT_GIC_VERSION_3;
54
+ qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
54
+ } else {
55
bus->n_slots = n_slots;
55
+ vms->gic_version = VIRT_GIC_VERSION_2;
56
bus->set_irq = handler;
56
+ }
57
}
57
}
58
diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c
58
}
59
} else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
60
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
61
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/kvm.c
60
--- a/hw/ipack/tpci200.c
63
+++ b/target/arm/kvm.c
61
+++ b/hw/ipack/tpci200.c
64
@@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s)
62
@@ -XXX,XX +XXX,XX @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
65
63
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
66
int kvm_arm_vgic_probe(void)
64
pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
67
{
65
68
+ int val = 0;
66
- ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
69
+
67
- N_MODULES, tpci200_set_irq);
70
if (kvm_create_device(kvm_state,
68
+ ipack_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
71
KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
69
+ N_MODULES, tpci200_set_irq);
72
- return 3;
73
- } else if (kvm_create_device(kvm_state,
74
- KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
75
- return 2;
76
- } else {
77
- return 0;
78
+ val |= KVM_ARM_VGIC_V3;
79
}
80
+ if (kvm_create_device(kvm_state,
81
+ KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
82
+ val |= KVM_ARM_VGIC_V2;
83
+ }
84
+ return val;
85
}
70
}
86
71
87
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level)
72
static const VMStateDescription vmstate_tpci200 = {
88
--
73
--
89
2.20.1
74
2.20.1
90
75
91
76
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
Rename the pci_root_bus_new_inplace() function to
2
pci_root_bus_init(); this brings the bus type in to line with a
3
"_init for in-place init, _new for allocate-and-return" convention.
4
To do this we need to rename the implementation-internal function
5
that was using the pci_root_bus_init() name to
6
pci_root_bus_internal_init().
2
7
3
The Aspeed SMC Controller can operate in different modes : Read, Fast
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Read, Write and User modes. When the User mode is configured, it
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
selects automatically the SPI slave device until the CE_STOP_ACTIVE
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
6
bit is set to 1. When any other modes are configured the device is
11
Message-id: 20210923121153.23754-4-peter.maydell@linaro.org
7
unselected. The HW logic handles the chip select automatically when
12
---
8
the flash is accessed through its AHB window.
13
include/hw/pci/pci.h | 10 +++++-----
14
hw/pci-host/raven.c | 4 ++--
15
hw/pci-host/versatile.c | 6 +++---
16
hw/pci/pci.c | 26 +++++++++++++-------------
17
4 files changed, 23 insertions(+), 23 deletions(-)
9
18
10
When configuring the CEx Control Register, the User mode logic to
19
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
11
select and unselect the slave is incorrect and data corruption can be
12
seen on machines using two chips, witherspoon and romulus.
13
14
Rework the handler setting the CEx Control Register to fix this issue.
15
16
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
18
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
19
Message-id: 20200206112645.21275-3-clg@kaod.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++----------------
23
hw/ssi/trace-events | 1 +
24
2 files changed, 24 insertions(+), 16 deletions(-)
25
26
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
27
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/aspeed_smc.c
21
--- a/include/hw/pci/pci.h
29
+++ b/hw/ssi/aspeed_smc.c
22
+++ b/include/hw/pci/pci.h
30
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
23
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
31
}
24
25
bool pci_bus_is_express(PCIBus *bus);
26
27
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
28
- const char *name,
29
- MemoryRegion *address_space_mem,
30
- MemoryRegion *address_space_io,
31
- uint8_t devfn_min, const char *typename);
32
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
33
+ const char *name,
34
+ MemoryRegion *address_space_mem,
35
+ MemoryRegion *address_space_io,
36
+ uint8_t devfn_min, const char *typename);
37
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
38
MemoryRegion *address_space_mem,
39
MemoryRegion *address_space_io,
40
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/pci-host/raven.c
43
+++ b/hw/pci-host/raven.c
44
@@ -XXX,XX +XXX,XX @@ static void raven_pcihost_initfn(Object *obj)
45
memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
46
&s->pci_io_non_contiguous, 1);
47
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
48
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
49
- &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
50
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
51
+ &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
52
53
/* Bus master address space */
54
memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
55
diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/pci-host/versatile.c
58
+++ b/hw/pci-host/versatile.c
59
@@ -XXX,XX +XXX,XX @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
60
memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB);
61
memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB);
62
63
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
64
- &s->pci_mem_space, &s->pci_io_space,
65
- PCI_DEVFN(11, 0), TYPE_PCI_BUS);
66
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
67
+ &s->pci_mem_space, &s->pci_io_space,
68
+ PCI_DEVFN(11, 0), TYPE_PCI_BUS);
69
h->bus = &s->pci_bus;
70
71
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
72
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/pci/pci.c
75
+++ b/hw/pci/pci.c
76
@@ -XXX,XX +XXX,XX @@ bool pci_bus_bypass_iommu(PCIBus *bus)
77
return host_bridge->bypass_iommu;
32
}
78
}
33
79
34
-static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
80
-static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
35
+static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
81
- MemoryRegion *address_space_mem,
82
- MemoryRegion *address_space_io,
83
- uint8_t devfn_min)
84
+static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent,
85
+ MemoryRegion *address_space_mem,
86
+ MemoryRegion *address_space_io,
87
+ uint8_t devfn_min)
36
{
88
{
37
- const AspeedSMCState *s = fl->controller;
89
assert(PCI_FUNC(devfn_min) == 0);
38
+ AspeedSMCState *s = fl->controller;
90
bus->devfn_min = devfn_min;
39
91
@@ -XXX,XX +XXX,XX @@ bool pci_bus_is_express(PCIBus *bus)
40
- return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
92
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
41
+ trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
42
+
43
+ qemu_set_irq(s->cs_lines[fl->id], unselect);
44
}
93
}
45
94
46
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
95
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
96
- const char *name,
97
- MemoryRegion *address_space_mem,
98
- MemoryRegion *address_space_io,
99
- uint8_t devfn_min, const char *typename)
100
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
101
+ const char *name,
102
+ MemoryRegion *address_space_mem,
103
+ MemoryRegion *address_space_io,
104
+ uint8_t devfn_min, const char *typename)
47
{
105
{
48
- AspeedSMCState *s = fl->controller;
106
qbus_create_inplace(bus, bus_size, typename, parent, name);
49
-
107
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
50
- s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
108
- devfn_min);
51
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
109
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
52
+ aspeed_smc_flash_do_select(fl, false);
110
+ address_space_io, devfn_min);
53
}
111
}
54
112
55
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
113
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
56
{
114
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
57
- AspeedSMCState *s = fl->controller;
115
PCIBus *bus;
58
-
116
59
- s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
117
bus = PCI_BUS(qbus_create(typename, parent, name));
60
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
118
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
61
+ aspeed_smc_flash_do_select(fl, true);
119
- devfn_min);
120
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
121
+ address_space_io, devfn_min);
122
return bus;
62
}
123
}
63
124
64
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
65
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = {
66
},
67
};
68
69
-static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
70
+static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
71
{
72
AspeedSMCState *s = fl->controller;
73
+ bool unselect;
74
75
- s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START;
76
+ /* User mode selects the CS, other modes unselect */
77
+ unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
78
79
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
80
+ /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
81
+ if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
82
+ value & CTRL_CE_STOP_ACTIVE) {
83
+ unselect = true;
84
+ }
85
+
86
+ s->regs[s->r_ctrl0 + fl->id] = value;
87
+
88
+ s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
89
+
90
+ aspeed_smc_flash_do_select(fl, unselect);
91
}
92
93
static void aspeed_smc_reset(DeviceState *d)
94
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
95
s->regs[addr] = value;
96
} else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
97
int cs = addr - s->r_ctrl0;
98
- s->regs[addr] = value;
99
- aspeed_smc_flash_update_cs(&s->flashes[cs]);
100
+ aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
101
} else if (addr >= R_SEG_ADDR0 &&
102
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
103
int cs = addr - R_SEG_ADDR0;
104
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/ssi/trace-events
107
+++ b/hw/ssi/trace-events
108
@@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int
109
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
110
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
111
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
112
+aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
113
--
125
--
114
2.20.1
126
2.20.1
115
127
116
128
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
Rename qbus_create_inplace() to qbus_init(); this is more in line
2
with our usual naming convention for functions that in-place
3
initialize objects.
2
4
3
Restructure the finalize_gic_version with switch cases and
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
clearly separate the following cases:
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
8
Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
9
---
10
include/hw/qdev-core.h | 4 ++--
11
hw/audio/intel-hda.c | 2 +-
12
hw/block/fdc.c | 2 +-
13
hw/block/swim.c | 3 +--
14
hw/char/virtio-serial-bus.c | 4 ++--
15
hw/core/bus.c | 11 ++++++-----
16
hw/core/sysbus.c | 10 ++++++----
17
hw/gpio/bcm2835_gpio.c | 3 +--
18
hw/ide/qdev.c | 2 +-
19
hw/ipack/ipack.c | 2 +-
20
hw/misc/mac_via.c | 4 ++--
21
hw/misc/macio/cuda.c | 4 ++--
22
hw/misc/macio/macio.c | 4 ++--
23
hw/misc/macio/pmu.c | 4 ++--
24
hw/nubus/nubus-bridge.c | 2 +-
25
hw/nvme/ctrl.c | 4 ++--
26
hw/nvme/subsys.c | 3 +--
27
hw/pci/pci.c | 2 +-
28
hw/pci/pci_bridge.c | 4 ++--
29
hw/s390x/event-facility.c | 4 ++--
30
hw/s390x/virtio-ccw.c | 3 +--
31
hw/scsi/scsi-bus.c | 2 +-
32
hw/sd/allwinner-sdhost.c | 4 ++--
33
hw/sd/bcm2835_sdhost.c | 4 ++--
34
hw/sd/pl181.c | 3 +--
35
hw/sd/pxa2xx_mmci.c | 4 ++--
36
hw/sd/sdhci.c | 3 +--
37
hw/sd/ssi-sd.c | 3 +--
38
hw/usb/bus.c | 2 +-
39
hw/usb/dev-smartcard-reader.c | 3 +--
40
hw/virtio/virtio-mmio.c | 3 +--
41
hw/virtio/virtio-pci.c | 3 +--
42
32 files changed, 54 insertions(+), 61 deletions(-)
5
43
6
- KVM mode / in-kernel irqchip
44
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
7
- KVM mode / userspace irqchip
45
index XXXXXXX..XXXXXXX 100644
8
- TCG mode
46
--- a/include/hw/qdev-core.h
9
47
+++ b/include/hw/qdev-core.h
10
In KVM mode / in-kernel irqchip , we explictly check whether
48
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_find_recursive(BusState *bus, const char *id);
11
the chosen version is supported by the host. If the end-user
49
typedef int (qbus_walkerfn)(BusState *bus, void *opaque);
12
explicitly sets v2/v3 and this is not supported by the host,
50
typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
13
then the user gets an explicit error message. Note that for
51
14
old kernels where the CREATE_DEVICE ioctl doesn't exist then
52
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
15
we will now fail if the user specifically asked for gicv2,
53
- DeviceState *parent, const char *name);
16
where previously we (probably) would have succeeded.
54
+void qbus_init(void *bus, size_t size, const char *typename,
17
55
+ DeviceState *parent, const char *name);
18
In KVM mode / userspace irqchip we immediatly output an error
56
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
19
in case the end-user explicitly selected v3. Also we warn the
57
bool qbus_realize(BusState *bus, Error **errp);
20
end-user about the unexpected usage of gic-version=host in
58
void qbus_unrealize(BusState *bus);
21
that case as only userspace GICv2 is supported.
59
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
22
60
index XXXXXXX..XXXXXXX 100644
23
Signed-off-by: Eric Auger <eric.auger@redhat.com>
61
--- a/hw/audio/intel-hda.c
24
Reviewed-by: Andrew Jones <drjones@redhat.com>
62
+++ b/hw/audio/intel-hda.c
25
Message-id: 20200311131618.7187-6-eric.auger@redhat.com
63
@@ -XXX,XX +XXX,XX @@ void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
64
hda_codec_response_func response,
27
---
65
hda_codec_xfer_func xfer)
28
hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------
66
{
29
1 file changed, 67 insertions(+), 21 deletions(-)
67
- qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
30
68
+ qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
31
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
69
bus->response = response;
32
index XXXXXXX..XXXXXXX 100644
70
bus->xfer = xfer;
33
--- a/hw/arm/virt.c
71
}
34
+++ b/hw/arm/virt.c
72
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
35
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
73
index XXXXXXX..XXXXXXX 100644
36
*/
74
--- a/hw/block/fdc.c
37
static void finalize_gic_version(VirtMachineState *vms)
75
+++ b/hw/block/fdc.c
38
{
76
@@ -XXX,XX +XXX,XX @@ static const TypeInfo floppy_bus_info = {
39
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
77
40
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
78
static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
41
- if (!kvm_enabled()) {
79
{
42
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
80
- qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
43
- error_report("gic-version=host requires KVM");
81
+ qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
44
- exit(1);
82
bus->fdc = fdc;
45
- } else {
83
}
46
- /* "max": currently means 3 for TCG */
84
47
- vms->gic_version = VIRT_GIC_VERSION_3;
85
diff --git a/hw/block/swim.c b/hw/block/swim.c
48
- }
86
index XXXXXXX..XXXXXXX 100644
49
- } else {
87
--- a/hw/block/swim.c
50
- int probe_bitmap = kvm_arm_vgic_probe();
88
+++ b/hw/block/swim.c
51
+ if (kvm_enabled()) {
89
@@ -XXX,XX +XXX,XX @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp)
52
+ int probe_bitmap;
90
Swim *sys = SWIM(dev);
53
91
SWIMCtrl *swimctrl = &sys->ctrl;
54
- if (!probe_bitmap) {
92
55
+ if (!kvm_irqchip_in_kernel()) {
93
- qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
56
+ switch (vms->gic_version) {
94
- NULL);
57
+ case VIRT_GIC_VERSION_HOST:
95
+ qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL);
58
+ warn_report(
96
swimctrl->bus.ctrl = swimctrl;
59
+ "gic-version=host not relevant with kernel-irqchip=off "
97
}
60
+ "as only userspace GICv2 is supported. Using v2 ...");
98
61
+ return;
99
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
62
+ case VIRT_GIC_VERSION_MAX:
100
index XXXXXXX..XXXXXXX 100644
63
+ case VIRT_GIC_VERSION_NOSEL:
101
--- a/hw/char/virtio-serial-bus.c
64
+ vms->gic_version = VIRT_GIC_VERSION_2;
102
+++ b/hw/char/virtio-serial-bus.c
65
+ return;
103
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp)
66
+ case VIRT_GIC_VERSION_2:
104
config_size);
67
+ return;
105
68
+ case VIRT_GIC_VERSION_3:
106
/* Spawn a new virtio-serial bus on which the ports will ride as devices */
69
error_report(
107
- qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
70
- "Unable to determine GIC version supported by host");
108
- dev, vdev->bus_name);
71
+ "gic-version=3 is not supported with kernel-irqchip=off");
109
+ qbus_init(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
72
exit(1);
110
+ dev, vdev->bus_name);
73
- } else {
111
qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser));
74
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
112
vser->bus.vser = vser;
75
- vms->gic_version = VIRT_GIC_VERSION_3;
113
QTAILQ_INIT(&vser->ports);
76
- } else {
114
diff --git a/hw/core/bus.c b/hw/core/bus.c
77
- vms->gic_version = VIRT_GIC_VERSION_2;
115
index XXXXXXX..XXXXXXX 100644
78
- }
116
--- a/hw/core/bus.c
79
}
117
+++ b/hw/core/bus.c
80
}
118
@@ -XXX,XX +XXX,XX @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
81
- } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
82
+
83
+ probe_bitmap = kvm_arm_vgic_probe();
84
+ if (!probe_bitmap) {
85
+ error_report("Unable to determine GIC version supported by host");
86
+ exit(1);
87
+ }
88
+
89
+ switch (vms->gic_version) {
90
+ case VIRT_GIC_VERSION_HOST:
91
+ case VIRT_GIC_VERSION_MAX:
92
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
93
+ vms->gic_version = VIRT_GIC_VERSION_3;
94
+ } else {
95
+ vms->gic_version = VIRT_GIC_VERSION_2;
96
+ }
97
+ return;
98
+ case VIRT_GIC_VERSION_NOSEL:
99
+ vms->gic_version = VIRT_GIC_VERSION_2;
100
+ break;
101
+ case VIRT_GIC_VERSION_2:
102
+ case VIRT_GIC_VERSION_3:
103
+ break;
104
+ }
105
+
106
+ /* Check chosen version is effectively supported by the host */
107
+ if (vms->gic_version == VIRT_GIC_VERSION_2 &&
108
+ !(probe_bitmap & KVM_ARM_VGIC_V2)) {
109
+ error_report("host does not support in-kernel GICv2 emulation");
110
+ exit(1);
111
+ } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
112
+ !(probe_bitmap & KVM_ARM_VGIC_V3)) {
113
+ error_report("host does not support in-kernel GICv3 emulation");
114
+ exit(1);
115
+ }
116
+ return;
117
+ }
118
+
119
+ /* TCG mode */
120
+ switch (vms->gic_version) {
121
+ case VIRT_GIC_VERSION_NOSEL:
122
vms->gic_version = VIRT_GIC_VERSION_2;
123
+ break;
124
+ case VIRT_GIC_VERSION_MAX:
125
+ vms->gic_version = VIRT_GIC_VERSION_3;
126
+ break;
127
+ case VIRT_GIC_VERSION_HOST:
128
+ error_report("gic-version=host requires KVM");
129
+ exit(1);
130
+ case VIRT_GIC_VERSION_2:
131
+ case VIRT_GIC_VERSION_3:
132
+ break;
133
}
119
}
134
}
120
}
135
121
122
-static void qbus_init(BusState *bus, DeviceState *parent, const char *name)
123
+static void qbus_init_internal(BusState *bus, DeviceState *parent,
124
+ const char *name)
125
{
126
const char *typename = object_get_typename(OBJECT(bus));
127
BusClass *bc;
128
@@ -XXX,XX +XXX,XX @@ static void bus_unparent(Object *obj)
129
bus->parent = NULL;
130
}
131
132
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
133
- DeviceState *parent, const char *name)
134
+void qbus_init(void *bus, size_t size, const char *typename,
135
+ DeviceState *parent, const char *name)
136
{
137
object_initialize(bus, size, typename);
138
- qbus_init(bus, parent, name);
139
+ qbus_init_internal(bus, parent, name);
140
}
141
142
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
143
@@ -XXX,XX +XXX,XX @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam
144
BusState *bus;
145
146
bus = BUS(object_new(typename));
147
- qbus_init(bus, parent, name);
148
+ qbus_init_internal(bus, parent, name);
149
150
return bus;
151
}
152
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/hw/core/sysbus.c
155
+++ b/hw/core/sysbus.c
156
@@ -XXX,XX +XXX,XX @@ static BusState *main_system_bus;
157
158
static void main_system_bus_create(void)
159
{
160
- /* assign main_system_bus before qbus_create_inplace()
161
- * in order to make "if (bus != sysbus_get_default())" work */
162
+ /*
163
+ * assign main_system_bus before qbus_init()
164
+ * in order to make "if (bus != sysbus_get_default())" work
165
+ */
166
main_system_bus = g_malloc0(system_bus_info.instance_size);
167
- qbus_create_inplace(main_system_bus, system_bus_info.instance_size,
168
- TYPE_SYSTEM_BUS, NULL, "main-system-bus");
169
+ qbus_init(main_system_bus, system_bus_info.instance_size,
170
+ TYPE_SYSTEM_BUS, NULL, "main-system-bus");
171
OBJECT(main_system_bus)->free = g_free;
172
}
173
174
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
175
index XXXXXXX..XXXXXXX 100644
176
--- a/hw/gpio/bcm2835_gpio.c
177
+++ b/hw/gpio/bcm2835_gpio.c
178
@@ -XXX,XX +XXX,XX @@ static void bcm2835_gpio_init(Object *obj)
179
DeviceState *dev = DEVICE(obj);
180
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
181
182
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
183
- TYPE_SD_BUS, DEVICE(s), "sd-bus");
184
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(s), "sd-bus");
185
186
memory_region_init_io(&s->iomem, obj,
187
&bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
188
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
189
index XXXXXXX..XXXXXXX 100644
190
--- a/hw/ide/qdev.c
191
+++ b/hw/ide/qdev.c
192
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
193
void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
194
int bus_id, int max_units)
195
{
196
- qbus_create_inplace(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
197
+ qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
198
idebus->bus_id = bus_id;
199
idebus->max_units = max_units;
200
}
201
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/hw/ipack/ipack.c
204
+++ b/hw/ipack/ipack.c
205
@@ -XXX,XX +XXX,XX @@ void ipack_bus_init(IPackBus *bus, size_t bus_size,
206
uint8_t n_slots,
207
qemu_irq_handler handler)
208
{
209
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
210
+ qbus_init(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
211
bus->n_slots = n_slots;
212
bus->set_irq = handler;
213
}
214
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/misc/mac_via.c
217
+++ b/hw/misc/mac_via.c
218
@@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_init(Object *obj)
219
sysbus_init_mmio(sbd, &v1s->via_mem);
220
221
/* ADB */
222
- qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
223
- TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
224
+ qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
225
+ TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
226
227
qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB);
228
}
229
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
230
index XXXXXXX..XXXXXXX 100644
231
--- a/hw/misc/macio/cuda.c
232
+++ b/hw/misc/macio/cuda.c
233
@@ -XXX,XX +XXX,XX @@ static void cuda_init(Object *obj)
234
memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000);
235
sysbus_init_mmio(sbd, &s->mem);
236
237
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
238
- DEVICE(obj), "adb.0");
239
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
240
+ DEVICE(obj), "adb.0");
241
}
242
243
static Property cuda_properties[] = {
244
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/hw/misc/macio/macio.c
247
+++ b/hw/misc/macio/macio.c
248
@@ -XXX,XX +XXX,XX @@ static void macio_instance_init(Object *obj)
249
250
memory_region_init(&s->bar, obj, "macio", 0x80000);
251
252
- qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
253
- DEVICE(obj), "macio.0");
254
+ qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
255
+ DEVICE(obj), "macio.0");
256
257
object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
258
259
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
260
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/misc/macio/pmu.c
262
+++ b/hw/misc/macio/pmu.c
263
@@ -XXX,XX +XXX,XX @@ static void pmu_realize(DeviceState *dev, Error **errp)
264
timer_mod(s->one_sec_timer, s->one_sec_target);
265
266
if (s->has_adb) {
267
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
268
- dev, "adb.0");
269
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
270
+ dev, "adb.0");
271
adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s);
272
}
273
}
274
diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
275
index XXXXXXX..XXXXXXX 100644
276
--- a/hw/nubus/nubus-bridge.c
277
+++ b/hw/nubus/nubus-bridge.c
278
@@ -XXX,XX +XXX,XX @@ static void nubus_bridge_init(Object *obj)
279
NubusBridge *s = NUBUS_BRIDGE(obj);
280
NubusBus *bus = &s->bus;
281
282
- qbus_create_inplace(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
283
+ qbus_init(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
284
285
qdev_init_gpio_out(DEVICE(s), bus->irqs, NUBUS_IRQS);
286
}
287
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/nvme/ctrl.c
290
+++ b/hw/nvme/ctrl.c
291
@@ -XXX,XX +XXX,XX @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
292
return;
293
}
294
295
- qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
296
- &pci_dev->qdev, n->parent_obj.qdev.id);
297
+ qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
298
+ &pci_dev->qdev, n->parent_obj.qdev.id);
299
300
nvme_init_state(n);
301
if (nvme_init_pci(n, pci_dev, errp)) {
302
diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c
303
index XXXXXXX..XXXXXXX 100644
304
--- a/hw/nvme/subsys.c
305
+++ b/hw/nvme/subsys.c
306
@@ -XXX,XX +XXX,XX @@ static void nvme_subsys_realize(DeviceState *dev, Error **errp)
307
{
308
NvmeSubsystem *subsys = NVME_SUBSYS(dev);
309
310
- qbus_create_inplace(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev,
311
- dev->id);
312
+ qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id);
313
314
nvme_subsys_setup(subsys);
315
}
316
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
317
index XXXXXXX..XXXXXXX 100644
318
--- a/hw/pci/pci.c
319
+++ b/hw/pci/pci.c
320
@@ -XXX,XX +XXX,XX @@ void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
321
MemoryRegion *address_space_io,
322
uint8_t devfn_min, const char *typename)
323
{
324
- qbus_create_inplace(bus, bus_size, typename, parent, name);
325
+ qbus_init(bus, bus_size, typename, parent, name);
326
pci_root_bus_internal_init(bus, parent, address_space_mem,
327
address_space_io, devfn_min);
328
}
329
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
330
index XXXXXXX..XXXXXXX 100644
331
--- a/hw/pci/pci_bridge.c
332
+++ b/hw/pci/pci_bridge.c
333
@@ -XXX,XX +XXX,XX @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
334
br->bus_name = dev->qdev.id;
335
}
336
337
- qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
338
- br->bus_name);
339
+ qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
340
+ br->bus_name);
341
sec_bus->parent_dev = dev;
342
sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
343
sec_bus->address_space_mem = &br->address_space_mem;
344
diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/hw/s390x/event-facility.c
347
+++ b/hw/s390x/event-facility.c
348
@@ -XXX,XX +XXX,XX @@ static void init_event_facility(Object *obj)
349
sclp_event_set_allow_all_mask_sizes);
350
351
/* Spawn a new bus for SCLP events */
352
- qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus),
353
- TYPE_SCLP_EVENTS_BUS, sdev, NULL);
354
+ qbus_init(&event_facility->sbus, sizeof(event_facility->sbus),
355
+ TYPE_SCLP_EVENTS_BUS, sdev, NULL);
356
357
object_initialize_child(obj, TYPE_SCLP_QUIESCE,
358
&event_facility->quiesce,
359
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
360
index XXXXXXX..XXXXXXX 100644
361
--- a/hw/s390x/virtio-ccw.c
362
+++ b/hw/s390x/virtio-ccw.c
363
@@ -XXX,XX +XXX,XX @@ static void virtio_ccw_bus_new(VirtioBusState *bus, size_t bus_size,
364
DeviceState *qdev = DEVICE(dev);
365
char virtio_bus_name[] = "virtio-bus";
366
367
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_CCW_BUS,
368
- qdev, virtio_bus_name);
369
+ qbus_init(bus, bus_size, TYPE_VIRTIO_CCW_BUS, qdev, virtio_bus_name);
370
}
371
372
static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data)
373
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
374
index XXXXXXX..XXXXXXX 100644
375
--- a/hw/scsi/scsi-bus.c
376
+++ b/hw/scsi/scsi-bus.c
377
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
378
void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
379
const SCSIBusInfo *info, const char *bus_name)
380
{
381
- qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
382
+ qbus_init(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
383
bus->busnr = next_scsi_bus++;
384
bus->info = info;
385
qbus_set_bus_hotplug_handler(BUS(bus));
386
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/hw/sd/allwinner-sdhost.c
389
+++ b/hw/sd/allwinner-sdhost.c
390
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
391
{
392
AwSdHostState *s = AW_SDHOST(obj);
393
394
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
395
- TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
396
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
397
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
398
399
memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
400
TYPE_AW_SDHOST, 4 * KiB);
401
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
402
index XXXXXXX..XXXXXXX 100644
403
--- a/hw/sd/bcm2835_sdhost.c
404
+++ b/hw/sd/bcm2835_sdhost.c
405
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_init(Object *obj)
406
{
407
BCM2835SDHostState *s = BCM2835_SDHOST(obj);
408
409
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
410
- TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
411
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
412
+ TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
413
414
memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
415
TYPE_BCM2835_SDHOST, 0x1000);
416
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/sd/pl181.c
419
+++ b/hw/sd/pl181.c
420
@@ -XXX,XX +XXX,XX @@ static void pl181_init(Object *obj)
421
qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1);
422
qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1);
423
424
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
425
- TYPE_PL181_BUS, dev, "sd-bus");
426
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_PL181_BUS, dev, "sd-bus");
427
}
428
429
static void pl181_class_init(ObjectClass *klass, void *data)
430
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
431
index XXXXXXX..XXXXXXX 100644
432
--- a/hw/sd/pxa2xx_mmci.c
433
+++ b/hw/sd/pxa2xx_mmci.c
434
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mmci_instance_init(Object *obj)
435
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
436
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
437
438
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
439
- TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
440
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
441
+ TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
442
}
443
444
static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
445
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
446
index XXXXXXX..XXXXXXX 100644
447
--- a/hw/sd/sdhci.c
448
+++ b/hw/sd/sdhci.c
449
@@ -XXX,XX +XXX,XX @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
450
451
void sdhci_initfn(SDHCIState *s)
452
{
453
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
454
- TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
455
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
456
457
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
458
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
459
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
460
index XXXXXXX..XXXXXXX 100644
461
--- a/hw/sd/ssi-sd.c
462
+++ b/hw/sd/ssi-sd.c
463
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSIPeripheral *d, Error **errp)
464
DeviceState *carddev;
465
DriveInfo *dinfo;
466
467
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
468
- DEVICE(d), "sd-bus");
469
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus");
470
471
/* Create and plug in the sd card */
472
/* FIXME use a qdev drive property instead of drive_get_next() */
473
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
474
index XXXXXXX..XXXXXXX 100644
475
--- a/hw/usb/bus.c
476
+++ b/hw/usb/bus.c
477
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_usb_device = {
478
void usb_bus_new(USBBus *bus, size_t bus_size,
479
USBBusOps *ops, DeviceState *host)
480
{
481
- qbus_create_inplace(bus, bus_size, TYPE_USB_BUS, host, NULL);
482
+ qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL);
483
qbus_set_bus_hotplug_handler(BUS(bus));
484
bus->ops = ops;
485
bus->busnr = next_usb_bus++;
486
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/usb/dev-smartcard-reader.c
489
+++ b/hw/usb/dev-smartcard-reader.c
490
@@ -XXX,XX +XXX,XX @@ static void ccid_realize(USBDevice *dev, Error **errp)
491
492
usb_desc_create_serial(dev);
493
usb_desc_init(dev);
494
- qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev),
495
- NULL);
496
+ qbus_init(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), NULL);
497
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
498
s->intr = usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP);
499
s->bulk = usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP);
500
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/virtio/virtio-mmio.c
503
+++ b/hw/virtio/virtio-mmio.c
504
@@ -XXX,XX +XXX,XX @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp)
505
VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d);
506
SysBusDevice *sbd = SYS_BUS_DEVICE(d);
507
508
- qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS,
509
- d, NULL);
510
+ qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL);
511
sysbus_init_irq(sbd, &proxy->irq);
512
513
if (!kvm_eventfds_enabled()) {
514
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
515
index XXXXXXX..XXXXXXX 100644
516
--- a/hw/virtio/virtio-pci.c
517
+++ b/hw/virtio/virtio-pci.c
518
@@ -XXX,XX +XXX,XX @@ static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
519
DeviceState *qdev = DEVICE(dev);
520
char virtio_bus_name[] = "virtio-bus";
521
522
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
523
- virtio_bus_name);
524
+ qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name);
525
}
526
527
static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
136
--
528
--
137
2.20.1
529
2.20.1
138
530
139
531
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
Rename the "allocate and return" qbus creation function to
2
2
qbus_new(), to bring it into line with our _init vs _new convention.
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
3
4
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20200206112645.21275-2-clg@kaod.org
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
8
Message-id: 20210923121153.23754-6-peter.maydell@linaro.org
9
---
9
---
10
Makefile.objs | 1 +
10
include/hw/qdev-core.h | 2 +-
11
hw/ssi/aspeed_smc.c | 17 +++++++++++++++++
11
hw/core/bus.c | 2 +-
12
hw/ssi/trace-events | 9 +++++++++
12
hw/hyperv/vmbus.c | 2 +-
13
3 files changed, 27 insertions(+)
13
hw/i2c/core.c | 2 +-
14
create mode 100644 hw/ssi/trace-events
14
hw/isa/isa-bus.c | 2 +-
15
15
hw/misc/auxbus.c | 2 +-
16
diff --git a/Makefile.objs b/Makefile.objs
16
hw/pci/pci.c | 2 +-
17
index XXXXXXX..XXXXXXX 100644
17
hw/ppc/spapr_vio.c | 2 +-
18
--- a/Makefile.objs
18
hw/s390x/ap-bridge.c | 2 +-
19
+++ b/Makefile.objs
19
hw/s390x/css-bridge.c | 2 +-
20
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi
20
hw/s390x/s390-pci-bus.c | 2 +-
21
trace-events-subdirs += hw/sd
21
hw/ssi/ssi.c | 2 +-
22
trace-events-subdirs += hw/sparc
22
hw/xen/xen-bus.c | 2 +-
23
trace-events-subdirs += hw/sparc64
23
hw/xen/xen-legacy-backend.c | 2 +-
24
+trace-events-subdirs += hw/ssi
24
14 files changed, 14 insertions(+), 14 deletions(-)
25
trace-events-subdirs += hw/timer
25
26
trace-events-subdirs += hw/tpm
26
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
27
trace-events-subdirs += hw/usb
27
index XXXXXXX..XXXXXXX 100644
28
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
28
--- a/include/hw/qdev-core.h
29
index XXXXXXX..XXXXXXX 100644
29
+++ b/include/hw/qdev-core.h
30
--- a/hw/ssi/aspeed_smc.c
30
@@ -XXX,XX +XXX,XX @@ typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
31
+++ b/hw/ssi/aspeed_smc.c
31
32
@@ -XXX,XX +XXX,XX @@
32
void qbus_init(void *bus, size_t size, const char *typename,
33
#include "qapi/error.h"
33
DeviceState *parent, const char *name);
34
#include "exec/address-spaces.h"
34
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
35
#include "qemu/units.h"
35
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name);
36
+#include "trace.h"
36
bool qbus_realize(BusState *bus, Error **errp);
37
37
void qbus_unrealize(BusState *bus);
38
#include "hw/irq.h"
38
39
#include "hw/qdev-properties.h"
39
diff --git a/hw/core/bus.c b/hw/core/bus.c
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
40
index XXXXXXX..XXXXXXX 100644
41
41
--- a/hw/core/bus.c
42
s->ctrl->reg_to_segment(s, new, &seg);
42
+++ b/hw/core/bus.c
43
43
@@ -XXX,XX +XXX,XX @@ void qbus_init(void *bus, size_t size, const char *typename,
44
+ trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
44
qbus_init_internal(bus, parent, name);
45
+
45
}
46
/* The start address of CS0 is read-only */
46
47
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
47
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
48
qemu_log_mask(LOG_GUEST_ERROR,
48
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name)
49
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
49
{
50
__func__, aspeed_smc_flash_mode(fl));
50
BusState *bus;
51
52
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/hyperv/vmbus.c
55
+++ b/hw/hyperv/vmbus.c
56
@@ -XXX,XX +XXX,XX @@ static void vmbus_bridge_realize(DeviceState *dev, Error **errp)
57
return;
51
}
58
}
52
59
53
+ trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
60
- bridge->bus = VMBUS(qbus_create(TYPE_VMBUS, dev, "vmbus"));
54
+ aspeed_smc_flash_mode(fl));
61
+ bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus"));
55
return ret;
56
}
62
}
57
63
58
@@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
64
static char *vmbus_bridge_ofw_unit_address(const SysBusDevice *dev)
59
AspeedSMCState *s = fl->controller;
65
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
60
uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
66
index XXXXXXX..XXXXXXX 100644
61
67
--- a/hw/i2c/core.c
62
+ trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
68
+++ b/hw/i2c/core.c
63
+ (uint8_t) data & 0xff);
69
@@ -XXX,XX +XXX,XX @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
64
+
70
{
65
if (s->snoop_index == SNOOP_OFF) {
71
I2CBus *bus;
66
return false; /* Do nothing */
72
67
73
- bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
68
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
74
+ bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
69
AspeedSMCState *s = fl->controller;
75
QLIST_INIT(&bus->current_devs);
70
int i;
76
vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
71
77
return bus;
72
+ trace_aspeed_smc_flash_write(fl->id, addr, size, data,
78
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
73
+ aspeed_smc_flash_mode(fl));
79
index XXXXXXX..XXXXXXX 100644
74
+
80
--- a/hw/isa/isa-bus.c
75
if (!aspeed_smc_is_writable(fl)) {
81
+++ b/hw/isa/isa-bus.c
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
82
@@ -XXX,XX +XXX,XX @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
77
HWADDR_PRIx "\n", __func__, addr);
83
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
78
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
84
}
79
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
85
80
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
86
- isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
81
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
87
+ isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL));
82
+
88
isabus->address_space = address_space;
83
+ trace_aspeed_smc_read(addr, size, s->regs[addr]);
89
isabus->address_space_io = address_space_io;
84
+
90
return isabus;
85
return s->regs[addr];
91
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
86
} else {
92
index XXXXXXX..XXXXXXX 100644
87
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
93
--- a/hw/misc/auxbus.c
88
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
94
+++ b/hw/misc/auxbus.c
89
__func__, s->regs[R_DMA_FLASH_ADDR]);
95
@@ -XXX,XX +XXX,XX @@ AUXBus *aux_bus_init(DeviceState *parent, const char *name)
90
return;
96
AUXBus *bus;
91
}
97
Object *auxtoi2c;
92
+ trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
98
93
99
- bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
94
/*
100
+ bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name));
95
* When the DMA is on-going, the DMA registers are updated
101
auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
96
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
102
&error_abort, NULL);
97
103
98
addr >>= 2;
104
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
99
105
index XXXXXXX..XXXXXXX 100644
100
+ trace_aspeed_smc_write(addr, size, data);
106
--- a/hw/pci/pci.c
101
+
107
+++ b/hw/pci/pci.c
102
if (addr == s->r_conf ||
108
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
103
(addr >= s->r_timings &&
109
{
104
addr < s->r_timings + s->ctrl->nregs_timings) ||
110
PCIBus *bus;
105
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
111
106
new file mode 100644
112
- bus = PCI_BUS(qbus_create(typename, parent, name));
107
index XXXXXXX..XXXXXXX
113
+ bus = PCI_BUS(qbus_new(typename, parent, name));
108
--- /dev/null
114
pci_root_bus_internal_init(bus, parent, address_space_mem,
109
+++ b/hw/ssi/trace-events
115
address_space_io, devfn_min);
110
@@ -XXX,XX +XXX,XX @@
116
return bus;
111
+# aspeed_smc.c
117
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
112
+
118
index XXXXXXX..XXXXXXX 100644
113
+aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
119
--- a/hw/ppc/spapr_vio.c
114
+aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
120
+++ b/hw/ppc/spapr_vio.c
115
+aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
121
@@ -XXX,XX +XXX,XX @@ SpaprVioBus *spapr_vio_bus_init(void)
116
+aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
122
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
117
+aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
123
118
+aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
124
/* Create bus on bridge device */
119
+aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
125
- qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
126
+ qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
127
bus = SPAPR_VIO_BUS(qbus);
128
bus->next_reg = SPAPR_VIO_REG_BASE;
129
130
diff --git a/hw/s390x/ap-bridge.c b/hw/s390x/ap-bridge.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/s390x/ap-bridge.c
133
+++ b/hw/s390x/ap-bridge.c
134
@@ -XXX,XX +XXX,XX @@ void s390_init_ap(void)
135
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
136
137
/* Create bus on bridge device */
138
- bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);
139
+ bus = qbus_new(TYPE_AP_BUS, dev, TYPE_AP_BUS);
140
141
/* Enable hotplugging */
142
qbus_set_hotplug_handler(bus, OBJECT(dev));
143
diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/s390x/css-bridge.c
146
+++ b/hw/s390x/css-bridge.c
147
@@ -XXX,XX +XXX,XX @@ VirtualCssBus *virtual_css_bus_init(void)
148
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
149
150
/* Create bus on bridge device */
151
- bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
152
+ bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
153
cbus = VIRTUAL_CSS_BUS(bus);
154
155
/* Enable hotplugging */
156
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/hw/s390x/s390-pci-bus.c
159
+++ b/hw/s390x/s390-pci-bus.c
160
@@ -XXX,XX +XXX,XX @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp)
161
qbus_set_hotplug_handler(bus, OBJECT(dev));
162
phb->bus = b;
163
164
- s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL));
165
+ s->bus = S390_PCI_BUS(qbus_new(TYPE_S390_PCI_BUS, dev, NULL));
166
qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev));
167
168
s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal,
169
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/hw/ssi/ssi.c
172
+++ b/hw/ssi/ssi.c
173
@@ -XXX,XX +XXX,XX @@ DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name)
174
SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
175
{
176
BusState *bus;
177
- bus = qbus_create(TYPE_SSI_BUS, parent, name);
178
+ bus = qbus_new(TYPE_SSI_BUS, parent, name);
179
return SSI_BUS(bus);
180
}
181
182
diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/hw/xen/xen-bus.c
185
+++ b/hw/xen/xen-bus.c
186
@@ -XXX,XX +XXX,XX @@ type_init(xen_register_types)
187
void xen_bus_init(void)
188
{
189
DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE);
190
- BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL);
191
+ BusState *bus = qbus_new(TYPE_XEN_BUS, dev, NULL);
192
193
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
194
qbus_set_bus_hotplug_handler(bus);
195
diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c
196
index XXXXXXX..XXXXXXX 100644
197
--- a/hw/xen/xen-legacy-backend.c
198
+++ b/hw/xen/xen-legacy-backend.c
199
@@ -XXX,XX +XXX,XX @@ int xen_be_init(void)
200
201
xen_sysdev = qdev_new(TYPE_XENSYSDEV);
202
sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal);
203
- xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
204
+ xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
205
qbus_set_bus_hotplug_handler(xen_sysbus);
206
207
return 0;
120
--
208
--
121
2.20.1
209
2.20.1
122
210
123
211
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We must include the tag in the FAR_ELx register when raising
4
an addressing exception. Which means that we should not clear
5
out the tag during translation.
6
7
We cannot at present comply with this for user mode, so we
8
retain the clean_data_tbi function for the moment, though it
9
no longer does what it says on the tin for system mode. This
10
function is to be replaced with MTE, so don't worry about the
11
slight misnaming.
12
13
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200308012946.16303-3-richard.henderson@linaro.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/translate-a64.c | 11 +++++++++++
20
1 file changed, 11 insertions(+)
21
22
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-a64.c
25
+++ b/target/arm/translate-a64.c
26
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
27
static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
28
{
29
TCGv_i64 clean = new_tmp_a64(s);
30
+ /*
31
+ * In order to get the correct value in the FAR_ELx register,
32
+ * we must present the memory subsystem with the "dirty" address
33
+ * including the TBI. In system mode we can make this work via
34
+ * the TLB, dropping the TBI during translation. But for user-only
35
+ * mode we don't have that option, and must remove the top byte now.
36
+ */
37
+#ifdef CONFIG_USER_ONLY
38
gen_top_byte_ignore(s, clean, addr, s->tbid);
39
+#else
40
+ tcg_gen_mov_i64(clean, addr);
41
+#endif
42
return clean;
43
}
44
45
--
46
2.20.1
47
48
diff view generated by jsdifflib
Deleted patch
1
From: Igor Mammedov <imammedo@redhat.com>
2
1
3
SOC object returned by object_new() is leaked in current code.
4
Set SOC parent explicitly to board and then unref to SOC object
5
to make sure that refererence returned by object_new() is taken
6
care of.
7
8
The SOC object will be kept alive by its parent (machine) and
9
will be automatically freed when MachineState is destroyed.
10
11
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
12
Reported-by: Andrew Jones <drjones@redhat.com>
13
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Message-id: 20200303091254.22373-1-imammedo@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/arm/cubieboard.c | 3 +++
19
1 file changed, 3 insertions(+)
20
21
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/cubieboard.c
24
+++ b/hw/arm/cubieboard.c
25
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
26
}
27
28
a10 = AW_A10(object_new(TYPE_AW_A10));
29
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),
30
+ &error_abort);
31
+ object_unref(OBJECT(a10));
32
33
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
34
if (err != NULL) {
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
4
provided on the command line to available eSDHC controllers.
5
6
This patch enables booting the imx25-pdk emulation from SD card.
7
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200310215146.19688-2-linux@roeck-us.net
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: made commit subject consistent with other patch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/hw/arm/fsl-imx25.h | 9 +++++++++
15
hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++
16
hw/arm/imx25_pdk.c | 16 ++++++++++++++++
17
3 files changed, 57 insertions(+)
18
19
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/fsl-imx25.h
22
+++ b/include/hw/arm/fsl-imx25.h
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/misc/imx_rngc.h"
25
#include "hw/i2c/imx_i2c.h"
26
#include "hw/gpio/imx_gpio.h"
27
+#include "hw/sd/sdhci.h"
28
#include "exec/memory.h"
29
#include "target/arm/cpu.h"
30
31
@@ -XXX,XX +XXX,XX @@
32
#define FSL_IMX25_NUM_EPITS 2
33
#define FSL_IMX25_NUM_I2CS 3
34
#define FSL_IMX25_NUM_GPIOS 4
35
+#define FSL_IMX25_NUM_ESDHCS 2
36
37
typedef struct FslIMX25State {
38
/*< private >*/
39
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
40
IMXRNGCState rngc;
41
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
42
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
43
+ SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
44
MemoryRegion rom[2];
45
MemoryRegion iram;
46
MemoryRegion iram_alias;
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
#define FSL_IMX25_GPIO3_SIZE 0x4000
49
#define FSL_IMX25_RNGC_ADDR 0x53FB0000
50
#define FSL_IMX25_RNGC_SIZE 0x4000
51
+#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
52
+#define FSL_IMX25_ESDHC1_SIZE 0x4000
53
+#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
54
+#define FSL_IMX25_ESDHC2_SIZE 0x4000
55
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
56
#define FSL_IMX25_GPIO1_SIZE 0x4000
57
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
58
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
59
#define FSL_IMX25_GPIO2_IRQ 51
60
#define FSL_IMX25_GPIO3_IRQ 16
61
#define FSL_IMX25_GPIO4_IRQ 23
62
+#define FSL_IMX25_ESDHC1_IRQ 9
63
+#define FSL_IMX25_ESDHC2_IRQ 8
64
65
#endif /* FSL_IMX25_H */
66
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/fsl-imx25.c
69
+++ b/hw/arm/fsl-imx25.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "hw/qdev-properties.h"
72
#include "chardev/char.h"
73
74
+#define IMX25_ESDHC_CAPABILITIES 0x07e20000
75
+
76
static void fsl_imx25_init(Object *obj)
77
{
78
FslIMX25State *s = FSL_IMX25(obj);
79
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
80
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
81
TYPE_IMX_GPIO);
82
}
83
+
84
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
85
+ sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
86
+ TYPE_IMX_USDHC);
87
+ }
88
}
89
90
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
91
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
92
gpio_table[i].irq));
93
}
94
95
+ /* Initialize all SDHC */
96
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
97
+ static const struct {
98
+ hwaddr addr;
99
+ unsigned int irq;
100
+ } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
101
+ { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
102
+ { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
103
+ };
104
+
105
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
106
+ &err);
107
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
108
+ "capareg", &err);
109
+ object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
110
+ if (err) {
111
+ error_propagate(errp, err);
112
+ return;
113
+ }
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->avic),
117
+ esdhc_table[i].irq));
118
+ }
119
+
120
/* initialize 2 x 16 KB ROM */
121
memory_region_init_rom(&s->rom[0], NULL,
122
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
123
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/imx25_pdk.c
126
+++ b/hw/arm/imx25_pdk.c
127
@@ -XXX,XX +XXX,XX @@
128
#include "qemu/osdep.h"
129
#include "qapi/error.h"
130
#include "cpu.h"
131
+#include "hw/qdev-properties.h"
132
#include "hw/arm/fsl-imx25.h"
133
#include "hw/boards.h"
134
#include "qemu/error-report.h"
135
@@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine)
136
imx25_pdk_binfo.board_id = 1771,
137
imx25_pdk_binfo.nb_cpus = 1;
138
139
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
140
+ BusState *bus;
141
+ DeviceState *carddev;
142
+ DriveInfo *di;
143
+ BlockBackend *blk;
144
+
145
+ di = drive_get_next(IF_SD);
146
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
147
+ bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
148
+ carddev = qdev_create(bus, TYPE_SD_CARD);
149
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
150
+ object_property_set_bool(OBJECT(carddev), true,
151
+ "realized", &error_fatal);
152
+ }
153
+
154
/*
155
* We test explicitly for qtest here as it is not done (yet?) in
156
* arm_load_kernel(). Without this the "make check" command would
157
--
158
2.20.1
159
160
diff view generated by jsdifflib
Deleted patch
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
2
1
3
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
4
based embedded computer with mainline support in both U-Boot
5
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
6
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
7
various other I/O. This commit add support for the Xunlong
8
Orange Pi PC machine.
9
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Acked-by: Igor Mammedov <imammedo@redhat.com>
16
Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/arm/Makefile.objs | 2 +-
20
hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
21
MAINTAINERS | 1 +
22
3 files changed, 94 insertions(+), 1 deletion(-)
23
create mode 100644 hw/arm/orangepi.c
24
25
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/Makefile.objs
28
+++ b/hw/arm/Makefile.objs
29
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
30
obj-$(CONFIG_OMAP) += omap1.o omap2.o
31
obj-$(CONFIG_STRONGARM) += strongarm.o
32
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
33
-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
38
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
39
new file mode 100644
40
index XXXXXXX..XXXXXXX
41
--- /dev/null
42
+++ b/hw/arm/orangepi.c
43
@@ -XXX,XX +XXX,XX @@
44
+/*
45
+ * Orange Pi emulation
46
+ *
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
48
+ *
49
+ * This program is free software: you can redistribute it and/or modify
50
+ * it under the terms of the GNU General Public License as published by
51
+ * the Free Software Foundation, either version 2 of the License, or
52
+ * (at your option) any later version.
53
+ *
54
+ * This program is distributed in the hope that it will be useful,
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57
+ * GNU General Public License for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
62
+
63
+#include "qemu/osdep.h"
64
+#include "qemu/units.h"
65
+#include "exec/address-spaces.h"
66
+#include "qapi/error.h"
67
+#include "cpu.h"
68
+#include "hw/sysbus.h"
69
+#include "hw/boards.h"
70
+#include "hw/qdev-properties.h"
71
+#include "hw/arm/allwinner-h3.h"
72
+#include "sysemu/sysemu.h"
73
+
74
+static struct arm_boot_info orangepi_binfo = {
75
+ .nb_cpus = AW_H3_NUM_CPUS,
76
+};
77
+
78
+static void orangepi_init(MachineState *machine)
79
+{
80
+ AwH3State *h3;
81
+
82
+ /* BIOS is not supported by this board */
83
+ if (bios_name) {
84
+ error_report("BIOS not supported for this machine");
85
+ exit(1);
86
+ }
87
+
88
+ /* This board has fixed size RAM */
89
+ if (machine->ram_size != 1 * GiB) {
90
+ error_report("This machine can only be used with 1GiB of RAM");
91
+ exit(1);
92
+ }
93
+
94
+ /* Only allow Cortex-A7 for this board */
95
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
96
+ error_report("This board can only be used with cortex-a7 CPU");
97
+ exit(1);
98
+ }
99
+
100
+ h3 = AW_H3(object_new(TYPE_AW_H3));
101
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(h3),
102
+ &error_abort);
103
+ object_unref(OBJECT(h3));
104
+
105
+ /* Setup timer properties */
106
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
107
+ &error_abort);
108
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
109
+ &error_abort);
110
+
111
+ /* Mark H3 object realized */
112
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
113
+
114
+ /* SDRAM */
115
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
116
+ machine->ram);
117
+
118
+ orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
119
+ orangepi_binfo.ram_size = machine->ram_size;
120
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
121
+}
122
+
123
+static void orangepi_machine_init(MachineClass *mc)
124
+{
125
+ mc->desc = "Orange Pi PC";
126
+ mc->init = orangepi_init;
127
+ mc->min_cpus = AW_H3_NUM_CPUS;
128
+ mc->max_cpus = AW_H3_NUM_CPUS;
129
+ mc->default_cpus = AW_H3_NUM_CPUS;
130
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
131
+ mc->default_ram_size = 1 * GiB;
132
+ mc->default_ram_id = "orangepi.ram";
133
+}
134
+
135
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
136
diff --git a/MAINTAINERS b/MAINTAINERS
137
index XXXXXXX..XXXXXXX 100644
138
--- a/MAINTAINERS
139
+++ b/MAINTAINERS
140
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
141
S: Maintained
142
F: hw/*/allwinner-h3*
143
F: include/hw/*/allwinner-h3*
144
+F: hw/arm/orangepi.c
145
146
ARM PrimeCell and CMSDK devices
147
M: Peter Maydell <peter.maydell@linaro.org>
148
--
149
2.20.1
150
151
diff view generated by jsdifflib
Deleted patch
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
2
1
3
The Clock Control Unit is responsible for clock signal generation,
4
configuration and distribution in the Allwinner H3 System on Chip.
5
This commit adds support for the Clock Control Unit which emulates
6
a simple read/write register interface.
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/misc/Makefile.objs | 1 +
16
include/hw/arm/allwinner-h3.h | 3 +
17
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
18
hw/arm/allwinner-h3.c | 9 +-
19
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
20
5 files changed, 320 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
22
create mode 100644 hw/misc/allwinner-h3-ccu.c
23
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
27
+++ b/hw/misc/Makefile.objs
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
29
30
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
31
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/arm/boot.h"
42
#include "hw/timer/allwinner-a10-pit.h"
43
#include "hw/intc/arm_gic.h"
44
+#include "hw/misc/allwinner-h3-ccu.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
AW_H3_UART1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
ARMCPU cpus[AW_H3_NUM_CPUS];
58
const hwaddr *memmap;
59
AwA10PITState timer;
60
+ AwH3ClockCtlState ccu;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-ccu.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner H3 Clock Control Unit emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
89
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
90
+#define HW_MISC_ALLWINNER_H3_CCU_H
91
+
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
94
+
95
+/**
96
+ * @name Constants
97
+ * @{
98
+ */
99
+
100
+/** Size of register I/O address space used by CCU device */
101
+#define AW_H3_CCU_IOSIZE (0x400)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
105
+
106
+/** @} */
107
+
108
+/**
109
+ * @name Object model
110
+ * @{
111
+ */
112
+
113
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
114
+#define AW_H3_CCU(obj) \
115
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
116
+
117
+/** @} */
118
+
119
+/**
120
+ * Allwinner H3 CCU object instance state.
121
+ */
122
+typedef struct AwH3ClockCtlState {
123
+ /*< private >*/
124
+ SysBusDevice parent_obj;
125
+ /*< public >*/
126
+
127
+ /** Maps I/O registers in physical memory */
128
+ MemoryRegion iomem;
129
+
130
+ /** Array of hardware registers */
131
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
132
+
133
+} AwH3ClockCtlState;
134
+
135
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
136
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/arm/allwinner-h3.c
139
+++ b/hw/arm/allwinner-h3.c
140
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
141
[AW_H3_SRAM_A1] = 0x00000000,
142
[AW_H3_SRAM_A2] = 0x00044000,
143
[AW_H3_SRAM_C] = 0x00010000,
144
+ [AW_H3_CCU] = 0x01c20000,
145
[AW_H3_PIT] = 0x01c20c00,
146
[AW_H3_UART0] = 0x01c28000,
147
[AW_H3_UART1] = 0x01c28400,
148
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
149
{ "usb2-phy", 0x01c1c000, 4 * KiB },
150
{ "usb3-phy", 0x01c1d000, 4 * KiB },
151
{ "smc", 0x01c1e000, 4 * KiB },
152
- { "ccu", 0x01c20000, 1 * KiB },
153
{ "pio", 0x01c20800, 1 * KiB },
154
{ "owa", 0x01c21000, 1 * KiB },
155
{ "pwm", 0x01c21400, 1 * KiB },
156
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
157
"clk0-freq", &error_abort);
158
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
159
"clk1-freq", &error_abort);
160
+
161
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
162
+ TYPE_AW_H3_CCU);
163
}
164
165
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
166
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
168
&s->sram_c);
169
170
+ /* Clock Control Unit */
171
+ qdev_init_nofail(DEVICE(&s->ccu));
172
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
173
+
174
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
175
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
176
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
177
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
178
new file mode 100644
179
index XXXXXXX..XXXXXXX
180
--- /dev/null
181
+++ b/hw/misc/allwinner-h3-ccu.c
182
@@ -XXX,XX +XXX,XX @@
183
+/*
184
+ * Allwinner H3 Clock Control Unit emulation
185
+ *
186
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
187
+ *
188
+ * This program is free software: you can redistribute it and/or modify
189
+ * it under the terms of the GNU General Public License as published by
190
+ * the Free Software Foundation, either version 2 of the License, or
191
+ * (at your option) any later version.
192
+ *
193
+ * This program is distributed in the hope that it will be useful,
194
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
195
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196
+ * GNU General Public License for more details.
197
+ *
198
+ * You should have received a copy of the GNU General Public License
199
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
200
+ */
201
+
202
+#include "qemu/osdep.h"
203
+#include "qemu/units.h"
204
+#include "hw/sysbus.h"
205
+#include "migration/vmstate.h"
206
+#include "qemu/log.h"
207
+#include "qemu/module.h"
208
+#include "hw/misc/allwinner-h3-ccu.h"
209
+
210
+/* CCU register offsets */
211
+enum {
212
+ REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
213
+ REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
214
+ REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
215
+ REG_PLL_VE = 0x0018, /* PLL VE Control */
216
+ REG_PLL_DDR = 0x0020, /* PLL DDR Control */
217
+ REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
218
+ REG_PLL_GPU = 0x0038, /* PLL GPU Control */
219
+ REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
220
+ REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
221
+ REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
222
+ REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
223
+ REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
224
+ REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
225
+ REG_MBUS = 0x00FC, /* MBUS Reset */
226
+ REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
227
+ REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
228
+ REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
229
+ REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
230
+ REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
231
+ REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
232
+ REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
233
+ REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
234
+ REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
235
+ REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
236
+ REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
237
+ REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
238
+ REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
239
+};
240
+
241
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
242
+
243
+/* CCU register flags */
244
+enum {
245
+ REG_DRAM_CFG_UPDATE = (1 << 16),
246
+};
247
+
248
+enum {
249
+ REG_PLL_ENABLE = (1 << 31),
250
+ REG_PLL_LOCK = (1 << 28),
251
+};
252
+
253
+
254
+/* CCU register reset values */
255
+enum {
256
+ REG_PLL_CPUX_RST = 0x00001000,
257
+ REG_PLL_AUDIO_RST = 0x00035514,
258
+ REG_PLL_VIDEO_RST = 0x03006207,
259
+ REG_PLL_VE_RST = 0x03006207,
260
+ REG_PLL_DDR_RST = 0x00001000,
261
+ REG_PLL_PERIPH0_RST = 0x00041811,
262
+ REG_PLL_GPU_RST = 0x03006207,
263
+ REG_PLL_PERIPH1_RST = 0x00041811,
264
+ REG_PLL_DE_RST = 0x03006207,
265
+ REG_CPUX_AXI_RST = 0x00010000,
266
+ REG_APB1_RST = 0x00001010,
267
+ REG_APB2_RST = 0x01000000,
268
+ REG_DRAM_CFG_RST = 0x00000000,
269
+ REG_MBUS_RST = 0x80000000,
270
+ REG_PLL_TIME0_RST = 0x000000FF,
271
+ REG_PLL_TIME1_RST = 0x000000FF,
272
+ REG_PLL_CPUX_BIAS_RST = 0x08100200,
273
+ REG_PLL_AUDIO_BIAS_RST = 0x10100000,
274
+ REG_PLL_VIDEO_BIAS_RST = 0x10100000,
275
+ REG_PLL_VE_BIAS_RST = 0x10100000,
276
+ REG_PLL_DDR_BIAS_RST = 0x81104000,
277
+ REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
278
+ REG_PLL_GPU_BIAS_RST = 0x10100000,
279
+ REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
280
+ REG_PLL_DE_BIAS_RST = 0x10100000,
281
+ REG_PLL_CPUX_TUNING_RST = 0x0A101000,
282
+ REG_PLL_DDR_TUNING_RST = 0x14880000,
283
+};
284
+
285
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
286
+ unsigned size)
287
+{
288
+ const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
289
+ const uint32_t idx = REG_INDEX(offset);
290
+
291
+ switch (offset) {
292
+ case 0x308 ... AW_H3_CCU_IOSIZE:
293
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
294
+ __func__, (uint32_t)offset);
295
+ return 0;
296
+ }
297
+
298
+ return s->regs[idx];
299
+}
300
+
301
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
302
+ uint64_t val, unsigned size)
303
+{
304
+ AwH3ClockCtlState *s = AW_H3_CCU(opaque);
305
+ const uint32_t idx = REG_INDEX(offset);
306
+
307
+ switch (offset) {
308
+ case REG_DRAM_CFG: /* DRAM Configuration */
309
+ val &= ~REG_DRAM_CFG_UPDATE;
310
+ break;
311
+ case REG_PLL_CPUX: /* PLL CPUX Control */
312
+ case REG_PLL_AUDIO: /* PLL Audio Control */
313
+ case REG_PLL_VIDEO: /* PLL Video Control */
314
+ case REG_PLL_VE: /* PLL VE Control */
315
+ case REG_PLL_DDR: /* PLL DDR Control */
316
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
317
+ case REG_PLL_GPU: /* PLL GPU Control */
318
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
319
+ case REG_PLL_DE: /* PLL Display Engine Control */
320
+ if (val & REG_PLL_ENABLE) {
321
+ val |= REG_PLL_LOCK;
322
+ }
323
+ break;
324
+ case 0x308 ... AW_H3_CCU_IOSIZE:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ default:
329
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
330
+ __func__, (uint32_t)offset);
331
+ break;
332
+ }
333
+
334
+ s->regs[idx] = (uint32_t) val;
335
+}
336
+
337
+static const MemoryRegionOps allwinner_h3_ccu_ops = {
338
+ .read = allwinner_h3_ccu_read,
339
+ .write = allwinner_h3_ccu_write,
340
+ .endianness = DEVICE_NATIVE_ENDIAN,
341
+ .valid = {
342
+ .min_access_size = 4,
343
+ .max_access_size = 4,
344
+ },
345
+ .impl.min_access_size = 4,
346
+};
347
+
348
+static void allwinner_h3_ccu_reset(DeviceState *dev)
349
+{
350
+ AwH3ClockCtlState *s = AW_H3_CCU(dev);
351
+
352
+ /* Set default values for registers */
353
+ s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
354
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
355
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
356
+ s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
357
+ s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
358
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
359
+ s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
360
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
361
+ s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
362
+ s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
363
+ s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
364
+ s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
365
+ s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
366
+ s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
367
+ s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
368
+ s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
369
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
370
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
371
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
372
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
373
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
374
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
375
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
376
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
377
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
378
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
379
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
380
+}
381
+
382
+static void allwinner_h3_ccu_init(Object *obj)
383
+{
384
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
385
+ AwH3ClockCtlState *s = AW_H3_CCU(obj);
386
+
387
+ /* Memory mapping */
388
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
389
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
390
+ sysbus_init_mmio(sbd, &s->iomem);
391
+}
392
+
393
+static const VMStateDescription allwinner_h3_ccu_vmstate = {
394
+ .name = "allwinner-h3-ccu",
395
+ .version_id = 1,
396
+ .minimum_version_id = 1,
397
+ .fields = (VMStateField[]) {
398
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
399
+ VMSTATE_END_OF_LIST()
400
+ }
401
+};
402
+
403
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
404
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
407
+ dc->reset = allwinner_h3_ccu_reset;
408
+ dc->vmsd = &allwinner_h3_ccu_vmstate;
409
+}
410
+
411
+static const TypeInfo allwinner_h3_ccu_info = {
412
+ .name = TYPE_AW_H3_CCU,
413
+ .parent = TYPE_SYS_BUS_DEVICE,
414
+ .instance_init = allwinner_h3_ccu_init,
415
+ .instance_size = sizeof(AwH3ClockCtlState),
416
+ .class_init = allwinner_h3_ccu_class_init,
417
+};
418
+
419
+static void allwinner_h3_ccu_register(void)
420
+{
421
+ type_register_static(&allwinner_h3_ccu_info);
422
+}
423
+
424
+type_init(allwinner_h3_ccu_register)
425
--
426
2.20.1
427
428
diff view generated by jsdifflib
Deleted patch
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
2
1
3
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
4
connections which provide software access using the Enhanced
5
Host Controller Interface (EHCI) and Open Host Controller
6
Interface (OHCI) interfaces. This commit adds support for
7
both interfaces in the Allwinner H3 System on Chip.
8
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/usb/hcd-ehci.h | 1 +
18
include/hw/arm/allwinner-h3.h | 8 +++++++
19
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
20
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
21
hw/arm/Kconfig | 2 ++
22
5 files changed, 72 insertions(+)
23
24
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/usb/hcd-ehci.h
27
+++ b/hw/usb/hcd-ehci.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState {
29
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
30
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
31
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
32
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
33
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
34
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
35
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@ enum {
41
AW_H3_SRAM_A1,
42
AW_H3_SRAM_A2,
43
AW_H3_SRAM_C,
44
+ AW_H3_EHCI0,
45
+ AW_H3_OHCI0,
46
+ AW_H3_EHCI1,
47
+ AW_H3_OHCI1,
48
+ AW_H3_EHCI2,
49
+ AW_H3_OHCI2,
50
+ AW_H3_EHCI3,
51
+ AW_H3_OHCI3,
52
AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/allwinner-h3.c
58
+++ b/hw/arm/allwinner-h3.c
59
@@ -XXX,XX +XXX,XX @@
60
#include "hw/sysbus.h"
61
#include "hw/char/serial.h"
62
#include "hw/misc/unimp.h"
63
+#include "hw/usb/hcd-ehci.h"
64
#include "sysemu/sysemu.h"
65
#include "hw/arm/allwinner-h3.h"
66
67
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
68
[AW_H3_SRAM_A1] = 0x00000000,
69
[AW_H3_SRAM_A2] = 0x00044000,
70
[AW_H3_SRAM_C] = 0x00010000,
71
+ [AW_H3_EHCI0] = 0x01c1a000,
72
+ [AW_H3_OHCI0] = 0x01c1a400,
73
+ [AW_H3_EHCI1] = 0x01c1b000,
74
+ [AW_H3_OHCI1] = 0x01c1b400,
75
+ [AW_H3_EHCI2] = 0x01c1c000,
76
+ [AW_H3_OHCI2] = 0x01c1c400,
77
+ [AW_H3_EHCI3] = 0x01c1d000,
78
+ [AW_H3_OHCI3] = 0x01c1d400,
79
[AW_H3_CCU] = 0x01c20000,
80
[AW_H3_PIT] = 0x01c20c00,
81
[AW_H3_UART0] = 0x01c28000,
82
@@ -XXX,XX +XXX,XX @@ enum {
83
AW_H3_GIC_SPI_UART3 = 3,
84
AW_H3_GIC_SPI_TIMER0 = 18,
85
AW_H3_GIC_SPI_TIMER1 = 19,
86
+ AW_H3_GIC_SPI_EHCI0 = 72,
87
+ AW_H3_GIC_SPI_OHCI0 = 73,
88
+ AW_H3_GIC_SPI_EHCI1 = 74,
89
+ AW_H3_GIC_SPI_OHCI1 = 75,
90
+ AW_H3_GIC_SPI_EHCI2 = 76,
91
+ AW_H3_GIC_SPI_OHCI2 = 77,
92
+ AW_H3_GIC_SPI_EHCI3 = 78,
93
+ AW_H3_GIC_SPI_OHCI3 = 79,
94
};
95
96
/* Allwinner H3 general constants */
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
98
qdev_init_nofail(DEVICE(&s->ccu));
99
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
100
101
+ /* Universal Serial Bus */
102
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
103
+ qdev_get_gpio_in(DEVICE(&s->gic),
104
+ AW_H3_GIC_SPI_EHCI0));
105
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
106
+ qdev_get_gpio_in(DEVICE(&s->gic),
107
+ AW_H3_GIC_SPI_EHCI1));
108
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
109
+ qdev_get_gpio_in(DEVICE(&s->gic),
110
+ AW_H3_GIC_SPI_EHCI2));
111
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
112
+ qdev_get_gpio_in(DEVICE(&s->gic),
113
+ AW_H3_GIC_SPI_EHCI3));
114
+
115
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
116
+ qdev_get_gpio_in(DEVICE(&s->gic),
117
+ AW_H3_GIC_SPI_OHCI0));
118
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
119
+ qdev_get_gpio_in(DEVICE(&s->gic),
120
+ AW_H3_GIC_SPI_OHCI1));
121
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
122
+ qdev_get_gpio_in(DEVICE(&s->gic),
123
+ AW_H3_GIC_SPI_OHCI2));
124
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
125
+ qdev_get_gpio_in(DEVICE(&s->gic),
126
+ AW_H3_GIC_SPI_OHCI3));
127
+
128
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
129
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
130
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
131
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/usb/hcd-ehci-sysbus.c
134
+++ b/hw/usb/hcd-ehci-sysbus.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = {
136
.class_init = ehci_exynos4210_class_init,
137
};
138
139
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
140
+{
141
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
142
+ DeviceClass *dc = DEVICE_CLASS(oc);
143
+
144
+ sec->capsbase = 0x0;
145
+ sec->opregbase = 0x10;
146
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
147
+}
148
+
149
+static const TypeInfo ehci_aw_h3_type_info = {
150
+ .name = TYPE_AW_H3_EHCI,
151
+ .parent = TYPE_SYS_BUS_EHCI,
152
+ .class_init = ehci_aw_h3_class_init,
153
+};
154
+
155
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
156
{
157
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
158
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
159
type_register_static(&ehci_type_info);
160
type_register_static(&ehci_platform_type_info);
161
type_register_static(&ehci_exynos4210_type_info);
162
+ type_register_static(&ehci_aw_h3_type_info);
163
type_register_static(&ehci_tegra2_type_info);
164
type_register_static(&ehci_ppc4xx_type_info);
165
type_register_static(&ehci_fusbh200_type_info);
166
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
167
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/arm/Kconfig
169
+++ b/hw/arm/Kconfig
170
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
171
select ARM_TIMER
172
select ARM_GIC
173
select UNIMP
174
+ select USB_OHCI
175
+ select USB_EHCI_SYSBUS
176
177
config RASPI
178
bool
179
--
180
2.20.1
181
182
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
The function ide_bus_new() does an in-place initialization. Rename
2
it to ide_bus_init() to follow our _init vs _new convention.
2
3
3
The Allwinner System on Chip families sun4i and above contain
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
an integrated storage controller for Secure Digital (SD) and
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Multi Media Card (MMC) interfaces. This commit adds support
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
6
for the Allwinner SD/MMC storage controller with the following
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
7
emulated features:
8
Reviewed-by: John Snow <jsnow@redhat.com>
9
Acked-by: John Snow <jsnow@redhat.com> (Feel free to merge.)
10
Message-id: 20210923121153.23754-7-peter.maydell@linaro.org
11
---
12
include/hw/ide/internal.h | 4 ++--
13
hw/ide/ahci.c | 2 +-
14
hw/ide/cmd646.c | 2 +-
15
hw/ide/isa.c | 2 +-
16
hw/ide/macio.c | 2 +-
17
hw/ide/microdrive.c | 2 +-
18
hw/ide/mmio.c | 2 +-
19
hw/ide/piix.c | 2 +-
20
hw/ide/qdev.c | 2 +-
21
hw/ide/sii3112.c | 2 +-
22
hw/ide/via.c | 2 +-
23
11 files changed, 12 insertions(+), 12 deletions(-)
8
24
9
* DMA transfers
25
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
10
* Direct FIFO I/O
11
* Short/Long format command responses
12
* Auto-Stop command (CMD12)
13
* Insert & remove card detection
14
15
The following boards are extended with the SD host controller:
16
17
* Cubieboard (hw/arm/cubieboard.c)
18
* Orange Pi PC (hw/arm/orangepi.c)
19
20
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
21
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
22
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
hw/sd/Makefile.objs | 1 +
27
include/hw/arm/allwinner-a10.h | 2 +
28
include/hw/arm/allwinner-h3.h | 3 +
29
include/hw/sd/allwinner-sdhost.h | 135 +++++
30
hw/arm/allwinner-a10.c | 11 +
31
hw/arm/allwinner-h3.c | 15 +-
32
hw/arm/cubieboard.c | 15 +
33
hw/arm/orangepi.c | 16 +
34
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
35
hw/arm/Kconfig | 1 +
36
hw/sd/trace-events | 7 +
37
11 files changed, 1059 insertions(+), 1 deletion(-)
38
create mode 100644 include/hw/sd/allwinner-sdhost.h
39
create mode 100644 hw/sd/allwinner-sdhost.c
40
41
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
42
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/sd/Makefile.objs
27
--- a/include/hw/ide/internal.h
44
+++ b/hw/sd/Makefile.objs
28
+++ b/include/hw/ide/internal.h
45
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o
29
@@ -XXX,XX +XXX,XX @@ void ide_atapi_cmd(IDEState *s);
46
common-obj-$(CONFIG_SDHCI) += sdhci.o
30
void ide_atapi_cmd_reply_end(IDEState *s);
47
common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o
31
48
32
/* hw/ide/qdev.c */
49
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o
33
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
50
common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
34
- int bus_id, int max_units);
51
common-obj-$(CONFIG_OMAP) += omap_mmc.o
35
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
52
common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
36
+ int bus_id, int max_units);
53
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
37
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
38
39
int ide_handle_rw_error(IDEState *s, int error, int op);
40
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
54
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
55
--- a/include/hw/arm/allwinner-a10.h
42
--- a/hw/ide/ahci.c
56
+++ b/include/hw/arm/allwinner-a10.h
43
+++ b/hw/ide/ahci.c
57
@@ -XXX,XX +XXX,XX @@
44
@@ -XXX,XX +XXX,XX @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
58
#include "hw/timer/allwinner-a10-pit.h"
45
for (i = 0; i < s->ports; i++) {
59
#include "hw/intc/allwinner-a10-pic.h"
46
AHCIDevice *ad = &s->dev[i];
60
#include "hw/net/allwinner_emac.h"
47
61
+#include "hw/sd/allwinner-sdhost.h"
48
- ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
62
#include "hw/ide/ahci.h"
49
+ ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
63
#include "hw/usb/hcd-ohci.h"
50
ide_init2(&ad->port, irqs[i]);
64
#include "hw/usb/hcd-ehci.h"
51
65
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
52
ad->hba = s;
66
AwA10PICState intc;
53
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
67
AwEmacState emac;
68
AllwinnerAHCIState sata;
69
+ AwSdHostState mmc0;
70
MemoryRegion sram_a;
71
EHCISysBusState ehci[AW_A10_NUM_USB];
72
OHCISysBusState ohci[AW_A10_NUM_USB];
73
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
74
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
75
--- a/include/hw/arm/allwinner-h3.h
55
--- a/hw/ide/cmd646.c
76
+++ b/include/hw/arm/allwinner-h3.h
56
+++ b/hw/ide/cmd646.c
77
@@ -XXX,XX +XXX,XX @@
57
@@ -XXX,XX +XXX,XX @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
78
#include "hw/misc/allwinner-cpucfg.h"
58
79
#include "hw/misc/allwinner-h3-sysctrl.h"
59
qdev_init_gpio_in(ds, cmd646_set_irq, 2);
80
#include "hw/misc/allwinner-sid.h"
60
for (i = 0; i < 2; i++) {
81
+#include "hw/sd/allwinner-sdhost.h"
61
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
82
#include "target/arm/cpu.h"
62
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
83
63
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
84
/**
64
85
@@ -XXX,XX +XXX,XX @@ enum {
65
bmdma_init(&d->bus[i], &d->bmdma[i], d);
86
AW_H3_SRAM_A2,
66
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
87
AW_H3_SRAM_C,
88
AW_H3_SYSCTRL,
89
+ AW_H3_MMC0,
90
AW_H3_SID,
91
AW_H3_EHCI0,
92
AW_H3_OHCI0,
93
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
94
AwCpuCfgState cpucfg;
95
AwH3SysCtrlState sysctrl;
96
AwSidState sid;
97
+ AwSdHostState mmc0;
98
GICState gic;
99
MemoryRegion sram_a1;
100
MemoryRegion sram_a2;
101
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
102
new file mode 100644
103
index XXXXXXX..XXXXXXX
104
--- /dev/null
105
+++ b/include/hw/sd/allwinner-sdhost.h
106
@@ -XXX,XX +XXX,XX @@
107
+/*
108
+ * Allwinner (sun4i and above) SD Host Controller emulation
109
+ *
110
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
111
+ *
112
+ * This program is free software: you can redistribute it and/or modify
113
+ * it under the terms of the GNU General Public License as published by
114
+ * the Free Software Foundation, either version 2 of the License, or
115
+ * (at your option) any later version.
116
+ *
117
+ * This program is distributed in the hope that it will be useful,
118
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
119
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
120
+ * GNU General Public License for more details.
121
+ *
122
+ * You should have received a copy of the GNU General Public License
123
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
124
+ */
125
+
126
+#ifndef HW_SD_ALLWINNER_SDHOST_H
127
+#define HW_SD_ALLWINNER_SDHOST_H
128
+
129
+#include "qom/object.h"
130
+#include "hw/sysbus.h"
131
+#include "hw/sd/sd.h"
132
+
133
+/**
134
+ * Object model types
135
+ * @{
136
+ */
137
+
138
+/** Generic Allwinner SD Host Controller (abstract) */
139
+#define TYPE_AW_SDHOST "allwinner-sdhost"
140
+
141
+/** Allwinner sun4i family (A10, A12) */
142
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
143
+
144
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
145
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
146
+
147
+/** @} */
148
+
149
+/**
150
+ * Object model macros
151
+ * @{
152
+ */
153
+
154
+#define AW_SDHOST(obj) \
155
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
156
+#define AW_SDHOST_CLASS(klass) \
157
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
158
+#define AW_SDHOST_GET_CLASS(obj) \
159
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
160
+
161
+/** @} */
162
+
163
+/**
164
+ * Allwinner SD Host Controller object instance state.
165
+ */
166
+typedef struct AwSdHostState {
167
+ /*< private >*/
168
+ SysBusDevice busdev;
169
+ /*< public >*/
170
+
171
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
172
+ SDBus sdbus;
173
+
174
+ /** Maps I/O registers in physical memory */
175
+ MemoryRegion iomem;
176
+
177
+ /** Interrupt output signal to notify CPU */
178
+ qemu_irq irq;
179
+
180
+ /** Number of bytes left in current DMA transfer */
181
+ uint32_t transfer_cnt;
182
+
183
+ /**
184
+ * @name Hardware Registers
185
+ * @{
186
+ */
187
+
188
+ uint32_t global_ctl; /**< Global Control */
189
+ uint32_t clock_ctl; /**< Clock Control */
190
+ uint32_t timeout; /**< Timeout */
191
+ uint32_t bus_width; /**< Bus Width */
192
+ uint32_t block_size; /**< Block Size */
193
+ uint32_t byte_count; /**< Byte Count */
194
+
195
+ uint32_t command; /**< Command */
196
+ uint32_t command_arg; /**< Command Argument */
197
+ uint32_t response[4]; /**< Command Response */
198
+
199
+ uint32_t irq_mask; /**< Interrupt Mask */
200
+ uint32_t irq_status; /**< Raw Interrupt Status */
201
+ uint32_t status; /**< Status */
202
+
203
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
204
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
205
+ uint32_t debug_enable; /**< Debug Enable */
206
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
207
+ uint32_t newtiming_set; /**< SD New Timing Set */
208
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
209
+ uint32_t hardware_rst; /**< Hardware Reset */
210
+ uint32_t dmac; /**< Internal DMA Controller Control */
211
+ uint32_t desc_base; /**< Descriptor List Base Address */
212
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
213
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
214
+ uint32_t card_threshold; /**< Card Threshold Control */
215
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
216
+ uint32_t response_crc; /**< Response CRC */
217
+ uint32_t data_crc[8]; /**< Data CRC */
218
+ uint32_t status_crc; /**< Status CRC */
219
+
220
+ /** @} */
221
+
222
+} AwSdHostState;
223
+
224
+/**
225
+ * Allwinner SD Host Controller class-level struct.
226
+ *
227
+ * This struct is filled by each sunxi device specific code
228
+ * such that the generic code can use this struct to support
229
+ * all devices.
230
+ */
231
+typedef struct AwSdHostClass {
232
+ /*< private >*/
233
+ SysBusDeviceClass parent_class;
234
+ /*< public >*/
235
+
236
+ /** Maximum buffer size in bytes per DMA descriptor */
237
+ size_t max_desc_size;
238
+
239
+} AwSdHostClass;
240
+
241
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
242
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
243
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/arm/allwinner-a10.c
68
--- a/hw/ide/isa.c
245
+++ b/hw/arm/allwinner-a10.c
69
+++ b/hw/ide/isa.c
246
@@ -XXX,XX +XXX,XX @@
70
@@ -XXX,XX +XXX,XX @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)
247
#include "hw/boards.h"
71
ISADevice *isadev = ISA_DEVICE(dev);
248
#include "hw/usb/hcd-ohci.h"
72
ISAIDEState *s = ISA_IDE(dev);
249
73
250
+#define AW_A10_MMC0_BASE 0x01c0f000
74
- ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2);
251
#define AW_A10_PIC_REG_BASE 0x01c20400
75
+ ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
252
#define AW_A10_PIT_REG_BASE 0x01c20c00
76
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
253
#define AW_A10_UART0_REG_BASE 0x01c28000
77
isa_init_irq(isadev, &s->irq, s->isairq);
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
78
ide_init2(&s->bus, s->irq);
255
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
79
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
256
}
80
index XXXXXXX..XXXXXXX 100644
257
}
81
--- a/hw/ide/macio.c
258
+
82
+++ b/hw/ide/macio.c
259
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
83
@@ -XXX,XX +XXX,XX @@ static void macio_ide_initfn(Object *obj)
260
+ TYPE_AW_SDHOST_SUN4I);
84
SysBusDevice *d = SYS_BUS_DEVICE(obj);
85
MACIOIDEState *s = MACIO_IDE(obj);
86
87
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
88
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
89
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
90
sysbus_init_mmio(d, &s->mem);
91
sysbus_init_irq(d, &s->real_ide_irq);
92
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/ide/microdrive.c
95
+++ b/hw/ide/microdrive.c
96
@@ -XXX,XX +XXX,XX @@ static void microdrive_init(Object *obj)
97
{
98
MicroDriveState *md = MICRODRIVE(obj);
99
100
- ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
101
+ ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
261
}
102
}
262
103
263
static void aw_a10_realize(DeviceState *dev, Error **errp)
104
static void microdrive_class_init(ObjectClass *oc, void *data)
264
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
105
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
265
qdev_get_gpio_in(dev, 64 + i));
106
index XXXXXXX..XXXXXXX 100644
266
}
107
--- a/hw/ide/mmio.c
267
}
108
+++ b/hw/ide/mmio.c
268
+
109
@@ -XXX,XX +XXX,XX @@ static void mmio_ide_initfn(Object *obj)
269
+ /* SD/MMC */
110
SysBusDevice *d = SYS_BUS_DEVICE(obj);
270
+ qdev_init_nofail(DEVICE(&s->mmc0));
111
MMIOState *s = MMIO_IDE(obj);
271
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
112
272
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
113
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
273
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
114
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
274
+ "sd-bus", &error_abort);
115
sysbus_init_irq(d, &s->irq);
275
}
116
}
276
117
277
static void aw_a10_class_init(ObjectClass *oc, void *data)
118
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
278
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
279
index XXXXXXX..XXXXXXX 100644
119
index XXXXXXX..XXXXXXX 100644
280
--- a/hw/arm/allwinner-h3.c
120
--- a/hw/ide/piix.c
281
+++ b/hw/arm/allwinner-h3.c
121
+++ b/hw/ide/piix.c
282
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
122
@@ -XXX,XX +XXX,XX @@ static int pci_piix_init_ports(PCIIDEState *d)
283
[AW_H3_SRAM_A2] = 0x00044000,
123
int i, ret;
284
[AW_H3_SRAM_C] = 0x00010000,
124
285
[AW_H3_SYSCTRL] = 0x01c00000,
125
for (i = 0; i < 2; i++) {
286
+ [AW_H3_MMC0] = 0x01c0f000,
126
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
287
[AW_H3_SID] = 0x01c14000,
127
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
288
[AW_H3_EHCI0] = 0x01c1a000,
128
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
289
[AW_H3_OHCI0] = 0x01c1a400,
129
port_info[i].iobase2);
290
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
130
if (ret) {
291
{ "lcd0", 0x01c0c000, 4 * KiB },
131
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
292
{ "lcd1", 0x01c0d000, 4 * KiB },
293
{ "ve", 0x01c0e000, 4 * KiB },
294
- { "mmc0", 0x01c0f000, 4 * KiB },
295
{ "mmc1", 0x01c10000, 4 * KiB },
296
{ "mmc2", 0x01c11000, 4 * KiB },
297
{ "crypto", 0x01c15000, 4 * KiB },
298
@@ -XXX,XX +XXX,XX @@ enum {
299
AW_H3_GIC_SPI_UART3 = 3,
300
AW_H3_GIC_SPI_TIMER0 = 18,
301
AW_H3_GIC_SPI_TIMER1 = 19,
302
+ AW_H3_GIC_SPI_MMC0 = 60,
303
AW_H3_GIC_SPI_EHCI0 = 72,
304
AW_H3_GIC_SPI_OHCI0 = 73,
305
AW_H3_GIC_SPI_EHCI1 = 74,
306
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
307
TYPE_AW_SID);
308
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
309
"identifier", &error_abort);
310
+
311
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
312
+ TYPE_AW_SDHOST_SUN5I);
313
}
314
315
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
316
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
317
qdev_init_nofail(DEVICE(&s->sid));
318
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
319
320
+ /* SD/MMC */
321
+ qdev_init_nofail(DEVICE(&s->mmc0));
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
323
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
324
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
325
+
326
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
327
+ "sd-bus", &error_abort);
328
+
329
/* Universal Serial Bus */
330
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
331
qdev_get_gpio_in(DEVICE(&s->gic),
332
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
333
index XXXXXXX..XXXXXXX 100644
132
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/cubieboard.c
133
--- a/hw/ide/qdev.c
335
+++ b/hw/arm/cubieboard.c
134
+++ b/hw/ide/qdev.c
336
@@ -XXX,XX +XXX,XX @@
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
337
#include "sysemu/sysemu.h"
136
.class_init = ide_bus_class_init,
338
#include "hw/sysbus.h"
137
};
339
#include "hw/boards.h"
138
340
+#include "hw/qdev-properties.h"
139
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
341
#include "hw/arm/allwinner-a10.h"
140
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
342
141
int bus_id, int max_units)
343
static struct arm_boot_info cubieboard_binfo = {
344
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
345
{
142
{
346
AwA10State *a10;
143
qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
347
Error *err = NULL;
144
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
348
+ DriveInfo *di;
349
+ BlockBackend *blk;
350
+ BusState *bus;
351
+ DeviceState *carddev;
352
353
/* BIOS is not supported by this board */
354
if (bios_name) {
355
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
356
exit(1);
357
}
358
359
+ /* Retrieve SD bus */
360
+ di = drive_get_next(IF_SD);
361
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
362
+ bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
363
+
364
+ /* Plug in SD card */
365
+ carddev = qdev_create(bus, TYPE_SD_CARD);
366
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
367
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
368
+
369
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
370
machine->ram);
371
372
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
373
index XXXXXXX..XXXXXXX 100644
145
index XXXXXXX..XXXXXXX 100644
374
--- a/hw/arm/orangepi.c
146
--- a/hw/ide/sii3112.c
375
+++ b/hw/arm/orangepi.c
147
+++ b/hw/ide/sii3112.c
376
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = {
148
@@ -XXX,XX +XXX,XX @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
377
static void orangepi_init(MachineState *machine)
149
378
{
150
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
379
AwH3State *h3;
151
for (i = 0; i < 2; i++) {
380
+ DriveInfo *di;
152
- ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
381
+ BlockBackend *blk;
153
+ ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
382
+ BusState *bus;
154
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
383
+ DeviceState *carddev;
155
384
156
bmdma_init(&s->bus[i], &s->bmdma[i], s);
385
/* BIOS is not supported by this board */
157
diff --git a/hw/ide/via.c b/hw/ide/via.c
386
if (bios_name) {
387
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
388
/* Mark H3 object realized */
389
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
390
391
+ /* Retrieve SD bus */
392
+ di = drive_get_next(IF_SD);
393
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
394
+ bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
395
+
396
+ /* Plug in SD card */
397
+ carddev = qdev_create(bus, TYPE_SD_CARD);
398
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
399
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
400
+
401
/* SDRAM */
402
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
403
machine->ram);
404
@@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc)
405
{
406
mc->desc = "Orange Pi PC";
407
mc->init = orangepi_init;
408
+ mc->block_default_type = IF_SD;
409
+ mc->units_per_default_bus = 1;
410
mc->min_cpus = AW_H3_NUM_CPUS;
411
mc->max_cpus = AW_H3_NUM_CPUS;
412
mc->default_cpus = AW_H3_NUM_CPUS;
413
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
414
new file mode 100644
415
index XXXXXXX..XXXXXXX
416
--- /dev/null
417
+++ b/hw/sd/allwinner-sdhost.c
418
@@ -XXX,XX +XXX,XX @@
419
+/*
420
+ * Allwinner (sun4i and above) SD Host Controller emulation
421
+ *
422
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
423
+ *
424
+ * This program is free software: you can redistribute it and/or modify
425
+ * it under the terms of the GNU General Public License as published by
426
+ * the Free Software Foundation, either version 2 of the License, or
427
+ * (at your option) any later version.
428
+ *
429
+ * This program is distributed in the hope that it will be useful,
430
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
431
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
432
+ * GNU General Public License for more details.
433
+ *
434
+ * You should have received a copy of the GNU General Public License
435
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
436
+ */
437
+
438
+#include "qemu/osdep.h"
439
+#include "qemu/log.h"
440
+#include "qemu/module.h"
441
+#include "qemu/units.h"
442
+#include "sysemu/blockdev.h"
443
+#include "hw/irq.h"
444
+#include "hw/sd/allwinner-sdhost.h"
445
+#include "migration/vmstate.h"
446
+#include "trace.h"
447
+
448
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
449
+#define AW_SDHOST_BUS(obj) \
450
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
451
+
452
+/* SD Host register offsets */
453
+enum {
454
+ REG_SD_GCTL = 0x00, /* Global Control */
455
+ REG_SD_CKCR = 0x04, /* Clock Control */
456
+ REG_SD_TMOR = 0x08, /* Timeout */
457
+ REG_SD_BWDR = 0x0C, /* Bus Width */
458
+ REG_SD_BKSR = 0x10, /* Block Size */
459
+ REG_SD_BYCR = 0x14, /* Byte Count */
460
+ REG_SD_CMDR = 0x18, /* Command */
461
+ REG_SD_CAGR = 0x1C, /* Command Argument */
462
+ REG_SD_RESP0 = 0x20, /* Response Zero */
463
+ REG_SD_RESP1 = 0x24, /* Response One */
464
+ REG_SD_RESP2 = 0x28, /* Response Two */
465
+ REG_SD_RESP3 = 0x2C, /* Response Three */
466
+ REG_SD_IMKR = 0x30, /* Interrupt Mask */
467
+ REG_SD_MISR = 0x34, /* Masked Interrupt Status */
468
+ REG_SD_RISR = 0x38, /* Raw Interrupt Status */
469
+ REG_SD_STAR = 0x3C, /* Status */
470
+ REG_SD_FWLR = 0x40, /* FIFO Water Level */
471
+ REG_SD_FUNS = 0x44, /* FIFO Function Select */
472
+ REG_SD_DBGC = 0x50, /* Debug Enable */
473
+ REG_SD_A12A = 0x58, /* Auto command 12 argument */
474
+ REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
475
+ REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
476
+ REG_SD_HWRST = 0x78, /* Hardware Reset Register */
477
+ REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
478
+ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
479
+ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
480
+ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
481
+ REG_SD_THLDC = 0x100, /* Card Threshold Control */
482
+ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
483
+ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
484
+ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
485
+ REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
486
+ REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
487
+ REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
488
+ REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
489
+ REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
490
+ REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
491
+ REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
492
+ REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
493
+ REG_SD_FIFO = 0x200, /* Read/Write FIFO */
494
+};
495
+
496
+/* SD Host register flags */
497
+enum {
498
+ SD_GCTL_FIFO_AC_MOD = (1 << 31),
499
+ SD_GCTL_DDR_MOD_SEL = (1 << 10),
500
+ SD_GCTL_CD_DBC_ENB = (1 << 8),
501
+ SD_GCTL_DMA_ENB = (1 << 5),
502
+ SD_GCTL_INT_ENB = (1 << 4),
503
+ SD_GCTL_DMA_RST = (1 << 2),
504
+ SD_GCTL_FIFO_RST = (1 << 1),
505
+ SD_GCTL_SOFT_RST = (1 << 0),
506
+};
507
+
508
+enum {
509
+ SD_CMDR_LOAD = (1 << 31),
510
+ SD_CMDR_CLKCHANGE = (1 << 21),
511
+ SD_CMDR_WRITE = (1 << 10),
512
+ SD_CMDR_AUTOSTOP = (1 << 12),
513
+ SD_CMDR_DATA = (1 << 9),
514
+ SD_CMDR_RESPONSE_LONG = (1 << 7),
515
+ SD_CMDR_RESPONSE = (1 << 6),
516
+ SD_CMDR_CMDID_MASK = (0x3f),
517
+};
518
+
519
+enum {
520
+ SD_RISR_CARD_REMOVE = (1 << 31),
521
+ SD_RISR_CARD_INSERT = (1 << 30),
522
+ SD_RISR_SDIO_INTR = (1 << 16),
523
+ SD_RISR_AUTOCMD_DONE = (1 << 14),
524
+ SD_RISR_DATA_COMPLETE = (1 << 3),
525
+ SD_RISR_CMD_COMPLETE = (1 << 2),
526
+ SD_RISR_NO_RESPONSE = (1 << 1),
527
+};
528
+
529
+enum {
530
+ SD_STAR_CARD_PRESENT = (1 << 8),
531
+};
532
+
533
+enum {
534
+ SD_IDST_INT_SUMMARY = (1 << 8),
535
+ SD_IDST_RECEIVE_IRQ = (1 << 1),
536
+ SD_IDST_TRANSMIT_IRQ = (1 << 0),
537
+ SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
538
+ SD_IDST_WR_MASK = (0x3ff),
539
+};
540
+
541
+/* SD Host register reset values */
542
+enum {
543
+ REG_SD_GCTL_RST = 0x00000300,
544
+ REG_SD_CKCR_RST = 0x0,
545
+ REG_SD_TMOR_RST = 0xFFFFFF40,
546
+ REG_SD_BWDR_RST = 0x0,
547
+ REG_SD_BKSR_RST = 0x00000200,
548
+ REG_SD_BYCR_RST = 0x00000200,
549
+ REG_SD_CMDR_RST = 0x0,
550
+ REG_SD_CAGR_RST = 0x0,
551
+ REG_SD_RESP_RST = 0x0,
552
+ REG_SD_IMKR_RST = 0x0,
553
+ REG_SD_MISR_RST = 0x0,
554
+ REG_SD_RISR_RST = 0x0,
555
+ REG_SD_STAR_RST = 0x00000100,
556
+ REG_SD_FWLR_RST = 0x000F0000,
557
+ REG_SD_FUNS_RST = 0x0,
558
+ REG_SD_DBGC_RST = 0x0,
559
+ REG_SD_A12A_RST = 0x0000FFFF,
560
+ REG_SD_NTSR_RST = 0x00000001,
561
+ REG_SD_SDBG_RST = 0x0,
562
+ REG_SD_HWRST_RST = 0x00000001,
563
+ REG_SD_DMAC_RST = 0x0,
564
+ REG_SD_DLBA_RST = 0x0,
565
+ REG_SD_IDST_RST = 0x0,
566
+ REG_SD_IDIE_RST = 0x0,
567
+ REG_SD_THLDC_RST = 0x0,
568
+ REG_SD_DSBD_RST = 0x0,
569
+ REG_SD_RES_CRC_RST = 0x0,
570
+ REG_SD_DATA_CRC_RST = 0x0,
571
+ REG_SD_CRC_STA_RST = 0x0,
572
+ REG_SD_FIFO_RST = 0x0,
573
+};
574
+
575
+/* Data transfer descriptor for DMA */
576
+typedef struct TransferDescriptor {
577
+ uint32_t status; /* Status flags */
578
+ uint32_t size; /* Data buffer size */
579
+ uint32_t addr; /* Data buffer address */
580
+ uint32_t next; /* Physical address of next descriptor */
581
+} TransferDescriptor;
582
+
583
+/* Data transfer descriptor flags */
584
+enum {
585
+ DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
586
+ DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
587
+ DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
588
+ DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
589
+ DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
590
+ DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
591
+ DESC_SIZE_MASK = (0xfffffffc)
592
+};
593
+
594
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
595
+{
596
+ uint32_t irq;
597
+
598
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
599
+ irq = s->irq_status & s->irq_mask;
600
+ } else {
601
+ irq = 0;
602
+ }
603
+
604
+ trace_allwinner_sdhost_update_irq(irq);
605
+ qemu_set_irq(s->irq, irq);
606
+}
607
+
608
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
609
+ uint32_t bytes)
610
+{
611
+ if (s->transfer_cnt > bytes) {
612
+ s->transfer_cnt -= bytes;
613
+ } else {
614
+ s->transfer_cnt = 0;
615
+ }
616
+
617
+ if (!s->transfer_cnt) {
618
+ s->irq_status |= SD_RISR_DATA_COMPLETE;
619
+ }
620
+}
621
+
622
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
623
+{
624
+ AwSdHostState *s = AW_SDHOST(dev);
625
+
626
+ trace_allwinner_sdhost_set_inserted(inserted);
627
+
628
+ if (inserted) {
629
+ s->irq_status |= SD_RISR_CARD_INSERT;
630
+ s->irq_status &= ~SD_RISR_CARD_REMOVE;
631
+ s->status |= SD_STAR_CARD_PRESENT;
632
+ } else {
633
+ s->irq_status &= ~SD_RISR_CARD_INSERT;
634
+ s->irq_status |= SD_RISR_CARD_REMOVE;
635
+ s->status &= ~SD_STAR_CARD_PRESENT;
636
+ }
637
+
638
+ allwinner_sdhost_update_irq(s);
639
+}
640
+
641
+static void allwinner_sdhost_send_command(AwSdHostState *s)
642
+{
643
+ SDRequest request;
644
+ uint8_t resp[16];
645
+ int rlen;
646
+
647
+ /* Auto clear load flag */
648
+ s->command &= ~SD_CMDR_LOAD;
649
+
650
+ /* Clock change does not actually interact with the SD bus */
651
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
652
+
653
+ /* Prepare request */
654
+ request.cmd = s->command & SD_CMDR_CMDID_MASK;
655
+ request.arg = s->command_arg;
656
+
657
+ /* Send request to SD bus */
658
+ rlen = sdbus_do_command(&s->sdbus, &request, resp);
659
+ if (rlen < 0) {
660
+ goto error;
661
+ }
662
+
663
+ /* If the command has a response, store it in the response registers */
664
+ if ((s->command & SD_CMDR_RESPONSE)) {
665
+ if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
666
+ s->response[0] = ldl_be_p(&resp[0]);
667
+ s->response[1] = s->response[2] = s->response[3] = 0;
668
+
669
+ } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
670
+ s->response[0] = ldl_be_p(&resp[12]);
671
+ s->response[1] = ldl_be_p(&resp[8]);
672
+ s->response[2] = ldl_be_p(&resp[4]);
673
+ s->response[3] = ldl_be_p(&resp[0]);
674
+ } else {
675
+ goto error;
676
+ }
677
+ }
678
+ }
679
+
680
+ /* Set interrupt status bits */
681
+ s->irq_status |= SD_RISR_CMD_COMPLETE;
682
+ return;
683
+
684
+error:
685
+ s->irq_status |= SD_RISR_NO_RESPONSE;
686
+}
687
+
688
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
689
+{
690
+ /*
691
+ * The stop command (CMD12) ensures the SD bus
692
+ * returns to the transfer state.
693
+ */
694
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
695
+ /* First save current command registers */
696
+ uint32_t saved_cmd = s->command;
697
+ uint32_t saved_arg = s->command_arg;
698
+
699
+ /* Prepare stop command (CMD12) */
700
+ s->command &= ~SD_CMDR_CMDID_MASK;
701
+ s->command |= 12; /* CMD12 */
702
+ s->command_arg = 0;
703
+
704
+ /* Put the command on SD bus */
705
+ allwinner_sdhost_send_command(s);
706
+
707
+ /* Restore command values */
708
+ s->command = saved_cmd;
709
+ s->command_arg = saved_arg;
710
+
711
+ /* Set IRQ status bit for automatic stop done */
712
+ s->irq_status |= SD_RISR_AUTOCMD_DONE;
713
+ }
714
+}
715
+
716
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
717
+ hwaddr desc_addr,
718
+ TransferDescriptor *desc,
719
+ bool is_write, uint32_t max_bytes)
720
+{
721
+ AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
722
+ uint32_t num_done = 0;
723
+ uint32_t num_bytes = max_bytes;
724
+ uint8_t buf[1024];
725
+
726
+ /* Read descriptor */
727
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
728
+ if (desc->size == 0) {
729
+ desc->size = klass->max_desc_size;
730
+ } else if (desc->size > klass->max_desc_size) {
731
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
732
+ " is out-of-bounds: %" PRIu32 " > %zu",
733
+ __func__, desc->size, klass->max_desc_size);
734
+ desc->size = klass->max_desc_size;
735
+ }
736
+ if (desc->size < num_bytes) {
737
+ num_bytes = desc->size;
738
+ }
739
+
740
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
741
+ is_write, max_bytes);
742
+
743
+ while (num_done < num_bytes) {
744
+ /* Try to completely fill the local buffer */
745
+ uint32_t buf_bytes = num_bytes - num_done;
746
+ if (buf_bytes > sizeof(buf)) {
747
+ buf_bytes = sizeof(buf);
748
+ }
749
+
750
+ /* Write to SD bus */
751
+ if (is_write) {
752
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
753
+ buf, buf_bytes);
754
+
755
+ for (uint32_t i = 0; i < buf_bytes; i++) {
756
+ sdbus_write_data(&s->sdbus, buf[i]);
757
+ }
758
+
759
+ /* Read from SD bus */
760
+ } else {
761
+ for (uint32_t i = 0; i < buf_bytes; i++) {
762
+ buf[i] = sdbus_read_data(&s->sdbus);
763
+ }
764
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
765
+ buf, buf_bytes);
766
+ }
767
+ num_done += buf_bytes;
768
+ }
769
+
770
+ /* Clear hold flag and flush descriptor */
771
+ desc->status &= ~DESC_STATUS_HOLD;
772
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
773
+
774
+ return num_done;
775
+}
776
+
777
+static void allwinner_sdhost_dma(AwSdHostState *s)
778
+{
779
+ TransferDescriptor desc;
780
+ hwaddr desc_addr = s->desc_base;
781
+ bool is_write = (s->command & SD_CMDR_WRITE);
782
+ uint32_t bytes_done = 0;
783
+
784
+ /* Check if DMA can be performed */
785
+ if (s->byte_count == 0 || s->block_size == 0 ||
786
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
787
+ return;
788
+ }
789
+
790
+ /*
791
+ * For read operations, data must be available on the SD bus
792
+ * If not, it is an error and we should not act at all
793
+ */
794
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
795
+ return;
796
+ }
797
+
798
+ /* Process the DMA descriptors until all data is copied */
799
+ while (s->byte_count > 0) {
800
+ bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
801
+ is_write, s->byte_count);
802
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
803
+
804
+ if (bytes_done <= s->byte_count) {
805
+ s->byte_count -= bytes_done;
806
+ } else {
807
+ s->byte_count = 0;
808
+ }
809
+
810
+ if (desc.status & DESC_STATUS_LAST) {
811
+ break;
812
+ } else {
813
+ desc_addr = desc.next;
814
+ }
815
+ }
816
+
817
+ /* Raise IRQ to signal DMA is completed */
818
+ s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
819
+
820
+ /* Update DMAC bits */
821
+ s->dmac_status |= SD_IDST_INT_SUMMARY;
822
+
823
+ if (is_write) {
824
+ s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
825
+ } else {
826
+ s->dmac_status |= SD_IDST_RECEIVE_IRQ;
827
+ }
828
+}
829
+
830
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
831
+ unsigned size)
832
+{
833
+ AwSdHostState *s = AW_SDHOST(opaque);
834
+ uint32_t res = 0;
835
+
836
+ switch (offset) {
837
+ case REG_SD_GCTL: /* Global Control */
838
+ res = s->global_ctl;
839
+ break;
840
+ case REG_SD_CKCR: /* Clock Control */
841
+ res = s->clock_ctl;
842
+ break;
843
+ case REG_SD_TMOR: /* Timeout */
844
+ res = s->timeout;
845
+ break;
846
+ case REG_SD_BWDR: /* Bus Width */
847
+ res = s->bus_width;
848
+ break;
849
+ case REG_SD_BKSR: /* Block Size */
850
+ res = s->block_size;
851
+ break;
852
+ case REG_SD_BYCR: /* Byte Count */
853
+ res = s->byte_count;
854
+ break;
855
+ case REG_SD_CMDR: /* Command */
856
+ res = s->command;
857
+ break;
858
+ case REG_SD_CAGR: /* Command Argument */
859
+ res = s->command_arg;
860
+ break;
861
+ case REG_SD_RESP0: /* Response Zero */
862
+ res = s->response[0];
863
+ break;
864
+ case REG_SD_RESP1: /* Response One */
865
+ res = s->response[1];
866
+ break;
867
+ case REG_SD_RESP2: /* Response Two */
868
+ res = s->response[2];
869
+ break;
870
+ case REG_SD_RESP3: /* Response Three */
871
+ res = s->response[3];
872
+ break;
873
+ case REG_SD_IMKR: /* Interrupt Mask */
874
+ res = s->irq_mask;
875
+ break;
876
+ case REG_SD_MISR: /* Masked Interrupt Status */
877
+ res = s->irq_status & s->irq_mask;
878
+ break;
879
+ case REG_SD_RISR: /* Raw Interrupt Status */
880
+ res = s->irq_status;
881
+ break;
882
+ case REG_SD_STAR: /* Status */
883
+ res = s->status;
884
+ break;
885
+ case REG_SD_FWLR: /* FIFO Water Level */
886
+ res = s->fifo_wlevel;
887
+ break;
888
+ case REG_SD_FUNS: /* FIFO Function Select */
889
+ res = s->fifo_func_sel;
890
+ break;
891
+ case REG_SD_DBGC: /* Debug Enable */
892
+ res = s->debug_enable;
893
+ break;
894
+ case REG_SD_A12A: /* Auto command 12 argument */
895
+ res = s->auto12_arg;
896
+ break;
897
+ case REG_SD_NTSR: /* SD NewTiming Set */
898
+ res = s->newtiming_set;
899
+ break;
900
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
901
+ res = s->newtiming_debug;
902
+ break;
903
+ case REG_SD_HWRST: /* Hardware Reset Register */
904
+ res = s->hardware_rst;
905
+ break;
906
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
907
+ res = s->dmac;
908
+ break;
909
+ case REG_SD_DLBA: /* Descriptor List Base Address */
910
+ res = s->desc_base;
911
+ break;
912
+ case REG_SD_IDST: /* Internal DMA Controller Status */
913
+ res = s->dmac_status;
914
+ break;
915
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
916
+ res = s->dmac_irq;
917
+ break;
918
+ case REG_SD_THLDC: /* Card Threshold Control */
919
+ res = s->card_threshold;
920
+ break;
921
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
922
+ res = s->startbit_detect;
923
+ break;
924
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
925
+ res = s->response_crc;
926
+ break;
927
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
928
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
929
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
930
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
931
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
932
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
933
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
934
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
935
+ res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
936
+ break;
937
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
938
+ res = s->status_crc;
939
+ break;
940
+ case REG_SD_FIFO: /* Read/Write FIFO */
941
+ if (sdbus_data_ready(&s->sdbus)) {
942
+ res = sdbus_read_data(&s->sdbus);
943
+ res |= sdbus_read_data(&s->sdbus) << 8;
944
+ res |= sdbus_read_data(&s->sdbus) << 16;
945
+ res |= sdbus_read_data(&s->sdbus) << 24;
946
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
947
+ allwinner_sdhost_auto_stop(s);
948
+ allwinner_sdhost_update_irq(s);
949
+ } else {
950
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
951
+ __func__);
952
+ }
953
+ break;
954
+ default:
955
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
956
+ HWADDR_PRIx"\n", __func__, offset);
957
+ res = 0;
958
+ break;
959
+ }
960
+
961
+ trace_allwinner_sdhost_read(offset, res, size);
962
+ return res;
963
+}
964
+
965
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
966
+ uint64_t value, unsigned size)
967
+{
968
+ AwSdHostState *s = AW_SDHOST(opaque);
969
+
970
+ trace_allwinner_sdhost_write(offset, value, size);
971
+
972
+ switch (offset) {
973
+ case REG_SD_GCTL: /* Global Control */
974
+ s->global_ctl = value;
975
+ s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
976
+ SD_GCTL_SOFT_RST);
977
+ allwinner_sdhost_update_irq(s);
978
+ break;
979
+ case REG_SD_CKCR: /* Clock Control */
980
+ s->clock_ctl = value;
981
+ break;
982
+ case REG_SD_TMOR: /* Timeout */
983
+ s->timeout = value;
984
+ break;
985
+ case REG_SD_BWDR: /* Bus Width */
986
+ s->bus_width = value;
987
+ break;
988
+ case REG_SD_BKSR: /* Block Size */
989
+ s->block_size = value;
990
+ break;
991
+ case REG_SD_BYCR: /* Byte Count */
992
+ s->byte_count = value;
993
+ s->transfer_cnt = value;
994
+ break;
995
+ case REG_SD_CMDR: /* Command */
996
+ s->command = value;
997
+ if (value & SD_CMDR_LOAD) {
998
+ allwinner_sdhost_send_command(s);
999
+ allwinner_sdhost_dma(s);
1000
+ allwinner_sdhost_auto_stop(s);
1001
+ }
1002
+ allwinner_sdhost_update_irq(s);
1003
+ break;
1004
+ case REG_SD_CAGR: /* Command Argument */
1005
+ s->command_arg = value;
1006
+ break;
1007
+ case REG_SD_RESP0: /* Response Zero */
1008
+ s->response[0] = value;
1009
+ break;
1010
+ case REG_SD_RESP1: /* Response One */
1011
+ s->response[1] = value;
1012
+ break;
1013
+ case REG_SD_RESP2: /* Response Two */
1014
+ s->response[2] = value;
1015
+ break;
1016
+ case REG_SD_RESP3: /* Response Three */
1017
+ s->response[3] = value;
1018
+ break;
1019
+ case REG_SD_IMKR: /* Interrupt Mask */
1020
+ s->irq_mask = value;
1021
+ allwinner_sdhost_update_irq(s);
1022
+ break;
1023
+ case REG_SD_MISR: /* Masked Interrupt Status */
1024
+ case REG_SD_RISR: /* Raw Interrupt Status */
1025
+ s->irq_status &= ~value;
1026
+ allwinner_sdhost_update_irq(s);
1027
+ break;
1028
+ case REG_SD_STAR: /* Status */
1029
+ s->status &= ~value;
1030
+ allwinner_sdhost_update_irq(s);
1031
+ break;
1032
+ case REG_SD_FWLR: /* FIFO Water Level */
1033
+ s->fifo_wlevel = value;
1034
+ break;
1035
+ case REG_SD_FUNS: /* FIFO Function Select */
1036
+ s->fifo_func_sel = value;
1037
+ break;
1038
+ case REG_SD_DBGC: /* Debug Enable */
1039
+ s->debug_enable = value;
1040
+ break;
1041
+ case REG_SD_A12A: /* Auto command 12 argument */
1042
+ s->auto12_arg = value;
1043
+ break;
1044
+ case REG_SD_NTSR: /* SD NewTiming Set */
1045
+ s->newtiming_set = value;
1046
+ break;
1047
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
1048
+ s->newtiming_debug = value;
1049
+ break;
1050
+ case REG_SD_HWRST: /* Hardware Reset Register */
1051
+ s->hardware_rst = value;
1052
+ break;
1053
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
1054
+ s->dmac = value;
1055
+ allwinner_sdhost_update_irq(s);
1056
+ break;
1057
+ case REG_SD_DLBA: /* Descriptor List Base Address */
1058
+ s->desc_base = value;
1059
+ break;
1060
+ case REG_SD_IDST: /* Internal DMA Controller Status */
1061
+ s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
1062
+ allwinner_sdhost_update_irq(s);
1063
+ break;
1064
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
1065
+ s->dmac_irq = value;
1066
+ allwinner_sdhost_update_irq(s);
1067
+ break;
1068
+ case REG_SD_THLDC: /* Card Threshold Control */
1069
+ s->card_threshold = value;
1070
+ break;
1071
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
1072
+ s->startbit_detect = value;
1073
+ break;
1074
+ case REG_SD_FIFO: /* Read/Write FIFO */
1075
+ sdbus_write_data(&s->sdbus, value & 0xff);
1076
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
1077
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
1078
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
1079
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
1080
+ allwinner_sdhost_auto_stop(s);
1081
+ allwinner_sdhost_update_irq(s);
1082
+ break;
1083
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
1084
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
1085
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
1086
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
1087
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
1088
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
1089
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
1090
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
1091
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
1092
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
1093
+ break;
1094
+ default:
1095
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
1096
+ HWADDR_PRIx"\n", __func__, offset);
1097
+ break;
1098
+ }
1099
+}
1100
+
1101
+static const MemoryRegionOps allwinner_sdhost_ops = {
1102
+ .read = allwinner_sdhost_read,
1103
+ .write = allwinner_sdhost_write,
1104
+ .endianness = DEVICE_NATIVE_ENDIAN,
1105
+ .valid = {
1106
+ .min_access_size = 4,
1107
+ .max_access_size = 4,
1108
+ },
1109
+ .impl.min_access_size = 4,
1110
+};
1111
+
1112
+static const VMStateDescription vmstate_allwinner_sdhost = {
1113
+ .name = "allwinner-sdhost",
1114
+ .version_id = 1,
1115
+ .minimum_version_id = 1,
1116
+ .fields = (VMStateField[]) {
1117
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
1118
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
1119
+ VMSTATE_UINT32(timeout, AwSdHostState),
1120
+ VMSTATE_UINT32(bus_width, AwSdHostState),
1121
+ VMSTATE_UINT32(block_size, AwSdHostState),
1122
+ VMSTATE_UINT32(byte_count, AwSdHostState),
1123
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
1124
+ VMSTATE_UINT32(command, AwSdHostState),
1125
+ VMSTATE_UINT32(command_arg, AwSdHostState),
1126
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
1127
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
1128
+ VMSTATE_UINT32(irq_status, AwSdHostState),
1129
+ VMSTATE_UINT32(status, AwSdHostState),
1130
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
1131
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
1132
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
1133
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
1134
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
1135
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
1136
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
1137
+ VMSTATE_UINT32(dmac, AwSdHostState),
1138
+ VMSTATE_UINT32(desc_base, AwSdHostState),
1139
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
1140
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
1141
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
1142
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
1143
+ VMSTATE_UINT32(response_crc, AwSdHostState),
1144
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
1145
+ VMSTATE_UINT32(status_crc, AwSdHostState),
1146
+ VMSTATE_END_OF_LIST()
1147
+ }
1148
+};
1149
+
1150
+static void allwinner_sdhost_init(Object *obj)
1151
+{
1152
+ AwSdHostState *s = AW_SDHOST(obj);
1153
+
1154
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1155
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
1156
+
1157
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
1158
+ TYPE_AW_SDHOST, 4 * KiB);
1159
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
1160
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
1161
+}
1162
+
1163
+static void allwinner_sdhost_reset(DeviceState *dev)
1164
+{
1165
+ AwSdHostState *s = AW_SDHOST(dev);
1166
+
1167
+ s->global_ctl = REG_SD_GCTL_RST;
1168
+ s->clock_ctl = REG_SD_CKCR_RST;
1169
+ s->timeout = REG_SD_TMOR_RST;
1170
+ s->bus_width = REG_SD_BWDR_RST;
1171
+ s->block_size = REG_SD_BKSR_RST;
1172
+ s->byte_count = REG_SD_BYCR_RST;
1173
+ s->transfer_cnt = 0;
1174
+
1175
+ s->command = REG_SD_CMDR_RST;
1176
+ s->command_arg = REG_SD_CAGR_RST;
1177
+
1178
+ for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
1179
+ s->response[i] = REG_SD_RESP_RST;
1180
+ }
1181
+
1182
+ s->irq_mask = REG_SD_IMKR_RST;
1183
+ s->irq_status = REG_SD_RISR_RST;
1184
+ s->status = REG_SD_STAR_RST;
1185
+
1186
+ s->fifo_wlevel = REG_SD_FWLR_RST;
1187
+ s->fifo_func_sel = REG_SD_FUNS_RST;
1188
+ s->debug_enable = REG_SD_DBGC_RST;
1189
+ s->auto12_arg = REG_SD_A12A_RST;
1190
+ s->newtiming_set = REG_SD_NTSR_RST;
1191
+ s->newtiming_debug = REG_SD_SDBG_RST;
1192
+ s->hardware_rst = REG_SD_HWRST_RST;
1193
+ s->dmac = REG_SD_DMAC_RST;
1194
+ s->desc_base = REG_SD_DLBA_RST;
1195
+ s->dmac_status = REG_SD_IDST_RST;
1196
+ s->dmac_irq = REG_SD_IDIE_RST;
1197
+ s->card_threshold = REG_SD_THLDC_RST;
1198
+ s->startbit_detect = REG_SD_DSBD_RST;
1199
+ s->response_crc = REG_SD_RES_CRC_RST;
1200
+
1201
+ for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
1202
+ s->data_crc[i] = REG_SD_DATA_CRC_RST;
1203
+ }
1204
+
1205
+ s->status_crc = REG_SD_CRC_STA_RST;
1206
+}
1207
+
1208
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
1209
+{
1210
+ SDBusClass *sbc = SD_BUS_CLASS(klass);
1211
+
1212
+ sbc->set_inserted = allwinner_sdhost_set_inserted;
1213
+}
1214
+
1215
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
1216
+{
1217
+ DeviceClass *dc = DEVICE_CLASS(klass);
1218
+
1219
+ dc->reset = allwinner_sdhost_reset;
1220
+ dc->vmsd = &vmstate_allwinner_sdhost;
1221
+}
1222
+
1223
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
1224
+{
1225
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1226
+ sc->max_desc_size = 8 * KiB;
1227
+}
1228
+
1229
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
1230
+{
1231
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1232
+ sc->max_desc_size = 64 * KiB;
1233
+}
1234
+
1235
+static TypeInfo allwinner_sdhost_info = {
1236
+ .name = TYPE_AW_SDHOST,
1237
+ .parent = TYPE_SYS_BUS_DEVICE,
1238
+ .instance_init = allwinner_sdhost_init,
1239
+ .instance_size = sizeof(AwSdHostState),
1240
+ .class_init = allwinner_sdhost_class_init,
1241
+ .class_size = sizeof(AwSdHostClass),
1242
+ .abstract = true,
1243
+};
1244
+
1245
+static const TypeInfo allwinner_sdhost_sun4i_info = {
1246
+ .name = TYPE_AW_SDHOST_SUN4I,
1247
+ .parent = TYPE_AW_SDHOST,
1248
+ .class_init = allwinner_sdhost_sun4i_class_init,
1249
+};
1250
+
1251
+static const TypeInfo allwinner_sdhost_sun5i_info = {
1252
+ .name = TYPE_AW_SDHOST_SUN5I,
1253
+ .parent = TYPE_AW_SDHOST,
1254
+ .class_init = allwinner_sdhost_sun5i_class_init,
1255
+};
1256
+
1257
+static const TypeInfo allwinner_sdhost_bus_info = {
1258
+ .name = TYPE_AW_SDHOST_BUS,
1259
+ .parent = TYPE_SD_BUS,
1260
+ .instance_size = sizeof(SDBus),
1261
+ .class_init = allwinner_sdhost_bus_class_init,
1262
+};
1263
+
1264
+static void allwinner_sdhost_register_types(void)
1265
+{
1266
+ type_register_static(&allwinner_sdhost_info);
1267
+ type_register_static(&allwinner_sdhost_sun4i_info);
1268
+ type_register_static(&allwinner_sdhost_sun5i_info);
1269
+ type_register_static(&allwinner_sdhost_bus_info);
1270
+}
1271
+
1272
+type_init(allwinner_sdhost_register_types)
1273
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1274
index XXXXXXX..XXXXXXX 100644
158
index XXXXXXX..XXXXXXX 100644
1275
--- a/hw/arm/Kconfig
159
--- a/hw/ide/via.c
1276
+++ b/hw/arm/Kconfig
160
+++ b/hw/ide/via.c
1277
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
161
@@ -XXX,XX +XXX,XX @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
1278
select UNIMP
162
1279
select USB_OHCI
163
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
1280
select USB_EHCI_SYSBUS
164
for (i = 0; i < 2; i++) {
1281
+ select SD
165
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
1282
166
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
1283
config RASPI
167
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
1284
bool
168
1285
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
169
bmdma_init(&d->bus[i], &d->bmdma[i], d);
1286
index XXXXXXX..XXXXXXX 100644
1287
--- a/hw/sd/trace-events
1288
+++ b/hw/sd/trace-events
1289
@@ -XXX,XX +XXX,XX @@
1290
# See docs/devel/tracing.txt for syntax documentation.
1291
1292
+# allwinner-sdhost.c
1293
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
1294
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32
1295
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1296
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1297
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
1298
+
1299
# bcm2835_sdhost.c
1300
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1301
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1302
--
170
--
1303
2.20.1
171
2.20.1
1304
172
1305
173
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots a Linux kernel on a OrangePi PC board and verify
4
the serial output is working.
5
6
The kernel image and DeviceTree blob are built by the Armbian
7
project (based on Debian):
8
https://www.armbian.com/orange-pi-pc/
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ make check-venv
16
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
17
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
18
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
19
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
20
console: Uncompressing Linux... done, booting the kernel.
21
console: Booting Linux on physical CPU 0x0
22
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
23
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
24
console: CPU: div instructions available: patching division code
25
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
26
console: OF: fdt: Machine model: Xunlong Orange Pi PC
27
console: Memory policy: Data cache writealloc
28
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
29
console: cma: Failed to reserve 128 MiB
30
console: psci: probing for conduit method from DT.
31
console: psci: PSCIv0.2 detected in firmware.
32
console: psci: Using standard PSCI v0.2 function IDs
33
console: psci: Trusted OS migration not required
34
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
35
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
36
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
37
console: Kernel command line: printk.time=0 console=ttyS0,115200
38
PASS (8.59 s)
39
JOB TIME : 8.81 s
40
41
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
42
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
43
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
44
Tested-by: Alex Bennée <alex.bennee@linaro.org>
45
Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com
46
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
49
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
50
1 file changed, 25 insertions(+)
51
52
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tests/acceptance/boot_linux_console.py
55
+++ b/tests/acceptance/boot_linux_console.py
56
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
57
exec_command_and_wait_for_pattern(self, 'reboot',
58
'reboot: Restarting system')
59
60
+ def test_arm_orangepi(self):
61
+ """
62
+ :avocado: tags=arch:arm
63
+ :avocado: tags=machine:orangepi-pc
64
+ """
65
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
66
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
67
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
68
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
69
+ kernel_path = self.extract_from_deb(deb_path,
70
+ '/boot/vmlinuz-4.20.7-sunxi')
71
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
72
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
73
+
74
+ self.vm.set_console()
75
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
76
+ 'console=ttyS0,115200n8 '
77
+ 'earlycon=uart,mmio32,0x1c28000')
78
+ self.vm.add_args('-kernel', kernel_path,
79
+ '-dtb', dtb_path,
80
+ '-append', kernel_command_line)
81
+ self.vm.launch()
82
+ console_pattern = 'Kernel command line: %s' % kernel_command_line
83
+ self.wait_for_console_pattern(console_pattern)
84
+
85
def test_s390x_s390_ccw_virtio(self):
86
"""
87
:avocado: tags=arch:s390x
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots a Linux kernel on a OrangePi PC board and verify
4
the serial output is working.
5
6
The kernel image and DeviceTree blob are built by the Armbian
7
project (based on Debian):
8
https://www.armbian.com/orange-pi-pc/
9
10
The cpio image used comes from the linux-build-test project:
11
https://github.com/groeck/linux-build-test
12
13
If ARM is a target being built, "make check-acceptance" will
14
automatically include this test by the use of the "arch:arm" tags.
15
16
Alternatively, this test can be run using:
17
18
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
19
console: Uncompressing Linux... done, booting the kernel.
20
console: Booting Linux on physical CPU 0x0
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
23
console: CPU: div instructions available: patching division code
24
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
25
console: OF: fdt: Machine model: Xunlong Orange Pi PC
26
[...]
27
console: Trying to unpack rootfs image as initramfs...
28
console: Freeing initrd memory: 3256K
29
console: Freeing unused kernel memory: 1024K
30
console: Run /init as init process
31
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
32
console: Starting logging: OK
33
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
34
console: done.
35
console: Starting network: OK
36
console: Found console ttyS0
37
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
38
console: Boot successful.
39
console: cat /proc/cpuinfo
40
console: / # cat /proc/cpuinfo
41
console: processor : 0
42
console: model name : ARMv7 Processor rev 5 (v7l)
43
console: BogoMIPS : 125.00
44
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
45
console: CPU implementer : 0x41
46
console: CPU architecture: 7
47
console: CPU variant : 0x0
48
console: CPU part : 0xc07
49
console: CPU revision : 5
50
[...]
51
console: processor : 3
52
console: model name : ARMv7 Processor rev 5 (v7l)
53
console: BogoMIPS : 125.00
54
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
55
console: CPU implementer : 0x41
56
console: CPU architecture: 7
57
console: CPU variant : 0x0
58
console: CPU part : 0xc07
59
console: CPU revision : 5
60
console: Hardware : Allwinner sun8i Family
61
console: Revision : 0000
62
console: Serial : 0000000000000000
63
console: cat /proc/iomem
64
console: / # cat /proc/iomem
65
console: 01000000-010fffff : clock@1000000
66
console: 01c00000-01c00fff : system-control@1c00000
67
console: 01c02000-01c02fff : dma-controller@1c02000
68
[...]
69
console: reboot
70
console: / # reboot
71
console: / # Found console ttyS0
72
console: Stopping network: OK
73
console: hrtimer: interrupt took 21852064 ns
74
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
75
console: done.
76
console: Stopping logging: OK
77
console: umount: devtmpfs busy - remounted read-only
78
console: umount: can't unmount /: Invalid argument
79
console: The system is going down NOW!
80
console: Sent SIGTERM to all processes
81
console: Sent SIGKILL to all processes
82
console: Requesting system reboot
83
console: reboot: Restarting system
84
PASS (48.32 s)
85
JOB TIME : 49.16 s
86
87
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
88
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
89
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
90
Tested-by: Alex Bennée <alex.bennee@linaro.org>
91
Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com
92
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
93
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94
---
95
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
96
1 file changed, 40 insertions(+)
97
98
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
99
index XXXXXXX..XXXXXXX 100644
100
--- a/tests/acceptance/boot_linux_console.py
101
+++ b/tests/acceptance/boot_linux_console.py
102
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
103
console_pattern = 'Kernel command line: %s' % kernel_command_line
104
self.wait_for_console_pattern(console_pattern)
105
106
+ def test_arm_orangepi_initrd(self):
107
+ """
108
+ :avocado: tags=arch:arm
109
+ :avocado: tags=machine:orangepi-pc
110
+ """
111
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
112
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
113
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
114
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
115
+ kernel_path = self.extract_from_deb(deb_path,
116
+ '/boot/vmlinuz-4.20.7-sunxi')
117
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
118
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
119
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
120
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
121
+ 'arm/rootfs-armv7a.cpio.gz')
122
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
123
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
124
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
125
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
126
+
127
+ self.vm.set_console()
128
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
129
+ 'console=ttyS0,115200 '
130
+ 'panic=-1 noreboot')
131
+ self.vm.add_args('-kernel', kernel_path,
132
+ '-dtb', dtb_path,
133
+ '-initrd', initrd_path,
134
+ '-append', kernel_command_line,
135
+ '-no-reboot')
136
+ self.vm.launch()
137
+ self.wait_for_console_pattern('Boot successful.')
138
+
139
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
140
+ 'Allwinner sun8i Family')
141
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
142
+ 'system-control@1c00000')
143
+ exec_command_and_wait_for_pattern(self, 'reboot',
144
+ 'reboot: Restarting system')
145
+
146
def test_s390x_s390_ccw_virtio(self):
147
"""
148
:avocado: tags=arch:s390x
149
--
150
2.20.1
151
152
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The kernel image and DeviceTree blob are built by the Armbian
4
project (based on Debian):
5
https://www.armbian.com/orange-pi-pc/
6
7
The SD image is from the kernelci.org project:
8
https://kernelci.org/faq/#the-code
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
16
console: Uncompressing Linux... done, booting the kernel.
17
console: Booting Linux on physical CPU 0x0
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
19
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
20
[...]
21
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
22
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
23
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
24
console: ledtrig-cpu: registered to indicate activity on CPUs
25
console: hidraw: raw HID events driver (C) Jiri Kosina
26
console: usbcore: registered new interface driver usbhid
27
console: usbhid: USB HID core driver
28
console: Initializing XFRM netlink socket
29
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
30
console: NET: Registered protocol family 10
31
console: mmc0: host does not support reading read-only switch, assuming write-enable
32
console: mmc0: Problem switching card into high-speed mode!
33
console: mmc0: new SD card at address 4567
34
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
35
[...]
36
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
37
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
38
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
39
console: Run /sbin/init as init process
40
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
41
console: Starting syslogd: OK
42
console: Starting klogd: OK
43
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
44
console: /bin/sh: can't access tty; job control turned off
45
console: cat /proc/partitions
46
console: / # cat /proc/partitions
47
console: major minor #blocks name
48
console: 1 0 4096 ram0
49
console: 1 1 4096 ram1
50
console: 1 2 4096 ram2
51
console: 1 3 4096 ram3
52
console: 179 0 61440 mmcblk0
53
console: reboot
54
console: / # reboot
55
console: umount: devtmpfs busy - remounted read-only
56
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
57
console: The system is going down NOW!
58
console: Sent SIGTERM to all processes
59
console: Sent SIGKILL to all processes
60
console: Requesting system reboot
61
console: reboot: Restarting system
62
JOB TIME : 68.64 s
63
64
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
65
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
66
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
67
Tested-by: Alex Bennée <alex.bennee@linaro.org>
68
Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com
69
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
70
[NL: extend test with ethernet device checks]
71
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
72
---
73
tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++
74
1 file changed, 47 insertions(+)
75
76
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
77
index XXXXXXX..XXXXXXX 100644
78
--- a/tests/acceptance/boot_linux_console.py
79
+++ b/tests/acceptance/boot_linux_console.py
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
81
exec_command_and_wait_for_pattern(self, 'reboot',
82
'reboot: Restarting system')
83
84
+ def test_arm_orangepi_sd(self):
85
+ """
86
+ :avocado: tags=arch:arm
87
+ :avocado: tags=machine:orangepi-pc
88
+ """
89
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
90
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
91
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
92
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
93
+ kernel_path = self.extract_from_deb(deb_path,
94
+ '/boot/vmlinuz-4.20.7-sunxi')
95
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
96
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
97
+ rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
98
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
99
+ rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061'
100
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
101
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
102
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
103
+
104
+ self.vm.set_console()
105
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
106
+ 'console=ttyS0,115200 '
107
+ 'root=/dev/mmcblk0 rootwait rw '
108
+ 'panic=-1 noreboot')
109
+ self.vm.add_args('-kernel', kernel_path,
110
+ '-dtb', dtb_path,
111
+ '-drive', 'file=' + rootfs_path + ',if=sd,format=raw',
112
+ '-append', kernel_command_line,
113
+ '-no-reboot')
114
+ self.vm.launch()
115
+ shell_ready = "/bin/sh: can't access tty; job control turned off"
116
+ self.wait_for_console_pattern(shell_ready)
117
+
118
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
119
+ 'Allwinner sun8i Family')
120
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
121
+ 'mmcblk0')
122
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
123
+ 'eth0: Link is Up')
124
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
125
+ 'udhcpc: lease of 10.0.2.15 obtained')
126
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
127
+ '3 packets transmitted, 3 packets received, 0% packet loss')
128
+ exec_command_and_wait_for_pattern(self, 'reboot',
129
+ 'reboot: Restarting system')
130
+
131
def test_s390x_s390_ccw_virtio(self):
132
"""
133
:avocado: tags=arch:s390x
134
--
135
2.20.1
136
137
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots Ubuntu Bionic on a OrangePi PC board.
4
5
As it requires 1GB of storage, and is slow, this test is disabled
6
on automatic CI testing.
7
8
It is useful for workstation testing. Currently Avocado timeouts too
9
quickly, so we can't run userland commands.
10
11
The kernel image and DeviceTree blob are built by the Armbian
12
project (based on Debian):
13
https://www.armbian.com/orange-pi-pc/
14
15
The Ubuntu image is downloaded from:
16
https://dl.armbian.com/orangepipc/Bionic_current
17
18
This test can be run using:
19
20
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
21
avocado --show=app,console run -t machine:orangepi-pc \
22
tests/acceptance/boot_linux_console.py
23
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
24
console: DRAM: 1024 MiB
25
console: Failed to set core voltage! Can't set CPU frequency
26
console: Trying to boot from MMC1
27
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
28
console: CPU: Allwinner H3 (SUN8I 0000)
29
console: Model: Xunlong Orange Pi PC
30
console: DRAM: 1 GiB
31
console: MMC: mmc@1c0f000: 0
32
[...]
33
console: Uncompressing Linux... done, booting the kernel.
34
console: Booting Linux on physical CPU 0x0
35
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
36
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
37
console: CPU: div instructions available: patching division code
38
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
39
console: OF: fdt: Machine model: Xunlong Orange Pi PC
40
[...]
41
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
42
console: done.
43
console: Begin: Running /scripts/local-bottom ... done.
44
console: Begin: Running /scripts/init-bottom ... done.
45
console: systemd[1]: systemd 237 running in system mode. (...)
46
console: systemd[1]: Detected architecture arm.
47
console: Welcome to Ubuntu 18.04.3 LTS!
48
console: systemd[1]: Set hostname to <orangepipc>.
49
50
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
51
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
52
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
53
Tested-by: Alex Bennée <alex.bennee@linaro.org>
54
Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com
55
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
56
[NL: changed test to boot from SD card via BootROM, added check for 7z]
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
58
---
59
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
60
1 file changed, 48 insertions(+)
61
62
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tests/acceptance/boot_linux_console.py
65
+++ b/tests/acceptance/boot_linux_console.py
66
@@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern
67
from avocado_qemu import wait_for_console_pattern
68
from avocado.utils import process
69
from avocado.utils import archive
70
+from avocado.utils.path import find_command, CmdNotFoundError
71
72
+P7ZIP_AVAILABLE = True
73
+try:
74
+ find_command('7z')
75
+except CmdNotFoundError:
76
+ P7ZIP_AVAILABLE = False
77
78
class BootLinuxConsole(Test):
79
"""
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
81
exec_command_and_wait_for_pattern(self, 'reboot',
82
'reboot: Restarting system')
83
84
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
85
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
86
+ def test_arm_orangepi_bionic(self):
87
+ """
88
+ :avocado: tags=arch:arm
89
+ :avocado: tags=machine:orangepi-pc
90
+ """
91
+
92
+ # This test download a 196MB compressed image and expand it to 932MB...
93
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
94
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
95
+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
96
+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
97
+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
98
+ image_path = os.path.join(self.workdir, image_name)
99
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
100
+
101
+ self.vm.set_console()
102
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
103
+ '-nic', 'user',
104
+ '-no-reboot')
105
+ self.vm.launch()
106
+
107
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
108
+ 'console=ttyS0,115200 '
109
+ 'loglevel=7 '
110
+ 'nosmp '
111
+ 'systemd.default_timeout_start_sec=9000 '
112
+ 'systemd.mask=armbian-zram-config.service '
113
+ 'systemd.mask=armbian-ramlog.service')
114
+
115
+ self.wait_for_console_pattern('U-Boot SPL')
116
+ self.wait_for_console_pattern('Autoboot in ')
117
+ exec_command_and_wait_for_pattern(self, ' ', '=>')
118
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
119
+ kernel_command_line + "'", '=>')
120
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
121
+
122
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
123
+ 'to <orangepipc>')
124
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
125
+
126
def test_s390x_s390_ccw_virtio(self):
127
"""
128
:avocado: tags=arch:s390x
129
--
130
2.20.1
131
132
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots U-Boot then NetBSD (stored on a SD card) on
4
a OrangePi PC board.
5
6
As it requires ~1.3GB of storage, it is disabled by default.
7
8
U-Boot is built by the Debian project [1], and the SD card image
9
is provided by the NetBSD organization [2].
10
11
Once the compressed SD card image is downloaded (304MB) and
12
extracted, this test is fast:
13
14
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
15
avocado --show=app,console run -t machine:orangepi-pc \
16
tests/acceptance/boot_linux_console.py
17
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
18
console: DRAM: 1024 MiB
19
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
20
console: CPU: Allwinner H3 (SUN8I 0000)
21
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
22
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
23
console: scanning usb for storage devices... 0 Storage Device(s) found
24
console: Hit any key to stop autoboot: 0
25
console: => setenv bootargs root=ld0a
26
console: => setenv kernel netbsd-GENERIC.ub
27
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
28
console: => boot
29
console: ## Booting kernel from Legacy Image at 42000000 ...
30
console: Image Name: NetBSD/earmv7hf 9.0_RC1
31
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
32
console: XIP Kernel Image (no loading done)
33
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
34
console: Starting kernel ...
35
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
36
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
37
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
38
console: [ 1.0000000] total memory = 1024 MB
39
console: [ 1.0000000] avail memory = 1003 MB
40
console: [ 1.0000000] armfdt0 (root)
41
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
42
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
43
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
44
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
45
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
46
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
47
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
48
...
49
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
50
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
51
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors
52
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
53
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log.
54
console: [ 3.1179868] boot device: ld0
55
console: [ 3.1470623] root on ld0a dumps on ld0b
56
console: [ 3.2464436] root file system type: ffs
57
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
58
console: Mon Feb 17 20:33:35 UTC 2020
59
console: Starting root file system check:
60
PASS (35.96 s)
61
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
62
JOB TIME : 36.09 s
63
64
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
65
66
This test is based on a description from Niek Linnenbank from [4].
67
68
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
69
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
70
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
71
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
72
73
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
74
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
75
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
76
Tested-by: Alex Bennée <alex.bennee@linaro.org>
77
Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com
78
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
---
81
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
82
1 file changed, 70 insertions(+)
83
84
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
85
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/acceptance/boot_linux_console.py
87
+++ b/tests/acceptance/boot_linux_console.py
88
@@ -XXX,XX +XXX,XX @@ import shutil
89
from avocado import skipUnless
90
from avocado_qemu import Test
91
from avocado_qemu import exec_command_and_wait_for_pattern
92
+from avocado_qemu import interrupt_interactive_console_until_pattern
93
from avocado_qemu import wait_for_console_pattern
94
from avocado.utils import process
95
from avocado.utils import archive
96
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
97
'to <orangepipc>')
98
self.wait_for_console_pattern('Starting Load Kernel Modules...')
99
100
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
101
+ def test_arm_orangepi_uboot_netbsd9(self):
102
+ """
103
+ :avocado: tags=arch:arm
104
+ :avocado: tags=machine:orangepi-pc
105
+ """
106
+ # This test download a 304MB compressed image and expand it to 1.3GB...
107
+ deb_url = ('http://snapshot.debian.org/archive/debian/'
108
+ '20200108T145233Z/pool/main/u/u-boot/'
109
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
110
+ deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99'
111
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
112
+ # We use the common OrangePi PC 'plus' build of U-Boot for our secondary
113
+ # program loader (SPL). We will then set the path to the more specific
114
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt,
115
+ # before to boot NetBSD.
116
+ uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin'
117
+ uboot_path = self.extract_from_deb(deb_path, uboot_path)
118
+ image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
119
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
120
+ image_hash = '2babb29d36d8360adcb39c09e31060945259917a'
121
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
122
+ image_path = os.path.join(self.workdir, 'armv7.img')
123
+ image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path
124
+ archive.gzip_uncompress(image_path_gz, image_path)
125
+
126
+ # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc
127
+ with open(uboot_path, 'rb') as f_in:
128
+ with open(image_path, 'r+b') as f_out:
129
+ f_out.seek(8 * 1024)
130
+ shutil.copyfileobj(f_in, f_out)
131
+
132
+ # Extend image, to avoid that NetBSD thinks the partition
133
+ # inside the image is larger than device size itself
134
+ f_out.seek(0, 2)
135
+ f_out.seek(64 * 1024 * 1024, 1)
136
+ f_out.write(bytearray([0x00]))
137
+
138
+ self.vm.set_console()
139
+ self.vm.add_args('-nic', 'user',
140
+ '-drive', image_drive_args,
141
+ '-global', 'allwinner-rtc.base-year=2000',
142
+ '-no-reboot')
143
+ self.vm.launch()
144
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
145
+ interrupt_interactive_console_until_pattern(self,
146
+ 'Hit any key to stop autoboot:',
147
+ 'switch to partitions #0, OK')
148
+
149
+ exec_command_and_wait_for_pattern(self, '', '=>')
150
+ cmd = 'setenv bootargs root=ld0a'
151
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
152
+ cmd = 'setenv kernel netbsd-GENERIC.ub'
153
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
154
+ cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
155
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
156
+ cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; "
157
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
158
+ "fdt addr ${fdt_addr_r}; "
159
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
160
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
161
+
162
+ exec_command_and_wait_for_pattern(self, 'boot',
163
+ 'Booting kernel from Legacy Image')
164
+ wait_for_console_pattern(self, 'Starting kernel ...')
165
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
166
+ # Wait for user-space
167
+ wait_for_console_pattern(self, 'Starting root file system check')
168
+
169
def test_s390x_s390_ccw_virtio(self):
170
"""
171
:avocado: tags=arch:s390x
172
--
173
2.20.1
174
175
diff view generated by jsdifflib
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
Mention 'max' value in the gic-version property description.
4
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20200311131618.7187-2-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/virt.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
17
+++ b/hw/arm/virt.c
18
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
19
virt_set_gic_version, NULL);
20
object_property_set_description(obj, "gic-version",
21
"Set GIC version. "
22
- "Valid values are 2, 3 and host", NULL);
23
+ "Valid values are 2, 3, host and max",
24
+ NULL);
25
26
vms->highmem_ecam = !vmc->no_highmem_ecam;
27
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
2
2
3
We plan to introduce yet another value for the gic version (nosel).
3
The Linux spi-imx driver does not work on QEMU. The reason is that the
4
As we already use exotic values such as 0 and -1, let's introduce
4
state of m25p80 loops in STATE_READING_DATA state after receiving
5
a dedicated enum type and let vms->gic_version take this
5
RDSR command, the new command is ignored. Before sending a new command,
6
type.
6
CS line should be pulled high to make the state of m25p80 back to IDLE.
7
7
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Currently the SPI flash CS line is connected to the SPI controller, but
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
on the real board, it's connected to GPIO3_19. This matches the ecspi1
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
device node in the board dts.
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
11
12
Message-id: 20200311131618.7187-3-eric.auger@redhat.com
12
ecspi1 node in imx6qdl-sabrelite.dtsi:
13
&ecspi1 {
14
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
15
pinctrl-names = "default";
16
pinctrl-0 = <&pinctrl_ecspi1>;
17
status = "okay";
18
19
flash: m25p80@0 {
20
compatible = "sst,sst25vf016b", "jedec,spi-nor";
21
spi-max-frequency = <20000000>;
22
reg = <0>;
23
};
24
};
25
26
Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to
27
spi1 on sabrelite machine.
28
29
Verified this patch on Linux v5.14.
30
31
Logs:
32
# echo "01234567899876543210" > test
33
# mtd_debug erase /dev/mtd0 0x0 0x1000
34
Erased 4096 bytes from address 0x00000000 in flash
35
# mtd_debug write /dev/mtdblock0 0x0 20 test
36
Copied 20 bytes from test to address 0x00000000 in flash
37
# mtd_debug read /dev/mtdblock0 0x0 20 test_out
38
Copied 20 bytes from address 0x00000000 in flash to test_out
39
# cat test_out
40
01234567899876543210#
41
42
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
43
Reported-by: Guenter Roeck <linux@roeck-us.net>
44
Reviewed-by: Bin Meng <bin.meng@windriver.com>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Message-id: 20210927142825.491-1-xchengl.cn@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
48
---
15
include/hw/arm/virt.h | 11 +++++++++--
49
hw/arm/sabrelite.c | 2 +-
16
hw/arm/virt.c | 30 +++++++++++++++---------------
50
1 file changed, 1 insertion(+), 1 deletion(-)
17
2 files changed, 24 insertions(+), 17 deletions(-)
18
51
19
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
52
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
20
index XXXXXXX..XXXXXXX 100644
53
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/virt.h
54
--- a/hw/arm/sabrelite.c
22
+++ b/include/hw/arm/virt.h
55
+++ b/hw/arm/sabrelite.c
23
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
56
@@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine)
24
VIRT_IOMMU_VIRTIO,
57
qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
25
} VirtIOMMUType;
58
26
59
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
27
+typedef enum VirtGICType {
60
- sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
28
+ VIRT_GIC_VERSION_MAX,
61
+ qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line);
29
+ VIRT_GIC_VERSION_HOST,
62
}
30
+ VIRT_GIC_VERSION_2,
31
+ VIRT_GIC_VERSION_3,
32
+} VirtGICType;
33
+
34
typedef struct MemMapEntry {
35
hwaddr base;
36
hwaddr size;
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
bool highmem_ecam;
39
bool its;
40
bool virt;
41
- int32_t gic_version;
42
+ VirtGICType gic_version;
43
VirtIOMMUType iommu;
44
uint16_t virtio_iommu_bdf;
45
struct arm_boot_info bootinfo;
46
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
47
uint32_t redist0_capacity =
48
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
49
50
- assert(vms->gic_version == 3);
51
+ assert(vms->gic_version == VIRT_GIC_VERSION_3);
52
53
return vms->smp_cpus > redist0_capacity ? 2 : 1;
54
}
55
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/virt.c
58
+++ b/hw/arm/virt.c
59
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
60
irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
61
}
62
63
- if (vms->gic_version == 2) {
64
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
65
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
66
GIC_FDT_IRQ_PPI_CPU_WIDTH,
67
(1 << vms->smp_cpus) - 1);
68
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
70
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
71
qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
72
- if (vms->gic_version == 3) {
73
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
74
int nb_redist_regions = virt_gicv3_redist_region_count(vms);
75
76
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
77
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
78
}
63
}
79
}
64
}
80
81
- if (vms->gic_version == 2) {
82
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
83
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
84
GIC_FDT_IRQ_PPI_CPU_WIDTH,
85
(1 << vms->smp_cpus) - 1);
86
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
87
* purposes are to make TCG consistent (with 64-bit KVM hosts)
88
* and to improve SGI efficiency.
89
*/
90
- if (vms->gic_version == 3) {
91
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
92
clustersz = GICV3_TARGETLIST_BITS;
93
} else {
94
clustersz = GIC_TARGETLIST_BITS;
95
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
96
/* We can probe only here because during property set
97
* KVM is not available yet
98
*/
99
- if (vms->gic_version <= 0) {
100
- /* "host" or "max" */
101
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
102
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
103
if (!kvm_enabled()) {
104
- if (vms->gic_version == 0) {
105
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
106
error_report("gic-version=host requires KVM");
107
exit(1);
108
} else {
109
/* "max": currently means 3 for TCG */
110
- vms->gic_version = 3;
111
+ vms->gic_version = VIRT_GIC_VERSION_3;
112
}
113
} else {
114
vms->gic_version = kvm_arm_vgic_probe();
115
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
116
/* The maximum number of CPUs depends on the GIC version, or on how
117
* many redistributors we can fit into the memory map.
118
*/
119
- if (vms->gic_version == 3) {
120
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
121
virt_max_cpus =
122
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
123
virt_max_cpus +=
124
@@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp)
125
static char *virt_get_gic_version(Object *obj, Error **errp)
126
{
127
VirtMachineState *vms = VIRT_MACHINE(obj);
128
- const char *val = vms->gic_version == 3 ? "3" : "2";
129
+ const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
130
131
return g_strdup(val);
132
}
133
@@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
134
VirtMachineState *vms = VIRT_MACHINE(obj);
135
136
if (!strcmp(value, "3")) {
137
- vms->gic_version = 3;
138
+ vms->gic_version = VIRT_GIC_VERSION_3;
139
} else if (!strcmp(value, "2")) {
140
- vms->gic_version = 2;
141
+ vms->gic_version = VIRT_GIC_VERSION_2;
142
} else if (!strcmp(value, "host")) {
143
- vms->gic_version = 0; /* Will probe later */
144
+ vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
145
} else if (!strcmp(value, "max")) {
146
- vms->gic_version = -1; /* Will probe later */
147
+ vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
148
} else {
149
error_setg(errp, "Invalid gic-version value");
150
error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
151
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
152
"physical address space above 32 bits",
153
NULL);
154
/* Default GIC type is v2 */
155
- vms->gic_version = 2;
156
+ vms->gic_version = VIRT_GIC_VERSION_2;
157
object_property_add_str(obj, "gic-version", virt_get_gic_version,
158
virt_set_gic_version, NULL);
159
object_property_set_description(obj, "gic-version",
160
--
65
--
161
2.20.1
66
2.20.1
162
67
163
68
diff view generated by jsdifflib
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
At the moment if the end-user does not specify the gic-version along
4
with KVM acceleration, v2 is set by default. However most of the
5
systems now have GICv3 and sometimes they do not support GICv2
6
compatibility.
7
8
This patch keeps the default v2 selection in all cases except
9
in the KVM accelerated mode when either
10
- the host does not support GICv2 in-kernel emulation or
11
- number of VCPUS exceeds 8.
12
13
Those cases did not work anyway so we do not break any compatibility.
14
Now we get v3 selected in such a case.
15
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
18
Reviewed-by: Andrew Jones <drjones@redhat.com>
19
Message-id: 20200311131618.7187-7-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
hw/arm/virt.c | 17 ++++++++++++++++-
23
1 file changed, 16 insertions(+), 1 deletion(-)
24
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
28
+++ b/hw/arm/virt.c
29
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
30
*/
31
static void finalize_gic_version(VirtMachineState *vms)
32
{
33
+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
34
+
35
if (kvm_enabled()) {
36
int probe_bitmap;
37
38
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
39
}
40
return;
41
case VIRT_GIC_VERSION_NOSEL:
42
- vms->gic_version = VIRT_GIC_VERSION_2;
43
+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
44
+ vms->gic_version = VIRT_GIC_VERSION_2;
45
+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
46
+ /*
47
+ * in case the host does not support v2 in-kernel emulation or
48
+ * the end-user requested more than 8 VCPUs we now default
49
+ * to v3. In any case defaulting to v2 would be broken.
50
+ */
51
+ vms->gic_version = VIRT_GIC_VERSION_3;
52
+ } else if (max_cpus > GIC_NCPU) {
53
+ error_report("host only supports in-kernel GICv2 emulation "
54
+ "but more than 8 vcpus are requested");
55
+ exit(1);
56
+ }
57
break;
58
case VIRT_GIC_VERSION_2:
59
case VIRT_GIC_VERSION_3:
60
--
61
2.20.1
62
63
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