1
arm queue; dunno if this will be the last before softfreeze
1
The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
2
or not, but anyway probably the last large one. New orangepi-pc
3
board model is the big item here.
4
2
5
thanks
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
6
-- PMM
7
8
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
9
10
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
15
8
16
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
9
for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
17
10
18
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
target-arm queue:
14
target-arm queue:
22
* Fix various bugs that might result in an assert() due to
15
* more MVE instructions
23
incorrect hflags for M-profile CPUs
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
24
* Fix Aspeed SMC Controller user-mode select handling
17
* target/arm: Check NaN mode before silencing NaN
25
* Report correct (with-tag) address in fault address register
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
26
when TBI is enabled
19
* hw/arm: Add basic power management to raspi.
27
* cubieboard: make sure SOC object isn't leaked
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
28
* fsl-imx25: Wire up eSDHC controllers
29
* fsl-imx25: Wire up USB controllers
30
* New board model: orangepi-pc (OrangePi PC)
31
* ARM/KVM: if user doesn't select GIC version and the
32
host kernel can only provide GICv3, use that, rather
33
than defaulting to "fail because GICv2 isn't possible"
34
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
35
21
36
----------------------------------------------------------------
22
----------------------------------------------------------------
37
Beata Michalska (1):
23
Joe Komlodi (1):
38
target/arm: kvm: Inject events at the last stage of sync
24
target/arm: Check NaN mode before silencing NaN
39
25
40
Cédric Le Goater (2):
26
Maxim Uvarov (1):
41
aspeed/smc: Add some tracing
27
hw/gpio/gpio_pwr: use shutdown function for reboot
42
aspeed/smc: Fix User mode select/unselect scheme
43
28
44
Eric Auger (6):
29
Nolan Leake (1):
45
hw/arm/virt: Document 'max' value in gic-version property description
30
hw/arm: Add basic power management to raspi.
46
hw/arm/virt: Introduce VirtGICType enum type
47
hw/arm/virt: Introduce finalize_gic_version()
48
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
49
hw/arm/virt: kvm: Restructure finalize_gic_version()
50
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
51
31
52
Guenter Roeck (2):
32
Patrick Venture (2):
53
hw/arm/fsl-imx25: Wire up eSDHC controllers
33
docs/system/arm: Add quanta-q7l1-bmc reference
54
hw/arm/fsl-imx25: Wire up USB controllers
34
docs/system/arm: Add quanta-gbs-bmc reference
55
35
56
Igor Mammedov (1):
36
Peter Maydell (18):
57
hw/arm/cubieboard: make sure SOC object isn't leaked
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
39
target/arm: Make asimd_imm_const() public
40
target/arm: Use asimd_imm_const for A64 decode
41
target/arm: Use dup_const() instead of bitfield_replicate()
42
target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
44
target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
58
55
59
Niek Linnenbank (13):
56
Philippe Mathieu-Daudé (1):
60
hw/arm: add Allwinner H3 System-on-Chip
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
61
hw/arm: add Xunlong Orange Pi PC machine
62
hw/arm/allwinner-h3: add Clock Control Unit
63
hw/arm/allwinner-h3: add USB host controller
64
hw/arm/allwinner-h3: add System Control module
65
hw/arm/allwinner: add CPU Configuration module
66
hw/arm/allwinner: add Security Identifier device
67
hw/arm/allwinner: add SD/MMC host controller
68
hw/arm/allwinner-h3: add EMAC ethernet device
69
hw/arm/allwinner-h3: add Boot ROM support
70
hw/arm/allwinner-h3: add SDRAM controller device
71
hw/arm/allwinner: add RTC device support
72
docs: add Orange Pi PC document
73
58
74
Peter Maydell (4):
59
docs/system/arm/aspeed.rst | 1 +
75
hw/intc/armv7m_nvic: Rebuild hflags on reset
60
docs/system/arm/nuvoton.rst | 5 +-
76
target/arm: Update hflags in trans_CPS_v7m()
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
77
target/arm: Recalculate hflags correctly after writes to CONTROL
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
78
target/arm: Fix some comment typos
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
79
82
80
Philippe Mathieu-Daudé (5):
81
tests/boot_linux_console: Add a quick test for the OrangePi PC board
82
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
83
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
84
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
85
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
86
87
Richard Henderson (2):
88
target/arm: Check addresses for disabled regimes
89
target/arm: Disable clean_data_tbi for system mode
90
91
Makefile.objs | 1 +
92
hw/arm/Makefile.objs | 1 +
93
hw/misc/Makefile.objs | 5 +
94
hw/net/Makefile.objs | 1 +
95
hw/rtc/Makefile.objs | 1 +
96
hw/sd/Makefile.objs | 1 +
97
hw/usb/hcd-ehci.h | 1 +
98
include/hw/arm/allwinner-a10.h | 4 +
99
include/hw/arm/allwinner-h3.h | 161 ++++++
100
include/hw/arm/fsl-imx25.h | 18 +
101
include/hw/arm/virt.h | 12 +-
102
include/hw/misc/allwinner-cpucfg.h | 52 ++
103
include/hw/misc/allwinner-h3-ccu.h | 66 +++
104
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
105
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
106
include/hw/misc/allwinner-sid.h | 60 +++
107
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
108
include/hw/rtc/allwinner-rtc.h | 134 +++++
109
include/hw/sd/allwinner-sdhost.h | 135 +++++
110
target/arm/helper.h | 1 +
111
target/arm/kvm_arm.h | 3 +
112
hw/arm/allwinner-a10.c | 19 +
113
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
114
hw/arm/cubieboard.c | 18 +
115
hw/arm/fsl-imx25.c | 56 +++
116
hw/arm/imx25_pdk.c | 16 +
117
hw/arm/orangepi.c | 130 +++++
118
hw/arm/virt.c | 145 ++++--
119
hw/intc/armv7m_nvic.c | 6 +
120
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
121
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
122
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
123
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
124
hw/misc/allwinner-sid.c | 168 +++++++
125
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
126
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
127
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
128
hw/ssi/aspeed_smc.c | 56 ++-
129
hw/usb/hcd-ehci-sysbus.c | 17 +
130
target/arm/helper.c | 49 +-
131
target/arm/kvm.c | 14 +-
132
target/arm/kvm32.c | 15 +-
133
target/arm/kvm64.c | 15 +-
134
target/arm/translate-a64.c | 11 +
135
target/arm/translate.c | 14 +-
136
MAINTAINERS | 9 +
137
default-configs/arm-softmmu.mak | 1 +
138
docs/system/arm/orangepi.rst | 253 ++++++++++
139
docs/system/target-arm.rst | 2 +
140
hw/arm/Kconfig | 12 +
141
hw/misc/trace-events | 19 +
142
hw/net/Kconfig | 3 +
143
hw/net/trace-events | 10 +
144
hw/rtc/trace-events | 4 +
145
hw/sd/trace-events | 7 +
146
hw/ssi/trace-events | 10 +
147
tests/acceptance/boot_linux_console.py | 230 +++++++++
148
57 files changed, 5787 insertions(+), 74 deletions(-)
149
create mode 100644 include/hw/arm/allwinner-h3.h
150
create mode 100644 include/hw/misc/allwinner-cpucfg.h
151
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
152
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
153
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
154
create mode 100644 include/hw/misc/allwinner-sid.h
155
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
156
create mode 100644 include/hw/rtc/allwinner-rtc.h
157
create mode 100644 include/hw/sd/allwinner-sdhost.h
158
create mode 100644 hw/arm/allwinner-h3.c
159
create mode 100644 hw/arm/orangepi.c
160
create mode 100644 hw/misc/allwinner-cpucfg.c
161
create mode 100644 hw/misc/allwinner-h3-ccu.c
162
create mode 100644 hw/misc/allwinner-h3-dramc.c
163
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
164
create mode 100644 hw/misc/allwinner-sid.c
165
create mode 100644 hw/net/allwinner-sun8i-emac.c
166
create mode 100644 hw/rtc/allwinner-rtc.c
167
create mode 100644 hw/sd/allwinner-sdhost.c
168
create mode 100644 docs/system/arm/orangepi.rst
169
create mode 100644 hw/ssi/trace-events
170
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Mention 'max' value in the gic-version property description.
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
entry.
4
5
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20210615192848.1065297-2-venture@google.com
8
Message-id: 20200311131618.7187-2-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/arm/virt.c | 3 ++-
11
docs/system/arm/aspeed.rst | 1 +
12
1 file changed, 2 insertions(+), 1 deletion(-)
12
1 file changed, 1 insertion(+)
13
13
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/hw/arm/virt.c
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ etc.
19
virt_set_gic_version, NULL);
19
AST2400 SoC based machines :
20
object_property_set_description(obj, "gic-version",
20
21
"Set GIC version. "
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
22
- "Valid values are 2, 3 and host", NULL);
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
23
+ "Valid values are 2, 3, host and max",
23
24
+ NULL);
24
AST2500 SoC based machines :
25
26
vms->highmem_ecam = !vmc->no_highmem_ecam;
27
25
28
--
26
--
29
2.20.1
27
2.20.1
30
28
31
29
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
At the moment if the end-user does not specify the gic-version along
3
Add line item reference to quanta-gbs-bmc machine.
4
with KVM acceleration, v2 is set by default. However most of the
5
systems now have GICv3 and sometimes they do not support GICv2
6
compatibility.
7
4
8
This patch keeps the default v2 selection in all cases except
5
Signed-off-by: Patrick Venture <venture@google.com>
9
in the KVM accelerated mode when either
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
- the host does not support GICv2 in-kernel emulation or
7
Message-id: 20210615192848.1065297-3-venture@google.com
11
- number of VCPUS exceeds 8.
8
[PMM: fixed underline Sphinx warning]
12
13
Those cases did not work anyway so we do not break any compatibility.
14
Now we get v3 selected in such a case.
15
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
18
Reviewed-by: Andrew Jones <drjones@redhat.com>
19
Message-id: 20200311131618.7187-7-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
10
---
22
hw/arm/virt.c | 17 ++++++++++++++++-
11
docs/system/arm/nuvoton.rst | 5 +++--
23
1 file changed, 16 insertions(+), 1 deletion(-)
12
1 file changed, 3 insertions(+), 2 deletions(-)
24
13
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
26
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
16
--- a/docs/system/arm/nuvoton.rst
28
+++ b/hw/arm/virt.c
17
+++ b/docs/system/arm/nuvoton.rst
29
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
18
@@ -XXX,XX +XXX,XX @@
30
*/
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
31
static void finalize_gic_version(VirtMachineState *vms)
20
-=====================================================
32
{
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
33
+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
22
+================================================================
34
+
23
35
if (kvm_enabled()) {
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
36
int probe_bitmap;
25
designed to be used as Baseboard Management Controllers (BMCs) in various
37
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
38
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
39
}
28
Hyperscale applications. The following machines are based on this chip :
40
return;
29
41
case VIRT_GIC_VERSION_NOSEL:
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
42
- vms->gic_version = VIRT_GIC_VERSION_2;
31
- ``quanta-gsj`` Quanta GSJ server BMC
43
+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
32
44
+ vms->gic_version = VIRT_GIC_VERSION_2;
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
45
+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
46
+ /*
47
+ * in case the host does not support v2 in-kernel emulation or
48
+ * the end-user requested more than 8 VCPUs we now default
49
+ * to v3. In any case defaulting to v2 would be broken.
50
+ */
51
+ vms->gic_version = VIRT_GIC_VERSION_3;
52
+ } else if (max_cpus > GIC_NCPU) {
53
+ error_report("host only supports in-kernel GICv2 emulation "
54
+ "but more than 8 vcpus are requested");
55
+ exit(1);
56
+ }
57
break;
58
case VIRT_GIC_VERSION_2:
59
case VIRT_GIC_VERSION_3:
60
--
34
--
61
2.20.1
35
2.20.1
62
36
63
37
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
The Clock Control Unit is responsible for clock signal generation,
3
This is just enough to make reboot and poweroff work. Works for
4
configuration and distribution in the Allwinner H3 System on Chip.
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
This commit adds support for the Clock Control Unit which emulates
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
a simple read/write register interface.
6
do what linux does for reset.
7
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
The watchdog timer functionality is not yet implemented.
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
18
---
15
hw/misc/Makefile.objs | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
16
include/hw/arm/allwinner-h3.h | 3 +
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
17
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
18
hw/arm/allwinner-h3.c | 9 +-
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
19
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
20
5 files changed, 320 insertions(+), 1 deletion(-)
24
5 files changed, 204 insertions(+), 2 deletions(-)
21
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
22
create mode 100644 hw/misc/allwinner-h3-ccu.c
26
create mode 100644 hw/misc/bcm2835_powermgt.c
23
27
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
25
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
30
--- a/include/hw/arm/bcm2835_peripherals.h
27
+++ b/hw/misc/Makefile.objs
31
+++ b/include/hw/arm/bcm2835_peripherals.h
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
29
30
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
31
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
41
#include "hw/arm/boot.h"
33
#include "hw/misc/bcm2835_mphi.h"
42
#include "hw/timer/allwinner-a10-pit.h"
34
#include "hw/misc/bcm2835_thermal.h"
43
#include "hw/intc/arm_gic.h"
35
#include "hw/misc/bcm2835_cprman.h"
44
+#include "hw/misc/allwinner-h3-ccu.h"
36
+#include "hw/misc/bcm2835_powermgt.h"
45
#include "target/arm/cpu.h"
37
#include "hw/sd/sdhci.h"
46
38
#include "hw/sd/bcm2835_sdhost.h"
47
/**
39
#include "hw/gpio/bcm2835_gpio.h"
48
@@ -XXX,XX +XXX,XX @@ enum {
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
49
AW_H3_SRAM_A1,
41
BCM2835MphiState mphi;
50
AW_H3_SRAM_A2,
42
UnimplementedDeviceState txp;
51
AW_H3_SRAM_C,
43
UnimplementedDeviceState armtmr;
52
+ AW_H3_CCU,
44
- UnimplementedDeviceState powermgt;
53
AW_H3_PIT,
45
+ BCM2835PowerMgtState powermgt;
54
AW_H3_UART0,
46
BCM2835CprmanState cprman;
55
AW_H3_UART1,
47
PL011State uart0;
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
48
BCM2835AuxState aux;
57
ARMCPU cpus[AW_H3_NUM_CPUS];
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
58
const hwaddr *memmap;
59
AwA10PITState timer;
60
+ AwH3ClockCtlState ccu;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h
65
new file mode 100644
50
new file mode 100644
66
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
67
--- /dev/null
52
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-ccu.h
53
+++ b/include/hw/misc/bcm2835_powermgt.h
69
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
70
+/*
55
+/*
71
+ * Allwinner H3 Clock Control Unit emulation
56
+ * BCM2835 Power Management emulation
72
+ *
57
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
74
+ *
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
75
+ * This program is free software: you can redistribute it and/or modify
60
+ *
76
+ * it under the terms of the GNU General Public License as published by
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
77
+ * the Free Software Foundation, either version 2 of the License, or
62
+ * See the COPYING file in the top-level directory.
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
63
+ */
88
+
64
+
89
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
65
+#ifndef BCM2835_POWERMGT_H
90
+#define HW_MISC_ALLWINNER_H3_CCU_H
66
+#define BCM2835_POWERMGT_H
91
+
67
+
68
+#include "hw/sysbus.h"
92
+#include "qom/object.h"
69
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
70
+
94
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
95
+/**
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
96
+ * @name Constants
73
+
97
+ * @{
74
+struct BCM2835PowerMgtState {
98
+ */
75
+ SysBusDevice busdev;
99
+
100
+/** Size of register I/O address space used by CCU device */
101
+#define AW_H3_CCU_IOSIZE (0x400)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
105
+
106
+/** @} */
107
+
108
+/**
109
+ * @name Object model
110
+ * @{
111
+ */
112
+
113
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
114
+#define AW_H3_CCU(obj) \
115
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
116
+
117
+/** @} */
118
+
119
+/**
120
+ * Allwinner H3 CCU object instance state.
121
+ */
122
+typedef struct AwH3ClockCtlState {
123
+ /*< private >*/
124
+ SysBusDevice parent_obj;
125
+ /*< public >*/
126
+
127
+ /** Maps I/O registers in physical memory */
128
+ MemoryRegion iomem;
76
+ MemoryRegion iomem;
129
+
77
+
130
+ /** Array of hardware registers */
78
+ uint32_t rstc;
131
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
79
+ uint32_t rsts;
132
+
80
+ uint32_t wdog;
133
+} AwH3ClockCtlState;
81
+};
134
+
82
+
135
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
83
+#endif
136
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
137
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/arm/allwinner-h3.c
86
--- a/hw/arm/bcm2835_peripherals.c
139
+++ b/hw/arm/allwinner-h3.c
87
+++ b/hw/arm/bcm2835_peripherals.c
140
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
141
[AW_H3_SRAM_A1] = 0x00000000,
89
142
[AW_H3_SRAM_A2] = 0x00044000,
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
143
[AW_H3_SRAM_C] = 0x00010000,
91
OBJECT(&s->gpu_bus_mr));
144
+ [AW_H3_CCU] = 0x01c20000,
92
+
145
[AW_H3_PIT] = 0x01c20c00,
93
+ /* Power Management */
146
[AW_H3_UART0] = 0x01c28000,
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
147
[AW_H3_UART1] = 0x01c28400,
95
+ TYPE_BCM2835_POWERMGT);
148
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
149
{ "usb2-phy", 0x01c1c000, 4 * KiB },
150
{ "usb3-phy", 0x01c1d000, 4 * KiB },
151
{ "smc", 0x01c1e000, 4 * KiB },
152
- { "ccu", 0x01c20000, 1 * KiB },
153
{ "pio", 0x01c20800, 1 * KiB },
154
{ "owa", 0x01c21000, 1 * KiB },
155
{ "pwm", 0x01c21400, 1 * KiB },
156
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
157
"clk0-freq", &error_abort);
158
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
159
"clk1-freq", &error_abort);
160
+
161
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
162
+ TYPE_AW_H3_CCU);
163
}
96
}
164
97
165
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
166
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
167
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
168
&s->sram_c);
101
INTERRUPT_USB));
169
102
170
+ /* Clock Control Unit */
103
+ /* Power Management */
171
+ qdev_init_nofail(DEVICE(&s->ccu));
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
172
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
105
+ return;
173
+
106
+ }
174
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
107
+
175
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
176
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
177
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
178
new file mode 100644
118
new file mode 100644
179
index XXXXXXX..XXXXXXX
119
index XXXXXXX..XXXXXXX
180
--- /dev/null
120
--- /dev/null
181
+++ b/hw/misc/allwinner-h3-ccu.c
121
+++ b/hw/misc/bcm2835_powermgt.c
182
@@ -XXX,XX +XXX,XX @@
122
@@ -XXX,XX +XXX,XX @@
183
+/*
123
+/*
184
+ * Allwinner H3 Clock Control Unit emulation
124
+ * BCM2835 Power Management emulation
185
+ *
125
+ *
186
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
187
+ *
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
188
+ * This program is free software: you can redistribute it and/or modify
128
+ *
189
+ * it under the terms of the GNU General Public License as published by
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
190
+ * the Free Software Foundation, either version 2 of the License, or
130
+ * See the COPYING file in the top-level directory.
191
+ * (at your option) any later version.
192
+ *
193
+ * This program is distributed in the hope that it will be useful,
194
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
195
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196
+ * GNU General Public License for more details.
197
+ *
198
+ * You should have received a copy of the GNU General Public License
199
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
200
+ */
131
+ */
201
+
132
+
202
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
203
+#include "qemu/units.h"
204
+#include "hw/sysbus.h"
205
+#include "migration/vmstate.h"
206
+#include "qemu/log.h"
134
+#include "qemu/log.h"
207
+#include "qemu/module.h"
135
+#include "qemu/module.h"
208
+#include "hw/misc/allwinner-h3-ccu.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
209
+
137
+#include "migration/vmstate.h"
210
+/* CCU register offsets */
138
+#include "sysemu/runstate.h"
211
+enum {
139
+
212
+ REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
140
+#define PASSWORD 0x5a000000
213
+ REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
141
+#define PASSWORD_MASK 0xff000000
214
+ REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
142
+
215
+ REG_PLL_VE = 0x0018, /* PLL VE Control */
143
+#define R_RSTC 0x1c
216
+ REG_PLL_DDR = 0x0020, /* PLL DDR Control */
144
+#define V_RSTC_RESET 0x20
217
+ REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
145
+#define R_RSTS 0x20
218
+ REG_PLL_GPU = 0x0038, /* PLL GPU Control */
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
219
+ REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
147
+#define R_WDOG 0x24
220
+ REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
148
+
221
+ REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
222
+ REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
223
+ REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
224
+ REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
225
+ REG_MBUS = 0x00FC, /* MBUS Reset */
226
+ REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
227
+ REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
228
+ REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
229
+ REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
230
+ REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
231
+ REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
232
+ REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
233
+ REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
234
+ REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
235
+ REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
236
+ REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
237
+ REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
238
+ REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
239
+};
240
+
241
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
242
+
243
+/* CCU register flags */
244
+enum {
245
+ REG_DRAM_CFG_UPDATE = (1 << 16),
246
+};
247
+
248
+enum {
249
+ REG_PLL_ENABLE = (1 << 31),
250
+ REG_PLL_LOCK = (1 << 28),
251
+};
252
+
253
+
254
+/* CCU register reset values */
255
+enum {
256
+ REG_PLL_CPUX_RST = 0x00001000,
257
+ REG_PLL_AUDIO_RST = 0x00035514,
258
+ REG_PLL_VIDEO_RST = 0x03006207,
259
+ REG_PLL_VE_RST = 0x03006207,
260
+ REG_PLL_DDR_RST = 0x00001000,
261
+ REG_PLL_PERIPH0_RST = 0x00041811,
262
+ REG_PLL_GPU_RST = 0x03006207,
263
+ REG_PLL_PERIPH1_RST = 0x00041811,
264
+ REG_PLL_DE_RST = 0x03006207,
265
+ REG_CPUX_AXI_RST = 0x00010000,
266
+ REG_APB1_RST = 0x00001010,
267
+ REG_APB2_RST = 0x01000000,
268
+ REG_DRAM_CFG_RST = 0x00000000,
269
+ REG_MBUS_RST = 0x80000000,
270
+ REG_PLL_TIME0_RST = 0x000000FF,
271
+ REG_PLL_TIME1_RST = 0x000000FF,
272
+ REG_PLL_CPUX_BIAS_RST = 0x08100200,
273
+ REG_PLL_AUDIO_BIAS_RST = 0x10100000,
274
+ REG_PLL_VIDEO_BIAS_RST = 0x10100000,
275
+ REG_PLL_VE_BIAS_RST = 0x10100000,
276
+ REG_PLL_DDR_BIAS_RST = 0x81104000,
277
+ REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
278
+ REG_PLL_GPU_BIAS_RST = 0x10100000,
279
+ REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
280
+ REG_PLL_DE_BIAS_RST = 0x10100000,
281
+ REG_PLL_CPUX_TUNING_RST = 0x0A101000,
282
+ REG_PLL_DDR_TUNING_RST = 0x14880000,
283
+};
284
+
285
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
286
+ unsigned size)
150
+ unsigned size)
287
+{
151
+{
288
+ const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
289
+ const uint32_t idx = REG_INDEX(offset);
153
+ uint32_t res = 0;
290
+
154
+
291
+ switch (offset) {
155
+ switch (offset) {
292
+ case 0x308 ... AW_H3_CCU_IOSIZE:
156
+ case R_RSTC:
293
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
157
+ res = s->rstc;
294
+ __func__, (uint32_t)offset);
158
+ break;
295
+ return 0;
159
+ case R_RSTS:
296
+ }
160
+ res = s->rsts;
297
+
161
+ break;
298
+ return s->regs[idx];
162
+ case R_WDOG:
299
+}
163
+ res = s->wdog;
300
+
164
+ break;
301
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
165
+
302
+ uint64_t val, unsigned size)
166
+ default:
303
+{
167
+ qemu_log_mask(LOG_UNIMP,
304
+ AwH3ClockCtlState *s = AW_H3_CCU(opaque);
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
305
+ const uint32_t idx = REG_INDEX(offset);
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
306
+
191
+
307
+ switch (offset) {
192
+ switch (offset) {
308
+ case REG_DRAM_CFG: /* DRAM Configuration */
193
+ case R_RSTC:
309
+ val &= ~REG_DRAM_CFG_UPDATE;
194
+ s->rstc = value;
310
+ break;
195
+ if (value & V_RSTC_RESET) {
311
+ case REG_PLL_CPUX: /* PLL CPUX Control */
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
312
+ case REG_PLL_AUDIO: /* PLL Audio Control */
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
313
+ case REG_PLL_VIDEO: /* PLL Video Control */
198
+ } else {
314
+ case REG_PLL_VE: /* PLL VE Control */
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
315
+ case REG_PLL_DDR: /* PLL DDR Control */
200
+ }
316
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
317
+ case REG_PLL_GPU: /* PLL GPU Control */
318
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
319
+ case REG_PLL_DE: /* PLL Display Engine Control */
320
+ if (val & REG_PLL_ENABLE) {
321
+ val |= REG_PLL_LOCK;
322
+ }
201
+ }
323
+ break;
202
+ break;
324
+ case 0x308 ... AW_H3_CCU_IOSIZE:
203
+ case R_RSTS:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
204
+ qemu_log_mask(LOG_UNIMP,
326
+ __func__, (uint32_t)offset);
205
+ "bcm2835_powermgt_write: RSTS\n");
327
+ break;
206
+ s->rsts = value;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
328
+ default:
214
+ default:
329
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
215
+ qemu_log_mask(LOG_UNIMP,
330
+ __func__, (uint32_t)offset);
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
331
+ break;
217
+ "\n", offset);
332
+ }
218
+ break;
333
+
219
+ }
334
+ s->regs[idx] = (uint32_t) val;
220
+}
335
+}
221
+
336
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
337
+static const MemoryRegionOps allwinner_h3_ccu_ops = {
223
+ .read = bcm2835_powermgt_read,
338
+ .read = allwinner_h3_ccu_read,
224
+ .write = bcm2835_powermgt_write,
339
+ .write = allwinner_h3_ccu_write,
340
+ .endianness = DEVICE_NATIVE_ENDIAN,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
341
+ .valid = {
342
+ .min_access_size = 4,
343
+ .max_access_size = 4,
344
+ },
345
+ .impl.min_access_size = 4,
226
+ .impl.min_access_size = 4,
346
+};
227
+ .impl.max_access_size = 4,
347
+
228
+};
348
+static void allwinner_h3_ccu_reset(DeviceState *dev)
229
+
349
+{
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
350
+ AwH3ClockCtlState *s = AW_H3_CCU(dev);
231
+ .name = TYPE_BCM2835_POWERMGT,
351
+
352
+ /* Set default values for registers */
353
+ s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
354
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
355
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
356
+ s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
357
+ s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
358
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
359
+ s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
360
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
361
+ s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
362
+ s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
363
+ s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
364
+ s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
365
+ s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
366
+ s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
367
+ s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
368
+ s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
369
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
370
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
371
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
372
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
373
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
374
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
375
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
376
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
377
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
378
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
379
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
380
+}
381
+
382
+static void allwinner_h3_ccu_init(Object *obj)
383
+{
384
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
385
+ AwH3ClockCtlState *s = AW_H3_CCU(obj);
386
+
387
+ /* Memory mapping */
388
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
389
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
390
+ sysbus_init_mmio(sbd, &s->iomem);
391
+}
392
+
393
+static const VMStateDescription allwinner_h3_ccu_vmstate = {
394
+ .name = "allwinner-h3-ccu",
395
+ .version_id = 1,
232
+ .version_id = 1,
396
+ .minimum_version_id = 1,
233
+ .minimum_version_id = 1,
397
+ .fields = (VMStateField[]) {
234
+ .fields = (VMStateField[]) {
398
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
399
+ VMSTATE_END_OF_LIST()
238
+ VMSTATE_END_OF_LIST()
400
+ }
239
+ }
401
+};
240
+};
402
+
241
+
403
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
404
+{
262
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
264
+
407
+ dc->reset = allwinner_h3_ccu_reset;
265
+ dc->reset = bcm2835_powermgt_reset;
408
+ dc->vmsd = &allwinner_h3_ccu_vmstate;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
409
+}
267
+}
410
+
268
+
411
+static const TypeInfo allwinner_h3_ccu_info = {
269
+static TypeInfo bcm2835_powermgt_info = {
412
+ .name = TYPE_AW_H3_CCU,
270
+ .name = TYPE_BCM2835_POWERMGT,
413
+ .parent = TYPE_SYS_BUS_DEVICE,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
414
+ .instance_init = allwinner_h3_ccu_init,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
415
+ .instance_size = sizeof(AwH3ClockCtlState),
273
+ .class_init = bcm2835_powermgt_class_init,
416
+ .class_init = allwinner_h3_ccu_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
417
+};
275
+};
418
+
276
+
419
+static void allwinner_h3_ccu_register(void)
277
+static void bcm2835_powermgt_register_types(void)
420
+{
278
+{
421
+ type_register_static(&allwinner_h3_ccu_info);
279
+ type_register_static(&bcm2835_powermgt_info);
422
+}
280
+}
423
+
281
+
424
+type_init(allwinner_h3_ccu_register)
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
425
--
295
--
426
2.20.1
296
2.20.1
427
297
428
298
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
Add a test booting and quickly shutdown a raspi2 machine,
4
the serial output is working.
4
to test the power management model:
5
5
6
The kernel image and DeviceTree blob are built by the Armbian
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
project (based on Debian):
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
https://www.armbian.com/orange-pi-pc/
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
The cpio image used comes from the linux-build-test project:
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
https://github.com/groeck/linux-build-test
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
If ARM is a target being built, "make check-acceptance" will
13
...
14
automatically include this test by the use of the "arch:arm" tags.
15
16
Alternatively, this test can be run using:
17
18
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
19
console: Uncompressing Linux... done, booting the kernel.
20
console: Booting Linux on physical CPU 0x0
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
23
console: CPU: div instructions available: patching division code
24
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
25
console: OF: fdt: Machine model: Xunlong Orange Pi PC
26
[...]
27
console: Trying to unpack rootfs image as initramfs...
28
console: Freeing initrd memory: 3256K
29
console: Freeing unused kernel memory: 1024K
30
console: Run /init as init process
31
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
32
console: Starting logging: OK
33
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
34
console: done.
35
console: Starting network: OK
36
console: Found console ttyS0
37
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
38
console: Boot successful.
14
console: Boot successful.
39
console: cat /proc/cpuinfo
15
console: cat /proc/cpuinfo
40
console: / # cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
41
console: processor : 0
17
...
42
console: model name : ARMv7 Processor rev 5 (v7l)
43
console: BogoMIPS : 125.00
44
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
45
console: CPU implementer : 0x41
46
console: CPU architecture: 7
47
console: CPU variant : 0x0
48
console: CPU part : 0xc07
49
console: CPU revision : 5
50
[...]
51
console: processor : 3
18
console: processor : 3
52
console: model name : ARMv7 Processor rev 5 (v7l)
19
console: model name : ARMv7 Processor rev 5 (v7l)
53
console: BogoMIPS : 125.00
20
console: BogoMIPS : 125.00
54
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
55
console: CPU implementer : 0x41
22
console: CPU implementer : 0x41
56
console: CPU architecture: 7
23
console: CPU architecture: 7
57
console: CPU variant : 0x0
24
console: CPU variant : 0x0
58
console: CPU part : 0xc07
25
console: CPU part : 0xc07
59
console: CPU revision : 5
26
console: CPU revision : 5
60
console: Hardware : Allwinner sun8i Family
27
console: Hardware : BCM2835
61
console: Revision : 0000
28
console: Revision : 0000
62
console: Serial : 0000000000000000
29
console: Serial : 0000000000000000
63
console: cat /proc/iomem
30
console: cat /proc/iomem
64
console: / # cat /proc/iomem
31
console: / # cat /proc/iomem
65
console: 01000000-010fffff : clock@1000000
32
console: 00000000-3bffffff : System RAM
66
console: 01c00000-01c00fff : system-control@1c00000
33
console: 00008000-00afffff : Kernel code
67
console: 01c02000-01c02fff : dma-controller@1c02000
34
console: 00c00000-00d468ef : Kernel data
68
[...]
35
console: 3f006000-3f006fff : dwc_otg
69
console: reboot
36
console: 3f007000-3f007eff : /soc/dma@7e007000
70
console: / # reboot
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
71
console: / # Found console ttyS0
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
72
console: Stopping network: OK
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
73
console: hrtimer: interrupt took 21852064 ns
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
74
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
41
PASS (24.59 s)
75
console: done.
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
76
console: Stopping logging: OK
43
JOB TIME : 25.02 s
77
console: umount: devtmpfs busy - remounted read-only
78
console: umount: can't unmount /: Invalid argument
79
console: The system is going down NOW!
80
console: Sent SIGTERM to all processes
81
console: Sent SIGKILL to all processes
82
console: Requesting system reboot
83
console: reboot: Restarting system
84
PASS (48.32 s)
85
JOB TIME : 49.16 s
86
44
87
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
88
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
89
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
90
Tested-by: Alex Bennée <alex.bennee@linaro.org>
91
Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com
92
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
93
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94
---
49
---
95
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
96
1 file changed, 40 insertions(+)
51
1 file changed, 43 insertions(+)
97
52
98
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
99
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
100
--- a/tests/acceptance/boot_linux_console.py
55
--- a/tests/acceptance/boot_linux_console.py
101
+++ b/tests/acceptance/boot_linux_console.py
56
+++ b/tests/acceptance/boot_linux_console.py
102
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
57
@@ -XXX,XX +XXX,XX @@
103
console_pattern = 'Kernel command line: %s' % kernel_command_line
58
from avocado import skip
104
self.wait_for_console_pattern(console_pattern)
59
from avocado import skipUnless
105
60
from avocado_qemu import Test
106
+ def test_arm_orangepi_initrd(self):
61
+from avocado_qemu import exec_command
62
from avocado_qemu import exec_command_and_wait_for_pattern
63
from avocado_qemu import interrupt_interactive_console_until_pattern
64
from avocado_qemu import wait_for_console_pattern
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
66
"""
67
self.do_test_arm_raspi2(0)
68
69
+ def test_arm_raspi2_initrd(self):
107
+ """
70
+ """
108
+ :avocado: tags=arch:arm
71
+ :avocado: tags=arch:arm
109
+ :avocado: tags=machine:orangepi-pc
72
+ :avocado: tags=machine:raspi2
110
+ """
73
+ """
111
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
112
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
75
+ 'pool/main/r/raspberrypi-firmware/'
113
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
114
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
115
+ kernel_path = self.extract_from_deb(deb_path,
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
116
+ '/boot/vmlinuz-4.20.7-sunxi')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
117
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
81
+
118
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
119
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
120
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
121
+ 'arm/rootfs-armv7a.cpio.gz')
84
+ 'arm/rootfs-armv7a.cpio.gz')
122
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
123
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
124
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
125
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
126
+
89
+
127
+ self.vm.set_console()
90
+ self.vm.set_console()
128
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
129
+ 'console=ttyS0,115200 '
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
130
+ 'panic=-1 noreboot')
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
131
+ self.vm.add_args('-kernel', kernel_path,
95
+ self.vm.add_args('-kernel', kernel_path,
132
+ '-dtb', dtb_path,
96
+ '-dtb', dtb_path,
133
+ '-initrd', initrd_path,
97
+ '-initrd', initrd_path,
134
+ '-append', kernel_command_line,
98
+ '-append', kernel_command_line,
135
+ '-no-reboot')
99
+ '-no-reboot')
136
+ self.vm.launch()
100
+ self.vm.launch()
137
+ self.wait_for_console_pattern('Boot successful.')
101
+ self.wait_for_console_pattern('Boot successful.')
138
+
102
+
139
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
140
+ 'Allwinner sun8i Family')
104
+ 'BCM2835')
141
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
142
+ 'system-control@1c00000')
106
+ '/soc/cprman@7e101000')
143
+ exec_command_and_wait_for_pattern(self, 'reboot',
107
+ exec_command(self, 'halt')
144
+ 'reboot: Restarting system')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
145
+
110
+
146
def test_s390x_s390_ccw_virtio(self):
111
def test_arm_exynos4210_initrd(self):
147
"""
112
"""
148
:avocado: tags=arch:s390x
113
:avocado: tags=arch:arm
149
--
114
--
150
2.20.1
115
2.20.1
151
116
152
117
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
We fail to validate the upper bits of a virtual address on a
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
translation disabled regime, as per AArch64.TranslateAddressS1Off.
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
To avoid this, we check to see what NaN mode we're running in before we call
7
Message-id: 20200308012946.16303-2-richard.henderson@linaro.org
8
floatxx_silence_nan().
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
15
---
11
target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++-
16
target/arm/helper-a64.c | 12 +++++++++---
12
1 file changed, 34 insertions(+), 1 deletion(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
13
19
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
22
--- a/target/arm/helper-a64.c
17
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper-a64.c
18
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
19
/* Definitely a real MMU, not an MPU */
25
float16 nan = a;
20
26
if (float16_is_signaling_nan(a, fpst)) {
21
if (regime_translation_disabled(env, mmu_idx)) {
27
float_raise(float_flag_invalid, fpst);
22
- /* MMU disabled. */
28
- nan = float16_silence_nan(a, fpst);
23
+ /*
29
+ if (!fpst->default_nan_mode) {
24
+ * MMU disabled. S1 addresses within aa64 translation regimes are
30
+ nan = float16_silence_nan(a, fpst);
25
+ * still checked for bounds -- see AArch64.TranslateAddressS1Off.
26
+ */
27
+ if (mmu_idx != ARMMMUIdx_Stage2) {
28
+ int r_el = regime_el(env, mmu_idx);
29
+ if (arm_el_is_aa64(env, r_el)) {
30
+ int pamax = arm_pamax(env_archcpu(env));
31
+ uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
32
+ int addrtop, tbi;
33
+
34
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
35
+ if (access_type == MMU_INST_FETCH) {
36
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
37
+ }
38
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
39
+ addrtop = (tbi ? 55 : 63);
40
+
41
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
42
+ fi->type = ARMFault_AddressSize;
43
+ fi->level = 0;
44
+ fi->stage2 = false;
45
+ return 1;
46
+ }
47
+
48
+ /*
49
+ * When TBI is disabled, we've just validated that all of the
50
+ * bits above PAMax are zero, so logically we only need to
51
+ * clear the top byte for TBI. But it's clearer to follow
52
+ * the pseudocode set of addrdesc.paddress.
53
+ */
54
+ address = extract64(address, 0, 52);
55
+ }
31
+ }
56
+ }
32
}
57
*phys_ptr = address;
33
if (fpst->default_nan_mode) {
58
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
34
nan = float16_default_nan(fpst);
59
*page_size = TARGET_PAGE_SIZE;
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
36
float32 nan = a;
37
if (float32_is_signaling_nan(a, fpst)) {
38
float_raise(float_flag_invalid, fpst);
39
- nan = float32_silence_nan(a, fpst);
40
+ if (!fpst->default_nan_mode) {
41
+ nan = float32_silence_nan(a, fpst);
42
+ }
43
}
44
if (fpst->default_nan_mode) {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/vfp_helper.c
60
+++ b/target/arm/vfp_helper.c
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
62
float16 nan = f16;
63
if (float16_is_signaling_nan(f16, fpst)) {
64
float_raise(float_flag_invalid, fpst);
65
- nan = float16_silence_nan(f16, fpst);
66
+ if (!fpst->default_nan_mode) {
67
+ nan = float16_silence_nan(f16, fpst);
68
+ }
69
}
70
if (fpst->default_nan_mode) {
71
nan = float16_default_nan(fpst);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
73
float32 nan = f32;
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
60
--
127
--
61
2.20.1
128
2.20.1
62
129
63
130
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
Restructure the finalize_gic_version with switch cases and
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
clearly separate the following cases:
4
function has to be used for machine shutdown. Otherwise we cause
5
a reset with a bogus "cause" value, when we intended a shutdown.
5
6
6
- KVM mode / in-kernel irqchip
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
- KVM mode / userspace irqchip
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
- TCG mode
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
9
10
[PMM: tweaked commit message]
10
In KVM mode / in-kernel irqchip , we explictly check whether
11
the chosen version is supported by the host. If the end-user
12
explicitly sets v2/v3 and this is not supported by the host,
13
then the user gets an explicit error message. Note that for
14
old kernels where the CREATE_DEVICE ioctl doesn't exist then
15
we will now fail if the user specifically asked for gicv2,
16
where previously we (probably) would have succeeded.
17
18
In KVM mode / userspace irqchip we immediatly output an error
19
in case the end-user explicitly selected v3. Also we warn the
20
end-user about the unexpected usage of gic-version=host in
21
that case as only userspace GICv2 is supported.
22
23
Signed-off-by: Eric Auger <eric.auger@redhat.com>
24
Reviewed-by: Andrew Jones <drjones@redhat.com>
25
Message-id: 20200311131618.7187-6-eric.auger@redhat.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
12
---
28
hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------
13
hw/gpio/gpio_pwr.c | 2 +-
29
1 file changed, 67 insertions(+), 21 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
30
15
31
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
32
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/virt.c
18
--- a/hw/gpio/gpio_pwr.c
34
+++ b/hw/arm/virt.c
19
+++ b/hw/gpio/gpio_pwr.c
35
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
36
*/
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
37
static void finalize_gic_version(VirtMachineState *vms)
38
{
22
{
39
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
23
if (level) {
40
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
41
- if (!kvm_enabled()) {
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
42
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
43
- error_report("gic-version=host requires KVM");
44
- exit(1);
45
- } else {
46
- /* "max": currently means 3 for TCG */
47
- vms->gic_version = VIRT_GIC_VERSION_3;
48
- }
49
- } else {
50
- int probe_bitmap = kvm_arm_vgic_probe();
51
+ if (kvm_enabled()) {
52
+ int probe_bitmap;
53
54
- if (!probe_bitmap) {
55
+ if (!kvm_irqchip_in_kernel()) {
56
+ switch (vms->gic_version) {
57
+ case VIRT_GIC_VERSION_HOST:
58
+ warn_report(
59
+ "gic-version=host not relevant with kernel-irqchip=off "
60
+ "as only userspace GICv2 is supported. Using v2 ...");
61
+ return;
62
+ case VIRT_GIC_VERSION_MAX:
63
+ case VIRT_GIC_VERSION_NOSEL:
64
+ vms->gic_version = VIRT_GIC_VERSION_2;
65
+ return;
66
+ case VIRT_GIC_VERSION_2:
67
+ return;
68
+ case VIRT_GIC_VERSION_3:
69
error_report(
70
- "Unable to determine GIC version supported by host");
71
+ "gic-version=3 is not supported with kernel-irqchip=off");
72
exit(1);
73
- } else {
74
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
75
- vms->gic_version = VIRT_GIC_VERSION_3;
76
- } else {
77
- vms->gic_version = VIRT_GIC_VERSION_2;
78
- }
79
}
80
}
81
- } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
82
+
83
+ probe_bitmap = kvm_arm_vgic_probe();
84
+ if (!probe_bitmap) {
85
+ error_report("Unable to determine GIC version supported by host");
86
+ exit(1);
87
+ }
88
+
89
+ switch (vms->gic_version) {
90
+ case VIRT_GIC_VERSION_HOST:
91
+ case VIRT_GIC_VERSION_MAX:
92
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
93
+ vms->gic_version = VIRT_GIC_VERSION_3;
94
+ } else {
95
+ vms->gic_version = VIRT_GIC_VERSION_2;
96
+ }
97
+ return;
98
+ case VIRT_GIC_VERSION_NOSEL:
99
+ vms->gic_version = VIRT_GIC_VERSION_2;
100
+ break;
101
+ case VIRT_GIC_VERSION_2:
102
+ case VIRT_GIC_VERSION_3:
103
+ break;
104
+ }
105
+
106
+ /* Check chosen version is effectively supported by the host */
107
+ if (vms->gic_version == VIRT_GIC_VERSION_2 &&
108
+ !(probe_bitmap & KVM_ARM_VGIC_V2)) {
109
+ error_report("host does not support in-kernel GICv2 emulation");
110
+ exit(1);
111
+ } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
112
+ !(probe_bitmap & KVM_ARM_VGIC_V3)) {
113
+ error_report("host does not support in-kernel GICv3 emulation");
114
+ exit(1);
115
+ }
116
+ return;
117
+ }
118
+
119
+ /* TCG mode */
120
+ switch (vms->gic_version) {
121
+ case VIRT_GIC_VERSION_NOSEL:
122
vms->gic_version = VIRT_GIC_VERSION_2;
123
+ break;
124
+ case VIRT_GIC_VERSION_MAX:
125
+ vms->gic_version = VIRT_GIC_VERSION_3;
126
+ break;
127
+ case VIRT_GIC_VERSION_HOST:
128
+ error_report("gic-version=host requires KVM");
129
+ exit(1);
130
+ case VIRT_GIC_VERSION_2:
131
+ case VIRT_GIC_VERSION_3:
132
+ break;
133
}
26
}
134
}
27
}
135
28
136
--
29
--
137
2.20.1
30
2.20.1
138
31
139
32
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
The Aspeed SMC Controller can operate in different modes : Read, Fast
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Read, Write and User modes. When the User mode is configured, it
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
selects automatically the SPI slave device until the CE_STOP_ACTIVE
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
6
bit is set to 1. When any other modes are configured the device is
9
---
7
unselected. The HW logic handles the chip select automatically when
10
target/arm/translate-mve.c | 17 +++++++++--------
8
the flash is accessed through its AHB window.
11
1 file changed, 9 insertions(+), 8 deletions(-)
9
12
10
When configuring the CEx Control Register, the User mode logic to
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
11
select and unselect the slave is incorrect and data corruption can be
12
seen on machines using two chips, witherspoon and romulus.
13
14
Rework the handler setting the CEx Control Register to fix this issue.
15
16
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
18
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
19
Message-id: 20200206112645.21275-3-clg@kaod.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++----------------
23
hw/ssi/trace-events | 1 +
24
2 files changed, 24 insertions(+), 16 deletions(-)
25
26
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
27
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/aspeed_smc.c
15
--- a/target/arm/translate-mve.c
29
+++ b/hw/ssi/aspeed_smc.c
16
+++ b/target/arm/translate-mve.c
30
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
31
}
18
}
32
}
19
}
33
20
34
-static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
35
+static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
23
+ unsigned msize)
36
{
24
{
37
- const AspeedSMCState *s = fl->controller;
25
TCGv_i32 addr;
38
+ AspeedSMCState *s = fl->controller;
26
uint32_t offset;
39
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
40
- return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
28
return true;
41
+ trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
29
}
42
+
30
43
+ qemu_set_irq(s->cs_lines[fl->id], unselect);
31
- offset = a->imm << a->size;
32
+ offset = a->imm << msize;
33
if (!a->a) {
34
offset = -offset;
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
44
}
42
}
45
43
46
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
47
{
64
{
48
- AspeedSMCState *s = fl->controller;
49
-
50
- s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
51
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
52
+ aspeed_smc_flash_do_select(fl, false);
53
}
54
55
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
56
{
57
- AspeedSMCState *s = fl->controller;
58
-
59
- s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
60
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
61
+ aspeed_smc_flash_do_select(fl, true);
62
}
63
64
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
65
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = {
66
},
67
};
68
69
-static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
70
+static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
71
{
72
AspeedSMCState *s = fl->controller;
73
+ bool unselect;
74
75
- s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START;
76
+ /* User mode selects the CS, other modes unselect */
77
+ unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
78
79
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
80
+ /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
81
+ if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
82
+ value & CTRL_CE_STOP_ACTIVE) {
83
+ unselect = true;
84
+ }
85
+
86
+ s->regs[s->r_ctrl0 + fl->id] = value;
87
+
88
+ s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
89
+
90
+ aspeed_smc_flash_do_select(fl, unselect);
91
}
92
93
static void aspeed_smc_reset(DeviceState *d)
94
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
95
s->regs[addr] = value;
96
} else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
97
int cs = addr - s->r_ctrl0;
98
- s->regs[addr] = value;
99
- aspeed_smc_flash_update_cs(&s->flashes[cs]);
100
+ aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
101
} else if (addr >= R_SEG_ADDR0 &&
102
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
103
int cs = addr - R_SEG_ADDR0;
104
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/ssi/trace-events
107
+++ b/hw/ssi/trace-events
108
@@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int
109
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
110
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
111
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
112
+aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
113
--
65
--
114
2.20.1
66
2.20.1
115
67
116
68
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
We plan to introduce yet another value for the gic version (nosel).
10
In particular, fixing the second of these allows us to recast
4
As we already use exotic values such as 0 and -1, let's introduce
11
the implementation to avoid 128-bit arithmetic entirely.
5
a dedicated enum type and let vms->gic_version take this
6
type.
7
12
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Message-id: 20200311131618.7187-3-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
20
---
15
include/hw/arm/virt.h | 11 +++++++++--
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
16
hw/arm/virt.c | 30 +++++++++++++++---------------
22
1 file changed, 21 insertions(+), 17 deletions(-)
17
2 files changed, 24 insertions(+), 17 deletions(-)
18
23
19
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
20
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/virt.h
26
--- a/target/arm/mve_helper.c
22
+++ b/include/hw/arm/virt.h
27
+++ b/target/arm/mve_helper.c
23
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
28
@@ -XXX,XX +XXX,XX @@
24
VIRT_IOMMU_VIRTIO,
29
*/
25
} VirtIOMMUType;
30
26
31
#include "qemu/osdep.h"
27
+typedef enum VirtGICType {
32
-#include "qemu/int128.h"
28
+ VIRT_GIC_VERSION_MAX,
33
#include "cpu.h"
29
+ VIRT_GIC_VERSION_HOST,
34
#include "internals.h"
30
+ VIRT_GIC_VERSION_2,
35
#include "vec_internal.h"
31
+ VIRT_GIC_VERSION_3,
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
32
+} VirtGICType;
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
33
+
38
34
typedef struct MemMapEntry {
39
/*
35
hwaddr base;
40
- * Rounding multiply add long dual accumulate high: we must keep
36
hwaddr size;
41
- * a 72-bit internal accumulator value and return the top 64 bits.
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
38
bool highmem_ecam;
43
+ * this is implemented with a 72-bit internal accumulator value of which
39
bool its;
44
+ * the top 64 bits are returned. We optimize this to avoid having to
40
bool virt;
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
41
- int32_t gic_version;
46
+ * is squashed back into 64-bits after each beat.
42
+ VirtGICType gic_version;
47
*/
43
VirtIOMMUType iommu;
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
44
uint16_t virtio_iommu_bdf;
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
45
struct arm_boot_info bootinfo;
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
46
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
51
void *vm, uint64_t a) \
47
uint32_t redist0_capacity =
52
{ \
48
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
53
uint16_t mask = mve_element_mask(env); \
49
54
unsigned e; \
50
- assert(vms->gic_version == 3);
55
TYPE *n = vn, *m = vm; \
51
+ assert(vms->gic_version == VIRT_GIC_VERSION_3);
56
- Int128 acc = int128_lshift(TO128(a), 8); \
52
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
53
return vms->smp_cpus > redist0_capacity ? 2 : 1;
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
54
}
59
if (mask & 1) { \
55
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
60
+ LTYPE mul; \
56
index XXXXXXX..XXXXXXX 100644
61
if (e & 1) { \
57
--- a/hw/arm/virt.c
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
58
+++ b/hw/arm/virt.c
63
- m[H##ESIZE(e)])); \
59
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
60
irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
65
+ if (SUB) { \
66
+ mul = -mul; \
67
+ } \
68
} else { \
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
70
- m[H##ESIZE(e)])); \
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
72
} \
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
75
+ a += mul; \
76
} \
77
} \
78
mve_advance_vpt(env); \
79
- return int128_getlo(int128_rshift(acc, 8)); \
80
+ return a; \
61
}
81
}
62
82
63
- if (vms->gic_version == 2) {
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
64
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
65
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
66
GIC_FDT_IRQ_PPI_CPU_WIDTH,
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
67
(1 << vms->smp_cpus) - 1);
87
68
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
70
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
90
71
qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
72
- if (vms->gic_version == 3) {
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
73
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
74
int nb_redist_regions = virt_gicv3_redist_region_count(vms);
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
75
95
76
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
96
/* Vector add across vector */
77
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
97
#define DO_VADDV(OP, ESIZE, TYPE) \
78
}
79
}
80
81
- if (vms->gic_version == 2) {
82
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
83
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
84
GIC_FDT_IRQ_PPI_CPU_WIDTH,
85
(1 << vms->smp_cpus) - 1);
86
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
87
* purposes are to make TCG consistent (with 64-bit KVM hosts)
88
* and to improve SGI efficiency.
89
*/
90
- if (vms->gic_version == 3) {
91
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
92
clustersz = GICV3_TARGETLIST_BITS;
93
} else {
94
clustersz = GIC_TARGETLIST_BITS;
95
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
96
/* We can probe only here because during property set
97
* KVM is not available yet
98
*/
99
- if (vms->gic_version <= 0) {
100
- /* "host" or "max" */
101
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
102
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
103
if (!kvm_enabled()) {
104
- if (vms->gic_version == 0) {
105
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
106
error_report("gic-version=host requires KVM");
107
exit(1);
108
} else {
109
/* "max": currently means 3 for TCG */
110
- vms->gic_version = 3;
111
+ vms->gic_version = VIRT_GIC_VERSION_3;
112
}
113
} else {
114
vms->gic_version = kvm_arm_vgic_probe();
115
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
116
/* The maximum number of CPUs depends on the GIC version, or on how
117
* many redistributors we can fit into the memory map.
118
*/
119
- if (vms->gic_version == 3) {
120
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
121
virt_max_cpus =
122
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
123
virt_max_cpus +=
124
@@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp)
125
static char *virt_get_gic_version(Object *obj, Error **errp)
126
{
127
VirtMachineState *vms = VIRT_MACHINE(obj);
128
- const char *val = vms->gic_version == 3 ? "3" : "2";
129
+ const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
130
131
return g_strdup(val);
132
}
133
@@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
134
VirtMachineState *vms = VIRT_MACHINE(obj);
135
136
if (!strcmp(value, "3")) {
137
- vms->gic_version = 3;
138
+ vms->gic_version = VIRT_GIC_VERSION_3;
139
} else if (!strcmp(value, "2")) {
140
- vms->gic_version = 2;
141
+ vms->gic_version = VIRT_GIC_VERSION_2;
142
} else if (!strcmp(value, "host")) {
143
- vms->gic_version = 0; /* Will probe later */
144
+ vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
145
} else if (!strcmp(value, "max")) {
146
- vms->gic_version = -1; /* Will probe later */
147
+ vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
148
} else {
149
error_setg(errp, "Invalid gic-version value");
150
error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
151
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
152
"physical address space above 32 bits",
153
NULL);
154
/* Default GIC type is v2 */
155
- vms->gic_version = 2;
156
+ vms->gic_version = VIRT_GIC_VERSION_2;
157
object_property_add_str(obj, "gic-version", virt_get_gic_version,
158
virt_set_gic_version, NULL);
159
object_property_set_description(obj, "gic-version",
160
--
98
--
161
2.20.1
99
2.20.1
162
100
163
101
diff view generated by jsdifflib
1
Fix a couple of comment typos.
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
2
5
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200303174950.3298-5-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
6
---
9
---
7
target/arm/helper.c | 2 +-
10
target/arm/translate.h | 16 ++++++++++
8
target/arm/translate.c | 2 +-
11
target/arm/translate-neon.c | 63 -------------------------------------
9
2 files changed, 2 insertions(+), 2 deletions(-)
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
10
14
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
17
--- a/target/arm/translate.h
14
+++ b/target/arm/helper.c
18
+++ b/target/arm/translate.h
15
@@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
16
20
return opc | s->be_data;
17
/*
21
}
18
* If we have triggered a EL state change we can't rely on the
22
19
- * translator having passed it too us, we need to recompute.
23
+/**
20
+ * translator having passed it to us, we need to recompute.
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
21
*/
25
+ *
22
void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
49
-{
50
- /*
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
109
-}
110
-
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
112
GVecGen2iFn *fn)
23
{
113
{
24
diff --git a/target/arm/translate.c b/target/arm/translate.c
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
115
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate.c
116
--- a/target/arm/translate.c
27
+++ b/target/arm/translate.c
117
+++ b/target/arm/translate.c
28
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
29
119
a64_translate_init();
30
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
120
}
31
/*
121
32
- * A write to any coprocessor regiser that ends a TB
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
33
+ * A write to any coprocessor register that ends a TB
123
+{
34
* must rebuild the hflags for the next TB.
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
35
*/
125
+ switch (cmode) {
36
TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
126
+ case 0: case 1:
127
+ /* no-op */
128
+ break;
129
+ case 2: case 3:
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
181
{
37
--
182
--
38
2.20.1
183
2.20.1
39
184
40
185
diff view generated by jsdifflib
1
From: Beata Michalska <beata.michalska@linaro.org>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
As such this should be the last step of sync to avoid potential overwriting
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
of whatever changes KVM might have done.
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 3 +-
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
6
14
7
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Message-id: 20200312003401.29017-2-beata.michalska@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/kvm32.c | 15 ++++++++++-----
13
target/arm/kvm64.c | 15 ++++++++++-----
14
2 files changed, 20 insertions(+), 10 deletions(-)
15
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
17
--- a/target/arm/translate.h
19
+++ b/target/arm/kvm32.c
18
+++ b/target/arm/translate.h
20
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
21
return ret;
20
* VMVN and VBIC (when cmode < 14 && op == 1).
21
*
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
23
- * callers must catch this.
24
+ * callers must catch this; we return the 64-bit constant value defined
25
+ * for AArch64.
26
*
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
34
{
35
int rd = extract32(insn, 0, 5);
36
int cmode = extract32(insn, 12, 4);
37
- int cmode_3_1 = extract32(cmode, 1, 3);
38
- int cmode_0 = extract32(cmode, 0, 1);
39
int o2 = extract32(insn, 11, 1);
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
41
bool is_neg = extract32(insn, 29, 1);
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
43
return;
22
}
44
}
23
45
24
- ret = kvm_put_vcpu_events(cpu);
46
- /* See AdvSIMDExpandImm() in ARM ARM */
25
- if (ret) {
47
- switch (cmode_3_1) {
26
- return ret;
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
27
- }
119
- }
28
-
120
-
29
write_cpustate_to_list(cpu, true);
121
- if (cmode_3_1 != 7 && is_neg) {
30
122
- imm = ~imm;
31
if (!write_list_to_kvmstate(cpu, level)) {
123
+ if (cmode == 15 && o2 && !is_neg) {
32
return EINVAL;
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
33
}
130
}
34
131
35
+ /*
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
36
+ * Setting VCPU events should be triggered after syncing the registers
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
37
+ * to avoid overwriting potential changes made by KVM upon calling
38
+ * KVM_SET_VCPU_EVENTS ioctl
39
+ */
40
+ ret = kvm_put_vcpu_events(cpu);
41
+ if (ret) {
42
+ return ret;
43
+ }
44
+
45
kvm_arm_sync_mpstate_to_kvm(cpu);
46
47
return ret;
48
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
49
index XXXXXXX..XXXXXXX 100644
134
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/kvm64.c
135
--- a/target/arm/translate.c
51
+++ b/target/arm/kvm64.c
136
+++ b/target/arm/translate.c
52
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
53
return ret;
138
case 14:
54
}
139
if (op) {
55
140
/*
56
- ret = kvm_put_vcpu_events(cpu);
141
- * This is the only case where the top and bottom 32 bits
57
- if (ret) {
142
- * of the encoded constant differ.
58
- return ret;
143
+ * This and cmode == 15 op == 1 are the only cases where
59
- }
144
+ * the top and bottom 32 bits of the encoded constant differ.
60
-
145
*/
61
write_cpustate_to_list(cpu, true);
146
uint64_t imm64 = 0;
62
147
int n;
63
if (!write_list_to_kvmstate(cpu, level)) {
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
64
return -EINVAL;
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
65
}
150
break;
66
151
case 15:
67
+ /*
152
+ if (op) {
68
+ * Setting VCPU events should be triggered after syncing the registers
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
69
+ * to avoid overwriting potential changes made by KVM upon calling
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
70
+ * KVM_SET_VCPU_EVENTS ioctl
155
+ if (imm & 0x80) {
71
+ */
156
+ imm64 |= 0x8000000000000000ULL;
72
+ ret = kvm_put_vcpu_events(cpu);
157
+ }
73
+ if (ret) {
158
+ if (imm & 0x40) {
74
+ return ret;
159
+ imm64 |= 0x3fc0000000000000ULL;
75
+ }
160
+ } else {
76
+
161
+ imm64 |= 0x4000000000000000ULL;
77
kvm_arm_sync_mpstate_to_kvm(cpu);
162
+ }
78
163
+ return imm64;
79
return ret;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
80
--
168
--
81
2.20.1
169
2.20.1
82
170
83
171
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
2
3
3
We must include the tag in the FAR_ELx register when raising
4
(We can't replace the other use of bitfield_replicate() in this file,
4
an addressing exception. Which means that we should not clear
5
in logic_imm_decode_wmask(), because that location needs to handle 2
5
out the tag during translation.
6
and 4 bit elements, which dup_const() cannot.)
6
7
7
We cannot at present comply with this for user mode, so we
8
retain the clean_data_tbi function for the moment, though it
9
no longer does what it says on the tin for system mode. This
10
function is to be replaced with MTE, so don't worry about the
11
slight misnaming.
12
13
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200308012946.16303-3-richard.henderson@linaro.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
18
---
11
---
19
target/arm/translate-a64.c | 11 +++++++++++
12
target/arm/translate-a64.c | 2 +-
20
1 file changed, 11 insertions(+)
13
1 file changed, 1 insertion(+), 1 deletion(-)
21
14
22
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
25
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
26
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
27
static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
20
/* FMOV (vector, immediate) - half-precision */
28
{
21
imm = vfp_expand_imm(MO_16, abcdefgh);
29
TCGv_i64 clean = new_tmp_a64(s);
22
/* now duplicate across the lanes */
30
+ /*
23
- imm = bitfield_replicate(imm, 16);
31
+ * In order to get the correct value in the FAR_ELx register,
24
+ imm = dup_const(MO_16, imm);
32
+ * we must present the memory subsystem with the "dirty" address
25
} else {
33
+ * including the TBI. In system mode we can make this work via
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
34
+ * the TLB, dropping the TBI during translation. But for user-only
27
}
35
+ * mode we don't have that option, and must remove the top byte now.
36
+ */
37
+#ifdef CONFIG_USER_ONLY
38
gen_top_byte_ignore(s, clean, addr, s->tbid);
39
+#else
40
+ tcg_gen_mov_i64(clean, addr);
41
+#endif
42
return clean;
43
}
44
45
--
28
--
46
2.20.1
29
2.20.1
47
30
48
31
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
2
5
3
The Security Identifier device found in various Allwinner System on Chip
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
designs gives applications a per-board unique identifier. This commit
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
adds support for the Allwinner Security Identifier using a 128-bit
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
6
UUID value as input.
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
7
15
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/misc/Makefile.objs | 1 +
14
include/hw/arm/allwinner-h3.h | 3 +
15
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
16
hw/arm/allwinner-h3.c | 11 ++-
17
hw/arm/orangepi.c | 8 ++
18
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
19
hw/misc/trace-events | 4 +
20
7 files changed, 254 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-sid.h
22
create mode 100644 hw/misc/allwinner-sid.c
23
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
25
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
18
--- a/target/arm/helper-mve.h
27
+++ b/hw/misc/Makefile.objs
19
+++ b/target/arm/helper-mve.h
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
29
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
30
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
24
+
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
34
common-obj-$(CONFIG_NSERIES) += cbus.o
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
37
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
30
--- a/target/arm/mve.decode
39
+++ b/include/hw/arm/allwinner-h3.h
31
+++ b/target/arm/mve.decode
40
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
41
#include "hw/misc/allwinner-h3-ccu.h"
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
42
#include "hw/misc/allwinner-cpucfg.h"
34
%size_28 28:1 !function=plus_1
43
#include "hw/misc/allwinner-h3-sysctrl.h"
35
44
+#include "hw/misc/allwinner-sid.h"
36
+# 1imm format immediate
45
#include "target/arm/cpu.h"
37
+%imm_28_16_0 28:1 16:3 0:4
46
38
+
47
/**
39
&vldr_vstr rn qd imm p a w size l u
48
@@ -XXX,XX +XXX,XX @@ enum {
40
&1op qd qm size
49
AW_H3_SRAM_A2,
41
&2op qd qm qn size
50
AW_H3_SRAM_C,
42
&2scalar qd qn rm size
51
AW_H3_SYSCTRL,
43
+&1imm qd imm cmode op
52
+ AW_H3_SID,
44
53
AW_H3_EHCI0,
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
54
AW_H3_OHCI0,
46
# Note that both Rn and Qd are 3 bits only (no D bit)
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
AwH3ClockCtlState ccu;
58
AwCpuCfgState cpucfg;
59
AwH3SysCtrlState sysctrl;
60
+ AwSidState sid;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-sid.h
69
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
70
+/*
79
+/*
71
+ * Allwinner Security ID emulation
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
72
+ *
81
+ * All these insns work at 64-bit widths.
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
82
+ */
88
+
83
+#define DO_1OP_IMM(OP, FN) \
89
+#ifndef HW_MISC_ALLWINNER_SID_H
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
90
+#define HW_MISC_ALLWINNER_SID_H
85
+ { \
91
+
86
+ uint64_t *da = vda; \
92
+#include "qom/object.h"
87
+ uint16_t mask = mve_element_mask(env); \
93
+#include "hw/sysbus.h"
88
+ unsigned e; \
94
+#include "qemu/uuid.h"
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
95
+
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
96
+/**
91
+ } \
97
+ * Object model
92
+ mve_advance_vpt(env); \
98
+ * @{
99
+ */
100
+
101
+#define TYPE_AW_SID "allwinner-sid"
102
+#define AW_SID(obj) \
103
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
104
+
105
+/** @} */
106
+
107
+/**
108
+ * Allwinner Security ID object instance state
109
+ */
110
+typedef struct AwSidState {
111
+ /*< private >*/
112
+ SysBusDevice parent_obj;
113
+ /*< public >*/
114
+
115
+ /** Maps I/O registers in physical memory */
116
+ MemoryRegion iomem;
117
+
118
+ /** Control register defines how and what to read */
119
+ uint32_t control;
120
+
121
+ /** RdKey register contains the data retrieved by the device */
122
+ uint32_t rdkey;
123
+
124
+ /** Stores the emulated device identifier */
125
+ QemuUUID identifier;
126
+
127
+} AwSidState;
128
+
129
+#endif /* HW_MISC_ALLWINNER_SID_H */
130
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/arm/allwinner-h3.c
133
+++ b/hw/arm/allwinner-h3.c
134
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
135
[AW_H3_SRAM_A2] = 0x00044000,
136
[AW_H3_SRAM_C] = 0x00010000,
137
[AW_H3_SYSCTRL] = 0x01c00000,
138
+ [AW_H3_SID] = 0x01c14000,
139
[AW_H3_EHCI0] = 0x01c1a000,
140
[AW_H3_OHCI0] = 0x01c1a400,
141
[AW_H3_EHCI1] = 0x01c1b000,
142
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
143
{ "mmc0", 0x01c0f000, 4 * KiB },
144
{ "mmc1", 0x01c10000, 4 * KiB },
145
{ "mmc2", 0x01c11000, 4 * KiB },
146
- { "sid", 0x01c14000, 1 * KiB },
147
{ "crypto", 0x01c15000, 4 * KiB },
148
{ "msgbox", 0x01c17000, 4 * KiB },
149
{ "spinlock", 0x01c18000, 4 * KiB },
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
151
152
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
153
TYPE_AW_CPUCFG);
154
+
155
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
156
+ TYPE_AW_SID);
157
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
158
+ "identifier", &error_abort);
159
}
160
161
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
162
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
163
qdev_init_nofail(DEVICE(&s->cpucfg));
164
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
165
166
+ /* Security Identifier */
167
+ qdev_init_nofail(DEVICE(&s->sid));
168
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
169
+
170
/* Universal Serial Bus */
171
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
172
qdev_get_gpio_in(DEVICE(&s->gic),
173
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/orangepi.c
176
+++ b/hw/arm/orangepi.c
177
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
178
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
179
&error_abort);
180
181
+ /* Setup SID properties. Currently using a default fixed SID identifier. */
182
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
183
+ qdev_prop_set_string(DEVICE(h3), "identifier",
184
+ "02c00081-1111-2222-3333-000044556677");
185
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) {
186
+ warn_report("Security Identifier value does not include H3 prefix");
187
+ }
93
+ }
188
+
94
+
189
/* Mark H3 object realized */
95
+#define DO_MOVI(N, I) (I)
190
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
96
+#define DO_ANDI(N, I) ((N) & (I))
191
97
+#define DO_ORRI(N, I) ((N) | (I))
192
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
193
new file mode 100644
194
index XXXXXXX..XXXXXXX
195
--- /dev/null
196
+++ b/hw/misc/allwinner-sid.c
197
@@ -XXX,XX +XXX,XX @@
198
+/*
199
+ * Allwinner Security ID emulation
200
+ *
201
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
202
+ *
203
+ * This program is free software: you can redistribute it and/or modify
204
+ * it under the terms of the GNU General Public License as published by
205
+ * the Free Software Foundation, either version 2 of the License, or
206
+ * (at your option) any later version.
207
+ *
208
+ * This program is distributed in the hope that it will be useful,
209
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
210
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
211
+ * GNU General Public License for more details.
212
+ *
213
+ * You should have received a copy of the GNU General Public License
214
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
215
+ */
216
+
98
+
217
+#include "qemu/osdep.h"
99
+DO_1OP_IMM(vmovi, DO_MOVI)
218
+#include "qemu/units.h"
100
+DO_1OP_IMM(vandi, DO_ANDI)
219
+#include "hw/sysbus.h"
101
+DO_1OP_IMM(vorri, DO_ORRI)
220
+#include "migration/vmstate.h"
221
+#include "qemu/log.h"
222
+#include "qemu/module.h"
223
+#include "qemu/guest-random.h"
224
+#include "qapi/error.h"
225
+#include "hw/qdev-properties.h"
226
+#include "hw/misc/allwinner-sid.h"
227
+#include "trace.h"
228
+
102
+
229
+/* SID register offsets */
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
230
+enum {
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
231
+ REG_PRCTL = 0x40, /* Control */
105
void *vd, void *vn, void *vm) \
232
+ REG_RDKEY = 0x60, /* Read Key */
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
233
+};
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
234
+
122
+
235
+/* SID register flags */
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
236
+enum {
124
+{
237
+ REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */
125
+ TCGv_ptr qd;
238
+ REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */
126
+ uint64_t imm;
239
+};
240
+
127
+
241
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
128
+ if (!dc_isar_feature(aa32_mve, s) ||
242
+ unsigned size)
129
+ !mve_check_qreg_bank(s, a->qd) ||
243
+{
130
+ !fn) {
244
+ const AwSidState *s = AW_SID(opaque);
131
+ return false;
245
+ uint64_t val = 0;
132
+ }
246
+
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
247
+ switch (offset) {
134
+ return true;
248
+ case REG_PRCTL: /* Control */
249
+ val = s->control;
250
+ break;
251
+ case REG_RDKEY: /* Read Key */
252
+ val = s->rdkey;
253
+ break;
254
+ default:
255
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
256
+ __func__, (uint32_t)offset);
257
+ return 0;
258
+ }
135
+ }
259
+
136
+
260
+ trace_allwinner_sid_read(offset, val, size);
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
261
+
138
+
262
+ return val;
139
+ qd = mve_qreg_ptr(a->qd);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
263
+}
144
+}
264
+
145
+
265
+static void allwinner_sid_write(void *opaque, hwaddr offset,
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
266
+ uint64_t val, unsigned size)
267
+{
147
+{
268
+ AwSidState *s = AW_SID(opaque);
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
269
+
150
+
270
+ trace_allwinner_sid_write(offset, val, size);
151
+ if ((a->cmode & 1) && a->cmode < 12) {
271
+
152
+ if (a->op) {
272
+ switch (offset) {
153
+ /*
273
+ case REG_PRCTL: /* Control */
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
274
+ s->control = val;
155
+ * so the VBIC becomes a logical AND operation.
275
+
156
+ */
276
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
157
+ fn = gen_helper_mve_vandi;
277
+ (s->control & REG_PRCTL_WRITE)) {
158
+ } else {
278
+ uint32_t id = s->control >> 16;
159
+ fn = gen_helper_mve_vorri;
279
+
280
+ if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) {
281
+ s->rdkey = ldl_be_p(&s->identifier.data[id]);
282
+ }
283
+ }
160
+ }
284
+ s->control &= ~REG_PRCTL_WRITE;
161
+ } else {
285
+ break;
162
+ /* There is one unallocated cmode/op combination in this space */
286
+ case REG_RDKEY: /* Read Key */
163
+ if (a->cmode == 15 && a->op == 1) {
287
+ break;
164
+ return false;
288
+ default:
165
+ }
289
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
290
+ __func__, (uint32_t)offset);
167
+ fn = gen_helper_mve_vmovi;
291
+ break;
292
+ }
168
+ }
169
+ return do_1imm(s, a, fn);
293
+}
170
+}
294
+
295
+static const MemoryRegionOps allwinner_sid_ops = {
296
+ .read = allwinner_sid_read,
297
+ .write = allwinner_sid_write,
298
+ .endianness = DEVICE_NATIVE_ENDIAN,
299
+ .valid = {
300
+ .min_access_size = 4,
301
+ .max_access_size = 4,
302
+ },
303
+ .impl.min_access_size = 4,
304
+};
305
+
306
+static void allwinner_sid_reset(DeviceState *dev)
307
+{
308
+ AwSidState *s = AW_SID(dev);
309
+
310
+ /* Set default values for registers */
311
+ s->control = 0;
312
+ s->rdkey = 0;
313
+}
314
+
315
+static void allwinner_sid_init(Object *obj)
316
+{
317
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
318
+ AwSidState *s = AW_SID(obj);
319
+
320
+ /* Memory mapping */
321
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
322
+ TYPE_AW_SID, 1 * KiB);
323
+ sysbus_init_mmio(sbd, &s->iomem);
324
+}
325
+
326
+static Property allwinner_sid_properties[] = {
327
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
328
+ DEFINE_PROP_END_OF_LIST()
329
+};
330
+
331
+static const VMStateDescription allwinner_sid_vmstate = {
332
+ .name = "allwinner-sid",
333
+ .version_id = 1,
334
+ .minimum_version_id = 1,
335
+ .fields = (VMStateField[]) {
336
+ VMSTATE_UINT32(control, AwSidState),
337
+ VMSTATE_UINT32(rdkey, AwSidState),
338
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1),
339
+ VMSTATE_END_OF_LIST()
340
+ }
341
+};
342
+
343
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
344
+{
345
+ DeviceClass *dc = DEVICE_CLASS(klass);
346
+
347
+ dc->reset = allwinner_sid_reset;
348
+ dc->vmsd = &allwinner_sid_vmstate;
349
+ device_class_set_props(dc, allwinner_sid_properties);
350
+}
351
+
352
+static const TypeInfo allwinner_sid_info = {
353
+ .name = TYPE_AW_SID,
354
+ .parent = TYPE_SYS_BUS_DEVICE,
355
+ .instance_init = allwinner_sid_init,
356
+ .instance_size = sizeof(AwSidState),
357
+ .class_init = allwinner_sid_class_init,
358
+};
359
+
360
+static void allwinner_sid_register(void)
361
+{
362
+ type_register_static(&allwinner_sid_info);
363
+}
364
+
365
+type_init(allwinner_sid_register)
366
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
367
index XXXXXXX..XXXXXXX 100644
368
--- a/hw/misc/trace-events
369
+++ b/hw/misc/trace-events
370
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
371
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
372
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
373
374
+# allwinner-sid.c
375
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
376
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
377
+
378
# eccmemctl.c
379
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
380
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
381
--
171
--
382
2.20.1
172
2.20.1
383
173
384
174
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
2
and VQSHLU.
3
Let's move the code which freezes which gic-version to
3
4
be applied in a dedicated function. We also now set by
4
The size-and-immediate encoding here is the same as Neon, and we
5
default the VIRT_GIC_VERSION_NO_SET. This eventually
5
handle it the same way neon-dp.decode does.
6
turns into the legacy v2 choice in the finalize() function.
6
7
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
11
Message-id: 20200311131618.7187-4-eric.auger@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
include/hw/arm/virt.h | 1 +
11
target/arm/helper-mve.h | 16 +++++++++++
15
hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------
12
target/arm/mve.decode | 23 +++++++++++++++
16
2 files changed, 34 insertions(+), 21 deletions(-)
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
17
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
18
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
15
4 files changed, 147 insertions(+)
19
index XXXXXXX..XXXXXXX 100644
16
20
--- a/include/hw/arm/virt.h
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
21
+++ b/include/hw/arm/virt.h
18
index XXXXXXX..XXXXXXX 100644
22
@@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType {
19
--- a/target/arm/helper-mve.h
23
VIRT_GIC_VERSION_HOST,
20
+++ b/target/arm/helper-mve.h
24
VIRT_GIC_VERSION_2,
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
25
VIRT_GIC_VERSION_3,
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
+ VIRT_GIC_VERSION_NOSEL,
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
} VirtGICType;
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
28
25
+
29
typedef struct MemMapEntry {
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
index XXXXXXX..XXXXXXX 100644
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
--- a/hw/arm/virt.c
29
+
33
+++ b/hw/arm/virt.c
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
35
}
171
}
172
return do_1imm(s, a, fn);
36
}
173
}
37
174
+
38
+/*
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
39
+ * finalize_gic_version - Determines the final gic_version
176
+ bool negateshift)
40
+ * according to the gic-version property
41
+ *
42
+ * Default GIC type is v2
43
+ */
44
+static void finalize_gic_version(VirtMachineState *vms)
45
+{
177
+{
46
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
178
+ TCGv_ptr qd, qm;
47
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
179
+ int shift = a->shift;
48
+ if (!kvm_enabled()) {
180
+
49
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
181
+ if (!dc_isar_feature(aa32_mve, s) ||
50
+ error_report("gic-version=host requires KVM");
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
51
+ exit(1);
183
+ !fn) {
52
+ } else {
184
+ return false;
53
+ /* "max": currently means 3 for TCG */
185
+ }
54
+ vms->gic_version = VIRT_GIC_VERSION_3;
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
55
+ }
187
+ return true;
56
+ } else {
188
+ }
57
+ vms->gic_version = kvm_arm_vgic_probe();
189
+
58
+ if (!vms->gic_version) {
190
+ /*
59
+ error_report(
191
+ * When we handle a right shift insn using a left-shift helper
60
+ "Unable to determine GIC version supported by host");
192
+ * which permits a negative shift count to indicate a right-shift,
61
+ exit(1);
193
+ * we must negate the shift count.
62
+ }
194
+ */
63
+ }
195
+ if (negateshift) {
64
+ } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
196
+ shift = -shift;
65
+ vms->gic_version = VIRT_GIC_VERSION_2;
197
+ }
66
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
67
+}
206
+}
68
+
207
+
69
static void machvirt_init(MachineState *machine)
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
70
{
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
71
VirtMachineState *vms = VIRT_MACHINE(machine);
210
+ { \
72
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
73
/* We can probe only here because during property set
212
+ gen_helper_mve_##FN##b, \
74
* KVM is not available yet
213
+ gen_helper_mve_##FN##h, \
75
*/
214
+ gen_helper_mve_##FN##w, \
76
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
215
+ NULL, \
77
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
216
+ }; \
78
- if (!kvm_enabled()) {
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
79
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
218
+ }
80
- error_report("gic-version=host requires KVM");
219
+
81
- exit(1);
220
+DO_2SHIFT(VSHLI, vshli_u, false)
82
- } else {
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
83
- /* "max": currently means 3 for TCG */
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
84
- vms->gic_version = VIRT_GIC_VERSION_3;
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
85
- }
86
- } else {
87
- vms->gic_version = kvm_arm_vgic_probe();
88
- if (!vms->gic_version) {
89
- error_report(
90
- "Unable to determine GIC version supported by host");
91
- exit(1);
92
- }
93
- }
94
- }
95
+ finalize_gic_version(vms);
96
97
if (!cpu_type_valid(machine->cpu_type)) {
98
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
99
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
100
"Set on/off to enable/disable using "
101
"physical address space above 32 bits",
102
NULL);
103
- /* Default GIC type is v2 */
104
- vms->gic_version = VIRT_GIC_VERSION_2;
105
+ vms->gic_version = VIRT_GIC_VERSION_NOSEL;
106
object_property_add_str(obj, "gic-version", virt_get_gic_version,
107
virt_set_gic_version, NULL);
108
object_property_set_description(obj, "gic-version",
109
--
224
--
110
2.20.1
225
2.20.1
111
226
112
227
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
Various Allwinner System on Chip designs contain multiple processors
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
that can be configured and reset using the generic CPU Configuration
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
module interface. This commit adds support for the Allwinner CPU
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
6
configuration interface which emulates the following features:
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
7
17
8
* CPU reset
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
* CPU status
10
11
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/misc/Makefile.objs | 1 +
17
include/hw/arm/allwinner-h3.h | 3 +
18
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
19
hw/arm/allwinner-h3.c | 9 +-
20
hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++
21
hw/misc/trace-events | 5 +
22
6 files changed, 351 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/misc/allwinner-cpucfg.h
24
create mode 100644 hw/misc/allwinner-cpucfg.c
25
26
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
27
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/misc/Makefile.objs
20
--- a/target/arm/helper-mve.h
29
+++ b/hw/misc/Makefile.objs
21
+++ b/target/arm/helper-mve.h
30
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
31
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
32
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
33
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
25
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
common-obj-$(CONFIG_NSERIES) += cbus.o
29
+
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
39
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/allwinner-h3.h
47
--- a/target/arm/translate.h
41
+++ b/include/hw/arm/allwinner-h3.h
48
+++ b/target/arm/translate.h
42
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
43
#include "hw/timer/allwinner-a10-pit.h"
50
return x * 2 + 1;
44
#include "hw/intc/arm_gic.h"
45
#include "hw/misc/allwinner-h3-ccu.h"
46
+#include "hw/misc/allwinner-cpucfg.h"
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "target/arm/cpu.h"
49
50
@@ -XXX,XX +XXX,XX @@ enum {
51
AW_H3_GIC_CPU,
52
AW_H3_GIC_HYP,
53
AW_H3_GIC_VCPU,
54
+ AW_H3_CPUCFG,
55
AW_H3_SDRAM
56
};
57
58
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
59
const hwaddr *memmap;
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
+ AwCpuCfgState cpucfg;
63
AwH3SysCtrlState sysctrl;
64
GICState gic;
65
MemoryRegion sram_a1;
66
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h
67
new file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- /dev/null
70
+++ b/include/hw/misc/allwinner-cpucfg.h
71
@@ -XXX,XX +XXX,XX @@
72
+/*
73
+ * Allwinner CPU Configuration Module emulation
74
+ *
75
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
76
+ *
77
+ * This program is free software: you can redistribute it and/or modify
78
+ * it under the terms of the GNU General Public License as published by
79
+ * the Free Software Foundation, either version 2 of the License, or
80
+ * (at your option) any later version.
81
+ *
82
+ * This program is distributed in the hope that it will be useful,
83
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
84
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
85
+ * GNU General Public License for more details.
86
+ *
87
+ * You should have received a copy of the GNU General Public License
88
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
89
+ */
90
+
91
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
92
+#define HW_MISC_ALLWINNER_CPUCFG_H
93
+
94
+#include "qom/object.h"
95
+#include "hw/sysbus.h"
96
+
97
+/**
98
+ * Object model
99
+ * @{
100
+ */
101
+
102
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
103
+#define AW_CPUCFG(obj) \
104
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
105
+
106
+/** @} */
107
+
108
+/**
109
+ * Allwinner CPU Configuration Module instance state
110
+ */
111
+typedef struct AwCpuCfgState {
112
+ /*< private >*/
113
+ SysBusDevice parent_obj;
114
+ /*< public >*/
115
+
116
+ MemoryRegion iomem;
117
+ uint32_t gen_ctrl;
118
+ uint32_t super_standby;
119
+ uint32_t entry_addr;
120
+
121
+} AwCpuCfgState;
122
+
123
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
124
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/arm/allwinner-h3.c
127
+++ b/hw/arm/allwinner-h3.c
128
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
129
[AW_H3_GIC_CPU] = 0x01c82000,
130
[AW_H3_GIC_HYP] = 0x01c84000,
131
[AW_H3_GIC_VCPU] = 0x01c86000,
132
+ [AW_H3_CPUCFG] = 0x01f01c00,
133
[AW_H3_SDRAM] = 0x40000000
134
};
135
136
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
137
{ "r_wdog", 0x01f01000, 1 * KiB },
138
{ "r_prcm", 0x01f01400, 1 * KiB },
139
{ "r_twd", 0x01f01800, 1 * KiB },
140
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
141
{ "r_cir-rx", 0x01f02000, 1 * KiB },
142
{ "r_twi", 0x01f02400, 1 * KiB },
143
{ "r_uart", 0x01f02800, 1 * KiB },
144
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
145
146
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
147
TYPE_AW_H3_SYSCTRL);
148
+
149
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
150
+ TYPE_AW_CPUCFG);
151
}
51
}
152
52
153
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
53
+static inline int rsub_64(DisasContext *s, int x)
154
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
155
qdev_init_nofail(DEVICE(&s->sysctrl));
156
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
157
158
+ /* CPU Configuration */
159
+ qdev_init_nofail(DEVICE(&s->cpucfg));
160
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
161
+
162
/* Universal Serial Bus */
163
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
164
qdev_get_gpio_in(DEVICE(&s->gic),
165
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
166
new file mode 100644
167
index XXXXXXX..XXXXXXX
168
--- /dev/null
169
+++ b/hw/misc/allwinner-cpucfg.c
170
@@ -XXX,XX +XXX,XX @@
171
+/*
172
+ * Allwinner CPU Configuration Module emulation
173
+ *
174
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
175
+ *
176
+ * This program is free software: you can redistribute it and/or modify
177
+ * it under the terms of the GNU General Public License as published by
178
+ * the Free Software Foundation, either version 2 of the License, or
179
+ * (at your option) any later version.
180
+ *
181
+ * This program is distributed in the hope that it will be useful,
182
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
183
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
184
+ * GNU General Public License for more details.
185
+ *
186
+ * You should have received a copy of the GNU General Public License
187
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
188
+ */
189
+
190
+#include "qemu/osdep.h"
191
+#include "qemu/units.h"
192
+#include "hw/sysbus.h"
193
+#include "migration/vmstate.h"
194
+#include "qemu/log.h"
195
+#include "qemu/module.h"
196
+#include "qemu/error-report.h"
197
+#include "qemu/timer.h"
198
+#include "hw/core/cpu.h"
199
+#include "target/arm/arm-powerctl.h"
200
+#include "target/arm/cpu.h"
201
+#include "hw/misc/allwinner-cpucfg.h"
202
+#include "trace.h"
203
+
204
+/* CPUCFG register offsets */
205
+enum {
206
+ REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
207
+ REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
208
+ REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
209
+ REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
210
+ REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
211
+ REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
212
+ REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
213
+ REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
214
+ REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
215
+ REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
216
+ REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
217
+ REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
218
+ REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
219
+ REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
220
+ REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
221
+ REG_GEN_CTRL = 0x0184, /* General Control */
222
+ REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */
223
+ REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */
224
+ REG_DBG_EXTERN = 0x01E4, /* Debug External */
225
+ REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
226
+ REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
227
+ REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
228
+};
229
+
230
+/* CPUCFG register flags */
231
+enum {
232
+ CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)),
233
+ CPUX_STATUS_SMP = (1 << 0),
234
+ CPU_SYS_RESET_RELEASED = (1 << 0),
235
+ CLK_GATING_ENABLE = ((1 << 8) | 0xF),
236
+};
237
+
238
+/* CPUCFG register reset values */
239
+enum {
240
+ REG_CLK_GATING_RST = 0x0000010F,
241
+ REG_GEN_CTRL_RST = 0x00000020,
242
+ REG_SUPER_STANDBY_RST = 0x0,
243
+ REG_CNT64_CTRL_RST = 0x0,
244
+};
245
+
246
+/* CPUCFG constants */
247
+enum {
248
+ CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
249
+};
250
+
251
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
252
+{
54
+{
253
+ int ret;
55
+ return 64 - x;
254
+
255
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
256
+
257
+ ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
258
+ if (!target_cpu) {
259
+ /*
260
+ * Called with a bogus value for cpu_id. Guest error will
261
+ * already have been logged, we can simply return here.
262
+ */
263
+ return;
264
+ }
265
+ bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
266
+
267
+ ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
268
+ CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64);
269
+ if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
270
+ error_report("%s: failed to bring up CPU %d: err %d",
271
+ __func__, cpu_id, ret);
272
+ return;
273
+ }
274
+}
56
+}
275
+
57
+
276
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
58
+static inline int rsub_32(DisasContext *s, int x)
277
+ unsigned size)
278
+{
59
+{
279
+ const AwCpuCfgState *s = AW_CPUCFG(opaque);
60
+ return 32 - x;
280
+ uint64_t val = 0;
281
+
282
+ switch (offset) {
283
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
284
+ case REG_CPU_SYS_RST: /* CPU System Reset */
285
+ val = CPU_SYS_RESET_RELEASED;
286
+ break;
287
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
288
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
289
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
290
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
291
+ val = CPUX_RESET_RELEASED;
292
+ break;
293
+ case REG_CPU0_CTRL: /* CPU#0 Control */
294
+ case REG_CPU1_CTRL: /* CPU#1 Control */
295
+ case REG_CPU2_CTRL: /* CPU#2 Control */
296
+ case REG_CPU3_CTRL: /* CPU#3 Control */
297
+ val = 0;
298
+ break;
299
+ case REG_CPU0_STATUS: /* CPU#0 Status */
300
+ case REG_CPU1_STATUS: /* CPU#1 Status */
301
+ case REG_CPU2_STATUS: /* CPU#2 Status */
302
+ case REG_CPU3_STATUS: /* CPU#3 Status */
303
+ val = CPUX_STATUS_SMP;
304
+ break;
305
+ case REG_CLK_GATING: /* CPU Clock Gating */
306
+ val = CLK_GATING_ENABLE;
307
+ break;
308
+ case REG_GEN_CTRL: /* General Control */
309
+ val = s->gen_ctrl;
310
+ break;
311
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
312
+ val = s->super_standby;
313
+ break;
314
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
315
+ val = s->entry_addr;
316
+ break;
317
+ case REG_DBG_EXTERN: /* Debug External */
318
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
319
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
320
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
321
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
322
+ __func__, (uint32_t)offset);
323
+ break;
324
+ default:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ }
329
+
330
+ trace_allwinner_cpucfg_read(offset, val, size);
331
+
332
+ return val;
333
+}
61
+}
334
+
62
+
335
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
63
+static inline int rsub_16(DisasContext *s, int x)
336
+ uint64_t val, unsigned size)
337
+{
64
+{
338
+ AwCpuCfgState *s = AW_CPUCFG(opaque);
65
+ return 16 - x;
339
+
340
+ trace_allwinner_cpucfg_write(offset, val, size);
341
+
342
+ switch (offset) {
343
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
344
+ case REG_CPU_SYS_RST: /* CPU System Reset */
345
+ break;
346
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
347
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
348
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
349
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
350
+ if (val) {
351
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6);
352
+ }
353
+ break;
354
+ case REG_CPU0_CTRL: /* CPU#0 Control */
355
+ case REG_CPU1_CTRL: /* CPU#1 Control */
356
+ case REG_CPU2_CTRL: /* CPU#2 Control */
357
+ case REG_CPU3_CTRL: /* CPU#3 Control */
358
+ case REG_CPU0_STATUS: /* CPU#0 Status */
359
+ case REG_CPU1_STATUS: /* CPU#1 Status */
360
+ case REG_CPU2_STATUS: /* CPU#2 Status */
361
+ case REG_CPU3_STATUS: /* CPU#3 Status */
362
+ case REG_CLK_GATING: /* CPU Clock Gating */
363
+ break;
364
+ case REG_GEN_CTRL: /* General Control */
365
+ s->gen_ctrl = val;
366
+ break;
367
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
368
+ s->super_standby = val;
369
+ break;
370
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
371
+ s->entry_addr = val;
372
+ break;
373
+ case REG_DBG_EXTERN: /* Debug External */
374
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
375
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
376
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
377
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
378
+ __func__, (uint32_t)offset);
379
+ break;
380
+ default:
381
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
382
+ __func__, (uint32_t)offset);
383
+ break;
384
+ }
385
+}
66
+}
386
+
67
+
387
+static const MemoryRegionOps allwinner_cpucfg_ops = {
68
+static inline int rsub_8(DisasContext *s, int x)
388
+ .read = allwinner_cpucfg_read,
389
+ .write = allwinner_cpucfg_write,
390
+ .endianness = DEVICE_NATIVE_ENDIAN,
391
+ .valid = {
392
+ .min_access_size = 4,
393
+ .max_access_size = 4,
394
+ },
395
+ .impl.min_access_size = 4,
396
+};
397
+
398
+static void allwinner_cpucfg_reset(DeviceState *dev)
399
+{
69
+{
400
+ AwCpuCfgState *s = AW_CPUCFG(dev);
70
+ return 8 - x;
401
+
402
+ /* Set default values for registers */
403
+ s->gen_ctrl = REG_GEN_CTRL_RST;
404
+ s->super_standby = REG_SUPER_STANDBY_RST;
405
+ s->entry_addr = 0;
406
+}
71
+}
407
+
72
+
408
+static void allwinner_cpucfg_init(Object *obj)
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
409
+{
74
{
410
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
75
return (dc->features & (1ULL << feature)) != 0;
411
+ AwCpuCfgState *s = AW_CPUCFG(obj);
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/mve.decode
79
+++ b/target/arm/mve.decode
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
412
+
88
+
413
+ /* Memory mapping */
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
414
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
90
+ size=0 shift=%rshift_i3
415
+ TYPE_AW_CPUCFG, 1 * KiB);
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
416
+ sysbus_init_mmio(sbd, &s->iomem);
92
+ size=1 shift=%rshift_i4
417
+}
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
418
+
95
+
419
+static const VMStateDescription allwinner_cpucfg_vmstate = {
96
# Vector loads and stores
420
+ .name = "allwinner-cpucfg",
97
421
+ .version_id = 1,
98
# Widening loads and narrowing stores:
422
+ .minimum_version_id = 1,
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
423
+ .fields = (VMStateField[]) {
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
424
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
425
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
426
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
427
+ VMSTATE_END_OF_LIST()
428
+ }
429
+};
430
+
103
+
431
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
432
+{
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
433
+ DeviceClass *dc = DEVICE_CLASS(klass);
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
434
+
107
+
435
+ dc->reset = allwinner_cpucfg_reset;
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
436
+ dc->vmsd = &allwinner_cpucfg_vmstate;
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
437
+}
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
438
+
111
+
439
+static const TypeInfo allwinner_cpucfg_info = {
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
440
+ .name = TYPE_AW_CPUCFG,
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
441
+ .parent = TYPE_SYS_BUS_DEVICE,
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
442
+ .instance_init = allwinner_cpucfg_init,
443
+ .instance_size = sizeof(AwCpuCfgState),
444
+ .class_init = allwinner_cpucfg_class_init,
445
+};
446
+
115
+
447
+static void allwinner_cpucfg_register(void)
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
448
+{
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
449
+ type_register_static(&allwinner_cpucfg_info);
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
450
+}
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
451
+
452
+type_init(allwinner_cpucfg_register)
453
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
454
index XXXXXXX..XXXXXXX 100644
120
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/misc/trace-events
121
--- a/target/arm/mve_helper.c
456
+++ b/hw/misc/trace-events
122
+++ b/target/arm/mve_helper.c
457
@@ -XXX,XX +XXX,XX @@
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
458
# See docs/devel/tracing.txt for syntax documentation.
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
459
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
460
+# allwinner-cpucfg.c
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
461
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32
127
+#define DO_2SHIFT_S(OP, FN) \
462
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
463
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
464
+
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
465
# eccmemctl.c
131
466
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
132
#define DO_2SHIFT_SAT_U(OP, FN) \
467
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
163
}
164
165
-static inline int rsub_64(DisasContext *s, int x)
166
-{
167
- return 64 - x;
168
-}
169
-
170
-static inline int rsub_32(DisasContext *s, int x)
171
-{
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
468
--
186
--
469
2.20.1
187
2.20.1
470
188
471
189
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
for non-volatile system date and time keeping. This commit adds a generic
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
6
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
9
---
7
The following RTC functionality and features are implemented:
10
target/arm/helper-mve.h | 9 +++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
8
15
9
* Year-Month-Day read/write
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
10
* Hour-Minute-Second read/write
11
* General Purpose storage
12
13
The following boards are extended with the RTC device:
14
15
* Cubieboard (hw/arm/cubieboard.c)
16
* Orange Pi PC (hw/arm/orangepi.c)
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/rtc/Makefile.objs | 1 +
24
include/hw/arm/allwinner-a10.h | 2 +
25
include/hw/arm/allwinner-h3.h | 3 +
26
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
27
hw/arm/allwinner-a10.c | 8 +
28
hw/arm/allwinner-h3.c | 9 +-
29
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
30
hw/rtc/trace-events | 4 +
31
8 files changed, 571 insertions(+), 1 deletion(-)
32
create mode 100644 include/hw/rtc/allwinner-rtc.h
33
create mode 100644 hw/rtc/allwinner-rtc.c
34
35
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
36
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/rtc/Makefile.objs
18
--- a/target/arm/helper-mve.h
38
+++ b/hw/rtc/Makefile.objs
19
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o
24
+
44
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
45
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/arm/allwinner-a10.h
35
--- a/target/arm/mve.decode
47
+++ b/include/hw/arm/allwinner-a10.h
36
+++ b/target/arm/mve.decode
48
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
49
#include "hw/ide/ahci.h"
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
50
#include "hw/usb/hcd-ohci.h"
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
51
#include "hw/usb/hcd-ehci.h"
40
52
+#include "hw/rtc/allwinner-rtc.h"
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
53
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
54
#include "target/arm/cpu.h"
43
+# VSHLL encoding T2 where shift == esize
55
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
45
+ qd=%qd qm=%qm size=0 shift=8
57
AwEmacState emac;
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
58
AllwinnerAHCIState sata;
47
+ qd=%qd qm=%qm size=1 shift=16
59
AwSdHostState mmc0;
60
+ AwRtcState rtc;
61
MemoryRegion sram_a;
62
EHCISysBusState ehci[AW_A10_NUM_USB];
63
OHCISysBusState ohci[AW_A10_NUM_USB];
64
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/include/hw/arm/allwinner-h3.h
67
+++ b/include/hw/arm/allwinner-h3.h
68
@@ -XXX,XX +XXX,XX @@
69
#include "hw/misc/allwinner-sid.h"
70
#include "hw/sd/allwinner-sdhost.h"
71
#include "hw/net/allwinner-sun8i-emac.h"
72
+#include "hw/rtc/allwinner-rtc.h"
73
#include "target/arm/cpu.h"
74
#include "sysemu/block-backend.h"
75
76
@@ -XXX,XX +XXX,XX @@ enum {
77
AW_H3_GIC_CPU,
78
AW_H3_GIC_HYP,
79
AW_H3_GIC_VCPU,
80
+ AW_H3_RTC,
81
AW_H3_CPUCFG,
82
AW_H3_SDRAM
83
};
84
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
85
AwSidState sid;
86
AwSdHostState mmc0;
87
AwSun8iEmacState emac;
88
+ AwRtcState rtc;
89
GICState gic;
90
MemoryRegion sram_a1;
91
MemoryRegion sram_a2;
92
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
93
new file mode 100644
94
index XXXXXXX..XXXXXXX
95
--- /dev/null
96
+++ b/include/hw/rtc/allwinner-rtc.h
97
@@ -XXX,XX +XXX,XX @@
98
+/*
99
+ * Allwinner Real Time Clock emulation
100
+ *
101
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
102
+ *
103
+ * This program is free software: you can redistribute it and/or modify
104
+ * it under the terms of the GNU General Public License as published by
105
+ * the Free Software Foundation, either version 2 of the License, or
106
+ * (at your option) any later version.
107
+ *
108
+ * This program is distributed in the hope that it will be useful,
109
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
110
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
111
+ * GNU General Public License for more details.
112
+ *
113
+ * You should have received a copy of the GNU General Public License
114
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
115
+ */
116
+
48
+
117
+#ifndef HW_MISC_ALLWINNER_RTC_H
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
118
+#define HW_MISC_ALLWINNER_RTC_H
50
%rshift_i5 16:5 !function=rsub_32
119
+
51
%rshift_i4 16:4 !function=rsub_16
120
+#include "qom/object.h"
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
121
+#include "hw/sysbus.h"
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
122
+
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
123
+/**
55
124
+ * Constants
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
125
+ * @{
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
126
+ */
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
127
+
59
+# overlaps what would be size=0b11 VMULH/VRMULH
128
+/** Highest register address used by RTC device */
129
+#define AW_RTC_REGS_MAXADDR (0x200)
130
+
131
+/** Total number of known registers */
132
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
133
+
134
+/** @} */
135
+
136
+/**
137
+ * Object model types
138
+ * @{
139
+ */
140
+
141
+/** Generic Allwinner RTC device (abstract) */
142
+#define TYPE_AW_RTC "allwinner-rtc"
143
+
144
+/** Allwinner RTC sun4i family (A10, A12) */
145
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
146
+
147
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
148
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
149
+
150
+/** Allwinner RTC sun7i family (A20) */
151
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
152
+
153
+/** @} */
154
+
155
+/**
156
+ * Object model macros
157
+ * @{
158
+ */
159
+
160
+#define AW_RTC(obj) \
161
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
162
+#define AW_RTC_CLASS(klass) \
163
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
164
+#define AW_RTC_GET_CLASS(obj) \
165
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
166
+
167
+/** @} */
168
+
169
+/**
170
+ * Allwinner RTC per-object instance state.
171
+ */
172
+typedef struct AwRtcState {
173
+ /*< private >*/
174
+ SysBusDevice parent_obj;
175
+ /*< public >*/
176
+
177
+ /**
178
+ * Actual year represented by the device when year counter is zero
179
+ *
180
+ * Can be overridden by the user using the corresponding 'base-year'
181
+ * property. The base year used by the target OS driver can vary, for
182
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
183
+ */
184
+ int base_year;
185
+
186
+ /** Maps I/O registers in physical memory */
187
+ MemoryRegion iomem;
188
+
189
+ /** Array of hardware registers */
190
+ uint32_t regs[AW_RTC_REGS_NUM];
191
+
192
+} AwRtcState;
193
+
194
+/**
195
+ * Allwinner RTC class-level struct.
196
+ *
197
+ * This struct is filled by each sunxi device specific code
198
+ * such that the generic code can use this struct to support
199
+ * all devices.
200
+ */
201
+typedef struct AwRtcClass {
202
+ /*< private >*/
203
+ SysBusDeviceClass parent_class;
204
+ /*< public >*/
205
+
206
+ /** Defines device specific register map */
207
+ const uint8_t *regmap;
208
+
209
+ /** Size of the regmap in bytes */
210
+ size_t regmap_size;
211
+
212
+ /**
213
+ * Read device specific register
214
+ *
215
+ * @offset: register offset to read
216
+ * @return true if register read successful, false otherwise
217
+ */
218
+ bool (*read)(AwRtcState *s, uint32_t offset);
219
+
220
+ /**
221
+ * Write device specific register
222
+ *
223
+ * @offset: register offset to write
224
+ * @data: value to set in register
225
+ * @return true if register write successful, false otherwise
226
+ */
227
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
228
+
229
+} AwRtcClass;
230
+
231
+#endif /* HW_MISC_ALLWINNER_RTC_H */
232
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/arm/allwinner-a10.c
235
+++ b/hw/arm/allwinner-a10.c
236
@@ -XXX,XX +XXX,XX @@
237
#define AW_A10_EHCI_BASE 0x01c14000
238
#define AW_A10_OHCI_BASE 0x01c14400
239
#define AW_A10_SATA_BASE 0x01c18000
240
+#define AW_A10_RTC_BASE 0x01c20d00
241
242
static void aw_a10_init(Object *obj)
243
{
244
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
245
246
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
247
TYPE_AW_SDHOST_SUN4I);
248
+
249
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
250
+ TYPE_AW_RTC_SUN4I);
251
}
252
253
static void aw_a10_realize(DeviceState *dev, Error **errp)
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
255
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
256
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
257
"sd-bus", &error_abort);
258
+
259
+ /* RTC */
260
+ qdev_init_nofail(DEVICE(&s->rtc));
261
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
262
}
263
264
static void aw_a10_class_init(ObjectClass *oc, void *data)
265
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
266
index XXXXXXX..XXXXXXX 100644
267
--- a/hw/arm/allwinner-h3.c
268
+++ b/hw/arm/allwinner-h3.c
269
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
270
[AW_H3_GIC_CPU] = 0x01c82000,
271
[AW_H3_GIC_HYP] = 0x01c84000,
272
[AW_H3_GIC_VCPU] = 0x01c86000,
273
+ [AW_H3_RTC] = 0x01f00000,
274
[AW_H3_CPUCFG] = 0x01f01c00,
275
[AW_H3_SDRAM] = 0x40000000
276
};
277
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
278
{ "csi", 0x01cb0000, 320 * KiB },
279
{ "tve", 0x01e00000, 64 * KiB },
280
{ "hdmi", 0x01ee0000, 128 * KiB },
281
- { "rtc", 0x01f00000, 1 * KiB },
282
{ "r_timer", 0x01f00800, 1 * KiB },
283
{ "r_intc", 0x01f00c00, 1 * KiB },
284
{ "r_wdog", 0x01f01000, 1 * KiB },
285
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
286
"ram-addr", &error_abort);
287
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
288
"ram-size", &error_abort);
289
+
290
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
291
+ TYPE_AW_RTC_SUN6I);
292
}
293
294
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
295
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
296
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
297
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
298
299
+ /* RTC */
300
+ qdev_init_nofail(DEVICE(&s->rtc));
301
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
302
+
303
/* Unimplemented devices */
304
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
305
create_unimplemented_device(unimplemented[i].device_name,
306
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
307
new file mode 100644
308
index XXXXXXX..XXXXXXX
309
--- /dev/null
310
+++ b/hw/rtc/allwinner-rtc.c
311
@@ -XXX,XX +XXX,XX @@
312
+/*
313
+ * Allwinner Real Time Clock emulation
314
+ *
315
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
316
+ *
317
+ * This program is free software: you can redistribute it and/or modify
318
+ * it under the terms of the GNU General Public License as published by
319
+ * the Free Software Foundation, either version 2 of the License, or
320
+ * (at your option) any later version.
321
+ *
322
+ * This program is distributed in the hope that it will be useful,
323
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
324
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
325
+ * GNU General Public License for more details.
326
+ *
327
+ * You should have received a copy of the GNU General Public License
328
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
329
+ */
330
+
331
+#include "qemu/osdep.h"
332
+#include "qemu/units.h"
333
+#include "hw/sysbus.h"
334
+#include "migration/vmstate.h"
335
+#include "qemu/log.h"
336
+#include "qemu/module.h"
337
+#include "qemu-common.h"
338
+#include "hw/qdev-properties.h"
339
+#include "hw/rtc/allwinner-rtc.h"
340
+#include "trace.h"
341
+
342
+/* RTC registers */
343
+enum {
344
+ REG_LOSC = 1, /* Low Oscillator Control */
345
+ REG_YYMMDD, /* RTC Year-Month-Day */
346
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
347
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
348
+ REG_ALARM1_EN, /* Alarm1 Enable */
349
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
350
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
351
+ REG_GP0, /* General Purpose Register 0 */
352
+ REG_GP1, /* General Purpose Register 1 */
353
+ REG_GP2, /* General Purpose Register 2 */
354
+ REG_GP3, /* General Purpose Register 3 */
355
+
356
+ /* sun4i registers */
357
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
358
+ REG_CPUCFG, /* CPU Configuration Register */
359
+
360
+ /* sun6i registers */
361
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
362
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
363
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
364
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
365
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
366
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
367
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
368
+ REG_ALARM_CONFIG, /* Alarm Config */
369
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
370
+ REG_GP4, /* General Purpose Register 4 */
371
+ REG_GP5, /* General Purpose Register 5 */
372
+ REG_GP6, /* General Purpose Register 6 */
373
+ REG_GP7, /* General Purpose Register 7 */
374
+ REG_RTC_DBG, /* RTC Debug Register */
375
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
376
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
377
+ REG_IC_CHARA, /* IC Characteristics Register */
378
+};
379
+
380
+/* RTC register flags */
381
+enum {
382
+ REG_LOSC_YMD = (1 << 7),
383
+ REG_LOSC_HMS = (1 << 8),
384
+};
385
+
386
+/* RTC sun4i register map (offset to name) */
387
+const uint8_t allwinner_rtc_sun4i_regmap[] = {
388
+ [0x0000] = REG_LOSC,
389
+ [0x0004] = REG_YYMMDD,
390
+ [0x0008] = REG_HHMMSS,
391
+ [0x000C] = REG_ALARM1_DDHHMMSS,
392
+ [0x0010] = REG_ALARM1_WKHHMMSS,
393
+ [0x0014] = REG_ALARM1_EN,
394
+ [0x0018] = REG_ALARM1_IRQ_EN,
395
+ [0x001C] = REG_ALARM1_IRQ_STA,
396
+ [0x0020] = REG_GP0,
397
+ [0x0024] = REG_GP1,
398
+ [0x0028] = REG_GP2,
399
+ [0x002C] = REG_GP3,
400
+ [0x003C] = REG_CPUCFG,
401
+};
402
+
403
+/* RTC sun6i register map (offset to name) */
404
+const uint8_t allwinner_rtc_sun6i_regmap[] = {
405
+ [0x0000] = REG_LOSC,
406
+ [0x0004] = REG_LOSC_AUTOSTA,
407
+ [0x0008] = REG_INT_OSC_PRE,
408
+ [0x0010] = REG_YYMMDD,
409
+ [0x0014] = REG_HHMMSS,
410
+ [0x0020] = REG_ALARM0_COUNTER,
411
+ [0x0024] = REG_ALARM0_CUR_VLU,
412
+ [0x0028] = REG_ALARM0_ENABLE,
413
+ [0x002C] = REG_ALARM0_IRQ_EN,
414
+ [0x0030] = REG_ALARM0_IRQ_STA,
415
+ [0x0040] = REG_ALARM1_WKHHMMSS,
416
+ [0x0044] = REG_ALARM1_EN,
417
+ [0x0048] = REG_ALARM1_IRQ_EN,
418
+ [0x004C] = REG_ALARM1_IRQ_STA,
419
+ [0x0050] = REG_ALARM_CONFIG,
420
+ [0x0060] = REG_LOSC_OUT_GATING,
421
+ [0x0100] = REG_GP0,
422
+ [0x0104] = REG_GP1,
423
+ [0x0108] = REG_GP2,
424
+ [0x010C] = REG_GP3,
425
+ [0x0110] = REG_GP4,
426
+ [0x0114] = REG_GP5,
427
+ [0x0118] = REG_GP6,
428
+ [0x011C] = REG_GP7,
429
+ [0x0170] = REG_RTC_DBG,
430
+ [0x0180] = REG_GPL_HOLD_OUT,
431
+ [0x0190] = REG_VDD_RTC,
432
+ [0x01F0] = REG_IC_CHARA,
433
+};
434
+
435
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
436
+{
60
+{
437
+ /* no sun4i specific registers currently implemented */
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
438
+ return false;
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
63
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
439
+}
67
+}
440
+
68
+
441
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
442
+ uint32_t data)
443
+{
69
+{
444
+ /* no sun4i specific registers currently implemented */
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
445
+ return false;
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
446
+}
74
+}
447
+
75
+
448
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
449
+{
76
+{
450
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
451
+
79
+
452
+ switch (c->regmap[offset]) {
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
453
+ case REG_GP4: /* General Purpose Register 4 */
454
+ case REG_GP5: /* General Purpose Register 5 */
455
+ case REG_GP6: /* General Purpose Register 6 */
456
+ case REG_GP7: /* General Purpose Register 7 */
457
+ return true;
458
+ default:
459
+ break;
460
+ }
461
+ return false;
462
+}
81
+}
463
+
82
+
464
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
465
+ uint32_t data)
466
+{
83
+{
467
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
468
+
86
+
469
+ switch (c->regmap[offset]) {
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
470
+ case REG_GP4: /* General Purpose Register 4 */
471
+ case REG_GP5: /* General Purpose Register 5 */
472
+ case REG_GP6: /* General Purpose Register 6 */
473
+ case REG_GP7: /* General Purpose Register 7 */
474
+ return true;
475
+ default:
476
+ break;
477
+ }
478
+ return false;
479
+}
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
480
+
96
+
481
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
482
+ unsigned size)
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
483
+{
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
484
+ AwRtcState *s = AW_RTC(opaque);
485
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
486
+ uint64_t val = 0;
487
+
100
+
488
+ if (offset >= c->regmap_size) {
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
489
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
490
+ __func__, (uint32_t)offset);
103
+
491
+ return 0;
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
112
+++ b/target/arm/mve_helper.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
492
+ }
139
+ }
493
+
140
+
494
+ if (!c->regmap[offset]) {
141
+#define DO_VSHLL_ALL(OP, TOP) \
495
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
496
+ __func__, (uint32_t)offset);
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
497
+ return 0;
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
498
+ }
166
+ }
499
+
167
+
500
+ switch (c->regmap[offset]) {
168
+DO_VSHLL(VSHLL_BS, vshllbs)
501
+ case REG_LOSC: /* Low Oscillator Control */
169
+DO_VSHLL(VSHLL_BU, vshllbu)
502
+ val = s->regs[REG_LOSC];
170
+DO_VSHLL(VSHLL_TS, vshllts)
503
+ s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
171
+DO_VSHLL(VSHLL_TU, vshlltu)
504
+ break;
505
+ case REG_YYMMDD: /* RTC Year-Month-Day */
506
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
507
+ case REG_GP0: /* General Purpose Register 0 */
508
+ case REG_GP1: /* General Purpose Register 1 */
509
+ case REG_GP2: /* General Purpose Register 2 */
510
+ case REG_GP3: /* General Purpose Register 3 */
511
+ val = s->regs[c->regmap[offset]];
512
+ break;
513
+ default:
514
+ if (!c->read(s, offset)) {
515
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
516
+ __func__, (uint32_t)offset);
517
+ }
518
+ val = s->regs[c->regmap[offset]];
519
+ break;
520
+ }
521
+
522
+ trace_allwinner_rtc_read(offset, val);
523
+ return val;
524
+}
525
+
526
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
527
+ uint64_t val, unsigned size)
528
+{
529
+ AwRtcState *s = AW_RTC(opaque);
530
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
531
+
532
+ if (offset >= c->regmap_size) {
533
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
534
+ __func__, (uint32_t)offset);
535
+ return;
536
+ }
537
+
538
+ if (!c->regmap[offset]) {
539
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
540
+ __func__, (uint32_t)offset);
541
+ return;
542
+ }
543
+
544
+ trace_allwinner_rtc_write(offset, val);
545
+
546
+ switch (c->regmap[offset]) {
547
+ case REG_YYMMDD: /* RTC Year-Month-Day */
548
+ s->regs[REG_YYMMDD] = val;
549
+ s->regs[REG_LOSC] |= REG_LOSC_YMD;
550
+ break;
551
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
552
+ s->regs[REG_HHMMSS] = val;
553
+ s->regs[REG_LOSC] |= REG_LOSC_HMS;
554
+ break;
555
+ case REG_GP0: /* General Purpose Register 0 */
556
+ case REG_GP1: /* General Purpose Register 1 */
557
+ case REG_GP2: /* General Purpose Register 2 */
558
+ case REG_GP3: /* General Purpose Register 3 */
559
+ s->regs[c->regmap[offset]] = val;
560
+ break;
561
+ default:
562
+ if (!c->write(s, offset, val)) {
563
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
564
+ __func__, (uint32_t)offset);
565
+ }
566
+ break;
567
+ }
568
+}
569
+
570
+static const MemoryRegionOps allwinner_rtc_ops = {
571
+ .read = allwinner_rtc_read,
572
+ .write = allwinner_rtc_write,
573
+ .endianness = DEVICE_NATIVE_ENDIAN,
574
+ .valid = {
575
+ .min_access_size = 4,
576
+ .max_access_size = 4,
577
+ },
578
+ .impl.min_access_size = 4,
579
+};
580
+
581
+static void allwinner_rtc_reset(DeviceState *dev)
582
+{
583
+ AwRtcState *s = AW_RTC(dev);
584
+ struct tm now;
585
+
586
+ /* Clear registers */
587
+ memset(s->regs, 0, sizeof(s->regs));
588
+
589
+ /* Get current datetime */
590
+ qemu_get_timedate(&now, 0);
591
+
592
+ /* Set RTC with current datetime */
593
+ if (s->base_year > 1900) {
594
+ s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
595
+ ((now.tm_mon + 1) << 8) |
596
+ now.tm_mday;
597
+ s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
598
+ (now.tm_hour << 16) |
599
+ (now.tm_min << 8) |
600
+ now.tm_sec;
601
+ }
602
+}
603
+
604
+static void allwinner_rtc_init(Object *obj)
605
+{
606
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
607
+ AwRtcState *s = AW_RTC(obj);
608
+
609
+ /* Memory mapping */
610
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
611
+ TYPE_AW_RTC, 1 * KiB);
612
+ sysbus_init_mmio(sbd, &s->iomem);
613
+}
614
+
615
+static const VMStateDescription allwinner_rtc_vmstate = {
616
+ .name = "allwinner-rtc",
617
+ .version_id = 1,
618
+ .minimum_version_id = 1,
619
+ .fields = (VMStateField[]) {
620
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
621
+ VMSTATE_END_OF_LIST()
622
+ }
623
+};
624
+
625
+static Property allwinner_rtc_properties[] = {
626
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
627
+ DEFINE_PROP_END_OF_LIST(),
628
+};
629
+
630
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
631
+{
632
+ DeviceClass *dc = DEVICE_CLASS(klass);
633
+
634
+ dc->reset = allwinner_rtc_reset;
635
+ dc->vmsd = &allwinner_rtc_vmstate;
636
+ device_class_set_props(dc, allwinner_rtc_properties);
637
+}
638
+
639
+static void allwinner_rtc_sun4i_init(Object *obj)
640
+{
641
+ AwRtcState *s = AW_RTC(obj);
642
+ s->base_year = 2010;
643
+}
644
+
645
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
646
+{
647
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
648
+
649
+ arc->regmap = allwinner_rtc_sun4i_regmap;
650
+ arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
651
+ arc->read = allwinner_rtc_sun4i_read;
652
+ arc->write = allwinner_rtc_sun4i_write;
653
+}
654
+
655
+static void allwinner_rtc_sun6i_init(Object *obj)
656
+{
657
+ AwRtcState *s = AW_RTC(obj);
658
+ s->base_year = 1970;
659
+}
660
+
661
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
662
+{
663
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
664
+
665
+ arc->regmap = allwinner_rtc_sun6i_regmap;
666
+ arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
667
+ arc->read = allwinner_rtc_sun6i_read;
668
+ arc->write = allwinner_rtc_sun6i_write;
669
+}
670
+
671
+static void allwinner_rtc_sun7i_init(Object *obj)
672
+{
673
+ AwRtcState *s = AW_RTC(obj);
674
+ s->base_year = 1970;
675
+}
676
+
677
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
678
+{
679
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
680
+ allwinner_rtc_sun4i_class_init(klass, arc);
681
+}
682
+
683
+static const TypeInfo allwinner_rtc_info = {
684
+ .name = TYPE_AW_RTC,
685
+ .parent = TYPE_SYS_BUS_DEVICE,
686
+ .instance_init = allwinner_rtc_init,
687
+ .instance_size = sizeof(AwRtcState),
688
+ .class_init = allwinner_rtc_class_init,
689
+ .class_size = sizeof(AwRtcClass),
690
+ .abstract = true,
691
+};
692
+
693
+static const TypeInfo allwinner_rtc_sun4i_info = {
694
+ .name = TYPE_AW_RTC_SUN4I,
695
+ .parent = TYPE_AW_RTC,
696
+ .class_init = allwinner_rtc_sun4i_class_init,
697
+ .instance_init = allwinner_rtc_sun4i_init,
698
+};
699
+
700
+static const TypeInfo allwinner_rtc_sun6i_info = {
701
+ .name = TYPE_AW_RTC_SUN6I,
702
+ .parent = TYPE_AW_RTC,
703
+ .class_init = allwinner_rtc_sun6i_class_init,
704
+ .instance_init = allwinner_rtc_sun6i_init,
705
+};
706
+
707
+static const TypeInfo allwinner_rtc_sun7i_info = {
708
+ .name = TYPE_AW_RTC_SUN7I,
709
+ .parent = TYPE_AW_RTC,
710
+ .class_init = allwinner_rtc_sun7i_class_init,
711
+ .instance_init = allwinner_rtc_sun7i_init,
712
+};
713
+
714
+static void allwinner_rtc_register(void)
715
+{
716
+ type_register_static(&allwinner_rtc_info);
717
+ type_register_static(&allwinner_rtc_sun4i_info);
718
+ type_register_static(&allwinner_rtc_sun6i_info);
719
+ type_register_static(&allwinner_rtc_sun7i_info);
720
+}
721
+
722
+type_init(allwinner_rtc_register)
723
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
724
index XXXXXXX..XXXXXXX 100644
725
--- a/hw/rtc/trace-events
726
+++ b/hw/rtc/trace-events
727
@@ -XXX,XX +XXX,XX @@
728
# See docs/devel/tracing.txt for syntax documentation.
729
730
+# allwinner-rtc.c
731
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
732
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
733
+
734
# sun4v-rtc.c
735
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
736
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
737
--
172
--
738
2.20.1
173
2.20.1
739
174
740
175
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
2
3
3
A real Allwinner H3 SoC contains a Boot ROM which is the
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
first code that runs right after the SoC is powered on.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
The Boot ROM is responsible for loading user code (e.g. a bootloader)
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
6
from any of the supported external devices and writing the downloaded
7
---
7
code to internal SRAM. After loading the SoC begins executing the code
8
target/arm/helper-mve.h | 8 ++++++++
8
written to SRAM.
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
9
13
10
This commits adds emulation of the Boot ROM firmware setup functionality
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
11
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
12
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
13
sizes larger than 32KiB. For reference, this behaviour is documented
14
by the Linux Sunxi project wiki at:
15
16
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
24
hw/arm/allwinner-h3.c | 17 +++++++++++++++++
25
hw/arm/orangepi.c | 5 +++++
26
3 files changed, 43 insertions(+)
27
28
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
29
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-h3.h
16
--- a/target/arm/helper-mve.h
31
+++ b/include/hw/arm/allwinner-h3.h
17
+++ b/target/arm/helper-mve.h
32
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
#include "hw/sd/allwinner-sdhost.h"
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
#include "hw/net/allwinner-sun8i-emac.h"
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
#include "target/arm/cpu.h"
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+#include "sysemu/block-backend.h"
37
38
/**
39
* Allwinner H3 device list
40
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
41
MemoryRegion sram_c;
42
} AwH3State;
43
44
+/**
45
+ * Emulate Boot ROM firmware setup functionality.
46
+ *
47
+ * A real Allwinner H3 SoC contains a Boot ROM
48
+ * which is the first code that runs right after
49
+ * the SoC is powered on. The Boot ROM is responsible
50
+ * for loading user code (e.g. a bootloader) from any
51
+ * of the supported external devices and writing the
52
+ * downloaded code to internal SRAM. After loading the SoC
53
+ * begins executing the code written to SRAM.
54
+ *
55
+ * This function emulates the Boot ROM by copying 32 KiB
56
+ * of data from the given block device and writes it to
57
+ * the start of the first internal SRAM memory.
58
+ *
59
+ * @s: Allwinner H3 state object pointer
60
+ * @blk: Block backend device object pointer
61
+ */
62
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
63
+
22
+
64
#endif /* HW_ARM_ALLWINNER_H3_H */
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
65
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
66
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/allwinner-h3.c
32
--- a/target/arm/mve.decode
68
+++ b/hw/arm/allwinner-h3.c
33
+++ b/target/arm/mve.decode
69
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
70
#include "hw/char/serial.h"
35
71
#include "hw/misc/unimp.h"
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
72
#include "hw/usb/hcd-ehci.h"
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
73
+#include "hw/loader.h"
74
#include "sysemu/sysemu.h"
75
#include "hw/arm/allwinner-h3.h"
76
77
@@ -XXX,XX +XXX,XX @@ enum {
78
AW_H3_GIC_NUM_SPI = 128
79
};
80
81
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
82
+{
83
+ const int64_t rom_size = 32 * KiB;
84
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
85
+
38
+
86
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
39
+# Shift-and-insert
87
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
88
+ __func__);
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
89
+ return;
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
90
+ }
83
+ }
91
+
84
+
92
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
93
+ rom_size, s->memmap[AW_H3_SRAM_A1],
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
94
+ NULL, NULL, NULL, NULL, false);
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
95
+}
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
96
+
89
+
97
static void allwinner_h3_init(Object *obj)
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
98
{
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
99
AwH3State *s = AW_H3(obj);
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
100
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/orangepi.c
102
--- a/target/arm/translate-mve.c
103
+++ b/hw/arm/orangepi.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
machine->ram);
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
107
108
+ /* Load target kernel or start using BootROM */
108
+DO_2SHIFT(VSRI, vsri, false)
109
+ if (!machine->kernel_filename && blk_is_available(blk)) {
109
+DO_2SHIFT(VSLI, vsli, false)
110
+ /* Use Boot ROM to copy data from SD card to SRAM */
110
+
111
+ allwinner_h3_bootrom_setup(h3, blk);
111
#define DO_VSHLL(INSN, FN) \
112
+ }
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
113
{ \
114
orangepi_binfo.ram_size = machine->ram_size;
115
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
116
--
114
--
117
2.20.1
115
2.20.1
118
116
119
117
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
2
3
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
3
do_urshr() is borrowed from sve_helper.c.
4
which provides 10M/100M/1000M Ethernet connectivity. This commit
5
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
6
including emulation for the following functionality:
7
4
8
* DMA transfers
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
* MII interface
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
* Transmit CRC calculation
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 10 ++++++++++
10
target/arm/mve.decode | 11 +++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
11
14
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/net/Makefile.objs | 1 +
18
include/hw/arm/allwinner-h3.h | 3 +
19
include/hw/net/allwinner-sun8i-emac.h | 99 +++
20
hw/arm/allwinner-h3.c | 16 +-
21
hw/arm/orangepi.c | 3 +
22
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
23
hw/arm/Kconfig | 1 +
24
hw/net/Kconfig | 3 +
25
hw/net/trace-events | 10 +
26
9 files changed, 1006 insertions(+), 1 deletion(-)
27
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
28
create mode 100644 hw/net/allwinner-sun8i-emac.c
29
30
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
31
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/net/Makefile.objs
17
--- a/target/arm/helper-mve.h
33
+++ b/hw/net/Makefile.objs
18
+++ b/target/arm/helper-mve.h
34
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
23
+
39
common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
43
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
44
--- a/include/hw/arm/allwinner-h3.h
35
--- a/target/arm/mve.decode
45
+++ b/include/hw/arm/allwinner-h3.h
36
+++ b/target/arm/mve.decode
46
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
47
#include "hw/misc/allwinner-h3-sysctrl.h"
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
48
#include "hw/misc/allwinner-sid.h"
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
49
#include "hw/sd/allwinner-sdhost.h"
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
50
+#include "hw/net/allwinner-sun8i-emac.h"
41
+
51
#include "target/arm/cpu.h"
42
+# Narrowing shifts (which only support b and h sizes)
52
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
53
/**
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
54
@@ -XXX,XX +XXX,XX @@ enum {
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
55
AW_H3_UART1,
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
56
AW_H3_UART2,
47
+
57
AW_H3_UART3,
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
58
+ AW_H3_EMAC,
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
59
AW_H3_GIC_DIST,
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
60
AW_H3_GIC_CPU,
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
61
AW_H3_GIC_HYP,
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
62
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
53
index XXXXXXX..XXXXXXX 100644
63
AwH3SysCtrlState sysctrl;
54
--- a/target/arm/mve_helper.c
64
AwSidState sid;
55
+++ b/target/arm/mve_helper.c
65
AwSdHostState mmc0;
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
66
+ AwSun8iEmacState emac;
57
67
GICState gic;
58
DO_VSHLL_ALL(vshllb, false)
68
MemoryRegion sram_a1;
59
DO_VSHLL_ALL(vshllt, true)
69
MemoryRegion sram_a2;
60
+
70
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
71
new file mode 100644
72
index XXXXXXX..XXXXXXX
73
--- /dev/null
74
+++ b/include/hw/net/allwinner-sun8i-emac.h
75
@@ -XXX,XX +XXX,XX @@
76
+/*
61
+/*
77
+ * Allwinner Sun8i Ethernet MAC emulation
62
+ * Narrowing right shifts, taking a double sized input, shifting it
78
+ *
63
+ * and putting the result in either the top or bottom half of the output.
79
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
80
+ *
81
+ * This program is free software: you can redistribute it and/or modify
82
+ * it under the terms of the GNU General Public License as published by
83
+ * the Free Software Foundation, either version 2 of the License, or
84
+ * (at your option) any later version.
85
+ *
86
+ * This program is distributed in the hope that it will be useful,
87
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
88
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89
+ * GNU General Public License for more details.
90
+ *
91
+ * You should have received a copy of the GNU General Public License
92
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
93
+ */
65
+ */
94
+
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
95
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
96
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
68
+ void *vm, uint32_t shift) \
97
+
69
+ { \
98
+#include "qom/object.h"
70
+ LTYPE *m = vm; \
99
+#include "net/net.h"
71
+ TYPE *d = vd; \
100
+#include "hw/sysbus.h"
72
+ uint16_t mask = mve_element_mask(env); \
101
+
73
+ unsigned le; \
102
+/**
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
103
+ * Object model
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
104
+ * @{
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
105
+ */
77
+ } \
106
+
78
+ mve_advance_vpt(env); \
107
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
108
+#define AW_SUN8I_EMAC(obj) \
109
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
110
+
111
+/** @} */
112
+
113
+/**
114
+ * Allwinner Sun8i EMAC object instance state
115
+ */
116
+typedef struct AwSun8iEmacState {
117
+ /*< private >*/
118
+ SysBusDevice parent_obj;
119
+ /*< public >*/
120
+
121
+ /** Maps I/O registers in physical memory */
122
+ MemoryRegion iomem;
123
+
124
+ /** Interrupt output signal to notify CPU */
125
+ qemu_irq irq;
126
+
127
+ /** Generic Network Interface Controller (NIC) for networking API */
128
+ NICState *nic;
129
+
130
+ /** Generic Network Interface Controller (NIC) configuration */
131
+ NICConf conf;
132
+
133
+ /**
134
+ * @name Media Independent Interface (MII)
135
+ * @{
136
+ */
137
+
138
+ uint8_t mii_phy_addr; /**< PHY address */
139
+ uint32_t mii_cr; /**< Control */
140
+ uint32_t mii_st; /**< Status */
141
+ uint32_t mii_adv; /**< Advertised Abilities */
142
+
143
+ /** @} */
144
+
145
+ /**
146
+ * @name Hardware Registers
147
+ * @{
148
+ */
149
+
150
+ uint32_t basic_ctl0; /**< Basic Control 0 */
151
+ uint32_t basic_ctl1; /**< Basic Control 1 */
152
+ uint32_t int_en; /**< Interrupt Enable */
153
+ uint32_t int_sta; /**< Interrupt Status */
154
+ uint32_t frm_flt; /**< Receive Frame Filter */
155
+
156
+ uint32_t rx_ctl0; /**< Receive Control 0 */
157
+ uint32_t rx_ctl1; /**< Receive Control 1 */
158
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
159
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
160
+
161
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
162
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
163
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
164
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
165
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
166
+
167
+ uint32_t mii_cmd; /**< Management Interface Command */
168
+ uint32_t mii_data; /**< Management Interface Data */
169
+
170
+ /** @} */
171
+
172
+} AwSun8iEmacState;
173
+
174
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
175
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/arm/allwinner-h3.c
178
+++ b/hw/arm/allwinner-h3.c
179
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
180
[AW_H3_UART1] = 0x01c28400,
181
[AW_H3_UART2] = 0x01c28800,
182
[AW_H3_UART3] = 0x01c28c00,
183
+ [AW_H3_EMAC] = 0x01c30000,
184
[AW_H3_GIC_DIST] = 0x01c81000,
185
[AW_H3_GIC_CPU] = 0x01c82000,
186
[AW_H3_GIC_HYP] = 0x01c84000,
187
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
188
{ "twi1", 0x01c2b000, 1 * KiB },
189
{ "twi2", 0x01c2b400, 1 * KiB },
190
{ "scr", 0x01c2c400, 1 * KiB },
191
- { "emac", 0x01c30000, 64 * KiB },
192
{ "gpu", 0x01c40000, 64 * KiB },
193
{ "hstmr", 0x01c60000, 4 * KiB },
194
{ "dramcom", 0x01c62000, 4 * KiB },
195
@@ -XXX,XX +XXX,XX @@ enum {
196
AW_H3_GIC_SPI_OHCI2 = 77,
197
AW_H3_GIC_SPI_EHCI3 = 78,
198
AW_H3_GIC_SPI_OHCI3 = 79,
199
+ AW_H3_GIC_SPI_EMAC = 82
200
};
201
202
/* Allwinner H3 general constants */
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
206
TYPE_AW_SDHOST_SUN5I);
207
+
208
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
209
+ TYPE_AW_SUN8I_EMAC);
210
}
211
212
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
213
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
214
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
215
"sd-bus", &error_abort);
216
217
+ /* EMAC */
218
+ if (nd_table[0].used) {
219
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
220
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
221
+ }
222
+ qdev_init_nofail(DEVICE(&s->emac));
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
224
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
225
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
226
+
227
/* Universal Serial Bus */
228
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
229
qdev_get_gpio_in(DEVICE(&s->gic),
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
warn_report("Security Identifier value does not include H3 prefix");
236
}
237
238
+ /* Setup EMAC properties */
239
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
240
+
241
/* Mark H3 object realized */
242
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
243
244
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
245
new file mode 100644
246
index XXXXXXX..XXXXXXX
247
--- /dev/null
248
+++ b/hw/net/allwinner-sun8i-emac.c
249
@@ -XXX,XX +XXX,XX @@
250
+/*
251
+ * Allwinner Sun8i Ethernet MAC emulation
252
+ *
253
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
254
+ *
255
+ * This program is free software: you can redistribute it and/or modify
256
+ * it under the terms of the GNU General Public License as published by
257
+ * the Free Software Foundation, either version 2 of the License, or
258
+ * (at your option) any later version.
259
+ *
260
+ * This program is distributed in the hope that it will be useful,
261
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
262
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
263
+ * GNU General Public License for more details.
264
+ *
265
+ * You should have received a copy of the GNU General Public License
266
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
267
+ */
268
+
269
+#include "qemu/osdep.h"
270
+#include "qemu/units.h"
271
+#include "hw/sysbus.h"
272
+#include "migration/vmstate.h"
273
+#include "net/net.h"
274
+#include "hw/irq.h"
275
+#include "hw/qdev-properties.h"
276
+#include "qemu/log.h"
277
+#include "trace.h"
278
+#include "net/checksum.h"
279
+#include "qemu/module.h"
280
+#include "exec/cpu-common.h"
281
+#include "hw/net/allwinner-sun8i-emac.h"
282
+
283
+/* EMAC register offsets */
284
+enum {
285
+ REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */
286
+ REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */
287
+ REG_INT_STA = 0x0008, /* Interrupt Status */
288
+ REG_INT_EN = 0x000C, /* Interrupt Enable */
289
+ REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
290
+ REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
291
+ REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
292
+ REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
293
+ REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
294
+ REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
295
+ REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
296
+ REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
297
+ REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
298
+ REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
299
+ REG_MII_CMD = 0x0048, /* Management Interface Command */
300
+ REG_MII_DATA = 0x004C, /* Management Interface Data */
301
+ REG_ADDR_HIGH = 0x0050, /* MAC Address High */
302
+ REG_ADDR_LOW = 0x0054, /* MAC Address Low */
303
+ REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
304
+ REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
305
+ REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
306
+ REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
307
+ REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
308
+ REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
309
+ REG_RGMII_STA = 0x00D0, /* RGMII Status */
310
+};
311
+
312
+/* EMAC register flags */
313
+enum {
314
+ BASIC_CTL0_100Mbps = (0b11 << 2),
315
+ BASIC_CTL0_FD = (1 << 0),
316
+ BASIC_CTL1_SOFTRST = (1 << 0),
317
+};
318
+
319
+enum {
320
+ INT_STA_RGMII_LINK = (1 << 16),
321
+ INT_STA_RX_EARLY = (1 << 13),
322
+ INT_STA_RX_OVERFLOW = (1 << 12),
323
+ INT_STA_RX_TIMEOUT = (1 << 11),
324
+ INT_STA_RX_DMA_STOP = (1 << 10),
325
+ INT_STA_RX_BUF_UA = (1 << 9),
326
+ INT_STA_RX = (1 << 8),
327
+ INT_STA_TX_EARLY = (1 << 5),
328
+ INT_STA_TX_UNDERFLOW = (1 << 4),
329
+ INT_STA_TX_TIMEOUT = (1 << 3),
330
+ INT_STA_TX_BUF_UA = (1 << 2),
331
+ INT_STA_TX_DMA_STOP = (1 << 1),
332
+ INT_STA_TX = (1 << 0),
333
+};
334
+
335
+enum {
336
+ INT_EN_RX_EARLY = (1 << 13),
337
+ INT_EN_RX_OVERFLOW = (1 << 12),
338
+ INT_EN_RX_TIMEOUT = (1 << 11),
339
+ INT_EN_RX_DMA_STOP = (1 << 10),
340
+ INT_EN_RX_BUF_UA = (1 << 9),
341
+ INT_EN_RX = (1 << 8),
342
+ INT_EN_TX_EARLY = (1 << 5),
343
+ INT_EN_TX_UNDERFLOW = (1 << 4),
344
+ INT_EN_TX_TIMEOUT = (1 << 3),
345
+ INT_EN_TX_BUF_UA = (1 << 2),
346
+ INT_EN_TX_DMA_STOP = (1 << 1),
347
+ INT_EN_TX = (1 << 0),
348
+};
349
+
350
+enum {
351
+ TX_CTL0_TX_EN = (1 << 31),
352
+ TX_CTL1_TX_DMA_START = (1 << 31),
353
+ TX_CTL1_TX_DMA_EN = (1 << 30),
354
+ TX_CTL1_TX_FLUSH = (1 << 0),
355
+};
356
+
357
+enum {
358
+ RX_CTL0_RX_EN = (1 << 31),
359
+ RX_CTL0_STRIP_FCS = (1 << 28),
360
+ RX_CTL0_CRC_IPV4 = (1 << 27),
361
+};
362
+
363
+enum {
364
+ RX_CTL1_RX_DMA_START = (1 << 31),
365
+ RX_CTL1_RX_DMA_EN = (1 << 30),
366
+ RX_CTL1_RX_MD = (1 << 1),
367
+};
368
+
369
+enum {
370
+ RX_FRM_FLT_DIS_ADDR = (1 << 31),
371
+};
372
+
373
+enum {
374
+ MII_CMD_PHY_ADDR_SHIFT = (12),
375
+ MII_CMD_PHY_ADDR_MASK = (0xf000),
376
+ MII_CMD_PHY_REG_SHIFT = (4),
377
+ MII_CMD_PHY_REG_MASK = (0xf0),
378
+ MII_CMD_PHY_RW = (1 << 1),
379
+ MII_CMD_PHY_BUSY = (1 << 0),
380
+};
381
+
382
+enum {
383
+ TX_DMA_STA_STOP = (0b000),
384
+ TX_DMA_STA_RUN_FETCH = (0b001),
385
+ TX_DMA_STA_WAIT_STA = (0b010),
386
+};
387
+
388
+enum {
389
+ RX_DMA_STA_STOP = (0b000),
390
+ RX_DMA_STA_RUN_FETCH = (0b001),
391
+ RX_DMA_STA_WAIT_FRM = (0b011),
392
+};
393
+
394
+/* EMAC register reset values */
395
+enum {
396
+ REG_BASIC_CTL_1_RST = 0x08000000,
397
+};
398
+
399
+/* EMAC constants */
400
+enum {
401
+ AW_SUN8I_EMAC_MIN_PKT_SZ = 64
402
+};
403
+
404
+/* Transmit/receive frame descriptor */
405
+typedef struct FrameDescriptor {
406
+ uint32_t status;
407
+ uint32_t status2;
408
+ uint32_t addr;
409
+ uint32_t next;
410
+} FrameDescriptor;
411
+
412
+/* Frame descriptor flags */
413
+enum {
414
+ DESC_STATUS_CTL = (1 << 31),
415
+ DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
416
+};
417
+
418
+/* Transmit frame descriptor flags */
419
+enum {
420
+ TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
421
+ TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
422
+ TX_DESC_STATUS2_LAST_DESC = (1 << 30),
423
+ TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
424
+};
425
+
426
+/* Receive frame descriptor flags */
427
+enum {
428
+ RX_DESC_STATUS_FIRST_DESC = (1 << 9),
429
+ RX_DESC_STATUS_LAST_DESC = (1 << 8),
430
+ RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
431
+ RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
432
+ RX_DESC_STATUS_NO_BUF = (1 << 14),
433
+ RX_DESC_STATUS_HEADER_ERR = (1 << 7),
434
+ RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
435
+ RX_DESC_STATUS_CRC_ERR = (1 << 1),
436
+ RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
437
+ RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
438
+};
439
+
440
+/* MII register offsets */
441
+enum {
442
+ MII_REG_CR = (0x0), /* Control */
443
+ MII_REG_ST = (0x1), /* Status */
444
+ MII_REG_ID_HIGH = (0x2), /* Identifier High */
445
+ MII_REG_ID_LOW = (0x3), /* Identifier Low */
446
+ MII_REG_ADV = (0x4), /* Advertised abilities */
447
+ MII_REG_LPA = (0x5), /* Link partner abilities */
448
+};
449
+
450
+/* MII register flags */
451
+enum {
452
+ MII_REG_CR_RESET = (1 << 15),
453
+ MII_REG_CR_POWERDOWN = (1 << 11),
454
+ MII_REG_CR_10Mbit = (0),
455
+ MII_REG_CR_100Mbit = (1 << 13),
456
+ MII_REG_CR_1000Mbit = (1 << 6),
457
+ MII_REG_CR_AUTO_NEG = (1 << 12),
458
+ MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
459
+ MII_REG_CR_FULLDUPLEX = (1 << 8),
460
+};
461
+
462
+enum {
463
+ MII_REG_ST_100BASE_T4 = (1 << 15),
464
+ MII_REG_ST_100BASE_X_FD = (1 << 14),
465
+ MII_REG_ST_100BASE_X_HD = (1 << 13),
466
+ MII_REG_ST_10_FD = (1 << 12),
467
+ MII_REG_ST_10_HD = (1 << 11),
468
+ MII_REG_ST_100BASE_T2_FD = (1 << 10),
469
+ MII_REG_ST_100BASE_T2_HD = (1 << 9),
470
+ MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
471
+ MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
472
+ MII_REG_ST_LINK_UP = (1 << 2),
473
+};
474
+
475
+enum {
476
+ MII_REG_LPA_10_HD = (1 << 5),
477
+ MII_REG_LPA_10_FD = (1 << 6),
478
+ MII_REG_LPA_100_HD = (1 << 7),
479
+ MII_REG_LPA_100_FD = (1 << 8),
480
+ MII_REG_LPA_PAUSE = (1 << 10),
481
+ MII_REG_LPA_ASYMPAUSE = (1 << 11),
482
+};
483
+
484
+/* MII constants */
485
+enum {
486
+ MII_PHY_ID_HIGH = 0x0044,
487
+ MII_PHY_ID_LOW = 0x1400,
488
+};
489
+
490
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
491
+ bool link_active)
492
+{
493
+ if (link_active) {
494
+ s->mii_st |= MII_REG_ST_LINK_UP;
495
+ } else {
496
+ s->mii_st &= ~MII_REG_ST_LINK_UP;
497
+ }
498
+}
499
+
500
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
501
+ bool link_active)
502
+{
503
+ s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
504
+ MII_REG_CR_FULLDUPLEX;
505
+ s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
506
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
507
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
508
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
509
+ s->mii_adv = 0;
510
+
511
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
512
+}
513
+
514
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
515
+{
516
+ uint8_t addr, reg;
517
+
518
+ addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
519
+ reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
520
+
521
+ if (addr != s->mii_phy_addr) {
522
+ return;
523
+ }
79
+ }
524
+
80
+
525
+ /* Read or write a PHY register? */
81
+#define DO_VSHRN_ALL(OP, FN) \
526
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
527
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
528
+
86
+
529
+ switch (reg) {
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
530
+ case MII_REG_CR:
531
+ if (s->mii_data & MII_REG_CR_RESET) {
532
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
533
+ MII_REG_ST_LINK_UP);
534
+ } else {
535
+ s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
536
+ MII_REG_CR_AUTO_NEG_RESTART);
537
+ }
538
+ break;
539
+ case MII_REG_ADV:
540
+ s->mii_adv = s->mii_data;
541
+ break;
542
+ case MII_REG_ID_HIGH:
543
+ case MII_REG_ID_LOW:
544
+ case MII_REG_LPA:
545
+ break;
546
+ default:
547
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
548
+ "unknown MII register 0x%x\n", reg);
549
+ break;
550
+ }
551
+ } else {
552
+ switch (reg) {
553
+ case MII_REG_CR:
554
+ s->mii_data = s->mii_cr;
555
+ break;
556
+ case MII_REG_ST:
557
+ s->mii_data = s->mii_st;
558
+ break;
559
+ case MII_REG_ID_HIGH:
560
+ s->mii_data = MII_PHY_ID_HIGH;
561
+ break;
562
+ case MII_REG_ID_LOW:
563
+ s->mii_data = MII_PHY_ID_LOW;
564
+ break;
565
+ case MII_REG_ADV:
566
+ s->mii_data = s->mii_adv;
567
+ break;
568
+ case MII_REG_LPA:
569
+ s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
570
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
571
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
572
+ break;
573
+ default:
574
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
575
+ "unknown MII register 0x%x\n", reg);
576
+ s->mii_data = 0;
577
+ break;
578
+ }
579
+
580
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
581
+ }
582
+}
583
+
584
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
585
+{
88
+{
586
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
89
+ if (likely(sh < 64)) {
587
+}
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
588
+
91
+ } else if (sh == 64) {
589
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
92
+ return x >> 63;
590
+ size_t min_size)
591
+{
592
+ uint32_t paddr = desc->next;
593
+
594
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
595
+
596
+ if ((desc->status & DESC_STATUS_CTL) &&
597
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
598
+ return paddr;
599
+ } else {
93
+ } else {
600
+ return 0;
94
+ return 0;
601
+ }
95
+ }
602
+}
96
+}
603
+
97
+
604
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
605
+ uint32_t start_addr,
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
606
+ size_t min_size)
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
607
+{
101
index XXXXXXX..XXXXXXX 100644
608
+ uint32_t desc_addr = start_addr;
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
609
+
108
+
610
+ /* Note that the list is a cycle. Last entry points back to the head. */
109
+#define DO_2SHIFT_N(INSN, FN) \
611
+ while (desc_addr != 0) {
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
612
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
111
+ { \
613
+
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
614
+ if ((desc->status & DESC_STATUS_CTL) &&
113
+ gen_helper_mve_##FN##b, \
615
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
114
+ gen_helper_mve_##FN##h, \
616
+ return desc_addr;
115
+ }; \
617
+ } else if (desc->next == start_addr) {
116
+ return do_2shift(s, a, fns[a->size], false); \
618
+ break;
619
+ } else {
620
+ desc_addr = desc->next;
621
+ }
622
+ }
117
+ }
623
+
118
+
624
+ return 0;
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
625
+}
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
626
+
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
627
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
628
+ FrameDescriptor *desc,
629
+ size_t min_size)
630
+{
631
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
632
+}
633
+
634
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
635
+ FrameDescriptor *desc,
636
+ size_t min_size)
637
+{
638
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
639
+}
640
+
641
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
642
+ uint32_t phys_addr)
643
+{
644
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
645
+}
646
+
647
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
648
+{
649
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
650
+ FrameDescriptor desc;
651
+
652
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
653
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
654
+}
655
+
656
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
657
+ const uint8_t *buf,
658
+ size_t size)
659
+{
660
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
661
+ FrameDescriptor desc;
662
+ size_t bytes_left = size;
663
+ size_t desc_bytes = 0;
664
+ size_t pad_fcs_size = 4;
665
+ size_t padding = 0;
666
+
667
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
668
+ return -1;
669
+ }
670
+
671
+ s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
672
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
673
+ if (!s->rx_desc_curr) {
674
+ s->int_sta |= INT_STA_RX_BUF_UA;
675
+ }
676
+
677
+ /* Keep filling RX descriptors until the whole frame is written */
678
+ while (s->rx_desc_curr && bytes_left > 0) {
679
+ desc.status &= ~DESC_STATUS_CTL;
680
+ desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
681
+
682
+ if (bytes_left == size) {
683
+ desc.status |= RX_DESC_STATUS_FIRST_DESC;
684
+ }
685
+
686
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
687
+ (bytes_left + pad_fcs_size)) {
688
+ desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
689
+ desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
690
+ } else {
691
+ padding = pad_fcs_size;
692
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
693
+ padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
694
+ }
695
+
696
+ desc_bytes = (bytes_left);
697
+ desc.status |= RX_DESC_STATUS_LAST_DESC;
698
+ desc.status |= (bytes_left + padding)
699
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
700
+ }
701
+
702
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
703
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
704
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
705
+ desc_bytes);
706
+
707
+ /* Check if frame needs to raise the receive interrupt */
708
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
709
+ s->int_sta |= INT_STA_RX;
710
+ }
711
+
712
+ /* Increment variables */
713
+ buf += desc_bytes;
714
+ bytes_left -= desc_bytes;
715
+
716
+ /* Move to the next descriptor */
717
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
718
+ if (!s->rx_desc_curr) {
719
+ /* Not enough buffer space available */
720
+ s->int_sta |= INT_STA_RX_BUF_UA;
721
+ s->rx_desc_curr = s->rx_desc_head;
722
+ break;
723
+ }
724
+ }
725
+
726
+ /* Report receive DMA is finished */
727
+ s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
728
+ allwinner_sun8i_emac_update_irq(s);
729
+
730
+ return size;
731
+}
732
+
733
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
734
+{
735
+ NetClientState *nc = qemu_get_queue(s->nic);
736
+ FrameDescriptor desc;
737
+ size_t bytes = 0;
738
+ size_t packet_bytes = 0;
739
+ size_t transmitted = 0;
740
+ static uint8_t packet_buf[2048];
741
+
742
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
743
+
744
+ /* Read all transmit descriptors */
745
+ while (s->tx_desc_curr != 0) {
746
+
747
+ /* Read from physical memory into packet buffer */
748
+ bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
749
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
750
+ desc.status |= TX_DESC_STATUS_LENGTH_ERR;
751
+ break;
752
+ }
753
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
754
+ packet_bytes += bytes;
755
+ desc.status &= ~DESC_STATUS_CTL;
756
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
757
+
758
+ /* After the last descriptor, send the packet */
759
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
760
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
761
+ net_checksum_calculate(packet_buf, packet_bytes);
762
+ }
763
+
764
+ qemu_send_packet(nc, packet_buf, packet_bytes);
765
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
766
+ bytes);
767
+
768
+ packet_bytes = 0;
769
+ transmitted++;
770
+ }
771
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
772
+ }
773
+
774
+ /* Raise transmit completed interrupt */
775
+ if (transmitted > 0) {
776
+ s->int_sta |= INT_STA_TX;
777
+ s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
778
+ allwinner_sun8i_emac_update_irq(s);
779
+ }
780
+}
781
+
782
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
783
+{
784
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
785
+ NetClientState *nc = qemu_get_queue(s->nic);
786
+
787
+ trace_allwinner_sun8i_emac_reset();
788
+
789
+ s->mii_cmd = 0;
790
+ s->mii_data = 0;
791
+ s->basic_ctl0 = 0;
792
+ s->basic_ctl1 = REG_BASIC_CTL_1_RST;
793
+ s->int_en = 0;
794
+ s->int_sta = 0;
795
+ s->frm_flt = 0;
796
+ s->rx_ctl0 = 0;
797
+ s->rx_ctl1 = RX_CTL1_RX_MD;
798
+ s->rx_desc_head = 0;
799
+ s->rx_desc_curr = 0;
800
+ s->tx_ctl0 = 0;
801
+ s->tx_ctl1 = 0;
802
+ s->tx_desc_head = 0;
803
+ s->tx_desc_curr = 0;
804
+ s->tx_flowctl = 0;
805
+
806
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
807
+}
808
+
809
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
810
+ unsigned size)
811
+{
812
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
813
+ uint64_t value = 0;
814
+ FrameDescriptor desc;
815
+
816
+ switch (offset) {
817
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
818
+ value = s->basic_ctl0;
819
+ break;
820
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
821
+ value = s->basic_ctl1;
822
+ break;
823
+ case REG_INT_STA: /* Interrupt Status */
824
+ value = s->int_sta;
825
+ break;
826
+ case REG_INT_EN: /* Interupt Enable */
827
+ value = s->int_en;
828
+ break;
829
+ case REG_TX_CTL_0: /* Transmit Control 0 */
830
+ value = s->tx_ctl0;
831
+ break;
832
+ case REG_TX_CTL_1: /* Transmit Control 1 */
833
+ value = s->tx_ctl1;
834
+ break;
835
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
836
+ value = s->tx_flowctl;
837
+ break;
838
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
839
+ value = s->tx_desc_head;
840
+ break;
841
+ case REG_RX_CTL_0: /* Receive Control 0 */
842
+ value = s->rx_ctl0;
843
+ break;
844
+ case REG_RX_CTL_1: /* Receive Control 1 */
845
+ value = s->rx_ctl1;
846
+ break;
847
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
848
+ value = s->rx_desc_head;
849
+ break;
850
+ case REG_FRM_FLT: /* Receive Frame Filter */
851
+ value = s->frm_flt;
852
+ break;
853
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
854
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
855
+ break;
856
+ case REG_MII_CMD: /* Management Interface Command */
857
+ value = s->mii_cmd;
858
+ break;
859
+ case REG_MII_DATA: /* Management Interface Data */
860
+ value = s->mii_data;
861
+ break;
862
+ case REG_ADDR_HIGH: /* MAC Address High */
863
+ value = *(((uint32_t *) (s->conf.macaddr.a)) + 1);
864
+ break;
865
+ case REG_ADDR_LOW: /* MAC Address Low */
866
+ value = *(uint32_t *) (s->conf.macaddr.a);
867
+ break;
868
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
869
+ break;
870
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
871
+ value = s->tx_desc_curr;
872
+ break;
873
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
874
+ if (s->tx_desc_curr != 0) {
875
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
876
+ value = desc.addr;
877
+ } else {
878
+ value = 0;
879
+ }
880
+ break;
881
+ case REG_RX_DMA_STA: /* Receive DMA Status */
882
+ break;
883
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
884
+ value = s->rx_desc_curr;
885
+ break;
886
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
887
+ if (s->rx_desc_curr != 0) {
888
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
889
+ value = desc.addr;
890
+ } else {
891
+ value = 0;
892
+ }
893
+ break;
894
+ case REG_RGMII_STA: /* RGMII Status */
895
+ break;
896
+ default:
897
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
898
+ "EMAC register 0x" TARGET_FMT_plx "\n",
899
+ offset);
900
+ }
901
+
902
+ trace_allwinner_sun8i_emac_read(offset, value);
903
+ return value;
904
+}
905
+
906
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
907
+ uint64_t value, unsigned size)
908
+{
909
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
910
+ NetClientState *nc = qemu_get_queue(s->nic);
911
+
912
+ trace_allwinner_sun8i_emac_write(offset, value);
913
+
914
+ switch (offset) {
915
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
916
+ s->basic_ctl0 = value;
917
+ break;
918
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
919
+ if (value & BASIC_CTL1_SOFTRST) {
920
+ allwinner_sun8i_emac_reset(DEVICE(s));
921
+ value &= ~BASIC_CTL1_SOFTRST;
922
+ }
923
+ s->basic_ctl1 = value;
924
+ if (allwinner_sun8i_emac_can_receive(nc)) {
925
+ qemu_flush_queued_packets(nc);
926
+ }
927
+ break;
928
+ case REG_INT_STA: /* Interrupt Status */
929
+ s->int_sta &= ~value;
930
+ allwinner_sun8i_emac_update_irq(s);
931
+ break;
932
+ case REG_INT_EN: /* Interrupt Enable */
933
+ s->int_en = value;
934
+ allwinner_sun8i_emac_update_irq(s);
935
+ break;
936
+ case REG_TX_CTL_0: /* Transmit Control 0 */
937
+ s->tx_ctl0 = value;
938
+ break;
939
+ case REG_TX_CTL_1: /* Transmit Control 1 */
940
+ s->tx_ctl1 = value;
941
+ if (value & TX_CTL1_TX_DMA_EN) {
942
+ allwinner_sun8i_emac_transmit(s);
943
+ }
944
+ break;
945
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
946
+ s->tx_flowctl = value;
947
+ break;
948
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
949
+ s->tx_desc_head = value;
950
+ s->tx_desc_curr = value;
951
+ break;
952
+ case REG_RX_CTL_0: /* Receive Control 0 */
953
+ s->rx_ctl0 = value;
954
+ break;
955
+ case REG_RX_CTL_1: /* Receive Control 1 */
956
+ s->rx_ctl1 = value | RX_CTL1_RX_MD;
957
+ if ((value & RX_CTL1_RX_DMA_EN) &&
958
+ allwinner_sun8i_emac_can_receive(nc)) {
959
+ qemu_flush_queued_packets(nc);
960
+ }
961
+ break;
962
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
963
+ s->rx_desc_head = value;
964
+ s->rx_desc_curr = value;
965
+ break;
966
+ case REG_FRM_FLT: /* Receive Frame Filter */
967
+ s->frm_flt = value;
968
+ break;
969
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
970
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
971
+ break;
972
+ case REG_MII_CMD: /* Management Interface Command */
973
+ s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
974
+ allwinner_sun8i_emac_mii_cmd(s);
975
+ break;
976
+ case REG_MII_DATA: /* Management Interface Data */
977
+ s->mii_data = value;
978
+ break;
979
+ case REG_ADDR_HIGH: /* MAC Address High */
980
+ s->conf.macaddr.a[4] = (value & 0xff);
981
+ s->conf.macaddr.a[5] = (value & 0xff00) >> 8;
982
+ break;
983
+ case REG_ADDR_LOW: /* MAC Address Low */
984
+ s->conf.macaddr.a[0] = (value & 0xff);
985
+ s->conf.macaddr.a[1] = (value & 0xff00) >> 8;
986
+ s->conf.macaddr.a[2] = (value & 0xff0000) >> 16;
987
+ s->conf.macaddr.a[3] = (value & 0xff000000) >> 24;
988
+ break;
989
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
990
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
991
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
992
+ case REG_RX_DMA_STA: /* Receive DMA Status */
993
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
994
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
995
+ case REG_RGMII_STA: /* RGMII Status */
996
+ break;
997
+ default:
998
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
999
+ "EMAC register 0x" TARGET_FMT_plx "\n",
1000
+ offset);
1001
+ }
1002
+}
1003
+
1004
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
1005
+{
1006
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
1007
+
1008
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
1009
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
1010
+}
1011
+
1012
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
1013
+ .read = allwinner_sun8i_emac_read,
1014
+ .write = allwinner_sun8i_emac_write,
1015
+ .endianness = DEVICE_NATIVE_ENDIAN,
1016
+ .valid = {
1017
+ .min_access_size = 4,
1018
+ .max_access_size = 4,
1019
+ },
1020
+ .impl.min_access_size = 4,
1021
+};
1022
+
1023
+static NetClientInfo net_allwinner_sun8i_emac_info = {
1024
+ .type = NET_CLIENT_DRIVER_NIC,
1025
+ .size = sizeof(NICState),
1026
+ .can_receive = allwinner_sun8i_emac_can_receive,
1027
+ .receive = allwinner_sun8i_emac_receive,
1028
+ .link_status_changed = allwinner_sun8i_emac_set_link,
1029
+};
1030
+
1031
+static void allwinner_sun8i_emac_init(Object *obj)
1032
+{
1033
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1034
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
1035
+
1036
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
1037
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
1038
+ sysbus_init_mmio(sbd, &s->iomem);
1039
+ sysbus_init_irq(sbd, &s->irq);
1040
+}
1041
+
1042
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
1043
+{
1044
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
1045
+
1046
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
1047
+ s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
1048
+ object_get_typename(OBJECT(dev)), dev->id, s);
1049
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1050
+}
1051
+
1052
+static Property allwinner_sun8i_emac_properties[] = {
1053
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
1054
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
1055
+ DEFINE_PROP_END_OF_LIST(),
1056
+};
1057
+
1058
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
1059
+{
1060
+ AwSun8iEmacState *s = opaque;
1061
+
1062
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
1063
+
1064
+ return 0;
1065
+}
1066
+
1067
+static const VMStateDescription vmstate_aw_emac = {
1068
+ .name = "allwinner-sun8i-emac",
1069
+ .version_id = 1,
1070
+ .minimum_version_id = 1,
1071
+ .post_load = allwinner_sun8i_emac_post_load,
1072
+ .fields = (VMStateField[]) {
1073
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
1074
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
1075
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
1076
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
1077
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
1078
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
1079
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
1080
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
1081
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
1082
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
1083
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
1084
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
1085
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
1086
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
1087
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
1088
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
1089
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
1090
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
1091
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
1092
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
1093
+ VMSTATE_END_OF_LIST()
1094
+ }
1095
+};
1096
+
1097
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
1098
+{
1099
+ DeviceClass *dc = DEVICE_CLASS(klass);
1100
+
1101
+ dc->realize = allwinner_sun8i_emac_realize;
1102
+ dc->reset = allwinner_sun8i_emac_reset;
1103
+ dc->vmsd = &vmstate_aw_emac;
1104
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
1105
+}
1106
+
1107
+static const TypeInfo allwinner_sun8i_emac_info = {
1108
+ .name = TYPE_AW_SUN8I_EMAC,
1109
+ .parent = TYPE_SYS_BUS_DEVICE,
1110
+ .instance_size = sizeof(AwSun8iEmacState),
1111
+ .instance_init = allwinner_sun8i_emac_init,
1112
+ .class_init = allwinner_sun8i_emac_class_init,
1113
+};
1114
+
1115
+static void allwinner_sun8i_emac_register_types(void)
1116
+{
1117
+ type_register_static(&allwinner_sun8i_emac_info);
1118
+}
1119
+
1120
+type_init(allwinner_sun8i_emac_register_types)
1121
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1122
index XXXXXXX..XXXXXXX 100644
1123
--- a/hw/arm/Kconfig
1124
+++ b/hw/arm/Kconfig
1125
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
1126
config ALLWINNER_H3
1127
bool
1128
select ALLWINNER_A10_PIT
1129
+ select ALLWINNER_SUN8I_EMAC
1130
select SERIAL
1131
select ARM_TIMER
1132
select ARM_GIC
1133
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/hw/net/Kconfig
1136
+++ b/hw/net/Kconfig
1137
@@ -XXX,XX +XXX,XX @@ config MIPSNET
1138
config ALLWINNER_EMAC
1139
bool
1140
1141
+config ALLWINNER_SUN8I_EMAC
1142
+ bool
1143
+
1144
config IMX_FEC
1145
bool
1146
1147
diff --git a/hw/net/trace-events b/hw/net/trace-events
1148
index XXXXXXX..XXXXXXX 100644
1149
--- a/hw/net/trace-events
1150
+++ b/hw/net/trace-events
1151
@@ -XXX,XX +XXX,XX @@
1152
# See docs/devel/tracing.txt for syntax documentation.
1153
1154
+# allwinner-sun8i-emac.c
1155
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
1156
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
1157
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1158
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1159
+allwinner_sun8i_emac_reset(void) "HW reset"
1160
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
1161
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
1162
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
1163
+
1164
# etraxfs_eth.c
1165
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
1166
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
1167
--
123
--
1168
2.20.1
124
2.20.1
1169
125
1170
126
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
The Allwinner H3 System on Chip has an System Control
3
4
module that provides system wide generic controls and
4
do_srshr() is borrowed from sve_helper.c.
5
device information. This commit adds support for the
5
6
Allwinner H3 System Control module.
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
14
---
9
---
15
hw/misc/Makefile.objs | 1 +
10
target/arm/helper-mve.h | 30 +++++++++++
16
include/hw/arm/allwinner-h3.h | 3 +
11
target/arm/mve.decode | 28 ++++++++++
17
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
13
target/arm/translate-mve.c | 12 +++++
19
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
14
4 files changed, 174 insertions(+)
20
5 files changed, 219 insertions(+), 1 deletion(-)
15
21
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
22
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
17
index XXXXXXX..XXXXXXX 100644
23
18
--- a/target/arm/helper-mve.h
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
19
+++ b/target/arm/helper-mve.h
25
index XXXXXXX..XXXXXXX 100644
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
--- a/hw/misc/Makefile.objs
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+++ b/hw/misc/Makefile.objs
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
24
+
30
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
common-obj-$(CONFIG_NSERIES) += cbus.o
29
+
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
index XXXXXXX..XXXXXXX 100644
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
--- a/include/hw/arm/allwinner-h3.h
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+++ b/include/hw/arm/allwinner-h3.h
34
+
40
@@ -XXX,XX +XXX,XX @@
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
#include "hw/timer/allwinner-a10-pit.h"
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
#include "hw/intc/arm_gic.h"
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
#include "hw/misc/allwinner-h3-ccu.h"
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+#include "hw/misc/allwinner-h3-sysctrl.h"
39
+
45
#include "target/arm/cpu.h"
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
/**
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
@@ -XXX,XX +XXX,XX @@ enum {
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
AW_H3_SRAM_A1,
44
+
50
AW_H3_SRAM_A2,
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
AW_H3_SRAM_C,
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+ AW_H3_SYSCTRL,
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
AW_H3_EHCI0,
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
AW_H3_OHCI0,
49
+
55
AW_H3_EHCI1,
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
57
const hwaddr *memmap;
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
58
AwA10PITState timer;
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
59
AwH3ClockCtlState ccu;
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
60
+ AwH3SysCtrlState sysctrl;
55
index XXXXXXX..XXXXXXX 100644
61
GICState gic;
56
--- a/target/arm/mve.decode
62
MemoryRegion sram_a1;
57
+++ b/target/arm/mve.decode
63
MemoryRegion sram_a2;
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
64
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
65
new file mode 100644
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
66
index XXXXXXX..XXXXXXX
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
67
--- /dev/null
62
+
68
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
69
@@ -XXX,XX +XXX,XX @@
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
70
+/*
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
71
+ * Allwinner H3 System Control emulation
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
72
+ *
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
74
+ *
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
75
+ * This program is free software: you can redistribute it and/or modify
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
76
+ * it under the terms of the GNU General Public License as published by
71
+
77
+ * the Free Software Foundation, either version 2 of the License, or
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
78
+ * (at your option) any later version.
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
79
+ *
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
80
+ * This program is distributed in the hope that it will be useful,
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
76
+
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
83
+ * GNU General Public License for more details.
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
84
+ *
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
85
+ * You should have received a copy of the GNU General Public License
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
87
+ */
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
88
+
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
89
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
90
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
85
+
91
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
92
+#include "qom/object.h"
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
93
+#include "hw/sysbus.h"
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
94
+
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
95
+/**
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
96
+ * @name Constants
91
index XXXXXXX..XXXXXXX 100644
97
+ * @{
92
--- a/target/arm/mve_helper.c
98
+ */
93
+++ b/target/arm/mve_helper.c
99
+
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
100
+/** Highest register address used by System Control device */
95
}
101
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
105
+ sizeof(uint32_t)) + 1)
106
+
107
+/** @} */
108
+
109
+/**
110
+ * @name Object model
111
+ * @{
112
+ */
113
+
114
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
115
+#define AW_H3_SYSCTRL(obj) \
116
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
117
+
118
+/** @} */
119
+
120
+/**
121
+ * Allwinner H3 System Control object instance state
122
+ */
123
+typedef struct AwH3SysCtrlState {
124
+ /*< private >*/
125
+ SysBusDevice parent_obj;
126
+ /*< public >*/
127
+
128
+ /** Maps I/O registers in physical memory */
129
+ MemoryRegion iomem;
130
+
131
+ /** Array of hardware registers */
132
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
133
+
134
+} AwH3SysCtrlState;
135
+
136
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
137
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/hw/arm/allwinner-h3.c
140
+++ b/hw/arm/allwinner-h3.c
141
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
142
[AW_H3_SRAM_A1] = 0x00000000,
143
[AW_H3_SRAM_A2] = 0x00044000,
144
[AW_H3_SRAM_C] = 0x00010000,
145
+ [AW_H3_SYSCTRL] = 0x01c00000,
146
[AW_H3_EHCI0] = 0x01c1a000,
147
[AW_H3_OHCI0] = 0x01c1a400,
148
[AW_H3_EHCI1] = 0x01c1b000,
149
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
150
} unimplemented[] = {
151
{ "d-engine", 0x01000000, 4 * MiB },
152
{ "d-inter", 0x01400000, 128 * KiB },
153
- { "syscon", 0x01c00000, 4 * KiB },
154
{ "dma", 0x01c02000, 4 * KiB },
155
{ "nfdc", 0x01c03000, 4 * KiB },
156
{ "ts", 0x01c06000, 4 * KiB },
157
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
158
159
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
160
TYPE_AW_H3_CCU);
161
+
162
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
163
+ TYPE_AW_H3_SYSCTRL);
164
}
96
}
165
97
166
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
167
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
168
qdev_init_nofail(DEVICE(&s->ccu));
169
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
170
171
+ /* System Control */
172
+ qdev_init_nofail(DEVICE(&s->sysctrl));
173
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
174
+
175
/* Universal Serial Bus */
176
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
177
qdev_get_gpio_in(DEVICE(&s->gic),
178
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
179
new file mode 100644
180
index XXXXXXX..XXXXXXX
181
--- /dev/null
182
+++ b/hw/misc/allwinner-h3-sysctrl.c
183
@@ -XXX,XX +XXX,XX @@
184
+/*
185
+ * Allwinner H3 System Control emulation
186
+ *
187
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
188
+ *
189
+ * This program is free software: you can redistribute it and/or modify
190
+ * it under the terms of the GNU General Public License as published by
191
+ * the Free Software Foundation, either version 2 of the License, or
192
+ * (at your option) any later version.
193
+ *
194
+ * This program is distributed in the hope that it will be useful,
195
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
196
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
197
+ * GNU General Public License for more details.
198
+ *
199
+ * You should have received a copy of the GNU General Public License
200
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
201
+ */
202
+
203
+#include "qemu/osdep.h"
204
+#include "qemu/units.h"
205
+#include "hw/sysbus.h"
206
+#include "migration/vmstate.h"
207
+#include "qemu/log.h"
208
+#include "qemu/module.h"
209
+#include "hw/misc/allwinner-h3-sysctrl.h"
210
+
211
+/* System Control register offsets */
212
+enum {
213
+ REG_VER = 0x24, /* Version */
214
+ REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
215
+};
216
+
217
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
218
+
219
+/* System Control register reset values */
220
+enum {
221
+ REG_VER_RST = 0x0,
222
+ REG_EMAC_PHY_CLK_RST = 0x58000,
223
+};
224
+
225
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
226
+ unsigned size)
227
+{
99
+{
228
+ const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
100
+ if (likely(sh < 64)) {
229
+ const uint32_t idx = REG_INDEX(offset);
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
230
+
102
+ } else {
231
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
103
+ /* Rounding the sign bit always produces 0. */
232
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
233
+ __func__, (uint32_t)offset);
234
+ return 0;
104
+ return 0;
235
+ }
105
+ }
236
+
237
+ return s->regs[idx];
238
+}
106
+}
239
+
107
+
240
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
108
DO_VSHRN_ALL(vshrn, DO_SHR)
241
+ uint64_t val, unsigned size)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
242
+{
113
+{
243
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
114
+ if (val > max) {
244
+ const uint32_t idx = REG_INDEX(offset);
115
+ *satp = true;
245
+
116
+ return max;
246
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
117
+ } else if (val < min) {
247
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
118
+ *satp = true;
248
+ __func__, (uint32_t)offset);
119
+ return min;
249
+ return;
120
+ } else {
250
+ }
121
+ return val;
251
+
252
+ switch (offset) {
253
+ case REG_VER: /* Version */
254
+ break;
255
+ default:
256
+ s->regs[idx] = (uint32_t) val;
257
+ break;
258
+ }
122
+ }
259
+}
123
+}
260
+
124
+
261
+static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
125
+/* Saturating narrowing right shifts */
262
+ .read = allwinner_h3_sysctrl_read,
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
263
+ .write = allwinner_h3_sysctrl_write,
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
264
+ .endianness = DEVICE_NATIVE_ENDIAN,
128
+ void *vm, uint32_t shift) \
265
+ .valid = {
129
+ { \
266
+ .min_access_size = 4,
130
+ LTYPE *m = vm; \
267
+ .max_access_size = 4,
131
+ TYPE *d = vd; \
268
+ },
132
+ uint16_t mask = mve_element_mask(env); \
269
+ .impl.min_access_size = 4,
133
+ bool qc = false; \
270
+};
134
+ unsigned le; \
271
+
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
272
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
136
+ bool sat = false; \
273
+{
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
274
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
275
+
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
276
+ /* Set default values for registers */
140
+ } \
277
+ s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
141
+ if (qc) { \
278
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
142
+ env->vfp.qc[0] = qc; \
279
+}
143
+ } \
280
+
144
+ mve_advance_vpt(env); \
281
+static void allwinner_h3_sysctrl_init(Object *obj)
282
+{
283
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
284
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
285
+
286
+ /* Memory mapping */
287
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
288
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
289
+ sysbus_init_mmio(sbd, &s->iomem);
290
+}
291
+
292
+static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
293
+ .name = "allwinner-h3-sysctrl",
294
+ .version_id = 1,
295
+ .minimum_version_id = 1,
296
+ .fields = (VMStateField[]) {
297
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
298
+ VMSTATE_END_OF_LIST()
299
+ }
145
+ }
300
+};
146
+
301
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
302
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
303
+{
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
150
+
305
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
306
+ dc->reset = allwinner_h3_sysctrl_reset;
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
307
+ dc->vmsd = &allwinner_h3_sysctrl_vmstate;
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
308
+}
154
+
309
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
310
+static const TypeInfo allwinner_h3_sysctrl_info = {
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
311
+ .name = TYPE_AW_H3_SYSCTRL,
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
312
+ .parent = TYPE_SYS_BUS_DEVICE,
158
+
313
+ .instance_init = allwinner_h3_sysctrl_init,
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
314
+ .instance_size = sizeof(AwH3SysCtrlState),
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
315
+ .class_init = allwinner_h3_sysctrl_class_init,
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
316
+};
162
+
317
+
163
+#define DO_SHRN_SB(N, M, SATP) \
318
+static void allwinner_h3_sysctrl_register(void)
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
319
+{
165
+#define DO_SHRN_UB(N, M, SATP) \
320
+ type_register_static(&allwinner_h3_sysctrl_info);
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
321
+}
167
+#define DO_SHRUN_B(N, M, SATP) \
322
+
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
323
+type_init(allwinner_h3_sysctrl_register)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
324
--
224
--
325
2.20.1
225
2.20.1
326
226
327
227
diff view generated by jsdifflib
1
Some of an M-profile CPU's cached hflags state depends on state that's
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
in our NVIC object. We already do an hflags rebuild when the NVIC
2
entire vector with carry in bits provided from a general purpose
3
registers are written, but we also need to do this on NVIC reset,
3
register and carry out bits written back to that register.
4
because there's no guarantee that this will happen before the
5
CPU reset.
6
7
This fixes an assertion due to mismatched hflags which happens if
8
the CPU is reset from inside a HardFault handler.
9
4
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200303174950.3298-2-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
13
---
8
---
14
hw/intc/armv7m_nvic.c | 6 ++++++
9
target/arm/helper-mve.h | 2 ++
15
1 file changed, 6 insertions(+)
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
16
14
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
17
--- a/target/arm/helper-mve.h
20
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
s->itns[i] = true;
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
}
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
}
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/mve.decode
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
33
+
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
25
+
51
+
26
+ /*
52
+ /*
27
+ * We updated state that affects the CPU's MMUidx and thus its hflags;
53
+ * For each 32-bit element, we shift it left, bringing in the
28
+ * and we can't guarantee that we run before the CPU reset function.
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
29
+ */
58
+ */
30
+ arm_rebuild_hflags(&s->cpu->env);
59
+ if (shift == 0) {
31
}
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
32
61
+ r = rdm;
33
static void nvic_systick_trigger(void *opaque, int n, int level)
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
34
--
119
--
35
2.20.1
120
2.20.1
36
121
37
122
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
2
4
3
The Allwinner System on Chip families sun4i and above contain
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
an integrated storage controller for Secure Digital (SD) and
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Multi Media Card (MMC) interfaces. This commit adds support
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
6
for the Allwinner SD/MMC storage controller with the following
8
---
7
emulated features:
9
target/arm/helper-mve.h | 3 ++
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
8
14
9
* DMA transfers
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
10
* Direct FIFO I/O
11
* Short/Long format command responses
12
* Auto-Stop command (CMD12)
13
* Insert & remove card detection
14
15
The following boards are extended with the SD host controller:
16
17
* Cubieboard (hw/arm/cubieboard.c)
18
* Orange Pi PC (hw/arm/orangepi.c)
19
20
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
21
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
22
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
hw/sd/Makefile.objs | 1 +
27
include/hw/arm/allwinner-a10.h | 2 +
28
include/hw/arm/allwinner-h3.h | 3 +
29
include/hw/sd/allwinner-sdhost.h | 135 +++++
30
hw/arm/allwinner-a10.c | 11 +
31
hw/arm/allwinner-h3.c | 15 +-
32
hw/arm/cubieboard.c | 15 +
33
hw/arm/orangepi.c | 16 +
34
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
35
hw/arm/Kconfig | 1 +
36
hw/sd/trace-events | 7 +
37
11 files changed, 1059 insertions(+), 1 deletion(-)
38
create mode 100644 include/hw/sd/allwinner-sdhost.h
39
create mode 100644 hw/sd/allwinner-sdhost.c
40
41
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
42
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/sd/Makefile.objs
17
--- a/target/arm/helper-mve.h
44
+++ b/hw/sd/Makefile.objs
18
+++ b/target/arm/helper-mve.h
45
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
46
common-obj-$(CONFIG_SDHCI) += sdhci.o
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
47
common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
48
22
49
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
50
common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
51
common-obj-$(CONFIG_OMAP) += omap_mmc.o
25
+
52
common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
53
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
54
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
55
--- a/include/hw/arm/allwinner-a10.h
31
--- a/target/arm/mve.decode
56
+++ b/include/hw/arm/allwinner-a10.h
32
+++ b/target/arm/mve.decode
57
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
58
#include "hw/timer/allwinner-a10-pit.h"
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
59
#include "hw/intc/allwinner-a10-pic.h"
35
60
#include "hw/net/allwinner_emac.h"
36
# Vector add across vector
61
+#include "hw/sd/allwinner-sdhost.h"
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
62
#include "hw/ide/ahci.h"
38
+{
63
#include "hw/usb/hcd-ohci.h"
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
64
#include "hw/usb/hcd-ehci.h"
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
65
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
41
+ rdahi=%rdahi rdalo=%rdalo
66
AwA10PICState intc;
42
+}
67
AwEmacState emac;
43
68
AllwinnerAHCIState sata;
44
# Predicate operations
69
+ AwSdHostState mmc0;
45
%mask_22_13 22:1 13:3
70
MemoryRegion sram_a;
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
71
EHCISysBusState ehci[AW_A10_NUM_USB];
72
OHCISysBusState ohci[AW_A10_NUM_USB];
73
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
74
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
75
--- a/include/hw/arm/allwinner-h3.h
48
--- a/target/arm/mve_helper.c
76
+++ b/include/hw/arm/allwinner-h3.h
49
+++ b/target/arm/mve_helper.c
77
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
78
#include "hw/misc/allwinner-cpucfg.h"
51
DO_VADDV(vaddvuh, 2, uint16_t)
79
#include "hw/misc/allwinner-h3-sysctrl.h"
52
DO_VADDV(vaddvuw, 4, uint32_t)
80
#include "hw/misc/allwinner-sid.h"
53
81
+#include "hw/sd/allwinner-sdhost.h"
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
82
#include "target/arm/cpu.h"
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
83
56
+ uint64_t ra) \
84
/**
57
+ { \
85
@@ -XXX,XX +XXX,XX @@ enum {
58
+ uint16_t mask = mve_element_mask(env); \
86
AW_H3_SRAM_A2,
59
+ unsigned e; \
87
AW_H3_SRAM_C,
60
+ TYPE *m = vm; \
88
AW_H3_SYSCTRL,
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
89
+ AW_H3_MMC0,
62
+ if (mask & 1) { \
90
AW_H3_SID,
63
+ ra += (LTYPE)m[H4(e)]; \
91
AW_H3_EHCI0,
64
+ } \
92
AW_H3_OHCI0,
65
+ } \
93
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
66
+ mve_advance_vpt(env); \
94
AwCpuCfgState cpucfg;
67
+ return ra; \
95
AwH3SysCtrlState sysctrl;
68
+ } \
96
AwSidState sid;
97
+ AwSdHostState mmc0;
98
GICState gic;
99
MemoryRegion sram_a1;
100
MemoryRegion sram_a2;
101
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
102
new file mode 100644
103
index XXXXXXX..XXXXXXX
104
--- /dev/null
105
+++ b/include/hw/sd/allwinner-sdhost.h
106
@@ -XXX,XX +XXX,XX @@
107
+/*
108
+ * Allwinner (sun4i and above) SD Host Controller emulation
109
+ *
110
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
111
+ *
112
+ * This program is free software: you can redistribute it and/or modify
113
+ * it under the terms of the GNU General Public License as published by
114
+ * the Free Software Foundation, either version 2 of the License, or
115
+ * (at your option) any later version.
116
+ *
117
+ * This program is distributed in the hope that it will be useful,
118
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
119
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
120
+ * GNU General Public License for more details.
121
+ *
122
+ * You should have received a copy of the GNU General Public License
123
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
124
+ */
125
+
69
+
126
+#ifndef HW_SD_ALLWINNER_SDHOST_H
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
127
+#define HW_SD_ALLWINNER_SDHOST_H
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
128
+
72
+
129
+#include "qom/object.h"
73
/* Shifts by immediate */
130
+#include "hw/sysbus.h"
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
131
+#include "hw/sd/sd.h"
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
132
+
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
133
+/**
134
+ * Object model types
135
+ * @{
136
+ */
137
+
138
+/** Generic Allwinner SD Host Controller (abstract) */
139
+#define TYPE_AW_SDHOST "allwinner-sdhost"
140
+
141
+/** Allwinner sun4i family (A10, A12) */
142
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
143
+
144
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
145
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
146
+
147
+/** @} */
148
+
149
+/**
150
+ * Object model macros
151
+ * @{
152
+ */
153
+
154
+#define AW_SDHOST(obj) \
155
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
156
+#define AW_SDHOST_CLASS(klass) \
157
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
158
+#define AW_SDHOST_GET_CLASS(obj) \
159
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
160
+
161
+/** @} */
162
+
163
+/**
164
+ * Allwinner SD Host Controller object instance state.
165
+ */
166
+typedef struct AwSdHostState {
167
+ /*< private >*/
168
+ SysBusDevice busdev;
169
+ /*< public >*/
170
+
171
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
172
+ SDBus sdbus;
173
+
174
+ /** Maps I/O registers in physical memory */
175
+ MemoryRegion iomem;
176
+
177
+ /** Interrupt output signal to notify CPU */
178
+ qemu_irq irq;
179
+
180
+ /** Number of bytes left in current DMA transfer */
181
+ uint32_t transfer_cnt;
182
+
183
+ /**
184
+ * @name Hardware Registers
185
+ * @{
186
+ */
187
+
188
+ uint32_t global_ctl; /**< Global Control */
189
+ uint32_t clock_ctl; /**< Clock Control */
190
+ uint32_t timeout; /**< Timeout */
191
+ uint32_t bus_width; /**< Bus Width */
192
+ uint32_t block_size; /**< Block Size */
193
+ uint32_t byte_count; /**< Byte Count */
194
+
195
+ uint32_t command; /**< Command */
196
+ uint32_t command_arg; /**< Command Argument */
197
+ uint32_t response[4]; /**< Command Response */
198
+
199
+ uint32_t irq_mask; /**< Interrupt Mask */
200
+ uint32_t irq_status; /**< Raw Interrupt Status */
201
+ uint32_t status; /**< Status */
202
+
203
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
204
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
205
+ uint32_t debug_enable; /**< Debug Enable */
206
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
207
+ uint32_t newtiming_set; /**< SD New Timing Set */
208
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
209
+ uint32_t hardware_rst; /**< Hardware Reset */
210
+ uint32_t dmac; /**< Internal DMA Controller Control */
211
+ uint32_t desc_base; /**< Descriptor List Base Address */
212
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
213
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
214
+ uint32_t card_threshold; /**< Card Threshold Control */
215
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
216
+ uint32_t response_crc; /**< Response CRC */
217
+ uint32_t data_crc[8]; /**< Data CRC */
218
+ uint32_t status_crc; /**< Status CRC */
219
+
220
+ /** @} */
221
+
222
+} AwSdHostState;
223
+
224
+/**
225
+ * Allwinner SD Host Controller class-level struct.
226
+ *
227
+ * This struct is filled by each sunxi device specific code
228
+ * such that the generic code can use this struct to support
229
+ * all devices.
230
+ */
231
+typedef struct AwSdHostClass {
232
+ /*< private >*/
233
+ SysBusDeviceClass parent_class;
234
+ /*< public >*/
235
+
236
+ /** Maximum buffer size in bytes per DMA descriptor */
237
+ size_t max_desc_size;
238
+
239
+} AwSdHostClass;
240
+
241
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
242
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
243
index XXXXXXX..XXXXXXX 100644
77
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/arm/allwinner-a10.c
78
--- a/target/arm/translate-mve.c
245
+++ b/hw/arm/allwinner-a10.c
79
+++ b/target/arm/translate-mve.c
246
@@ -XXX,XX +XXX,XX @@
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
247
#include "hw/boards.h"
81
return true;
248
#include "hw/usb/hcd-ohci.h"
249
250
+#define AW_A10_MMC0_BASE 0x01c0f000
251
#define AW_A10_PIC_REG_BASE 0x01c20400
252
#define AW_A10_PIT_REG_BASE 0x01c20c00
253
#define AW_A10_UART0_REG_BASE 0x01c28000
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
255
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
256
}
257
}
258
+
259
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
260
+ TYPE_AW_SDHOST_SUN4I);
261
}
82
}
262
83
263
static void aw_a10_realize(DeviceState *dev, Error **errp)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
264
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
265
qdev_get_gpio_in(dev, 64 + i));
266
}
267
}
268
+
269
+ /* SD/MMC */
270
+ qdev_init_nofail(DEVICE(&s->mmc0));
271
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
272
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
273
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
274
+ "sd-bus", &error_abort);
275
}
276
277
static void aw_a10_class_init(ObjectClass *oc, void *data)
278
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
279
index XXXXXXX..XXXXXXX 100644
280
--- a/hw/arm/allwinner-h3.c
281
+++ b/hw/arm/allwinner-h3.c
282
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
283
[AW_H3_SRAM_A2] = 0x00044000,
284
[AW_H3_SRAM_C] = 0x00010000,
285
[AW_H3_SYSCTRL] = 0x01c00000,
286
+ [AW_H3_MMC0] = 0x01c0f000,
287
[AW_H3_SID] = 0x01c14000,
288
[AW_H3_EHCI0] = 0x01c1a000,
289
[AW_H3_OHCI0] = 0x01c1a400,
290
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
291
{ "lcd0", 0x01c0c000, 4 * KiB },
292
{ "lcd1", 0x01c0d000, 4 * KiB },
293
{ "ve", 0x01c0e000, 4 * KiB },
294
- { "mmc0", 0x01c0f000, 4 * KiB },
295
{ "mmc1", 0x01c10000, 4 * KiB },
296
{ "mmc2", 0x01c11000, 4 * KiB },
297
{ "crypto", 0x01c15000, 4 * KiB },
298
@@ -XXX,XX +XXX,XX @@ enum {
299
AW_H3_GIC_SPI_UART3 = 3,
300
AW_H3_GIC_SPI_TIMER0 = 18,
301
AW_H3_GIC_SPI_TIMER1 = 19,
302
+ AW_H3_GIC_SPI_MMC0 = 60,
303
AW_H3_GIC_SPI_EHCI0 = 72,
304
AW_H3_GIC_SPI_OHCI0 = 73,
305
AW_H3_GIC_SPI_EHCI1 = 74,
306
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
307
TYPE_AW_SID);
308
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
309
"identifier", &error_abort);
310
+
311
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
312
+ TYPE_AW_SDHOST_SUN5I);
313
}
314
315
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
316
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
317
qdev_init_nofail(DEVICE(&s->sid));
318
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
319
320
+ /* SD/MMC */
321
+ qdev_init_nofail(DEVICE(&s->mmc0));
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
323
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
324
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
325
+
326
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
327
+ "sd-bus", &error_abort);
328
+
329
/* Universal Serial Bus */
330
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
331
qdev_get_gpio_in(DEVICE(&s->gic),
332
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/cubieboard.c
335
+++ b/hw/arm/cubieboard.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "sysemu/sysemu.h"
338
#include "hw/sysbus.h"
339
#include "hw/boards.h"
340
+#include "hw/qdev-properties.h"
341
#include "hw/arm/allwinner-a10.h"
342
343
static struct arm_boot_info cubieboard_binfo = {
344
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
345
{
346
AwA10State *a10;
347
Error *err = NULL;
348
+ DriveInfo *di;
349
+ BlockBackend *blk;
350
+ BusState *bus;
351
+ DeviceState *carddev;
352
353
/* BIOS is not supported by this board */
354
if (bios_name) {
355
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
356
exit(1);
357
}
358
359
+ /* Retrieve SD bus */
360
+ di = drive_get_next(IF_SD);
361
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
362
+ bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
363
+
364
+ /* Plug in SD card */
365
+ carddev = qdev_create(bus, TYPE_SD_CARD);
366
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
367
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
368
+
369
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
370
machine->ram);
371
372
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
373
index XXXXXXX..XXXXXXX 100644
374
--- a/hw/arm/orangepi.c
375
+++ b/hw/arm/orangepi.c
376
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = {
377
static void orangepi_init(MachineState *machine)
378
{
379
AwH3State *h3;
380
+ DriveInfo *di;
381
+ BlockBackend *blk;
382
+ BusState *bus;
383
+ DeviceState *carddev;
384
385
/* BIOS is not supported by this board */
386
if (bios_name) {
387
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
388
/* Mark H3 object realized */
389
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
390
391
+ /* Retrieve SD bus */
392
+ di = drive_get_next(IF_SD);
393
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
394
+ bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
395
+
396
+ /* Plug in SD card */
397
+ carddev = qdev_create(bus, TYPE_SD_CARD);
398
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
399
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
400
+
401
/* SDRAM */
402
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
403
machine->ram);
404
@@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc)
405
{
406
mc->desc = "Orange Pi PC";
407
mc->init = orangepi_init;
408
+ mc->block_default_type = IF_SD;
409
+ mc->units_per_default_bus = 1;
410
mc->min_cpus = AW_H3_NUM_CPUS;
411
mc->max_cpus = AW_H3_NUM_CPUS;
412
mc->default_cpus = AW_H3_NUM_CPUS;
413
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
414
new file mode 100644
415
index XXXXXXX..XXXXXXX
416
--- /dev/null
417
+++ b/hw/sd/allwinner-sdhost.c
418
@@ -XXX,XX +XXX,XX @@
419
+/*
420
+ * Allwinner (sun4i and above) SD Host Controller emulation
421
+ *
422
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
423
+ *
424
+ * This program is free software: you can redistribute it and/or modify
425
+ * it under the terms of the GNU General Public License as published by
426
+ * the Free Software Foundation, either version 2 of the License, or
427
+ * (at your option) any later version.
428
+ *
429
+ * This program is distributed in the hope that it will be useful,
430
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
431
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
432
+ * GNU General Public License for more details.
433
+ *
434
+ * You should have received a copy of the GNU General Public License
435
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
436
+ */
437
+
438
+#include "qemu/osdep.h"
439
+#include "qemu/log.h"
440
+#include "qemu/module.h"
441
+#include "qemu/units.h"
442
+#include "sysemu/blockdev.h"
443
+#include "hw/irq.h"
444
+#include "hw/sd/allwinner-sdhost.h"
445
+#include "migration/vmstate.h"
446
+#include "trace.h"
447
+
448
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
449
+#define AW_SDHOST_BUS(obj) \
450
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
451
+
452
+/* SD Host register offsets */
453
+enum {
454
+ REG_SD_GCTL = 0x00, /* Global Control */
455
+ REG_SD_CKCR = 0x04, /* Clock Control */
456
+ REG_SD_TMOR = 0x08, /* Timeout */
457
+ REG_SD_BWDR = 0x0C, /* Bus Width */
458
+ REG_SD_BKSR = 0x10, /* Block Size */
459
+ REG_SD_BYCR = 0x14, /* Byte Count */
460
+ REG_SD_CMDR = 0x18, /* Command */
461
+ REG_SD_CAGR = 0x1C, /* Command Argument */
462
+ REG_SD_RESP0 = 0x20, /* Response Zero */
463
+ REG_SD_RESP1 = 0x24, /* Response One */
464
+ REG_SD_RESP2 = 0x28, /* Response Two */
465
+ REG_SD_RESP3 = 0x2C, /* Response Three */
466
+ REG_SD_IMKR = 0x30, /* Interrupt Mask */
467
+ REG_SD_MISR = 0x34, /* Masked Interrupt Status */
468
+ REG_SD_RISR = 0x38, /* Raw Interrupt Status */
469
+ REG_SD_STAR = 0x3C, /* Status */
470
+ REG_SD_FWLR = 0x40, /* FIFO Water Level */
471
+ REG_SD_FUNS = 0x44, /* FIFO Function Select */
472
+ REG_SD_DBGC = 0x50, /* Debug Enable */
473
+ REG_SD_A12A = 0x58, /* Auto command 12 argument */
474
+ REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
475
+ REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
476
+ REG_SD_HWRST = 0x78, /* Hardware Reset Register */
477
+ REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
478
+ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
479
+ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
480
+ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
481
+ REG_SD_THLDC = 0x100, /* Card Threshold Control */
482
+ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
483
+ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
484
+ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
485
+ REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
486
+ REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
487
+ REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
488
+ REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
489
+ REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
490
+ REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
491
+ REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
492
+ REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
493
+ REG_SD_FIFO = 0x200, /* Read/Write FIFO */
494
+};
495
+
496
+/* SD Host register flags */
497
+enum {
498
+ SD_GCTL_FIFO_AC_MOD = (1 << 31),
499
+ SD_GCTL_DDR_MOD_SEL = (1 << 10),
500
+ SD_GCTL_CD_DBC_ENB = (1 << 8),
501
+ SD_GCTL_DMA_ENB = (1 << 5),
502
+ SD_GCTL_INT_ENB = (1 << 4),
503
+ SD_GCTL_DMA_RST = (1 << 2),
504
+ SD_GCTL_FIFO_RST = (1 << 1),
505
+ SD_GCTL_SOFT_RST = (1 << 0),
506
+};
507
+
508
+enum {
509
+ SD_CMDR_LOAD = (1 << 31),
510
+ SD_CMDR_CLKCHANGE = (1 << 21),
511
+ SD_CMDR_WRITE = (1 << 10),
512
+ SD_CMDR_AUTOSTOP = (1 << 12),
513
+ SD_CMDR_DATA = (1 << 9),
514
+ SD_CMDR_RESPONSE_LONG = (1 << 7),
515
+ SD_CMDR_RESPONSE = (1 << 6),
516
+ SD_CMDR_CMDID_MASK = (0x3f),
517
+};
518
+
519
+enum {
520
+ SD_RISR_CARD_REMOVE = (1 << 31),
521
+ SD_RISR_CARD_INSERT = (1 << 30),
522
+ SD_RISR_SDIO_INTR = (1 << 16),
523
+ SD_RISR_AUTOCMD_DONE = (1 << 14),
524
+ SD_RISR_DATA_COMPLETE = (1 << 3),
525
+ SD_RISR_CMD_COMPLETE = (1 << 2),
526
+ SD_RISR_NO_RESPONSE = (1 << 1),
527
+};
528
+
529
+enum {
530
+ SD_STAR_CARD_PRESENT = (1 << 8),
531
+};
532
+
533
+enum {
534
+ SD_IDST_INT_SUMMARY = (1 << 8),
535
+ SD_IDST_RECEIVE_IRQ = (1 << 1),
536
+ SD_IDST_TRANSMIT_IRQ = (1 << 0),
537
+ SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
538
+ SD_IDST_WR_MASK = (0x3ff),
539
+};
540
+
541
+/* SD Host register reset values */
542
+enum {
543
+ REG_SD_GCTL_RST = 0x00000300,
544
+ REG_SD_CKCR_RST = 0x0,
545
+ REG_SD_TMOR_RST = 0xFFFFFF40,
546
+ REG_SD_BWDR_RST = 0x0,
547
+ REG_SD_BKSR_RST = 0x00000200,
548
+ REG_SD_BYCR_RST = 0x00000200,
549
+ REG_SD_CMDR_RST = 0x0,
550
+ REG_SD_CAGR_RST = 0x0,
551
+ REG_SD_RESP_RST = 0x0,
552
+ REG_SD_IMKR_RST = 0x0,
553
+ REG_SD_MISR_RST = 0x0,
554
+ REG_SD_RISR_RST = 0x0,
555
+ REG_SD_STAR_RST = 0x00000100,
556
+ REG_SD_FWLR_RST = 0x000F0000,
557
+ REG_SD_FUNS_RST = 0x0,
558
+ REG_SD_DBGC_RST = 0x0,
559
+ REG_SD_A12A_RST = 0x0000FFFF,
560
+ REG_SD_NTSR_RST = 0x00000001,
561
+ REG_SD_SDBG_RST = 0x0,
562
+ REG_SD_HWRST_RST = 0x00000001,
563
+ REG_SD_DMAC_RST = 0x0,
564
+ REG_SD_DLBA_RST = 0x0,
565
+ REG_SD_IDST_RST = 0x0,
566
+ REG_SD_IDIE_RST = 0x0,
567
+ REG_SD_THLDC_RST = 0x0,
568
+ REG_SD_DSBD_RST = 0x0,
569
+ REG_SD_RES_CRC_RST = 0x0,
570
+ REG_SD_DATA_CRC_RST = 0x0,
571
+ REG_SD_CRC_STA_RST = 0x0,
572
+ REG_SD_FIFO_RST = 0x0,
573
+};
574
+
575
+/* Data transfer descriptor for DMA */
576
+typedef struct TransferDescriptor {
577
+ uint32_t status; /* Status flags */
578
+ uint32_t size; /* Data buffer size */
579
+ uint32_t addr; /* Data buffer address */
580
+ uint32_t next; /* Physical address of next descriptor */
581
+} TransferDescriptor;
582
+
583
+/* Data transfer descriptor flags */
584
+enum {
585
+ DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
586
+ DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
587
+ DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
588
+ DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
589
+ DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
590
+ DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
591
+ DESC_SIZE_MASK = (0xfffffffc)
592
+};
593
+
594
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
595
+{
596
+ uint32_t irq;
597
+
598
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
599
+ irq = s->irq_status & s->irq_mask;
600
+ } else {
601
+ irq = 0;
602
+ }
603
+
604
+ trace_allwinner_sdhost_update_irq(irq);
605
+ qemu_set_irq(s->irq, irq);
606
+}
607
+
608
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
609
+ uint32_t bytes)
610
+{
611
+ if (s->transfer_cnt > bytes) {
612
+ s->transfer_cnt -= bytes;
613
+ } else {
614
+ s->transfer_cnt = 0;
615
+ }
616
+
617
+ if (!s->transfer_cnt) {
618
+ s->irq_status |= SD_RISR_DATA_COMPLETE;
619
+ }
620
+}
621
+
622
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
623
+{
624
+ AwSdHostState *s = AW_SDHOST(dev);
625
+
626
+ trace_allwinner_sdhost_set_inserted(inserted);
627
+
628
+ if (inserted) {
629
+ s->irq_status |= SD_RISR_CARD_INSERT;
630
+ s->irq_status &= ~SD_RISR_CARD_REMOVE;
631
+ s->status |= SD_STAR_CARD_PRESENT;
632
+ } else {
633
+ s->irq_status &= ~SD_RISR_CARD_INSERT;
634
+ s->irq_status |= SD_RISR_CARD_REMOVE;
635
+ s->status &= ~SD_STAR_CARD_PRESENT;
636
+ }
637
+
638
+ allwinner_sdhost_update_irq(s);
639
+}
640
+
641
+static void allwinner_sdhost_send_command(AwSdHostState *s)
642
+{
643
+ SDRequest request;
644
+ uint8_t resp[16];
645
+ int rlen;
646
+
647
+ /* Auto clear load flag */
648
+ s->command &= ~SD_CMDR_LOAD;
649
+
650
+ /* Clock change does not actually interact with the SD bus */
651
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
652
+
653
+ /* Prepare request */
654
+ request.cmd = s->command & SD_CMDR_CMDID_MASK;
655
+ request.arg = s->command_arg;
656
+
657
+ /* Send request to SD bus */
658
+ rlen = sdbus_do_command(&s->sdbus, &request, resp);
659
+ if (rlen < 0) {
660
+ goto error;
661
+ }
662
+
663
+ /* If the command has a response, store it in the response registers */
664
+ if ((s->command & SD_CMDR_RESPONSE)) {
665
+ if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
666
+ s->response[0] = ldl_be_p(&resp[0]);
667
+ s->response[1] = s->response[2] = s->response[3] = 0;
668
+
669
+ } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
670
+ s->response[0] = ldl_be_p(&resp[12]);
671
+ s->response[1] = ldl_be_p(&resp[8]);
672
+ s->response[2] = ldl_be_p(&resp[4]);
673
+ s->response[3] = ldl_be_p(&resp[0]);
674
+ } else {
675
+ goto error;
676
+ }
677
+ }
678
+ }
679
+
680
+ /* Set interrupt status bits */
681
+ s->irq_status |= SD_RISR_CMD_COMPLETE;
682
+ return;
683
+
684
+error:
685
+ s->irq_status |= SD_RISR_NO_RESPONSE;
686
+}
687
+
688
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
689
+{
85
+{
690
+ /*
86
+ /*
691
+ * The stop command (CMD12) ensures the SD bus
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
692
+ * returns to the transfer state.
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
693
+ */
91
+ */
694
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
92
+ TCGv_ptr qm;
695
+ /* First save current command registers */
93
+ TCGv_i64 rda;
696
+ uint32_t saved_cmd = s->command;
94
+ TCGv_i32 rdalo, rdahi;
697
+ uint32_t saved_arg = s->command_arg;
698
+
95
+
699
+ /* Prepare stop command (CMD12) */
96
+ if (!dc_isar_feature(aa32_mve, s)) {
700
+ s->command &= ~SD_CMDR_CMDID_MASK;
97
+ return false;
701
+ s->command |= 12; /* CMD12 */
702
+ s->command_arg = 0;
703
+
704
+ /* Put the command on SD bus */
705
+ allwinner_sdhost_send_command(s);
706
+
707
+ /* Restore command values */
708
+ s->command = saved_cmd;
709
+ s->command_arg = saved_arg;
710
+
711
+ /* Set IRQ status bit for automatic stop done */
712
+ s->irq_status |= SD_RISR_AUTOCMD_DONE;
713
+ }
98
+ }
714
+}
99
+ /*
715
+
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
716
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
717
+ hwaddr desc_addr,
102
+ */
718
+ TransferDescriptor *desc,
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
719
+ bool is_write, uint32_t max_bytes)
104
+ return false;
720
+{
721
+ AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
722
+ uint32_t num_done = 0;
723
+ uint32_t num_bytes = max_bytes;
724
+ uint8_t buf[1024];
725
+
726
+ /* Read descriptor */
727
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
728
+ if (desc->size == 0) {
729
+ desc->size = klass->max_desc_size;
730
+ } else if (desc->size > klass->max_desc_size) {
731
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
732
+ " is out-of-bounds: %" PRIu32 " > %zu",
733
+ __func__, desc->size, klass->max_desc_size);
734
+ desc->size = klass->max_desc_size;
735
+ }
105
+ }
736
+ if (desc->size < num_bytes) {
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
737
+ num_bytes = desc->size;
107
+ return true;
738
+ }
739
+
740
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
741
+ is_write, max_bytes);
742
+
743
+ while (num_done < num_bytes) {
744
+ /* Try to completely fill the local buffer */
745
+ uint32_t buf_bytes = num_bytes - num_done;
746
+ if (buf_bytes > sizeof(buf)) {
747
+ buf_bytes = sizeof(buf);
748
+ }
749
+
750
+ /* Write to SD bus */
751
+ if (is_write) {
752
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
753
+ buf, buf_bytes);
754
+
755
+ for (uint32_t i = 0; i < buf_bytes; i++) {
756
+ sdbus_write_data(&s->sdbus, buf[i]);
757
+ }
758
+
759
+ /* Read from SD bus */
760
+ } else {
761
+ for (uint32_t i = 0; i < buf_bytes; i++) {
762
+ buf[i] = sdbus_read_data(&s->sdbus);
763
+ }
764
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
765
+ buf, buf_bytes);
766
+ }
767
+ num_done += buf_bytes;
768
+ }
769
+
770
+ /* Clear hold flag and flush descriptor */
771
+ desc->status &= ~DESC_STATUS_HOLD;
772
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
773
+
774
+ return num_done;
775
+}
776
+
777
+static void allwinner_sdhost_dma(AwSdHostState *s)
778
+{
779
+ TransferDescriptor desc;
780
+ hwaddr desc_addr = s->desc_base;
781
+ bool is_write = (s->command & SD_CMDR_WRITE);
782
+ uint32_t bytes_done = 0;
783
+
784
+ /* Check if DMA can be performed */
785
+ if (s->byte_count == 0 || s->block_size == 0 ||
786
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
787
+ return;
788
+ }
108
+ }
789
+
109
+
790
+ /*
110
+ /*
791
+ * For read operations, data must be available on the SD bus
111
+ * This insn is subject to beat-wise execution. Partial execution
792
+ * If not, it is an error and we should not act at all
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
793
+ */
114
+ */
794
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
115
+ if (a->a || mve_skip_first_beat(s)) {
795
+ return;
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
796
+ }
126
+ }
797
+
127
+
798
+ /* Process the DMA descriptors until all data is copied */
128
+ qm = mve_qreg_ptr(a->qm);
799
+ while (s->byte_count > 0) {
129
+ if (a->u) {
800
+ bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
801
+ is_write, s->byte_count);
131
+ } else {
802
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
803
+
135
+
804
+ if (bytes_done <= s->byte_count) {
136
+ rdalo = tcg_temp_new_i32();
805
+ s->byte_count -= bytes_done;
137
+ rdahi = tcg_temp_new_i32();
806
+ } else {
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
807
+ s->byte_count = 0;
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
808
+ }
140
+ store_reg(s, a->rdalo, rdalo);
809
+
141
+ store_reg(s, a->rdahi, rdahi);
810
+ if (desc.status & DESC_STATUS_LAST) {
142
+ tcg_temp_free_i64(rda);
811
+ break;
143
+ mve_update_eci(s);
812
+ } else {
144
+ return true;
813
+ desc_addr = desc.next;
814
+ }
815
+ }
816
+
817
+ /* Raise IRQ to signal DMA is completed */
818
+ s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
819
+
820
+ /* Update DMAC bits */
821
+ s->dmac_status |= SD_IDST_INT_SUMMARY;
822
+
823
+ if (is_write) {
824
+ s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
825
+ } else {
826
+ s->dmac_status |= SD_IDST_RECEIVE_IRQ;
827
+ }
828
+}
145
+}
829
+
146
+
830
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
831
+ unsigned size)
148
{
832
+{
149
TCGv_ptr qd;
833
+ AwSdHostState *s = AW_SDHOST(opaque);
834
+ uint32_t res = 0;
835
+
836
+ switch (offset) {
837
+ case REG_SD_GCTL: /* Global Control */
838
+ res = s->global_ctl;
839
+ break;
840
+ case REG_SD_CKCR: /* Clock Control */
841
+ res = s->clock_ctl;
842
+ break;
843
+ case REG_SD_TMOR: /* Timeout */
844
+ res = s->timeout;
845
+ break;
846
+ case REG_SD_BWDR: /* Bus Width */
847
+ res = s->bus_width;
848
+ break;
849
+ case REG_SD_BKSR: /* Block Size */
850
+ res = s->block_size;
851
+ break;
852
+ case REG_SD_BYCR: /* Byte Count */
853
+ res = s->byte_count;
854
+ break;
855
+ case REG_SD_CMDR: /* Command */
856
+ res = s->command;
857
+ break;
858
+ case REG_SD_CAGR: /* Command Argument */
859
+ res = s->command_arg;
860
+ break;
861
+ case REG_SD_RESP0: /* Response Zero */
862
+ res = s->response[0];
863
+ break;
864
+ case REG_SD_RESP1: /* Response One */
865
+ res = s->response[1];
866
+ break;
867
+ case REG_SD_RESP2: /* Response Two */
868
+ res = s->response[2];
869
+ break;
870
+ case REG_SD_RESP3: /* Response Three */
871
+ res = s->response[3];
872
+ break;
873
+ case REG_SD_IMKR: /* Interrupt Mask */
874
+ res = s->irq_mask;
875
+ break;
876
+ case REG_SD_MISR: /* Masked Interrupt Status */
877
+ res = s->irq_status & s->irq_mask;
878
+ break;
879
+ case REG_SD_RISR: /* Raw Interrupt Status */
880
+ res = s->irq_status;
881
+ break;
882
+ case REG_SD_STAR: /* Status */
883
+ res = s->status;
884
+ break;
885
+ case REG_SD_FWLR: /* FIFO Water Level */
886
+ res = s->fifo_wlevel;
887
+ break;
888
+ case REG_SD_FUNS: /* FIFO Function Select */
889
+ res = s->fifo_func_sel;
890
+ break;
891
+ case REG_SD_DBGC: /* Debug Enable */
892
+ res = s->debug_enable;
893
+ break;
894
+ case REG_SD_A12A: /* Auto command 12 argument */
895
+ res = s->auto12_arg;
896
+ break;
897
+ case REG_SD_NTSR: /* SD NewTiming Set */
898
+ res = s->newtiming_set;
899
+ break;
900
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
901
+ res = s->newtiming_debug;
902
+ break;
903
+ case REG_SD_HWRST: /* Hardware Reset Register */
904
+ res = s->hardware_rst;
905
+ break;
906
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
907
+ res = s->dmac;
908
+ break;
909
+ case REG_SD_DLBA: /* Descriptor List Base Address */
910
+ res = s->desc_base;
911
+ break;
912
+ case REG_SD_IDST: /* Internal DMA Controller Status */
913
+ res = s->dmac_status;
914
+ break;
915
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
916
+ res = s->dmac_irq;
917
+ break;
918
+ case REG_SD_THLDC: /* Card Threshold Control */
919
+ res = s->card_threshold;
920
+ break;
921
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
922
+ res = s->startbit_detect;
923
+ break;
924
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
925
+ res = s->response_crc;
926
+ break;
927
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
928
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
929
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
930
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
931
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
932
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
933
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
934
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
935
+ res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
936
+ break;
937
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
938
+ res = s->status_crc;
939
+ break;
940
+ case REG_SD_FIFO: /* Read/Write FIFO */
941
+ if (sdbus_data_ready(&s->sdbus)) {
942
+ res = sdbus_read_data(&s->sdbus);
943
+ res |= sdbus_read_data(&s->sdbus) << 8;
944
+ res |= sdbus_read_data(&s->sdbus) << 16;
945
+ res |= sdbus_read_data(&s->sdbus) << 24;
946
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
947
+ allwinner_sdhost_auto_stop(s);
948
+ allwinner_sdhost_update_irq(s);
949
+ } else {
950
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
951
+ __func__);
952
+ }
953
+ break;
954
+ default:
955
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
956
+ HWADDR_PRIx"\n", __func__, offset);
957
+ res = 0;
958
+ break;
959
+ }
960
+
961
+ trace_allwinner_sdhost_read(offset, res, size);
962
+ return res;
963
+}
964
+
965
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
966
+ uint64_t value, unsigned size)
967
+{
968
+ AwSdHostState *s = AW_SDHOST(opaque);
969
+
970
+ trace_allwinner_sdhost_write(offset, value, size);
971
+
972
+ switch (offset) {
973
+ case REG_SD_GCTL: /* Global Control */
974
+ s->global_ctl = value;
975
+ s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
976
+ SD_GCTL_SOFT_RST);
977
+ allwinner_sdhost_update_irq(s);
978
+ break;
979
+ case REG_SD_CKCR: /* Clock Control */
980
+ s->clock_ctl = value;
981
+ break;
982
+ case REG_SD_TMOR: /* Timeout */
983
+ s->timeout = value;
984
+ break;
985
+ case REG_SD_BWDR: /* Bus Width */
986
+ s->bus_width = value;
987
+ break;
988
+ case REG_SD_BKSR: /* Block Size */
989
+ s->block_size = value;
990
+ break;
991
+ case REG_SD_BYCR: /* Byte Count */
992
+ s->byte_count = value;
993
+ s->transfer_cnt = value;
994
+ break;
995
+ case REG_SD_CMDR: /* Command */
996
+ s->command = value;
997
+ if (value & SD_CMDR_LOAD) {
998
+ allwinner_sdhost_send_command(s);
999
+ allwinner_sdhost_dma(s);
1000
+ allwinner_sdhost_auto_stop(s);
1001
+ }
1002
+ allwinner_sdhost_update_irq(s);
1003
+ break;
1004
+ case REG_SD_CAGR: /* Command Argument */
1005
+ s->command_arg = value;
1006
+ break;
1007
+ case REG_SD_RESP0: /* Response Zero */
1008
+ s->response[0] = value;
1009
+ break;
1010
+ case REG_SD_RESP1: /* Response One */
1011
+ s->response[1] = value;
1012
+ break;
1013
+ case REG_SD_RESP2: /* Response Two */
1014
+ s->response[2] = value;
1015
+ break;
1016
+ case REG_SD_RESP3: /* Response Three */
1017
+ s->response[3] = value;
1018
+ break;
1019
+ case REG_SD_IMKR: /* Interrupt Mask */
1020
+ s->irq_mask = value;
1021
+ allwinner_sdhost_update_irq(s);
1022
+ break;
1023
+ case REG_SD_MISR: /* Masked Interrupt Status */
1024
+ case REG_SD_RISR: /* Raw Interrupt Status */
1025
+ s->irq_status &= ~value;
1026
+ allwinner_sdhost_update_irq(s);
1027
+ break;
1028
+ case REG_SD_STAR: /* Status */
1029
+ s->status &= ~value;
1030
+ allwinner_sdhost_update_irq(s);
1031
+ break;
1032
+ case REG_SD_FWLR: /* FIFO Water Level */
1033
+ s->fifo_wlevel = value;
1034
+ break;
1035
+ case REG_SD_FUNS: /* FIFO Function Select */
1036
+ s->fifo_func_sel = value;
1037
+ break;
1038
+ case REG_SD_DBGC: /* Debug Enable */
1039
+ s->debug_enable = value;
1040
+ break;
1041
+ case REG_SD_A12A: /* Auto command 12 argument */
1042
+ s->auto12_arg = value;
1043
+ break;
1044
+ case REG_SD_NTSR: /* SD NewTiming Set */
1045
+ s->newtiming_set = value;
1046
+ break;
1047
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
1048
+ s->newtiming_debug = value;
1049
+ break;
1050
+ case REG_SD_HWRST: /* Hardware Reset Register */
1051
+ s->hardware_rst = value;
1052
+ break;
1053
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
1054
+ s->dmac = value;
1055
+ allwinner_sdhost_update_irq(s);
1056
+ break;
1057
+ case REG_SD_DLBA: /* Descriptor List Base Address */
1058
+ s->desc_base = value;
1059
+ break;
1060
+ case REG_SD_IDST: /* Internal DMA Controller Status */
1061
+ s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
1062
+ allwinner_sdhost_update_irq(s);
1063
+ break;
1064
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
1065
+ s->dmac_irq = value;
1066
+ allwinner_sdhost_update_irq(s);
1067
+ break;
1068
+ case REG_SD_THLDC: /* Card Threshold Control */
1069
+ s->card_threshold = value;
1070
+ break;
1071
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
1072
+ s->startbit_detect = value;
1073
+ break;
1074
+ case REG_SD_FIFO: /* Read/Write FIFO */
1075
+ sdbus_write_data(&s->sdbus, value & 0xff);
1076
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
1077
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
1078
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
1079
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
1080
+ allwinner_sdhost_auto_stop(s);
1081
+ allwinner_sdhost_update_irq(s);
1082
+ break;
1083
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
1084
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
1085
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
1086
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
1087
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
1088
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
1089
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
1090
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
1091
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
1092
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
1093
+ break;
1094
+ default:
1095
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
1096
+ HWADDR_PRIx"\n", __func__, offset);
1097
+ break;
1098
+ }
1099
+}
1100
+
1101
+static const MemoryRegionOps allwinner_sdhost_ops = {
1102
+ .read = allwinner_sdhost_read,
1103
+ .write = allwinner_sdhost_write,
1104
+ .endianness = DEVICE_NATIVE_ENDIAN,
1105
+ .valid = {
1106
+ .min_access_size = 4,
1107
+ .max_access_size = 4,
1108
+ },
1109
+ .impl.min_access_size = 4,
1110
+};
1111
+
1112
+static const VMStateDescription vmstate_allwinner_sdhost = {
1113
+ .name = "allwinner-sdhost",
1114
+ .version_id = 1,
1115
+ .minimum_version_id = 1,
1116
+ .fields = (VMStateField[]) {
1117
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
1118
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
1119
+ VMSTATE_UINT32(timeout, AwSdHostState),
1120
+ VMSTATE_UINT32(bus_width, AwSdHostState),
1121
+ VMSTATE_UINT32(block_size, AwSdHostState),
1122
+ VMSTATE_UINT32(byte_count, AwSdHostState),
1123
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
1124
+ VMSTATE_UINT32(command, AwSdHostState),
1125
+ VMSTATE_UINT32(command_arg, AwSdHostState),
1126
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
1127
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
1128
+ VMSTATE_UINT32(irq_status, AwSdHostState),
1129
+ VMSTATE_UINT32(status, AwSdHostState),
1130
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
1131
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
1132
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
1133
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
1134
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
1135
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
1136
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
1137
+ VMSTATE_UINT32(dmac, AwSdHostState),
1138
+ VMSTATE_UINT32(desc_base, AwSdHostState),
1139
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
1140
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
1141
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
1142
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
1143
+ VMSTATE_UINT32(response_crc, AwSdHostState),
1144
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
1145
+ VMSTATE_UINT32(status_crc, AwSdHostState),
1146
+ VMSTATE_END_OF_LIST()
1147
+ }
1148
+};
1149
+
1150
+static void allwinner_sdhost_init(Object *obj)
1151
+{
1152
+ AwSdHostState *s = AW_SDHOST(obj);
1153
+
1154
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1155
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
1156
+
1157
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
1158
+ TYPE_AW_SDHOST, 4 * KiB);
1159
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
1160
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
1161
+}
1162
+
1163
+static void allwinner_sdhost_reset(DeviceState *dev)
1164
+{
1165
+ AwSdHostState *s = AW_SDHOST(dev);
1166
+
1167
+ s->global_ctl = REG_SD_GCTL_RST;
1168
+ s->clock_ctl = REG_SD_CKCR_RST;
1169
+ s->timeout = REG_SD_TMOR_RST;
1170
+ s->bus_width = REG_SD_BWDR_RST;
1171
+ s->block_size = REG_SD_BKSR_RST;
1172
+ s->byte_count = REG_SD_BYCR_RST;
1173
+ s->transfer_cnt = 0;
1174
+
1175
+ s->command = REG_SD_CMDR_RST;
1176
+ s->command_arg = REG_SD_CAGR_RST;
1177
+
1178
+ for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
1179
+ s->response[i] = REG_SD_RESP_RST;
1180
+ }
1181
+
1182
+ s->irq_mask = REG_SD_IMKR_RST;
1183
+ s->irq_status = REG_SD_RISR_RST;
1184
+ s->status = REG_SD_STAR_RST;
1185
+
1186
+ s->fifo_wlevel = REG_SD_FWLR_RST;
1187
+ s->fifo_func_sel = REG_SD_FUNS_RST;
1188
+ s->debug_enable = REG_SD_DBGC_RST;
1189
+ s->auto12_arg = REG_SD_A12A_RST;
1190
+ s->newtiming_set = REG_SD_NTSR_RST;
1191
+ s->newtiming_debug = REG_SD_SDBG_RST;
1192
+ s->hardware_rst = REG_SD_HWRST_RST;
1193
+ s->dmac = REG_SD_DMAC_RST;
1194
+ s->desc_base = REG_SD_DLBA_RST;
1195
+ s->dmac_status = REG_SD_IDST_RST;
1196
+ s->dmac_irq = REG_SD_IDIE_RST;
1197
+ s->card_threshold = REG_SD_THLDC_RST;
1198
+ s->startbit_detect = REG_SD_DSBD_RST;
1199
+ s->response_crc = REG_SD_RES_CRC_RST;
1200
+
1201
+ for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
1202
+ s->data_crc[i] = REG_SD_DATA_CRC_RST;
1203
+ }
1204
+
1205
+ s->status_crc = REG_SD_CRC_STA_RST;
1206
+}
1207
+
1208
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
1209
+{
1210
+ SDBusClass *sbc = SD_BUS_CLASS(klass);
1211
+
1212
+ sbc->set_inserted = allwinner_sdhost_set_inserted;
1213
+}
1214
+
1215
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
1216
+{
1217
+ DeviceClass *dc = DEVICE_CLASS(klass);
1218
+
1219
+ dc->reset = allwinner_sdhost_reset;
1220
+ dc->vmsd = &vmstate_allwinner_sdhost;
1221
+}
1222
+
1223
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
1224
+{
1225
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1226
+ sc->max_desc_size = 8 * KiB;
1227
+}
1228
+
1229
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
1230
+{
1231
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1232
+ sc->max_desc_size = 64 * KiB;
1233
+}
1234
+
1235
+static TypeInfo allwinner_sdhost_info = {
1236
+ .name = TYPE_AW_SDHOST,
1237
+ .parent = TYPE_SYS_BUS_DEVICE,
1238
+ .instance_init = allwinner_sdhost_init,
1239
+ .instance_size = sizeof(AwSdHostState),
1240
+ .class_init = allwinner_sdhost_class_init,
1241
+ .class_size = sizeof(AwSdHostClass),
1242
+ .abstract = true,
1243
+};
1244
+
1245
+static const TypeInfo allwinner_sdhost_sun4i_info = {
1246
+ .name = TYPE_AW_SDHOST_SUN4I,
1247
+ .parent = TYPE_AW_SDHOST,
1248
+ .class_init = allwinner_sdhost_sun4i_class_init,
1249
+};
1250
+
1251
+static const TypeInfo allwinner_sdhost_sun5i_info = {
1252
+ .name = TYPE_AW_SDHOST_SUN5I,
1253
+ .parent = TYPE_AW_SDHOST,
1254
+ .class_init = allwinner_sdhost_sun5i_class_init,
1255
+};
1256
+
1257
+static const TypeInfo allwinner_sdhost_bus_info = {
1258
+ .name = TYPE_AW_SDHOST_BUS,
1259
+ .parent = TYPE_SD_BUS,
1260
+ .instance_size = sizeof(SDBus),
1261
+ .class_init = allwinner_sdhost_bus_class_init,
1262
+};
1263
+
1264
+static void allwinner_sdhost_register_types(void)
1265
+{
1266
+ type_register_static(&allwinner_sdhost_info);
1267
+ type_register_static(&allwinner_sdhost_sun4i_info);
1268
+ type_register_static(&allwinner_sdhost_sun5i_info);
1269
+ type_register_static(&allwinner_sdhost_bus_info);
1270
+}
1271
+
1272
+type_init(allwinner_sdhost_register_types)
1273
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1274
index XXXXXXX..XXXXXXX 100644
1275
--- a/hw/arm/Kconfig
1276
+++ b/hw/arm/Kconfig
1277
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
1278
select UNIMP
1279
select USB_OHCI
1280
select USB_EHCI_SYSBUS
1281
+ select SD
1282
1283
config RASPI
1284
bool
1285
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
1286
index XXXXXXX..XXXXXXX 100644
1287
--- a/hw/sd/trace-events
1288
+++ b/hw/sd/trace-events
1289
@@ -XXX,XX +XXX,XX @@
1290
# See docs/devel/tracing.txt for syntax documentation.
1291
1292
+# allwinner-sdhost.c
1293
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
1294
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32
1295
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1296
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1297
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
1298
+
1299
# bcm2835_sdhost.c
1300
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1301
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1302
--
150
--
1303
2.20.1
151
2.20.1
1304
152
1305
153
diff view generated by jsdifflib
1
A write to the CONTROL register can change our current EL (by
1
The MVE extension to v8.1M includes some new shift instructions which
2
writing to the nPRIV bit). That means that we can't assume
2
sit entirely within the non-coprocessor part of the encoding space
3
that s->current_el is still valid in trans_MSR_v7m() when
3
and which operate only on general-purpose registers. They take up
4
we try to rebuild the hflags.
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
5
with Rm == 13 or 15.
6
Add a new helper rebuild_hflags_m32_newel() which, like the
6
7
existing rebuild_hflags_a32_newel(), recalculates the current
7
Implement the long shifts by immediate, which perform shifts on a
8
EL from scratch, and use it in trans_MSR_v7m().
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
9
an immediate shift count between 1 and 32.
10
This fixes an assertion about an hflags mismatch when the
10
11
guest changes privilege by writing to CONTROL.
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
12
23
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200303174950.3298-4-peter.maydell@linaro.org
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
16
---
27
---
17
target/arm/helper.h | 1 +
28
target/arm/helper-mve.h | 3 ++
18
target/arm/helper.c | 12 ++++++++++++
29
target/arm/translate.h | 1 +
19
target/arm/translate.c | 7 +++----
30
target/arm/t32.decode | 28 +++++++++++++
20
3 files changed, 16 insertions(+), 4 deletions(-)
31
target/arm/mve_helper.c | 10 +++++
21
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
22
diff --git a/target/arm/helper.h b/target/arm/helper.h
33
5 files changed, 132 insertions(+)
23
index XXXXXXX..XXXXXXX 100644
34
24
--- a/target/arm/helper.h
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
25
+++ b/target/arm/helper.h
36
index XXXXXXX..XXXXXXX 100644
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
37
--- a/target/arm/helper-mve.h
27
DEF_HELPER_2(get_user_reg, i32, env, i32)
38
+++ b/target/arm/helper-mve.h
28
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env)
41
31
DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
32
DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
43
+
33
DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
index XXXXXXX..XXXXXXX 100644
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
36
--- a/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
37
+++ b/target/arm/helper.c
48
--- a/target/arm/translate.h
38
@@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env)
49
+++ b/target/arm/translate.h
39
env->hflags = rebuild_hflags_internal(env);
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
40
}
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
41
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
42
+/*
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
43
+ * If we have triggered a EL state change we can't rely on the
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
44
+ * translator having passed it to us, we need to recompute.
55
45
+ */
56
/**
46
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
57
* arm_tbflags_from_tb:
47
+{
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
48
+ int el = arm_current_el(env);
59
index XXXXXXX..XXXXXXX 100644
49
+ int fp_el = fp_exception_el(env, el);
60
--- a/target/arm/t32.decode
50
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
61
+++ b/target/arm/t32.decode
51
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
62
@@ -XXX,XX +XXX,XX @@
52
+}
63
&mcr !extern cp opc1 crn crm opc2 rt
53
+
64
&mcrr !extern cp opc1 crm rt rt2
54
void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
55
{
83
{
56
int fp_el = fp_exception_el(env, el);
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
57
diff --git a/target/arm/translate.c b/target/arm/translate.c
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
58
index XXXXXXX..XXXXXXX 100644
129
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/translate.c
130
--- a/target/arm/translate.c
60
+++ b/target/arm/translate.c
131
+++ b/target/arm/translate.c
61
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
62
63
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
64
{
65
- TCGv_i32 addr, reg, el;
66
+ TCGv_i32 addr, reg;
67
68
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
69
return false;
70
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
71
gen_helper_v7m_msr(cpu_env, addr, reg);
72
tcg_temp_free_i32(addr);
73
tcg_temp_free_i32(reg);
74
- el = tcg_const_i32(s->current_el);
75
- gen_helper_rebuild_hflags_m32(cpu_env, el);
76
- tcg_temp_free_i32(el);
77
+ /* If we wrote to CONTROL, the EL might have changed */
78
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
79
gen_lookup_tb(s);
80
return true;
133
return true;
81
}
134
}
135
136
+/*
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
82
--
229
--
83
2.20.1
230
2.20.1
84
231
85
232
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE long shifts by register, which perform shifts on a
2
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
In the Allwinner H3 SoC the SDRAM controller is responsible
3
the shift count in another general-purpose register, which might be
4
for interfacing with the external Synchronous Dynamic Random
4
either positive or negative.
5
Access Memory (SDRAM). Types of memory that the SDRAM controller
5
6
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
adds emulation support of the Allwinner H3 SDRAM controller.
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
we have to move the CSEL pattern into the same decodetree group.
11
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
13
---
15
---
14
hw/misc/Makefile.objs | 1 +
16
target/arm/helper-mve.h | 6 +++
15
include/hw/arm/allwinner-h3.h | 5 +
17
target/arm/translate.h | 1 +
16
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
18
target/arm/t32.decode | 16 +++++--
17
hw/arm/allwinner-h3.c | 19 +-
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
18
hw/arm/orangepi.c | 6 +
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
19
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
21
5 files changed, 182 insertions(+), 3 deletions(-)
20
hw/misc/trace-events | 10 +
22
21
7 files changed, 502 insertions(+), 3 deletions(-)
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
22
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
24
index XXXXXXX..XXXXXXX 100644
23
create mode 100644 hw/misc/allwinner-h3-dramc.c
25
--- a/target/arm/helper-mve.h
24
26
+++ b/target/arm/helper-mve.h
25
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
index XXXXXXX..XXXXXXX 100644
28
27
--- a/hw/misc/Makefile.objs
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
28
+++ b/hw/misc/Makefile.objs
30
29
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
38
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/arm/allwinner-h3.h
41
--- a/target/arm/translate.h
40
+++ b/include/hw/arm/allwinner-h3.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
41
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@
42
#include "hw/intc/arm_gic.h"
56
&mcrr !extern cp opc1 crm rt rt2
43
#include "hw/misc/allwinner-h3-ccu.h"
57
44
#include "hw/misc/allwinner-cpucfg.h"
58
&mve_shl_ri rdalo rdahi shim
45
+#include "hw/misc/allwinner-h3-dramc.h"
59
+&mve_shl_rr rdalo rdahi rm
46
#include "hw/misc/allwinner-h3-sysctrl.h"
60
47
#include "hw/misc/allwinner-sid.h"
61
# rdahi: bits [3:1] from insn, bit 0 is 1
48
#include "hw/sd/allwinner-sdhost.h"
62
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@ enum {
50
AW_H3_UART2,
51
AW_H3_UART3,
52
AW_H3_EMAC,
53
+ AW_H3_DRAMCOM,
54
+ AW_H3_DRAMCTL,
55
+ AW_H3_DRAMPHY,
56
AW_H3_GIC_DIST,
57
AW_H3_GIC_CPU,
58
AW_H3_GIC_HYP,
59
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
AwCpuCfgState cpucfg;
63
+ AwH3DramCtlState dramc;
64
AwH3SysCtrlState sysctrl;
65
AwSidState sid;
66
AwSdHostState mmc0;
67
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h
68
new file mode 100644
69
index XXXXXXX..XXXXXXX
70
--- /dev/null
71
+++ b/include/hw/misc/allwinner-h3-dramc.h
72
@@ -XXX,XX +XXX,XX @@
63
@@ -XXX,XX +XXX,XX @@
73
+/*
64
74
+ * Allwinner H3 SDRAM Controller emulation
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
75
+ *
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
76
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
77
+ *
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
78
+ * This program is free software: you can redistribute it and/or modify
69
79
+ * it under the terms of the GNU General Public License as published by
70
{
80
+ * the Free Software Foundation, either version 2 of the License, or
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
81
+ * (at your option) any later version.
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
82
+ *
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ * This program is distributed in the hope that it will be useful,
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
84
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
85
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
76
+
86
+ * GNU General Public License for more details.
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
87
+ *
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
88
+ * You should have received a copy of the GNU General Public License
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
89
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
90
+ */
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
91
+
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
92
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
83
]
93
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
84
94
+
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
95
+#include "qom/object.h"
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
96
+#include "hw/sysbus.h"
87
+
97
+#include "exec/hwaddr.h"
88
+ # v8.1M CSEL and friends
98
+
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
+/**
90
}
100
+ * Constants
91
{
101
+ * @{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
102
+ */
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
103
+
94
}
104
+/** Highest register address used by DRAMCOM module */
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
105
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
96
106
+
97
-# v8.1M CSEL and friends
107
+/** Total number of known DRAMCOM registers */
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
108
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
99
-
109
+ sizeof(uint32_t))
100
# Data-processing (register-shifted register)
110
+
101
111
+/** Highest register address used by DRAMCTL module */
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
112
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
113
+
104
index XXXXXXX..XXXXXXX 100644
114
+/** Total number of known DRAMCTL registers */
105
--- a/target/arm/mve_helper.c
115
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
106
+++ b/target/arm/mve_helper.c
116
+ sizeof(uint32_t))
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
117
+
108
return rdm;
118
+/** Highest register address used by DRAMPHY module */
109
}
119
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
110
120
+
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
121
+/** Total number of known DRAMPHY registers */
112
+{
122
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
123
+ sizeof(uint32_t))
114
+}
124
+
115
+
125
+/** @} */
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
126
+
117
+{
127
+/**
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
128
+ * Object model
119
+}
129
+ * @{
120
+
130
+ */
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
131
+
122
{
132
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
133
+#define AW_H3_DRAMC(obj) \
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
134
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
125
{
135
+
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
136
+/** @} */
127
}
137
+
128
+
138
+/**
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
139
+ * Allwinner H3 SDRAM Controller object instance state.
130
+{
140
+ */
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
141
+typedef struct AwH3DramCtlState {
132
+}
142
+ /*< private >*/
133
+
143
+ SysBusDevice parent_obj;
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
144
+ /*< public >*/
135
+{
145
+
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
146
+ /** Physical base address for start of RAM */
137
+}
147
+ hwaddr ram_addr;
138
+
148
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
149
+ /** Total RAM size in megabytes */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
150
+ uint32_t ram_size;
141
+ bool round, uint32_t *sat)
151
+
142
+{
152
+ /**
143
+ if (shift <= -48) {
153
+ * @name Memory Regions
144
+ /* Rounding the sign bit always produces 0. */
154
+ * @{
145
+ if (round) {
155
+ */
146
+ return 0;
156
+
147
+ }
157
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
148
+ return src >> 63;
158
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
149
+ } else if (shift < 0) {
159
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
150
+ if (round) {
160
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
151
+ src >>= -shift - 1;
161
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
152
+ return (src >> 1) + (src & 1);
162
+
153
+ }
163
+ /** @} */
154
+ return src >> -shift;
164
+
155
+ } else if (shift < 48) {
165
+ /**
156
+ int64_t val = src << shift;
166
+ * @name Hardware Registers
157
+ int64_t extval = sextract64(val, 0, 48);
167
+ * @{
158
+ if (!sat || val == extval) {
168
+ */
159
+ return extval;
169
+
160
+ }
170
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
161
+ } else if (!sat || src == 0) {
171
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
172
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
173
+
174
+ /** @} */
175
+
176
+} AwH3DramCtlState;
177
+
178
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
179
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/hw/arm/allwinner-h3.c
182
+++ b/hw/arm/allwinner-h3.c
183
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
184
[AW_H3_UART2] = 0x01c28800,
185
[AW_H3_UART3] = 0x01c28c00,
186
[AW_H3_EMAC] = 0x01c30000,
187
+ [AW_H3_DRAMCOM] = 0x01c62000,
188
+ [AW_H3_DRAMCTL] = 0x01c63000,
189
+ [AW_H3_DRAMPHY] = 0x01c65000,
190
[AW_H3_GIC_DIST] = 0x01c81000,
191
[AW_H3_GIC_CPU] = 0x01c82000,
192
[AW_H3_GIC_HYP] = 0x01c84000,
193
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
194
{ "scr", 0x01c2c400, 1 * KiB },
195
{ "gpu", 0x01c40000, 64 * KiB },
196
{ "hstmr", 0x01c60000, 4 * KiB },
197
- { "dramcom", 0x01c62000, 4 * KiB },
198
- { "dramctl0", 0x01c63000, 4 * KiB },
199
- { "dramphy0", 0x01c65000, 4 * KiB },
200
{ "spi0", 0x01c68000, 4 * KiB },
201
{ "spi1", 0x01c69000, 4 * KiB },
202
{ "csi", 0x01cb0000, 320 * KiB },
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
206
TYPE_AW_SUN8I_EMAC);
207
+
208
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
209
+ TYPE_AW_H3_DRAMC);
210
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
211
+ "ram-addr", &error_abort);
212
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
213
+ "ram-size", &error_abort);
214
}
215
216
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
217
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
218
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
219
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
220
221
+ /* DRAMC */
222
+ qdev_init_nofail(DEVICE(&s->dramc));
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
224
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
225
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
226
+
227
/* Unimplemented devices */
228
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
229
create_unimplemented_device(unimplemented[i].device_name,
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
/* Setup EMAC properties */
236
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
237
238
+ /* DRAMC */
239
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
240
+ "ram-addr", &error_abort);
241
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",
242
+ &error_abort);
243
+
244
/* Mark H3 object realized */
245
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
246
247
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
248
new file mode 100644
249
index XXXXXXX..XXXXXXX
250
--- /dev/null
251
+++ b/hw/misc/allwinner-h3-dramc.c
252
@@ -XXX,XX +XXX,XX @@
253
+/*
254
+ * Allwinner H3 SDRAM Controller emulation
255
+ *
256
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
257
+ *
258
+ * This program is free software: you can redistribute it and/or modify
259
+ * it under the terms of the GNU General Public License as published by
260
+ * the Free Software Foundation, either version 2 of the License, or
261
+ * (at your option) any later version.
262
+ *
263
+ * This program is distributed in the hope that it will be useful,
264
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
265
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
266
+ * GNU General Public License for more details.
267
+ *
268
+ * You should have received a copy of the GNU General Public License
269
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "qemu/units.h"
274
+#include "qemu/error-report.h"
275
+#include "hw/sysbus.h"
276
+#include "migration/vmstate.h"
277
+#include "qemu/log.h"
278
+#include "qemu/module.h"
279
+#include "exec/address-spaces.h"
280
+#include "hw/qdev-properties.h"
281
+#include "qapi/error.h"
282
+#include "hw/misc/allwinner-h3-dramc.h"
283
+#include "trace.h"
284
+
285
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
286
+
287
+/* DRAMCOM register offsets */
288
+enum {
289
+ REG_DRAMCOM_CR = 0x0000, /* Control Register */
290
+};
291
+
292
+/* DRAMCTL register offsets */
293
+enum {
294
+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
295
+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
296
+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */
297
+};
298
+
299
+/* DRAMCTL register flags */
300
+enum {
301
+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
302
+};
303
+
304
+enum {
305
+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
306
+};
307
+
308
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
309
+ uint8_t bank_bits, uint16_t page_size)
310
+{
311
+ /*
312
+ * This function simulates row addressing behavior when bootloader
313
+ * software attempts to detect the amount of available SDRAM. In U-Boot
314
+ * the controller is configured with the widest row addressing available.
315
+ * Then a pattern is written to RAM at an offset on the row boundary size.
316
+ * If the value read back equals the value read back from the
317
+ * start of RAM, the bootloader knows the amount of row bits.
318
+ *
319
+ * This function inserts a mirrored memory region when the configured row
320
+ * bits are not matching the actual emulated memory, to simulate the
321
+ * same behavior on hardware as expected by the bootloader.
322
+ */
323
+ uint8_t row_bits_actual = 0;
324
+
325
+ /* Calculate the actual row bits using the ram_size property */
326
+ for (uint8_t i = 8; i < 12; i++) {
327
+ if (1 << i == s->ram_size) {
328
+ row_bits_actual = i + 3;
329
+ break;
330
+ }
331
+ }
332
+
333
+ if (s->ram_size == (1 << (row_bits - 3))) {
334
+ /* When row bits is the expected value, remove the mirror */
335
+ memory_region_set_enabled(&s->row_mirror_alias, false);
336
+ trace_allwinner_h3_dramc_rowmirror_disable();
337
+
338
+ } else if (row_bits_actual) {
339
+ /* Row bits not matching ram_size, install the rows mirror */
340
+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
341
+ bank_bits)) * page_size);
342
+
343
+ memory_region_set_enabled(&s->row_mirror_alias, true);
344
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
345
+
346
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
347
+ }
348
+}
349
+
350
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
351
+ unsigned size)
352
+{
353
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
354
+ const uint32_t idx = REG_INDEX(offset);
355
+
356
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
357
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
358
+ __func__, (uint32_t)offset);
359
+ return 0;
162
+ return 0;
360
+ }
163
+ }
361
+
164
+
362
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
165
+ *sat = 1;
363
+
166
+ return (1ULL << 47) - (src >= 0);
364
+ return s->dramcom[idx];
167
+}
365
+}
168
+
366
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
367
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
368
+ uint64_t val, unsigned size)
171
+ bool round, uint32_t *sat)
369
+{
172
+{
370
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
173
+ uint64_t val, extval;
371
+ const uint32_t idx = REG_INDEX(offset);
174
+
372
+
175
+ if (shift <= -(48 + round)) {
373
+ trace_allwinner_h3_dramcom_write(offset, val, size);
374
+
375
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
376
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
377
+ __func__, (uint32_t)offset);
378
+ return;
379
+ }
380
+
381
+ switch (offset) {
382
+ case REG_DRAMCOM_CR: /* Control Register */
383
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
384
+ ((val >> 2) & 0x1) + 2,
385
+ 1 << (((val >> 8) & 0xf) + 3));
386
+ break;
387
+ default:
388
+ break;
389
+ };
390
+
391
+ s->dramcom[idx] = (uint32_t) val;
392
+}
393
+
394
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
395
+ unsigned size)
396
+{
397
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
398
+ const uint32_t idx = REG_INDEX(offset);
399
+
400
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
401
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
402
+ __func__, (uint32_t)offset);
403
+ return 0;
176
+ return 0;
404
+ }
177
+ } else if (shift < 0) {
405
+
178
+ if (round) {
406
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
179
+ val = src >> (-shift - 1);
407
+
180
+ val = (val >> 1) + (val & 1);
408
+ return s->dramctl[idx];
181
+ } else {
409
+}
182
+ val = src >> -shift;
410
+
183
+ }
411
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
184
+ extval = extract64(val, 0, 48);
412
+ uint64_t val, unsigned size)
185
+ if (!sat || val == extval) {
413
+{
186
+ return extval;
414
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
187
+ }
415
+ const uint32_t idx = REG_INDEX(offset);
188
+ } else if (shift < 48) {
416
+
189
+ uint64_t val = src << shift;
417
+ trace_allwinner_h3_dramctl_write(offset, val, size);
190
+ uint64_t extval = extract64(val, 0, 48);
418
+
191
+ if (!sat || val == extval) {
419
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
192
+ return extval;
420
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
193
+ }
421
+ __func__, (uint32_t)offset);
194
+ } else if (!sat || src == 0) {
422
+ return;
423
+ }
424
+
425
+ switch (offset) {
426
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
427
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
428
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
429
+ break;
430
+ default:
431
+ break;
432
+ }
433
+
434
+ s->dramctl[idx] = (uint32_t) val;
435
+}
436
+
437
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
438
+ unsigned size)
439
+{
440
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
441
+ const uint32_t idx = REG_INDEX(offset);
442
+
443
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
445
+ __func__, (uint32_t)offset);
446
+ return 0;
195
+ return 0;
447
+ }
196
+ }
448
+
197
+
449
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
198
+ *sat = 1;
450
+
199
+ return MAKE_64BIT_MASK(0, 48);
451
+ return s->dramphy[idx];
200
+}
452
+}
201
+
453
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
454
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
203
+{
455
+ uint64_t val, unsigned size)
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
456
+{
205
+}
457
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
206
+
458
+ const uint32_t idx = REG_INDEX(offset);
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
459
+
208
+{
460
+ trace_allwinner_h3_dramphy_write(offset, val, size);
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
461
+
210
+}
462
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
463
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
212
index XXXXXXX..XXXXXXX 100644
464
+ __func__, (uint32_t)offset);
213
--- a/target/arm/translate.c
465
+ return;
214
+++ b/target/arm/translate.c
466
+ }
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
467
+
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
468
+ s->dramphy[idx] = (uint32_t) val;
217
}
469
+}
218
470
+
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
471
+static const MemoryRegionOps allwinner_h3_dramcom_ops = {
220
+{
472
+ .read = allwinner_h3_dramcom_read,
221
+ TCGv_i64 rda;
473
+ .write = allwinner_h3_dramcom_write,
222
+ TCGv_i32 rdalo, rdahi;
474
+ .endianness = DEVICE_NATIVE_ENDIAN,
223
+
475
+ .valid = {
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
476
+ .min_access_size = 4,
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
477
+ .max_access_size = 4,
226
+ return false;
478
+ },
227
+ }
479
+ .impl.min_access_size = 4,
228
+ if (a->rdahi == 15) {
480
+};
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
481
+
230
+ return false;
482
+static const MemoryRegionOps allwinner_h3_dramctl_ops = {
231
+ }
483
+ .read = allwinner_h3_dramctl_read,
232
+ if (!dc_isar_feature(aa32_mve, s) ||
484
+ .write = allwinner_h3_dramctl_write,
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
485
+ .endianness = DEVICE_NATIVE_ENDIAN,
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
486
+ .valid = {
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
487
+ .min_access_size = 4,
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
488
+ .max_access_size = 4,
237
+ unallocated_encoding(s);
489
+ },
238
+ return true;
490
+ .impl.min_access_size = 4,
239
+ }
491
+};
240
+
492
+
241
+ rda = tcg_temp_new_i64();
493
+static const MemoryRegionOps allwinner_h3_dramphy_ops = {
242
+ rdalo = load_reg(s, a->rdalo);
494
+ .read = allwinner_h3_dramphy_read,
243
+ rdahi = load_reg(s, a->rdahi);
495
+ .write = allwinner_h3_dramphy_write,
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
496
+ .endianness = DEVICE_NATIVE_ENDIAN,
245
+
497
+ .valid = {
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
498
+ .min_access_size = 4,
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
499
+ .max_access_size = 4,
248
+
500
+ },
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
501
+ .impl.min_access_size = 4,
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
502
+};
251
+ store_reg(s, a->rdalo, rdalo);
503
+
252
+ store_reg(s, a->rdahi, rdahi);
504
+static void allwinner_h3_dramc_reset(DeviceState *dev)
253
+ tcg_temp_free_i64(rda);
505
+{
254
+
506
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
255
+ return true;
507
+
256
+}
508
+ /* Set default values for registers */
257
+
509
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
510
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
259
+{
511
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
512
+}
261
+}
513
+
262
+
514
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
515
+{
264
+{
516
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
517
+
266
+}
518
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
267
+
519
+ for (uint8_t i = 8; i < 13; i++) {
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
520
+ if (1 << i == s->ram_size) {
269
+{
521
+ break;
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
522
+ } else if (i == 12) {
271
+}
523
+ error_report("%s: ram-size %u MiB is not supported",
272
+
524
+ __func__, s->ram_size);
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
525
+ exit(1);
274
+{
526
+ }
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
527
+ }
276
+}
528
+
277
+
529
+ /* Setup row mirror mappings */
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
530
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
279
+{
531
+ "allwinner-h3-dramc.row-mirror",
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
532
+ 4 * KiB, &error_abort);
281
+}
533
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
282
+
534
+ &s->row_mirror, 10);
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
535
+
284
+{
536
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
537
+ "allwinner-h3-dramc.row-mirror-alias",
286
+}
538
+ &s->row_mirror, 0, 4 * KiB);
287
+
539
+ memory_region_add_subregion_overlap(get_system_memory(),
288
/*
540
+ s->ram_addr + 1 * MiB,
289
* Multiply and multiply accumulate
541
+ &s->row_mirror_alias, 10);
290
*/
542
+ memory_region_set_enabled(&s->row_mirror_alias, false);
543
+}
544
+
545
+static void allwinner_h3_dramc_init(Object *obj)
546
+{
547
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
548
+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);
549
+
550
+ /* DRAMCOM registers */
551
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
552
+ &allwinner_h3_dramcom_ops, s,
553
+ TYPE_AW_H3_DRAMC, 4 * KiB);
554
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
555
+
556
+ /* DRAMCTL registers */
557
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
558
+ &allwinner_h3_dramctl_ops, s,
559
+ TYPE_AW_H3_DRAMC, 4 * KiB);
560
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
561
+
562
+ /* DRAMPHY registers */
563
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
564
+ &allwinner_h3_dramphy_ops, s,
565
+ TYPE_AW_H3_DRAMC, 4 * KiB);
566
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
567
+}
568
+
569
+static Property allwinner_h3_dramc_properties[] = {
570
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
571
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
572
+ DEFINE_PROP_END_OF_LIST()
573
+};
574
+
575
+static const VMStateDescription allwinner_h3_dramc_vmstate = {
576
+ .name = "allwinner-h3-dramc",
577
+ .version_id = 1,
578
+ .minimum_version_id = 1,
579
+ .fields = (VMStateField[]) {
580
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
581
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
582
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
583
+ VMSTATE_END_OF_LIST()
584
+ }
585
+};
586
+
587
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
588
+{
589
+ DeviceClass *dc = DEVICE_CLASS(klass);
590
+
591
+ dc->reset = allwinner_h3_dramc_reset;
592
+ dc->vmsd = &allwinner_h3_dramc_vmstate;
593
+ dc->realize = allwinner_h3_dramc_realize;
594
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
595
+}
596
+
597
+static const TypeInfo allwinner_h3_dramc_info = {
598
+ .name = TYPE_AW_H3_DRAMC,
599
+ .parent = TYPE_SYS_BUS_DEVICE,
600
+ .instance_init = allwinner_h3_dramc_init,
601
+ .instance_size = sizeof(AwH3DramCtlState),
602
+ .class_init = allwinner_h3_dramc_class_init,
603
+};
604
+
605
+static void allwinner_h3_dramc_register(void)
606
+{
607
+ type_register_static(&allwinner_h3_dramc_info);
608
+}
609
+
610
+type_init(allwinner_h3_dramc_register)
611
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
612
index XXXXXXX..XXXXXXX 100644
613
--- a/hw/misc/trace-events
614
+++ b/hw/misc/trace-events
615
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
616
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
617
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
618
619
+# allwinner-h3-dramc.c
620
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
621
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
622
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
623
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
624
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
625
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
626
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
627
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
628
+
629
# allwinner-sid.c
630
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
631
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
632
--
291
--
633
2.20.1
292
2.20.1
634
293
635
294
diff view generated by jsdifflib
1
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
1
Implement the MVE shifts by immediate, which perform shifts
2
(it changes the NegPri bit). We update the hflags after calls
2
on a single general-purpose register.
3
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
3
4
in trans_CPS_v7m().
4
These patterns overlap with the long-shift-by-immediates,
5
so we have to rearrange the grouping a little here.
5
6
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200303174950.3298-3-peter.maydell@linaro.org
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
9
---
10
---
10
target/arm/translate.c | 5 ++++-
11
target/arm/helper-mve.h | 3 ++
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
target/arm/translate.h | 1 +
12
13
target/arm/t32.decode | 31 ++++++++++++++-----
14
target/arm/mve_helper.c | 10 ++++++
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
16
5 files changed, 104 insertions(+), 9 deletions(-)
17
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
21
+++ b/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
45
@@ -XXX,XX +XXX,XX @@
46
47
&mve_shl_ri rdalo rdahi shim
48
&mve_shl_rr rdalo rdahi rm
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
105
}
106
+
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
108
+{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
110
+}
111
+
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
113
+{
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
115
+}
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
117
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
118
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
119
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
18
121
19
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
20
{
123
{
21
- TCGv_i32 tmp, addr;
124
- TCGv_i32 t = tcg_temp_new_i32();
22
+ TCGv_i32 tmp, addr, el;
125
+ TCGv_i32 t;
23
126
24
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
25
return false;
128
+ if (sh == 32) {
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
129
+ tcg_gen_movi_i32(d, 0);
27
gen_helper_v7m_msr(cpu_env, addr, tmp);
130
+ return;
28
tcg_temp_free_i32(addr);
131
+ }
29
}
132
+ t = tcg_temp_new_i32();
30
+ el = tcg_const_i32(s->current_el);
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
31
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
134
tcg_gen_sari_i32(d, a, sh);
32
+ tcg_temp_free_i32(el);
135
tcg_gen_add_i32(d, d, t);
33
tcg_temp_free_i32(tmp);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
34
gen_lookup_tb(s);
137
35
return true;
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
154
}
155
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
157
+{
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
36
--
211
--
37
2.20.1
212
2.20.1
38
213
39
214
diff view generated by jsdifflib
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
5
Reviewed-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20200206112645.21275-2-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
Makefile.objs | 1 +
11
hw/ssi/aspeed_smc.c | 17 +++++++++++++++++
12
hw/ssi/trace-events | 9 +++++++++
13
3 files changed, 27 insertions(+)
14
create mode 100644 hw/ssi/trace-events
15
16
diff --git a/Makefile.objs b/Makefile.objs
17
index XXXXXXX..XXXXXXX 100644
18
--- a/Makefile.objs
19
+++ b/Makefile.objs
20
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi
21
trace-events-subdirs += hw/sd
22
trace-events-subdirs += hw/sparc
23
trace-events-subdirs += hw/sparc64
24
+trace-events-subdirs += hw/ssi
25
trace-events-subdirs += hw/timer
26
trace-events-subdirs += hw/tpm
27
trace-events-subdirs += hw/usb
28
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/ssi/aspeed_smc.c
31
+++ b/hw/ssi/aspeed_smc.c
32
@@ -XXX,XX +XXX,XX @@
33
#include "qapi/error.h"
34
#include "exec/address-spaces.h"
35
#include "qemu/units.h"
36
+#include "trace.h"
37
38
#include "hw/irq.h"
39
#include "hw/qdev-properties.h"
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
41
42
s->ctrl->reg_to_segment(s, new, &seg);
43
44
+ trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
45
+
46
/* The start address of CS0 is read-only */
47
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
48
qemu_log_mask(LOG_GUEST_ERROR,
49
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
50
__func__, aspeed_smc_flash_mode(fl));
51
}
52
53
+ trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
54
+ aspeed_smc_flash_mode(fl));
55
return ret;
56
}
57
58
@@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
59
AspeedSMCState *s = fl->controller;
60
uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
61
62
+ trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
63
+ (uint8_t) data & 0xff);
64
+
65
if (s->snoop_index == SNOOP_OFF) {
66
return false; /* Do nothing */
67
68
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
69
AspeedSMCState *s = fl->controller;
70
int i;
71
72
+ trace_aspeed_smc_flash_write(fl->id, addr, size, data,
73
+ aspeed_smc_flash_mode(fl));
74
+
75
if (!aspeed_smc_is_writable(fl)) {
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
77
HWADDR_PRIx "\n", __func__, addr);
78
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
79
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
80
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
81
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
82
+
83
+ trace_aspeed_smc_read(addr, size, s->regs[addr]);
84
+
85
return s->regs[addr];
86
} else {
87
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
88
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
89
__func__, s->regs[R_DMA_FLASH_ADDR]);
90
return;
91
}
92
+ trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
93
94
/*
95
* When the DMA is on-going, the DMA registers are updated
96
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
97
98
addr >>= 2;
99
100
+ trace_aspeed_smc_write(addr, size, data);
101
+
102
if (addr == s->r_conf ||
103
(addr >= s->r_timings &&
104
addr < s->r_timings + s->ctrl->nregs_timings) ||
105
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
106
new file mode 100644
107
index XXXXXXX..XXXXXXX
108
--- /dev/null
109
+++ b/hw/ssi/trace-events
110
@@ -XXX,XX +XXX,XX @@
111
+# aspeed_smc.c
112
+
113
+aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
114
+aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
115
+aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
116
+aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
117
+aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
118
+aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
119
+aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
120
--
121
2.20.1
122
123
diff view generated by jsdifflib
Deleted patch
1
From: Igor Mammedov <imammedo@redhat.com>
2
1
3
SOC object returned by object_new() is leaked in current code.
4
Set SOC parent explicitly to board and then unref to SOC object
5
to make sure that refererence returned by object_new() is taken
6
care of.
7
8
The SOC object will be kept alive by its parent (machine) and
9
will be automatically freed when MachineState is destroyed.
10
11
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
12
Reported-by: Andrew Jones <drjones@redhat.com>
13
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Message-id: 20200303091254.22373-1-imammedo@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/arm/cubieboard.c | 3 +++
19
1 file changed, 3 insertions(+)
20
21
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/cubieboard.c
24
+++ b/hw/arm/cubieboard.c
25
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
26
}
27
28
a10 = AW_A10(object_new(TYPE_AW_A10));
29
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),
30
+ &error_abort);
31
+ object_unref(OBJECT(a10));
32
33
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
34
if (err != NULL) {
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
4
provided on the command line to available eSDHC controllers.
5
6
This patch enables booting the imx25-pdk emulation from SD card.
7
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200310215146.19688-2-linux@roeck-us.net
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: made commit subject consistent with other patch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/hw/arm/fsl-imx25.h | 9 +++++++++
15
hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++
16
hw/arm/imx25_pdk.c | 16 ++++++++++++++++
17
3 files changed, 57 insertions(+)
18
19
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/fsl-imx25.h
22
+++ b/include/hw/arm/fsl-imx25.h
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/misc/imx_rngc.h"
25
#include "hw/i2c/imx_i2c.h"
26
#include "hw/gpio/imx_gpio.h"
27
+#include "hw/sd/sdhci.h"
28
#include "exec/memory.h"
29
#include "target/arm/cpu.h"
30
31
@@ -XXX,XX +XXX,XX @@
32
#define FSL_IMX25_NUM_EPITS 2
33
#define FSL_IMX25_NUM_I2CS 3
34
#define FSL_IMX25_NUM_GPIOS 4
35
+#define FSL_IMX25_NUM_ESDHCS 2
36
37
typedef struct FslIMX25State {
38
/*< private >*/
39
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
40
IMXRNGCState rngc;
41
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
42
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
43
+ SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
44
MemoryRegion rom[2];
45
MemoryRegion iram;
46
MemoryRegion iram_alias;
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
#define FSL_IMX25_GPIO3_SIZE 0x4000
49
#define FSL_IMX25_RNGC_ADDR 0x53FB0000
50
#define FSL_IMX25_RNGC_SIZE 0x4000
51
+#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
52
+#define FSL_IMX25_ESDHC1_SIZE 0x4000
53
+#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
54
+#define FSL_IMX25_ESDHC2_SIZE 0x4000
55
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
56
#define FSL_IMX25_GPIO1_SIZE 0x4000
57
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
58
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
59
#define FSL_IMX25_GPIO2_IRQ 51
60
#define FSL_IMX25_GPIO3_IRQ 16
61
#define FSL_IMX25_GPIO4_IRQ 23
62
+#define FSL_IMX25_ESDHC1_IRQ 9
63
+#define FSL_IMX25_ESDHC2_IRQ 8
64
65
#endif /* FSL_IMX25_H */
66
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/fsl-imx25.c
69
+++ b/hw/arm/fsl-imx25.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "hw/qdev-properties.h"
72
#include "chardev/char.h"
73
74
+#define IMX25_ESDHC_CAPABILITIES 0x07e20000
75
+
76
static void fsl_imx25_init(Object *obj)
77
{
78
FslIMX25State *s = FSL_IMX25(obj);
79
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
80
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
81
TYPE_IMX_GPIO);
82
}
83
+
84
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
85
+ sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
86
+ TYPE_IMX_USDHC);
87
+ }
88
}
89
90
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
91
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
92
gpio_table[i].irq));
93
}
94
95
+ /* Initialize all SDHC */
96
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
97
+ static const struct {
98
+ hwaddr addr;
99
+ unsigned int irq;
100
+ } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
101
+ { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
102
+ { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
103
+ };
104
+
105
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
106
+ &err);
107
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
108
+ "capareg", &err);
109
+ object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
110
+ if (err) {
111
+ error_propagate(errp, err);
112
+ return;
113
+ }
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->avic),
117
+ esdhc_table[i].irq));
118
+ }
119
+
120
/* initialize 2 x 16 KB ROM */
121
memory_region_init_rom(&s->rom[0], NULL,
122
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
123
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/imx25_pdk.c
126
+++ b/hw/arm/imx25_pdk.c
127
@@ -XXX,XX +XXX,XX @@
128
#include "qemu/osdep.h"
129
#include "qapi/error.h"
130
#include "cpu.h"
131
+#include "hw/qdev-properties.h"
132
#include "hw/arm/fsl-imx25.h"
133
#include "hw/boards.h"
134
#include "qemu/error-report.h"
135
@@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine)
136
imx25_pdk_binfo.board_id = 1771,
137
imx25_pdk_binfo.nb_cpus = 1;
138
139
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
140
+ BusState *bus;
141
+ DeviceState *carddev;
142
+ DriveInfo *di;
143
+ BlockBackend *blk;
144
+
145
+ di = drive_get_next(IF_SD);
146
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
147
+ bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
148
+ carddev = qdev_create(bus, TYPE_SD_CARD);
149
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
150
+ object_property_set_bool(OBJECT(carddev), true,
151
+ "realized", &error_fatal);
152
+ }
153
+
154
/*
155
* We test explicitly for qtest here as it is not done (yet?) in
156
* arm_load_kernel(). Without this the "make check" command would
157
--
158
2.20.1
159
160
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
i.MX25 supports two USB controllers. Let's wire them up.
4
5
With this patch, imx25-pdk can boot from both USB ports.
6
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200310215146.19688-3-linux@roeck-us.net
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/fsl-imx25.h | 9 +++++++++
13
hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++
14
2 files changed, 33 insertions(+)
15
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
19
+++ b/include/hw/arm/fsl-imx25.h
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/i2c/imx_i2c.h"
22
#include "hw/gpio/imx_gpio.h"
23
#include "hw/sd/sdhci.h"
24
+#include "hw/usb/chipidea.h"
25
#include "exec/memory.h"
26
#include "target/arm/cpu.h"
27
28
@@ -XXX,XX +XXX,XX @@
29
#define FSL_IMX25_NUM_I2CS 3
30
#define FSL_IMX25_NUM_GPIOS 4
31
#define FSL_IMX25_NUM_ESDHCS 2
32
+#define FSL_IMX25_NUM_USBS 2
33
34
typedef struct FslIMX25State {
35
/*< private >*/
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
38
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
39
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
40
+ ChipideaState usb[FSL_IMX25_NUM_USBS];
41
MemoryRegion rom[2];
42
MemoryRegion iram;
43
MemoryRegion iram_alias;
44
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
45
#define FSL_IMX25_GPIO1_SIZE 0x4000
46
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
47
#define FSL_IMX25_GPIO2_SIZE 0x4000
48
+#define FSL_IMX25_USB1_ADDR 0x53FF4000
49
+#define FSL_IMX25_USB1_SIZE 0x0200
50
+#define FSL_IMX25_USB2_ADDR 0x53FF4400
51
+#define FSL_IMX25_USB2_SIZE 0x0200
52
#define FSL_IMX25_AVIC_ADDR 0x68000000
53
#define FSL_IMX25_AVIC_SIZE 0x4000
54
#define FSL_IMX25_IRAM_ADDR 0x78000000
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
56
#define FSL_IMX25_GPIO4_IRQ 23
57
#define FSL_IMX25_ESDHC1_IRQ 9
58
#define FSL_IMX25_ESDHC2_IRQ 8
59
+#define FSL_IMX25_USB1_IRQ 37
60
+#define FSL_IMX25_USB2_IRQ 35
61
62
#endif /* FSL_IMX25_H */
63
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/fsl-imx25.c
66
+++ b/hw/arm/fsl-imx25.c
67
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
68
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
69
TYPE_IMX_USDHC);
70
}
71
+
72
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
73
+ sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
74
+ TYPE_CHIPIDEA);
75
+ }
76
+
77
}
78
79
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
80
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
81
esdhc_table[i].irq));
82
}
83
84
+ /* USB */
85
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
86
+ static const struct {
87
+ hwaddr addr;
88
+ unsigned int irq;
89
+ } usb_table[FSL_IMX25_NUM_USBS] = {
90
+ { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
91
+ { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
92
+ };
93
+
94
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
95
+ &error_abort);
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
97
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
98
+ qdev_get_gpio_in(DEVICE(&s->avic),
99
+ usb_table[i].irq));
100
+ }
101
+
102
/* initialize 2 x 16 KB ROM */
103
memory_region_init_rom(&s->rom[0], NULL,
104
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
105
--
106
2.20.1
107
108
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
processor cores. Features and specifications include DDR2/DDR3 memory,
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
6
various I/O modules. This commit adds support for the Allwinner H3
7
---
7
System on Chip.
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
8
14
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/Makefile.objs | 1 +
17
include/hw/arm/allwinner-h3.h | 106 +++++++++++
18
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
19
MAINTAINERS | 7 +
20
default-configs/arm-softmmu.mak | 1 +
21
hw/arm/Kconfig | 8 +
22
6 files changed, 450 insertions(+)
23
create mode 100644 include/hw/arm/allwinner-h3.h
24
create mode 100644 hw/arm/allwinner-h3.c
25
26
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
27
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/Makefile.objs
17
--- a/target/arm/helper-mve.h
29
+++ b/hw/arm/Makefile.objs
18
+++ b/target/arm/helper-mve.h
30
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
obj-$(CONFIG_OMAP) += omap1.o omap2.o
20
32
obj-$(CONFIG_STRONGARM) += strongarm.o
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
33
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
26
index XXXXXXX..XXXXXXX 100644
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
27
--- a/target/arm/translate.h
39
new file mode 100644
28
+++ b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
41
--- /dev/null
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
42
+++ b/include/hw/arm/allwinner-h3.h
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
43
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
44
+/*
42
&mve_shl_ri rdalo rdahi shim
45
+ * Allwinner H3 System on Chip emulation
43
&mve_shl_rr rdalo rdahi rm
46
+ *
44
&mve_sh_ri rda shim
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
45
+&mve_sh_rr rda rm
48
+ *
46
49
+ * This program is free software: you can redistribute it and/or modify
47
# rdahi: bits [3:1] from insn, bit 0 is 1
50
+ * it under the terms of the GNU General Public License as published by
48
# rdalo: bits [3:1] from insn, bit 0 is 0
51
+ * the Free Software Foundation, either version 2 of the License, or
52
+ * (at your option) any later version.
53
+ *
54
+ * This program is distributed in the hope that it will be useful,
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57
+ * GNU General Public License for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
62
+
63
+/*
64
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
65
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
66
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
67
+ * various I/O modules.
68
+ *
69
+ * This implementation is based on the following datasheet:
70
+ *
71
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
72
+ *
73
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
74
+ *
75
+ * https://linux-sunxi.org/H3
76
+ */
77
+
78
+#ifndef HW_ARM_ALLWINNER_H3_H
79
+#define HW_ARM_ALLWINNER_H3_H
80
+
81
+#include "qom/object.h"
82
+#include "hw/arm/boot.h"
83
+#include "hw/timer/allwinner-a10-pit.h"
84
+#include "hw/intc/arm_gic.h"
85
+#include "target/arm/cpu.h"
86
+
87
+/**
88
+ * Allwinner H3 device list
89
+ *
90
+ * This enumeration is can be used refer to a particular device in the
91
+ * Allwinner H3 SoC. For example, the physical memory base address for
92
+ * each device can be found in the AwH3State object in the memmap member
93
+ * using the device enum value as index.
94
+ *
95
+ * @see AwH3State
96
+ */
97
+enum {
98
+ AW_H3_SRAM_A1,
99
+ AW_H3_SRAM_A2,
100
+ AW_H3_SRAM_C,
101
+ AW_H3_PIT,
102
+ AW_H3_UART0,
103
+ AW_H3_UART1,
104
+ AW_H3_UART2,
105
+ AW_H3_UART3,
106
+ AW_H3_GIC_DIST,
107
+ AW_H3_GIC_CPU,
108
+ AW_H3_GIC_HYP,
109
+ AW_H3_GIC_VCPU,
110
+ AW_H3_SDRAM
111
+};
112
+
113
+/** Total number of CPU cores in the H3 SoC */
114
+#define AW_H3_NUM_CPUS (4)
115
+
116
+/**
117
+ * Allwinner H3 object model
118
+ * @{
119
+ */
120
+
121
+/** Object type for the Allwinner H3 SoC */
122
+#define TYPE_AW_H3 "allwinner-h3"
123
+
124
+/** Convert input object to Allwinner H3 state object */
125
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
126
+
127
+/** @} */
128
+
129
+/**
130
+ * Allwinner H3 object
131
+ *
132
+ * This struct contains the state of all the devices
133
+ * which are currently emulated by the H3 SoC code.
134
+ */
135
+typedef struct AwH3State {
136
+ /*< private >*/
137
+ DeviceState parent_obj;
138
+ /*< public >*/
139
+
140
+ ARMCPU cpus[AW_H3_NUM_CPUS];
141
+ const hwaddr *memmap;
142
+ AwA10PITState timer;
143
+ GICState gic;
144
+ MemoryRegion sram_a1;
145
+ MemoryRegion sram_a2;
146
+ MemoryRegion sram_c;
147
+} AwH3State;
148
+
149
+#endif /* HW_ARM_ALLWINNER_H3_H */
150
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
151
new file mode 100644
152
index XXXXXXX..XXXXXXX
153
--- /dev/null
154
+++ b/hw/arm/allwinner-h3.c
155
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@
156
+/*
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
157
+ * Allwinner H3 System on Chip emulation
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
158
+ *
52
&mve_sh_ri shim=%imm5_12_6
159
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
160
+ *
54
161
+ * This program is free software: you can redistribute it and/or modify
55
{
162
+ * it under the terms of the GNU General Public License as published by
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
163
+ * the Free Software Foundation, either version 2 of the License, or
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
164
+ * (at your option) any later version.
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
165
+ *
59
}
166
+ * This program is distributed in the hope that it will be useful,
60
167
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
168
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
169
+ * GNU General Public License for more details.
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
170
+ *
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
171
+ * You should have received a copy of the GNU General Public License
65
+ {
172
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
173
+ */
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
174
+
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
175
+#include "qemu/osdep.h"
176
+#include "exec/address-spaces.h"
177
+#include "qapi/error.h"
178
+#include "qemu/error-report.h"
179
+#include "qemu/module.h"
180
+#include "qemu/units.h"
181
+#include "hw/qdev-core.h"
182
+#include "cpu.h"
183
+#include "hw/sysbus.h"
184
+#include "hw/char/serial.h"
185
+#include "hw/misc/unimp.h"
186
+#include "sysemu/sysemu.h"
187
+#include "hw/arm/allwinner-h3.h"
188
+
189
+/* Memory map */
190
+const hwaddr allwinner_h3_memmap[] = {
191
+ [AW_H3_SRAM_A1] = 0x00000000,
192
+ [AW_H3_SRAM_A2] = 0x00044000,
193
+ [AW_H3_SRAM_C] = 0x00010000,
194
+ [AW_H3_PIT] = 0x01c20c00,
195
+ [AW_H3_UART0] = 0x01c28000,
196
+ [AW_H3_UART1] = 0x01c28400,
197
+ [AW_H3_UART2] = 0x01c28800,
198
+ [AW_H3_UART3] = 0x01c28c00,
199
+ [AW_H3_GIC_DIST] = 0x01c81000,
200
+ [AW_H3_GIC_CPU] = 0x01c82000,
201
+ [AW_H3_GIC_HYP] = 0x01c84000,
202
+ [AW_H3_GIC_VCPU] = 0x01c86000,
203
+ [AW_H3_SDRAM] = 0x40000000
204
+};
205
+
206
+/* List of unimplemented devices */
207
+struct AwH3Unimplemented {
208
+ const char *device_name;
209
+ hwaddr base;
210
+ hwaddr size;
211
+} unimplemented[] = {
212
+ { "d-engine", 0x01000000, 4 * MiB },
213
+ { "d-inter", 0x01400000, 128 * KiB },
214
+ { "syscon", 0x01c00000, 4 * KiB },
215
+ { "dma", 0x01c02000, 4 * KiB },
216
+ { "nfdc", 0x01c03000, 4 * KiB },
217
+ { "ts", 0x01c06000, 4 * KiB },
218
+ { "keymem", 0x01c0b000, 4 * KiB },
219
+ { "lcd0", 0x01c0c000, 4 * KiB },
220
+ { "lcd1", 0x01c0d000, 4 * KiB },
221
+ { "ve", 0x01c0e000, 4 * KiB },
222
+ { "mmc0", 0x01c0f000, 4 * KiB },
223
+ { "mmc1", 0x01c10000, 4 * KiB },
224
+ { "mmc2", 0x01c11000, 4 * KiB },
225
+ { "sid", 0x01c14000, 1 * KiB },
226
+ { "crypto", 0x01c15000, 4 * KiB },
227
+ { "msgbox", 0x01c17000, 4 * KiB },
228
+ { "spinlock", 0x01c18000, 4 * KiB },
229
+ { "usb0-otg", 0x01c19000, 4 * KiB },
230
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
231
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
232
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
233
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
234
+ { "smc", 0x01c1e000, 4 * KiB },
235
+ { "ccu", 0x01c20000, 1 * KiB },
236
+ { "pio", 0x01c20800, 1 * KiB },
237
+ { "owa", 0x01c21000, 1 * KiB },
238
+ { "pwm", 0x01c21400, 1 * KiB },
239
+ { "keyadc", 0x01c21800, 1 * KiB },
240
+ { "pcm0", 0x01c22000, 1 * KiB },
241
+ { "pcm1", 0x01c22400, 1 * KiB },
242
+ { "pcm2", 0x01c22800, 1 * KiB },
243
+ { "audio", 0x01c22c00, 2 * KiB },
244
+ { "smta", 0x01c23400, 1 * KiB },
245
+ { "ths", 0x01c25000, 1 * KiB },
246
+ { "uart0", 0x01c28000, 1 * KiB },
247
+ { "uart1", 0x01c28400, 1 * KiB },
248
+ { "uart2", 0x01c28800, 1 * KiB },
249
+ { "uart3", 0x01c28c00, 1 * KiB },
250
+ { "twi0", 0x01c2ac00, 1 * KiB },
251
+ { "twi1", 0x01c2b000, 1 * KiB },
252
+ { "twi2", 0x01c2b400, 1 * KiB },
253
+ { "scr", 0x01c2c400, 1 * KiB },
254
+ { "emac", 0x01c30000, 64 * KiB },
255
+ { "gpu", 0x01c40000, 64 * KiB },
256
+ { "hstmr", 0x01c60000, 4 * KiB },
257
+ { "dramcom", 0x01c62000, 4 * KiB },
258
+ { "dramctl0", 0x01c63000, 4 * KiB },
259
+ { "dramphy0", 0x01c65000, 4 * KiB },
260
+ { "spi0", 0x01c68000, 4 * KiB },
261
+ { "spi1", 0x01c69000, 4 * KiB },
262
+ { "csi", 0x01cb0000, 320 * KiB },
263
+ { "tve", 0x01e00000, 64 * KiB },
264
+ { "hdmi", 0x01ee0000, 128 * KiB },
265
+ { "rtc", 0x01f00000, 1 * KiB },
266
+ { "r_timer", 0x01f00800, 1 * KiB },
267
+ { "r_intc", 0x01f00c00, 1 * KiB },
268
+ { "r_wdog", 0x01f01000, 1 * KiB },
269
+ { "r_prcm", 0x01f01400, 1 * KiB },
270
+ { "r_twd", 0x01f01800, 1 * KiB },
271
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
272
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
273
+ { "r_twi", 0x01f02400, 1 * KiB },
274
+ { "r_uart", 0x01f02800, 1 * KiB },
275
+ { "r_pio", 0x01f02c00, 1 * KiB },
276
+ { "r_pwm", 0x01f03800, 1 * KiB },
277
+ { "core-dbg", 0x3f500000, 128 * KiB },
278
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
279
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
280
+ { "ddr-mem", 0x40000000, 2 * GiB },
281
+ { "n-brom", 0xffff0000, 32 * KiB },
282
+ { "s-brom", 0xffff0000, 64 * KiB }
283
+};
284
+
285
+/* Per Processor Interrupts */
286
+enum {
287
+ AW_H3_GIC_PPI_MAINT = 9,
288
+ AW_H3_GIC_PPI_HYPTIMER = 10,
289
+ AW_H3_GIC_PPI_VIRTTIMER = 11,
290
+ AW_H3_GIC_PPI_SECTIMER = 13,
291
+ AW_H3_GIC_PPI_PHYSTIMER = 14
292
+};
293
+
294
+/* Shared Processor Interrupts */
295
+enum {
296
+ AW_H3_GIC_SPI_UART0 = 0,
297
+ AW_H3_GIC_SPI_UART1 = 1,
298
+ AW_H3_GIC_SPI_UART2 = 2,
299
+ AW_H3_GIC_SPI_UART3 = 3,
300
+ AW_H3_GIC_SPI_TIMER0 = 18,
301
+ AW_H3_GIC_SPI_TIMER1 = 19,
302
+};
303
+
304
+/* Allwinner H3 general constants */
305
+enum {
306
+ AW_H3_GIC_NUM_SPI = 128
307
+};
308
+
309
+static void allwinner_h3_init(Object *obj)
310
+{
311
+ AwH3State *s = AW_H3(obj);
312
+
313
+ s->memmap = allwinner_h3_memmap;
314
+
315
+ for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
316
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
317
+ ARM_CPU_TYPE_NAME("cortex-a7"),
318
+ &error_abort, NULL);
319
+ }
69
+ }
320
+
70
+
321
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
71
+ {
322
+ TYPE_ARM_GIC);
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
323
+
76
+
324
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
325
+ TYPE_AW_A10_PIT);
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
326
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
79
]
327
+ "clk0-freq", &error_abort);
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
328
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
81
index XXXXXXX..XXXXXXX 100644
329
+ "clk1-freq", &error_abort);
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
330
+}
92
+}
331
+
93
+
332
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
333
+{
95
+{
334
+ AwH3State *s = AW_H3(dev);
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
335
+ unsigned i;
97
+}
336
+
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
337
+ /* CPUs */
99
index XXXXXXX..XXXXXXX 100644
338
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
100
--- a/target/arm/translate.c
339
+
101
+++ b/target/arm/translate.c
340
+ /* Provide Power State Coordination Interface */
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
341
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
342
+ QEMU_PSCI_CONDUIT_HVC);
104
}
343
+
105
344
+ /* Disable secondary CPUs */
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
345
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
107
+{
346
+ i > 0);
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
347
+
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
348
+ /* All exception levels required */
110
+ return false;
349
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
111
+ }
350
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
112
+ if (!dc_isar_feature(aa32_mve, s) ||
351
+
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
352
+ /* Mark realized */
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
353
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
354
+ }
119
+ }
355
+
120
+
356
+ /* Generic Interrupt Controller */
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
357
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
358
+ GIC_INTERNAL);
123
+ return true;
359
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
360
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
361
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
362
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
363
+ qdev_init_nofail(DEVICE(&s->gic));
364
+
365
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
366
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
367
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
368
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
369
+
370
+ /*
371
+ * Wire the outputs from each CPU's generic timer and the GICv3
372
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
373
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
374
+ */
375
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
376
+ DeviceState *cpudev = DEVICE(&s->cpus[i]);
377
+ int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
378
+ int irq;
379
+ /*
380
+ * Mapping from the output timer irq lines from the CPU to the
381
+ * GIC PPI inputs used for this board.
382
+ */
383
+ const int timer_irq[] = {
384
+ [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
385
+ [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
386
+ [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
387
+ [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
388
+ };
389
+
390
+ /* Connect CPU timer outputs to GIC PPI inputs */
391
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
392
+ qdev_connect_gpio_out(cpudev, irq,
393
+ qdev_get_gpio_in(DEVICE(&s->gic),
394
+ ppibase + timer_irq[irq]));
395
+ }
396
+
397
+ /* Connect GIC outputs to CPU interrupt inputs */
398
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
399
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
400
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
401
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
402
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
403
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
404
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
405
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
406
+
407
+ /* GIC maintenance signal */
408
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
409
+ qdev_get_gpio_in(DEVICE(&s->gic),
410
+ ppibase + AW_H3_GIC_PPI_MAINT));
411
+ }
412
+
413
+ /* Timer */
414
+ qdev_init_nofail(DEVICE(&s->timer));
415
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
416
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
417
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
418
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
419
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
420
+
421
+ /* SRAM */
422
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
423
+ 64 * KiB, &error_abort);
424
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
425
+ 32 * KiB, &error_abort);
426
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
427
+ 44 * KiB, &error_abort);
428
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
429
+ &s->sram_a1);
430
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
431
+ &s->sram_a2);
432
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
433
+ &s->sram_c);
434
+
435
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
436
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
437
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
438
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
439
+ /* UART1 */
440
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
441
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
442
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
443
+ /* UART2 */
444
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
445
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
446
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
447
+ /* UART3 */
448
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
449
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
450
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
451
+
452
+ /* Unimplemented devices */
453
+ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
454
+ create_unimplemented_device(unimplemented[i].device_name,
455
+ unimplemented[i].base,
456
+ unimplemented[i].size);
457
+ }
458
+}
124
+}
459
+
125
+
460
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
461
+{
127
+{
462
+ DeviceClass *dc = DEVICE_CLASS(oc);
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
463
+
464
+ dc->realize = allwinner_h3_realize;
465
+ /* Reason: uses serial_hd() in realize function */
466
+ dc->user_creatable = false;
467
+}
129
+}
468
+
130
+
469
+static const TypeInfo allwinner_h3_type_info = {
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
470
+ .name = TYPE_AW_H3,
471
+ .parent = TYPE_DEVICE,
472
+ .instance_size = sizeof(AwH3State),
473
+ .instance_init = allwinner_h3_init,
474
+ .class_init = allwinner_h3_class_init,
475
+};
476
+
477
+static void allwinner_h3_register_types(void)
478
+{
132
+{
479
+ type_register_static(&allwinner_h3_type_info);
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
480
+}
134
+}
481
+
135
+
482
+type_init(allwinner_h3_register_types)
136
/*
483
diff --git a/MAINTAINERS b/MAINTAINERS
137
* Multiply and multiply accumulate
484
index XXXXXXX..XXXXXXX 100644
138
*/
485
--- a/MAINTAINERS
486
+++ b/MAINTAINERS
487
@@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner*
488
F: include/hw/*/allwinner*
489
F: hw/arm/cubieboard.c
490
491
+Allwinner-h3
492
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
493
+L: qemu-arm@nongnu.org
494
+S: Maintained
495
+F: hw/*/allwinner-h3*
496
+F: include/hw/*/allwinner-h3*
497
+
498
ARM PrimeCell and CMSDK devices
499
M: Peter Maydell <peter.maydell@linaro.org>
500
L: qemu-arm@nongnu.org
501
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
502
index XXXXXXX..XXXXXXX 100644
503
--- a/default-configs/arm-softmmu.mak
504
+++ b/default-configs/arm-softmmu.mak
505
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y
506
CONFIG_FSL_IMX7=y
507
CONFIG_FSL_IMX6UL=y
508
CONFIG_SEMIHOSTING=y
509
+CONFIG_ALLWINNER_H3=y
510
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
511
index XXXXXXX..XXXXXXX 100644
512
--- a/hw/arm/Kconfig
513
+++ b/hw/arm/Kconfig
514
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
515
select SERIAL
516
select UNIMP
517
518
+config ALLWINNER_H3
519
+ bool
520
+ select ALLWINNER_A10_PIT
521
+ select SERIAL
522
+ select ARM_TIMER
523
+ select ARM_GIC
524
+ select UNIMP
525
+
526
config RASPI
527
bool
528
select FRAMEBUFFER
529
--
139
--
530
2.20.1
140
2.20.1
531
141
532
142
diff view generated by jsdifflib
Deleted patch
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
2
1
3
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
4
based embedded computer with mainline support in both U-Boot
5
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
6
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
7
various other I/O. This commit add support for the Xunlong
8
Orange Pi PC machine.
9
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Acked-by: Igor Mammedov <imammedo@redhat.com>
16
Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/arm/Makefile.objs | 2 +-
20
hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
21
MAINTAINERS | 1 +
22
3 files changed, 94 insertions(+), 1 deletion(-)
23
create mode 100644 hw/arm/orangepi.c
24
25
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/Makefile.objs
28
+++ b/hw/arm/Makefile.objs
29
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
30
obj-$(CONFIG_OMAP) += omap1.o omap2.o
31
obj-$(CONFIG_STRONGARM) += strongarm.o
32
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
33
-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
38
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
39
new file mode 100644
40
index XXXXXXX..XXXXXXX
41
--- /dev/null
42
+++ b/hw/arm/orangepi.c
43
@@ -XXX,XX +XXX,XX @@
44
+/*
45
+ * Orange Pi emulation
46
+ *
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
48
+ *
49
+ * This program is free software: you can redistribute it and/or modify
50
+ * it under the terms of the GNU General Public License as published by
51
+ * the Free Software Foundation, either version 2 of the License, or
52
+ * (at your option) any later version.
53
+ *
54
+ * This program is distributed in the hope that it will be useful,
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57
+ * GNU General Public License for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
62
+
63
+#include "qemu/osdep.h"
64
+#include "qemu/units.h"
65
+#include "exec/address-spaces.h"
66
+#include "qapi/error.h"
67
+#include "cpu.h"
68
+#include "hw/sysbus.h"
69
+#include "hw/boards.h"
70
+#include "hw/qdev-properties.h"
71
+#include "hw/arm/allwinner-h3.h"
72
+#include "sysemu/sysemu.h"
73
+
74
+static struct arm_boot_info orangepi_binfo = {
75
+ .nb_cpus = AW_H3_NUM_CPUS,
76
+};
77
+
78
+static void orangepi_init(MachineState *machine)
79
+{
80
+ AwH3State *h3;
81
+
82
+ /* BIOS is not supported by this board */
83
+ if (bios_name) {
84
+ error_report("BIOS not supported for this machine");
85
+ exit(1);
86
+ }
87
+
88
+ /* This board has fixed size RAM */
89
+ if (machine->ram_size != 1 * GiB) {
90
+ error_report("This machine can only be used with 1GiB of RAM");
91
+ exit(1);
92
+ }
93
+
94
+ /* Only allow Cortex-A7 for this board */
95
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
96
+ error_report("This board can only be used with cortex-a7 CPU");
97
+ exit(1);
98
+ }
99
+
100
+ h3 = AW_H3(object_new(TYPE_AW_H3));
101
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(h3),
102
+ &error_abort);
103
+ object_unref(OBJECT(h3));
104
+
105
+ /* Setup timer properties */
106
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
107
+ &error_abort);
108
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
109
+ &error_abort);
110
+
111
+ /* Mark H3 object realized */
112
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
113
+
114
+ /* SDRAM */
115
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
116
+ machine->ram);
117
+
118
+ orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
119
+ orangepi_binfo.ram_size = machine->ram_size;
120
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
121
+}
122
+
123
+static void orangepi_machine_init(MachineClass *mc)
124
+{
125
+ mc->desc = "Orange Pi PC";
126
+ mc->init = orangepi_init;
127
+ mc->min_cpus = AW_H3_NUM_CPUS;
128
+ mc->max_cpus = AW_H3_NUM_CPUS;
129
+ mc->default_cpus = AW_H3_NUM_CPUS;
130
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
131
+ mc->default_ram_size = 1 * GiB;
132
+ mc->default_ram_id = "orangepi.ram";
133
+}
134
+
135
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
136
diff --git a/MAINTAINERS b/MAINTAINERS
137
index XXXXXXX..XXXXXXX 100644
138
--- a/MAINTAINERS
139
+++ b/MAINTAINERS
140
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
141
S: Maintained
142
F: hw/*/allwinner-h3*
143
F: include/hw/*/allwinner-h3*
144
+F: hw/arm/orangepi.c
145
146
ARM PrimeCell and CMSDK devices
147
M: Peter Maydell <peter.maydell@linaro.org>
148
--
149
2.20.1
150
151
diff view generated by jsdifflib
Deleted patch
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
2
1
3
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
4
connections which provide software access using the Enhanced
5
Host Controller Interface (EHCI) and Open Host Controller
6
Interface (OHCI) interfaces. This commit adds support for
7
both interfaces in the Allwinner H3 System on Chip.
8
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/usb/hcd-ehci.h | 1 +
18
include/hw/arm/allwinner-h3.h | 8 +++++++
19
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
20
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
21
hw/arm/Kconfig | 2 ++
22
5 files changed, 72 insertions(+)
23
24
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/usb/hcd-ehci.h
27
+++ b/hw/usb/hcd-ehci.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState {
29
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
30
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
31
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
32
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
33
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
34
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
35
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@ enum {
41
AW_H3_SRAM_A1,
42
AW_H3_SRAM_A2,
43
AW_H3_SRAM_C,
44
+ AW_H3_EHCI0,
45
+ AW_H3_OHCI0,
46
+ AW_H3_EHCI1,
47
+ AW_H3_OHCI1,
48
+ AW_H3_EHCI2,
49
+ AW_H3_OHCI2,
50
+ AW_H3_EHCI3,
51
+ AW_H3_OHCI3,
52
AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/allwinner-h3.c
58
+++ b/hw/arm/allwinner-h3.c
59
@@ -XXX,XX +XXX,XX @@
60
#include "hw/sysbus.h"
61
#include "hw/char/serial.h"
62
#include "hw/misc/unimp.h"
63
+#include "hw/usb/hcd-ehci.h"
64
#include "sysemu/sysemu.h"
65
#include "hw/arm/allwinner-h3.h"
66
67
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
68
[AW_H3_SRAM_A1] = 0x00000000,
69
[AW_H3_SRAM_A2] = 0x00044000,
70
[AW_H3_SRAM_C] = 0x00010000,
71
+ [AW_H3_EHCI0] = 0x01c1a000,
72
+ [AW_H3_OHCI0] = 0x01c1a400,
73
+ [AW_H3_EHCI1] = 0x01c1b000,
74
+ [AW_H3_OHCI1] = 0x01c1b400,
75
+ [AW_H3_EHCI2] = 0x01c1c000,
76
+ [AW_H3_OHCI2] = 0x01c1c400,
77
+ [AW_H3_EHCI3] = 0x01c1d000,
78
+ [AW_H3_OHCI3] = 0x01c1d400,
79
[AW_H3_CCU] = 0x01c20000,
80
[AW_H3_PIT] = 0x01c20c00,
81
[AW_H3_UART0] = 0x01c28000,
82
@@ -XXX,XX +XXX,XX @@ enum {
83
AW_H3_GIC_SPI_UART3 = 3,
84
AW_H3_GIC_SPI_TIMER0 = 18,
85
AW_H3_GIC_SPI_TIMER1 = 19,
86
+ AW_H3_GIC_SPI_EHCI0 = 72,
87
+ AW_H3_GIC_SPI_OHCI0 = 73,
88
+ AW_H3_GIC_SPI_EHCI1 = 74,
89
+ AW_H3_GIC_SPI_OHCI1 = 75,
90
+ AW_H3_GIC_SPI_EHCI2 = 76,
91
+ AW_H3_GIC_SPI_OHCI2 = 77,
92
+ AW_H3_GIC_SPI_EHCI3 = 78,
93
+ AW_H3_GIC_SPI_OHCI3 = 79,
94
};
95
96
/* Allwinner H3 general constants */
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
98
qdev_init_nofail(DEVICE(&s->ccu));
99
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
100
101
+ /* Universal Serial Bus */
102
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
103
+ qdev_get_gpio_in(DEVICE(&s->gic),
104
+ AW_H3_GIC_SPI_EHCI0));
105
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
106
+ qdev_get_gpio_in(DEVICE(&s->gic),
107
+ AW_H3_GIC_SPI_EHCI1));
108
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
109
+ qdev_get_gpio_in(DEVICE(&s->gic),
110
+ AW_H3_GIC_SPI_EHCI2));
111
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
112
+ qdev_get_gpio_in(DEVICE(&s->gic),
113
+ AW_H3_GIC_SPI_EHCI3));
114
+
115
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
116
+ qdev_get_gpio_in(DEVICE(&s->gic),
117
+ AW_H3_GIC_SPI_OHCI0));
118
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
119
+ qdev_get_gpio_in(DEVICE(&s->gic),
120
+ AW_H3_GIC_SPI_OHCI1));
121
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
122
+ qdev_get_gpio_in(DEVICE(&s->gic),
123
+ AW_H3_GIC_SPI_OHCI2));
124
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
125
+ qdev_get_gpio_in(DEVICE(&s->gic),
126
+ AW_H3_GIC_SPI_OHCI3));
127
+
128
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
129
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
130
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
131
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/usb/hcd-ehci-sysbus.c
134
+++ b/hw/usb/hcd-ehci-sysbus.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = {
136
.class_init = ehci_exynos4210_class_init,
137
};
138
139
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
140
+{
141
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
142
+ DeviceClass *dc = DEVICE_CLASS(oc);
143
+
144
+ sec->capsbase = 0x0;
145
+ sec->opregbase = 0x10;
146
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
147
+}
148
+
149
+static const TypeInfo ehci_aw_h3_type_info = {
150
+ .name = TYPE_AW_H3_EHCI,
151
+ .parent = TYPE_SYS_BUS_EHCI,
152
+ .class_init = ehci_aw_h3_class_init,
153
+};
154
+
155
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
156
{
157
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
158
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
159
type_register_static(&ehci_type_info);
160
type_register_static(&ehci_platform_type_info);
161
type_register_static(&ehci_exynos4210_type_info);
162
+ type_register_static(&ehci_aw_h3_type_info);
163
type_register_static(&ehci_tegra2_type_info);
164
type_register_static(&ehci_ppc4xx_type_info);
165
type_register_static(&ehci_fusbh200_type_info);
166
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
167
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/arm/Kconfig
169
+++ b/hw/arm/Kconfig
170
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
171
select ARM_TIMER
172
select ARM_GIC
173
select UNIMP
174
+ select USB_OHCI
175
+ select USB_EHCI_SYSBUS
176
177
config RASPI
178
bool
179
--
180
2.20.1
181
182
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots a Linux kernel on a OrangePi PC board and verify
4
the serial output is working.
5
6
The kernel image and DeviceTree blob are built by the Armbian
7
project (based on Debian):
8
https://www.armbian.com/orange-pi-pc/
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ make check-venv
16
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
17
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
18
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
19
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
20
console: Uncompressing Linux... done, booting the kernel.
21
console: Booting Linux on physical CPU 0x0
22
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
23
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
24
console: CPU: div instructions available: patching division code
25
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
26
console: OF: fdt: Machine model: Xunlong Orange Pi PC
27
console: Memory policy: Data cache writealloc
28
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
29
console: cma: Failed to reserve 128 MiB
30
console: psci: probing for conduit method from DT.
31
console: psci: PSCIv0.2 detected in firmware.
32
console: psci: Using standard PSCI v0.2 function IDs
33
console: psci: Trusted OS migration not required
34
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
35
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
36
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
37
console: Kernel command line: printk.time=0 console=ttyS0,115200
38
PASS (8.59 s)
39
JOB TIME : 8.81 s
40
41
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
42
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
43
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
44
Tested-by: Alex Bennée <alex.bennee@linaro.org>
45
Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com
46
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
49
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
50
1 file changed, 25 insertions(+)
51
52
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tests/acceptance/boot_linux_console.py
55
+++ b/tests/acceptance/boot_linux_console.py
56
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
57
exec_command_and_wait_for_pattern(self, 'reboot',
58
'reboot: Restarting system')
59
60
+ def test_arm_orangepi(self):
61
+ """
62
+ :avocado: tags=arch:arm
63
+ :avocado: tags=machine:orangepi-pc
64
+ """
65
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
66
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
67
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
68
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
69
+ kernel_path = self.extract_from_deb(deb_path,
70
+ '/boot/vmlinuz-4.20.7-sunxi')
71
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
72
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
73
+
74
+ self.vm.set_console()
75
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
76
+ 'console=ttyS0,115200n8 '
77
+ 'earlycon=uart,mmio32,0x1c28000')
78
+ self.vm.add_args('-kernel', kernel_path,
79
+ '-dtb', dtb_path,
80
+ '-append', kernel_command_line)
81
+ self.vm.launch()
82
+ console_pattern = 'Kernel command line: %s' % kernel_command_line
83
+ self.wait_for_console_pattern(console_pattern)
84
+
85
def test_s390x_s390_ccw_virtio(self):
86
"""
87
:avocado: tags=arch:s390x
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The kernel image and DeviceTree blob are built by the Armbian
4
project (based on Debian):
5
https://www.armbian.com/orange-pi-pc/
6
7
The SD image is from the kernelci.org project:
8
https://kernelci.org/faq/#the-code
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
16
console: Uncompressing Linux... done, booting the kernel.
17
console: Booting Linux on physical CPU 0x0
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
19
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
20
[...]
21
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
22
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
23
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
24
console: ledtrig-cpu: registered to indicate activity on CPUs
25
console: hidraw: raw HID events driver (C) Jiri Kosina
26
console: usbcore: registered new interface driver usbhid
27
console: usbhid: USB HID core driver
28
console: Initializing XFRM netlink socket
29
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
30
console: NET: Registered protocol family 10
31
console: mmc0: host does not support reading read-only switch, assuming write-enable
32
console: mmc0: Problem switching card into high-speed mode!
33
console: mmc0: new SD card at address 4567
34
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
35
[...]
36
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
37
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
38
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
39
console: Run /sbin/init as init process
40
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
41
console: Starting syslogd: OK
42
console: Starting klogd: OK
43
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
44
console: /bin/sh: can't access tty; job control turned off
45
console: cat /proc/partitions
46
console: / # cat /proc/partitions
47
console: major minor #blocks name
48
console: 1 0 4096 ram0
49
console: 1 1 4096 ram1
50
console: 1 2 4096 ram2
51
console: 1 3 4096 ram3
52
console: 179 0 61440 mmcblk0
53
console: reboot
54
console: / # reboot
55
console: umount: devtmpfs busy - remounted read-only
56
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
57
console: The system is going down NOW!
58
console: Sent SIGTERM to all processes
59
console: Sent SIGKILL to all processes
60
console: Requesting system reboot
61
console: reboot: Restarting system
62
JOB TIME : 68.64 s
63
64
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
65
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
66
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
67
Tested-by: Alex Bennée <alex.bennee@linaro.org>
68
Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com
69
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
70
[NL: extend test with ethernet device checks]
71
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
72
---
73
tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++
74
1 file changed, 47 insertions(+)
75
76
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
77
index XXXXXXX..XXXXXXX 100644
78
--- a/tests/acceptance/boot_linux_console.py
79
+++ b/tests/acceptance/boot_linux_console.py
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
81
exec_command_and_wait_for_pattern(self, 'reboot',
82
'reboot: Restarting system')
83
84
+ def test_arm_orangepi_sd(self):
85
+ """
86
+ :avocado: tags=arch:arm
87
+ :avocado: tags=machine:orangepi-pc
88
+ """
89
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
90
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
91
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
92
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
93
+ kernel_path = self.extract_from_deb(deb_path,
94
+ '/boot/vmlinuz-4.20.7-sunxi')
95
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
96
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
97
+ rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
98
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
99
+ rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061'
100
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
101
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
102
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
103
+
104
+ self.vm.set_console()
105
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
106
+ 'console=ttyS0,115200 '
107
+ 'root=/dev/mmcblk0 rootwait rw '
108
+ 'panic=-1 noreboot')
109
+ self.vm.add_args('-kernel', kernel_path,
110
+ '-dtb', dtb_path,
111
+ '-drive', 'file=' + rootfs_path + ',if=sd,format=raw',
112
+ '-append', kernel_command_line,
113
+ '-no-reboot')
114
+ self.vm.launch()
115
+ shell_ready = "/bin/sh: can't access tty; job control turned off"
116
+ self.wait_for_console_pattern(shell_ready)
117
+
118
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
119
+ 'Allwinner sun8i Family')
120
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
121
+ 'mmcblk0')
122
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
123
+ 'eth0: Link is Up')
124
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
125
+ 'udhcpc: lease of 10.0.2.15 obtained')
126
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
127
+ '3 packets transmitted, 3 packets received, 0% packet loss')
128
+ exec_command_and_wait_for_pattern(self, 'reboot',
129
+ 'reboot: Restarting system')
130
+
131
def test_s390x_s390_ccw_virtio(self):
132
"""
133
:avocado: tags=arch:s390x
134
--
135
2.20.1
136
137
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots Ubuntu Bionic on a OrangePi PC board.
4
5
As it requires 1GB of storage, and is slow, this test is disabled
6
on automatic CI testing.
7
8
It is useful for workstation testing. Currently Avocado timeouts too
9
quickly, so we can't run userland commands.
10
11
The kernel image and DeviceTree blob are built by the Armbian
12
project (based on Debian):
13
https://www.armbian.com/orange-pi-pc/
14
15
The Ubuntu image is downloaded from:
16
https://dl.armbian.com/orangepipc/Bionic_current
17
18
This test can be run using:
19
20
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
21
avocado --show=app,console run -t machine:orangepi-pc \
22
tests/acceptance/boot_linux_console.py
23
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
24
console: DRAM: 1024 MiB
25
console: Failed to set core voltage! Can't set CPU frequency
26
console: Trying to boot from MMC1
27
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
28
console: CPU: Allwinner H3 (SUN8I 0000)
29
console: Model: Xunlong Orange Pi PC
30
console: DRAM: 1 GiB
31
console: MMC: mmc@1c0f000: 0
32
[...]
33
console: Uncompressing Linux... done, booting the kernel.
34
console: Booting Linux on physical CPU 0x0
35
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
36
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
37
console: CPU: div instructions available: patching division code
38
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
39
console: OF: fdt: Machine model: Xunlong Orange Pi PC
40
[...]
41
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
42
console: done.
43
console: Begin: Running /scripts/local-bottom ... done.
44
console: Begin: Running /scripts/init-bottom ... done.
45
console: systemd[1]: systemd 237 running in system mode. (...)
46
console: systemd[1]: Detected architecture arm.
47
console: Welcome to Ubuntu 18.04.3 LTS!
48
console: systemd[1]: Set hostname to <orangepipc>.
49
50
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
51
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
52
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
53
Tested-by: Alex Bennée <alex.bennee@linaro.org>
54
Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com
55
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
56
[NL: changed test to boot from SD card via BootROM, added check for 7z]
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
58
---
59
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
60
1 file changed, 48 insertions(+)
61
62
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tests/acceptance/boot_linux_console.py
65
+++ b/tests/acceptance/boot_linux_console.py
66
@@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern
67
from avocado_qemu import wait_for_console_pattern
68
from avocado.utils import process
69
from avocado.utils import archive
70
+from avocado.utils.path import find_command, CmdNotFoundError
71
72
+P7ZIP_AVAILABLE = True
73
+try:
74
+ find_command('7z')
75
+except CmdNotFoundError:
76
+ P7ZIP_AVAILABLE = False
77
78
class BootLinuxConsole(Test):
79
"""
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
81
exec_command_and_wait_for_pattern(self, 'reboot',
82
'reboot: Restarting system')
83
84
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
85
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
86
+ def test_arm_orangepi_bionic(self):
87
+ """
88
+ :avocado: tags=arch:arm
89
+ :avocado: tags=machine:orangepi-pc
90
+ """
91
+
92
+ # This test download a 196MB compressed image and expand it to 932MB...
93
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
94
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
95
+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
96
+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
97
+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
98
+ image_path = os.path.join(self.workdir, image_name)
99
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
100
+
101
+ self.vm.set_console()
102
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
103
+ '-nic', 'user',
104
+ '-no-reboot')
105
+ self.vm.launch()
106
+
107
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
108
+ 'console=ttyS0,115200 '
109
+ 'loglevel=7 '
110
+ 'nosmp '
111
+ 'systemd.default_timeout_start_sec=9000 '
112
+ 'systemd.mask=armbian-zram-config.service '
113
+ 'systemd.mask=armbian-ramlog.service')
114
+
115
+ self.wait_for_console_pattern('U-Boot SPL')
116
+ self.wait_for_console_pattern('Autoboot in ')
117
+ exec_command_and_wait_for_pattern(self, ' ', '=>')
118
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
119
+ kernel_command_line + "'", '=>')
120
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
121
+
122
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
123
+ 'to <orangepipc>')
124
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
125
+
126
def test_s390x_s390_ccw_virtio(self):
127
"""
128
:avocado: tags=arch:s390x
129
--
130
2.20.1
131
132
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots U-Boot then NetBSD (stored on a SD card) on
4
a OrangePi PC board.
5
6
As it requires ~1.3GB of storage, it is disabled by default.
7
8
U-Boot is built by the Debian project [1], and the SD card image
9
is provided by the NetBSD organization [2].
10
11
Once the compressed SD card image is downloaded (304MB) and
12
extracted, this test is fast:
13
14
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
15
avocado --show=app,console run -t machine:orangepi-pc \
16
tests/acceptance/boot_linux_console.py
17
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
18
console: DRAM: 1024 MiB
19
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
20
console: CPU: Allwinner H3 (SUN8I 0000)
21
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
22
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
23
console: scanning usb for storage devices... 0 Storage Device(s) found
24
console: Hit any key to stop autoboot: 0
25
console: => setenv bootargs root=ld0a
26
console: => setenv kernel netbsd-GENERIC.ub
27
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
28
console: => boot
29
console: ## Booting kernel from Legacy Image at 42000000 ...
30
console: Image Name: NetBSD/earmv7hf 9.0_RC1
31
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
32
console: XIP Kernel Image (no loading done)
33
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
34
console: Starting kernel ...
35
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
36
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
37
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
38
console: [ 1.0000000] total memory = 1024 MB
39
console: [ 1.0000000] avail memory = 1003 MB
40
console: [ 1.0000000] armfdt0 (root)
41
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
42
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
43
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
44
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
45
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
46
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
47
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
48
...
49
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
50
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
51
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors
52
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
53
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log.
54
console: [ 3.1179868] boot device: ld0
55
console: [ 3.1470623] root on ld0a dumps on ld0b
56
console: [ 3.2464436] root file system type: ffs
57
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
58
console: Mon Feb 17 20:33:35 UTC 2020
59
console: Starting root file system check:
60
PASS (35.96 s)
61
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
62
JOB TIME : 36.09 s
63
64
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
65
66
This test is based on a description from Niek Linnenbank from [4].
67
68
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
69
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
70
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
71
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
72
73
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
74
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
75
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
76
Tested-by: Alex Bennée <alex.bennee@linaro.org>
77
Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com
78
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
---
81
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
82
1 file changed, 70 insertions(+)
83
84
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
85
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/acceptance/boot_linux_console.py
87
+++ b/tests/acceptance/boot_linux_console.py
88
@@ -XXX,XX +XXX,XX @@ import shutil
89
from avocado import skipUnless
90
from avocado_qemu import Test
91
from avocado_qemu import exec_command_and_wait_for_pattern
92
+from avocado_qemu import interrupt_interactive_console_until_pattern
93
from avocado_qemu import wait_for_console_pattern
94
from avocado.utils import process
95
from avocado.utils import archive
96
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
97
'to <orangepipc>')
98
self.wait_for_console_pattern('Starting Load Kernel Modules...')
99
100
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
101
+ def test_arm_orangepi_uboot_netbsd9(self):
102
+ """
103
+ :avocado: tags=arch:arm
104
+ :avocado: tags=machine:orangepi-pc
105
+ """
106
+ # This test download a 304MB compressed image and expand it to 1.3GB...
107
+ deb_url = ('http://snapshot.debian.org/archive/debian/'
108
+ '20200108T145233Z/pool/main/u/u-boot/'
109
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
110
+ deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99'
111
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
112
+ # We use the common OrangePi PC 'plus' build of U-Boot for our secondary
113
+ # program loader (SPL). We will then set the path to the more specific
114
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt,
115
+ # before to boot NetBSD.
116
+ uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin'
117
+ uboot_path = self.extract_from_deb(deb_path, uboot_path)
118
+ image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
119
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
120
+ image_hash = '2babb29d36d8360adcb39c09e31060945259917a'
121
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
122
+ image_path = os.path.join(self.workdir, 'armv7.img')
123
+ image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path
124
+ archive.gzip_uncompress(image_path_gz, image_path)
125
+
126
+ # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc
127
+ with open(uboot_path, 'rb') as f_in:
128
+ with open(image_path, 'r+b') as f_out:
129
+ f_out.seek(8 * 1024)
130
+ shutil.copyfileobj(f_in, f_out)
131
+
132
+ # Extend image, to avoid that NetBSD thinks the partition
133
+ # inside the image is larger than device size itself
134
+ f_out.seek(0, 2)
135
+ f_out.seek(64 * 1024 * 1024, 1)
136
+ f_out.write(bytearray([0x00]))
137
+
138
+ self.vm.set_console()
139
+ self.vm.add_args('-nic', 'user',
140
+ '-drive', image_drive_args,
141
+ '-global', 'allwinner-rtc.base-year=2000',
142
+ '-no-reboot')
143
+ self.vm.launch()
144
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
145
+ interrupt_interactive_console_until_pattern(self,
146
+ 'Hit any key to stop autoboot:',
147
+ 'switch to partitions #0, OK')
148
+
149
+ exec_command_and_wait_for_pattern(self, '', '=>')
150
+ cmd = 'setenv bootargs root=ld0a'
151
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
152
+ cmd = 'setenv kernel netbsd-GENERIC.ub'
153
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
154
+ cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
155
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
156
+ cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; "
157
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
158
+ "fdt addr ${fdt_addr_r}; "
159
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
160
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
161
+
162
+ exec_command_and_wait_for_pattern(self, 'boot',
163
+ 'Booting kernel from Legacy Image')
164
+ wait_for_console_pattern(self, 'Starting kernel ...')
165
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
166
+ # Wait for user-space
167
+ wait_for_console_pattern(self, 'Starting root file system check')
168
+
169
def test_s390x_s390_ccw_virtio(self):
170
"""
171
:avocado: tags=arch:s390x
172
--
173
2.20.1
174
175
diff view generated by jsdifflib
Deleted patch
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
2
1
3
The Xunlong Orange Pi PC machine is a functional ARM machine
4
based on the Allwinner H3 System-on-Chip. It supports mainline
5
Linux, U-Boot, NetBSD and is covered by acceptance tests.
6
7
This commit adds a documentation text file with a description
8
of the machine and instructions for the user.
9
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com
13
[PMM: moved file into docs/system/arm to match the reorg
14
of the arm target part of the docs; tweaked heading to
15
match other boards]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
MAINTAINERS | 1 +
19
docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++
20
docs/system/target-arm.rst | 2 +
21
3 files changed, 256 insertions(+)
22
create mode 100644 docs/system/arm/orangepi.rst
23
24
diff --git a/MAINTAINERS b/MAINTAINERS
25
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
27
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ S: Maintained
29
F: hw/*/allwinner-h3*
30
F: include/hw/*/allwinner-h3*
31
F: hw/arm/orangepi.c
32
+F: docs/system/orangepi.rst
33
34
ARM PrimeCell and CMSDK devices
35
M: Peter Maydell <peter.maydell@linaro.org>
36
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
37
new file mode 100644
38
index XXXXXXX..XXXXXXX
39
--- /dev/null
40
+++ b/docs/system/arm/orangepi.rst
41
@@ -XXX,XX +XXX,XX @@
42
+Orange Pi PC (``orangepi-pc``)
43
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
44
+
45
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
46
+based embedded computer with mainline support in both U-Boot
47
+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
48
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
49
+various other I/O.
50
+
51
+Supported devices
52
+"""""""""""""""""
53
+
54
+The Orange Pi PC machine supports the following devices:
55
+
56
+ * SMP (Quad Core Cortex-A7)
57
+ * Generic Interrupt Controller configuration
58
+ * SRAM mappings
59
+ * SDRAM controller
60
+ * Real Time Clock
61
+ * Timer device (re-used from Allwinner A10)
62
+ * UART
63
+ * SD/MMC storage controller
64
+ * EMAC ethernet
65
+ * USB 2.0 interfaces
66
+ * Clock Control Unit
67
+ * System Control module
68
+ * Security Identifier device
69
+
70
+Limitations
71
+"""""""""""
72
+
73
+Currently, Orange Pi PC does *not* support the following features:
74
+
75
+- Graphical output via HDMI, GPU and/or the Display Engine
76
+- Audio output
77
+- Hardware Watchdog
78
+
79
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
80
+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``
81
+
82
+Boot options
83
+""""""""""""
84
+
85
+The Orange Pi PC machine can start using the standard -kernel functionality
86
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC
87
+machine can also emulate the BootROM which is present on an actual Allwinner H3
88
+based SoC, which loads the bootloader from a SD card, specified via the -sd argument
89
+to qemu-system-arm.
90
+
91
+Machine-specific options
92
+""""""""""""""""""""""""
93
+
94
+The following machine-specific options are supported:
95
+
96
+- allwinner-rtc.base-year=YYYY
97
+
98
+ The Allwinner RTC device is automatically created by the Orange Pi PC machine
99
+ and uses a default base year value which can be overridden using the 'base-year' property.
100
+ The base year is the actual represented year when the RTC year value is zero.
101
+ This option can be used in case the target operating system driver uses a different
102
+ base year value. The minimum value for the base year is 1900.
103
+
104
+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff
105
+
106
+ The Security Identifier value can be read by the guest.
107
+ For example, U-Boot uses it to determine a unique MAC address.
108
+
109
+The above machine-specific options can be specified in qemu-system-arm
110
+via the '-global' argument, for example:
111
+
112
+.. code-block:: bash
113
+
114
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
115
+ -global allwinner-rtc.base-year=2000
116
+
117
+Running mainline Linux
118
+""""""""""""""""""""""
119
+
120
+Mainline Linux kernels from 4.19 up to latest master are known to work.
121
+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,
122
+simply configure the kernel using the sunxi_defconfig configuration:
123
+
124
+.. code-block:: bash
125
+
126
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper
127
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig
128
+
129
+To be able to use USB storage, you need to manually enable the corresponding
130
+configuration item. Start the kconfig configuration tool:
131
+
132
+.. code-block:: bash
133
+
134
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig
135
+
136
+Navigate to the following item, enable it and save your configuration:
137
+
138
+ Device Drivers > USB support > USB Mass Storage support
139
+
140
+Build the Linux kernel with:
141
+
142
+.. code-block:: bash
143
+
144
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make
145
+
146
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:
147
+
148
+.. code-block:: bash
149
+
150
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
151
+ -kernel /path/to/linux/arch/arm/boot/zImage \
152
+ -append 'console=ttyS0,115200' \
153
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
154
+
155
+Orange Pi PC images
156
+"""""""""""""""""""
157
+
158
+Note that the mainline kernel does not have a root filesystem. You may provide it
159
+with an official Orange Pi PC image from the official website:
160
+
161
+ http://www.orangepi.org/downloadresources/
162
+
163
+Another possibility is to run an Armbian image for Orange Pi PC which
164
+can be downloaded from:
165
+
166
+ https://www.armbian.com/orange-pi-pc/
167
+
168
+Alternatively, you can also choose to build you own image with buildroot
169
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.
170
+
171
+You can choose to attach the selected image either as an SD card or as USB mass storage.
172
+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd
173
+argument and provide the proper root= kernel parameter:
174
+
175
+.. code-block:: bash
176
+
177
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
178
+ -kernel /path/to/linux/arch/arm/boot/zImage \
179
+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \
180
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
181
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
182
+
183
+To attach the image as an USB mass storage device to the machine,
184
+simply append to the command:
185
+
186
+.. code-block:: bash
187
+
188
+ -drive if=none,id=stick,file=myimage.img \
189
+ -device usb-storage,bus=usb-bus.0,drive=stick
190
+
191
+Instead of providing a custom Linux kernel via the -kernel command you may also
192
+choose to let the Orange Pi PC machine load the bootloader from SD card, just like
193
+a real board would do using the BootROM. Simply pass the selected image via the -sd
194
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
195
+
196
+.. code-block:: bash
197
+
198
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
199
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
200
+
201
+Note that both the official Orange Pi PC images and Armbian images start
202
+a lot of userland programs via systemd. Depending on the host hardware and OS,
203
+they may be slow to emulate, especially due to emulating the 4 cores.
204
+To help reduce the performance slow down due to emulating the 4 cores, you can
205
+give the following kernel parameters via U-Boot (or via -append):
206
+
207
+.. code-block:: bash
208
+
209
+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'
210
+
211
+Running U-Boot
212
+""""""""""""""
213
+
214
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
215
+using similar commands as describe above for Linux. Note that it is recommended
216
+for development/testing to select the following configuration setting in U-Boot:
217
+
218
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
219
+
220
+To start U-Boot using the Orange Pi PC machine, provide the
221
+u-boot binary to the -kernel argument:
222
+
223
+.. code-block:: bash
224
+
225
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
226
+ -kernel /path/to/uboot/u-boot -sd disk.img
227
+
228
+Use the following U-boot commands to load and boot a Linux kernel from SD card:
229
+
230
+.. code-block:: bash
231
+
232
+ => setenv bootargs console=ttyS0,115200
233
+ => ext2load mmc 0 0x42000000 zImage
234
+ => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
235
+ => bootz 0x42000000 - 0x43000000
236
+
237
+Running NetBSD
238
+""""""""""""""
239
+
240
+The NetBSD operating system also includes support for Allwinner H3 based boards,
241
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC
242
+board and provides a fully working system with serial console, networking and storage.
243
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
244
+
245
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz
246
+
247
+The image requires manually installing U-Boot in the image. Build U-Boot with
248
+the orangepi_pc_defconfig configuration as described in the previous section.
249
+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:
250
+
251
+.. code-block:: bash
252
+
253
+ $ gunzip armv7.img.gz
254
+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc
255
+
256
+Finally, before starting the machine the SD image must be extended such
257
+that the NetBSD kernel will not conclude the NetBSD partition is larger than
258
+the emulated SD card:
259
+
260
+.. code-block:: bash
261
+
262
+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img
263
+
264
+Start the machine using the following command:
265
+
266
+.. code-block:: bash
267
+
268
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
269
+ -sd armv7.img -global allwinner-rtc.base-year=2000
270
+
271
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
272
+and set the following environment variables before booting:
273
+
274
+.. code-block:: bash
275
+
276
+ => setenv bootargs root=ld0a
277
+ => setenv kernel netbsd-GENERIC.ub
278
+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
279
+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'
280
+
281
+Optionally you may save the environment variables to SD card with 'saveenv'.
282
+To continue booting simply give the 'boot' command and NetBSD boots.
283
+
284
+Orange Pi PC acceptance tests
285
+"""""""""""""""""""""""""""""
286
+
287
+The Orange Pi PC machine has several acceptance tests included.
288
+To run the whole set of tests, build QEMU from source and simply
289
+provide the following command:
290
+
291
+.. code-block:: bash
292
+
293
+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \
294
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
295
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
296
index XXXXXXX..XXXXXXX 100644
297
--- a/docs/system/target-arm.rst
298
+++ b/docs/system/target-arm.rst
299
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
300
``qemu-system-aarch64 --machine help``.
301
302
.. toctree::
303
+ :maxdepth: 1
304
305
arm/integratorcp
306
arm/versatile
307
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
308
arm/stellaris
309
arm/musicpal
310
arm/sx1
311
+ arm/orangepi
312
313
Arm CPU features
314
================
315
--
316
2.20.1
317
318
diff view generated by jsdifflib
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
Convert kvm_arm_vgic_probe() so that it returns a
4
bitmap of supported in-kernel emulation VGIC versions instead
5
of the max version: at the moment values can be v2 and v3.
6
This allows to expose the case where the host GICv3 also
7
supports GICv2 emulation. This will be useful to choose the
8
default version in KVM accelerated mode.
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20200311131618.7187-5-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/kvm_arm.h | 3 +++
17
hw/arm/virt.c | 11 +++++++++--
18
target/arm/kvm.c | 14 ++++++++------
19
3 files changed, 20 insertions(+), 8 deletions(-)
20
21
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/kvm_arm.h
24
+++ b/target/arm/kvm_arm.h
25
@@ -XXX,XX +XXX,XX @@
26
#include "exec/memory.h"
27
#include "qemu/error-report.h"
28
29
+#define KVM_ARM_VGIC_V2 (1 << 0)
30
+#define KVM_ARM_VGIC_V3 (1 << 1)
31
+
32
/**
33
* kvm_arm_vcpu_init:
34
* @cs: CPUState
35
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/virt.c
38
+++ b/hw/arm/virt.c
39
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
40
vms->gic_version = VIRT_GIC_VERSION_3;
41
}
42
} else {
43
- vms->gic_version = kvm_arm_vgic_probe();
44
- if (!vms->gic_version) {
45
+ int probe_bitmap = kvm_arm_vgic_probe();
46
+
47
+ if (!probe_bitmap) {
48
error_report(
49
"Unable to determine GIC version supported by host");
50
exit(1);
51
+ } else {
52
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
53
+ vms->gic_version = VIRT_GIC_VERSION_3;
54
+ } else {
55
+ vms->gic_version = VIRT_GIC_VERSION_2;
56
+ }
57
}
58
}
59
} else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
60
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/kvm.c
63
+++ b/target/arm/kvm.c
64
@@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s)
65
66
int kvm_arm_vgic_probe(void)
67
{
68
+ int val = 0;
69
+
70
if (kvm_create_device(kvm_state,
71
KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
72
- return 3;
73
- } else if (kvm_create_device(kvm_state,
74
- KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
75
- return 2;
76
- } else {
77
- return 0;
78
+ val |= KVM_ARM_VGIC_V3;
79
}
80
+ if (kvm_create_device(kvm_state,
81
+ KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
82
+ val |= KVM_ARM_VGIC_V2;
83
+ }
84
+ return val;
85
}
86
87
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level)
88
--
89
2.20.1
90
91
diff view generated by jsdifflib