1
arm queue; dunno if this will be the last before softfreeze
1
The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89:
2
or not, but anyway probably the last large one. New orangepi-pc
3
board model is the big item here.
4
2
5
thanks
3
Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100)
6
-- PMM
7
8
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
9
10
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020
15
8
16
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
9
for you to fetch changes up to 6358890cb939192f6169fdf7664d903bf9b1d338:
17
10
18
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
11
tests/tcg/aarch64: Add bti smoke tests (2020-10-20 16:12:02 +0100)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
target-arm queue:
14
target-arm queue:
22
* Fix various bugs that might result in an assert() due to
15
* Fix AArch32 SMLAD incorrect setting of Q bit
23
incorrect hflags for M-profile CPUs
16
* AArch32 VCVT fixed-point to float is always round-to-nearest
24
* Fix Aspeed SMC Controller user-mode select handling
17
* strongarm: Fix 'time to transmit a char' unit comment
25
* Report correct (with-tag) address in fault address register
18
* Restrict APEI tables generation to the 'virt' machine
26
when TBI is enabled
19
* bcm2835: minor code cleanups
27
* cubieboard: make sure SOC object isn't leaked
20
* correctly flush TLBs when TBI is enabled
28
* fsl-imx25: Wire up eSDHC controllers
21
* tests/qtest: Add npcm7xx timer test
29
* fsl-imx25: Wire up USB controllers
22
* loads-stores.rst: add footnote that clarifies GETPC usage
30
* New board model: orangepi-pc (OrangePi PC)
23
* Fix reported EL for mte_check_fail
31
* ARM/KVM: if user doesn't select GIC version and the
24
* Ignore HCR_EL2.ATA when {E2H,TGE} != 11
32
host kernel can only provide GICv3, use that, rather
25
* microbit_i2c: Fix coredump when dump-vmstate
33
than defaulting to "fail because GICv2 isn't possible"
26
* nseries: Fix loading kernel image on n8x0 machines
34
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
27
* Implement v8.1M low-overhead-loops
28
* linux-user: Support AArch64 BTI
35
29
36
----------------------------------------------------------------
30
----------------------------------------------------------------
37
Beata Michalska (1):
31
Emanuele Giuseppe Esposito (1):
38
target/arm: kvm: Inject events at the last stage of sync
32
loads-stores.rst: add footnote that clarifies GETPC usage
39
33
40
Cédric Le Goater (2):
34
Havard Skinnemoen (1):
41
aspeed/smc: Add some tracing
35
tests/qtest: Add npcm7xx timer test
42
aspeed/smc: Fix User mode select/unselect scheme
43
36
44
Eric Auger (6):
37
Peng Liang (1):
45
hw/arm/virt: Document 'max' value in gic-version property description
38
microbit_i2c: Fix coredump when dump-vmstate
46
hw/arm/virt: Introduce VirtGICType enum type
47
hw/arm/virt: Introduce finalize_gic_version()
48
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
49
hw/arm/virt: kvm: Restructure finalize_gic_version()
50
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
51
39
52
Guenter Roeck (2):
40
Peter Maydell (12):
53
hw/arm/fsl-imx25: Wire up eSDHC controllers
41
target/arm: Fix SMLAD incorrect setting of Q bit
54
hw/arm/fsl-imx25: Wire up USB controllers
42
target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
43
decodetree: Fix codegen for non-overlapping group inside overlapping group
44
target/arm: Implement v8.1M NOCP handling
45
target/arm: Implement v8.1M conditional-select insns
46
target/arm: Make the t32 insn[25:23]=111 group non-overlapping
47
target/arm: Don't allow BLX imm for M-profile
48
target/arm: Implement v8.1M branch-future insns (as NOPs)
49
target/arm: Implement v8.1M low-overhead-loop instructions
50
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
51
target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
52
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
55
53
56
Igor Mammedov (1):
54
Philippe Mathieu-Daudé (10):
57
hw/arm/cubieboard: make sure SOC object isn't leaked
55
hw/arm/strongarm: Fix 'time to transmit a char' unit comment
56
hw/arm: Restrict APEI tables generation to the 'virt' machine
57
hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
58
hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
59
hw/timer/bcm2835: Support the timer COMPARE registers
60
hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
61
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
62
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
63
hw/arm/nseries: Fix loading kernel image on n8x0 machines
64
linux-user/elfload: Avoid leaking interp_name using GLib memory API
58
65
59
Niek Linnenbank (13):
66
Richard Henderson (16):
60
hw/arm: add Allwinner H3 System-on-Chip
67
accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
61
hw/arm: add Xunlong Orange Pi PC machine
68
target/arm: Use tlb_flush_page_bits_by_mmuidx*
62
hw/arm/allwinner-h3: add Clock Control Unit
69
target/arm: Remove redundant mmu_idx lookup
63
hw/arm/allwinner-h3: add USB host controller
70
target/arm: Fix reported EL for mte_check_fail
64
hw/arm/allwinner-h3: add System Control module
71
target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
65
hw/arm/allwinner: add CPU Configuration module
72
linux-user/aarch64: Reset btype for signals
66
hw/arm/allwinner: add Security Identifier device
73
linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
67
hw/arm/allwinner: add SD/MMC host controller
74
include/elf: Add defines related to GNU property notes for AArch64
68
hw/arm/allwinner-h3: add EMAC ethernet device
75
linux-user/elfload: Fix coding style in load_elf_image
69
hw/arm/allwinner-h3: add Boot ROM support
76
linux-user/elfload: Adjust iteration over phdr
70
hw/arm/allwinner-h3: add SDRAM controller device
77
linux-user/elfload: Move PT_INTERP detection to first loop
71
hw/arm/allwinner: add RTC device support
78
linux-user/elfload: Use Error for load_elf_image
72
docs: add Orange Pi PC document
79
linux-user/elfload: Use Error for load_elf_interp
80
linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes
81
linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND
82
tests/tcg/aarch64: Add bti smoke tests
73
83
74
Peter Maydell (4):
84
docs/devel/loads-stores.rst | 8 +-
75
hw/intc/armv7m_nvic: Rebuild hflags on reset
85
default-configs/devices/arm-softmmu.mak | 1 -
76
target/arm: Update hflags in trans_CPS_v7m()
86
include/elf.h | 22 ++
77
target/arm: Recalculate hflags correctly after writes to CONTROL
87
include/exec/cpu-all.h | 2 +
78
target/arm: Fix some comment typos
88
include/exec/exec-all.h | 36 ++
89
include/hw/timer/bcm2835_systmr.h | 17 +-
90
linux-user/qemu.h | 4 +
91
linux-user/syscall_defs.h | 4 +
92
target/arm/cpu.h | 13 +
93
target/arm/helper.h | 13 +
94
target/arm/internals.h | 9 +-
95
target/arm/m-nocp.decode | 10 +-
96
target/arm/t32.decode | 50 ++-
97
accel/tcg/cputlb.c | 275 +++++++++++++++-
98
hw/arm/bcm2835_peripherals.c | 13 +-
99
hw/arm/nseries.c | 1 +
100
hw/arm/strongarm.c | 2 +-
101
hw/i2c/microbit_i2c.c | 1 +
102
hw/intc/bcm2835_ic.c | 4 +-
103
hw/intc/bcm2836_control.c | 8 +-
104
hw/timer/bcm2835_systmr.c | 57 ++--
105
linux-user/aarch64/signal.c | 10 +-
106
linux-user/elfload.c | 326 ++++++++++++++----
107
linux-user/mmap.c | 16 +
108
target/arm/cpu.c | 38 ++-
109
target/arm/helper.c | 55 +++-
110
target/arm/mte_helper.c | 13 +-
111
target/arm/translate-a64.c | 6 +-
112
target/arm/translate.c | 239 +++++++++++++-
113
target/arm/vfp_helper.c | 76 +++--
114
tests/qtest/npcm7xx_timer-test.c | 562 ++++++++++++++++++++++++++++++++
115
tests/tcg/aarch64/bti-1.c | 62 ++++
116
tests/tcg/aarch64/bti-2.c | 108 ++++++
117
tests/tcg/aarch64/bti-crt.inc.c | 51 +++
118
hw/arm/Kconfig | 1 +
119
hw/intc/trace-events | 4 +
120
hw/timer/trace-events | 6 +-
121
scripts/decodetree.py | 2 +-
122
target/arm/translate-vfp.c.inc | 41 ++-
123
tests/qtest/meson.build | 1 +
124
tests/tcg/aarch64/Makefile.target | 10 +
125
tests/tcg/configure.sh | 4 +
126
42 files changed, 1973 insertions(+), 208 deletions(-)
127
create mode 100644 tests/qtest/npcm7xx_timer-test.c
128
create mode 100644 tests/tcg/aarch64/bti-1.c
129
create mode 100644 tests/tcg/aarch64/bti-2.c
130
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
79
131
80
Philippe Mathieu-Daudé (5):
81
tests/boot_linux_console: Add a quick test for the OrangePi PC board
82
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
83
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
84
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
85
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
86
87
Richard Henderson (2):
88
target/arm: Check addresses for disabled regimes
89
target/arm: Disable clean_data_tbi for system mode
90
91
Makefile.objs | 1 +
92
hw/arm/Makefile.objs | 1 +
93
hw/misc/Makefile.objs | 5 +
94
hw/net/Makefile.objs | 1 +
95
hw/rtc/Makefile.objs | 1 +
96
hw/sd/Makefile.objs | 1 +
97
hw/usb/hcd-ehci.h | 1 +
98
include/hw/arm/allwinner-a10.h | 4 +
99
include/hw/arm/allwinner-h3.h | 161 ++++++
100
include/hw/arm/fsl-imx25.h | 18 +
101
include/hw/arm/virt.h | 12 +-
102
include/hw/misc/allwinner-cpucfg.h | 52 ++
103
include/hw/misc/allwinner-h3-ccu.h | 66 +++
104
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
105
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
106
include/hw/misc/allwinner-sid.h | 60 +++
107
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
108
include/hw/rtc/allwinner-rtc.h | 134 +++++
109
include/hw/sd/allwinner-sdhost.h | 135 +++++
110
target/arm/helper.h | 1 +
111
target/arm/kvm_arm.h | 3 +
112
hw/arm/allwinner-a10.c | 19 +
113
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
114
hw/arm/cubieboard.c | 18 +
115
hw/arm/fsl-imx25.c | 56 +++
116
hw/arm/imx25_pdk.c | 16 +
117
hw/arm/orangepi.c | 130 +++++
118
hw/arm/virt.c | 145 ++++--
119
hw/intc/armv7m_nvic.c | 6 +
120
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
121
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
122
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
123
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
124
hw/misc/allwinner-sid.c | 168 +++++++
125
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
126
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
127
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
128
hw/ssi/aspeed_smc.c | 56 ++-
129
hw/usb/hcd-ehci-sysbus.c | 17 +
130
target/arm/helper.c | 49 +-
131
target/arm/kvm.c | 14 +-
132
target/arm/kvm32.c | 15 +-
133
target/arm/kvm64.c | 15 +-
134
target/arm/translate-a64.c | 11 +
135
target/arm/translate.c | 14 +-
136
MAINTAINERS | 9 +
137
default-configs/arm-softmmu.mak | 1 +
138
docs/system/arm/orangepi.rst | 253 ++++++++++
139
docs/system/target-arm.rst | 2 +
140
hw/arm/Kconfig | 12 +
141
hw/misc/trace-events | 19 +
142
hw/net/Kconfig | 3 +
143
hw/net/trace-events | 10 +
144
hw/rtc/trace-events | 4 +
145
hw/sd/trace-events | 7 +
146
hw/ssi/trace-events | 10 +
147
tests/acceptance/boot_linux_console.py | 230 +++++++++
148
57 files changed, 5787 insertions(+), 74 deletions(-)
149
create mode 100644 include/hw/arm/allwinner-h3.h
150
create mode 100644 include/hw/misc/allwinner-cpucfg.h
151
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
152
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
153
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
154
create mode 100644 include/hw/misc/allwinner-sid.h
155
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
156
create mode 100644 include/hw/rtc/allwinner-rtc.h
157
create mode 100644 include/hw/sd/allwinner-sdhost.h
158
create mode 100644 hw/arm/allwinner-h3.c
159
create mode 100644 hw/arm/orangepi.c
160
create mode 100644 hw/misc/allwinner-cpucfg.c
161
create mode 100644 hw/misc/allwinner-h3-ccu.c
162
create mode 100644 hw/misc/allwinner-h3-dramc.c
163
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
164
create mode 100644 hw/misc/allwinner-sid.c
165
create mode 100644 hw/net/allwinner-sun8i-emac.c
166
create mode 100644 hw/rtc/allwinner-rtc.c
167
create mode 100644 hw/sd/allwinner-sdhost.c
168
create mode 100644 docs/system/arm/orangepi.rst
169
create mode 100644 hw/ssi/trace-events
170
diff view generated by jsdifflib
1
Fix a couple of comment typos.
1
The SMLAD instruction is supposed to:
2
* signed multiply Rn[15:0] * Rm[15:0]
3
* signed multiply Rn[31:16] * Rm[31:16]
4
* perform a signed addition of the products and Ra
5
* set Rd to the low 32 bits of the theoretical
6
infinite-precision result
7
* set the Q flag if the sign-extension of Rd
8
would differ from the infinite-precision result
9
(ie on overflow)
10
11
Our current implementation doesn't quite do this, though: it performs
12
an addition of the products setting Q on overflow, and then it adds
13
Ra, again possibly setting Q. This sometimes incorrectly sets Q when
14
the architecturally mandated only-check-for-overflow-once algorithm
15
does not. For instance:
16
r1 = 0x80008000; r2 = 0x80008000; r3 = 0xffffffff
17
smlad r0, r1, r2, r3
18
This is (-32768 * -32768) + (-32768 * -32768) - 1
19
20
The products are both 0x4000_0000, so when added together as 32-bit
21
signed numbers they overflow (and QEMU sets Q), but because the
22
addition of Ra == -1 brings the total back down to 0x7fff_ffff
23
there is no overflow for the complete operation and setting Q is
24
incorrect.
25
26
Fix this edge case by resorting to 64-bit arithmetic for the
27
case where we need to add three values together.
2
28
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200303174950.3298-5-peter.maydell@linaro.org
31
Message-id: 20201009144712.11187-1-peter.maydell@linaro.org
6
---
32
---
7
target/arm/helper.c | 2 +-
33
target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++--------
8
target/arm/translate.c | 2 +-
34
1 file changed, 48 insertions(+), 10 deletions(-)
9
2 files changed, 2 insertions(+), 2 deletions(-)
10
35
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
16
17
/*
18
* If we have triggered a EL state change we can't rely on the
19
- * translator having passed it too us, we need to recompute.
20
+ * translator having passed it to us, we need to recompute.
21
*/
22
void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
23
{
24
diff --git a/target/arm/translate.c b/target/arm/translate.c
36
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate.c
38
--- a/target/arm/translate.c
27
+++ b/target/arm/translate.c
39
+++ b/target/arm/translate.c
28
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
40
@@ -XXX,XX +XXX,XX @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
29
41
gen_smul_dual(t1, t2);
30
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
42
31
/*
43
if (sub) {
32
- * A write to any coprocessor regiser that ends a TB
44
- /* This subtraction cannot overflow. */
33
+ * A write to any coprocessor register that ends a TB
45
+ /*
34
* must rebuild the hflags for the next TB.
46
+ * This subtraction cannot overflow, so we can do a simple
35
*/
47
+ * 32-bit subtraction and then a possible 32-bit saturating
36
TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
48
+ * addition of Ra.
49
+ */
50
tcg_gen_sub_i32(t1, t1, t2);
51
+ tcg_temp_free_i32(t2);
52
+
53
+ if (a->ra != 15) {
54
+ t2 = load_reg(s, a->ra);
55
+ gen_helper_add_setq(t1, cpu_env, t1, t2);
56
+ tcg_temp_free_i32(t2);
57
+ }
58
+ } else if (a->ra == 15) {
59
+ /* Single saturation-checking addition */
60
+ gen_helper_add_setq(t1, cpu_env, t1, t2);
61
+ tcg_temp_free_i32(t2);
62
} else {
63
/*
64
- * This addition cannot overflow 32 bits; however it may
65
- * overflow considered as a signed operation, in which case
66
- * we must set the Q flag.
67
+ * We need to add the products and Ra together and then
68
+ * determine whether the final result overflowed. Doing
69
+ * this as two separate add-and-check-overflow steps incorrectly
70
+ * sets Q for cases like (-32768 * -32768) + (-32768 * -32768) + -1.
71
+ * Do all the arithmetic at 64-bits and then check for overflow.
72
*/
73
- gen_helper_add_setq(t1, cpu_env, t1, t2);
74
- }
75
- tcg_temp_free_i32(t2);
76
+ TCGv_i64 p64, q64;
77
+ TCGv_i32 t3, qf, one;
78
79
- if (a->ra != 15) {
80
- t2 = load_reg(s, a->ra);
81
- gen_helper_add_setq(t1, cpu_env, t1, t2);
82
+ p64 = tcg_temp_new_i64();
83
+ q64 = tcg_temp_new_i64();
84
+ tcg_gen_ext_i32_i64(p64, t1);
85
+ tcg_gen_ext_i32_i64(q64, t2);
86
+ tcg_gen_add_i64(p64, p64, q64);
87
+ load_reg_var(s, t2, a->ra);
88
+ tcg_gen_ext_i32_i64(q64, t2);
89
+ tcg_gen_add_i64(p64, p64, q64);
90
+ tcg_temp_free_i64(q64);
91
+
92
+ tcg_gen_extr_i64_i32(t1, t2, p64);
93
+ tcg_temp_free_i64(p64);
94
+ /*
95
+ * t1 is the low half of the result which goes into Rd.
96
+ * We have overflow and must set Q if the high half (t2)
97
+ * is different from the sign-extension of t1.
98
+ */
99
+ t3 = tcg_temp_new_i32();
100
+ tcg_gen_sari_i32(t3, t1, 31);
101
+ qf = load_cpu_field(QF);
102
+ one = tcg_const_i32(1);
103
+ tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf);
104
+ store_cpu_field(qf, QF);
105
+ tcg_temp_free_i32(one);
106
+ tcg_temp_free_i32(t3);
107
tcg_temp_free_i32(t2);
108
}
109
store_reg(s, a->rd, t1);
37
--
110
--
38
2.20.1
111
2.20.1
39
112
40
113
diff view generated by jsdifflib
1
A write to the CONTROL register can change our current EL (by
1
For AArch32, unlike the VCVT of integer to float, which honours the
2
writing to the nPRIV bit). That means that we can't assume
2
rounding mode specified by the FPSCR, VCVT of fixed-point to float is
3
that s->current_el is still valid in trans_MSR_v7m() when
3
always round-to-nearest. (AArch64 fixed-point-to-float conversions
4
we try to rebuild the hflags.
4
always honour the FPCR rounding mode.)
5
5
6
Add a new helper rebuild_hflags_m32_newel() which, like the
6
Implement this by providing _round_to_nearest versions of the
7
existing rebuild_hflags_a32_newel(), recalculates the current
7
relevant helpers which set the rounding mode temporarily when making
8
EL from scratch, and use it in trans_MSR_v7m().
8
the call to the underlying softfloat function.
9
9
10
This fixes an assertion about an hflags mismatch when the
10
We only need to change the VFP VCVT instructions, because the
11
guest changes privilege by writing to CONTROL.
11
standard- FPSCR value used by the Neon VCVT is always set to
12
round-to-nearest, so we don't need to do the extra work of saving
13
and restoring the rounding mode.
12
14
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200303174950.3298-4-peter.maydell@linaro.org
17
Message-id: 20201013103532.13391-1-peter.maydell@linaro.org
16
---
18
---
17
target/arm/helper.h | 1 +
19
target/arm/helper.h | 13 +++++++++++++
18
target/arm/helper.c | 12 ++++++++++++
20
target/arm/vfp_helper.c | 23 ++++++++++++++++++++++-
19
target/arm/translate.c | 7 +++----
21
target/arm/translate-vfp.c.inc | 24 ++++++++++++------------
20
3 files changed, 16 insertions(+), 4 deletions(-)
22
3 files changed, 47 insertions(+), 13 deletions(-)
21
23
22
diff --git a/target/arm/helper.h b/target/arm/helper.h
24
diff --git a/target/arm/helper.h b/target/arm/helper.h
23
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.h
26
--- a/target/arm/helper.h
25
+++ b/target/arm/helper.h
27
+++ b/target/arm/helper.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
28
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
27
DEF_HELPER_2(get_user_reg, i32, env, i32)
29
DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
28
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
30
DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
29
31
30
+DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env)
32
+DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr)
31
DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
33
+DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr)
32
DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
34
+DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr)
33
DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
35
+DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr)
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
+DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr)
37
+DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr)
38
+DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr)
39
+DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr)
40
+DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr)
41
+DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr)
42
+DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr)
43
+DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr)
44
+
45
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
46
47
DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32)
48
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
35
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
50
--- a/target/arm/vfp_helper.c
37
+++ b/target/arm/helper.c
51
+++ b/target/arm/vfp_helper.c
38
@@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env)
52
@@ -XXX,XX +XXX,XX @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
39
env->hflags = rebuild_hflags_internal(env);
53
return float64_to_float32(x, &env->vfp.fp_status);
40
}
54
}
41
55
56
-/* VFP3 fixed point conversion. */
42
+/*
57
+/*
43
+ * If we have triggered a EL state change we can't rely on the
58
+ * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
44
+ * translator having passed it to us, we need to recompute.
59
+ * must always round-to-nearest; the AArch64 ones honour the FPSCR
60
+ * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
61
+ * round-to-nearest so either helper will work.) AArch32 float-to-fix
62
+ * must round-to-zero.
45
+ */
63
+ */
46
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
64
#define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
47
+{
65
ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
48
+ int el = arm_current_el(env);
66
void *fpstp) \
49
+ int fp_el = fp_exception_el(env, el);
67
{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
50
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
68
51
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
69
+#define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
52
+}
70
+ ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
71
+ uint32_t shift, \
72
+ void *fpstp) \
73
+ { \
74
+ ftype ret; \
75
+ float_status *fpst = fpstp; \
76
+ FloatRoundMode oldmode = fpst->float_rounding_mode; \
77
+ fpst->float_rounding_mode = float_round_nearest_even; \
78
+ ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
79
+ fpst->float_rounding_mode = oldmode; \
80
+ return ret; \
81
+ }
53
+
82
+
54
void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
83
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
55
{
84
uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
56
int fp_el = fp_exception_el(env, el);
85
void *fpst) \
57
diff --git a/target/arm/translate.c b/target/arm/translate.c
86
@@ -XXX,XX +XXX,XX @@ uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
87
88
#define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
89
VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
90
+VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
91
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
92
float_round_to_zero, _round_to_zero) \
93
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
94
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
58
index XXXXXXX..XXXXXXX 100644
95
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/translate.c
96
--- a/target/arm/translate-vfp.c.inc
60
+++ b/target/arm/translate.c
97
+++ b/target/arm/translate-vfp.c.inc
61
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
98
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
62
99
/* Switch on op:U:sx bits */
63
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
100
switch (a->opc) {
64
{
101
case 0:
65
- TCGv_i32 addr, reg, el;
102
- gen_helper_vfp_shtoh(vd, vd, shift, fpst);
66
+ TCGv_i32 addr, reg;
103
+ gen_helper_vfp_shtoh_round_to_nearest(vd, vd, shift, fpst);
67
104
break;
68
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
105
case 1:
69
return false;
106
- gen_helper_vfp_sltoh(vd, vd, shift, fpst);
70
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
107
+ gen_helper_vfp_sltoh_round_to_nearest(vd, vd, shift, fpst);
71
gen_helper_v7m_msr(cpu_env, addr, reg);
108
break;
72
tcg_temp_free_i32(addr);
109
case 2:
73
tcg_temp_free_i32(reg);
110
- gen_helper_vfp_uhtoh(vd, vd, shift, fpst);
74
- el = tcg_const_i32(s->current_el);
111
+ gen_helper_vfp_uhtoh_round_to_nearest(vd, vd, shift, fpst);
75
- gen_helper_rebuild_hflags_m32(cpu_env, el);
112
break;
76
- tcg_temp_free_i32(el);
113
case 3:
77
+ /* If we wrote to CONTROL, the EL might have changed */
114
- gen_helper_vfp_ultoh(vd, vd, shift, fpst);
78
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
115
+ gen_helper_vfp_ultoh_round_to_nearest(vd, vd, shift, fpst);
79
gen_lookup_tb(s);
116
break;
80
return true;
117
case 4:
81
}
118
gen_helper_vfp_toshh_round_to_zero(vd, vd, shift, fpst);
119
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
120
/* Switch on op:U:sx bits */
121
switch (a->opc) {
122
case 0:
123
- gen_helper_vfp_shtos(vd, vd, shift, fpst);
124
+ gen_helper_vfp_shtos_round_to_nearest(vd, vd, shift, fpst);
125
break;
126
case 1:
127
- gen_helper_vfp_sltos(vd, vd, shift, fpst);
128
+ gen_helper_vfp_sltos_round_to_nearest(vd, vd, shift, fpst);
129
break;
130
case 2:
131
- gen_helper_vfp_uhtos(vd, vd, shift, fpst);
132
+ gen_helper_vfp_uhtos_round_to_nearest(vd, vd, shift, fpst);
133
break;
134
case 3:
135
- gen_helper_vfp_ultos(vd, vd, shift, fpst);
136
+ gen_helper_vfp_ultos_round_to_nearest(vd, vd, shift, fpst);
137
break;
138
case 4:
139
gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst);
140
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
141
/* Switch on op:U:sx bits */
142
switch (a->opc) {
143
case 0:
144
- gen_helper_vfp_shtod(vd, vd, shift, fpst);
145
+ gen_helper_vfp_shtod_round_to_nearest(vd, vd, shift, fpst);
146
break;
147
case 1:
148
- gen_helper_vfp_sltod(vd, vd, shift, fpst);
149
+ gen_helper_vfp_sltod_round_to_nearest(vd, vd, shift, fpst);
150
break;
151
case 2:
152
- gen_helper_vfp_uhtod(vd, vd, shift, fpst);
153
+ gen_helper_vfp_uhtod_round_to_nearest(vd, vd, shift, fpst);
154
break;
155
case 3:
156
- gen_helper_vfp_ultod(vd, vd, shift, fpst);
157
+ gen_helper_vfp_ultod_round_to_nearest(vd, vd, shift, fpst);
158
break;
159
case 4:
160
gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst);
82
--
161
--
83
2.20.1
162
2.20.1
84
163
85
164
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots U-Boot then NetBSD (stored on a SD card) on
3
The time to transmit a char is expressed in nanoseconds, not in ticks.
4
a OrangePi PC board.
5
6
As it requires ~1.3GB of storage, it is disabled by default.
7
8
U-Boot is built by the Debian project [1], and the SD card image
9
is provided by the NetBSD organization [2].
10
11
Once the compressed SD card image is downloaded (304MB) and
12
extracted, this test is fast:
13
14
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
15
avocado --show=app,console run -t machine:orangepi-pc \
16
tests/acceptance/boot_linux_console.py
17
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
18
console: DRAM: 1024 MiB
19
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
20
console: CPU: Allwinner H3 (SUN8I 0000)
21
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
22
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
23
console: scanning usb for storage devices... 0 Storage Device(s) found
24
console: Hit any key to stop autoboot: 0
25
console: => setenv bootargs root=ld0a
26
console: => setenv kernel netbsd-GENERIC.ub
27
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
28
console: => boot
29
console: ## Booting kernel from Legacy Image at 42000000 ...
30
console: Image Name: NetBSD/earmv7hf 9.0_RC1
31
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
32
console: XIP Kernel Image (no loading done)
33
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
34
console: Starting kernel ...
35
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
36
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
37
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
38
console: [ 1.0000000] total memory = 1024 MB
39
console: [ 1.0000000] avail memory = 1003 MB
40
console: [ 1.0000000] armfdt0 (root)
41
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
42
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
43
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
44
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
45
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
46
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
47
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
48
...
49
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
50
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
51
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors
52
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
53
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log.
54
console: [ 3.1179868] boot device: ld0
55
console: [ 3.1470623] root on ld0a dumps on ld0b
56
console: [ 3.2464436] root file system type: ffs
57
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
58
console: Mon Feb 17 20:33:35 UTC 2020
59
console: Starting root file system check:
60
PASS (35.96 s)
61
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
62
JOB TIME : 36.09 s
63
64
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
65
66
This test is based on a description from Niek Linnenbank from [4].
67
68
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
69
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
70
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
71
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
72
4
73
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
74
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Message-id: 20201014213601.205222-1-f4bug@amsat.org
75
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
76
Tested-by: Alex Bennée <alex.bennee@linaro.org>
77
Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com
78
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
---
9
---
81
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
10
hw/arm/strongarm.c | 2 +-
82
1 file changed, 70 insertions(+)
11
1 file changed, 1 insertion(+), 1 deletion(-)
83
12
84
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
13
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
85
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/acceptance/boot_linux_console.py
15
--- a/hw/arm/strongarm.c
87
+++ b/tests/acceptance/boot_linux_console.py
16
+++ b/hw/arm/strongarm.c
88
@@ -XXX,XX +XXX,XX @@ import shutil
17
@@ -XXX,XX +XXX,XX @@ struct StrongARMUARTState {
89
from avocado import skipUnless
18
uint8_t rx_start;
90
from avocado_qemu import Test
19
uint8_t rx_len;
91
from avocado_qemu import exec_command_and_wait_for_pattern
20
92
+from avocado_qemu import interrupt_interactive_console_until_pattern
21
- uint64_t char_transmit_time; /* time to transmit a char in ticks*/
93
from avocado_qemu import wait_for_console_pattern
22
+ uint64_t char_transmit_time; /* time to transmit a char in nanoseconds */
94
from avocado.utils import process
23
bool wait_break_end;
95
from avocado.utils import archive
24
QEMUTimer *rx_timeout_timer;
96
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
25
QEMUTimer *tx_timer;
97
'to <orangepipc>')
98
self.wait_for_console_pattern('Starting Load Kernel Modules...')
99
100
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
101
+ def test_arm_orangepi_uboot_netbsd9(self):
102
+ """
103
+ :avocado: tags=arch:arm
104
+ :avocado: tags=machine:orangepi-pc
105
+ """
106
+ # This test download a 304MB compressed image and expand it to 1.3GB...
107
+ deb_url = ('http://snapshot.debian.org/archive/debian/'
108
+ '20200108T145233Z/pool/main/u/u-boot/'
109
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
110
+ deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99'
111
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
112
+ # We use the common OrangePi PC 'plus' build of U-Boot for our secondary
113
+ # program loader (SPL). We will then set the path to the more specific
114
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt,
115
+ # before to boot NetBSD.
116
+ uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin'
117
+ uboot_path = self.extract_from_deb(deb_path, uboot_path)
118
+ image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
119
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
120
+ image_hash = '2babb29d36d8360adcb39c09e31060945259917a'
121
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
122
+ image_path = os.path.join(self.workdir, 'armv7.img')
123
+ image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path
124
+ archive.gzip_uncompress(image_path_gz, image_path)
125
+
126
+ # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc
127
+ with open(uboot_path, 'rb') as f_in:
128
+ with open(image_path, 'r+b') as f_out:
129
+ f_out.seek(8 * 1024)
130
+ shutil.copyfileobj(f_in, f_out)
131
+
132
+ # Extend image, to avoid that NetBSD thinks the partition
133
+ # inside the image is larger than device size itself
134
+ f_out.seek(0, 2)
135
+ f_out.seek(64 * 1024 * 1024, 1)
136
+ f_out.write(bytearray([0x00]))
137
+
138
+ self.vm.set_console()
139
+ self.vm.add_args('-nic', 'user',
140
+ '-drive', image_drive_args,
141
+ '-global', 'allwinner-rtc.base-year=2000',
142
+ '-no-reboot')
143
+ self.vm.launch()
144
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
145
+ interrupt_interactive_console_until_pattern(self,
146
+ 'Hit any key to stop autoboot:',
147
+ 'switch to partitions #0, OK')
148
+
149
+ exec_command_and_wait_for_pattern(self, '', '=>')
150
+ cmd = 'setenv bootargs root=ld0a'
151
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
152
+ cmd = 'setenv kernel netbsd-GENERIC.ub'
153
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
154
+ cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
155
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
156
+ cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; "
157
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
158
+ "fdt addr ${fdt_addr_r}; "
159
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
160
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
161
+
162
+ exec_command_and_wait_for_pattern(self, 'boot',
163
+ 'Booting kernel from Legacy Image')
164
+ wait_for_console_pattern(self, 'Starting kernel ...')
165
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
166
+ # Wait for user-space
167
+ wait_for_console_pattern(self, 'Starting root file system check')
168
+
169
def test_s390x_s390_ccw_virtio(self):
170
"""
171
:avocado: tags=arch:s390x
172
--
26
--
173
2.20.1
27
2.20.1
174
28
175
29
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
3
While APEI is a generic ACPI feature (usable by X86 and ARM64), only
4
connections which provide software access using the Enhanced
4
the 'virt' machine uses it, by enabling the RAS Virtualization. See
5
Host Controller Interface (EHCI) and Open Host Controller
5
commit 2afa8c8519: "hw/arm/virt: Introduce a RAS machine option").
6
Interface (OHCI) interfaces. This commit adds support for
7
both interfaces in the Allwinner H3 System on Chip.
8
6
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
7
Restrict the APEI tables generation code to the single user: the virt
10
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
8
machine. If another machine wants to use it, it simply has to 'select
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
ACPI_APEI' in its Kconfig.
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
13
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Fixes: aa16508f1d ("ACPI: Build related register address fields via hardware error fw_cfg blob")
14
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
12
Acked-by: Michael S. Tsirkin <mst@redhat.com>
13
Reviewed-by: Dongjiu Geng <gengdongjiu@huawei.com>
14
Acked-by: Laszlo Ersek <lersek@redhat.com>
15
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Message-id: 20201008161414.2672569-1-philmd@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
19
---
17
hw/usb/hcd-ehci.h | 1 +
20
default-configs/devices/arm-softmmu.mak | 1 -
18
include/hw/arm/allwinner-h3.h | 8 +++++++
21
hw/arm/Kconfig | 1 +
19
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
22
2 files changed, 1 insertion(+), 1 deletion(-)
20
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
21
hw/arm/Kconfig | 2 ++
22
5 files changed, 72 insertions(+)
23
23
24
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
24
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
25
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/usb/hcd-ehci.h
26
--- a/default-configs/devices/arm-softmmu.mak
27
+++ b/hw/usb/hcd-ehci.h
27
+++ b/default-configs/devices/arm-softmmu.mak
28
@@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState {
28
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX7=y
29
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
29
CONFIG_FSL_IMX6UL=y
30
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
30
CONFIG_SEMIHOSTING=y
31
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
31
CONFIG_ALLWINNER_H3=y
32
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
32
-CONFIG_ACPI_APEI=y
33
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
34
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
35
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@ enum {
41
AW_H3_SRAM_A1,
42
AW_H3_SRAM_A2,
43
AW_H3_SRAM_C,
44
+ AW_H3_EHCI0,
45
+ AW_H3_OHCI0,
46
+ AW_H3_EHCI1,
47
+ AW_H3_OHCI1,
48
+ AW_H3_EHCI2,
49
+ AW_H3_OHCI2,
50
+ AW_H3_EHCI3,
51
+ AW_H3_OHCI3,
52
AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/allwinner-h3.c
58
+++ b/hw/arm/allwinner-h3.c
59
@@ -XXX,XX +XXX,XX @@
60
#include "hw/sysbus.h"
61
#include "hw/char/serial.h"
62
#include "hw/misc/unimp.h"
63
+#include "hw/usb/hcd-ehci.h"
64
#include "sysemu/sysemu.h"
65
#include "hw/arm/allwinner-h3.h"
66
67
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
68
[AW_H3_SRAM_A1] = 0x00000000,
69
[AW_H3_SRAM_A2] = 0x00044000,
70
[AW_H3_SRAM_C] = 0x00010000,
71
+ [AW_H3_EHCI0] = 0x01c1a000,
72
+ [AW_H3_OHCI0] = 0x01c1a400,
73
+ [AW_H3_EHCI1] = 0x01c1b000,
74
+ [AW_H3_OHCI1] = 0x01c1b400,
75
+ [AW_H3_EHCI2] = 0x01c1c000,
76
+ [AW_H3_OHCI2] = 0x01c1c400,
77
+ [AW_H3_EHCI3] = 0x01c1d000,
78
+ [AW_H3_OHCI3] = 0x01c1d400,
79
[AW_H3_CCU] = 0x01c20000,
80
[AW_H3_PIT] = 0x01c20c00,
81
[AW_H3_UART0] = 0x01c28000,
82
@@ -XXX,XX +XXX,XX @@ enum {
83
AW_H3_GIC_SPI_UART3 = 3,
84
AW_H3_GIC_SPI_TIMER0 = 18,
85
AW_H3_GIC_SPI_TIMER1 = 19,
86
+ AW_H3_GIC_SPI_EHCI0 = 72,
87
+ AW_H3_GIC_SPI_OHCI0 = 73,
88
+ AW_H3_GIC_SPI_EHCI1 = 74,
89
+ AW_H3_GIC_SPI_OHCI1 = 75,
90
+ AW_H3_GIC_SPI_EHCI2 = 76,
91
+ AW_H3_GIC_SPI_OHCI2 = 77,
92
+ AW_H3_GIC_SPI_EHCI3 = 78,
93
+ AW_H3_GIC_SPI_OHCI3 = 79,
94
};
95
96
/* Allwinner H3 general constants */
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
98
qdev_init_nofail(DEVICE(&s->ccu));
99
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
100
101
+ /* Universal Serial Bus */
102
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
103
+ qdev_get_gpio_in(DEVICE(&s->gic),
104
+ AW_H3_GIC_SPI_EHCI0));
105
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
106
+ qdev_get_gpio_in(DEVICE(&s->gic),
107
+ AW_H3_GIC_SPI_EHCI1));
108
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
109
+ qdev_get_gpio_in(DEVICE(&s->gic),
110
+ AW_H3_GIC_SPI_EHCI2));
111
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
112
+ qdev_get_gpio_in(DEVICE(&s->gic),
113
+ AW_H3_GIC_SPI_EHCI3));
114
+
115
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
116
+ qdev_get_gpio_in(DEVICE(&s->gic),
117
+ AW_H3_GIC_SPI_OHCI0));
118
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
119
+ qdev_get_gpio_in(DEVICE(&s->gic),
120
+ AW_H3_GIC_SPI_OHCI1));
121
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
122
+ qdev_get_gpio_in(DEVICE(&s->gic),
123
+ AW_H3_GIC_SPI_OHCI2));
124
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
125
+ qdev_get_gpio_in(DEVICE(&s->gic),
126
+ AW_H3_GIC_SPI_OHCI3));
127
+
128
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
129
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
130
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
131
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/usb/hcd-ehci-sysbus.c
134
+++ b/hw/usb/hcd-ehci-sysbus.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = {
136
.class_init = ehci_exynos4210_class_init,
137
};
138
139
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
140
+{
141
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
142
+ DeviceClass *dc = DEVICE_CLASS(oc);
143
+
144
+ sec->capsbase = 0x0;
145
+ sec->opregbase = 0x10;
146
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
147
+}
148
+
149
+static const TypeInfo ehci_aw_h3_type_info = {
150
+ .name = TYPE_AW_H3_EHCI,
151
+ .parent = TYPE_SYS_BUS_EHCI,
152
+ .class_init = ehci_aw_h3_class_init,
153
+};
154
+
155
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
156
{
157
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
158
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
159
type_register_static(&ehci_type_info);
160
type_register_static(&ehci_platform_type_info);
161
type_register_static(&ehci_exynos4210_type_info);
162
+ type_register_static(&ehci_aw_h3_type_info);
163
type_register_static(&ehci_tegra2_type_info);
164
type_register_static(&ehci_ppc4xx_type_info);
165
type_register_static(&ehci_fusbh200_type_info);
166
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
33
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
167
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/arm/Kconfig
35
--- a/hw/arm/Kconfig
169
+++ b/hw/arm/Kconfig
36
+++ b/hw/arm/Kconfig
170
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
37
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
171
select ARM_TIMER
38
select ACPI_MEMORY_HOTPLUG
172
select ARM_GIC
39
select ACPI_HW_REDUCED
173
select UNIMP
40
select ACPI_NVDIMM
174
+ select USB_OHCI
41
+ select ACPI_APEI
175
+ select USB_EHCI_SYSBUS
42
176
43
config CHEETAH
177
config RASPI
178
bool
44
bool
179
--
45
--
180
2.20.1
46
2.20.1
181
47
182
48
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots Ubuntu Bionic on a OrangePi PC board.
3
Use the BCM2835_SYSTIMER_COUNT definition instead of the
4
magic '4' value.
4
5
5
As it requires 1GB of storage, and is slow, this test is disabled
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
6
on automatic CI testing.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
8
It is useful for workstation testing. Currently Avocado timeouts too
9
quickly, so we can't run userland commands.
10
11
The kernel image and DeviceTree blob are built by the Armbian
12
project (based on Debian):
13
https://www.armbian.com/orange-pi-pc/
14
15
The Ubuntu image is downloaded from:
16
https://dl.armbian.com/orangepipc/Bionic_current
17
18
This test can be run using:
19
20
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
21
avocado --show=app,console run -t machine:orangepi-pc \
22
tests/acceptance/boot_linux_console.py
23
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
24
console: DRAM: 1024 MiB
25
console: Failed to set core voltage! Can't set CPU frequency
26
console: Trying to boot from MMC1
27
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
28
console: CPU: Allwinner H3 (SUN8I 0000)
29
console: Model: Xunlong Orange Pi PC
30
console: DRAM: 1 GiB
31
console: MMC: mmc@1c0f000: 0
32
[...]
33
console: Uncompressing Linux... done, booting the kernel.
34
console: Booting Linux on physical CPU 0x0
35
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
36
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
37
console: CPU: div instructions available: patching division code
38
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
39
console: OF: fdt: Machine model: Xunlong Orange Pi PC
40
[...]
41
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
42
console: done.
43
console: Begin: Running /scripts/local-bottom ... done.
44
console: Begin: Running /scripts/init-bottom ... done.
45
console: systemd[1]: systemd 237 running in system mode. (...)
46
console: systemd[1]: Detected architecture arm.
47
console: Welcome to Ubuntu 18.04.3 LTS!
48
console: systemd[1]: Set hostname to <orangepipc>.
49
50
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
51
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20201010203709.3116542-2-f4bug@amsat.org
52
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
53
Tested-by: Alex Bennée <alex.bennee@linaro.org>
54
Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com
55
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
56
[NL: changed test to boot from SD card via BootROM, added check for 7z]
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
58
---
11
---
59
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
12
include/hw/timer/bcm2835_systmr.h | 4 +++-
60
1 file changed, 48 insertions(+)
13
hw/timer/bcm2835_systmr.c | 3 ++-
14
2 files changed, 5 insertions(+), 2 deletions(-)
61
15
62
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
16
diff --git a/include/hw/timer/bcm2835_systmr.h b/include/hw/timer/bcm2835_systmr.h
63
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
64
--- a/tests/acceptance/boot_linux_console.py
18
--- a/include/hw/timer/bcm2835_systmr.h
65
+++ b/tests/acceptance/boot_linux_console.py
19
+++ b/include/hw/timer/bcm2835_systmr.h
66
@@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern
20
@@ -XXX,XX +XXX,XX @@
67
from avocado_qemu import wait_for_console_pattern
21
#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer"
68
from avocado.utils import process
22
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SystemTimerState, BCM2835_SYSTIMER)
69
from avocado.utils import archive
23
70
+from avocado.utils.path import find_command, CmdNotFoundError
24
+#define BCM2835_SYSTIMER_COUNT 4
71
72
+P7ZIP_AVAILABLE = True
73
+try:
74
+ find_command('7z')
75
+except CmdNotFoundError:
76
+ P7ZIP_AVAILABLE = False
77
78
class BootLinuxConsole(Test):
79
"""
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
81
exec_command_and_wait_for_pattern(self, 'reboot',
82
'reboot: Restarting system')
83
84
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
85
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
86
+ def test_arm_orangepi_bionic(self):
87
+ """
88
+ :avocado: tags=arch:arm
89
+ :avocado: tags=machine:orangepi-pc
90
+ """
91
+
25
+
92
+ # This test download a 196MB compressed image and expand it to 932MB...
26
struct BCM2835SystemTimerState {
93
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
27
/*< private >*/
94
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
28
SysBusDevice parent_obj;
95
+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
29
@@ -XXX,XX +XXX,XX @@ struct BCM2835SystemTimerState {
96
+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
30
97
+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
31
struct {
98
+ image_path = os.path.join(self.workdir, image_name)
32
uint32_t status;
99
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
33
- uint32_t compare[4];
100
+
34
+ uint32_t compare[BCM2835_SYSTIMER_COUNT];
101
+ self.vm.set_console()
35
} reg;
102
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
36
};
103
+ '-nic', 'user',
37
104
+ '-no-reboot')
38
diff --git a/hw/timer/bcm2835_systmr.c b/hw/timer/bcm2835_systmr.c
105
+ self.vm.launch()
39
index XXXXXXX..XXXXXXX 100644
106
+
40
--- a/hw/timer/bcm2835_systmr.c
107
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
41
+++ b/hw/timer/bcm2835_systmr.c
108
+ 'console=ttyS0,115200 '
42
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription bcm2835_systmr_vmstate = {
109
+ 'loglevel=7 '
43
.minimum_version_id = 1,
110
+ 'nosmp '
44
.fields = (VMStateField[]) {
111
+ 'systemd.default_timeout_start_sec=9000 '
45
VMSTATE_UINT32(reg.status, BCM2835SystemTimerState),
112
+ 'systemd.mask=armbian-zram-config.service '
46
- VMSTATE_UINT32_ARRAY(reg.compare, BCM2835SystemTimerState, 4),
113
+ 'systemd.mask=armbian-ramlog.service')
47
+ VMSTATE_UINT32_ARRAY(reg.compare, BCM2835SystemTimerState,
114
+
48
+ BCM2835_SYSTIMER_COUNT),
115
+ self.wait_for_console_pattern('U-Boot SPL')
49
VMSTATE_END_OF_LIST()
116
+ self.wait_for_console_pattern('Autoboot in ')
50
}
117
+ exec_command_and_wait_for_pattern(self, ' ', '=>')
51
};
118
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
119
+ kernel_command_line + "'", '=>')
120
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
121
+
122
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
123
+ 'to <orangepipc>')
124
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
125
+
126
def test_s390x_s390_ccw_virtio(self):
127
"""
128
:avocado: tags=arch:s390x
129
--
52
--
130
2.20.1
53
2.20.1
131
54
132
55
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The variable holding the CTRL_STATUS register is misnamed
4
'status'. Rename it 'ctrl_status' to make it more obvious
5
this register is also used to control the peripheral.
6
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20201010203709.3116542-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/timer/bcm2835_systmr.h | 2 +-
14
hw/timer/bcm2835_systmr.c | 8 ++++----
15
2 files changed, 5 insertions(+), 5 deletions(-)
16
17
diff --git a/include/hw/timer/bcm2835_systmr.h b/include/hw/timer/bcm2835_systmr.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/timer/bcm2835_systmr.h
20
+++ b/include/hw/timer/bcm2835_systmr.h
21
@@ -XXX,XX +XXX,XX @@ struct BCM2835SystemTimerState {
22
qemu_irq irq;
23
24
struct {
25
- uint32_t status;
26
+ uint32_t ctrl_status;
27
uint32_t compare[BCM2835_SYSTIMER_COUNT];
28
} reg;
29
};
30
diff --git a/hw/timer/bcm2835_systmr.c b/hw/timer/bcm2835_systmr.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/timer/bcm2835_systmr.c
33
+++ b/hw/timer/bcm2835_systmr.c
34
@@ -XXX,XX +XXX,XX @@ REG32(COMPARE3, 0x18)
35
36
static void bcm2835_systmr_update_irq(BCM2835SystemTimerState *s)
37
{
38
- bool enable = !!s->reg.status;
39
+ bool enable = !!s->reg.ctrl_status;
40
41
trace_bcm2835_systmr_irq(enable);
42
qemu_set_irq(s->irq, enable);
43
@@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset,
44
45
switch (offset) {
46
case A_CTRL_STATUS:
47
- r = s->reg.status;
48
+ r = s->reg.ctrl_status;
49
break;
50
case A_COMPARE0 ... A_COMPARE3:
51
r = s->reg.compare[(offset - A_COMPARE0) >> 2];
52
@@ -XXX,XX +XXX,XX @@ static void bcm2835_systmr_write(void *opaque, hwaddr offset,
53
trace_bcm2835_systmr_write(offset, value);
54
switch (offset) {
55
case A_CTRL_STATUS:
56
- s->reg.status &= ~value; /* Ack */
57
+ s->reg.ctrl_status &= ~value; /* Ack */
58
bcm2835_systmr_update_irq(s);
59
break;
60
case A_COMPARE0 ... A_COMPARE3:
61
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription bcm2835_systmr_vmstate = {
62
.version_id = 1,
63
.minimum_version_id = 1,
64
.fields = (VMStateField[]) {
65
- VMSTATE_UINT32(reg.status, BCM2835SystemTimerState),
66
+ VMSTATE_UINT32(reg.ctrl_status, BCM2835SystemTimerState),
67
VMSTATE_UINT32_ARRAY(reg.compare, BCM2835SystemTimerState,
68
BCM2835_SYSTIMER_COUNT),
69
VMSTATE_END_OF_LIST()
70
--
71
2.20.1
72
73
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The kernel image and DeviceTree blob are built by the Armbian
3
This peripheral has 1 free-running timer and 4 compare registers.
4
project (based on Debian):
5
https://www.armbian.com/orange-pi-pc/
6
4
7
The SD image is from the kernelci.org project:
5
Only the free-running timer is implemented. Add support the
8
https://kernelci.org/faq/#the-code
6
COMPARE registers (each register is wired to an IRQ).
9
7
10
If ARM is a target being built, "make check-acceptance" will
8
Reference: "BCM2835 ARM Peripherals" datasheet [*]
11
automatically include this test by the use of the "arch:arm" tags.
9
chapter 12 "System Timer":
12
10
13
Alternatively, this test can be run using:
11
The System Timer peripheral provides four 32-bit timer channels
12
and a single 64-bit free running counter. Each channel has an
13
output compare register, which is compared against the 32 least
14
significant bits of the free running counter values. When the
15
two values match, the system timer peripheral generates a signal
16
to indicate a match for the appropriate channel. The match signal
17
is then fed into the interrupt controller.
14
18
15
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
19
This peripheral is used since Linux 3.7, commit ee4af5696720
16
console: Uncompressing Linux... done, booting the kernel.
20
("ARM: bcm2835: add system timer").
17
console: Booting Linux on physical CPU 0x0
21
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
[*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
19
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
20
[...]
21
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
22
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
23
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
24
console: ledtrig-cpu: registered to indicate activity on CPUs
25
console: hidraw: raw HID events driver (C) Jiri Kosina
26
console: usbcore: registered new interface driver usbhid
27
console: usbhid: USB HID core driver
28
console: Initializing XFRM netlink socket
29
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
30
console: NET: Registered protocol family 10
31
console: mmc0: host does not support reading read-only switch, assuming write-enable
32
console: mmc0: Problem switching card into high-speed mode!
33
console: mmc0: new SD card at address 4567
34
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
35
[...]
36
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
37
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
38
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
39
console: Run /sbin/init as init process
40
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
41
console: Starting syslogd: OK
42
console: Starting klogd: OK
43
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
44
console: /bin/sh: can't access tty; job control turned off
45
console: cat /proc/partitions
46
console: / # cat /proc/partitions
47
console: major minor #blocks name
48
console: 1 0 4096 ram0
49
console: 1 1 4096 ram1
50
console: 1 2 4096 ram2
51
console: 1 3 4096 ram3
52
console: 179 0 61440 mmcblk0
53
console: reboot
54
console: / # reboot
55
console: umount: devtmpfs busy - remounted read-only
56
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
57
console: The system is going down NOW!
58
console: Sent SIGTERM to all processes
59
console: Sent SIGKILL to all processes
60
console: Requesting system reboot
61
console: reboot: Restarting system
62
JOB TIME : 68.64 s
63
23
64
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
65
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
25
Reviewed-by: Luc Michel <luc@lmichel.fr>
66
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
26
Message-id: 20201010203709.3116542-4-f4bug@amsat.org
67
Tested-by: Alex Bennée <alex.bennee@linaro.org>
68
Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com
69
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
70
[NL: extend test with ethernet device checks]
71
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
72
---
28
---
73
tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++
29
include/hw/timer/bcm2835_systmr.h | 11 +++++--
74
1 file changed, 47 insertions(+)
30
hw/timer/bcm2835_systmr.c | 48 ++++++++++++++++++++-----------
31
hw/timer/trace-events | 6 ++--
32
3 files changed, 44 insertions(+), 21 deletions(-)
75
33
76
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
34
diff --git a/include/hw/timer/bcm2835_systmr.h b/include/hw/timer/bcm2835_systmr.h
77
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
78
--- a/tests/acceptance/boot_linux_console.py
36
--- a/include/hw/timer/bcm2835_systmr.h
79
+++ b/tests/acceptance/boot_linux_console.py
37
+++ b/include/hw/timer/bcm2835_systmr.h
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
38
@@ -XXX,XX +XXX,XX @@
81
exec_command_and_wait_for_pattern(self, 'reboot',
39
82
'reboot: Restarting system')
40
#include "hw/sysbus.h"
83
41
#include "hw/irq.h"
84
+ def test_arm_orangepi_sd(self):
42
+#include "qemu/timer.h"
85
+ """
43
#include "qom/object.h"
86
+ :avocado: tags=arch:arm
44
87
+ :avocado: tags=machine:orangepi-pc
45
#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer"
88
+ """
46
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SystemTimerState, BCM2835_SYSTIMER)
89
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
47
90
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
48
#define BCM2835_SYSTIMER_COUNT 4
91
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
49
92
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
50
+typedef struct {
93
+ kernel_path = self.extract_from_deb(deb_path,
51
+ unsigned id;
94
+ '/boot/vmlinuz-4.20.7-sunxi')
52
+ QEMUTimer timer;
95
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
53
+ qemu_irq irq;
96
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
54
+ BCM2835SystemTimerState *state;
97
+ rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
55
+} BCM2835SystemTimerCompare;
98
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
99
+ rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061'
100
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
101
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
102
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
103
+
56
+
104
+ self.vm.set_console()
57
struct BCM2835SystemTimerState {
105
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
58
/*< private >*/
106
+ 'console=ttyS0,115200 '
59
SysBusDevice parent_obj;
107
+ 'root=/dev/mmcblk0 rootwait rw '
60
108
+ 'panic=-1 noreboot')
61
/*< public >*/
109
+ self.vm.add_args('-kernel', kernel_path,
62
MemoryRegion iomem;
110
+ '-dtb', dtb_path,
63
- qemu_irq irq;
111
+ '-drive', 'file=' + rootfs_path + ',if=sd,format=raw',
64
-
112
+ '-append', kernel_command_line,
65
struct {
113
+ '-no-reboot')
66
uint32_t ctrl_status;
114
+ self.vm.launch()
67
uint32_t compare[BCM2835_SYSTIMER_COUNT];
115
+ shell_ready = "/bin/sh: can't access tty; job control turned off"
68
} reg;
116
+ self.wait_for_console_pattern(shell_ready)
69
+ BCM2835SystemTimerCompare tmr[BCM2835_SYSTIMER_COUNT];
70
};
71
72
#endif
73
diff --git a/hw/timer/bcm2835_systmr.c b/hw/timer/bcm2835_systmr.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/timer/bcm2835_systmr.c
76
+++ b/hw/timer/bcm2835_systmr.c
77
@@ -XXX,XX +XXX,XX @@ REG32(COMPARE1, 0x10)
78
REG32(COMPARE2, 0x14)
79
REG32(COMPARE3, 0x18)
80
81
-static void bcm2835_systmr_update_irq(BCM2835SystemTimerState *s)
82
+static void bcm2835_systmr_timer_expire(void *opaque)
83
{
84
- bool enable = !!s->reg.ctrl_status;
85
+ BCM2835SystemTimerCompare *tmr = opaque;
86
87
- trace_bcm2835_systmr_irq(enable);
88
- qemu_set_irq(s->irq, enable);
89
-}
90
-
91
-static void bcm2835_systmr_update_compare(BCM2835SystemTimerState *s,
92
- unsigned timer_index)
93
-{
94
- /* TODO fow now, since neither Linux nor U-boot use these timers. */
95
- qemu_log_mask(LOG_UNIMP, "COMPARE register %u not implemented\n",
96
- timer_index);
97
+ trace_bcm2835_systmr_timer_expired(tmr->id);
98
+ tmr->state->reg.ctrl_status |= 1 << tmr->id;
99
+ qemu_set_irq(tmr->irq, 1);
100
}
101
102
static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset,
103
@@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset,
104
}
105
106
static void bcm2835_systmr_write(void *opaque, hwaddr offset,
107
- uint64_t value, unsigned size)
108
+ uint64_t value64, unsigned size)
109
{
110
BCM2835SystemTimerState *s = BCM2835_SYSTIMER(opaque);
111
+ int index;
112
+ uint32_t value = value64;
113
+ uint32_t triggers_delay_us;
114
+ uint64_t now;
115
116
trace_bcm2835_systmr_write(offset, value);
117
switch (offset) {
118
case A_CTRL_STATUS:
119
s->reg.ctrl_status &= ~value; /* Ack */
120
- bcm2835_systmr_update_irq(s);
121
+ for (index = 0; index < ARRAY_SIZE(s->tmr); index++) {
122
+ if (extract32(value, index, 1)) {
123
+ trace_bcm2835_systmr_irq_ack(index);
124
+ qemu_set_irq(s->tmr[index].irq, 0);
125
+ }
126
+ }
127
break;
128
case A_COMPARE0 ... A_COMPARE3:
129
- s->reg.compare[(offset - A_COMPARE0) >> 2] = value;
130
- bcm2835_systmr_update_compare(s, (offset - A_COMPARE0) >> 2);
131
+ index = (offset - A_COMPARE0) >> 2;
132
+ s->reg.compare[index] = value;
133
+ now = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL);
134
+ /* Compare lower 32-bits of the free-running counter. */
135
+ triggers_delay_us = value - now;
136
+ trace_bcm2835_systmr_run(index, triggers_delay_us);
137
+ timer_mod(&s->tmr[index].timer, now + triggers_delay_us);
138
break;
139
case A_COUNTER_LOW:
140
case A_COUNTER_HIGH:
141
@@ -XXX,XX +XXX,XX @@ static void bcm2835_systmr_realize(DeviceState *dev, Error **errp)
142
memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_systmr_ops,
143
s, "bcm2835-sys-timer", 0x20);
144
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
145
- sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
117
+
146
+
118
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
147
+ for (size_t i = 0; i < ARRAY_SIZE(s->tmr); i++) {
119
+ 'Allwinner sun8i Family')
148
+ s->tmr[i].id = i;
120
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
149
+ s->tmr[i].state = s;
121
+ 'mmcblk0')
150
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->tmr[i].irq);
122
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
151
+ timer_init_us(&s->tmr[i].timer, QEMU_CLOCK_VIRTUAL,
123
+ 'eth0: Link is Up')
152
+ bcm2835_systmr_timer_expire, &s->tmr[i]);
124
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
153
+ }
125
+ 'udhcpc: lease of 10.0.2.15 obtained')
154
}
126
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
155
127
+ '3 packets transmitted, 3 packets received, 0% packet loss')
156
static const VMStateDescription bcm2835_systmr_vmstate = {
128
+ exec_command_and_wait_for_pattern(self, 'reboot',
157
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
129
+ 'reboot: Restarting system')
158
index XXXXXXX..XXXXXXX 100644
130
+
159
--- a/hw/timer/trace-events
131
def test_s390x_s390_ccw_virtio(self):
160
+++ b/hw/timer/trace-events
132
"""
161
@@ -XXX,XX +XXX,XX @@ nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size
133
:avocado: tags=arch:s390x
162
nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
163
164
# bcm2835_systmr.c
165
-bcm2835_systmr_irq(bool enable) "timer irq state %u"
166
+bcm2835_systmr_timer_expired(unsigned id) "timer #%u expired"
167
+bcm2835_systmr_irq_ack(unsigned id) "timer #%u acked"
168
bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64
169
-bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx64
170
+bcm2835_systmr_write(uint64_t offset, uint32_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx32
171
+bcm2835_systmr_run(unsigned id, uint64_t delay_us) "timer #%u expiring in %"PRIu64" us"
172
173
# avr_timer16.c
174
avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:%u"
134
--
175
--
135
2.20.1
176
2.20.1
136
177
137
178
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The SYS_timer is not directly wired to the ARM core, but to the
4
SoC (peripheral) interrupt controller.
5
6
Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20201010203709.3116542-5-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/bcm2835_peripherals.c | 13 +++++++++++--
14
1 file changed, 11 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/bcm2835_peripherals.c
19
+++ b/hw/arm/bcm2835_peripherals.c
20
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
21
memory_region_add_subregion(&s->peri_mr, ST_OFFSET,
22
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0));
23
sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0,
24
- qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
25
- INTERRUPT_ARM_TIMER));
26
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
27
+ INTERRUPT_TIMER0));
28
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 1,
29
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
30
+ INTERRUPT_TIMER1));
31
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 2,
32
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
33
+ INTERRUPT_TIMER2));
34
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 3,
35
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
36
+ INTERRUPT_TIMER3));
37
38
/* UART0 */
39
qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner System on Chip families sun4i and above contain
3
On ARM, the Top Byte Ignore feature means that only 56 bits of
4
an integrated storage controller for Secure Digital (SD) and
4
the address are significant in the virtual address. We are
5
Multi Media Card (MMC) interfaces. This commit adds support
5
required to give the entire 64-bit address to FAR_ELx on fault,
6
for the Allwinner SD/MMC storage controller with the following
6
which means that we do not "clean" the top byte early in TCG.
7
emulated features:
7
8
8
This new interface allows us to flush all 256 possible aliases
9
* DMA transfers
9
for a given page, currently missed by tlb_flush_page*.
10
* Direct FIFO I/O
10
11
* Short/Long format command responses
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
* Auto-Stop command (CMD12)
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
* Insert & remove card detection
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
14
Message-id: 20201016210754.818257-2-richard.henderson@linaro.org
15
The following boards are extended with the SD host controller:
16
17
* Cubieboard (hw/arm/cubieboard.c)
18
* Orange Pi PC (hw/arm/orangepi.c)
19
20
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
21
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
22
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
16
---
26
hw/sd/Makefile.objs | 1 +
17
include/exec/exec-all.h | 36 ++++++
27
include/hw/arm/allwinner-a10.h | 2 +
18
accel/tcg/cputlb.c | 275 ++++++++++++++++++++++++++++++++++++++--
28
include/hw/arm/allwinner-h3.h | 3 +
19
2 files changed, 302 insertions(+), 9 deletions(-)
29
include/hw/sd/allwinner-sdhost.h | 135 +++++
20
30
hw/arm/allwinner-a10.c | 11 +
21
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
31
hw/arm/allwinner-h3.c | 15 +-
32
hw/arm/cubieboard.c | 15 +
33
hw/arm/orangepi.c | 16 +
34
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
35
hw/arm/Kconfig | 1 +
36
hw/sd/trace-events | 7 +
37
11 files changed, 1059 insertions(+), 1 deletion(-)
38
create mode 100644 include/hw/sd/allwinner-sdhost.h
39
create mode 100644 hw/sd/allwinner-sdhost.c
40
41
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
42
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/sd/Makefile.objs
23
--- a/include/exec/exec-all.h
44
+++ b/hw/sd/Makefile.objs
24
+++ b/include/exec/exec-all.h
45
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o
25
@@ -XXX,XX +XXX,XX @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
46
common-obj-$(CONFIG_SDHCI) += sdhci.o
26
* depend on when the guests translation ends the TB.
47
common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o
27
*/
48
28
void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
49
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o
29
+
50
common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
30
+/**
51
common-obj-$(CONFIG_OMAP) += omap_mmc.o
31
+ * tlb_flush_page_bits_by_mmuidx
52
common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
32
+ * @cpu: CPU whose TLB should be flushed
53
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
33
+ * @addr: virtual address of page to be flushed
34
+ * @idxmap: bitmap of mmu indexes to flush
35
+ * @bits: number of significant bits in address
36
+ *
37
+ * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
38
+ */
39
+void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
40
+ uint16_t idxmap, unsigned bits);
41
+
42
+/* Similarly, with broadcast and syncing. */
43
+void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
44
+ uint16_t idxmap, unsigned bits);
45
+void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
46
+ (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
47
+
48
/**
49
* tlb_set_page_with_attrs:
50
* @cpu: CPU to add this TLB entry for
51
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
52
uint16_t idxmap)
53
{
54
}
55
+static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
56
+ target_ulong addr,
57
+ uint16_t idxmap,
58
+ unsigned bits)
59
+{
60
+}
61
+static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
62
+ target_ulong addr,
63
+ uint16_t idxmap,
64
+ unsigned bits)
65
+{
66
+}
67
+static inline void
68
+tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
69
+ uint16_t idxmap, unsigned bits)
70
+{
71
+}
72
#endif
73
/**
74
* probe_access:
75
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
54
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
55
--- a/include/hw/arm/allwinner-a10.h
77
--- a/accel/tcg/cputlb.c
56
+++ b/include/hw/arm/allwinner-a10.h
78
+++ b/accel/tcg/cputlb.c
57
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu)
58
#include "hw/timer/allwinner-a10-pit.h"
80
tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS);
59
#include "hw/intc/allwinner-a10-pic.h"
81
}
60
#include "hw/net/allwinner_emac.h"
82
61
+#include "hw/sd/allwinner-sdhost.h"
83
+static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry,
62
#include "hw/ide/ahci.h"
84
+ target_ulong page, target_ulong mask)
63
#include "hw/usb/hcd-ohci.h"
85
+{
64
#include "hw/usb/hcd-ehci.h"
86
+ page &= mask;
65
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
87
+ mask &= TARGET_PAGE_MASK | TLB_INVALID_MASK;
66
AwA10PICState intc;
88
+
67
AwEmacState emac;
89
+ return (page == (tlb_entry->addr_read & mask) ||
68
AllwinnerAHCIState sata;
90
+ page == (tlb_addr_write(tlb_entry) & mask) ||
69
+ AwSdHostState mmc0;
91
+ page == (tlb_entry->addr_code & mask));
70
MemoryRegion sram_a;
92
+}
71
EHCISysBusState ehci[AW_A10_NUM_USB];
93
+
72
OHCISysBusState ohci[AW_A10_NUM_USB];
94
static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
73
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
95
target_ulong page)
74
index XXXXXXX..XXXXXXX 100644
96
{
75
--- a/include/hw/arm/allwinner-h3.h
97
- return tlb_hit_page(tlb_entry->addr_read, page) ||
76
+++ b/include/hw/arm/allwinner-h3.h
98
- tlb_hit_page(tlb_addr_write(tlb_entry), page) ||
77
@@ -XXX,XX +XXX,XX @@
99
- tlb_hit_page(tlb_entry->addr_code, page);
78
#include "hw/misc/allwinner-cpucfg.h"
100
+ return tlb_hit_page_mask_anyprot(tlb_entry, page, -1);
79
#include "hw/misc/allwinner-h3-sysctrl.h"
101
}
80
#include "hw/misc/allwinner-sid.h"
81
+#include "hw/sd/allwinner-sdhost.h"
82
#include "target/arm/cpu.h"
83
102
84
/**
103
/**
85
@@ -XXX,XX +XXX,XX @@ enum {
104
@@ -XXX,XX +XXX,XX @@ static inline bool tlb_entry_is_empty(const CPUTLBEntry *te)
86
AW_H3_SRAM_A2,
105
}
87
AW_H3_SRAM_C,
106
88
AW_H3_SYSCTRL,
107
/* Called with tlb_c.lock held */
89
+ AW_H3_MMC0,
108
-static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
90
AW_H3_SID,
109
- target_ulong page)
91
AW_H3_EHCI0,
110
+static bool tlb_flush_entry_mask_locked(CPUTLBEntry *tlb_entry,
92
AW_H3_OHCI0,
111
+ target_ulong page,
93
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
112
+ target_ulong mask)
94
AwCpuCfgState cpucfg;
113
{
95
AwH3SysCtrlState sysctrl;
114
- if (tlb_hit_page_anyprot(tlb_entry, page)) {
96
AwSidState sid;
115
+ if (tlb_hit_page_mask_anyprot(tlb_entry, page, mask)) {
97
+ AwSdHostState mmc0;
116
memset(tlb_entry, -1, sizeof(*tlb_entry));
98
GICState gic;
117
return true;
99
MemoryRegion sram_a1;
118
}
100
MemoryRegion sram_a2;
119
return false;
101
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
120
}
102
new file mode 100644
121
103
index XXXXXXX..XXXXXXX
122
+static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
104
--- /dev/null
123
+ target_ulong page)
105
+++ b/include/hw/sd/allwinner-sdhost.h
124
+{
106
@@ -XXX,XX +XXX,XX @@
125
+ return tlb_flush_entry_mask_locked(tlb_entry, page, -1);
107
+/*
126
+}
108
+ * Allwinner (sun4i and above) SD Host Controller emulation
127
+
109
+ *
128
/* Called with tlb_c.lock held */
110
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
129
-static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
111
+ *
130
- target_ulong page)
112
+ * This program is free software: you can redistribute it and/or modify
131
+static void tlb_flush_vtlb_page_mask_locked(CPUArchState *env, int mmu_idx,
113
+ * it under the terms of the GNU General Public License as published by
132
+ target_ulong page,
114
+ * the Free Software Foundation, either version 2 of the License, or
133
+ target_ulong mask)
115
+ * (at your option) any later version.
134
{
116
+ *
135
CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx];
117
+ * This program is distributed in the hope that it will be useful,
136
int k;
118
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
137
119
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
138
assert_cpu_is_self(env_cpu(env));
120
+ * GNU General Public License for more details.
139
for (k = 0; k < CPU_VTLB_SIZE; k++) {
121
+ *
140
- if (tlb_flush_entry_locked(&d->vtable[k], page)) {
122
+ * You should have received a copy of the GNU General Public License
141
+ if (tlb_flush_entry_mask_locked(&d->vtable[k], page, mask)) {
123
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
142
tlb_n_used_entries_dec(env, mmu_idx);
124
+ */
125
+
126
+#ifndef HW_SD_ALLWINNER_SDHOST_H
127
+#define HW_SD_ALLWINNER_SDHOST_H
128
+
129
+#include "qom/object.h"
130
+#include "hw/sysbus.h"
131
+#include "hw/sd/sd.h"
132
+
133
+/**
134
+ * Object model types
135
+ * @{
136
+ */
137
+
138
+/** Generic Allwinner SD Host Controller (abstract) */
139
+#define TYPE_AW_SDHOST "allwinner-sdhost"
140
+
141
+/** Allwinner sun4i family (A10, A12) */
142
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
143
+
144
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
145
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
146
+
147
+/** @} */
148
+
149
+/**
150
+ * Object model macros
151
+ * @{
152
+ */
153
+
154
+#define AW_SDHOST(obj) \
155
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
156
+#define AW_SDHOST_CLASS(klass) \
157
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
158
+#define AW_SDHOST_GET_CLASS(obj) \
159
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
160
+
161
+/** @} */
162
+
163
+/**
164
+ * Allwinner SD Host Controller object instance state.
165
+ */
166
+typedef struct AwSdHostState {
167
+ /*< private >*/
168
+ SysBusDevice busdev;
169
+ /*< public >*/
170
+
171
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
172
+ SDBus sdbus;
173
+
174
+ /** Maps I/O registers in physical memory */
175
+ MemoryRegion iomem;
176
+
177
+ /** Interrupt output signal to notify CPU */
178
+ qemu_irq irq;
179
+
180
+ /** Number of bytes left in current DMA transfer */
181
+ uint32_t transfer_cnt;
182
+
183
+ /**
184
+ * @name Hardware Registers
185
+ * @{
186
+ */
187
+
188
+ uint32_t global_ctl; /**< Global Control */
189
+ uint32_t clock_ctl; /**< Clock Control */
190
+ uint32_t timeout; /**< Timeout */
191
+ uint32_t bus_width; /**< Bus Width */
192
+ uint32_t block_size; /**< Block Size */
193
+ uint32_t byte_count; /**< Byte Count */
194
+
195
+ uint32_t command; /**< Command */
196
+ uint32_t command_arg; /**< Command Argument */
197
+ uint32_t response[4]; /**< Command Response */
198
+
199
+ uint32_t irq_mask; /**< Interrupt Mask */
200
+ uint32_t irq_status; /**< Raw Interrupt Status */
201
+ uint32_t status; /**< Status */
202
+
203
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
204
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
205
+ uint32_t debug_enable; /**< Debug Enable */
206
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
207
+ uint32_t newtiming_set; /**< SD New Timing Set */
208
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
209
+ uint32_t hardware_rst; /**< Hardware Reset */
210
+ uint32_t dmac; /**< Internal DMA Controller Control */
211
+ uint32_t desc_base; /**< Descriptor List Base Address */
212
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
213
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
214
+ uint32_t card_threshold; /**< Card Threshold Control */
215
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
216
+ uint32_t response_crc; /**< Response CRC */
217
+ uint32_t data_crc[8]; /**< Data CRC */
218
+ uint32_t status_crc; /**< Status CRC */
219
+
220
+ /** @} */
221
+
222
+} AwSdHostState;
223
+
224
+/**
225
+ * Allwinner SD Host Controller class-level struct.
226
+ *
227
+ * This struct is filled by each sunxi device specific code
228
+ * such that the generic code can use this struct to support
229
+ * all devices.
230
+ */
231
+typedef struct AwSdHostClass {
232
+ /*< private >*/
233
+ SysBusDeviceClass parent_class;
234
+ /*< public >*/
235
+
236
+ /** Maximum buffer size in bytes per DMA descriptor */
237
+ size_t max_desc_size;
238
+
239
+} AwSdHostClass;
240
+
241
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
242
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/arm/allwinner-a10.c
245
+++ b/hw/arm/allwinner-a10.c
246
@@ -XXX,XX +XXX,XX @@
247
#include "hw/boards.h"
248
#include "hw/usb/hcd-ohci.h"
249
250
+#define AW_A10_MMC0_BASE 0x01c0f000
251
#define AW_A10_PIC_REG_BASE 0x01c20400
252
#define AW_A10_PIT_REG_BASE 0x01c20c00
253
#define AW_A10_UART0_REG_BASE 0x01c28000
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
255
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
256
}
143
}
257
}
144
}
258
+
145
}
259
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
146
260
+ TYPE_AW_SDHOST_SUN4I);
147
+static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
261
}
148
+ target_ulong page)
262
149
+{
263
static void aw_a10_realize(DeviceState *dev, Error **errp)
150
+ tlb_flush_vtlb_page_mask_locked(env, mmu_idx, page, -1);
264
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
151
+}
265
qdev_get_gpio_in(dev, 64 + i));
152
+
266
}
153
static void tlb_flush_page_locked(CPUArchState *env, int midx,
267
}
154
target_ulong page)
268
+
269
+ /* SD/MMC */
270
+ qdev_init_nofail(DEVICE(&s->mmc0));
271
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
272
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
273
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
274
+ "sd-bus", &error_abort);
275
}
276
277
static void aw_a10_class_init(ObjectClass *oc, void *data)
278
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
279
index XXXXXXX..XXXXXXX 100644
280
--- a/hw/arm/allwinner-h3.c
281
+++ b/hw/arm/allwinner-h3.c
282
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
283
[AW_H3_SRAM_A2] = 0x00044000,
284
[AW_H3_SRAM_C] = 0x00010000,
285
[AW_H3_SYSCTRL] = 0x01c00000,
286
+ [AW_H3_MMC0] = 0x01c0f000,
287
[AW_H3_SID] = 0x01c14000,
288
[AW_H3_EHCI0] = 0x01c1a000,
289
[AW_H3_OHCI0] = 0x01c1a400,
290
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
291
{ "lcd0", 0x01c0c000, 4 * KiB },
292
{ "lcd1", 0x01c0d000, 4 * KiB },
293
{ "ve", 0x01c0e000, 4 * KiB },
294
- { "mmc0", 0x01c0f000, 4 * KiB },
295
{ "mmc1", 0x01c10000, 4 * KiB },
296
{ "mmc2", 0x01c11000, 4 * KiB },
297
{ "crypto", 0x01c15000, 4 * KiB },
298
@@ -XXX,XX +XXX,XX @@ enum {
299
AW_H3_GIC_SPI_UART3 = 3,
300
AW_H3_GIC_SPI_TIMER0 = 18,
301
AW_H3_GIC_SPI_TIMER1 = 19,
302
+ AW_H3_GIC_SPI_MMC0 = 60,
303
AW_H3_GIC_SPI_EHCI0 = 72,
304
AW_H3_GIC_SPI_OHCI0 = 73,
305
AW_H3_GIC_SPI_EHCI1 = 74,
306
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
307
TYPE_AW_SID);
308
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
309
"identifier", &error_abort);
310
+
311
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
312
+ TYPE_AW_SDHOST_SUN5I);
313
}
314
315
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
316
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
317
qdev_init_nofail(DEVICE(&s->sid));
318
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
319
320
+ /* SD/MMC */
321
+ qdev_init_nofail(DEVICE(&s->mmc0));
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
323
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
324
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
325
+
326
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
327
+ "sd-bus", &error_abort);
328
+
329
/* Universal Serial Bus */
330
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
331
qdev_get_gpio_in(DEVICE(&s->gic),
332
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/cubieboard.c
335
+++ b/hw/arm/cubieboard.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "sysemu/sysemu.h"
338
#include "hw/sysbus.h"
339
#include "hw/boards.h"
340
+#include "hw/qdev-properties.h"
341
#include "hw/arm/allwinner-a10.h"
342
343
static struct arm_boot_info cubieboard_binfo = {
344
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
345
{
155
{
346
AwA10State *a10;
156
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr)
347
Error *err = NULL;
157
tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS);
348
+ DriveInfo *di;
158
}
349
+ BlockBackend *blk;
159
350
+ BusState *bus;
160
+static void tlb_flush_page_bits_locked(CPUArchState *env, int midx,
351
+ DeviceState *carddev;
161
+ target_ulong page, unsigned bits)
352
162
+{
353
/* BIOS is not supported by this board */
163
+ CPUTLBDesc *d = &env_tlb(env)->d[midx];
354
if (bios_name) {
164
+ CPUTLBDescFast *f = &env_tlb(env)->f[midx];
355
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
165
+ target_ulong mask = MAKE_64BIT_MASK(0, bits);
356
exit(1);
166
+
357
}
167
+ /*
358
168
+ * If @bits is smaller than the tlb size, there may be multiple entries
359
+ /* Retrieve SD bus */
169
+ * within the TLB; otherwise all addresses that match under @mask hit
360
+ di = drive_get_next(IF_SD);
170
+ * the same TLB entry.
361
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
171
+ *
362
+ bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
172
+ * TODO: Perhaps allow bits to be a few bits less than the size.
363
+
173
+ * For now, just flush the entire TLB.
364
+ /* Plug in SD card */
174
+ */
365
+ carddev = qdev_create(bus, TYPE_SD_CARD);
175
+ if (mask < f->mask) {
366
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
176
+ tlb_debug("forcing full flush midx %d ("
367
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
177
+ TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
368
+
178
+ midx, page, mask);
369
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
179
+ tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());
370
machine->ram);
180
+ return;
371
181
+ }
372
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
182
+
373
index XXXXXXX..XXXXXXX 100644
183
+ /* Check if we need to flush due to large pages. */
374
--- a/hw/arm/orangepi.c
184
+ if ((page & d->large_page_mask) == d->large_page_addr) {
375
+++ b/hw/arm/orangepi.c
185
+ tlb_debug("forcing full flush midx %d ("
376
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = {
186
+ TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
377
static void orangepi_init(MachineState *machine)
187
+ midx, d->large_page_addr, d->large_page_mask);
378
{
188
+ tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());
379
AwH3State *h3;
189
+ return;
380
+ DriveInfo *di;
190
+ }
381
+ BlockBackend *blk;
191
+
382
+ BusState *bus;
192
+ if (tlb_flush_entry_mask_locked(tlb_entry(env, midx, page), page, mask)) {
383
+ DeviceState *carddev;
193
+ tlb_n_used_entries_dec(env, midx);
384
194
+ }
385
/* BIOS is not supported by this board */
195
+ tlb_flush_vtlb_page_mask_locked(env, midx, page, mask);
386
if (bios_name) {
196
+}
387
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
197
+
388
/* Mark H3 object realized */
198
+typedef struct {
389
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
199
+ target_ulong addr;
390
200
+ uint16_t idxmap;
391
+ /* Retrieve SD bus */
201
+ uint16_t bits;
392
+ di = drive_get_next(IF_SD);
202
+} TLBFlushPageBitsByMMUIdxData;
393
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
203
+
394
+ bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
204
+static void
395
+
205
+tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu,
396
+ /* Plug in SD card */
206
+ TLBFlushPageBitsByMMUIdxData d)
397
+ carddev = qdev_create(bus, TYPE_SD_CARD);
207
+{
398
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
208
+ CPUArchState *env = cpu->env_ptr;
399
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
209
+ int mmu_idx;
400
+
210
+
401
/* SDRAM */
211
+ assert_cpu_is_self(cpu);
402
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
212
+
403
machine->ram);
213
+ tlb_debug("page addr:" TARGET_FMT_lx "/%u mmu_map:0x%x\n",
404
@@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc)
214
+ d.addr, d.bits, d.idxmap);
405
{
215
+
406
mc->desc = "Orange Pi PC";
216
+ qemu_spin_lock(&env_tlb(env)->c.lock);
407
mc->init = orangepi_init;
217
+ for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
408
+ mc->block_default_type = IF_SD;
218
+ if ((d.idxmap >> mmu_idx) & 1) {
409
+ mc->units_per_default_bus = 1;
219
+ tlb_flush_page_bits_locked(env, mmu_idx, d.addr, d.bits);
410
mc->min_cpus = AW_H3_NUM_CPUS;
220
+ }
411
mc->max_cpus = AW_H3_NUM_CPUS;
221
+ }
412
mc->default_cpus = AW_H3_NUM_CPUS;
222
+ qemu_spin_unlock(&env_tlb(env)->c.lock);
413
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
223
+
414
new file mode 100644
224
+ tb_flush_jmp_cache(cpu, d.addr);
415
index XXXXXXX..XXXXXXX
225
+}
416
--- /dev/null
226
+
417
+++ b/hw/sd/allwinner-sdhost.c
227
+static bool encode_pbm_to_runon(run_on_cpu_data *out,
418
@@ -XXX,XX +XXX,XX @@
228
+ TLBFlushPageBitsByMMUIdxData d)
419
+/*
229
+{
420
+ * Allwinner (sun4i and above) SD Host Controller emulation
230
+ /* We need 6 bits to hold to hold @bits up to 63. */
421
+ *
231
+ if (d.idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) {
422
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
232
+ *out = RUN_ON_CPU_TARGET_PTR(d.addr | (d.idxmap << 6) | d.bits);
423
+ *
233
+ return true;
424
+ * This program is free software: you can redistribute it and/or modify
234
+ }
425
+ * it under the terms of the GNU General Public License as published by
235
+ return false;
426
+ * the Free Software Foundation, either version 2 of the License, or
236
+}
427
+ * (at your option) any later version.
237
+
428
+ *
238
+static TLBFlushPageBitsByMMUIdxData
429
+ * This program is distributed in the hope that it will be useful,
239
+decode_runon_to_pbm(run_on_cpu_data data)
430
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
240
+{
431
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
241
+ target_ulong addr_map_bits = (target_ulong) data.target_ptr;
432
+ * GNU General Public License for more details.
242
+ return (TLBFlushPageBitsByMMUIdxData){
433
+ *
243
+ .addr = addr_map_bits & TARGET_PAGE_MASK,
434
+ * You should have received a copy of the GNU General Public License
244
+ .idxmap = (addr_map_bits & ~TARGET_PAGE_MASK) >> 6,
435
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
245
+ .bits = addr_map_bits & 0x3f
436
+ */
246
+ };
437
+
247
+}
438
+#include "qemu/osdep.h"
248
+
439
+#include "qemu/log.h"
249
+static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu,
440
+#include "qemu/module.h"
250
+ run_on_cpu_data runon)
441
+#include "qemu/units.h"
251
+{
442
+#include "sysemu/blockdev.h"
252
+ tlb_flush_page_bits_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon));
443
+#include "hw/irq.h"
253
+}
444
+#include "hw/sd/allwinner-sdhost.h"
254
+
445
+#include "migration/vmstate.h"
255
+static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
446
+#include "trace.h"
256
+ run_on_cpu_data data)
447
+
257
+{
448
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
258
+ TLBFlushPageBitsByMMUIdxData *d = data.host_ptr;
449
+#define AW_SDHOST_BUS(obj) \
259
+ tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d);
450
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
260
+ g_free(d);
451
+
261
+}
452
+/* SD Host register offsets */
262
+
453
+enum {
263
+void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
454
+ REG_SD_GCTL = 0x00, /* Global Control */
264
+ uint16_t idxmap, unsigned bits)
455
+ REG_SD_CKCR = 0x04, /* Clock Control */
265
+{
456
+ REG_SD_TMOR = 0x08, /* Timeout */
266
+ TLBFlushPageBitsByMMUIdxData d;
457
+ REG_SD_BWDR = 0x0C, /* Bus Width */
267
+ run_on_cpu_data runon;
458
+ REG_SD_BKSR = 0x10, /* Block Size */
268
+
459
+ REG_SD_BYCR = 0x14, /* Byte Count */
269
+ /* If all bits are significant, this devolves to tlb_flush_page. */
460
+ REG_SD_CMDR = 0x18, /* Command */
270
+ if (bits >= TARGET_LONG_BITS) {
461
+ REG_SD_CAGR = 0x1C, /* Command Argument */
271
+ tlb_flush_page_by_mmuidx(cpu, addr, idxmap);
462
+ REG_SD_RESP0 = 0x20, /* Response Zero */
272
+ return;
463
+ REG_SD_RESP1 = 0x24, /* Response One */
273
+ }
464
+ REG_SD_RESP2 = 0x28, /* Response Two */
274
+ /* If no page bits are significant, this devolves to tlb_flush. */
465
+ REG_SD_RESP3 = 0x2C, /* Response Three */
275
+ if (bits < TARGET_PAGE_BITS) {
466
+ REG_SD_IMKR = 0x30, /* Interrupt Mask */
276
+ tlb_flush_by_mmuidx(cpu, idxmap);
467
+ REG_SD_MISR = 0x34, /* Masked Interrupt Status */
277
+ return;
468
+ REG_SD_RISR = 0x38, /* Raw Interrupt Status */
278
+ }
469
+ REG_SD_STAR = 0x3C, /* Status */
279
+
470
+ REG_SD_FWLR = 0x40, /* FIFO Water Level */
280
+ /* This should already be page aligned */
471
+ REG_SD_FUNS = 0x44, /* FIFO Function Select */
281
+ d.addr = addr & TARGET_PAGE_MASK;
472
+ REG_SD_DBGC = 0x50, /* Debug Enable */
282
+ d.idxmap = idxmap;
473
+ REG_SD_A12A = 0x58, /* Auto command 12 argument */
283
+ d.bits = bits;
474
+ REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
284
+
475
+ REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
285
+ if (qemu_cpu_is_self(cpu)) {
476
+ REG_SD_HWRST = 0x78, /* Hardware Reset Register */
286
+ tlb_flush_page_bits_by_mmuidx_async_0(cpu, d);
477
+ REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
287
+ } else if (encode_pbm_to_runon(&runon, d)) {
478
+ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
288
+ async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
479
+ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
480
+ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
481
+ REG_SD_THLDC = 0x100, /* Card Threshold Control */
482
+ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
483
+ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
484
+ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
485
+ REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
486
+ REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
487
+ REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
488
+ REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
489
+ REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
490
+ REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
491
+ REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
492
+ REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
493
+ REG_SD_FIFO = 0x200, /* Read/Write FIFO */
494
+};
495
+
496
+/* SD Host register flags */
497
+enum {
498
+ SD_GCTL_FIFO_AC_MOD = (1 << 31),
499
+ SD_GCTL_DDR_MOD_SEL = (1 << 10),
500
+ SD_GCTL_CD_DBC_ENB = (1 << 8),
501
+ SD_GCTL_DMA_ENB = (1 << 5),
502
+ SD_GCTL_INT_ENB = (1 << 4),
503
+ SD_GCTL_DMA_RST = (1 << 2),
504
+ SD_GCTL_FIFO_RST = (1 << 1),
505
+ SD_GCTL_SOFT_RST = (1 << 0),
506
+};
507
+
508
+enum {
509
+ SD_CMDR_LOAD = (1 << 31),
510
+ SD_CMDR_CLKCHANGE = (1 << 21),
511
+ SD_CMDR_WRITE = (1 << 10),
512
+ SD_CMDR_AUTOSTOP = (1 << 12),
513
+ SD_CMDR_DATA = (1 << 9),
514
+ SD_CMDR_RESPONSE_LONG = (1 << 7),
515
+ SD_CMDR_RESPONSE = (1 << 6),
516
+ SD_CMDR_CMDID_MASK = (0x3f),
517
+};
518
+
519
+enum {
520
+ SD_RISR_CARD_REMOVE = (1 << 31),
521
+ SD_RISR_CARD_INSERT = (1 << 30),
522
+ SD_RISR_SDIO_INTR = (1 << 16),
523
+ SD_RISR_AUTOCMD_DONE = (1 << 14),
524
+ SD_RISR_DATA_COMPLETE = (1 << 3),
525
+ SD_RISR_CMD_COMPLETE = (1 << 2),
526
+ SD_RISR_NO_RESPONSE = (1 << 1),
527
+};
528
+
529
+enum {
530
+ SD_STAR_CARD_PRESENT = (1 << 8),
531
+};
532
+
533
+enum {
534
+ SD_IDST_INT_SUMMARY = (1 << 8),
535
+ SD_IDST_RECEIVE_IRQ = (1 << 1),
536
+ SD_IDST_TRANSMIT_IRQ = (1 << 0),
537
+ SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
538
+ SD_IDST_WR_MASK = (0x3ff),
539
+};
540
+
541
+/* SD Host register reset values */
542
+enum {
543
+ REG_SD_GCTL_RST = 0x00000300,
544
+ REG_SD_CKCR_RST = 0x0,
545
+ REG_SD_TMOR_RST = 0xFFFFFF40,
546
+ REG_SD_BWDR_RST = 0x0,
547
+ REG_SD_BKSR_RST = 0x00000200,
548
+ REG_SD_BYCR_RST = 0x00000200,
549
+ REG_SD_CMDR_RST = 0x0,
550
+ REG_SD_CAGR_RST = 0x0,
551
+ REG_SD_RESP_RST = 0x0,
552
+ REG_SD_IMKR_RST = 0x0,
553
+ REG_SD_MISR_RST = 0x0,
554
+ REG_SD_RISR_RST = 0x0,
555
+ REG_SD_STAR_RST = 0x00000100,
556
+ REG_SD_FWLR_RST = 0x000F0000,
557
+ REG_SD_FUNS_RST = 0x0,
558
+ REG_SD_DBGC_RST = 0x0,
559
+ REG_SD_A12A_RST = 0x0000FFFF,
560
+ REG_SD_NTSR_RST = 0x00000001,
561
+ REG_SD_SDBG_RST = 0x0,
562
+ REG_SD_HWRST_RST = 0x00000001,
563
+ REG_SD_DMAC_RST = 0x0,
564
+ REG_SD_DLBA_RST = 0x0,
565
+ REG_SD_IDST_RST = 0x0,
566
+ REG_SD_IDIE_RST = 0x0,
567
+ REG_SD_THLDC_RST = 0x0,
568
+ REG_SD_DSBD_RST = 0x0,
569
+ REG_SD_RES_CRC_RST = 0x0,
570
+ REG_SD_DATA_CRC_RST = 0x0,
571
+ REG_SD_CRC_STA_RST = 0x0,
572
+ REG_SD_FIFO_RST = 0x0,
573
+};
574
+
575
+/* Data transfer descriptor for DMA */
576
+typedef struct TransferDescriptor {
577
+ uint32_t status; /* Status flags */
578
+ uint32_t size; /* Data buffer size */
579
+ uint32_t addr; /* Data buffer address */
580
+ uint32_t next; /* Physical address of next descriptor */
581
+} TransferDescriptor;
582
+
583
+/* Data transfer descriptor flags */
584
+enum {
585
+ DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
586
+ DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
587
+ DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
588
+ DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
589
+ DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
590
+ DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
591
+ DESC_SIZE_MASK = (0xfffffffc)
592
+};
593
+
594
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
595
+{
596
+ uint32_t irq;
597
+
598
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
599
+ irq = s->irq_status & s->irq_mask;
600
+ } else {
289
+ } else {
601
+ irq = 0;
290
+ TLBFlushPageBitsByMMUIdxData *p
602
+ }
291
+ = g_new(TLBFlushPageBitsByMMUIdxData, 1);
603
+
292
+
604
+ trace_allwinner_sdhost_update_irq(irq);
293
+ /* Otherwise allocate a structure, freed by the worker. */
605
+ qemu_set_irq(s->irq, irq);
294
+ *p = d;
606
+}
295
+ async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2,
607
+
296
+ RUN_ON_CPU_HOST_PTR(p));
608
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
297
+ }
609
+ uint32_t bytes)
298
+}
610
+{
299
+
611
+ if (s->transfer_cnt > bytes) {
300
+void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
612
+ s->transfer_cnt -= bytes;
301
+ target_ulong addr,
302
+ uint16_t idxmap,
303
+ unsigned bits)
304
+{
305
+ TLBFlushPageBitsByMMUIdxData d;
306
+ run_on_cpu_data runon;
307
+
308
+ /* If all bits are significant, this devolves to tlb_flush_page. */
309
+ if (bits >= TARGET_LONG_BITS) {
310
+ tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap);
311
+ return;
312
+ }
313
+ /* If no page bits are significant, this devolves to tlb_flush. */
314
+ if (bits < TARGET_PAGE_BITS) {
315
+ tlb_flush_by_mmuidx_all_cpus(src_cpu, idxmap);
316
+ return;
317
+ }
318
+
319
+ /* This should already be page aligned */
320
+ d.addr = addr & TARGET_PAGE_MASK;
321
+ d.idxmap = idxmap;
322
+ d.bits = bits;
323
+
324
+ if (encode_pbm_to_runon(&runon, d)) {
325
+ flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
613
+ } else {
326
+ } else {
614
+ s->transfer_cnt = 0;
327
+ CPUState *dst_cpu;
615
+ }
328
+ TLBFlushPageBitsByMMUIdxData *p;
616
+
329
+
617
+ if (!s->transfer_cnt) {
330
+ /* Allocate a separate data block for each destination cpu. */
618
+ s->irq_status |= SD_RISR_DATA_COMPLETE;
331
+ CPU_FOREACH(dst_cpu) {
619
+ }
332
+ if (dst_cpu != src_cpu) {
620
+}
333
+ p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
621
+
334
+ *p = d;
622
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
335
+ async_run_on_cpu(dst_cpu,
623
+{
336
+ tlb_flush_page_bits_by_mmuidx_async_2,
624
+ AwSdHostState *s = AW_SDHOST(dev);
337
+ RUN_ON_CPU_HOST_PTR(p));
625
+
626
+ trace_allwinner_sdhost_set_inserted(inserted);
627
+
628
+ if (inserted) {
629
+ s->irq_status |= SD_RISR_CARD_INSERT;
630
+ s->irq_status &= ~SD_RISR_CARD_REMOVE;
631
+ s->status |= SD_STAR_CARD_PRESENT;
632
+ } else {
633
+ s->irq_status &= ~SD_RISR_CARD_INSERT;
634
+ s->irq_status |= SD_RISR_CARD_REMOVE;
635
+ s->status &= ~SD_STAR_CARD_PRESENT;
636
+ }
637
+
638
+ allwinner_sdhost_update_irq(s);
639
+}
640
+
641
+static void allwinner_sdhost_send_command(AwSdHostState *s)
642
+{
643
+ SDRequest request;
644
+ uint8_t resp[16];
645
+ int rlen;
646
+
647
+ /* Auto clear load flag */
648
+ s->command &= ~SD_CMDR_LOAD;
649
+
650
+ /* Clock change does not actually interact with the SD bus */
651
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
652
+
653
+ /* Prepare request */
654
+ request.cmd = s->command & SD_CMDR_CMDID_MASK;
655
+ request.arg = s->command_arg;
656
+
657
+ /* Send request to SD bus */
658
+ rlen = sdbus_do_command(&s->sdbus, &request, resp);
659
+ if (rlen < 0) {
660
+ goto error;
661
+ }
662
+
663
+ /* If the command has a response, store it in the response registers */
664
+ if ((s->command & SD_CMDR_RESPONSE)) {
665
+ if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
666
+ s->response[0] = ldl_be_p(&resp[0]);
667
+ s->response[1] = s->response[2] = s->response[3] = 0;
668
+
669
+ } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
670
+ s->response[0] = ldl_be_p(&resp[12]);
671
+ s->response[1] = ldl_be_p(&resp[8]);
672
+ s->response[2] = ldl_be_p(&resp[4]);
673
+ s->response[3] = ldl_be_p(&resp[0]);
674
+ } else {
675
+ goto error;
676
+ }
338
+ }
677
+ }
339
+ }
678
+ }
340
+ }
679
+
341
+
680
+ /* Set interrupt status bits */
342
+ tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d);
681
+ s->irq_status |= SD_RISR_CMD_COMPLETE;
343
+}
682
+ return;
344
+
683
+
345
+void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
684
+error:
346
+ target_ulong addr,
685
+ s->irq_status |= SD_RISR_NO_RESPONSE;
347
+ uint16_t idxmap,
686
+}
348
+ unsigned bits)
687
+
349
+{
688
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
350
+ TLBFlushPageBitsByMMUIdxData d;
689
+{
351
+ run_on_cpu_data runon;
690
+ /*
352
+
691
+ * The stop command (CMD12) ensures the SD bus
353
+ /* If all bits are significant, this devolves to tlb_flush_page. */
692
+ * returns to the transfer state.
354
+ if (bits >= TARGET_LONG_BITS) {
693
+ */
355
+ tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
694
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
356
+ return;
695
+ /* First save current command registers */
357
+ }
696
+ uint32_t saved_cmd = s->command;
358
+ /* If no page bits are significant, this devolves to tlb_flush. */
697
+ uint32_t saved_arg = s->command_arg;
359
+ if (bits < TARGET_PAGE_BITS) {
698
+
360
+ tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap);
699
+ /* Prepare stop command (CMD12) */
361
+ return;
700
+ s->command &= ~SD_CMDR_CMDID_MASK;
362
+ }
701
+ s->command |= 12; /* CMD12 */
363
+
702
+ s->command_arg = 0;
364
+ /* This should already be page aligned */
703
+
365
+ d.addr = addr & TARGET_PAGE_MASK;
704
+ /* Put the command on SD bus */
366
+ d.idxmap = idxmap;
705
+ allwinner_sdhost_send_command(s);
367
+ d.bits = bits;
706
+
368
+
707
+ /* Restore command values */
369
+ if (encode_pbm_to_runon(&runon, d)) {
708
+ s->command = saved_cmd;
370
+ flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
709
+ s->command_arg = saved_arg;
371
+ async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1,
710
+
372
+ runon);
711
+ /* Set IRQ status bit for automatic stop done */
373
+ } else {
712
+ s->irq_status |= SD_RISR_AUTOCMD_DONE;
374
+ CPUState *dst_cpu;
713
+ }
375
+ TLBFlushPageBitsByMMUIdxData *p;
714
+}
376
+
715
+
377
+ /* Allocate a separate data block for each destination cpu. */
716
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
378
+ CPU_FOREACH(dst_cpu) {
717
+ hwaddr desc_addr,
379
+ if (dst_cpu != src_cpu) {
718
+ TransferDescriptor *desc,
380
+ p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
719
+ bool is_write, uint32_t max_bytes)
381
+ *p = d;
720
+{
382
+ async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
721
+ AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
383
+ RUN_ON_CPU_HOST_PTR(p));
722
+ uint32_t num_done = 0;
384
+ }
723
+ uint32_t num_bytes = max_bytes;
724
+ uint8_t buf[1024];
725
+
726
+ /* Read descriptor */
727
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
728
+ if (desc->size == 0) {
729
+ desc->size = klass->max_desc_size;
730
+ } else if (desc->size > klass->max_desc_size) {
731
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
732
+ " is out-of-bounds: %" PRIu32 " > %zu",
733
+ __func__, desc->size, klass->max_desc_size);
734
+ desc->size = klass->max_desc_size;
735
+ }
736
+ if (desc->size < num_bytes) {
737
+ num_bytes = desc->size;
738
+ }
739
+
740
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
741
+ is_write, max_bytes);
742
+
743
+ while (num_done < num_bytes) {
744
+ /* Try to completely fill the local buffer */
745
+ uint32_t buf_bytes = num_bytes - num_done;
746
+ if (buf_bytes > sizeof(buf)) {
747
+ buf_bytes = sizeof(buf);
748
+ }
385
+ }
749
+
386
+
750
+ /* Write to SD bus */
387
+ p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
751
+ if (is_write) {
388
+ *p = d;
752
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
389
+ async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
753
+ buf, buf_bytes);
390
+ RUN_ON_CPU_HOST_PTR(p));
754
+
391
+ }
755
+ for (uint32_t i = 0; i < buf_bytes; i++) {
392
+}
756
+ sdbus_write_data(&s->sdbus, buf[i]);
393
+
757
+ }
394
/* update the TLBs so that writes to code in the virtual page 'addr'
758
+
395
can be detected */
759
+ /* Read from SD bus */
396
void tlb_protect_code(ram_addr_t ram_addr)
760
+ } else {
761
+ for (uint32_t i = 0; i < buf_bytes; i++) {
762
+ buf[i] = sdbus_read_data(&s->sdbus);
763
+ }
764
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
765
+ buf, buf_bytes);
766
+ }
767
+ num_done += buf_bytes;
768
+ }
769
+
770
+ /* Clear hold flag and flush descriptor */
771
+ desc->status &= ~DESC_STATUS_HOLD;
772
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
773
+
774
+ return num_done;
775
+}
776
+
777
+static void allwinner_sdhost_dma(AwSdHostState *s)
778
+{
779
+ TransferDescriptor desc;
780
+ hwaddr desc_addr = s->desc_base;
781
+ bool is_write = (s->command & SD_CMDR_WRITE);
782
+ uint32_t bytes_done = 0;
783
+
784
+ /* Check if DMA can be performed */
785
+ if (s->byte_count == 0 || s->block_size == 0 ||
786
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
787
+ return;
788
+ }
789
+
790
+ /*
791
+ * For read operations, data must be available on the SD bus
792
+ * If not, it is an error and we should not act at all
793
+ */
794
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
795
+ return;
796
+ }
797
+
798
+ /* Process the DMA descriptors until all data is copied */
799
+ while (s->byte_count > 0) {
800
+ bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
801
+ is_write, s->byte_count);
802
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
803
+
804
+ if (bytes_done <= s->byte_count) {
805
+ s->byte_count -= bytes_done;
806
+ } else {
807
+ s->byte_count = 0;
808
+ }
809
+
810
+ if (desc.status & DESC_STATUS_LAST) {
811
+ break;
812
+ } else {
813
+ desc_addr = desc.next;
814
+ }
815
+ }
816
+
817
+ /* Raise IRQ to signal DMA is completed */
818
+ s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
819
+
820
+ /* Update DMAC bits */
821
+ s->dmac_status |= SD_IDST_INT_SUMMARY;
822
+
823
+ if (is_write) {
824
+ s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
825
+ } else {
826
+ s->dmac_status |= SD_IDST_RECEIVE_IRQ;
827
+ }
828
+}
829
+
830
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
831
+ unsigned size)
832
+{
833
+ AwSdHostState *s = AW_SDHOST(opaque);
834
+ uint32_t res = 0;
835
+
836
+ switch (offset) {
837
+ case REG_SD_GCTL: /* Global Control */
838
+ res = s->global_ctl;
839
+ break;
840
+ case REG_SD_CKCR: /* Clock Control */
841
+ res = s->clock_ctl;
842
+ break;
843
+ case REG_SD_TMOR: /* Timeout */
844
+ res = s->timeout;
845
+ break;
846
+ case REG_SD_BWDR: /* Bus Width */
847
+ res = s->bus_width;
848
+ break;
849
+ case REG_SD_BKSR: /* Block Size */
850
+ res = s->block_size;
851
+ break;
852
+ case REG_SD_BYCR: /* Byte Count */
853
+ res = s->byte_count;
854
+ break;
855
+ case REG_SD_CMDR: /* Command */
856
+ res = s->command;
857
+ break;
858
+ case REG_SD_CAGR: /* Command Argument */
859
+ res = s->command_arg;
860
+ break;
861
+ case REG_SD_RESP0: /* Response Zero */
862
+ res = s->response[0];
863
+ break;
864
+ case REG_SD_RESP1: /* Response One */
865
+ res = s->response[1];
866
+ break;
867
+ case REG_SD_RESP2: /* Response Two */
868
+ res = s->response[2];
869
+ break;
870
+ case REG_SD_RESP3: /* Response Three */
871
+ res = s->response[3];
872
+ break;
873
+ case REG_SD_IMKR: /* Interrupt Mask */
874
+ res = s->irq_mask;
875
+ break;
876
+ case REG_SD_MISR: /* Masked Interrupt Status */
877
+ res = s->irq_status & s->irq_mask;
878
+ break;
879
+ case REG_SD_RISR: /* Raw Interrupt Status */
880
+ res = s->irq_status;
881
+ break;
882
+ case REG_SD_STAR: /* Status */
883
+ res = s->status;
884
+ break;
885
+ case REG_SD_FWLR: /* FIFO Water Level */
886
+ res = s->fifo_wlevel;
887
+ break;
888
+ case REG_SD_FUNS: /* FIFO Function Select */
889
+ res = s->fifo_func_sel;
890
+ break;
891
+ case REG_SD_DBGC: /* Debug Enable */
892
+ res = s->debug_enable;
893
+ break;
894
+ case REG_SD_A12A: /* Auto command 12 argument */
895
+ res = s->auto12_arg;
896
+ break;
897
+ case REG_SD_NTSR: /* SD NewTiming Set */
898
+ res = s->newtiming_set;
899
+ break;
900
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
901
+ res = s->newtiming_debug;
902
+ break;
903
+ case REG_SD_HWRST: /* Hardware Reset Register */
904
+ res = s->hardware_rst;
905
+ break;
906
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
907
+ res = s->dmac;
908
+ break;
909
+ case REG_SD_DLBA: /* Descriptor List Base Address */
910
+ res = s->desc_base;
911
+ break;
912
+ case REG_SD_IDST: /* Internal DMA Controller Status */
913
+ res = s->dmac_status;
914
+ break;
915
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
916
+ res = s->dmac_irq;
917
+ break;
918
+ case REG_SD_THLDC: /* Card Threshold Control */
919
+ res = s->card_threshold;
920
+ break;
921
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
922
+ res = s->startbit_detect;
923
+ break;
924
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
925
+ res = s->response_crc;
926
+ break;
927
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
928
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
929
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
930
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
931
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
932
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
933
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
934
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
935
+ res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
936
+ break;
937
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
938
+ res = s->status_crc;
939
+ break;
940
+ case REG_SD_FIFO: /* Read/Write FIFO */
941
+ if (sdbus_data_ready(&s->sdbus)) {
942
+ res = sdbus_read_data(&s->sdbus);
943
+ res |= sdbus_read_data(&s->sdbus) << 8;
944
+ res |= sdbus_read_data(&s->sdbus) << 16;
945
+ res |= sdbus_read_data(&s->sdbus) << 24;
946
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
947
+ allwinner_sdhost_auto_stop(s);
948
+ allwinner_sdhost_update_irq(s);
949
+ } else {
950
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
951
+ __func__);
952
+ }
953
+ break;
954
+ default:
955
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
956
+ HWADDR_PRIx"\n", __func__, offset);
957
+ res = 0;
958
+ break;
959
+ }
960
+
961
+ trace_allwinner_sdhost_read(offset, res, size);
962
+ return res;
963
+}
964
+
965
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
966
+ uint64_t value, unsigned size)
967
+{
968
+ AwSdHostState *s = AW_SDHOST(opaque);
969
+
970
+ trace_allwinner_sdhost_write(offset, value, size);
971
+
972
+ switch (offset) {
973
+ case REG_SD_GCTL: /* Global Control */
974
+ s->global_ctl = value;
975
+ s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
976
+ SD_GCTL_SOFT_RST);
977
+ allwinner_sdhost_update_irq(s);
978
+ break;
979
+ case REG_SD_CKCR: /* Clock Control */
980
+ s->clock_ctl = value;
981
+ break;
982
+ case REG_SD_TMOR: /* Timeout */
983
+ s->timeout = value;
984
+ break;
985
+ case REG_SD_BWDR: /* Bus Width */
986
+ s->bus_width = value;
987
+ break;
988
+ case REG_SD_BKSR: /* Block Size */
989
+ s->block_size = value;
990
+ break;
991
+ case REG_SD_BYCR: /* Byte Count */
992
+ s->byte_count = value;
993
+ s->transfer_cnt = value;
994
+ break;
995
+ case REG_SD_CMDR: /* Command */
996
+ s->command = value;
997
+ if (value & SD_CMDR_LOAD) {
998
+ allwinner_sdhost_send_command(s);
999
+ allwinner_sdhost_dma(s);
1000
+ allwinner_sdhost_auto_stop(s);
1001
+ }
1002
+ allwinner_sdhost_update_irq(s);
1003
+ break;
1004
+ case REG_SD_CAGR: /* Command Argument */
1005
+ s->command_arg = value;
1006
+ break;
1007
+ case REG_SD_RESP0: /* Response Zero */
1008
+ s->response[0] = value;
1009
+ break;
1010
+ case REG_SD_RESP1: /* Response One */
1011
+ s->response[1] = value;
1012
+ break;
1013
+ case REG_SD_RESP2: /* Response Two */
1014
+ s->response[2] = value;
1015
+ break;
1016
+ case REG_SD_RESP3: /* Response Three */
1017
+ s->response[3] = value;
1018
+ break;
1019
+ case REG_SD_IMKR: /* Interrupt Mask */
1020
+ s->irq_mask = value;
1021
+ allwinner_sdhost_update_irq(s);
1022
+ break;
1023
+ case REG_SD_MISR: /* Masked Interrupt Status */
1024
+ case REG_SD_RISR: /* Raw Interrupt Status */
1025
+ s->irq_status &= ~value;
1026
+ allwinner_sdhost_update_irq(s);
1027
+ break;
1028
+ case REG_SD_STAR: /* Status */
1029
+ s->status &= ~value;
1030
+ allwinner_sdhost_update_irq(s);
1031
+ break;
1032
+ case REG_SD_FWLR: /* FIFO Water Level */
1033
+ s->fifo_wlevel = value;
1034
+ break;
1035
+ case REG_SD_FUNS: /* FIFO Function Select */
1036
+ s->fifo_func_sel = value;
1037
+ break;
1038
+ case REG_SD_DBGC: /* Debug Enable */
1039
+ s->debug_enable = value;
1040
+ break;
1041
+ case REG_SD_A12A: /* Auto command 12 argument */
1042
+ s->auto12_arg = value;
1043
+ break;
1044
+ case REG_SD_NTSR: /* SD NewTiming Set */
1045
+ s->newtiming_set = value;
1046
+ break;
1047
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
1048
+ s->newtiming_debug = value;
1049
+ break;
1050
+ case REG_SD_HWRST: /* Hardware Reset Register */
1051
+ s->hardware_rst = value;
1052
+ break;
1053
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
1054
+ s->dmac = value;
1055
+ allwinner_sdhost_update_irq(s);
1056
+ break;
1057
+ case REG_SD_DLBA: /* Descriptor List Base Address */
1058
+ s->desc_base = value;
1059
+ break;
1060
+ case REG_SD_IDST: /* Internal DMA Controller Status */
1061
+ s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
1062
+ allwinner_sdhost_update_irq(s);
1063
+ break;
1064
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
1065
+ s->dmac_irq = value;
1066
+ allwinner_sdhost_update_irq(s);
1067
+ break;
1068
+ case REG_SD_THLDC: /* Card Threshold Control */
1069
+ s->card_threshold = value;
1070
+ break;
1071
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
1072
+ s->startbit_detect = value;
1073
+ break;
1074
+ case REG_SD_FIFO: /* Read/Write FIFO */
1075
+ sdbus_write_data(&s->sdbus, value & 0xff);
1076
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
1077
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
1078
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
1079
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
1080
+ allwinner_sdhost_auto_stop(s);
1081
+ allwinner_sdhost_update_irq(s);
1082
+ break;
1083
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
1084
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
1085
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
1086
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
1087
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
1088
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
1089
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
1090
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
1091
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
1092
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
1093
+ break;
1094
+ default:
1095
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
1096
+ HWADDR_PRIx"\n", __func__, offset);
1097
+ break;
1098
+ }
1099
+}
1100
+
1101
+static const MemoryRegionOps allwinner_sdhost_ops = {
1102
+ .read = allwinner_sdhost_read,
1103
+ .write = allwinner_sdhost_write,
1104
+ .endianness = DEVICE_NATIVE_ENDIAN,
1105
+ .valid = {
1106
+ .min_access_size = 4,
1107
+ .max_access_size = 4,
1108
+ },
1109
+ .impl.min_access_size = 4,
1110
+};
1111
+
1112
+static const VMStateDescription vmstate_allwinner_sdhost = {
1113
+ .name = "allwinner-sdhost",
1114
+ .version_id = 1,
1115
+ .minimum_version_id = 1,
1116
+ .fields = (VMStateField[]) {
1117
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
1118
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
1119
+ VMSTATE_UINT32(timeout, AwSdHostState),
1120
+ VMSTATE_UINT32(bus_width, AwSdHostState),
1121
+ VMSTATE_UINT32(block_size, AwSdHostState),
1122
+ VMSTATE_UINT32(byte_count, AwSdHostState),
1123
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
1124
+ VMSTATE_UINT32(command, AwSdHostState),
1125
+ VMSTATE_UINT32(command_arg, AwSdHostState),
1126
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
1127
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
1128
+ VMSTATE_UINT32(irq_status, AwSdHostState),
1129
+ VMSTATE_UINT32(status, AwSdHostState),
1130
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
1131
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
1132
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
1133
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
1134
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
1135
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
1136
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
1137
+ VMSTATE_UINT32(dmac, AwSdHostState),
1138
+ VMSTATE_UINT32(desc_base, AwSdHostState),
1139
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
1140
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
1141
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
1142
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
1143
+ VMSTATE_UINT32(response_crc, AwSdHostState),
1144
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
1145
+ VMSTATE_UINT32(status_crc, AwSdHostState),
1146
+ VMSTATE_END_OF_LIST()
1147
+ }
1148
+};
1149
+
1150
+static void allwinner_sdhost_init(Object *obj)
1151
+{
1152
+ AwSdHostState *s = AW_SDHOST(obj);
1153
+
1154
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1155
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
1156
+
1157
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
1158
+ TYPE_AW_SDHOST, 4 * KiB);
1159
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
1160
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
1161
+}
1162
+
1163
+static void allwinner_sdhost_reset(DeviceState *dev)
1164
+{
1165
+ AwSdHostState *s = AW_SDHOST(dev);
1166
+
1167
+ s->global_ctl = REG_SD_GCTL_RST;
1168
+ s->clock_ctl = REG_SD_CKCR_RST;
1169
+ s->timeout = REG_SD_TMOR_RST;
1170
+ s->bus_width = REG_SD_BWDR_RST;
1171
+ s->block_size = REG_SD_BKSR_RST;
1172
+ s->byte_count = REG_SD_BYCR_RST;
1173
+ s->transfer_cnt = 0;
1174
+
1175
+ s->command = REG_SD_CMDR_RST;
1176
+ s->command_arg = REG_SD_CAGR_RST;
1177
+
1178
+ for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
1179
+ s->response[i] = REG_SD_RESP_RST;
1180
+ }
1181
+
1182
+ s->irq_mask = REG_SD_IMKR_RST;
1183
+ s->irq_status = REG_SD_RISR_RST;
1184
+ s->status = REG_SD_STAR_RST;
1185
+
1186
+ s->fifo_wlevel = REG_SD_FWLR_RST;
1187
+ s->fifo_func_sel = REG_SD_FUNS_RST;
1188
+ s->debug_enable = REG_SD_DBGC_RST;
1189
+ s->auto12_arg = REG_SD_A12A_RST;
1190
+ s->newtiming_set = REG_SD_NTSR_RST;
1191
+ s->newtiming_debug = REG_SD_SDBG_RST;
1192
+ s->hardware_rst = REG_SD_HWRST_RST;
1193
+ s->dmac = REG_SD_DMAC_RST;
1194
+ s->desc_base = REG_SD_DLBA_RST;
1195
+ s->dmac_status = REG_SD_IDST_RST;
1196
+ s->dmac_irq = REG_SD_IDIE_RST;
1197
+ s->card_threshold = REG_SD_THLDC_RST;
1198
+ s->startbit_detect = REG_SD_DSBD_RST;
1199
+ s->response_crc = REG_SD_RES_CRC_RST;
1200
+
1201
+ for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
1202
+ s->data_crc[i] = REG_SD_DATA_CRC_RST;
1203
+ }
1204
+
1205
+ s->status_crc = REG_SD_CRC_STA_RST;
1206
+}
1207
+
1208
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
1209
+{
1210
+ SDBusClass *sbc = SD_BUS_CLASS(klass);
1211
+
1212
+ sbc->set_inserted = allwinner_sdhost_set_inserted;
1213
+}
1214
+
1215
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
1216
+{
1217
+ DeviceClass *dc = DEVICE_CLASS(klass);
1218
+
1219
+ dc->reset = allwinner_sdhost_reset;
1220
+ dc->vmsd = &vmstate_allwinner_sdhost;
1221
+}
1222
+
1223
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
1224
+{
1225
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1226
+ sc->max_desc_size = 8 * KiB;
1227
+}
1228
+
1229
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
1230
+{
1231
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1232
+ sc->max_desc_size = 64 * KiB;
1233
+}
1234
+
1235
+static TypeInfo allwinner_sdhost_info = {
1236
+ .name = TYPE_AW_SDHOST,
1237
+ .parent = TYPE_SYS_BUS_DEVICE,
1238
+ .instance_init = allwinner_sdhost_init,
1239
+ .instance_size = sizeof(AwSdHostState),
1240
+ .class_init = allwinner_sdhost_class_init,
1241
+ .class_size = sizeof(AwSdHostClass),
1242
+ .abstract = true,
1243
+};
1244
+
1245
+static const TypeInfo allwinner_sdhost_sun4i_info = {
1246
+ .name = TYPE_AW_SDHOST_SUN4I,
1247
+ .parent = TYPE_AW_SDHOST,
1248
+ .class_init = allwinner_sdhost_sun4i_class_init,
1249
+};
1250
+
1251
+static const TypeInfo allwinner_sdhost_sun5i_info = {
1252
+ .name = TYPE_AW_SDHOST_SUN5I,
1253
+ .parent = TYPE_AW_SDHOST,
1254
+ .class_init = allwinner_sdhost_sun5i_class_init,
1255
+};
1256
+
1257
+static const TypeInfo allwinner_sdhost_bus_info = {
1258
+ .name = TYPE_AW_SDHOST_BUS,
1259
+ .parent = TYPE_SD_BUS,
1260
+ .instance_size = sizeof(SDBus),
1261
+ .class_init = allwinner_sdhost_bus_class_init,
1262
+};
1263
+
1264
+static void allwinner_sdhost_register_types(void)
1265
+{
1266
+ type_register_static(&allwinner_sdhost_info);
1267
+ type_register_static(&allwinner_sdhost_sun4i_info);
1268
+ type_register_static(&allwinner_sdhost_sun5i_info);
1269
+ type_register_static(&allwinner_sdhost_bus_info);
1270
+}
1271
+
1272
+type_init(allwinner_sdhost_register_types)
1273
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1274
index XXXXXXX..XXXXXXX 100644
1275
--- a/hw/arm/Kconfig
1276
+++ b/hw/arm/Kconfig
1277
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
1278
select UNIMP
1279
select USB_OHCI
1280
select USB_EHCI_SYSBUS
1281
+ select SD
1282
1283
config RASPI
1284
bool
1285
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
1286
index XXXXXXX..XXXXXXX 100644
1287
--- a/hw/sd/trace-events
1288
+++ b/hw/sd/trace-events
1289
@@ -XXX,XX +XXX,XX @@
1290
# See docs/devel/tracing.txt for syntax documentation.
1291
1292
+# allwinner-sdhost.c
1293
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
1294
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32
1295
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1296
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1297
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
1298
+
1299
# bcm2835_sdhost.c
1300
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1301
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1302
--
397
--
1303
2.20.1
398
2.20.1
1304
399
1305
400
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Aspeed SMC Controller can operate in different modes : Read, Fast
3
When TBI is enabled in a given regime, 56 bits of the address
4
Read, Write and User modes. When the User mode is configured, it
4
are significant and we need to clear out any other matching
5
selects automatically the SPI slave device until the CE_STOP_ACTIVE
5
virtual addresses with differing tags.
6
bit is set to 1. When any other modes are configured the device is
7
unselected. The HW logic handles the chip select automatically when
8
the flash is accessed through its AHB window.
9
6
10
When configuring the CEx Control Register, the User mode logic to
7
The other uses of tlb_flush_page (without mmuidx) in this file
11
select and unselect the slave is incorrect and data corruption can be
8
are only used by aarch32 mode.
12
seen on machines using two chips, witherspoon and romulus.
13
9
14
Rework the handler setting the CEx Control Register to fix this issue.
10
Fixes: 38d931687fa1
15
11
Reported-by: Jordan Frank <jordanfrank@fb.com>
16
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-id: 20200206112645.21275-3-clg@kaod.org
15
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
17
---
22
hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++----------------
18
target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++-------
23
hw/ssi/trace-events | 1 +
19
1 file changed, 39 insertions(+), 7 deletions(-)
24
2 files changed, 24 insertions(+), 16 deletions(-)
25
20
26
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
27
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/aspeed_smc.c
23
--- a/target/arm/helper.c
29
+++ b/hw/ssi/aspeed_smc.c
24
+++ b/target/arm/helper.c
30
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
25
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
26
#endif
27
28
static void switch_mode(CPUARMState *env, int mode);
29
+static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
30
31
static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
32
{
33
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbmask(CPUARMState *env)
31
}
34
}
32
}
35
}
33
36
34
-static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
37
+/* Return 56 if TBI is enabled, 64 otherwise. */
35
+static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
38
+static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
39
+ uint64_t addr)
40
+{
41
+ uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
42
+ int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
43
+ int select = extract64(addr, 55, 1);
44
+
45
+ return (tbi >> select) & 1 ? 56 : 64;
46
+}
47
+
48
+static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
49
+{
50
+ ARMMMUIdx mmu_idx;
51
+
52
+ /* Only the regime of the mmu_idx below is significant. */
53
+ if (arm_is_secure_below_el3(env)) {
54
+ mmu_idx = ARMMMUIdx_SE10_0;
55
+ } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
56
+ == (HCR_E2H | HCR_TGE)) {
57
+ mmu_idx = ARMMMUIdx_E20_0;
58
+ } else {
59
+ mmu_idx = ARMMMUIdx_E10_0;
60
+ }
61
+ return tlbbits_for_regime(env, mmu_idx, addr);
62
+}
63
+
64
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
65
uint64_t value)
36
{
66
{
37
- const AspeedSMCState *s = fl->controller;
67
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
38
+ AspeedSMCState *s = fl->controller;
68
CPUState *cs = env_cpu(env);
39
69
int mask = vae1_tlbmask(env);
40
- return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
70
uint64_t pageaddr = sextract64(value << 12, 0, 56);
41
+ trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
71
+ int bits = vae1_tlbbits(env, pageaddr);
42
+
72
43
+ qemu_set_irq(s->cs_lines[fl->id], unselect);
73
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
74
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
44
}
75
}
45
76
46
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
77
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
78
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
79
CPUState *cs = env_cpu(env);
80
int mask = vae1_tlbmask(env);
81
uint64_t pageaddr = sextract64(value << 12, 0, 56);
82
+ int bits = vae1_tlbbits(env, pageaddr);
83
84
if (tlb_force_broadcast(env)) {
85
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
86
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
87
} else {
88
- tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
89
+ tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
90
}
91
}
92
93
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
{
94
{
48
- AspeedSMCState *s = fl->controller;
95
CPUState *cs = env_cpu(env);
49
-
96
uint64_t pageaddr = sextract64(value << 12, 0, 56);
50
- s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
97
+ int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
51
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
98
52
+ aspeed_smc_flash_do_select(fl, false);
99
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
100
- ARMMMUIdxBit_E2);
101
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
102
+ ARMMMUIdxBit_E2, bits);
53
}
103
}
54
104
55
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
105
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
106
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
56
{
107
{
57
- AspeedSMCState *s = fl->controller;
108
CPUState *cs = env_cpu(env);
58
-
109
uint64_t pageaddr = sextract64(value << 12, 0, 56);
59
- s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
110
+ int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
60
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
111
61
+ aspeed_smc_flash_do_select(fl, true);
112
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
113
- ARMMMUIdxBit_SE3);
114
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
115
+ ARMMMUIdxBit_SE3, bits);
62
}
116
}
63
117
64
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
118
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
65
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = {
66
},
67
};
68
69
-static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
70
+static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
71
{
72
AspeedSMCState *s = fl->controller;
73
+ bool unselect;
74
75
- s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START;
76
+ /* User mode selects the CS, other modes unselect */
77
+ unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
78
79
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
80
+ /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
81
+ if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
82
+ value & CTRL_CE_STOP_ACTIVE) {
83
+ unselect = true;
84
+ }
85
+
86
+ s->regs[s->r_ctrl0 + fl->id] = value;
87
+
88
+ s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
89
+
90
+ aspeed_smc_flash_do_select(fl, unselect);
91
}
92
93
static void aspeed_smc_reset(DeviceState *d)
94
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
95
s->regs[addr] = value;
96
} else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
97
int cs = addr - s->r_ctrl0;
98
- s->regs[addr] = value;
99
- aspeed_smc_flash_update_cs(&s->flashes[cs]);
100
+ aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
101
} else if (addr >= R_SEG_ADDR0 &&
102
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
103
int cs = addr - R_SEG_ADDR0;
104
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/ssi/trace-events
107
+++ b/hw/ssi/trace-events
108
@@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int
109
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
110
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
111
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
112
+aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
113
--
119
--
114
2.20.1
120
2.20.1
115
121
116
122
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
3
This test exercises the various modes of the npcm7xx timer. In
4
based embedded computer with mainline support in both U-Boot
4
particular, it triggers the bug found by the fuzzer, as reported here:
5
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
5
6
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
6
https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg02992.html
7
various other I/O. This commit add support for the Xunlong
7
8
Orange Pi PC machine.
8
It also found several other bugs, especially related to interrupt
9
9
handling.
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
11
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
11
The test exercises all the timers in all the timer modules, which
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
expands to 180 test cases in total.
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
15
Acked-by: Igor Mammedov <imammedo@redhat.com>
15
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
16
Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com
16
Message-id: 20201008232154.94221-2-hskinnemoen@google.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
18
---
19
hw/arm/Makefile.objs | 2 +-
19
tests/qtest/npcm7xx_timer-test.c | 562 +++++++++++++++++++++++++++++++
20
hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
20
tests/qtest/meson.build | 1 +
21
MAINTAINERS | 1 +
21
2 files changed, 563 insertions(+)
22
3 files changed, 94 insertions(+), 1 deletion(-)
22
create mode 100644 tests/qtest/npcm7xx_timer-test.c
23
create mode 100644 hw/arm/orangepi.c
23
24
24
diff --git a/tests/qtest/npcm7xx_timer-test.c b/tests/qtest/npcm7xx_timer-test.c
25
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/Makefile.objs
28
+++ b/hw/arm/Makefile.objs
29
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
30
obj-$(CONFIG_OMAP) += omap1.o omap2.o
31
obj-$(CONFIG_STRONGARM) += strongarm.o
32
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
33
-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
38
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
39
new file mode 100644
25
new file mode 100644
40
index XXXXXXX..XXXXXXX
26
index XXXXXXX..XXXXXXX
41
--- /dev/null
27
--- /dev/null
42
+++ b/hw/arm/orangepi.c
28
+++ b/tests/qtest/npcm7xx_timer-test.c
43
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@
44
+/*
30
+/*
45
+ * Orange Pi emulation
31
+ * QTest testcase for the Nuvoton NPCM7xx Timer
46
+ *
32
+ *
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
33
+ * Copyright 2020 Google LLC
48
+ *
34
+ *
49
+ * This program is free software: you can redistribute it and/or modify
35
+ * This program is free software; you can redistribute it and/or modify it
50
+ * it under the terms of the GNU General Public License as published by
36
+ * under the terms of the GNU General Public License as published by the
51
+ * the Free Software Foundation, either version 2 of the License, or
37
+ * Free Software Foundation; either version 2 of the License, or
52
+ * (at your option) any later version.
38
+ * (at your option) any later version.
53
+ *
39
+ *
54
+ * This program is distributed in the hope that it will be useful,
40
+ * This program is distributed in the hope that it will be useful, but WITHOUT
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
57
+ * GNU General Public License for more details.
43
+ * for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
44
+ */
62
+
45
+
63
+#include "qemu/osdep.h"
46
+#include "qemu/osdep.h"
64
+#include "qemu/units.h"
47
+#include "qemu/timer.h"
65
+#include "exec/address-spaces.h"
48
+#include "libqtest-single.h"
66
+#include "qapi/error.h"
49
+
67
+#include "cpu.h"
50
+#define TIM_REF_HZ (25000000)
68
+#include "hw/sysbus.h"
51
+
69
+#include "hw/boards.h"
52
+/* Bits in TCSRx */
70
+#include "hw/qdev-properties.h"
53
+#define CEN BIT(30)
71
+#include "hw/arm/allwinner-h3.h"
54
+#define IE BIT(29)
72
+#include "sysemu/sysemu.h"
55
+#define MODE_ONESHOT (0 << 27)
73
+
56
+#define MODE_PERIODIC (1 << 27)
74
+static struct arm_boot_info orangepi_binfo = {
57
+#define CRST BIT(26)
75
+ .nb_cpus = AW_H3_NUM_CPUS,
58
+#define CACT BIT(25)
59
+#define PRESCALE(x) (x)
60
+
61
+/* Registers shared between all timers in a module. */
62
+#define TISR 0x18
63
+#define WTCR 0x1c
64
+# define WTCLK(x) ((x) << 10)
65
+
66
+/* Power-on default; used to re-initialize timers before each test. */
67
+#define TCSR_DEFAULT PRESCALE(5)
68
+
69
+/* Register offsets for a timer within a timer block. */
70
+typedef struct Timer {
71
+ unsigned int tcsr_offset;
72
+ unsigned int ticr_offset;
73
+ unsigned int tdr_offset;
74
+} Timer;
75
+
76
+/* A timer block containing 5 timers. */
77
+typedef struct TimerBlock {
78
+ int irq_base;
79
+ uint64_t base_addr;
80
+} TimerBlock;
81
+
82
+/* Testdata for testing a particular timer within a timer block. */
83
+typedef struct TestData {
84
+ const TimerBlock *tim;
85
+ const Timer *timer;
86
+} TestData;
87
+
88
+const TimerBlock timer_block[] = {
89
+ {
90
+ .irq_base = 32,
91
+ .base_addr = 0xf0008000,
92
+ },
93
+ {
94
+ .irq_base = 37,
95
+ .base_addr = 0xf0009000,
96
+ },
97
+ {
98
+ .irq_base = 42,
99
+ .base_addr = 0xf000a000,
100
+ },
76
+};
101
+};
77
+
102
+
78
+static void orangepi_init(MachineState *machine)
103
+const Timer timer[] = {
79
+{
104
+ {
80
+ AwH3State *h3;
105
+ .tcsr_offset = 0x00,
81
+
106
+ .ticr_offset = 0x08,
82
+ /* BIOS is not supported by this board */
107
+ .tdr_offset = 0x10,
83
+ if (bios_name) {
108
+ }, {
84
+ error_report("BIOS not supported for this machine");
109
+ .tcsr_offset = 0x04,
85
+ exit(1);
110
+ .ticr_offset = 0x0c,
111
+ .tdr_offset = 0x14,
112
+ }, {
113
+ .tcsr_offset = 0x20,
114
+ .ticr_offset = 0x28,
115
+ .tdr_offset = 0x30,
116
+ }, {
117
+ .tcsr_offset = 0x24,
118
+ .ticr_offset = 0x2c,
119
+ .tdr_offset = 0x34,
120
+ }, {
121
+ .tcsr_offset = 0x40,
122
+ .ticr_offset = 0x48,
123
+ .tdr_offset = 0x50,
124
+ },
125
+};
126
+
127
+/* Returns the index of the timer block. */
128
+static int tim_index(const TimerBlock *tim)
129
+{
130
+ ptrdiff_t diff = tim - timer_block;
131
+
132
+ g_assert(diff >= 0 && diff < ARRAY_SIZE(timer_block));
133
+
134
+ return diff;
135
+}
136
+
137
+/* Returns the index of a timer within a timer block. */
138
+static int timer_index(const Timer *t)
139
+{
140
+ ptrdiff_t diff = t - timer;
141
+
142
+ g_assert(diff >= 0 && diff < ARRAY_SIZE(timer));
143
+
144
+ return diff;
145
+}
146
+
147
+/* Returns the irq line for a given timer. */
148
+static int tim_timer_irq(const TestData *td)
149
+{
150
+ return td->tim->irq_base + timer_index(td->timer);
151
+}
152
+
153
+/* Register read/write accessors. */
154
+
155
+static void tim_write(const TestData *td,
156
+ unsigned int offset, uint32_t value)
157
+{
158
+ writel(td->tim->base_addr + offset, value);
159
+}
160
+
161
+static uint32_t tim_read(const TestData *td, unsigned int offset)
162
+{
163
+ return readl(td->tim->base_addr + offset);
164
+}
165
+
166
+static void tim_write_tcsr(const TestData *td, uint32_t value)
167
+{
168
+ tim_write(td, td->timer->tcsr_offset, value);
169
+}
170
+
171
+static uint32_t tim_read_tcsr(const TestData *td)
172
+{
173
+ return tim_read(td, td->timer->tcsr_offset);
174
+}
175
+
176
+static void tim_write_ticr(const TestData *td, uint32_t value)
177
+{
178
+ tim_write(td, td->timer->ticr_offset, value);
179
+}
180
+
181
+static uint32_t tim_read_ticr(const TestData *td)
182
+{
183
+ return tim_read(td, td->timer->ticr_offset);
184
+}
185
+
186
+static uint32_t tim_read_tdr(const TestData *td)
187
+{
188
+ return tim_read(td, td->timer->tdr_offset);
189
+}
190
+
191
+/* Returns the number of nanoseconds to count the given number of cycles. */
192
+static int64_t tim_calculate_step(uint32_t count, uint32_t prescale)
193
+{
194
+ return (1000000000LL / TIM_REF_HZ) * count * (prescale + 1);
195
+}
196
+
197
+/* Returns a bitmask corresponding to the timer under test. */
198
+static uint32_t tim_timer_bit(const TestData *td)
199
+{
200
+ return BIT(timer_index(td->timer));
201
+}
202
+
203
+/* Resets all timers to power-on defaults. */
204
+static void tim_reset(const TestData *td)
205
+{
206
+ int i, j;
207
+
208
+ /* Reset all the timers, in case a previous test left a timer running. */
209
+ for (i = 0; i < ARRAY_SIZE(timer_block); i++) {
210
+ for (j = 0; j < ARRAY_SIZE(timer); j++) {
211
+ writel(timer_block[i].base_addr + timer[j].tcsr_offset,
212
+ CRST | TCSR_DEFAULT);
213
+ }
214
+ writel(timer_block[i].base_addr + TISR, -1);
86
+ }
215
+ }
87
+
216
+}
88
+ /* This board has fixed size RAM */
217
+
89
+ if (machine->ram_size != 1 * GiB) {
218
+/* Verifies the reset state of a timer. */
90
+ error_report("This machine can only be used with 1GiB of RAM");
219
+static void test_reset(gconstpointer test_data)
91
+ exit(1);
220
+{
221
+ const TestData *td = test_data;
222
+
223
+ tim_reset(td);
224
+
225
+ g_assert_cmphex(tim_read_tcsr(td), ==, TCSR_DEFAULT);
226
+ g_assert_cmphex(tim_read_ticr(td), ==, 0);
227
+ g_assert_cmphex(tim_read_tdr(td), ==, 0);
228
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
229
+ g_assert_cmphex(tim_read(td, WTCR), ==, WTCLK(1));
230
+}
231
+
232
+/* Verifies that CRST wins if both CEN and CRST are set. */
233
+static void test_reset_overrides_enable(gconstpointer test_data)
234
+{
235
+ const TestData *td = test_data;
236
+
237
+ tim_reset(td);
238
+
239
+ /* CRST should force CEN to 0 */
240
+ tim_write_tcsr(td, CEN | CRST | TCSR_DEFAULT);
241
+
242
+ g_assert_cmphex(tim_read_tcsr(td), ==, TCSR_DEFAULT);
243
+ g_assert_cmphex(tim_read_tdr(td), ==, 0);
244
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
245
+}
246
+
247
+/* Verifies the behavior when CEN is set and then cleared. */
248
+static void test_oneshot_enable_then_disable(gconstpointer test_data)
249
+{
250
+ const TestData *td = test_data;
251
+
252
+ tim_reset(td);
253
+
254
+ /* Enable the timer with zero initial count, then disable it again. */
255
+ tim_write_tcsr(td, CEN | TCSR_DEFAULT);
256
+ tim_write_tcsr(td, TCSR_DEFAULT);
257
+
258
+ g_assert_cmphex(tim_read_tcsr(td), ==, TCSR_DEFAULT);
259
+ g_assert_cmphex(tim_read_tdr(td), ==, 0);
260
+ /* Timer interrupt flag should be set, but interrupts are not enabled. */
261
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
262
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
263
+}
264
+
265
+/* Verifies that a one-shot timer fires when expected with prescaler 5. */
266
+static void test_oneshot_ps5(gconstpointer test_data)
267
+{
268
+ const TestData *td = test_data;
269
+ unsigned int count = 256;
270
+ unsigned int ps = 5;
271
+
272
+ tim_reset(td);
273
+
274
+ tim_write_ticr(td, count);
275
+ tim_write_tcsr(td, CEN | PRESCALE(ps));
276
+ g_assert_cmphex(tim_read_tcsr(td), ==, CEN | CACT | PRESCALE(ps));
277
+ g_assert_cmpuint(tim_read_tdr(td), ==, count);
278
+
279
+ clock_step(tim_calculate_step(count, ps) - 1);
280
+
281
+ g_assert_cmphex(tim_read_tcsr(td), ==, CEN | CACT | PRESCALE(ps));
282
+ g_assert_cmpuint(tim_read_tdr(td), <, count);
283
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
284
+
285
+ clock_step(1);
286
+
287
+ g_assert_cmphex(tim_read_tcsr(td), ==, PRESCALE(ps));
288
+ g_assert_cmpuint(tim_read_tdr(td), ==, count);
289
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
290
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
291
+
292
+ /* Clear the interrupt flag. */
293
+ tim_write(td, TISR, tim_timer_bit(td));
294
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
295
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
296
+
297
+ /* Verify that this isn't a periodic timer. */
298
+ clock_step(2 * tim_calculate_step(count, ps));
299
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
300
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
301
+}
302
+
303
+/* Verifies that a one-shot timer fires when expected with prescaler 0. */
304
+static void test_oneshot_ps0(gconstpointer test_data)
305
+{
306
+ const TestData *td = test_data;
307
+ unsigned int count = 1;
308
+ unsigned int ps = 0;
309
+
310
+ tim_reset(td);
311
+
312
+ tim_write_ticr(td, count);
313
+ tim_write_tcsr(td, CEN | PRESCALE(ps));
314
+ g_assert_cmphex(tim_read_tcsr(td), ==, CEN | CACT | PRESCALE(ps));
315
+ g_assert_cmpuint(tim_read_tdr(td), ==, count);
316
+
317
+ clock_step(tim_calculate_step(count, ps) - 1);
318
+
319
+ g_assert_cmphex(tim_read_tcsr(td), ==, CEN | CACT | PRESCALE(ps));
320
+ g_assert_cmpuint(tim_read_tdr(td), <, count);
321
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
322
+
323
+ clock_step(1);
324
+
325
+ g_assert_cmphex(tim_read_tcsr(td), ==, PRESCALE(ps));
326
+ g_assert_cmpuint(tim_read_tdr(td), ==, count);
327
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
328
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
329
+}
330
+
331
+/* Verifies that a one-shot timer fires when expected with highest prescaler. */
332
+static void test_oneshot_ps255(gconstpointer test_data)
333
+{
334
+ const TestData *td = test_data;
335
+ unsigned int count = (1U << 24) - 1;
336
+ unsigned int ps = 255;
337
+
338
+ tim_reset(td);
339
+
340
+ tim_write_ticr(td, count);
341
+ tim_write_tcsr(td, CEN | PRESCALE(ps));
342
+ g_assert_cmphex(tim_read_tcsr(td), ==, CEN | CACT | PRESCALE(ps));
343
+ g_assert_cmpuint(tim_read_tdr(td), ==, count);
344
+
345
+ clock_step(tim_calculate_step(count, ps) - 1);
346
+
347
+ g_assert_cmphex(tim_read_tcsr(td), ==, CEN | CACT | PRESCALE(ps));
348
+ g_assert_cmpuint(tim_read_tdr(td), <, count);
349
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
350
+
351
+ clock_step(1);
352
+
353
+ g_assert_cmphex(tim_read_tcsr(td), ==, PRESCALE(ps));
354
+ g_assert_cmpuint(tim_read_tdr(td), ==, count);
355
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
356
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
357
+}
358
+
359
+/* Verifies that a oneshot timer fires an interrupt when expected. */
360
+static void test_oneshot_interrupt(gconstpointer test_data)
361
+{
362
+ const TestData *td = test_data;
363
+ unsigned int count = 256;
364
+ unsigned int ps = 7;
365
+
366
+ tim_reset(td);
367
+
368
+ tim_write_ticr(td, count);
369
+ tim_write_tcsr(td, IE | CEN | MODE_ONESHOT | PRESCALE(ps));
370
+
371
+ clock_step_next();
372
+
373
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
374
+ g_assert_true(qtest_get_irq(global_qtest, tim_timer_irq(td)));
375
+}
376
+
377
+/*
378
+ * Verifies that the timer can be paused and later resumed, and it still fires
379
+ * at the right moment.
380
+ */
381
+static void test_pause_resume(gconstpointer test_data)
382
+{
383
+ const TestData *td = test_data;
384
+ unsigned int count = 256;
385
+ unsigned int ps = 1;
386
+
387
+ tim_reset(td);
388
+
389
+ tim_write_ticr(td, count);
390
+ tim_write_tcsr(td, IE | CEN | MODE_ONESHOT | PRESCALE(ps));
391
+
392
+ /* Pause the timer halfway to expiration. */
393
+ clock_step(tim_calculate_step(count / 2, ps));
394
+ tim_write_tcsr(td, IE | MODE_ONESHOT | PRESCALE(ps));
395
+ g_assert_cmpuint(tim_read_tdr(td), ==, count / 2);
396
+
397
+ /* Counter should not advance during the following step. */
398
+ clock_step(2 * tim_calculate_step(count, ps));
399
+ g_assert_cmpuint(tim_read_tdr(td), ==, count / 2);
400
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
401
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
402
+
403
+ /* Resume the timer and run _almost_ to expiration. */
404
+ tim_write_tcsr(td, IE | CEN | MODE_ONESHOT | PRESCALE(ps));
405
+ clock_step(tim_calculate_step(count / 2, ps) - 1);
406
+ g_assert_cmpuint(tim_read_tdr(td), <, count);
407
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
408
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
409
+
410
+ /* Now, run the rest of the way and verify that the interrupt fires. */
411
+ clock_step(1);
412
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
413
+ g_assert_true(qtest_get_irq(global_qtest, tim_timer_irq(td)));
414
+}
415
+
416
+/* Verifies that the prescaler can be changed while the timer is runnin. */
417
+static void test_prescaler_change(gconstpointer test_data)
418
+{
419
+ const TestData *td = test_data;
420
+ unsigned int count = 256;
421
+ unsigned int ps = 5;
422
+
423
+ tim_reset(td);
424
+
425
+ tim_write_ticr(td, count);
426
+ tim_write_tcsr(td, CEN | MODE_ONESHOT | PRESCALE(ps));
427
+
428
+ /* Run a quarter of the way, and change the prescaler. */
429
+ clock_step(tim_calculate_step(count / 4, ps));
430
+ g_assert_cmpuint(tim_read_tdr(td), ==, 3 * count / 4);
431
+ ps = 2;
432
+ tim_write_tcsr(td, CEN | MODE_ONESHOT | PRESCALE(ps));
433
+ /* The counter must not change. */
434
+ g_assert_cmpuint(tim_read_tdr(td), ==, 3 * count / 4);
435
+
436
+ /* Run another quarter of the way, and change the prescaler again. */
437
+ clock_step(tim_calculate_step(count / 4, ps));
438
+ g_assert_cmpuint(tim_read_tdr(td), ==, count / 2);
439
+ ps = 8;
440
+ tim_write_tcsr(td, CEN | MODE_ONESHOT | PRESCALE(ps));
441
+ /* The counter must not change. */
442
+ g_assert_cmpuint(tim_read_tdr(td), ==, count / 2);
443
+
444
+ /* Run another quarter of the way, and change the prescaler again. */
445
+ clock_step(tim_calculate_step(count / 4, ps));
446
+ g_assert_cmpuint(tim_read_tdr(td), ==, count / 4);
447
+ ps = 0;
448
+ tim_write_tcsr(td, CEN | MODE_ONESHOT | PRESCALE(ps));
449
+ /* The counter must not change. */
450
+ g_assert_cmpuint(tim_read_tdr(td), ==, count / 4);
451
+
452
+ /* Run almost to expiration, and verify the timer didn't fire yet. */
453
+ clock_step(tim_calculate_step(count / 4, ps) - 1);
454
+ g_assert_cmpuint(tim_read_tdr(td), <, count);
455
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
456
+
457
+ /* Now, run the rest of the way and verify that the timer fires. */
458
+ clock_step(1);
459
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
460
+}
461
+
462
+/* Verifies that a periodic timer automatically restarts after expiration. */
463
+static void test_periodic_no_interrupt(gconstpointer test_data)
464
+{
465
+ const TestData *td = test_data;
466
+ unsigned int count = 2;
467
+ unsigned int ps = 3;
468
+ int i;
469
+
470
+ tim_reset(td);
471
+
472
+ tim_write_ticr(td, count);
473
+ tim_write_tcsr(td, CEN | MODE_PERIODIC | PRESCALE(ps));
474
+
475
+ for (i = 0; i < 4; i++) {
476
+ clock_step_next();
477
+
478
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
479
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
480
+
481
+ tim_write(td, TISR, tim_timer_bit(td));
482
+
483
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
484
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
92
+ }
485
+ }
93
+
486
+}
94
+ /* Only allow Cortex-A7 for this board */
487
+
95
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
488
+/* Verifies that a periodict timer fires an interrupt every time it expires. */
96
+ error_report("This board can only be used with cortex-a7 CPU");
489
+static void test_periodic_interrupt(gconstpointer test_data)
97
+ exit(1);
490
+{
491
+ const TestData *td = test_data;
492
+ unsigned int count = 65535;
493
+ unsigned int ps = 2;
494
+ int i;
495
+
496
+ tim_reset(td);
497
+
498
+ tim_write_ticr(td, count);
499
+ tim_write_tcsr(td, CEN | IE | MODE_PERIODIC | PRESCALE(ps));
500
+
501
+ for (i = 0; i < 4; i++) {
502
+ clock_step_next();
503
+
504
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
505
+ g_assert_true(qtest_get_irq(global_qtest, tim_timer_irq(td)));
506
+
507
+ tim_write(td, TISR, tim_timer_bit(td));
508
+
509
+ g_assert_cmphex(tim_read(td, TISR), ==, 0);
510
+ g_assert_false(qtest_get_irq(global_qtest, tim_timer_irq(td)));
98
+ }
511
+ }
99
+
512
+}
100
+ h3 = AW_H3(object_new(TYPE_AW_H3));
513
+
101
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(h3),
514
+/*
102
+ &error_abort);
515
+ * Verifies that the timer behaves correctly when disabled right before and
103
+ object_unref(OBJECT(h3));
516
+ * exactly when it's supposed to expire.
104
+
517
+ */
105
+ /* Setup timer properties */
518
+static void test_disable_on_expiration(gconstpointer test_data)
106
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
519
+{
107
+ &error_abort);
520
+ const TestData *td = test_data;
108
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
521
+ unsigned int count = 8;
109
+ &error_abort);
522
+ unsigned int ps = 255;
110
+
523
+
111
+ /* Mark H3 object realized */
524
+ tim_reset(td);
112
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
525
+
113
+
526
+ tim_write_ticr(td, count);
114
+ /* SDRAM */
527
+ tim_write_tcsr(td, CEN | MODE_ONESHOT | PRESCALE(ps));
115
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
528
+
116
+ machine->ram);
529
+ clock_step(tim_calculate_step(count, ps) - 1);
117
+
530
+
118
+ orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
531
+ tim_write_tcsr(td, MODE_ONESHOT | PRESCALE(ps));
119
+ orangepi_binfo.ram_size = machine->ram_size;
532
+ tim_write_tcsr(td, CEN | MODE_ONESHOT | PRESCALE(ps));
120
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
533
+ clock_step(1);
121
+}
534
+ tim_write_tcsr(td, MODE_ONESHOT | PRESCALE(ps));
122
+
535
+ g_assert_cmphex(tim_read(td, TISR), ==, tim_timer_bit(td));
123
+static void orangepi_machine_init(MachineClass *mc)
536
+}
124
+{
537
+
125
+ mc->desc = "Orange Pi PC";
538
+/*
126
+ mc->init = orangepi_init;
539
+ * Constructs a name that includes the timer block, timer and testcase name,
127
+ mc->min_cpus = AW_H3_NUM_CPUS;
540
+ * and adds the test to the test suite.
128
+ mc->max_cpus = AW_H3_NUM_CPUS;
541
+ */
129
+ mc->default_cpus = AW_H3_NUM_CPUS;
542
+static void tim_add_test(const char *name, const TestData *td, GTestDataFunc fn)
130
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
543
+{
131
+ mc->default_ram_size = 1 * GiB;
544
+ g_autofree char *full_name;
132
+ mc->default_ram_id = "orangepi.ram";
545
+
133
+}
546
+ full_name = g_strdup_printf("npcm7xx_timer/tim[%d]/timer[%d]/%s",
134
+
547
+ tim_index(td->tim), timer_index(td->timer),
135
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
548
+ name);
136
diff --git a/MAINTAINERS b/MAINTAINERS
549
+ qtest_add_data_func(full_name, td, fn);
550
+}
551
+
552
+/* Convenience macro for adding a test with a predictable function name. */
553
+#define add_test(name, td) tim_add_test(#name, td, test_##name)
554
+
555
+int main(int argc, char **argv)
556
+{
557
+ TestData testdata[ARRAY_SIZE(timer_block) * ARRAY_SIZE(timer)];
558
+ int ret;
559
+ int i, j;
560
+
561
+ g_test_init(&argc, &argv, NULL);
562
+ g_test_set_nonfatal_assertions();
563
+
564
+ for (i = 0; i < ARRAY_SIZE(timer_block); i++) {
565
+ for (j = 0; j < ARRAY_SIZE(timer); j++) {
566
+ TestData *td = &testdata[i * ARRAY_SIZE(timer) + j];
567
+ td->tim = &timer_block[i];
568
+ td->timer = &timer[j];
569
+
570
+ add_test(reset, td);
571
+ add_test(reset_overrides_enable, td);
572
+ add_test(oneshot_enable_then_disable, td);
573
+ add_test(oneshot_ps5, td);
574
+ add_test(oneshot_ps0, td);
575
+ add_test(oneshot_ps255, td);
576
+ add_test(oneshot_interrupt, td);
577
+ add_test(pause_resume, td);
578
+ add_test(prescaler_change, td);
579
+ add_test(periodic_no_interrupt, td);
580
+ add_test(periodic_interrupt, td);
581
+ add_test(disable_on_expiration, td);
582
+ }
583
+ }
584
+
585
+ qtest_start("-machine npcm750-evb");
586
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/a9mpcore/gic");
587
+ ret = g_test_run();
588
+ qtest_end();
589
+
590
+ return ret;
591
+}
592
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
137
index XXXXXXX..XXXXXXX 100644
593
index XXXXXXX..XXXXXXX 100644
138
--- a/MAINTAINERS
594
--- a/tests/qtest/meson.build
139
+++ b/MAINTAINERS
595
+++ b/tests/qtest/meson.build
140
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
596
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
141
S: Maintained
597
['arm-cpu-features',
142
F: hw/*/allwinner-h3*
598
'microbit-test',
143
F: include/hw/*/allwinner-h3*
599
'm25p80-test',
144
+F: hw/arm/orangepi.c
600
+ 'npcm7xx_timer-test',
145
601
'test-arm-mptimer',
146
ARM PrimeCell and CMSDK devices
602
'boot-serial-test',
147
M: Peter Maydell <peter.maydell@linaro.org>
603
'hexloader-test']
148
--
604
--
149
2.20.1
605
2.20.1
150
606
151
607
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
2
2
3
Mention 'max' value in the gic-version property description.
3
Current documentation is not too clear on the GETPC usage.
4
In particular, when used outside the top level helper function
5
it causes unexpected behavior.
4
6
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Signed-off-by: Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201015095147.1691-1-e.emanuelegiuseppe@gmail.com
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200311131618.7187-2-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/arm/virt.c | 3 ++-
12
docs/devel/loads-stores.rst | 8 +++++++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 7 insertions(+), 1 deletion(-)
13
14
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
17
--- a/docs/devel/loads-stores.rst
17
+++ b/hw/arm/virt.c
18
+++ b/docs/devel/loads-stores.rst
18
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ guest CPU state in case of a guest CPU exception. This is passed
19
virt_set_gic_version, NULL);
20
to ``cpu_restore_state()``. Therefore the value should either be 0,
20
object_property_set_description(obj, "gic-version",
21
to indicate that the guest CPU state is already synchronized, or
21
"Set GIC version. "
22
the result of ``GETPC()`` from the top level ``HELPER(foo)``
22
- "Valid values are 2, 3 and host", NULL);
23
-function, which is a return address into the generated code.
23
+ "Valid values are 2, 3, host and max",
24
+function, which is a return address into the generated code [#gpc]_.
24
+ NULL);
25
+
25
26
+.. [#gpc] Note that ``GETPC()`` should be used with great care: calling
26
vms->highmem_ecam = !vmc->no_highmem_ecam;
27
+ it in other functions that are *not* the top level
28
+ ``HELPER(foo)`` will cause unexpected behavior. Instead, the
29
+ value of ``GETPC()`` should be read from the helper and passed
30
+ if needed to the functions that the helper calls.
31
32
Function names follow the pattern:
27
33
28
--
34
--
29
2.20.1
35
2.20.1
30
36
31
37
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
Add trace events for GPU and CPU IRQs.
4
the serial output is working.
5
4
6
The kernel image and DeviceTree blob are built by the Armbian
5
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
project (based on Debian):
8
https://www.armbian.com/orange-pi-pc/
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ make check-venv
16
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
17
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
18
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
19
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
20
console: Uncompressing Linux... done, booting the kernel.
21
console: Booting Linux on physical CPU 0x0
22
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
23
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
24
console: CPU: div instructions available: patching division code
25
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
26
console: OF: fdt: Machine model: Xunlong Orange Pi PC
27
console: Memory policy: Data cache writealloc
28
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
29
console: cma: Failed to reserve 128 MiB
30
console: psci: probing for conduit method from DT.
31
console: psci: PSCIv0.2 detected in firmware.
32
console: psci: Using standard PSCI v0.2 function IDs
33
console: psci: Trusted OS migration not required
34
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
35
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
36
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
37
console: Kernel command line: printk.time=0 console=ttyS0,115200
38
PASS (8.59 s)
39
JOB TIME : 8.81 s
40
41
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
42
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
7
Message-id: 20201017180731.1165871-2-f4bug@amsat.org
43
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
44
Tested-by: Alex Bennée <alex.bennee@linaro.org>
45
Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com
46
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
9
---
49
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
10
hw/intc/bcm2835_ic.c | 4 +++-
50
1 file changed, 25 insertions(+)
11
hw/intc/trace-events | 4 ++++
12
2 files changed, 7 insertions(+), 1 deletion(-)
51
13
52
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
14
diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c
53
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
54
--- a/tests/acceptance/boot_linux_console.py
16
--- a/hw/intc/bcm2835_ic.c
55
+++ b/tests/acceptance/boot_linux_console.py
17
+++ b/hw/intc/bcm2835_ic.c
56
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
18
@@ -XXX,XX +XXX,XX @@
57
exec_command_and_wait_for_pattern(self, 'reboot',
19
#include "migration/vmstate.h"
58
'reboot: Restarting system')
20
#include "qemu/log.h"
59
21
#include "qemu/module.h"
60
+ def test_arm_orangepi(self):
22
+#include "trace.h"
61
+ """
23
62
+ :avocado: tags=arch:arm
24
#define GPU_IRQS 64
63
+ :avocado: tags=machine:orangepi-pc
25
#define ARM_IRQS 8
64
+ """
26
@@ -XXX,XX +XXX,XX @@ static void bcm2835_ic_update(BCM2835ICState *s)
65
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
27
set = (s->gpu_irq_level & s->gpu_irq_enable)
66
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
28
|| (s->arm_irq_level & s->arm_irq_enable);
67
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
29
qemu_set_irq(s->irq, set);
68
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
30
-
69
+ kernel_path = self.extract_from_deb(deb_path,
31
}
70
+ '/boot/vmlinuz-4.20.7-sunxi')
32
71
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
33
static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
72
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
34
@@ -XXX,XX +XXX,XX @@ static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
35
BCM2835ICState *s = opaque;
36
37
assert(irq >= 0 && irq < 64);
38
+ trace_bcm2835_ic_set_gpu_irq(irq, level);
39
s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
40
bcm2835_ic_update(s);
41
}
42
@@ -XXX,XX +XXX,XX @@ static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level)
43
BCM2835ICState *s = opaque;
44
45
assert(irq >= 0 && irq < 8);
46
+ trace_bcm2835_ic_set_cpu_irq(irq, level);
47
s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
48
bcm2835_ic_update(s);
49
}
50
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/intc/trace-events
53
+++ b/hw/intc/trace-events
54
@@ -XXX,XX +XXX,XX @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg wri
55
heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u: 0x%"PRIx64
56
heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u: 0x%"PRIx64
57
heathrow_set_irq(int num, int level) "set_irq: num=0x%02x level=%d"
73
+
58
+
74
+ self.vm.set_console()
59
+# bcm2835_ic.c
75
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
60
+bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d"
76
+ 'console=ttyS0,115200n8 '
61
+bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d"
77
+ 'earlycon=uart,mmio32,0x1c28000')
78
+ self.vm.add_args('-kernel', kernel_path,
79
+ '-dtb', dtb_path,
80
+ '-append', kernel_command_line)
81
+ self.vm.launch()
82
+ console_pattern = 'Kernel command line: %s' % kernel_command_line
83
+ self.wait_for_console_pattern(console_pattern)
84
+
85
def test_s390x_s390_ccw_virtio(self):
86
"""
87
:avocado: tags=arch:s390x
88
--
62
--
89
2.20.1
63
2.20.1
90
64
91
65
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
3
The IRQ values are defined few lines earlier, use them instead of
4
for non-volatile system date and time keeping. This commit adds a generic
4
the magic numbers.
5
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
6
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
7
The following RTC functionality and features are implemented:
8
5
9
* Year-Month-Day read/write
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
* Hour-Minute-Second read/write
7
Message-id: 20201017180731.1165871-3-f4bug@amsat.org
11
* General Purpose storage
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
13
The following boards are extended with the RTC device:
14
15
* Cubieboard (hw/arm/cubieboard.c)
16
* Orange Pi PC (hw/arm/orangepi.c)
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
10
---
23
hw/rtc/Makefile.objs | 1 +
11
hw/intc/bcm2836_control.c | 8 ++++----
24
include/hw/arm/allwinner-a10.h | 2 +
12
1 file changed, 4 insertions(+), 4 deletions(-)
25
include/hw/arm/allwinner-h3.h | 3 +
26
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
27
hw/arm/allwinner-a10.c | 8 +
28
hw/arm/allwinner-h3.c | 9 +-
29
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
30
hw/rtc/trace-events | 4 +
31
8 files changed, 571 insertions(+), 1 deletion(-)
32
create mode 100644 include/hw/rtc/allwinner-rtc.h
33
create mode 100644 hw/rtc/allwinner-rtc.c
34
13
35
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
14
diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c
36
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/rtc/Makefile.objs
16
--- a/hw/intc/bcm2836_control.c
38
+++ b/hw/rtc/Makefile.objs
17
+++ b/hw/intc/bcm2836_control.c
39
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
18
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq,
40
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
19
41
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o
20
static void bcm2836_control_set_local_irq0(void *opaque, int core, int level)
42
common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o
43
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o
44
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/arm/allwinner-a10.h
47
+++ b/include/hw/arm/allwinner-a10.h
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/ide/ahci.h"
50
#include "hw/usb/hcd-ohci.h"
51
#include "hw/usb/hcd-ehci.h"
52
+#include "hw/rtc/allwinner-rtc.h"
53
54
#include "target/arm/cpu.h"
55
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
57
AwEmacState emac;
58
AllwinnerAHCIState sata;
59
AwSdHostState mmc0;
60
+ AwRtcState rtc;
61
MemoryRegion sram_a;
62
EHCISysBusState ehci[AW_A10_NUM_USB];
63
OHCISysBusState ohci[AW_A10_NUM_USB];
64
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/include/hw/arm/allwinner-h3.h
67
+++ b/include/hw/arm/allwinner-h3.h
68
@@ -XXX,XX +XXX,XX @@
69
#include "hw/misc/allwinner-sid.h"
70
#include "hw/sd/allwinner-sdhost.h"
71
#include "hw/net/allwinner-sun8i-emac.h"
72
+#include "hw/rtc/allwinner-rtc.h"
73
#include "target/arm/cpu.h"
74
#include "sysemu/block-backend.h"
75
76
@@ -XXX,XX +XXX,XX @@ enum {
77
AW_H3_GIC_CPU,
78
AW_H3_GIC_HYP,
79
AW_H3_GIC_VCPU,
80
+ AW_H3_RTC,
81
AW_H3_CPUCFG,
82
AW_H3_SDRAM
83
};
84
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
85
AwSidState sid;
86
AwSdHostState mmc0;
87
AwSun8iEmacState emac;
88
+ AwRtcState rtc;
89
GICState gic;
90
MemoryRegion sram_a1;
91
MemoryRegion sram_a2;
92
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
93
new file mode 100644
94
index XXXXXXX..XXXXXXX
95
--- /dev/null
96
+++ b/include/hw/rtc/allwinner-rtc.h
97
@@ -XXX,XX +XXX,XX @@
98
+/*
99
+ * Allwinner Real Time Clock emulation
100
+ *
101
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
102
+ *
103
+ * This program is free software: you can redistribute it and/or modify
104
+ * it under the terms of the GNU General Public License as published by
105
+ * the Free Software Foundation, either version 2 of the License, or
106
+ * (at your option) any later version.
107
+ *
108
+ * This program is distributed in the hope that it will be useful,
109
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
110
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
111
+ * GNU General Public License for more details.
112
+ *
113
+ * You should have received a copy of the GNU General Public License
114
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
115
+ */
116
+
117
+#ifndef HW_MISC_ALLWINNER_RTC_H
118
+#define HW_MISC_ALLWINNER_RTC_H
119
+
120
+#include "qom/object.h"
121
+#include "hw/sysbus.h"
122
+
123
+/**
124
+ * Constants
125
+ * @{
126
+ */
127
+
128
+/** Highest register address used by RTC device */
129
+#define AW_RTC_REGS_MAXADDR (0x200)
130
+
131
+/** Total number of known registers */
132
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
133
+
134
+/** @} */
135
+
136
+/**
137
+ * Object model types
138
+ * @{
139
+ */
140
+
141
+/** Generic Allwinner RTC device (abstract) */
142
+#define TYPE_AW_RTC "allwinner-rtc"
143
+
144
+/** Allwinner RTC sun4i family (A10, A12) */
145
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
146
+
147
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
148
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
149
+
150
+/** Allwinner RTC sun7i family (A20) */
151
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
152
+
153
+/** @} */
154
+
155
+/**
156
+ * Object model macros
157
+ * @{
158
+ */
159
+
160
+#define AW_RTC(obj) \
161
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
162
+#define AW_RTC_CLASS(klass) \
163
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
164
+#define AW_RTC_GET_CLASS(obj) \
165
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
166
+
167
+/** @} */
168
+
169
+/**
170
+ * Allwinner RTC per-object instance state.
171
+ */
172
+typedef struct AwRtcState {
173
+ /*< private >*/
174
+ SysBusDevice parent_obj;
175
+ /*< public >*/
176
+
177
+ /**
178
+ * Actual year represented by the device when year counter is zero
179
+ *
180
+ * Can be overridden by the user using the corresponding 'base-year'
181
+ * property. The base year used by the target OS driver can vary, for
182
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
183
+ */
184
+ int base_year;
185
+
186
+ /** Maps I/O registers in physical memory */
187
+ MemoryRegion iomem;
188
+
189
+ /** Array of hardware registers */
190
+ uint32_t regs[AW_RTC_REGS_NUM];
191
+
192
+} AwRtcState;
193
+
194
+/**
195
+ * Allwinner RTC class-level struct.
196
+ *
197
+ * This struct is filled by each sunxi device specific code
198
+ * such that the generic code can use this struct to support
199
+ * all devices.
200
+ */
201
+typedef struct AwRtcClass {
202
+ /*< private >*/
203
+ SysBusDeviceClass parent_class;
204
+ /*< public >*/
205
+
206
+ /** Defines device specific register map */
207
+ const uint8_t *regmap;
208
+
209
+ /** Size of the regmap in bytes */
210
+ size_t regmap_size;
211
+
212
+ /**
213
+ * Read device specific register
214
+ *
215
+ * @offset: register offset to read
216
+ * @return true if register read successful, false otherwise
217
+ */
218
+ bool (*read)(AwRtcState *s, uint32_t offset);
219
+
220
+ /**
221
+ * Write device specific register
222
+ *
223
+ * @offset: register offset to write
224
+ * @data: value to set in register
225
+ * @return true if register write successful, false otherwise
226
+ */
227
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
228
+
229
+} AwRtcClass;
230
+
231
+#endif /* HW_MISC_ALLWINNER_RTC_H */
232
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/arm/allwinner-a10.c
235
+++ b/hw/arm/allwinner-a10.c
236
@@ -XXX,XX +XXX,XX @@
237
#define AW_A10_EHCI_BASE 0x01c14000
238
#define AW_A10_OHCI_BASE 0x01c14400
239
#define AW_A10_SATA_BASE 0x01c18000
240
+#define AW_A10_RTC_BASE 0x01c20d00
241
242
static void aw_a10_init(Object *obj)
243
{
21
{
244
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
22
- bcm2836_control_set_local_irq(opaque, core, 0, level);
245
23
+ bcm2836_control_set_local_irq(opaque, core, IRQ_CNTPSIRQ, level);
246
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
247
TYPE_AW_SDHOST_SUN4I);
248
+
249
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
250
+ TYPE_AW_RTC_SUN4I);
251
}
24
}
252
25
253
static void aw_a10_realize(DeviceState *dev, Error **errp)
26
static void bcm2836_control_set_local_irq1(void *opaque, int core, int level)
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
27
{
255
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
28
- bcm2836_control_set_local_irq(opaque, core, 1, level);
256
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
29
+ bcm2836_control_set_local_irq(opaque, core, IRQ_CNTPNSIRQ, level);
257
"sd-bus", &error_abort);
258
+
259
+ /* RTC */
260
+ qdev_init_nofail(DEVICE(&s->rtc));
261
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
262
}
30
}
263
31
264
static void aw_a10_class_init(ObjectClass *oc, void *data)
32
static void bcm2836_control_set_local_irq2(void *opaque, int core, int level)
265
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
33
{
266
index XXXXXXX..XXXXXXX 100644
34
- bcm2836_control_set_local_irq(opaque, core, 2, level);
267
--- a/hw/arm/allwinner-h3.c
35
+ bcm2836_control_set_local_irq(opaque, core, IRQ_CNTHPIRQ, level);
268
+++ b/hw/arm/allwinner-h3.c
269
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
270
[AW_H3_GIC_CPU] = 0x01c82000,
271
[AW_H3_GIC_HYP] = 0x01c84000,
272
[AW_H3_GIC_VCPU] = 0x01c86000,
273
+ [AW_H3_RTC] = 0x01f00000,
274
[AW_H3_CPUCFG] = 0x01f01c00,
275
[AW_H3_SDRAM] = 0x40000000
276
};
277
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
278
{ "csi", 0x01cb0000, 320 * KiB },
279
{ "tve", 0x01e00000, 64 * KiB },
280
{ "hdmi", 0x01ee0000, 128 * KiB },
281
- { "rtc", 0x01f00000, 1 * KiB },
282
{ "r_timer", 0x01f00800, 1 * KiB },
283
{ "r_intc", 0x01f00c00, 1 * KiB },
284
{ "r_wdog", 0x01f01000, 1 * KiB },
285
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
286
"ram-addr", &error_abort);
287
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
288
"ram-size", &error_abort);
289
+
290
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
291
+ TYPE_AW_RTC_SUN6I);
292
}
36
}
293
37
294
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
38
static void bcm2836_control_set_local_irq3(void *opaque, int core, int level)
295
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
39
{
296
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
40
- bcm2836_control_set_local_irq(opaque, core, 3, level);
297
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
41
+ bcm2836_control_set_local_irq(opaque, core, IRQ_CNTVIRQ, level);
298
42
}
299
+ /* RTC */
43
300
+ qdev_init_nofail(DEVICE(&s->rtc));
44
static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level)
301
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
302
+
303
/* Unimplemented devices */
304
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
305
create_unimplemented_device(unimplemented[i].device_name,
306
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
307
new file mode 100644
308
index XXXXXXX..XXXXXXX
309
--- /dev/null
310
+++ b/hw/rtc/allwinner-rtc.c
311
@@ -XXX,XX +XXX,XX @@
312
+/*
313
+ * Allwinner Real Time Clock emulation
314
+ *
315
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
316
+ *
317
+ * This program is free software: you can redistribute it and/or modify
318
+ * it under the terms of the GNU General Public License as published by
319
+ * the Free Software Foundation, either version 2 of the License, or
320
+ * (at your option) any later version.
321
+ *
322
+ * This program is distributed in the hope that it will be useful,
323
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
324
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
325
+ * GNU General Public License for more details.
326
+ *
327
+ * You should have received a copy of the GNU General Public License
328
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
329
+ */
330
+
331
+#include "qemu/osdep.h"
332
+#include "qemu/units.h"
333
+#include "hw/sysbus.h"
334
+#include "migration/vmstate.h"
335
+#include "qemu/log.h"
336
+#include "qemu/module.h"
337
+#include "qemu-common.h"
338
+#include "hw/qdev-properties.h"
339
+#include "hw/rtc/allwinner-rtc.h"
340
+#include "trace.h"
341
+
342
+/* RTC registers */
343
+enum {
344
+ REG_LOSC = 1, /* Low Oscillator Control */
345
+ REG_YYMMDD, /* RTC Year-Month-Day */
346
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
347
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
348
+ REG_ALARM1_EN, /* Alarm1 Enable */
349
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
350
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
351
+ REG_GP0, /* General Purpose Register 0 */
352
+ REG_GP1, /* General Purpose Register 1 */
353
+ REG_GP2, /* General Purpose Register 2 */
354
+ REG_GP3, /* General Purpose Register 3 */
355
+
356
+ /* sun4i registers */
357
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
358
+ REG_CPUCFG, /* CPU Configuration Register */
359
+
360
+ /* sun6i registers */
361
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
362
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
363
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
364
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
365
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
366
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
367
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
368
+ REG_ALARM_CONFIG, /* Alarm Config */
369
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
370
+ REG_GP4, /* General Purpose Register 4 */
371
+ REG_GP5, /* General Purpose Register 5 */
372
+ REG_GP6, /* General Purpose Register 6 */
373
+ REG_GP7, /* General Purpose Register 7 */
374
+ REG_RTC_DBG, /* RTC Debug Register */
375
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
376
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
377
+ REG_IC_CHARA, /* IC Characteristics Register */
378
+};
379
+
380
+/* RTC register flags */
381
+enum {
382
+ REG_LOSC_YMD = (1 << 7),
383
+ REG_LOSC_HMS = (1 << 8),
384
+};
385
+
386
+/* RTC sun4i register map (offset to name) */
387
+const uint8_t allwinner_rtc_sun4i_regmap[] = {
388
+ [0x0000] = REG_LOSC,
389
+ [0x0004] = REG_YYMMDD,
390
+ [0x0008] = REG_HHMMSS,
391
+ [0x000C] = REG_ALARM1_DDHHMMSS,
392
+ [0x0010] = REG_ALARM1_WKHHMMSS,
393
+ [0x0014] = REG_ALARM1_EN,
394
+ [0x0018] = REG_ALARM1_IRQ_EN,
395
+ [0x001C] = REG_ALARM1_IRQ_STA,
396
+ [0x0020] = REG_GP0,
397
+ [0x0024] = REG_GP1,
398
+ [0x0028] = REG_GP2,
399
+ [0x002C] = REG_GP3,
400
+ [0x003C] = REG_CPUCFG,
401
+};
402
+
403
+/* RTC sun6i register map (offset to name) */
404
+const uint8_t allwinner_rtc_sun6i_regmap[] = {
405
+ [0x0000] = REG_LOSC,
406
+ [0x0004] = REG_LOSC_AUTOSTA,
407
+ [0x0008] = REG_INT_OSC_PRE,
408
+ [0x0010] = REG_YYMMDD,
409
+ [0x0014] = REG_HHMMSS,
410
+ [0x0020] = REG_ALARM0_COUNTER,
411
+ [0x0024] = REG_ALARM0_CUR_VLU,
412
+ [0x0028] = REG_ALARM0_ENABLE,
413
+ [0x002C] = REG_ALARM0_IRQ_EN,
414
+ [0x0030] = REG_ALARM0_IRQ_STA,
415
+ [0x0040] = REG_ALARM1_WKHHMMSS,
416
+ [0x0044] = REG_ALARM1_EN,
417
+ [0x0048] = REG_ALARM1_IRQ_EN,
418
+ [0x004C] = REG_ALARM1_IRQ_STA,
419
+ [0x0050] = REG_ALARM_CONFIG,
420
+ [0x0060] = REG_LOSC_OUT_GATING,
421
+ [0x0100] = REG_GP0,
422
+ [0x0104] = REG_GP1,
423
+ [0x0108] = REG_GP2,
424
+ [0x010C] = REG_GP3,
425
+ [0x0110] = REG_GP4,
426
+ [0x0114] = REG_GP5,
427
+ [0x0118] = REG_GP6,
428
+ [0x011C] = REG_GP7,
429
+ [0x0170] = REG_RTC_DBG,
430
+ [0x0180] = REG_GPL_HOLD_OUT,
431
+ [0x0190] = REG_VDD_RTC,
432
+ [0x01F0] = REG_IC_CHARA,
433
+};
434
+
435
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
436
+{
437
+ /* no sun4i specific registers currently implemented */
438
+ return false;
439
+}
440
+
441
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
442
+ uint32_t data)
443
+{
444
+ /* no sun4i specific registers currently implemented */
445
+ return false;
446
+}
447
+
448
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
449
+{
450
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
451
+
452
+ switch (c->regmap[offset]) {
453
+ case REG_GP4: /* General Purpose Register 4 */
454
+ case REG_GP5: /* General Purpose Register 5 */
455
+ case REG_GP6: /* General Purpose Register 6 */
456
+ case REG_GP7: /* General Purpose Register 7 */
457
+ return true;
458
+ default:
459
+ break;
460
+ }
461
+ return false;
462
+}
463
+
464
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
465
+ uint32_t data)
466
+{
467
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
468
+
469
+ switch (c->regmap[offset]) {
470
+ case REG_GP4: /* General Purpose Register 4 */
471
+ case REG_GP5: /* General Purpose Register 5 */
472
+ case REG_GP6: /* General Purpose Register 6 */
473
+ case REG_GP7: /* General Purpose Register 7 */
474
+ return true;
475
+ default:
476
+ break;
477
+ }
478
+ return false;
479
+}
480
+
481
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
482
+ unsigned size)
483
+{
484
+ AwRtcState *s = AW_RTC(opaque);
485
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
486
+ uint64_t val = 0;
487
+
488
+ if (offset >= c->regmap_size) {
489
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
490
+ __func__, (uint32_t)offset);
491
+ return 0;
492
+ }
493
+
494
+ if (!c->regmap[offset]) {
495
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
496
+ __func__, (uint32_t)offset);
497
+ return 0;
498
+ }
499
+
500
+ switch (c->regmap[offset]) {
501
+ case REG_LOSC: /* Low Oscillator Control */
502
+ val = s->regs[REG_LOSC];
503
+ s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
504
+ break;
505
+ case REG_YYMMDD: /* RTC Year-Month-Day */
506
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
507
+ case REG_GP0: /* General Purpose Register 0 */
508
+ case REG_GP1: /* General Purpose Register 1 */
509
+ case REG_GP2: /* General Purpose Register 2 */
510
+ case REG_GP3: /* General Purpose Register 3 */
511
+ val = s->regs[c->regmap[offset]];
512
+ break;
513
+ default:
514
+ if (!c->read(s, offset)) {
515
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
516
+ __func__, (uint32_t)offset);
517
+ }
518
+ val = s->regs[c->regmap[offset]];
519
+ break;
520
+ }
521
+
522
+ trace_allwinner_rtc_read(offset, val);
523
+ return val;
524
+}
525
+
526
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
527
+ uint64_t val, unsigned size)
528
+{
529
+ AwRtcState *s = AW_RTC(opaque);
530
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
531
+
532
+ if (offset >= c->regmap_size) {
533
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
534
+ __func__, (uint32_t)offset);
535
+ return;
536
+ }
537
+
538
+ if (!c->regmap[offset]) {
539
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
540
+ __func__, (uint32_t)offset);
541
+ return;
542
+ }
543
+
544
+ trace_allwinner_rtc_write(offset, val);
545
+
546
+ switch (c->regmap[offset]) {
547
+ case REG_YYMMDD: /* RTC Year-Month-Day */
548
+ s->regs[REG_YYMMDD] = val;
549
+ s->regs[REG_LOSC] |= REG_LOSC_YMD;
550
+ break;
551
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
552
+ s->regs[REG_HHMMSS] = val;
553
+ s->regs[REG_LOSC] |= REG_LOSC_HMS;
554
+ break;
555
+ case REG_GP0: /* General Purpose Register 0 */
556
+ case REG_GP1: /* General Purpose Register 1 */
557
+ case REG_GP2: /* General Purpose Register 2 */
558
+ case REG_GP3: /* General Purpose Register 3 */
559
+ s->regs[c->regmap[offset]] = val;
560
+ break;
561
+ default:
562
+ if (!c->write(s, offset, val)) {
563
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
564
+ __func__, (uint32_t)offset);
565
+ }
566
+ break;
567
+ }
568
+}
569
+
570
+static const MemoryRegionOps allwinner_rtc_ops = {
571
+ .read = allwinner_rtc_read,
572
+ .write = allwinner_rtc_write,
573
+ .endianness = DEVICE_NATIVE_ENDIAN,
574
+ .valid = {
575
+ .min_access_size = 4,
576
+ .max_access_size = 4,
577
+ },
578
+ .impl.min_access_size = 4,
579
+};
580
+
581
+static void allwinner_rtc_reset(DeviceState *dev)
582
+{
583
+ AwRtcState *s = AW_RTC(dev);
584
+ struct tm now;
585
+
586
+ /* Clear registers */
587
+ memset(s->regs, 0, sizeof(s->regs));
588
+
589
+ /* Get current datetime */
590
+ qemu_get_timedate(&now, 0);
591
+
592
+ /* Set RTC with current datetime */
593
+ if (s->base_year > 1900) {
594
+ s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
595
+ ((now.tm_mon + 1) << 8) |
596
+ now.tm_mday;
597
+ s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
598
+ (now.tm_hour << 16) |
599
+ (now.tm_min << 8) |
600
+ now.tm_sec;
601
+ }
602
+}
603
+
604
+static void allwinner_rtc_init(Object *obj)
605
+{
606
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
607
+ AwRtcState *s = AW_RTC(obj);
608
+
609
+ /* Memory mapping */
610
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
611
+ TYPE_AW_RTC, 1 * KiB);
612
+ sysbus_init_mmio(sbd, &s->iomem);
613
+}
614
+
615
+static const VMStateDescription allwinner_rtc_vmstate = {
616
+ .name = "allwinner-rtc",
617
+ .version_id = 1,
618
+ .minimum_version_id = 1,
619
+ .fields = (VMStateField[]) {
620
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
621
+ VMSTATE_END_OF_LIST()
622
+ }
623
+};
624
+
625
+static Property allwinner_rtc_properties[] = {
626
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
627
+ DEFINE_PROP_END_OF_LIST(),
628
+};
629
+
630
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
631
+{
632
+ DeviceClass *dc = DEVICE_CLASS(klass);
633
+
634
+ dc->reset = allwinner_rtc_reset;
635
+ dc->vmsd = &allwinner_rtc_vmstate;
636
+ device_class_set_props(dc, allwinner_rtc_properties);
637
+}
638
+
639
+static void allwinner_rtc_sun4i_init(Object *obj)
640
+{
641
+ AwRtcState *s = AW_RTC(obj);
642
+ s->base_year = 2010;
643
+}
644
+
645
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
646
+{
647
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
648
+
649
+ arc->regmap = allwinner_rtc_sun4i_regmap;
650
+ arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
651
+ arc->read = allwinner_rtc_sun4i_read;
652
+ arc->write = allwinner_rtc_sun4i_write;
653
+}
654
+
655
+static void allwinner_rtc_sun6i_init(Object *obj)
656
+{
657
+ AwRtcState *s = AW_RTC(obj);
658
+ s->base_year = 1970;
659
+}
660
+
661
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
662
+{
663
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
664
+
665
+ arc->regmap = allwinner_rtc_sun6i_regmap;
666
+ arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
667
+ arc->read = allwinner_rtc_sun6i_read;
668
+ arc->write = allwinner_rtc_sun6i_write;
669
+}
670
+
671
+static void allwinner_rtc_sun7i_init(Object *obj)
672
+{
673
+ AwRtcState *s = AW_RTC(obj);
674
+ s->base_year = 1970;
675
+}
676
+
677
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
678
+{
679
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
680
+ allwinner_rtc_sun4i_class_init(klass, arc);
681
+}
682
+
683
+static const TypeInfo allwinner_rtc_info = {
684
+ .name = TYPE_AW_RTC,
685
+ .parent = TYPE_SYS_BUS_DEVICE,
686
+ .instance_init = allwinner_rtc_init,
687
+ .instance_size = sizeof(AwRtcState),
688
+ .class_init = allwinner_rtc_class_init,
689
+ .class_size = sizeof(AwRtcClass),
690
+ .abstract = true,
691
+};
692
+
693
+static const TypeInfo allwinner_rtc_sun4i_info = {
694
+ .name = TYPE_AW_RTC_SUN4I,
695
+ .parent = TYPE_AW_RTC,
696
+ .class_init = allwinner_rtc_sun4i_class_init,
697
+ .instance_init = allwinner_rtc_sun4i_init,
698
+};
699
+
700
+static const TypeInfo allwinner_rtc_sun6i_info = {
701
+ .name = TYPE_AW_RTC_SUN6I,
702
+ .parent = TYPE_AW_RTC,
703
+ .class_init = allwinner_rtc_sun6i_class_init,
704
+ .instance_init = allwinner_rtc_sun6i_init,
705
+};
706
+
707
+static const TypeInfo allwinner_rtc_sun7i_info = {
708
+ .name = TYPE_AW_RTC_SUN7I,
709
+ .parent = TYPE_AW_RTC,
710
+ .class_init = allwinner_rtc_sun7i_class_init,
711
+ .instance_init = allwinner_rtc_sun7i_init,
712
+};
713
+
714
+static void allwinner_rtc_register(void)
715
+{
716
+ type_register_static(&allwinner_rtc_info);
717
+ type_register_static(&allwinner_rtc_sun4i_info);
718
+ type_register_static(&allwinner_rtc_sun6i_info);
719
+ type_register_static(&allwinner_rtc_sun7i_info);
720
+}
721
+
722
+type_init(allwinner_rtc_register)
723
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
724
index XXXXXXX..XXXXXXX 100644
725
--- a/hw/rtc/trace-events
726
+++ b/hw/rtc/trace-events
727
@@ -XXX,XX +XXX,XX @@
728
# See docs/devel/tracing.txt for syntax documentation.
729
730
+# allwinner-rtc.c
731
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
732
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
733
+
734
# sun4v-rtc.c
735
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
736
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
737
--
45
--
738
2.20.1
46
2.20.1
739
47
740
48
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
At the moment if the end-user does not specify the gic-version along
3
We already have the full ARMMMUIdx as computed from the
4
with KVM acceleration, v2 is set by default. However most of the
4
function parameter.
5
systems now have GICv3 and sometimes they do not support GICv2
6
compatibility.
7
5
8
This patch keeps the default v2 selection in all cases except
6
For the purpose of regime_has_2_ranges, we can ignore any
9
in the KVM accelerated mode when either
7
difference between AccType_Normal and AccType_Unpriv, which
10
- the host does not support GICv2 in-kernel emulation or
8
would be the only difference between the passed mmu_idx
11
- number of VCPUS exceeds 8.
9
and arm_mmu_idx_el.
12
10
13
Those cases did not work anyway so we do not break any compatibility.
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Now we get v3 selected in such a case.
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
13
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
14
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
17
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
15
Message-id: 20201008162155.161886-2-richard.henderson@linaro.org
18
Reviewed-by: Andrew Jones <drjones@redhat.com>
19
Message-id: 20200311131618.7187-7-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
17
---
22
hw/arm/virt.c | 17 ++++++++++++++++-
18
target/arm/mte_helper.c | 3 +--
23
1 file changed, 16 insertions(+), 1 deletion(-)
19
1 file changed, 1 insertion(+), 2 deletions(-)
24
20
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
26
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
23
--- a/target/arm/mte_helper.c
28
+++ b/hw/arm/virt.c
24
+++ b/target/arm/mte_helper.c
29
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
25
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
30
*/
26
31
static void finalize_gic_version(VirtMachineState *vms)
27
case 2:
32
{
28
/* Tag check fail causes asynchronous flag set. */
33
+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
29
- mmu_idx = arm_mmu_idx_el(env, el);
34
+
30
- if (regime_has_2_ranges(mmu_idx)) {
35
if (kvm_enabled()) {
31
+ if (regime_has_2_ranges(arm_mmu_idx)) {
36
int probe_bitmap;
32
select = extract64(dirty_ptr, 55, 1);
37
33
} else {
38
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
34
select = 0;
39
}
40
return;
41
case VIRT_GIC_VERSION_NOSEL:
42
- vms->gic_version = VIRT_GIC_VERSION_2;
43
+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
44
+ vms->gic_version = VIRT_GIC_VERSION_2;
45
+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
46
+ /*
47
+ * in case the host does not support v2 in-kernel emulation or
48
+ * the end-user requested more than 8 VCPUs we now default
49
+ * to v3. In any case defaulting to v2 would be broken.
50
+ */
51
+ vms->gic_version = VIRT_GIC_VERSION_3;
52
+ } else if (max_cpus > GIC_NCPU) {
53
+ error_report("host only supports in-kernel GICv2 emulation "
54
+ "but more than 8 vcpus are requested");
55
+ exit(1);
56
+ }
57
break;
58
case VIRT_GIC_VERSION_2:
59
case VIRT_GIC_VERSION_3:
60
--
35
--
61
2.20.1
36
2.20.1
62
37
63
38
diff view generated by jsdifflib
1
From: Beata Michalska <beata.michalska@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
3
The reporting in AArch64.TagCheckFail only depends on PSTATE.EL,
4
As such this should be the last step of sync to avoid potential overwriting
4
and not the AccType of the operation. There are two guest
5
of whatever changes KVM might have done.
5
visible problems that affect LDTR and STTR because of this:
6
6
7
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
7
(1) Selecting TCF0 vs TCF1 to decide on reporting,
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
(2) Report "data abort same el" not "data abort lower el".
9
Message-id: 20200312003401.29017-2-beata.michalska@linaro.org
9
10
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
13
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
14
Message-id: 20201008162155.161886-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
target/arm/kvm32.c | 15 ++++++++++-----
17
target/arm/mte_helper.c | 10 +++-------
13
target/arm/kvm64.c | 15 ++++++++++-----
18
1 file changed, 3 insertions(+), 7 deletions(-)
14
2 files changed, 20 insertions(+), 10 deletions(-)
15
19
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
20
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
22
--- a/target/arm/mte_helper.c
19
+++ b/target/arm/kvm32.c
23
+++ b/target/arm/mte_helper.c
20
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
24
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
21
return ret;
25
reg_el = regime_el(env, arm_mmu_idx);
26
sctlr = env->cp15.sctlr_el[reg_el];
27
28
- switch (arm_mmu_idx) {
29
- case ARMMMUIdx_E10_0:
30
- case ARMMMUIdx_E20_0:
31
- el = 0;
32
+ el = arm_current_el(env);
33
+ if (el == 0) {
34
tcf = extract64(sctlr, 38, 2);
35
- break;
36
- default:
37
- el = reg_el;
38
+ } else {
39
tcf = extract64(sctlr, 40, 2);
22
}
40
}
23
41
24
- ret = kvm_put_vcpu_events(cpu);
25
- if (ret) {
26
- return ret;
27
- }
28
-
29
write_cpustate_to_list(cpu, true);
30
31
if (!write_list_to_kvmstate(cpu, level)) {
32
return EINVAL;
33
}
34
35
+ /*
36
+ * Setting VCPU events should be triggered after syncing the registers
37
+ * to avoid overwriting potential changes made by KVM upon calling
38
+ * KVM_SET_VCPU_EVENTS ioctl
39
+ */
40
+ ret = kvm_put_vcpu_events(cpu);
41
+ if (ret) {
42
+ return ret;
43
+ }
44
+
45
kvm_arm_sync_mpstate_to_kvm(cpu);
46
47
return ret;
48
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/kvm64.c
51
+++ b/target/arm/kvm64.c
52
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
53
return ret;
54
}
55
56
- ret = kvm_put_vcpu_events(cpu);
57
- if (ret) {
58
- return ret;
59
- }
60
-
61
write_cpustate_to_list(cpu, true);
62
63
if (!write_list_to_kvmstate(cpu, level)) {
64
return -EINVAL;
65
}
66
67
+ /*
68
+ * Setting VCPU events should be triggered after syncing the registers
69
+ * to avoid overwriting potential changes made by KVM upon calling
70
+ * KVM_SET_VCPU_EVENTS ioctl
71
+ */
72
+ ret = kvm_put_vcpu_events(cpu);
73
+ if (ret) {
74
+ return ret;
75
+ }
76
+
77
kvm_arm_sync_mpstate_to_kvm(cpu);
78
79
return ret;
80
--
42
--
81
2.20.1
43
2.20.1
82
44
83
45
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We fail to validate the upper bits of a virtual address on a
3
Unlike many other bits in HCR_EL2, the description for this
4
translation disabled regime, as per AArch64.TranslateAddressS1Off.
4
bit does not contain the phrase "if ... this field behaves
5
as 0 for all purposes other than", so do not squash the bit
6
in arm_hcr_el2_eff.
5
7
8
Instead, replicate the E2H+TGE test in the two places that
9
require it.
10
11
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200308012946.16303-2-richard.henderson@linaro.org
13
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
15
Message-id: 20201008162155.161886-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
17
---
11
target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++-
18
target/arm/internals.h | 9 +++++----
12
1 file changed, 34 insertions(+), 1 deletion(-)
19
target/arm/helper.c | 9 +++++----
20
2 files changed, 10 insertions(+), 8 deletions(-)
13
21
22
diff --git a/target/arm/internals.h b/target/arm/internals.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/internals.h
25
+++ b/target/arm/internals.h
26
@@ -XXX,XX +XXX,XX @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
27
&& !(env->cp15.scr_el3 & SCR_ATA)) {
28
return false;
29
}
30
- if (el < 2
31
- && arm_feature(env, ARM_FEATURE_EL2)
32
- && !(arm_hcr_el2_eff(env) & HCR_ATA)) {
33
- return false;
34
+ if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
35
+ uint64_t hcr = arm_hcr_el2_eff(env);
36
+ if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
37
+ return false;
38
+ }
39
}
40
sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);
41
return sctlr != 0;
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
42
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
44
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
45
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
46
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
19
/* Definitely a real MMU, not an MPU */
47
{
20
48
int el = arm_current_el(env);
21
if (regime_translation_disabled(env, mmu_idx)) {
49
22
- /* MMU disabled. */
50
- if (el < 2 &&
23
+ /*
51
- arm_feature(env, ARM_FEATURE_EL2) &&
24
+ * MMU disabled. S1 addresses within aa64 translation regimes are
52
- !(arm_hcr_el2_eff(env) & HCR_ATA)) {
25
+ * still checked for bounds -- see AArch64.TranslateAddressS1Off.
53
- return CP_ACCESS_TRAP_EL2;
26
+ */
54
+ if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
27
+ if (mmu_idx != ARMMMUIdx_Stage2) {
55
+ uint64_t hcr = arm_hcr_el2_eff(env);
28
+ int r_el = regime_el(env, mmu_idx);
56
+ if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
29
+ if (arm_el_is_aa64(env, r_el)) {
57
+ return CP_ACCESS_TRAP_EL2;
30
+ int pamax = arm_pamax(env_archcpu(env));
31
+ uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
32
+ int addrtop, tbi;
33
+
34
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
35
+ if (access_type == MMU_INST_FETCH) {
36
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
37
+ }
38
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
39
+ addrtop = (tbi ? 55 : 63);
40
+
41
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
42
+ fi->type = ARMFault_AddressSize;
43
+ fi->level = 0;
44
+ fi->stage2 = false;
45
+ return 1;
46
+ }
47
+
48
+ /*
49
+ * When TBI is disabled, we've just validated that all of the
50
+ * bits above PAMax are zero, so logically we only need to
51
+ * clear the top byte for TBI. But it's clearer to follow
52
+ * the pseudocode set of addrdesc.paddress.
53
+ */
54
+ address = extract64(address, 0, 52);
55
+ }
56
+ }
58
+ }
57
*phys_ptr = address;
59
}
58
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
60
if (el < 3 &&
59
*page_size = TARGET_PAGE_SIZE;
61
arm_feature(env, ARM_FEATURE_EL3) &&
60
--
62
--
61
2.20.1
63
2.20.1
62
64
63
65
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Peng Liang <liangpeng10@huawei.com>
2
2
3
A real Allwinner H3 SoC contains a Boot ROM which is the
3
VMStateDescription.fields should be end with VMSTATE_END_OF_LIST().
4
first code that runs right after the SoC is powered on.
4
However, microbit_i2c_vmstate doesn't follow it. Let's change it.
5
The Boot ROM is responsible for loading user code (e.g. a bootloader)
6
from any of the supported external devices and writing the downloaded
7
code to internal SRAM. After loading the SoC begins executing the code
8
written to SRAM.
9
5
10
This commits adds emulation of the Boot ROM firmware setup functionality
6
Fixes: 9d68bf564e ("arm: Stub out NRF51 TWI magnetometer/accelerometer detection")
11
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
7
Reported-by: Euler Robot <euler.robot@huawei.com>
12
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
8
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
13
sizes larger than 32KiB. For reference, this behaviour is documented
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
by the Linux Sunxi project wiki at:
10
Message-id: 20201019093401.2993833-1-liangpeng10@huawei.com
15
16
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
12
---
23
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
13
hw/i2c/microbit_i2c.c | 1 +
24
hw/arm/allwinner-h3.c | 17 +++++++++++++++++
14
1 file changed, 1 insertion(+)
25
hw/arm/orangepi.c | 5 +++++
26
3 files changed, 43 insertions(+)
27
15
28
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
16
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
29
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-h3.h
18
--- a/hw/i2c/microbit_i2c.c
31
+++ b/include/hw/arm/allwinner-h3.h
19
+++ b/hw/i2c/microbit_i2c.c
32
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription microbit_i2c_vmstate = {
33
#include "hw/sd/allwinner-sdhost.h"
21
.fields = (VMStateField[]) {
34
#include "hw/net/allwinner-sun8i-emac.h"
22
VMSTATE_UINT32_ARRAY(regs, MicrobitI2CState, MICROBIT_I2C_NREGS),
35
#include "target/arm/cpu.h"
23
VMSTATE_UINT32(read_idx, MicrobitI2CState),
36
+#include "sysemu/block-backend.h"
24
+ VMSTATE_END_OF_LIST()
37
25
},
38
/**
39
* Allwinner H3 device list
40
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
41
MemoryRegion sram_c;
42
} AwH3State;
43
44
+/**
45
+ * Emulate Boot ROM firmware setup functionality.
46
+ *
47
+ * A real Allwinner H3 SoC contains a Boot ROM
48
+ * which is the first code that runs right after
49
+ * the SoC is powered on. The Boot ROM is responsible
50
+ * for loading user code (e.g. a bootloader) from any
51
+ * of the supported external devices and writing the
52
+ * downloaded code to internal SRAM. After loading the SoC
53
+ * begins executing the code written to SRAM.
54
+ *
55
+ * This function emulates the Boot ROM by copying 32 KiB
56
+ * of data from the given block device and writes it to
57
+ * the start of the first internal SRAM memory.
58
+ *
59
+ * @s: Allwinner H3 state object pointer
60
+ * @blk: Block backend device object pointer
61
+ */
62
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
63
+
64
#endif /* HW_ARM_ALLWINNER_H3_H */
65
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/allwinner-h3.c
68
+++ b/hw/arm/allwinner-h3.c
69
@@ -XXX,XX +XXX,XX @@
70
#include "hw/char/serial.h"
71
#include "hw/misc/unimp.h"
72
#include "hw/usb/hcd-ehci.h"
73
+#include "hw/loader.h"
74
#include "sysemu/sysemu.h"
75
#include "hw/arm/allwinner-h3.h"
76
77
@@ -XXX,XX +XXX,XX @@ enum {
78
AW_H3_GIC_NUM_SPI = 128
79
};
26
};
80
27
81
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
82
+{
83
+ const int64_t rom_size = 32 * KiB;
84
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
85
+
86
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
87
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
88
+ __func__);
89
+ return;
90
+ }
91
+
92
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
93
+ rom_size, s->memmap[AW_H3_SRAM_A1],
94
+ NULL, NULL, NULL, NULL, false);
95
+}
96
+
97
static void allwinner_h3_init(Object *obj)
98
{
99
AwH3State *s = AW_H3(obj);
100
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/orangepi.c
103
+++ b/hw/arm/orangepi.c
104
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
105
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
106
machine->ram);
107
108
+ /* Load target kernel or start using BootROM */
109
+ if (!machine->kernel_filename && blk_is_available(blk)) {
110
+ /* Use Boot ROM to copy data from SD card to SRAM */
111
+ allwinner_h3_bootrom_setup(h3, blk);
112
+ }
113
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
114
orangepi_binfo.ram_size = machine->ram_size;
115
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
116
--
28
--
117
2.20.1
29
2.20.1
118
30
119
31
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
Commit 7998beb9c2e removed the ram_size initialization in the
4
the serial output is working.
4
arm_boot_info structure, however it is used by arm_load_kernel().
5
5
6
The kernel image and DeviceTree blob are built by the Armbian
6
Initialize the field to fix:
7
project (based on Debian):
8
https://www.armbian.com/orange-pi-pc/
9
7
10
The cpio image used comes from the linux-build-test project:
8
$ qemu-system-arm -M n800 -append 'console=ttyS1' \
11
https://github.com/groeck/linux-build-test
9
-kernel meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0
10
qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size 1964608, RAM size 0)
12
11
13
If ARM is a target being built, "make check-acceptance" will
12
Noticed while running the test introduced in commit 050a82f0c5b
14
automatically include this test by the use of the "arch:arm" tags.
13
("tests/acceptance: Add a test for the N800 and N810 arm machines").
15
14
16
Alternatively, this test can be run using:
15
Fixes: 7998beb9c2e ("arm/nseries: use memdev for RAM")
17
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
console: Uncompressing Linux... done, booting the kernel.
18
Tested-by: Thomas Huth <thuth@redhat.com>
20
console: Booting Linux on physical CPU 0x0
19
Message-id: 20201019095148.1602119-1-f4bug@amsat.org
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
23
console: CPU: div instructions available: patching division code
24
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
25
console: OF: fdt: Machine model: Xunlong Orange Pi PC
26
[...]
27
console: Trying to unpack rootfs image as initramfs...
28
console: Freeing initrd memory: 3256K
29
console: Freeing unused kernel memory: 1024K
30
console: Run /init as init process
31
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
32
console: Starting logging: OK
33
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
34
console: done.
35
console: Starting network: OK
36
console: Found console ttyS0
37
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
38
console: Boot successful.
39
console: cat /proc/cpuinfo
40
console: / # cat /proc/cpuinfo
41
console: processor : 0
42
console: model name : ARMv7 Processor rev 5 (v7l)
43
console: BogoMIPS : 125.00
44
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
45
console: CPU implementer : 0x41
46
console: CPU architecture: 7
47
console: CPU variant : 0x0
48
console: CPU part : 0xc07
49
console: CPU revision : 5
50
[...]
51
console: processor : 3
52
console: model name : ARMv7 Processor rev 5 (v7l)
53
console: BogoMIPS : 125.00
54
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
55
console: CPU implementer : 0x41
56
console: CPU architecture: 7
57
console: CPU variant : 0x0
58
console: CPU part : 0xc07
59
console: CPU revision : 5
60
console: Hardware : Allwinner sun8i Family
61
console: Revision : 0000
62
console: Serial : 0000000000000000
63
console: cat /proc/iomem
64
console: / # cat /proc/iomem
65
console: 01000000-010fffff : clock@1000000
66
console: 01c00000-01c00fff : system-control@1c00000
67
console: 01c02000-01c02fff : dma-controller@1c02000
68
[...]
69
console: reboot
70
console: / # reboot
71
console: / # Found console ttyS0
72
console: Stopping network: OK
73
console: hrtimer: interrupt took 21852064 ns
74
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
75
console: done.
76
console: Stopping logging: OK
77
console: umount: devtmpfs busy - remounted read-only
78
console: umount: can't unmount /: Invalid argument
79
console: The system is going down NOW!
80
console: Sent SIGTERM to all processes
81
console: Sent SIGKILL to all processes
82
console: Requesting system reboot
83
console: reboot: Restarting system
84
PASS (48.32 s)
85
JOB TIME : 49.16 s
86
87
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
88
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
89
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
90
Tested-by: Alex Bennée <alex.bennee@linaro.org>
91
Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com
92
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
93
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94
---
21
---
95
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
22
hw/arm/nseries.c | 1 +
96
1 file changed, 40 insertions(+)
23
1 file changed, 1 insertion(+)
97
24
98
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
99
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
100
--- a/tests/acceptance/boot_linux_console.py
27
--- a/hw/arm/nseries.c
101
+++ b/tests/acceptance/boot_linux_console.py
28
+++ b/hw/arm/nseries.c
102
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
103
console_pattern = 'Kernel command line: %s' % kernel_command_line
30
g_free(sz);
104
self.wait_for_console_pattern(console_pattern)
31
exit(EXIT_FAILURE);
105
32
}
106
+ def test_arm_orangepi_initrd(self):
33
+ binfo->ram_size = machine->ram_size;
107
+ """
34
108
+ :avocado: tags=arch:arm
35
memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
109
+ :avocado: tags=machine:orangepi-pc
36
machine->ram);
110
+ """
111
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
112
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
113
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
114
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
115
+ kernel_path = self.extract_from_deb(deb_path,
116
+ '/boot/vmlinuz-4.20.7-sunxi')
117
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
118
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
119
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
120
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
121
+ 'arm/rootfs-armv7a.cpio.gz')
122
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
123
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
124
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
125
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
126
+
127
+ self.vm.set_console()
128
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
129
+ 'console=ttyS0,115200 '
130
+ 'panic=-1 noreboot')
131
+ self.vm.add_args('-kernel', kernel_path,
132
+ '-dtb', dtb_path,
133
+ '-initrd', initrd_path,
134
+ '-append', kernel_command_line,
135
+ '-no-reboot')
136
+ self.vm.launch()
137
+ self.wait_for_console_pattern('Boot successful.')
138
+
139
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
140
+ 'Allwinner sun8i Family')
141
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
142
+ 'system-control@1c00000')
143
+ exec_command_and_wait_for_pattern(self, 'reboot',
144
+ 'reboot: Restarting system')
145
+
146
def test_s390x_s390_ccw_virtio(self):
147
"""
148
:avocado: tags=arch:s390x
149
--
37
--
150
2.20.1
38
2.20.1
151
39
152
40
diff view generated by jsdifflib
New patch
1
For nested groups like:
1
2
3
{
4
[
5
pattern 1
6
pattern 2
7
]
8
pattern 3
9
}
10
11
the intended behaviour is that patterns 1 and 2 must not
12
overlap with each other; if the insn matches neither then
13
we fall through to pattern 3 as the next thing in the
14
outer overlapping group.
15
16
Currently we generate incorrect code for this situation,
17
because in the code path for a failed match inside the
18
inner non-overlapping group we generate a "return" statement,
19
which causes decode to stop entirely rather than continuing
20
to the next thing in the outer group.
21
22
Generate a "break" instead, so that decode flow behaves
23
as required for this nested group case.
24
25
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Message-id: 20201019151301.2046-2-peter.maydell@linaro.org
29
---
30
scripts/decodetree.py | 2 +-
31
1 file changed, 1 insertion(+), 1 deletion(-)
32
33
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
34
index XXXXXXX..XXXXXXX 100644
35
--- a/scripts/decodetree.py
36
+++ b/scripts/decodetree.py
37
@@ -XXX,XX +XXX,XX @@ class Tree:
38
output(ind, ' /* ',
39
str_match_bits(innerbits, innermask), ' */\n')
40
s.output_code(i + 4, extracted, innerbits, innermask)
41
- output(ind, ' return false;\n')
42
+ output(ind, ' break;\n')
43
output(ind, '}\n')
44
# end Tree
45
46
--
47
2.20.1
48
49
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From v8.1M, disabled-coprocessor handling changes slightly:
2
* coprocessors 8, 9, 14 and 15 are also governed by the
3
cp10 enable bit, like cp11
4
* an extra range of instruction patterns is considered
5
to be inside the coprocessor space
2
6
3
Let's move the code which freezes which gic-version to
7
We previously marked these up with TODO comments; implement the
4
be applied in a dedicated function. We also now set by
8
correct behaviour.
5
default the VIRT_GIC_VERSION_NO_SET. This eventually
6
turns into the legacy v2 choice in the finalize() function.
7
9
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Unfortunately there is no ID register field which indicates this
11
behaviour. We could in theory test an unrelated ID register which
12
indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch
13
>= 3 (low-overhead-loops), but it seems better to simply define a new
14
ARM_FEATURE_V8_1M feature flag and use it for this and other
15
new-in-v8.1M behaviour that isn't identifiable from the ID registers.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
19
Message-id: 20201019151301.2046-3-peter.maydell@linaro.org
11
Message-id: 20200311131618.7187-4-eric.auger@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
20
---
14
include/hw/arm/virt.h | 1 +
21
target/arm/cpu.h | 1 +
15
hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------
22
target/arm/m-nocp.decode | 10 ++++++----
16
2 files changed, 34 insertions(+), 21 deletions(-)
23
target/arm/translate-vfp.c.inc | 17 +++++++++++++++--
24
3 files changed, 22 insertions(+), 6 deletions(-)
17
25
18
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
26
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/virt.h
28
--- a/target/arm/cpu.h
21
+++ b/include/hw/arm/virt.h
29
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType {
30
@@ -XXX,XX +XXX,XX @@ enum arm_features {
23
VIRT_GIC_VERSION_HOST,
31
ARM_FEATURE_VBAR, /* has cp15 VBAR */
24
VIRT_GIC_VERSION_2,
32
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
25
VIRT_GIC_VERSION_3,
33
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
26
+ VIRT_GIC_VERSION_NOSEL,
34
+ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
27
} VirtGICType;
35
};
28
36
29
typedef struct MemMapEntry {
37
static inline int arm_feature(CPUARMState *env, int feature)
30
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
38
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
31
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/virt.c
40
--- a/target/arm/m-nocp.decode
33
+++ b/hw/arm/virt.c
41
+++ b/target/arm/m-nocp.decode
34
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
42
@@ -XXX,XX +XXX,XX @@
43
# If the coprocessor is not present or disabled then we will generate
44
# the NOCP exception; otherwise we let the insn through to the main decode.
45
46
+&nocp cp
47
+
48
{
49
# Special cases which do not take an early NOCP: VLLDM and VLSTM
50
VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
51
# TODO: VSCCLRM (new in v8.1M) is similar:
52
#VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0
53
54
- NOCP 111- 1110 ---- ---- ---- cp:4 ---- ----
55
- NOCP 111- 110- ---- ---- ---- cp:4 ---- ----
56
- # TODO: From v8.1M onwards we will also want this range to NOCP
57
- #NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- cp=10
58
+ NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
59
+ NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
60
+ # From v8.1M onwards this range will also NOCP:
61
+ NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- &nocp cp=10
62
}
63
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/translate-vfp.c.inc
66
+++ b/target/arm/translate-vfp.c.inc
67
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
68
return true;
69
}
70
71
-static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
72
+static bool trans_NOCP(DisasContext *s, arg_nocp *a)
73
{
74
/*
75
* Handle M-profile early check for disabled coprocessor:
76
@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
77
if (a->cp == 11) {
78
a->cp = 10;
35
}
79
}
80
- /* TODO: in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
81
+ if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
82
+ (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
83
+ /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
84
+ a->cp = 10;
85
+ }
86
87
if (a->cp != 10) {
88
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
89
@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
90
return false;
36
}
91
}
37
92
38
+/*
93
+static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
39
+ * finalize_gic_version - Determines the final gic_version
40
+ * according to the gic-version property
41
+ *
42
+ * Default GIC type is v2
43
+ */
44
+static void finalize_gic_version(VirtMachineState *vms)
45
+{
94
+{
46
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
95
+ /* This range needs a coprocessor check for v8.1M and later only */
47
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
96
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
48
+ if (!kvm_enabled()) {
97
+ return false;
49
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
50
+ error_report("gic-version=host requires KVM");
51
+ exit(1);
52
+ } else {
53
+ /* "max": currently means 3 for TCG */
54
+ vms->gic_version = VIRT_GIC_VERSION_3;
55
+ }
56
+ } else {
57
+ vms->gic_version = kvm_arm_vgic_probe();
58
+ if (!vms->gic_version) {
59
+ error_report(
60
+ "Unable to determine GIC version supported by host");
61
+ exit(1);
62
+ }
63
+ }
64
+ } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
65
+ vms->gic_version = VIRT_GIC_VERSION_2;
66
+ }
98
+ }
99
+ return trans_NOCP(s, a);
67
+}
100
+}
68
+
101
+
69
static void machvirt_init(MachineState *machine)
102
static bool trans_VINS(DisasContext *s, arg_VINS *a)
70
{
103
{
71
VirtMachineState *vms = VIRT_MACHINE(machine);
104
TCGv_i32 rd, rm;
72
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
73
/* We can probe only here because during property set
74
* KVM is not available yet
75
*/
76
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
77
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
78
- if (!kvm_enabled()) {
79
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
80
- error_report("gic-version=host requires KVM");
81
- exit(1);
82
- } else {
83
- /* "max": currently means 3 for TCG */
84
- vms->gic_version = VIRT_GIC_VERSION_3;
85
- }
86
- } else {
87
- vms->gic_version = kvm_arm_vgic_probe();
88
- if (!vms->gic_version) {
89
- error_report(
90
- "Unable to determine GIC version supported by host");
91
- exit(1);
92
- }
93
- }
94
- }
95
+ finalize_gic_version(vms);
96
97
if (!cpu_type_valid(machine->cpu_type)) {
98
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
99
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
100
"Set on/off to enable/disable using "
101
"physical address space above 32 bits",
102
NULL);
103
- /* Default GIC type is v2 */
104
- vms->gic_version = VIRT_GIC_VERSION_2;
105
+ vms->gic_version = VIRT_GIC_VERSION_NOSEL;
106
object_property_add_str(obj, "gic-version", virt_get_gic_version,
107
virt_set_gic_version, NULL);
108
object_property_set_description(obj, "gic-version",
109
--
105
--
110
2.20.1
106
2.20.1
111
107
112
108
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
v8.1M brings four new insns to M-profile:
2
* CSEL : Rd = cond ? Rn : Rm
3
* CSINC : Rd = cond ? Rn : Rm+1
4
* CSINV : Rd = cond ? Rn : ~Rm
5
* CSNEG : Rd = cond ? Rn : -Rm
2
6
3
The Security Identifier device found in various Allwinner System on Chip
7
Implement these.
4
designs gives applications a per-board unique identifier. This commit
5
adds support for the Allwinner Security Identifier using a 128-bit
6
UUID value as input.
7
8
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20201019151301.2046-4-peter.maydell@linaro.org
12
---
12
---
13
hw/misc/Makefile.objs | 1 +
13
target/arm/t32.decode | 3 +++
14
include/hw/arm/allwinner-h3.h | 3 +
14
target/arm/translate.c | 60 ++++++++++++++++++++++++++++++++++++++++++
15
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
15
2 files changed, 63 insertions(+)
16
hw/arm/allwinner-h3.c | 11 ++-
17
hw/arm/orangepi.c | 8 ++
18
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
19
hw/misc/trace-events | 4 +
20
7 files changed, 254 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-sid.h
22
create mode 100644 hw/misc/allwinner-sid.c
23
16
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
17
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
25
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
19
--- a/target/arm/t32.decode
27
+++ b/hw/misc/Makefile.objs
20
+++ b/target/arm/t32.decode
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
21
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
29
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
22
}
30
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
23
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
24
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
25
+# v8.1M CSEL and friends
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
26
+CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
34
common-obj-$(CONFIG_NSERIES) += cbus.o
27
+
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
28
# Data-processing (register-shifted register)
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
29
30
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
31
diff --git a/target/arm/translate.c b/target/arm/translate.c
37
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
33
--- a/target/arm/translate.c
39
+++ b/include/hw/arm/allwinner-h3.h
34
+++ b/target/arm/translate.c
40
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ static bool trans_IT(DisasContext *s, arg_IT *a)
41
#include "hw/misc/allwinner-h3-ccu.h"
36
return true;
42
#include "hw/misc/allwinner-cpucfg.h"
37
}
43
#include "hw/misc/allwinner-h3-sysctrl.h"
38
44
+#include "hw/misc/allwinner-sid.h"
39
+/* v8.1M CSEL/CSINC/CSNEG/CSINV */
45
#include "target/arm/cpu.h"
40
+static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
46
41
+{
47
/**
42
+ TCGv_i32 rn, rm, zero;
48
@@ -XXX,XX +XXX,XX @@ enum {
43
+ DisasCompare c;
49
AW_H3_SRAM_A2,
50
AW_H3_SRAM_C,
51
AW_H3_SYSCTRL,
52
+ AW_H3_SID,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
AwH3ClockCtlState ccu;
58
AwCpuCfgState cpucfg;
59
AwH3SysCtrlState sysctrl;
60
+ AwSidState sid;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-sid.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner Security ID emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
44
+
89
+#ifndef HW_MISC_ALLWINNER_SID_H
45
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
90
+#define HW_MISC_ALLWINNER_SID_H
46
+ return false;
91
+
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
94
+#include "qemu/uuid.h"
95
+
96
+/**
97
+ * Object model
98
+ * @{
99
+ */
100
+
101
+#define TYPE_AW_SID "allwinner-sid"
102
+#define AW_SID(obj) \
103
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
104
+
105
+/** @} */
106
+
107
+/**
108
+ * Allwinner Security ID object instance state
109
+ */
110
+typedef struct AwSidState {
111
+ /*< private >*/
112
+ SysBusDevice parent_obj;
113
+ /*< public >*/
114
+
115
+ /** Maps I/O registers in physical memory */
116
+ MemoryRegion iomem;
117
+
118
+ /** Control register defines how and what to read */
119
+ uint32_t control;
120
+
121
+ /** RdKey register contains the data retrieved by the device */
122
+ uint32_t rdkey;
123
+
124
+ /** Stores the emulated device identifier */
125
+ QemuUUID identifier;
126
+
127
+} AwSidState;
128
+
129
+#endif /* HW_MISC_ALLWINNER_SID_H */
130
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/arm/allwinner-h3.c
133
+++ b/hw/arm/allwinner-h3.c
134
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
135
[AW_H3_SRAM_A2] = 0x00044000,
136
[AW_H3_SRAM_C] = 0x00010000,
137
[AW_H3_SYSCTRL] = 0x01c00000,
138
+ [AW_H3_SID] = 0x01c14000,
139
[AW_H3_EHCI0] = 0x01c1a000,
140
[AW_H3_OHCI0] = 0x01c1a400,
141
[AW_H3_EHCI1] = 0x01c1b000,
142
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
143
{ "mmc0", 0x01c0f000, 4 * KiB },
144
{ "mmc1", 0x01c10000, 4 * KiB },
145
{ "mmc2", 0x01c11000, 4 * KiB },
146
- { "sid", 0x01c14000, 1 * KiB },
147
{ "crypto", 0x01c15000, 4 * KiB },
148
{ "msgbox", 0x01c17000, 4 * KiB },
149
{ "spinlock", 0x01c18000, 4 * KiB },
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
151
152
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
153
TYPE_AW_CPUCFG);
154
+
155
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
156
+ TYPE_AW_SID);
157
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
158
+ "identifier", &error_abort);
159
}
160
161
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
162
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
163
qdev_init_nofail(DEVICE(&s->cpucfg));
164
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
165
166
+ /* Security Identifier */
167
+ qdev_init_nofail(DEVICE(&s->sid));
168
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
169
+
170
/* Universal Serial Bus */
171
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
172
qdev_get_gpio_in(DEVICE(&s->gic),
173
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/orangepi.c
176
+++ b/hw/arm/orangepi.c
177
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
178
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
179
&error_abort);
180
181
+ /* Setup SID properties. Currently using a default fixed SID identifier. */
182
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
183
+ qdev_prop_set_string(DEVICE(h3), "identifier",
184
+ "02c00081-1111-2222-3333-000044556677");
185
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) {
186
+ warn_report("Security Identifier value does not include H3 prefix");
187
+ }
47
+ }
188
+
48
+
189
/* Mark H3 object realized */
49
+ if (a->rm == 13) {
190
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
50
+ /* SEE "Related encodings" (MVE shifts) */
191
51
+ return false;
192
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
52
+ }
193
new file mode 100644
194
index XXXXXXX..XXXXXXX
195
--- /dev/null
196
+++ b/hw/misc/allwinner-sid.c
197
@@ -XXX,XX +XXX,XX @@
198
+/*
199
+ * Allwinner Security ID emulation
200
+ *
201
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
202
+ *
203
+ * This program is free software: you can redistribute it and/or modify
204
+ * it under the terms of the GNU General Public License as published by
205
+ * the Free Software Foundation, either version 2 of the License, or
206
+ * (at your option) any later version.
207
+ *
208
+ * This program is distributed in the hope that it will be useful,
209
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
210
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
211
+ * GNU General Public License for more details.
212
+ *
213
+ * You should have received a copy of the GNU General Public License
214
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
215
+ */
216
+
53
+
217
+#include "qemu/osdep.h"
54
+ if (a->rd == 13 || a->rd == 15 || a->rn == 13 || a->fcond >= 14) {
218
+#include "qemu/units.h"
55
+ /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
219
+#include "hw/sysbus.h"
56
+ return false;
220
+#include "migration/vmstate.h"
57
+ }
221
+#include "qemu/log.h"
222
+#include "qemu/module.h"
223
+#include "qemu/guest-random.h"
224
+#include "qapi/error.h"
225
+#include "hw/qdev-properties.h"
226
+#include "hw/misc/allwinner-sid.h"
227
+#include "trace.h"
228
+
58
+
229
+/* SID register offsets */
59
+ /* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
230
+enum {
60
+ if (a->rn == 15) {
231
+ REG_PRCTL = 0x40, /* Control */
61
+ rn = tcg_const_i32(0);
232
+ REG_RDKEY = 0x60, /* Read Key */
62
+ } else {
233
+};
63
+ rn = load_reg(s, a->rn);
64
+ }
65
+ if (a->rm == 15) {
66
+ rm = tcg_const_i32(0);
67
+ } else {
68
+ rm = load_reg(s, a->rm);
69
+ }
234
+
70
+
235
+/* SID register flags */
71
+ switch (a->op) {
236
+enum {
72
+ case 0: /* CSEL */
237
+ REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */
238
+ REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */
239
+};
240
+
241
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
242
+ unsigned size)
243
+{
244
+ const AwSidState *s = AW_SID(opaque);
245
+ uint64_t val = 0;
246
+
247
+ switch (offset) {
248
+ case REG_PRCTL: /* Control */
249
+ val = s->control;
250
+ break;
73
+ break;
251
+ case REG_RDKEY: /* Read Key */
74
+ case 1: /* CSINC */
252
+ val = s->rdkey;
75
+ tcg_gen_addi_i32(rm, rm, 1);
76
+ break;
77
+ case 2: /* CSINV */
78
+ tcg_gen_not_i32(rm, rm);
79
+ break;
80
+ case 3: /* CSNEG */
81
+ tcg_gen_neg_i32(rm, rm);
253
+ break;
82
+ break;
254
+ default:
83
+ default:
255
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
84
+ g_assert_not_reached();
256
+ __func__, (uint32_t)offset);
257
+ return 0;
258
+ }
85
+ }
259
+
86
+
260
+ trace_allwinner_sid_read(offset, val, size);
87
+ arm_test_cc(&c, a->fcond);
88
+ zero = tcg_const_i32(0);
89
+ tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
90
+ arm_free_cc(&c);
91
+ tcg_temp_free_i32(zero);
261
+
92
+
262
+ return val;
93
+ store_reg(s, a->rd, rn);
94
+ tcg_temp_free_i32(rm);
95
+
96
+ return true;
263
+}
97
+}
264
+
98
+
265
+static void allwinner_sid_write(void *opaque, hwaddr offset,
99
/*
266
+ uint64_t val, unsigned size)
100
* Legacy decoder.
267
+{
101
*/
268
+ AwSidState *s = AW_SID(opaque);
269
+
270
+ trace_allwinner_sid_write(offset, val, size);
271
+
272
+ switch (offset) {
273
+ case REG_PRCTL: /* Control */
274
+ s->control = val;
275
+
276
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
277
+ (s->control & REG_PRCTL_WRITE)) {
278
+ uint32_t id = s->control >> 16;
279
+
280
+ if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) {
281
+ s->rdkey = ldl_be_p(&s->identifier.data[id]);
282
+ }
283
+ }
284
+ s->control &= ~REG_PRCTL_WRITE;
285
+ break;
286
+ case REG_RDKEY: /* Read Key */
287
+ break;
288
+ default:
289
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
290
+ __func__, (uint32_t)offset);
291
+ break;
292
+ }
293
+}
294
+
295
+static const MemoryRegionOps allwinner_sid_ops = {
296
+ .read = allwinner_sid_read,
297
+ .write = allwinner_sid_write,
298
+ .endianness = DEVICE_NATIVE_ENDIAN,
299
+ .valid = {
300
+ .min_access_size = 4,
301
+ .max_access_size = 4,
302
+ },
303
+ .impl.min_access_size = 4,
304
+};
305
+
306
+static void allwinner_sid_reset(DeviceState *dev)
307
+{
308
+ AwSidState *s = AW_SID(dev);
309
+
310
+ /* Set default values for registers */
311
+ s->control = 0;
312
+ s->rdkey = 0;
313
+}
314
+
315
+static void allwinner_sid_init(Object *obj)
316
+{
317
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
318
+ AwSidState *s = AW_SID(obj);
319
+
320
+ /* Memory mapping */
321
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
322
+ TYPE_AW_SID, 1 * KiB);
323
+ sysbus_init_mmio(sbd, &s->iomem);
324
+}
325
+
326
+static Property allwinner_sid_properties[] = {
327
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
328
+ DEFINE_PROP_END_OF_LIST()
329
+};
330
+
331
+static const VMStateDescription allwinner_sid_vmstate = {
332
+ .name = "allwinner-sid",
333
+ .version_id = 1,
334
+ .minimum_version_id = 1,
335
+ .fields = (VMStateField[]) {
336
+ VMSTATE_UINT32(control, AwSidState),
337
+ VMSTATE_UINT32(rdkey, AwSidState),
338
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1),
339
+ VMSTATE_END_OF_LIST()
340
+ }
341
+};
342
+
343
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
344
+{
345
+ DeviceClass *dc = DEVICE_CLASS(klass);
346
+
347
+ dc->reset = allwinner_sid_reset;
348
+ dc->vmsd = &allwinner_sid_vmstate;
349
+ device_class_set_props(dc, allwinner_sid_properties);
350
+}
351
+
352
+static const TypeInfo allwinner_sid_info = {
353
+ .name = TYPE_AW_SID,
354
+ .parent = TYPE_SYS_BUS_DEVICE,
355
+ .instance_init = allwinner_sid_init,
356
+ .instance_size = sizeof(AwSidState),
357
+ .class_init = allwinner_sid_class_init,
358
+};
359
+
360
+static void allwinner_sid_register(void)
361
+{
362
+ type_register_static(&allwinner_sid_info);
363
+}
364
+
365
+type_init(allwinner_sid_register)
366
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
367
index XXXXXXX..XXXXXXX 100644
368
--- a/hw/misc/trace-events
369
+++ b/hw/misc/trace-events
370
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
371
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
372
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
373
374
+# allwinner-sid.c
375
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
376
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
377
+
378
# eccmemctl.c
379
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
380
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
381
--
102
--
382
2.20.1
103
2.20.1
383
104
384
105
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
The t32 decode has a group which represents a set of insns
2
which overlap with B_cond_thumb because they have [25:23]=111
3
(which is an invalid condition code field for the branch insn).
4
This group is currently defined using the {} overlap-OK syntax,
5
but it is almost entirely non-overlapping patterns. Switch
6
it over to use a non-overlapping group.
2
7
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
For this to be valid syntactically, CPS must move into the same
4
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
9
overlapping-group as the hint insns (CPS vs hints was the
5
Reviewed-by: Joel Stanley <joel@jms.id.au>
10
only actual use of the overlap facility for the group).
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
7
Message-id: 20200206112645.21275-2-clg@kaod.org
12
The non-overlapping subgroup for CLREX/DSB/DMB/ISB/SB is no longer
13
necessary and so we can remove it (promoting those insns to
14
be members of the parent group).
15
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 20201019151301.2046-5-peter.maydell@linaro.org
9
---
19
---
10
Makefile.objs | 1 +
20
target/arm/t32.decode | 26 ++++++++++++--------------
11
hw/ssi/aspeed_smc.c | 17 +++++++++++++++++
21
1 file changed, 12 insertions(+), 14 deletions(-)
12
hw/ssi/trace-events | 9 +++++++++
13
3 files changed, 27 insertions(+)
14
create mode 100644 hw/ssi/trace-events
15
22
16
diff --git a/Makefile.objs b/Makefile.objs
23
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
17
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
18
--- a/Makefile.objs
25
--- a/target/arm/t32.decode
19
+++ b/Makefile.objs
26
+++ b/target/arm/t32.decode
20
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi
27
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
21
trace-events-subdirs += hw/sd
28
{
22
trace-events-subdirs += hw/sparc
29
# Group insn[25:23] = 111, which is cond=111x for the branch below,
23
trace-events-subdirs += hw/sparc64
30
# or unconditional, which would be illegal for the branch.
24
+trace-events-subdirs += hw/ssi
31
- {
25
trace-events-subdirs += hw/timer
32
- # Hints
26
trace-events-subdirs += hw/tpm
33
+ [
27
trace-events-subdirs += hw/usb
34
+ # Hints, and CPS
28
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
35
{
29
index XXXXXXX..XXXXXXX 100644
36
YIELD 1111 0011 1010 1111 1000 0000 0000 0001
30
--- a/hw/ssi/aspeed_smc.c
37
WFE 1111 0011 1010 1111 1000 0000 0000 0010
31
+++ b/hw/ssi/aspeed_smc.c
38
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
32
@@ -XXX,XX +XXX,XX @@
39
# The canonical nop ends in 0000 0000, but the whole rest
33
#include "qapi/error.h"
40
# of the space is "reserved hint, behaves as nop".
34
#include "exec/address-spaces.h"
41
NOP 1111 0011 1010 1111 1000 0000 ---- ----
35
#include "qemu/units.h"
36
+#include "trace.h"
37
38
#include "hw/irq.h"
39
#include "hw/qdev-properties.h"
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
41
42
s->ctrl->reg_to_segment(s, new, &seg);
43
44
+ trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
45
+
42
+
46
/* The start address of CS0 is read-only */
43
+ # If imod == '00' && M == '0' then SEE "Hint instructions", above.
47
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
44
+ CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \
48
qemu_log_mask(LOG_GUEST_ERROR,
45
+ &cps
49
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
50
__func__, aspeed_smc_flash_mode(fl));
51
}
46
}
52
47
53
+ trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
48
- # If imod == '00' && M == '0' then SEE "Hint instructions", above.
54
+ aspeed_smc_flash_mode(fl));
49
- CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \
55
return ret;
50
- &cps
51
-
52
# Miscellaneous control
53
- [
54
- CLREX 1111 0011 1011 1111 1000 1111 0010 1111
55
- DSB 1111 0011 1011 1111 1000 1111 0100 ----
56
- DMB 1111 0011 1011 1111 1000 1111 0101 ----
57
- ISB 1111 0011 1011 1111 1000 1111 0110 ----
58
- SB 1111 0011 1011 1111 1000 1111 0111 0000
59
- ]
60
+ CLREX 1111 0011 1011 1111 1000 1111 0010 1111
61
+ DSB 1111 0011 1011 1111 1000 1111 0100 ----
62
+ DMB 1111 0011 1011 1111 1000 1111 0101 ----
63
+ ISB 1111 0011 1011 1111 1000 1111 0110 ----
64
+ SB 1111 0011 1011 1111 1000 1111 0111 0000
65
66
# Note that the v7m insn overlaps both the normal and banked insn.
67
{
68
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
69
HVC 1111 0111 1110 .... 1000 .... .... .... \
70
&i imm=%imm16_16_0
71
UDF 1111 0111 1111 ---- 1010 ---- ---- ----
72
- }
73
+ ]
74
B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21
56
}
75
}
57
76
58
@@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
59
AspeedSMCState *s = fl->controller;
60
uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
61
62
+ trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
63
+ (uint8_t) data & 0xff);
64
+
65
if (s->snoop_index == SNOOP_OFF) {
66
return false; /* Do nothing */
67
68
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
69
AspeedSMCState *s = fl->controller;
70
int i;
71
72
+ trace_aspeed_smc_flash_write(fl->id, addr, size, data,
73
+ aspeed_smc_flash_mode(fl));
74
+
75
if (!aspeed_smc_is_writable(fl)) {
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
77
HWADDR_PRIx "\n", __func__, addr);
78
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
79
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
80
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
81
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
82
+
83
+ trace_aspeed_smc_read(addr, size, s->regs[addr]);
84
+
85
return s->regs[addr];
86
} else {
87
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
88
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
89
__func__, s->regs[R_DMA_FLASH_ADDR]);
90
return;
91
}
92
+ trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
93
94
/*
95
* When the DMA is on-going, the DMA registers are updated
96
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
97
98
addr >>= 2;
99
100
+ trace_aspeed_smc_write(addr, size, data);
101
+
102
if (addr == s->r_conf ||
103
(addr >= s->r_timings &&
104
addr < s->r_timings + s->ctrl->nregs_timings) ||
105
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
106
new file mode 100644
107
index XXXXXXX..XXXXXXX
108
--- /dev/null
109
+++ b/hw/ssi/trace-events
110
@@ -XXX,XX +XXX,XX @@
111
+# aspeed_smc.c
112
+
113
+aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
114
+aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
115
+aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
116
+aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
117
+aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
118
+aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
119
+aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
120
--
77
--
121
2.20.1
78
2.20.1
122
79
123
80
diff view generated by jsdifflib
1
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
1
The BLX immediate insn in the Thumb encoding always performs
2
(it changes the NegPri bit). We update the hflags after calls
2
a switch from Thumb to Arm state. This would be totally useless
3
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
3
in M-profile which has no Arm decoder, and so the instruction
4
in trans_CPS_v7m().
4
does not exist at all there. Make the encoding UNDEF for M-profile.
5
5
6
(This part of the encoding space is used for the branch-future
7
and low-overhead-loop insns in v8.1M.)
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20201019151301.2046-6-peter.maydell@linaro.org
8
Message-id: 20200303174950.3298-3-peter.maydell@linaro.org
9
---
12
---
10
target/arm/translate.c | 5 ++++-
13
target/arm/translate.c | 8 ++++++++
11
1 file changed, 4 insertions(+), 1 deletion(-)
14
1 file changed, 8 insertions(+)
12
15
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
18
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
19
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
20
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
18
19
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
20
{
21
{
21
- TCGv_i32 tmp, addr;
22
TCGv_i32 tmp;
22
+ TCGv_i32 tmp, addr, el;
23
23
24
+ /*
24
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
25
+ * BLX <imm> would be useless on M-profile; the encoding space
26
+ * is used for other insns from v8.1M onward, and UNDEFs before that.
27
+ */
28
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
29
+ return false;
30
+ }
31
+
32
/* For A32, ARM_FEATURE_V5 is checked near the start of the uncond block. */
33
if (s->thumb && (a->imm & 2)) {
25
return false;
34
return false;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
27
gen_helper_v7m_msr(cpu_env, addr, tmp);
28
tcg_temp_free_i32(addr);
29
}
30
+ el = tcg_const_i32(s->current_el);
31
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
32
+ tcg_temp_free_i32(el);
33
tcg_temp_free_i32(tmp);
34
gen_lookup_tb(s);
35
return true;
36
--
35
--
37
2.20.1
36
2.20.1
38
37
39
38
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
v8.1M implements a new 'branch future' feature, which is a
2
set of instructions that request the CPU to perform a branch
3
"in the future", when it reaches a particular execution address.
4
In hardware, the expected implementation is that the information
5
about the branch location and destination is cached and then
6
acted upon when execution reaches the specified address.
7
However the architecture permits an implementation to discard
8
this cached information at any point, and so guest code must
9
always include a normal branch insn at the branch point as
10
a fallback. In particular, an implementation is specifically
11
permitted to treat all BF insns as NOPs (which is equivalent
12
to discarding the cached information immediately).
2
13
3
In the Allwinner H3 SoC the SDRAM controller is responsible
14
For QEMU, implementing this caching of branch information
4
for interfacing with the external Synchronous Dynamic Random
15
would be complicated and would not improve the speed of
5
Access Memory (SDRAM). Types of memory that the SDRAM controller
16
execution at all, so we make the IMPDEF choice to implement
6
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
17
all BF insns as NOPs.
7
adds emulation support of the Allwinner H3 SDRAM controller.
8
18
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Message-id: 20201019151301.2046-7-peter.maydell@linaro.org
13
---
22
---
14
hw/misc/Makefile.objs | 1 +
23
target/arm/cpu.h | 6 ++++++
15
include/hw/arm/allwinner-h3.h | 5 +
24
target/arm/t32.decode | 13 ++++++++++++-
16
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
25
target/arm/translate.c | 20 ++++++++++++++++++++
17
hw/arm/allwinner-h3.c | 19 +-
26
3 files changed, 38 insertions(+), 1 deletion(-)
18
hw/arm/orangepi.c | 6 +
19
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
20
hw/misc/trace-events | 10 +
21
7 files changed, 502 insertions(+), 3 deletions(-)
22
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
23
create mode 100644 hw/misc/allwinner-h3-dramc.c
24
27
25
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
28
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/misc/Makefile.objs
30
--- a/target/arm/cpu.h
28
+++ b/hw/misc/Makefile.objs
31
+++ b/target/arm/cpu.h
29
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
32
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
30
33
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
34
}
32
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
35
33
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o
36
+static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
34
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
37
+{
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
38
+ /* (M-profile) low-overhead loops and branch future */
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
39
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
37
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
40
+}
41
+
42
static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
43
{
44
return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
45
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/arm/allwinner-h3.h
47
--- a/target/arm/t32.decode
40
+++ b/include/hw/arm/allwinner-h3.h
48
+++ b/target/arm/t32.decode
41
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@ MRC 1110 1110 ... 1 .... .... .... ... 1 .... @mcr
42
#include "hw/intc/arm_gic.h"
50
43
#include "hw/misc/allwinner-h3-ccu.h"
51
B 1111 0. .......... 10.1 ............ @branch24
44
#include "hw/misc/allwinner-cpucfg.h"
52
BL 1111 0. .......... 11.1 ............ @branch24
45
+#include "hw/misc/allwinner-h3-dramc.h"
53
-BLX_i 1111 0. .......... 11.0 ............ @branch24
46
#include "hw/misc/allwinner-h3-sysctrl.h"
54
+{
47
#include "hw/misc/allwinner-sid.h"
55
+ # BLX_i is non-M-profile only
48
#include "hw/sd/allwinner-sdhost.h"
56
+ BLX_i 1111 0. .......... 11.0 ............ @branch24
49
@@ -XXX,XX +XXX,XX @@ enum {
57
+ # M-profile only: loop and branch insns
50
AW_H3_UART2,
58
+ [
51
AW_H3_UART3,
59
+ # All these BF insns have boff != 0b0000; we NOP them all
52
AW_H3_EMAC,
60
+ BF 1111 0 boff:4 ------- 1100 - ---------- 1 # BFL
53
+ AW_H3_DRAMCOM,
61
+ BF 1111 0 boff:4 0 ------ 1110 - ---------- 1 # BFCSEL
54
+ AW_H3_DRAMCTL,
62
+ BF 1111 0 boff:4 10 ----- 1110 - ---------- 1 # BF
55
+ AW_H3_DRAMPHY,
63
+ BF 1111 0 boff:4 11 ----- 1110 0 0000000000 1 # BFX, BFLX
56
AW_H3_GIC_DIST,
64
+ ]
57
AW_H3_GIC_CPU,
65
+}
58
AW_H3_GIC_HYP,
66
diff --git a/target/arm/translate.c b/target/arm/translate.c
59
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
AwCpuCfgState cpucfg;
63
+ AwH3DramCtlState dramc;
64
AwH3SysCtrlState sysctrl;
65
AwSidState sid;
66
AwSdHostState mmc0;
67
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h
68
new file mode 100644
69
index XXXXXXX..XXXXXXX
70
--- /dev/null
71
+++ b/include/hw/misc/allwinner-h3-dramc.h
72
@@ -XXX,XX +XXX,XX @@
73
+/*
74
+ * Allwinner H3 SDRAM Controller emulation
75
+ *
76
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
77
+ *
78
+ * This program is free software: you can redistribute it and/or modify
79
+ * it under the terms of the GNU General Public License as published by
80
+ * the Free Software Foundation, either version 2 of the License, or
81
+ * (at your option) any later version.
82
+ *
83
+ * This program is distributed in the hope that it will be useful,
84
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
85
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
86
+ * GNU General Public License for more details.
87
+ *
88
+ * You should have received a copy of the GNU General Public License
89
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
90
+ */
91
+
92
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
93
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
94
+
95
+#include "qom/object.h"
96
+#include "hw/sysbus.h"
97
+#include "exec/hwaddr.h"
98
+
99
+/**
100
+ * Constants
101
+ * @{
102
+ */
103
+
104
+/** Highest register address used by DRAMCOM module */
105
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
106
+
107
+/** Total number of known DRAMCOM registers */
108
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
109
+ sizeof(uint32_t))
110
+
111
+/** Highest register address used by DRAMCTL module */
112
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
113
+
114
+/** Total number of known DRAMCTL registers */
115
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
116
+ sizeof(uint32_t))
117
+
118
+/** Highest register address used by DRAMPHY module */
119
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
120
+
121
+/** Total number of known DRAMPHY registers */
122
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
123
+ sizeof(uint32_t))
124
+
125
+/** @} */
126
+
127
+/**
128
+ * Object model
129
+ * @{
130
+ */
131
+
132
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
133
+#define AW_H3_DRAMC(obj) \
134
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
135
+
136
+/** @} */
137
+
138
+/**
139
+ * Allwinner H3 SDRAM Controller object instance state.
140
+ */
141
+typedef struct AwH3DramCtlState {
142
+ /*< private >*/
143
+ SysBusDevice parent_obj;
144
+ /*< public >*/
145
+
146
+ /** Physical base address for start of RAM */
147
+ hwaddr ram_addr;
148
+
149
+ /** Total RAM size in megabytes */
150
+ uint32_t ram_size;
151
+
152
+ /**
153
+ * @name Memory Regions
154
+ * @{
155
+ */
156
+
157
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
158
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
159
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
160
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
161
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
162
+
163
+ /** @} */
164
+
165
+ /**
166
+ * @name Hardware Registers
167
+ * @{
168
+ */
169
+
170
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
171
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
172
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
173
+
174
+ /** @} */
175
+
176
+} AwH3DramCtlState;
177
+
178
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
179
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
180
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
181
--- a/hw/arm/allwinner-h3.c
68
--- a/target/arm/translate.c
182
+++ b/hw/arm/allwinner-h3.c
69
+++ b/target/arm/translate.c
183
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
70
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a)
184
[AW_H3_UART2] = 0x01c28800,
71
return true;
185
[AW_H3_UART3] = 0x01c28c00,
186
[AW_H3_EMAC] = 0x01c30000,
187
+ [AW_H3_DRAMCOM] = 0x01c62000,
188
+ [AW_H3_DRAMCTL] = 0x01c63000,
189
+ [AW_H3_DRAMPHY] = 0x01c65000,
190
[AW_H3_GIC_DIST] = 0x01c81000,
191
[AW_H3_GIC_CPU] = 0x01c82000,
192
[AW_H3_GIC_HYP] = 0x01c84000,
193
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
194
{ "scr", 0x01c2c400, 1 * KiB },
195
{ "gpu", 0x01c40000, 64 * KiB },
196
{ "hstmr", 0x01c60000, 4 * KiB },
197
- { "dramcom", 0x01c62000, 4 * KiB },
198
- { "dramctl0", 0x01c63000, 4 * KiB },
199
- { "dramphy0", 0x01c65000, 4 * KiB },
200
{ "spi0", 0x01c68000, 4 * KiB },
201
{ "spi1", 0x01c69000, 4 * KiB },
202
{ "csi", 0x01cb0000, 320 * KiB },
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
206
TYPE_AW_SUN8I_EMAC);
207
+
208
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
209
+ TYPE_AW_H3_DRAMC);
210
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
211
+ "ram-addr", &error_abort);
212
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
213
+ "ram-size", &error_abort);
214
}
72
}
215
73
216
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
74
+static bool trans_BF(DisasContext *s, arg_BF *a)
217
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
218
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
219
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
220
221
+ /* DRAMC */
222
+ qdev_init_nofail(DEVICE(&s->dramc));
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
224
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
225
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
226
+
227
/* Unimplemented devices */
228
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
229
create_unimplemented_device(unimplemented[i].device_name,
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
/* Setup EMAC properties */
236
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
237
238
+ /* DRAMC */
239
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
240
+ "ram-addr", &error_abort);
241
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",
242
+ &error_abort);
243
+
244
/* Mark H3 object realized */
245
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
246
247
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
248
new file mode 100644
249
index XXXXXXX..XXXXXXX
250
--- /dev/null
251
+++ b/hw/misc/allwinner-h3-dramc.c
252
@@ -XXX,XX +XXX,XX @@
253
+/*
254
+ * Allwinner H3 SDRAM Controller emulation
255
+ *
256
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
257
+ *
258
+ * This program is free software: you can redistribute it and/or modify
259
+ * it under the terms of the GNU General Public License as published by
260
+ * the Free Software Foundation, either version 2 of the License, or
261
+ * (at your option) any later version.
262
+ *
263
+ * This program is distributed in the hope that it will be useful,
264
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
265
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
266
+ * GNU General Public License for more details.
267
+ *
268
+ * You should have received a copy of the GNU General Public License
269
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "qemu/units.h"
274
+#include "qemu/error-report.h"
275
+#include "hw/sysbus.h"
276
+#include "migration/vmstate.h"
277
+#include "qemu/log.h"
278
+#include "qemu/module.h"
279
+#include "exec/address-spaces.h"
280
+#include "hw/qdev-properties.h"
281
+#include "qapi/error.h"
282
+#include "hw/misc/allwinner-h3-dramc.h"
283
+#include "trace.h"
284
+
285
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
286
+
287
+/* DRAMCOM register offsets */
288
+enum {
289
+ REG_DRAMCOM_CR = 0x0000, /* Control Register */
290
+};
291
+
292
+/* DRAMCTL register offsets */
293
+enum {
294
+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
295
+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
296
+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */
297
+};
298
+
299
+/* DRAMCTL register flags */
300
+enum {
301
+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
302
+};
303
+
304
+enum {
305
+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
306
+};
307
+
308
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
309
+ uint8_t bank_bits, uint16_t page_size)
310
+{
75
+{
311
+ /*
76
+ /*
312
+ * This function simulates row addressing behavior when bootloader
77
+ * M-profile branch future insns. The architecture permits an
313
+ * software attempts to detect the amount of available SDRAM. In U-Boot
78
+ * implementation to implement these as NOPs (equivalent to
314
+ * the controller is configured with the widest row addressing available.
79
+ * discarding the LO_BRANCH_INFO cache immediately), and we
315
+ * Then a pattern is written to RAM at an offset on the row boundary size.
80
+ * take that IMPDEF option because for QEMU a "real" implementation
316
+ * If the value read back equals the value read back from the
81
+ * would be complicated and wouldn't execute any faster.
317
+ * start of RAM, the bootloader knows the amount of row bits.
318
+ *
319
+ * This function inserts a mirrored memory region when the configured row
320
+ * bits are not matching the actual emulated memory, to simulate the
321
+ * same behavior on hardware as expected by the bootloader.
322
+ */
82
+ */
323
+ uint8_t row_bits_actual = 0;
83
+ if (!dc_isar_feature(aa32_lob, s)) {
324
+
84
+ return false;
325
+ /* Calculate the actual row bits using the ram_size property */
326
+ for (uint8_t i = 8; i < 12; i++) {
327
+ if (1 << i == s->ram_size) {
328
+ row_bits_actual = i + 3;
329
+ break;
330
+ }
331
+ }
85
+ }
332
+
86
+ if (a->boff == 0) {
333
+ if (s->ram_size == (1 << (row_bits - 3))) {
87
+ /* SEE "Related encodings" (loop insns) */
334
+ /* When row bits is the expected value, remove the mirror */
88
+ return false;
335
+ memory_region_set_enabled(&s->row_mirror_alias, false);
336
+ trace_allwinner_h3_dramc_rowmirror_disable();
337
+
338
+ } else if (row_bits_actual) {
339
+ /* Row bits not matching ram_size, install the rows mirror */
340
+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
341
+ bank_bits)) * page_size);
342
+
343
+ memory_region_set_enabled(&s->row_mirror_alias, true);
344
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
345
+
346
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
347
+ }
89
+ }
90
+ /* Handle as NOP */
91
+ return true;
348
+}
92
+}
349
+
93
+
350
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
94
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
351
+ unsigned size)
95
{
352
+{
96
TCGv_i32 addr, tmp;
353
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
354
+ const uint32_t idx = REG_INDEX(offset);
355
+
356
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
357
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
358
+ __func__, (uint32_t)offset);
359
+ return 0;
360
+ }
361
+
362
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
363
+
364
+ return s->dramcom[idx];
365
+}
366
+
367
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
368
+ uint64_t val, unsigned size)
369
+{
370
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
371
+ const uint32_t idx = REG_INDEX(offset);
372
+
373
+ trace_allwinner_h3_dramcom_write(offset, val, size);
374
+
375
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
376
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
377
+ __func__, (uint32_t)offset);
378
+ return;
379
+ }
380
+
381
+ switch (offset) {
382
+ case REG_DRAMCOM_CR: /* Control Register */
383
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
384
+ ((val >> 2) & 0x1) + 2,
385
+ 1 << (((val >> 8) & 0xf) + 3));
386
+ break;
387
+ default:
388
+ break;
389
+ };
390
+
391
+ s->dramcom[idx] = (uint32_t) val;
392
+}
393
+
394
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
395
+ unsigned size)
396
+{
397
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
398
+ const uint32_t idx = REG_INDEX(offset);
399
+
400
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
401
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
402
+ __func__, (uint32_t)offset);
403
+ return 0;
404
+ }
405
+
406
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
407
+
408
+ return s->dramctl[idx];
409
+}
410
+
411
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
412
+ uint64_t val, unsigned size)
413
+{
414
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
415
+ const uint32_t idx = REG_INDEX(offset);
416
+
417
+ trace_allwinner_h3_dramctl_write(offset, val, size);
418
+
419
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
420
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
421
+ __func__, (uint32_t)offset);
422
+ return;
423
+ }
424
+
425
+ switch (offset) {
426
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
427
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
428
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
429
+ break;
430
+ default:
431
+ break;
432
+ }
433
+
434
+ s->dramctl[idx] = (uint32_t) val;
435
+}
436
+
437
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
438
+ unsigned size)
439
+{
440
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
441
+ const uint32_t idx = REG_INDEX(offset);
442
+
443
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
445
+ __func__, (uint32_t)offset);
446
+ return 0;
447
+ }
448
+
449
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
450
+
451
+ return s->dramphy[idx];
452
+}
453
+
454
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
455
+ uint64_t val, unsigned size)
456
+{
457
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
458
+ const uint32_t idx = REG_INDEX(offset);
459
+
460
+ trace_allwinner_h3_dramphy_write(offset, val, size);
461
+
462
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
463
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
464
+ __func__, (uint32_t)offset);
465
+ return;
466
+ }
467
+
468
+ s->dramphy[idx] = (uint32_t) val;
469
+}
470
+
471
+static const MemoryRegionOps allwinner_h3_dramcom_ops = {
472
+ .read = allwinner_h3_dramcom_read,
473
+ .write = allwinner_h3_dramcom_write,
474
+ .endianness = DEVICE_NATIVE_ENDIAN,
475
+ .valid = {
476
+ .min_access_size = 4,
477
+ .max_access_size = 4,
478
+ },
479
+ .impl.min_access_size = 4,
480
+};
481
+
482
+static const MemoryRegionOps allwinner_h3_dramctl_ops = {
483
+ .read = allwinner_h3_dramctl_read,
484
+ .write = allwinner_h3_dramctl_write,
485
+ .endianness = DEVICE_NATIVE_ENDIAN,
486
+ .valid = {
487
+ .min_access_size = 4,
488
+ .max_access_size = 4,
489
+ },
490
+ .impl.min_access_size = 4,
491
+};
492
+
493
+static const MemoryRegionOps allwinner_h3_dramphy_ops = {
494
+ .read = allwinner_h3_dramphy_read,
495
+ .write = allwinner_h3_dramphy_write,
496
+ .endianness = DEVICE_NATIVE_ENDIAN,
497
+ .valid = {
498
+ .min_access_size = 4,
499
+ .max_access_size = 4,
500
+ },
501
+ .impl.min_access_size = 4,
502
+};
503
+
504
+static void allwinner_h3_dramc_reset(DeviceState *dev)
505
+{
506
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
507
+
508
+ /* Set default values for registers */
509
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
510
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
511
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
512
+}
513
+
514
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
515
+{
516
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
517
+
518
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
519
+ for (uint8_t i = 8; i < 13; i++) {
520
+ if (1 << i == s->ram_size) {
521
+ break;
522
+ } else if (i == 12) {
523
+ error_report("%s: ram-size %u MiB is not supported",
524
+ __func__, s->ram_size);
525
+ exit(1);
526
+ }
527
+ }
528
+
529
+ /* Setup row mirror mappings */
530
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
531
+ "allwinner-h3-dramc.row-mirror",
532
+ 4 * KiB, &error_abort);
533
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
534
+ &s->row_mirror, 10);
535
+
536
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
537
+ "allwinner-h3-dramc.row-mirror-alias",
538
+ &s->row_mirror, 0, 4 * KiB);
539
+ memory_region_add_subregion_overlap(get_system_memory(),
540
+ s->ram_addr + 1 * MiB,
541
+ &s->row_mirror_alias, 10);
542
+ memory_region_set_enabled(&s->row_mirror_alias, false);
543
+}
544
+
545
+static void allwinner_h3_dramc_init(Object *obj)
546
+{
547
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
548
+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);
549
+
550
+ /* DRAMCOM registers */
551
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
552
+ &allwinner_h3_dramcom_ops, s,
553
+ TYPE_AW_H3_DRAMC, 4 * KiB);
554
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
555
+
556
+ /* DRAMCTL registers */
557
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
558
+ &allwinner_h3_dramctl_ops, s,
559
+ TYPE_AW_H3_DRAMC, 4 * KiB);
560
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
561
+
562
+ /* DRAMPHY registers */
563
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
564
+ &allwinner_h3_dramphy_ops, s,
565
+ TYPE_AW_H3_DRAMC, 4 * KiB);
566
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
567
+}
568
+
569
+static Property allwinner_h3_dramc_properties[] = {
570
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
571
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
572
+ DEFINE_PROP_END_OF_LIST()
573
+};
574
+
575
+static const VMStateDescription allwinner_h3_dramc_vmstate = {
576
+ .name = "allwinner-h3-dramc",
577
+ .version_id = 1,
578
+ .minimum_version_id = 1,
579
+ .fields = (VMStateField[]) {
580
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
581
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
582
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
583
+ VMSTATE_END_OF_LIST()
584
+ }
585
+};
586
+
587
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
588
+{
589
+ DeviceClass *dc = DEVICE_CLASS(klass);
590
+
591
+ dc->reset = allwinner_h3_dramc_reset;
592
+ dc->vmsd = &allwinner_h3_dramc_vmstate;
593
+ dc->realize = allwinner_h3_dramc_realize;
594
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
595
+}
596
+
597
+static const TypeInfo allwinner_h3_dramc_info = {
598
+ .name = TYPE_AW_H3_DRAMC,
599
+ .parent = TYPE_SYS_BUS_DEVICE,
600
+ .instance_init = allwinner_h3_dramc_init,
601
+ .instance_size = sizeof(AwH3DramCtlState),
602
+ .class_init = allwinner_h3_dramc_class_init,
603
+};
604
+
605
+static void allwinner_h3_dramc_register(void)
606
+{
607
+ type_register_static(&allwinner_h3_dramc_info);
608
+}
609
+
610
+type_init(allwinner_h3_dramc_register)
611
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
612
index XXXXXXX..XXXXXXX 100644
613
--- a/hw/misc/trace-events
614
+++ b/hw/misc/trace-events
615
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
616
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
617
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
618
619
+# allwinner-h3-dramc.c
620
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
621
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
622
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
623
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
624
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
625
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
626
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
627
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
628
+
629
# allwinner-sid.c
630
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
631
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
632
--
97
--
633
2.20.1
98
2.20.1
634
99
635
100
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
v8.1M's "low-overhead-loop" extension has three instructions
2
for looping:
3
* DLS (start of a do-loop)
4
* WLS (start of a while-loop)
5
* LE (end of a loop)
2
6
3
Various Allwinner System on Chip designs contain multiple processors
7
The loop-start instructions are both simple operations to start a
4
that can be configured and reset using the generic CPU Configuration
8
loop whose iteration count (if any) is in LR. The loop-end
5
module interface. This commit adds support for the Allwinner CPU
9
instruction handles "decrement iteration count and jump back to loop
6
configuration interface which emulates the following features:
10
start"; it also caches the information about the branch back to the
11
start of the loop to improve performance of the branch on subsequent
12
iterations.
7
13
8
* CPU reset
14
As with the branch-future instructions, the architecture permits an
9
* CPU status
15
implementation to discard the LO_BRANCH_INFO cache at any time, and
16
QEMU takes the IMPDEF option to never set it in the first place
17
(equivalent to discarding it immediately), because for us a "real"
18
implementation would be unnecessary complexity.
10
19
11
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
20
(This implementation only provides the simple looping constructs; the
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
21
vector extension MVE (Helium) adds some extra variants to handle
13
Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com
22
looping across vectors. We'll add those later when we implement
23
MVE.)
24
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-id: 20201019151301.2046-8-peter.maydell@linaro.org
15
---
28
---
16
hw/misc/Makefile.objs | 1 +
29
target/arm/t32.decode | 8 ++++
17
include/hw/arm/allwinner-h3.h | 3 +
30
target/arm/translate.c | 93 +++++++++++++++++++++++++++++++++++++++++-
18
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
31
2 files changed, 99 insertions(+), 2 deletions(-)
19
hw/arm/allwinner-h3.c | 9 +-
20
hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++
21
hw/misc/trace-events | 5 +
22
6 files changed, 351 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/misc/allwinner-cpucfg.h
24
create mode 100644 hw/misc/allwinner-cpucfg.c
25
32
26
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
33
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
27
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/misc/Makefile.objs
35
--- a/target/arm/t32.decode
29
+++ b/hw/misc/Makefile.objs
36
+++ b/target/arm/t32.decode
30
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
37
@@ -XXX,XX +XXX,XX @@ BL 1111 0. .......... 11.1 ............ @branch24
31
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
38
BF 1111 0 boff:4 10 ----- 1110 - ---------- 1 # BF
32
39
BF 1111 0 boff:4 11 ----- 1110 0 0000000000 1 # BFX, BFLX
33
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
40
]
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
41
+ [
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
42
+ # LE and WLS immediate
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
43
+ %lob_imm 1:10 11:1 !function=times_2
37
common-obj-$(CONFIG_NSERIES) += cbus.o
44
+
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
45
+ DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001
46
+ WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm
47
+ LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
48
+ ]
49
}
50
diff --git a/target/arm/translate.c b/target/arm/translate.c
39
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/allwinner-h3.h
52
--- a/target/arm/translate.c
41
+++ b/include/hw/arm/allwinner-h3.h
53
+++ b/target/arm/translate.c
42
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
43
#include "hw/timer/allwinner-a10-pit.h"
55
s->base.is_jmp = DISAS_NORETURN;
44
#include "hw/intc/arm_gic.h"
45
#include "hw/misc/allwinner-h3-ccu.h"
46
+#include "hw/misc/allwinner-cpucfg.h"
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "target/arm/cpu.h"
49
50
@@ -XXX,XX +XXX,XX @@ enum {
51
AW_H3_GIC_CPU,
52
AW_H3_GIC_HYP,
53
AW_H3_GIC_VCPU,
54
+ AW_H3_CPUCFG,
55
AW_H3_SDRAM
56
};
57
58
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
59
const hwaddr *memmap;
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
+ AwCpuCfgState cpucfg;
63
AwH3SysCtrlState sysctrl;
64
GICState gic;
65
MemoryRegion sram_a1;
66
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h
67
new file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- /dev/null
70
+++ b/include/hw/misc/allwinner-cpucfg.h
71
@@ -XXX,XX +XXX,XX @@
72
+/*
73
+ * Allwinner CPU Configuration Module emulation
74
+ *
75
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
76
+ *
77
+ * This program is free software: you can redistribute it and/or modify
78
+ * it under the terms of the GNU General Public License as published by
79
+ * the Free Software Foundation, either version 2 of the License, or
80
+ * (at your option) any later version.
81
+ *
82
+ * This program is distributed in the hope that it will be useful,
83
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
84
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
85
+ * GNU General Public License for more details.
86
+ *
87
+ * You should have received a copy of the GNU General Public License
88
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
89
+ */
90
+
91
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
92
+#define HW_MISC_ALLWINNER_CPUCFG_H
93
+
94
+#include "qom/object.h"
95
+#include "hw/sysbus.h"
96
+
97
+/**
98
+ * Object model
99
+ * @{
100
+ */
101
+
102
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
103
+#define AW_CPUCFG(obj) \
104
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
105
+
106
+/** @} */
107
+
108
+/**
109
+ * Allwinner CPU Configuration Module instance state
110
+ */
111
+typedef struct AwCpuCfgState {
112
+ /*< private >*/
113
+ SysBusDevice parent_obj;
114
+ /*< public >*/
115
+
116
+ MemoryRegion iomem;
117
+ uint32_t gen_ctrl;
118
+ uint32_t super_standby;
119
+ uint32_t entry_addr;
120
+
121
+} AwCpuCfgState;
122
+
123
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
124
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/arm/allwinner-h3.c
127
+++ b/hw/arm/allwinner-h3.c
128
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
129
[AW_H3_GIC_CPU] = 0x01c82000,
130
[AW_H3_GIC_HYP] = 0x01c84000,
131
[AW_H3_GIC_VCPU] = 0x01c86000,
132
+ [AW_H3_CPUCFG] = 0x01f01c00,
133
[AW_H3_SDRAM] = 0x40000000
134
};
135
136
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
137
{ "r_wdog", 0x01f01000, 1 * KiB },
138
{ "r_prcm", 0x01f01400, 1 * KiB },
139
{ "r_twd", 0x01f01800, 1 * KiB },
140
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
141
{ "r_cir-rx", 0x01f02000, 1 * KiB },
142
{ "r_twi", 0x01f02400, 1 * KiB },
143
{ "r_uart", 0x01f02800, 1 * KiB },
144
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
145
146
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
147
TYPE_AW_H3_SYSCTRL);
148
+
149
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
150
+ TYPE_AW_CPUCFG);
151
}
56
}
152
57
153
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
58
-static inline void gen_jmp (DisasContext *s, uint32_t dest)
154
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
59
+/* Jump, specifying which TB number to use if we gen_goto_tb() */
155
qdev_init_nofail(DEVICE(&s->sysctrl));
60
+static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
156
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
61
{
157
62
if (unlikely(is_singlestepping(s))) {
158
+ /* CPU Configuration */
63
/* An indirect jump so that we still trigger the debug exception. */
159
+ qdev_init_nofail(DEVICE(&s->cpucfg));
64
gen_set_pc_im(s, dest);
160
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
65
s->base.is_jmp = DISAS_JUMP;
161
+
66
} else {
162
/* Universal Serial Bus */
67
- gen_goto_tb(s, 0, dest);
163
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
68
+ gen_goto_tb(s, tbno, dest);
164
qdev_get_gpio_in(DEVICE(&s->gic),
69
}
165
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
70
}
166
new file mode 100644
71
167
index XXXXXXX..XXXXXXX
72
+static inline void gen_jmp(DisasContext *s, uint32_t dest)
168
--- /dev/null
169
+++ b/hw/misc/allwinner-cpucfg.c
170
@@ -XXX,XX +XXX,XX @@
171
+/*
172
+ * Allwinner CPU Configuration Module emulation
173
+ *
174
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
175
+ *
176
+ * This program is free software: you can redistribute it and/or modify
177
+ * it under the terms of the GNU General Public License as published by
178
+ * the Free Software Foundation, either version 2 of the License, or
179
+ * (at your option) any later version.
180
+ *
181
+ * This program is distributed in the hope that it will be useful,
182
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
183
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
184
+ * GNU General Public License for more details.
185
+ *
186
+ * You should have received a copy of the GNU General Public License
187
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
188
+ */
189
+
190
+#include "qemu/osdep.h"
191
+#include "qemu/units.h"
192
+#include "hw/sysbus.h"
193
+#include "migration/vmstate.h"
194
+#include "qemu/log.h"
195
+#include "qemu/module.h"
196
+#include "qemu/error-report.h"
197
+#include "qemu/timer.h"
198
+#include "hw/core/cpu.h"
199
+#include "target/arm/arm-powerctl.h"
200
+#include "target/arm/cpu.h"
201
+#include "hw/misc/allwinner-cpucfg.h"
202
+#include "trace.h"
203
+
204
+/* CPUCFG register offsets */
205
+enum {
206
+ REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
207
+ REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
208
+ REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
209
+ REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
210
+ REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
211
+ REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
212
+ REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
213
+ REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
214
+ REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
215
+ REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
216
+ REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
217
+ REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
218
+ REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
219
+ REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
220
+ REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
221
+ REG_GEN_CTRL = 0x0184, /* General Control */
222
+ REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */
223
+ REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */
224
+ REG_DBG_EXTERN = 0x01E4, /* Debug External */
225
+ REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
226
+ REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
227
+ REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
228
+};
229
+
230
+/* CPUCFG register flags */
231
+enum {
232
+ CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)),
233
+ CPUX_STATUS_SMP = (1 << 0),
234
+ CPU_SYS_RESET_RELEASED = (1 << 0),
235
+ CLK_GATING_ENABLE = ((1 << 8) | 0xF),
236
+};
237
+
238
+/* CPUCFG register reset values */
239
+enum {
240
+ REG_CLK_GATING_RST = 0x0000010F,
241
+ REG_GEN_CTRL_RST = 0x00000020,
242
+ REG_SUPER_STANDBY_RST = 0x0,
243
+ REG_CNT64_CTRL_RST = 0x0,
244
+};
245
+
246
+/* CPUCFG constants */
247
+enum {
248
+ CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
249
+};
250
+
251
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
252
+{
73
+{
253
+ int ret;
74
+ gen_jmp_tb(s, dest, 0);
254
+
255
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
256
+
257
+ ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
258
+ if (!target_cpu) {
259
+ /*
260
+ * Called with a bogus value for cpu_id. Guest error will
261
+ * already have been logged, we can simply return here.
262
+ */
263
+ return;
264
+ }
265
+ bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
266
+
267
+ ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
268
+ CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64);
269
+ if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
270
+ error_report("%s: failed to bring up CPU %d: err %d",
271
+ __func__, cpu_id, ret);
272
+ return;
273
+ }
274
+}
75
+}
275
+
76
+
276
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
77
static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
277
+ unsigned size)
78
{
79
if (x)
80
@@ -XXX,XX +XXX,XX @@ static bool trans_BF(DisasContext *s, arg_BF *a)
81
return true;
82
}
83
84
+static bool trans_DLS(DisasContext *s, arg_DLS *a)
278
+{
85
+{
279
+ const AwCpuCfgState *s = AW_CPUCFG(opaque);
86
+ /* M-profile low-overhead loop start */
280
+ uint64_t val = 0;
87
+ TCGv_i32 tmp;
281
+
88
+
282
+ switch (offset) {
89
+ if (!dc_isar_feature(aa32_lob, s)) {
283
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
90
+ return false;
284
+ case REG_CPU_SYS_RST: /* CPU System Reset */
91
+ }
285
+ val = CPU_SYS_RESET_RELEASED;
92
+ if (a->rn == 13 || a->rn == 15) {
286
+ break;
93
+ /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
287
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
94
+ return false;
288
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
289
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
290
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
291
+ val = CPUX_RESET_RELEASED;
292
+ break;
293
+ case REG_CPU0_CTRL: /* CPU#0 Control */
294
+ case REG_CPU1_CTRL: /* CPU#1 Control */
295
+ case REG_CPU2_CTRL: /* CPU#2 Control */
296
+ case REG_CPU3_CTRL: /* CPU#3 Control */
297
+ val = 0;
298
+ break;
299
+ case REG_CPU0_STATUS: /* CPU#0 Status */
300
+ case REG_CPU1_STATUS: /* CPU#1 Status */
301
+ case REG_CPU2_STATUS: /* CPU#2 Status */
302
+ case REG_CPU3_STATUS: /* CPU#3 Status */
303
+ val = CPUX_STATUS_SMP;
304
+ break;
305
+ case REG_CLK_GATING: /* CPU Clock Gating */
306
+ val = CLK_GATING_ENABLE;
307
+ break;
308
+ case REG_GEN_CTRL: /* General Control */
309
+ val = s->gen_ctrl;
310
+ break;
311
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
312
+ val = s->super_standby;
313
+ break;
314
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
315
+ val = s->entry_addr;
316
+ break;
317
+ case REG_DBG_EXTERN: /* Debug External */
318
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
319
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
320
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
321
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
322
+ __func__, (uint32_t)offset);
323
+ break;
324
+ default:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ }
95
+ }
329
+
96
+
330
+ trace_allwinner_cpucfg_read(offset, val, size);
97
+ /* Not a while loop, no tail predication: just set LR to the count */
331
+
98
+ tmp = load_reg(s, a->rn);
332
+ return val;
99
+ store_reg(s, 14, tmp);
100
+ return true;
333
+}
101
+}
334
+
102
+
335
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
103
+static bool trans_WLS(DisasContext *s, arg_WLS *a)
336
+ uint64_t val, unsigned size)
337
+{
104
+{
338
+ AwCpuCfgState *s = AW_CPUCFG(opaque);
105
+ /* M-profile low-overhead while-loop start */
106
+ TCGv_i32 tmp;
107
+ TCGLabel *nextlabel;
339
+
108
+
340
+ trace_allwinner_cpucfg_write(offset, val, size);
109
+ if (!dc_isar_feature(aa32_lob, s)) {
110
+ return false;
111
+ }
112
+ if (a->rn == 13 || a->rn == 15) {
113
+ /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
114
+ return false;
115
+ }
116
+ if (s->condexec_mask) {
117
+ /*
118
+ * WLS in an IT block is CONSTRAINED UNPREDICTABLE;
119
+ * we choose to UNDEF, because otherwise our use of
120
+ * gen_goto_tb(1) would clash with the use of TB exit 1
121
+ * in the dc->condjmp condition-failed codepath in
122
+ * arm_tr_tb_stop() and we'd get an assertion.
123
+ */
124
+ return false;
125
+ }
126
+ nextlabel = gen_new_label();
127
+ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel);
128
+ tmp = load_reg(s, a->rn);
129
+ store_reg(s, 14, tmp);
130
+ gen_jmp_tb(s, s->base.pc_next, 1);
341
+
131
+
342
+ switch (offset) {
132
+ gen_set_label(nextlabel);
343
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
133
+ gen_jmp(s, read_pc(s) + a->imm);
344
+ case REG_CPU_SYS_RST: /* CPU System Reset */
134
+ return true;
345
+ break;
346
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
347
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
348
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
349
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
350
+ if (val) {
351
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6);
352
+ }
353
+ break;
354
+ case REG_CPU0_CTRL: /* CPU#0 Control */
355
+ case REG_CPU1_CTRL: /* CPU#1 Control */
356
+ case REG_CPU2_CTRL: /* CPU#2 Control */
357
+ case REG_CPU3_CTRL: /* CPU#3 Control */
358
+ case REG_CPU0_STATUS: /* CPU#0 Status */
359
+ case REG_CPU1_STATUS: /* CPU#1 Status */
360
+ case REG_CPU2_STATUS: /* CPU#2 Status */
361
+ case REG_CPU3_STATUS: /* CPU#3 Status */
362
+ case REG_CLK_GATING: /* CPU Clock Gating */
363
+ break;
364
+ case REG_GEN_CTRL: /* General Control */
365
+ s->gen_ctrl = val;
366
+ break;
367
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
368
+ s->super_standby = val;
369
+ break;
370
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
371
+ s->entry_addr = val;
372
+ break;
373
+ case REG_DBG_EXTERN: /* Debug External */
374
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
375
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
376
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
377
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
378
+ __func__, (uint32_t)offset);
379
+ break;
380
+ default:
381
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
382
+ __func__, (uint32_t)offset);
383
+ break;
384
+ }
385
+}
135
+}
386
+
136
+
387
+static const MemoryRegionOps allwinner_cpucfg_ops = {
137
+static bool trans_LE(DisasContext *s, arg_LE *a)
388
+ .read = allwinner_cpucfg_read,
138
+{
389
+ .write = allwinner_cpucfg_write,
139
+ /*
390
+ .endianness = DEVICE_NATIVE_ENDIAN,
140
+ * M-profile low-overhead loop end. The architecture permits an
391
+ .valid = {
141
+ * implementation to discard the LO_BRANCH_INFO cache at any time,
392
+ .min_access_size = 4,
142
+ * and we take the IMPDEF option to never set it in the first place
393
+ .max_access_size = 4,
143
+ * (equivalent to always discarding it immediately), because for QEMU
394
+ },
144
+ * a "real" implementation would be complicated and wouldn't execute
395
+ .impl.min_access_size = 4,
145
+ * any faster.
396
+};
146
+ */
147
+ TCGv_i32 tmp;
397
+
148
+
398
+static void allwinner_cpucfg_reset(DeviceState *dev)
149
+ if (!dc_isar_feature(aa32_lob, s)) {
399
+{
150
+ return false;
400
+ AwCpuCfgState *s = AW_CPUCFG(dev);
151
+ }
401
+
152
+
402
+ /* Set default values for registers */
153
+ if (!a->f) {
403
+ s->gen_ctrl = REG_GEN_CTRL_RST;
154
+ /* Not loop-forever. If LR <= 1 this is the last loop: do nothing. */
404
+ s->super_standby = REG_SUPER_STANDBY_RST;
155
+ arm_gen_condlabel(s);
405
+ s->entry_addr = 0;
156
+ tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, s->condlabel);
157
+ /* Decrement LR */
158
+ tmp = load_reg(s, 14);
159
+ tcg_gen_addi_i32(tmp, tmp, -1);
160
+ store_reg(s, 14, tmp);
161
+ }
162
+ /* Jump back to the loop start */
163
+ gen_jmp(s, read_pc(s) - a->imm);
164
+ return true;
406
+}
165
+}
407
+
166
+
408
+static void allwinner_cpucfg_init(Object *obj)
167
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
409
+{
168
{
410
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
169
TCGv_i32 addr, tmp;
411
+ AwCpuCfgState *s = AW_CPUCFG(obj);
412
+
413
+ /* Memory mapping */
414
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
415
+ TYPE_AW_CPUCFG, 1 * KiB);
416
+ sysbus_init_mmio(sbd, &s->iomem);
417
+}
418
+
419
+static const VMStateDescription allwinner_cpucfg_vmstate = {
420
+ .name = "allwinner-cpucfg",
421
+ .version_id = 1,
422
+ .minimum_version_id = 1,
423
+ .fields = (VMStateField[]) {
424
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
425
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
426
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
427
+ VMSTATE_END_OF_LIST()
428
+ }
429
+};
430
+
431
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
432
+{
433
+ DeviceClass *dc = DEVICE_CLASS(klass);
434
+
435
+ dc->reset = allwinner_cpucfg_reset;
436
+ dc->vmsd = &allwinner_cpucfg_vmstate;
437
+}
438
+
439
+static const TypeInfo allwinner_cpucfg_info = {
440
+ .name = TYPE_AW_CPUCFG,
441
+ .parent = TYPE_SYS_BUS_DEVICE,
442
+ .instance_init = allwinner_cpucfg_init,
443
+ .instance_size = sizeof(AwCpuCfgState),
444
+ .class_init = allwinner_cpucfg_class_init,
445
+};
446
+
447
+static void allwinner_cpucfg_register(void)
448
+{
449
+ type_register_static(&allwinner_cpucfg_info);
450
+}
451
+
452
+type_init(allwinner_cpucfg_register)
453
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
454
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/misc/trace-events
456
+++ b/hw/misc/trace-events
457
@@ -XXX,XX +XXX,XX @@
458
# See docs/devel/tracing.txt for syntax documentation.
459
460
+# allwinner-cpucfg.c
461
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32
462
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
463
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
464
+
465
# eccmemctl.c
466
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
467
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
468
--
170
--
469
2.20.1
171
2.20.1
470
172
471
173
diff view generated by jsdifflib
New patch
1
In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
2
squash the ID register fields so that we don't advertise it to the
3
guest. This code was written for A-profile and needs some tweaks to
4
work correctly on M-profile:
1
5
6
* A-profile only fields should not be zeroed on M-profile:
7
- MVFR0.FPSHVEC,FPTRAP
8
- MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP
9
- MVFR2.SIMDMISC
10
* M-profile only fields should be zeroed on M-profile:
11
- MVFR1.FP16
12
13
In particular, because MVFR1.SIMDHP on A-profile is the same field as
14
MVFR1.FP16 on M-profile this code was incorrectly disabling FP16
15
support on an M-profile CPU (where has_neon is always false). This
16
isn't a visible bug yet because we don't have any M-profile CPUs with
17
FP16 support, but the change is necessary before we introduce any.
18
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Message-id: 20201019151301.2046-9-peter.maydell@linaro.org
22
---
23
target/arm/cpu.c | 29 ++++++++++++++++++-----------
24
1 file changed, 18 insertions(+), 11 deletions(-)
25
26
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/cpu.c
29
+++ b/target/arm/cpu.c
30
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
31
u = cpu->isar.mvfr0;
32
u = FIELD_DP32(u, MVFR0, FPSP, 0);
33
u = FIELD_DP32(u, MVFR0, FPDP, 0);
34
- u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
35
u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
36
u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
37
- u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
38
u = FIELD_DP32(u, MVFR0, FPROUND, 0);
39
+ if (!arm_feature(env, ARM_FEATURE_M)) {
40
+ u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
41
+ u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
42
+ }
43
cpu->isar.mvfr0 = u;
44
45
u = cpu->isar.mvfr1;
46
u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
47
u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
48
u = FIELD_DP32(u, MVFR1, FPHP, 0);
49
+ if (arm_feature(env, ARM_FEATURE_M)) {
50
+ u = FIELD_DP32(u, MVFR1, FP16, 0);
51
+ }
52
cpu->isar.mvfr1 = u;
53
54
u = cpu->isar.mvfr2;
55
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
56
u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
57
cpu->isar.id_isar6 = u;
58
59
- u = cpu->isar.mvfr1;
60
- u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
61
- u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
62
- u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
63
- u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
64
- cpu->isar.mvfr1 = u;
65
+ if (!arm_feature(env, ARM_FEATURE_M)) {
66
+ u = cpu->isar.mvfr1;
67
+ u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
68
+ u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
69
+ u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
70
+ u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
71
+ cpu->isar.mvfr1 = u;
72
73
- u = cpu->isar.mvfr2;
74
- u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
75
- cpu->isar.mvfr2 = u;
76
+ u = cpu->isar.mvfr2;
77
+ u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
78
+ cpu->isar.mvfr2 = u;
79
+ }
80
}
81
82
if (!cpu->has_neon && !cpu->has_vfp) {
83
--
84
2.20.1
85
86
diff view generated by jsdifflib
1
Some of an M-profile CPU's cached hflags state depends on state that's
1
M-profile CPUs with half-precision floating point support should
2
in our NVIC object. We already do an hflags rebuild when the NVIC
2
be able to write to FPSCR.FZ16, but an M-profile specific masking
3
registers are written, but we also need to do this on NVIC reset,
3
of the value at the top of vfp_set_fpscr() currently prevents that.
4
because there's no guarantee that this will happen before the
4
This is not yet an active bug because we have no M-profile
5
CPU reset.
5
FP16 CPUs, but needs to be fixed before we can add any.
6
6
7
This fixes an assertion due to mismatched hflags which happens if
7
The bits that the masking is effectively preventing from being
8
the CPU is reset from inside a HardFault handler.
8
set are the A-profile only short-vector Len and Stride fields,
9
plus the Neon QC bit. Rearrange the order of the function so
10
that those fields are handled earlier and only under a suitable
11
guard; this allows us to drop the M-profile specific masking,
12
making FZ16 writeable.
13
14
This change also makes the QC bit correctly RAZ/WI for older
15
no-Neon A-profile cores.
16
17
This refactoring also paves the way for the low-overhead-branch
18
LTPSIZE field, which uses some of the bits that are used for
19
A-profile Stride and Len.
9
20
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200303174950.3298-2-peter.maydell@linaro.org
23
Message-id: 20201019151301.2046-10-peter.maydell@linaro.org
13
---
24
---
14
hw/intc/armv7m_nvic.c | 6 ++++++
25
target/arm/vfp_helper.c | 47 ++++++++++++++++++++++++-----------------
15
1 file changed, 6 insertions(+)
26
1 file changed, 28 insertions(+), 19 deletions(-)
16
27
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
28
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
18
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
30
--- a/target/arm/vfp_helper.c
20
+++ b/hw/intc/armv7m_nvic.c
31
+++ b/target/arm/vfp_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
32
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
22
s->itns[i] = true;
33
val &= ~FPCR_FZ16;
23
}
24
}
34
}
35
36
- if (arm_feature(env, ARM_FEATURE_M)) {
37
+ vfp_set_fpscr_to_host(env, val);
25
+
38
+
26
+ /*
39
+ if (!arm_feature(env, ARM_FEATURE_M)) {
27
+ * We updated state that affects the CPU's MMUidx and thus its hflags;
40
/*
28
+ * and we can't guarantee that we run before the CPU reset function.
41
- * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
29
+ */
42
- * and also for the trapped-exception-handling bits IxE.
30
+ arm_rebuild_hflags(&s->cpu->env);
43
+ * Short-vector length and stride; on M-profile these bits
44
+ * are used for different purposes.
45
+ * We can't make this conditional be "if MVFR0.FPShVec != 0",
46
+ * because in v7A no-short-vector-support cores still had to
47
+ * allow Stride/Len to be written with the only effect that
48
+ * some insns are required to UNDEF if the guest sets them.
49
+ *
50
+ * TODO: if M-profile MVE implemented, set LTPSIZE.
51
*/
52
- val &= 0xf7c0009f;
53
+ env->vfp.vec_len = extract32(val, 16, 3);
54
+ env->vfp.vec_stride = extract32(val, 20, 2);
55
}
56
57
- vfp_set_fpscr_to_host(env, val);
58
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
59
+ /*
60
+ * The bit we set within fpscr_q is arbitrary; the register as a
61
+ * whole being zero/non-zero is what counts.
62
+ * TODO: M-profile MVE also has a QC bit.
63
+ */
64
+ env->vfp.qc[0] = val & FPCR_QC;
65
+ env->vfp.qc[1] = 0;
66
+ env->vfp.qc[2] = 0;
67
+ env->vfp.qc[3] = 0;
68
+ }
69
70
/*
71
* We don't implement trapped exception handling, so the
72
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
73
*
74
- * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
75
- * (which are stored in fp_status), and the other RES0 bits
76
- * in between, then we clear all of the low 16 bits.
77
+ * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
78
+ * fp_status; QC, Len and Stride are stored separately earlier.
79
+ * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
80
+ * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
81
*/
82
env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
83
- env->vfp.vec_len = (val >> 16) & 7;
84
- env->vfp.vec_stride = (val >> 20) & 3;
85
-
86
- /*
87
- * The bit we set within fpscr_q is arbitrary; the register as a
88
- * whole being zero/non-zero is what counts.
89
- */
90
- env->vfp.qc[0] = val & FPCR_QC;
91
- env->vfp.qc[1] = 0;
92
- env->vfp.qc[2] = 0;
93
- env->vfp.qc[3] = 0;
31
}
94
}
32
95
33
static void nvic_systick_trigger(void *opaque, int n, int level)
96
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
34
--
97
--
35
2.20.1
98
2.20.1
36
99
37
100
diff view generated by jsdifflib
New patch
1
If the M-profile low-overhead-branch extension is implemented, FPSCR
2
bits [18:16] are a new field LTPSIZE. If MVE is not implemented
3
(currently always true for us) then this field always reads as 4 and
4
ignores writes.
1
5
6
These bits used to be the vector-length field for the old
7
short-vector extension, so we need to take care that they are not
8
misinterpreted as setting vec_len. We do this with a rearrangement
9
of the vfp_set_fpscr() code that deals with vec_len, vec_stride
10
and also the QC bit; this obviates the need for the M-profile
11
only masking step that we used to have at the start of the function.
12
13
We provide a new field in CPUState for LTPSIZE, even though this
14
will always be 4, in preparation for MVE, so we don't have to
15
come back later and split it out of the vfp.xregs[FPSCR] value.
16
(This state struct field will be saved and restored as part of
17
the FPSCR value via the vmstate_fpscr in machine.c.)
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20201019151301.2046-11-peter.maydell@linaro.org
22
---
23
target/arm/cpu.h | 1 +
24
target/arm/cpu.c | 9 +++++++++
25
target/arm/vfp_helper.c | 6 ++++++
26
3 files changed, 16 insertions(+)
27
28
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu.h
31
+++ b/target/arm/cpu.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
33
uint32_t fpdscr[M_REG_NUM_BANKS];
34
uint32_t cpacr[M_REG_NUM_BANKS];
35
uint32_t nsacr;
36
+ int ltpsize;
37
} v7m;
38
39
/* Information associated with an exception about to be taken:
40
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu.c
43
+++ b/target/arm/cpu.c
44
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
45
uint8_t *rom;
46
uint32_t vecbase;
47
48
+ if (cpu_isar_feature(aa32_lob, cpu)) {
49
+ /*
50
+ * LTPSIZE is constant 4 if MVE not implemented, and resets
51
+ * to an UNKNOWN value if MVE is implemented. We choose to
52
+ * always reset to 4.
53
+ */
54
+ env->v7m.ltpsize = 4;
55
+ }
56
+
57
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
58
env->v7m.secure = true;
59
} else {
60
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/vfp_helper.c
63
+++ b/target/arm/vfp_helper.c
64
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
65
| (env->vfp.vec_len << 16)
66
| (env->vfp.vec_stride << 20);
67
68
+ /*
69
+ * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
70
+ * two is not applicable to this CPU will always be zero.
71
+ */
72
+ fpscr |= env->v7m.ltpsize << 16;
73
+
74
fpscr |= vfp_get_fpscr_from_host(env);
75
76
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner H3 System on Chip has an System Control
3
The kernel sets btype for the signal handler as if for a call.
4
module that provides system wide generic controls and
5
device information. This commit adds support for the
6
Allwinner H3 System Control module.
7
4
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201016184207.786698-2-richard.henderson@linaro.org
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
9
---
15
hw/misc/Makefile.objs | 1 +
10
linux-user/aarch64/signal.c | 10 ++++++++--
16
include/hw/arm/allwinner-h3.h | 3 +
11
1 file changed, 8 insertions(+), 2 deletions(-)
17
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
19
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
20
5 files changed, 219 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
22
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
23
12
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
13
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
15
--- a/linux-user/aarch64/signal.c
27
+++ b/hw/misc/Makefile.objs
16
+++ b/linux-user/aarch64/signal.c
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
17
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
29
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
18
+ offsetof(struct target_rt_frame_record, tramp);
30
19
}
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
20
env->xregs[0] = usig;
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
21
- env->xregs[31] = frame_addr;
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
22
env->xregs[29] = frame_addr + fr_ofs;
34
common-obj-$(CONFIG_NSERIES) += cbus.o
23
- env->pc = ka->_sa_handler;
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
24
env->xregs[30] = return_addr;
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
25
+ env->xregs[31] = frame_addr;
37
index XXXXXXX..XXXXXXX 100644
26
+ env->pc = ka->_sa_handler;
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/timer/allwinner-a10-pit.h"
42
#include "hw/intc/arm_gic.h"
43
#include "hw/misc/allwinner-h3-ccu.h"
44
+#include "hw/misc/allwinner-h3-sysctrl.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_SYSCTRL,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
const hwaddr *memmap;
58
AwA10PITState timer;
59
AwH3ClockCtlState ccu;
60
+ AwH3SysCtrlState sysctrl;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner H3 System Control emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
27
+
89
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
28
+ /* Invoke the signal handler as if by indirect call. */
90
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
29
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
91
+
30
+ env->btype = 2;
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
94
+
95
+/**
96
+ * @name Constants
97
+ * @{
98
+ */
99
+
100
+/** Highest register address used by System Control device */
101
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
105
+ sizeof(uint32_t)) + 1)
106
+
107
+/** @} */
108
+
109
+/**
110
+ * @name Object model
111
+ * @{
112
+ */
113
+
114
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
115
+#define AW_H3_SYSCTRL(obj) \
116
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
117
+
118
+/** @} */
119
+
120
+/**
121
+ * Allwinner H3 System Control object instance state
122
+ */
123
+typedef struct AwH3SysCtrlState {
124
+ /*< private >*/
125
+ SysBusDevice parent_obj;
126
+ /*< public >*/
127
+
128
+ /** Maps I/O registers in physical memory */
129
+ MemoryRegion iomem;
130
+
131
+ /** Array of hardware registers */
132
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
133
+
134
+} AwH3SysCtrlState;
135
+
136
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
137
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/hw/arm/allwinner-h3.c
140
+++ b/hw/arm/allwinner-h3.c
141
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
142
[AW_H3_SRAM_A1] = 0x00000000,
143
[AW_H3_SRAM_A2] = 0x00044000,
144
[AW_H3_SRAM_C] = 0x00010000,
145
+ [AW_H3_SYSCTRL] = 0x01c00000,
146
[AW_H3_EHCI0] = 0x01c1a000,
147
[AW_H3_OHCI0] = 0x01c1a400,
148
[AW_H3_EHCI1] = 0x01c1b000,
149
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
150
} unimplemented[] = {
151
{ "d-engine", 0x01000000, 4 * MiB },
152
{ "d-inter", 0x01400000, 128 * KiB },
153
- { "syscon", 0x01c00000, 4 * KiB },
154
{ "dma", 0x01c02000, 4 * KiB },
155
{ "nfdc", 0x01c03000, 4 * KiB },
156
{ "ts", 0x01c06000, 4 * KiB },
157
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
158
159
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
160
TYPE_AW_H3_CCU);
161
+
162
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
163
+ TYPE_AW_H3_SYSCTRL);
164
}
165
166
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
168
qdev_init_nofail(DEVICE(&s->ccu));
169
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
170
171
+ /* System Control */
172
+ qdev_init_nofail(DEVICE(&s->sysctrl));
173
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
174
+
175
/* Universal Serial Bus */
176
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
177
qdev_get_gpio_in(DEVICE(&s->gic),
178
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
179
new file mode 100644
180
index XXXXXXX..XXXXXXX
181
--- /dev/null
182
+++ b/hw/misc/allwinner-h3-sysctrl.c
183
@@ -XXX,XX +XXX,XX @@
184
+/*
185
+ * Allwinner H3 System Control emulation
186
+ *
187
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
188
+ *
189
+ * This program is free software: you can redistribute it and/or modify
190
+ * it under the terms of the GNU General Public License as published by
191
+ * the Free Software Foundation, either version 2 of the License, or
192
+ * (at your option) any later version.
193
+ *
194
+ * This program is distributed in the hope that it will be useful,
195
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
196
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
197
+ * GNU General Public License for more details.
198
+ *
199
+ * You should have received a copy of the GNU General Public License
200
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
201
+ */
202
+
203
+#include "qemu/osdep.h"
204
+#include "qemu/units.h"
205
+#include "hw/sysbus.h"
206
+#include "migration/vmstate.h"
207
+#include "qemu/log.h"
208
+#include "qemu/module.h"
209
+#include "hw/misc/allwinner-h3-sysctrl.h"
210
+
211
+/* System Control register offsets */
212
+enum {
213
+ REG_VER = 0x24, /* Version */
214
+ REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
215
+};
216
+
217
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
218
+
219
+/* System Control register reset values */
220
+enum {
221
+ REG_VER_RST = 0x0,
222
+ REG_EMAC_PHY_CLK_RST = 0x58000,
223
+};
224
+
225
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
226
+ unsigned size)
227
+{
228
+ const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
229
+ const uint32_t idx = REG_INDEX(offset);
230
+
231
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
232
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
233
+ __func__, (uint32_t)offset);
234
+ return 0;
235
+ }
31
+ }
236
+
32
+
237
+ return s->regs[idx];
33
if (info) {
238
+}
34
tswap_siginfo(&frame->info, info);
239
+
35
env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
240
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
241
+ uint64_t val, unsigned size)
242
+{
243
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
244
+ const uint32_t idx = REG_INDEX(offset);
245
+
246
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
247
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
248
+ __func__, (uint32_t)offset);
249
+ return;
250
+ }
251
+
252
+ switch (offset) {
253
+ case REG_VER: /* Version */
254
+ break;
255
+ default:
256
+ s->regs[idx] = (uint32_t) val;
257
+ break;
258
+ }
259
+}
260
+
261
+static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
262
+ .read = allwinner_h3_sysctrl_read,
263
+ .write = allwinner_h3_sysctrl_write,
264
+ .endianness = DEVICE_NATIVE_ENDIAN,
265
+ .valid = {
266
+ .min_access_size = 4,
267
+ .max_access_size = 4,
268
+ },
269
+ .impl.min_access_size = 4,
270
+};
271
+
272
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
273
+{
274
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
275
+
276
+ /* Set default values for registers */
277
+ s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
278
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
279
+}
280
+
281
+static void allwinner_h3_sysctrl_init(Object *obj)
282
+{
283
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
284
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
285
+
286
+ /* Memory mapping */
287
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
288
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
289
+ sysbus_init_mmio(sbd, &s->iomem);
290
+}
291
+
292
+static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
293
+ .name = "allwinner-h3-sysctrl",
294
+ .version_id = 1,
295
+ .minimum_version_id = 1,
296
+ .fields = (VMStateField[]) {
297
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
298
+ VMSTATE_END_OF_LIST()
299
+ }
300
+};
301
+
302
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
303
+{
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
305
+
306
+ dc->reset = allwinner_h3_sysctrl_reset;
307
+ dc->vmsd = &allwinner_h3_sysctrl_vmstate;
308
+}
309
+
310
+static const TypeInfo allwinner_h3_sysctrl_info = {
311
+ .name = TYPE_AW_H3_SYSCTRL,
312
+ .parent = TYPE_SYS_BUS_DEVICE,
313
+ .instance_init = allwinner_h3_sysctrl_init,
314
+ .instance_size = sizeof(AwH3SysCtrlState),
315
+ .class_init = allwinner_h3_sysctrl_class_init,
316
+};
317
+
318
+static void allwinner_h3_sysctrl_register(void)
319
+{
320
+ type_register_static(&allwinner_h3_sysctrl_info);
321
+}
322
+
323
+type_init(allwinner_h3_sysctrl_register)
324
--
36
--
325
2.20.1
37
2.20.1
326
38
327
39
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We must include the tag in the FAR_ELx register when raising
3
Transform the prot bit to a qemu internal page bit, and save
4
an addressing exception. Which means that we should not clear
4
it in the page tables.
5
out the tag during translation.
6
5
7
We cannot at present comply with this for user mode, so we
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
retain the clean_data_tbi function for the moment, though it
9
no longer does what it says on the tin for system mode. This
10
function is to be replaced with MTE, so don't worry about the
11
slight misnaming.
12
13
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200308012946.16303-3-richard.henderson@linaro.org
8
Message-id: 20201016184207.786698-3-richard.henderson@linaro.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
10
---
19
target/arm/translate-a64.c | 11 +++++++++++
11
include/exec/cpu-all.h | 2 ++
20
1 file changed, 11 insertions(+)
12
linux-user/syscall_defs.h | 4 ++++
13
target/arm/cpu.h | 5 +++++
14
linux-user/mmap.c | 16 ++++++++++++++++
15
target/arm/translate-a64.c | 6 +++---
16
5 files changed, 30 insertions(+), 3 deletions(-)
21
17
18
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/exec/cpu-all.h
21
+++ b/include/exec/cpu-all.h
22
@@ -XXX,XX +XXX,XX @@ extern intptr_t qemu_host_page_mask;
23
/* FIXME: Code that sets/uses this is broken and needs to go away. */
24
#define PAGE_RESERVED 0x0020
25
#endif
26
+/* Target-specific bits that will be used via page_get_flags(). */
27
+#define PAGE_TARGET_1 0x0080
28
29
#if defined(CONFIG_USER_ONLY)
30
void page_dump(FILE *f);
31
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/linux-user/syscall_defs.h
34
+++ b/linux-user/syscall_defs.h
35
@@ -XXX,XX +XXX,XX @@ struct target_winsize {
36
#define TARGET_PROT_SEM 0x08
37
#endif
38
39
+#ifdef TARGET_AARCH64
40
+#define TARGET_PROT_BTI 0x10
41
+#endif
42
+
43
/* Common */
44
#define TARGET_MAP_SHARED    0x01        /* Share changes */
45
#define TARGET_MAP_PRIVATE    0x02        /* Changes are private */
46
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/cpu.h
49
+++ b/target/arm/cpu.h
50
@@ -XXX,XX +XXX,XX @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
51
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
52
#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
53
54
+/*
55
+ * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
56
+ */
57
+#define PAGE_BTI PAGE_TARGET_1
58
+
59
/*
60
* Naming convention for isar_feature functions:
61
* Functions which test 32-bit ID registers should have _aa32_ in
62
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/linux-user/mmap.c
65
+++ b/linux-user/mmap.c
66
@@ -XXX,XX +XXX,XX @@ static int validate_prot_to_pageflags(int *host_prot, int prot)
67
*host_prot = (prot & (PROT_READ | PROT_WRITE))
68
| (prot & PROT_EXEC ? PROT_READ : 0);
69
70
+#ifdef TARGET_AARCH64
71
+ /*
72
+ * The PROT_BTI bit is only accepted if the cpu supports the feature.
73
+ * Since this is the unusual case, don't bother checking unless
74
+ * the bit has been requested. If set and valid, record the bit
75
+ * within QEMU's page_flags.
76
+ */
77
+ if (prot & TARGET_PROT_BTI) {
78
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
79
+ if (cpu_isar_feature(aa64_bti, cpu)) {
80
+ valid |= TARGET_PROT_BTI;
81
+ page_flags |= PAGE_BTI;
82
+ }
83
+ }
84
+#endif
85
+
86
return prot & ~valid ? 0 : page_flags;
87
}
88
22
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
89
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
index XXXXXXX..XXXXXXX 100644
90
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-a64.c
91
--- a/target/arm/translate-a64.c
25
+++ b/target/arm/translate-a64.c
92
+++ b/target/arm/translate-a64.c
26
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
93
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
27
static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
94
*/
95
static bool is_guarded_page(CPUARMState *env, DisasContext *s)
28
{
96
{
29
TCGv_i64 clean = new_tmp_a64(s);
97
-#ifdef CONFIG_USER_ONLY
30
+ /*
98
- return false; /* FIXME */
31
+ * In order to get the correct value in the FAR_ELx register,
99
-#else
32
+ * we must present the memory subsystem with the "dirty" address
100
uint64_t addr = s->base.pc_first;
33
+ * including the TBI. In system mode we can make this work via
34
+ * the TLB, dropping the TBI during translation. But for user-only
35
+ * mode we don't have that option, and must remove the top byte now.
36
+ */
37
+#ifdef CONFIG_USER_ONLY
101
+#ifdef CONFIG_USER_ONLY
38
gen_top_byte_ignore(s, clean, addr, s->tbid);
102
+ return page_get_flags(addr) & PAGE_BTI;
39
+#else
103
+#else
40
+ tcg_gen_mov_i64(clean, addr);
104
int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
41
+#endif
105
unsigned int index = tlb_index(env, mmu_idx, addr);
42
return clean;
106
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
43
}
44
45
--
107
--
46
2.20.1
108
2.20.1
47
109
48
110
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert kvm_arm_vgic_probe() so that it returns a
3
These are all of the defines required to parse
4
bitmap of supported in-kernel emulation VGIC versions instead
4
GNU_PROPERTY_AARCH64_FEATURE_1_AND, copied from binutils.
5
of the max version: at the moment values can be v2 and v3.
5
Other missing defines related to other GNU program headers
6
This allows to expose the case where the host GICv3 also
6
and notes are elided for now.
7
supports GICv2 emulation. This will be useful to choose the
8
default version in KVM accelerated mode.
9
7
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20201016184207.786698-4-richard.henderson@linaro.org
13
Message-id: 20200311131618.7187-5-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
target/arm/kvm_arm.h | 3 +++
13
include/elf.h | 22 ++++++++++++++++++++++
17
hw/arm/virt.c | 11 +++++++++--
14
1 file changed, 22 insertions(+)
18
target/arm/kvm.c | 14 ++++++++------
19
3 files changed, 20 insertions(+), 8 deletions(-)
20
15
21
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
16
diff --git a/include/elf.h b/include/elf.h
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/kvm_arm.h
18
--- a/include/elf.h
24
+++ b/target/arm/kvm_arm.h
19
+++ b/include/elf.h
25
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ typedef int64_t Elf64_Sxword;
26
#include "exec/memory.h"
21
#define PT_NOTE 4
27
#include "qemu/error-report.h"
22
#define PT_SHLIB 5
28
23
#define PT_PHDR 6
29
+#define KVM_ARM_VGIC_V2 (1 << 0)
24
+#define PT_LOOS 0x60000000
30
+#define KVM_ARM_VGIC_V3 (1 << 1)
25
+#define PT_HIOS 0x6fffffff
26
#define PT_LOPROC 0x70000000
27
#define PT_HIPROC 0x7fffffff
28
29
+#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
31
+
30
+
32
/**
31
#define PT_MIPS_REGINFO 0x70000000
33
* kvm_arm_vcpu_init:
32
#define PT_MIPS_RTPROC 0x70000001
34
* @cs: CPUState
33
#define PT_MIPS_OPTIONS 0x70000002
35
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
34
@@ -XXX,XX +XXX,XX @@ typedef struct elf64_shdr {
36
index XXXXXXX..XXXXXXX 100644
35
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
37
--- a/hw/arm/virt.c
36
#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */
38
+++ b/hw/arm/virt.c
37
39
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
38
+/* Defined note types for GNU systems. */
40
vms->gic_version = VIRT_GIC_VERSION_3;
41
}
42
} else {
43
- vms->gic_version = kvm_arm_vgic_probe();
44
- if (!vms->gic_version) {
45
+ int probe_bitmap = kvm_arm_vgic_probe();
46
+
39
+
47
+ if (!probe_bitmap) {
40
+#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */
48
error_report(
49
"Unable to determine GIC version supported by host");
50
exit(1);
51
+ } else {
52
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
53
+ vms->gic_version = VIRT_GIC_VERSION_3;
54
+ } else {
55
+ vms->gic_version = VIRT_GIC_VERSION_2;
56
+ }
57
}
58
}
59
} else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
60
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/kvm.c
63
+++ b/target/arm/kvm.c
64
@@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s)
65
66
int kvm_arm_vgic_probe(void)
67
{
68
+ int val = 0;
69
+
41
+
70
if (kvm_create_device(kvm_state,
42
+/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */
71
KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
43
+
72
- return 3;
44
+#define GNU_PROPERTY_STACK_SIZE 1
73
- } else if (kvm_create_device(kvm_state,
45
+#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
74
- KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
46
+
75
- return 2;
47
+#define GNU_PROPERTY_LOPROC 0xc0000000
76
- } else {
48
+#define GNU_PROPERTY_HIPROC 0xdfffffff
77
- return 0;
49
+#define GNU_PROPERTY_LOUSER 0xe0000000
78
+ val |= KVM_ARM_VGIC_V3;
50
+#define GNU_PROPERTY_HIUSER 0xffffffff
79
}
51
+
80
+ if (kvm_create_device(kvm_state,
52
+#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
81
+ KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
53
+#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0)
82
+ val |= KVM_ARM_VGIC_V2;
54
+#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1)
83
+ }
55
+
84
+ return val;
56
/*
85
}
57
* Physical entry point into the kernel.
86
58
*
87
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level)
88
--
59
--
89
2.20.1
60
2.20.1
90
61
91
62
diff view generated by jsdifflib
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
SOC object returned by object_new() is leaked in current code.
3
Fix an unlikely memory leak in load_elf_image().
4
Set SOC parent explicitly to board and then unref to SOC object
5
to make sure that refererence returned by object_new() is taken
6
care of.
7
4
8
The SOC object will be kept alive by its parent (machine) and
5
Fixes: bf858897b7 ("linux-user: Re-use load_elf_image for the main binary.")
9
will be automatically freed when MachineState is destroyed.
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
8
Message-id: 20201016184207.786698-5-richard.henderson@linaro.org
12
Reported-by: Andrew Jones <drjones@redhat.com>
9
Message-Id: <20201003174944.1972444-1-f4bug@amsat.org>
13
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200303091254.22373-1-imammedo@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
13
---
18
hw/arm/cubieboard.c | 3 +++
14
linux-user/elfload.c | 8 ++++----
19
1 file changed, 3 insertions(+)
15
1 file changed, 4 insertions(+), 4 deletions(-)
20
16
21
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
17
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/cubieboard.c
19
--- a/linux-user/elfload.c
24
+++ b/hw/arm/cubieboard.c
20
+++ b/linux-user/elfload.c
25
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
21
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
22
info->brk = vaddr_em;
23
}
24
} else if (eppnt->p_type == PT_INTERP && pinterp_name) {
25
- char *interp_name;
26
+ g_autofree char *interp_name = NULL;
27
28
if (*pinterp_name) {
29
errmsg = "Multiple PT_INTERP entries";
30
goto exit_errmsg;
31
}
32
- interp_name = malloc(eppnt->p_filesz);
33
+ interp_name = g_malloc(eppnt->p_filesz);
34
if (!interp_name) {
35
goto exit_perror;
36
}
37
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
38
errmsg = "Invalid PT_INTERP entry";
39
goto exit_errmsg;
40
}
41
- *pinterp_name = interp_name;
42
+ *pinterp_name = g_steal_pointer(&interp_name);
43
#ifdef TARGET_MIPS
44
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
45
Mips_elf_abiflags_v0 abiflags;
46
@@ -XXX,XX +XXX,XX @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info)
47
if (elf_interpreter) {
48
info->load_bias = interp_info.load_bias;
49
info->entry = interp_info.entry;
50
- free(elf_interpreter);
51
+ g_free(elf_interpreter);
26
}
52
}
27
53
28
a10 = AW_A10(object_new(TYPE_AW_A10));
54
#ifdef USE_ELF_CORE_DUMP
29
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),
30
+ &error_abort);
31
+ object_unref(OBJECT(a10));
32
33
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
34
if (err != NULL) {
35
--
55
--
36
2.20.1
56
2.20.1
37
57
38
58
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Xunlong Orange Pi PC machine is a functional ARM machine
3
Fixing this now will clarify following patches.
4
based on the Allwinner H3 System-on-Chip. It supports mainline
5
Linux, U-Boot, NetBSD and is covered by acceptance tests.
6
4
7
This commit adds a documentation text file with a description
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
of the machine and instructions for the user.
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
7
Message-id: 20201016184207.786698-6-richard.henderson@linaro.org
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com
13
[PMM: moved file into docs/system/arm to match the reorg
14
of the arm target part of the docs; tweaked heading to
15
match other boards]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
9
---
18
MAINTAINERS | 1 +
10
linux-user/elfload.c | 12 +++++++++---
19
docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++
11
1 file changed, 9 insertions(+), 3 deletions(-)
20
docs/system/target-arm.rst | 2 +
21
3 files changed, 256 insertions(+)
22
create mode 100644 docs/system/arm/orangepi.rst
23
12
24
diff --git a/MAINTAINERS b/MAINTAINERS
13
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
15
--- a/linux-user/elfload.c
27
+++ b/MAINTAINERS
16
+++ b/linux-user/elfload.c
28
@@ -XXX,XX +XXX,XX @@ S: Maintained
17
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
29
F: hw/*/allwinner-h3*
18
abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em, vaddr_len;
30
F: include/hw/*/allwinner-h3*
19
int elf_prot = 0;
31
F: hw/arm/orangepi.c
20
32
+F: docs/system/orangepi.rst
21
- if (eppnt->p_flags & PF_R) elf_prot = PROT_READ;
33
22
- if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE;
34
ARM PrimeCell and CMSDK devices
23
- if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC;
35
M: Peter Maydell <peter.maydell@linaro.org>
24
+ if (eppnt->p_flags & PF_R) {
36
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
25
+ elf_prot |= PROT_READ;
37
new file mode 100644
26
+ }
38
index XXXXXXX..XXXXXXX
27
+ if (eppnt->p_flags & PF_W) {
39
--- /dev/null
28
+ elf_prot |= PROT_WRITE;
40
+++ b/docs/system/arm/orangepi.rst
29
+ }
41
@@ -XXX,XX +XXX,XX @@
30
+ if (eppnt->p_flags & PF_X) {
42
+Orange Pi PC (``orangepi-pc``)
31
+ elf_prot |= PROT_EXEC;
43
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
32
+ }
44
+
33
45
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
34
vaddr = load_bias + eppnt->p_vaddr;
46
+based embedded computer with mainline support in both U-Boot
35
vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
47
+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
48
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
49
+various other I/O.
50
+
51
+Supported devices
52
+"""""""""""""""""
53
+
54
+The Orange Pi PC machine supports the following devices:
55
+
56
+ * SMP (Quad Core Cortex-A7)
57
+ * Generic Interrupt Controller configuration
58
+ * SRAM mappings
59
+ * SDRAM controller
60
+ * Real Time Clock
61
+ * Timer device (re-used from Allwinner A10)
62
+ * UART
63
+ * SD/MMC storage controller
64
+ * EMAC ethernet
65
+ * USB 2.0 interfaces
66
+ * Clock Control Unit
67
+ * System Control module
68
+ * Security Identifier device
69
+
70
+Limitations
71
+"""""""""""
72
+
73
+Currently, Orange Pi PC does *not* support the following features:
74
+
75
+- Graphical output via HDMI, GPU and/or the Display Engine
76
+- Audio output
77
+- Hardware Watchdog
78
+
79
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
80
+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``
81
+
82
+Boot options
83
+""""""""""""
84
+
85
+The Orange Pi PC machine can start using the standard -kernel functionality
86
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC
87
+machine can also emulate the BootROM which is present on an actual Allwinner H3
88
+based SoC, which loads the bootloader from a SD card, specified via the -sd argument
89
+to qemu-system-arm.
90
+
91
+Machine-specific options
92
+""""""""""""""""""""""""
93
+
94
+The following machine-specific options are supported:
95
+
96
+- allwinner-rtc.base-year=YYYY
97
+
98
+ The Allwinner RTC device is automatically created by the Orange Pi PC machine
99
+ and uses a default base year value which can be overridden using the 'base-year' property.
100
+ The base year is the actual represented year when the RTC year value is zero.
101
+ This option can be used in case the target operating system driver uses a different
102
+ base year value. The minimum value for the base year is 1900.
103
+
104
+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff
105
+
106
+ The Security Identifier value can be read by the guest.
107
+ For example, U-Boot uses it to determine a unique MAC address.
108
+
109
+The above machine-specific options can be specified in qemu-system-arm
110
+via the '-global' argument, for example:
111
+
112
+.. code-block:: bash
113
+
114
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
115
+ -global allwinner-rtc.base-year=2000
116
+
117
+Running mainline Linux
118
+""""""""""""""""""""""
119
+
120
+Mainline Linux kernels from 4.19 up to latest master are known to work.
121
+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,
122
+simply configure the kernel using the sunxi_defconfig configuration:
123
+
124
+.. code-block:: bash
125
+
126
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper
127
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig
128
+
129
+To be able to use USB storage, you need to manually enable the corresponding
130
+configuration item. Start the kconfig configuration tool:
131
+
132
+.. code-block:: bash
133
+
134
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig
135
+
136
+Navigate to the following item, enable it and save your configuration:
137
+
138
+ Device Drivers > USB support > USB Mass Storage support
139
+
140
+Build the Linux kernel with:
141
+
142
+.. code-block:: bash
143
+
144
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make
145
+
146
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:
147
+
148
+.. code-block:: bash
149
+
150
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
151
+ -kernel /path/to/linux/arch/arm/boot/zImage \
152
+ -append 'console=ttyS0,115200' \
153
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
154
+
155
+Orange Pi PC images
156
+"""""""""""""""""""
157
+
158
+Note that the mainline kernel does not have a root filesystem. You may provide it
159
+with an official Orange Pi PC image from the official website:
160
+
161
+ http://www.orangepi.org/downloadresources/
162
+
163
+Another possibility is to run an Armbian image for Orange Pi PC which
164
+can be downloaded from:
165
+
166
+ https://www.armbian.com/orange-pi-pc/
167
+
168
+Alternatively, you can also choose to build you own image with buildroot
169
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.
170
+
171
+You can choose to attach the selected image either as an SD card or as USB mass storage.
172
+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd
173
+argument and provide the proper root= kernel parameter:
174
+
175
+.. code-block:: bash
176
+
177
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
178
+ -kernel /path/to/linux/arch/arm/boot/zImage \
179
+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \
180
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
181
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
182
+
183
+To attach the image as an USB mass storage device to the machine,
184
+simply append to the command:
185
+
186
+.. code-block:: bash
187
+
188
+ -drive if=none,id=stick,file=myimage.img \
189
+ -device usb-storage,bus=usb-bus.0,drive=stick
190
+
191
+Instead of providing a custom Linux kernel via the -kernel command you may also
192
+choose to let the Orange Pi PC machine load the bootloader from SD card, just like
193
+a real board would do using the BootROM. Simply pass the selected image via the -sd
194
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
195
+
196
+.. code-block:: bash
197
+
198
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
199
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
200
+
201
+Note that both the official Orange Pi PC images and Armbian images start
202
+a lot of userland programs via systemd. Depending on the host hardware and OS,
203
+they may be slow to emulate, especially due to emulating the 4 cores.
204
+To help reduce the performance slow down due to emulating the 4 cores, you can
205
+give the following kernel parameters via U-Boot (or via -append):
206
+
207
+.. code-block:: bash
208
+
209
+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'
210
+
211
+Running U-Boot
212
+""""""""""""""
213
+
214
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
215
+using similar commands as describe above for Linux. Note that it is recommended
216
+for development/testing to select the following configuration setting in U-Boot:
217
+
218
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
219
+
220
+To start U-Boot using the Orange Pi PC machine, provide the
221
+u-boot binary to the -kernel argument:
222
+
223
+.. code-block:: bash
224
+
225
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
226
+ -kernel /path/to/uboot/u-boot -sd disk.img
227
+
228
+Use the following U-boot commands to load and boot a Linux kernel from SD card:
229
+
230
+.. code-block:: bash
231
+
232
+ => setenv bootargs console=ttyS0,115200
233
+ => ext2load mmc 0 0x42000000 zImage
234
+ => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
235
+ => bootz 0x42000000 - 0x43000000
236
+
237
+Running NetBSD
238
+""""""""""""""
239
+
240
+The NetBSD operating system also includes support for Allwinner H3 based boards,
241
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC
242
+board and provides a fully working system with serial console, networking and storage.
243
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
244
+
245
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz
246
+
247
+The image requires manually installing U-Boot in the image. Build U-Boot with
248
+the orangepi_pc_defconfig configuration as described in the previous section.
249
+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:
250
+
251
+.. code-block:: bash
252
+
253
+ $ gunzip armv7.img.gz
254
+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc
255
+
256
+Finally, before starting the machine the SD image must be extended such
257
+that the NetBSD kernel will not conclude the NetBSD partition is larger than
258
+the emulated SD card:
259
+
260
+.. code-block:: bash
261
+
262
+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img
263
+
264
+Start the machine using the following command:
265
+
266
+.. code-block:: bash
267
+
268
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
269
+ -sd armv7.img -global allwinner-rtc.base-year=2000
270
+
271
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
272
+and set the following environment variables before booting:
273
+
274
+.. code-block:: bash
275
+
276
+ => setenv bootargs root=ld0a
277
+ => setenv kernel netbsd-GENERIC.ub
278
+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
279
+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'
280
+
281
+Optionally you may save the environment variables to SD card with 'saveenv'.
282
+To continue booting simply give the 'boot' command and NetBSD boots.
283
+
284
+Orange Pi PC acceptance tests
285
+"""""""""""""""""""""""""""""
286
+
287
+The Orange Pi PC machine has several acceptance tests included.
288
+To run the whole set of tests, build QEMU from source and simply
289
+provide the following command:
290
+
291
+.. code-block:: bash
292
+
293
+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \
294
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
295
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
296
index XXXXXXX..XXXXXXX 100644
297
--- a/docs/system/target-arm.rst
298
+++ b/docs/system/target-arm.rst
299
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
300
``qemu-system-aarch64 --machine help``.
301
302
.. toctree::
303
+ :maxdepth: 1
304
305
arm/integratorcp
306
arm/versatile
307
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
308
arm/stellaris
309
arm/musicpal
310
arm/sx1
311
+ arm/orangepi
312
313
Arm CPU features
314
================
315
--
36
--
316
2.20.1
37
2.20.1
317
38
318
39
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
3
The second loop uses a loop induction variable, and the first
4
which provides 10M/100M/1000M Ethernet connectivity. This commit
4
does not. Transform the first to match the second, to simplify
5
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
5
a following patch moving code between them.
6
including emulation for the following functionality:
7
6
8
* DMA transfers
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
* MII interface
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
* Transmit CRC calculation
9
Message-id: 20201016184207.786698-7-richard.henderson@linaro.org
11
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
11
---
17
hw/net/Makefile.objs | 1 +
12
linux-user/elfload.c | 9 +++++----
18
include/hw/arm/allwinner-h3.h | 3 +
13
1 file changed, 5 insertions(+), 4 deletions(-)
19
include/hw/net/allwinner-sun8i-emac.h | 99 +++
20
hw/arm/allwinner-h3.c | 16 +-
21
hw/arm/orangepi.c | 3 +
22
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
23
hw/arm/Kconfig | 1 +
24
hw/net/Kconfig | 3 +
25
hw/net/trace-events | 10 +
26
9 files changed, 1006 insertions(+), 1 deletion(-)
27
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
28
create mode 100644 hw/net/allwinner-sun8i-emac.c
29
14
30
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
15
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
31
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/net/Makefile.objs
17
--- a/linux-user/elfload.c
33
+++ b/hw/net/Makefile.objs
18
+++ b/linux-user/elfload.c
34
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
19
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
35
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
20
loaddr = -1, hiaddr = 0;
36
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
21
info->alignment = 0;
37
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
22
for (i = 0; i < ehdr->e_phnum; ++i) {
38
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
23
- if (phdr[i].p_type == PT_LOAD) {
39
common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
24
- abi_ulong a = phdr[i].p_vaddr - phdr[i].p_offset;
40
25
+ struct elf_phdr *eppnt = phdr + i;
41
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
26
+ if (eppnt->p_type == PT_LOAD) {
42
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
27
+ abi_ulong a = eppnt->p_vaddr - eppnt->p_offset;
43
index XXXXXXX..XXXXXXX 100644
28
if (a < loaddr) {
44
--- a/include/hw/arm/allwinner-h3.h
29
loaddr = a;
45
+++ b/include/hw/arm/allwinner-h3.h
30
}
46
@@ -XXX,XX +XXX,XX @@
31
- a = phdr[i].p_vaddr + phdr[i].p_memsz;
47
#include "hw/misc/allwinner-h3-sysctrl.h"
32
+ a = eppnt->p_vaddr + eppnt->p_memsz;
48
#include "hw/misc/allwinner-sid.h"
33
if (a > hiaddr) {
49
#include "hw/sd/allwinner-sdhost.h"
34
hiaddr = a;
50
+#include "hw/net/allwinner-sun8i-emac.h"
35
}
51
#include "target/arm/cpu.h"
36
++info->nsegs;
52
37
- info->alignment |= phdr[i].p_align;
53
/**
38
+ info->alignment |= eppnt->p_align;
54
@@ -XXX,XX +XXX,XX @@ enum {
39
}
55
AW_H3_UART1,
56
AW_H3_UART2,
57
AW_H3_UART3,
58
+ AW_H3_EMAC,
59
AW_H3_GIC_DIST,
60
AW_H3_GIC_CPU,
61
AW_H3_GIC_HYP,
62
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
63
AwH3SysCtrlState sysctrl;
64
AwSidState sid;
65
AwSdHostState mmc0;
66
+ AwSun8iEmacState emac;
67
GICState gic;
68
MemoryRegion sram_a1;
69
MemoryRegion sram_a2;
70
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
71
new file mode 100644
72
index XXXXXXX..XXXXXXX
73
--- /dev/null
74
+++ b/include/hw/net/allwinner-sun8i-emac.h
75
@@ -XXX,XX +XXX,XX @@
76
+/*
77
+ * Allwinner Sun8i Ethernet MAC emulation
78
+ *
79
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
80
+ *
81
+ * This program is free software: you can redistribute it and/or modify
82
+ * it under the terms of the GNU General Public License as published by
83
+ * the Free Software Foundation, either version 2 of the License, or
84
+ * (at your option) any later version.
85
+ *
86
+ * This program is distributed in the hope that it will be useful,
87
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
88
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89
+ * GNU General Public License for more details.
90
+ *
91
+ * You should have received a copy of the GNU General Public License
92
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
93
+ */
94
+
95
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
96
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
97
+
98
+#include "qom/object.h"
99
+#include "net/net.h"
100
+#include "hw/sysbus.h"
101
+
102
+/**
103
+ * Object model
104
+ * @{
105
+ */
106
+
107
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
108
+#define AW_SUN8I_EMAC(obj) \
109
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
110
+
111
+/** @} */
112
+
113
+/**
114
+ * Allwinner Sun8i EMAC object instance state
115
+ */
116
+typedef struct AwSun8iEmacState {
117
+ /*< private >*/
118
+ SysBusDevice parent_obj;
119
+ /*< public >*/
120
+
121
+ /** Maps I/O registers in physical memory */
122
+ MemoryRegion iomem;
123
+
124
+ /** Interrupt output signal to notify CPU */
125
+ qemu_irq irq;
126
+
127
+ /** Generic Network Interface Controller (NIC) for networking API */
128
+ NICState *nic;
129
+
130
+ /** Generic Network Interface Controller (NIC) configuration */
131
+ NICConf conf;
132
+
133
+ /**
134
+ * @name Media Independent Interface (MII)
135
+ * @{
136
+ */
137
+
138
+ uint8_t mii_phy_addr; /**< PHY address */
139
+ uint32_t mii_cr; /**< Control */
140
+ uint32_t mii_st; /**< Status */
141
+ uint32_t mii_adv; /**< Advertised Abilities */
142
+
143
+ /** @} */
144
+
145
+ /**
146
+ * @name Hardware Registers
147
+ * @{
148
+ */
149
+
150
+ uint32_t basic_ctl0; /**< Basic Control 0 */
151
+ uint32_t basic_ctl1; /**< Basic Control 1 */
152
+ uint32_t int_en; /**< Interrupt Enable */
153
+ uint32_t int_sta; /**< Interrupt Status */
154
+ uint32_t frm_flt; /**< Receive Frame Filter */
155
+
156
+ uint32_t rx_ctl0; /**< Receive Control 0 */
157
+ uint32_t rx_ctl1; /**< Receive Control 1 */
158
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
159
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
160
+
161
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
162
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
163
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
164
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
165
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
166
+
167
+ uint32_t mii_cmd; /**< Management Interface Command */
168
+ uint32_t mii_data; /**< Management Interface Data */
169
+
170
+ /** @} */
171
+
172
+} AwSun8iEmacState;
173
+
174
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
175
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/arm/allwinner-h3.c
178
+++ b/hw/arm/allwinner-h3.c
179
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
180
[AW_H3_UART1] = 0x01c28400,
181
[AW_H3_UART2] = 0x01c28800,
182
[AW_H3_UART3] = 0x01c28c00,
183
+ [AW_H3_EMAC] = 0x01c30000,
184
[AW_H3_GIC_DIST] = 0x01c81000,
185
[AW_H3_GIC_CPU] = 0x01c82000,
186
[AW_H3_GIC_HYP] = 0x01c84000,
187
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
188
{ "twi1", 0x01c2b000, 1 * KiB },
189
{ "twi2", 0x01c2b400, 1 * KiB },
190
{ "scr", 0x01c2c400, 1 * KiB },
191
- { "emac", 0x01c30000, 64 * KiB },
192
{ "gpu", 0x01c40000, 64 * KiB },
193
{ "hstmr", 0x01c60000, 4 * KiB },
194
{ "dramcom", 0x01c62000, 4 * KiB },
195
@@ -XXX,XX +XXX,XX @@ enum {
196
AW_H3_GIC_SPI_OHCI2 = 77,
197
AW_H3_GIC_SPI_EHCI3 = 78,
198
AW_H3_GIC_SPI_OHCI3 = 79,
199
+ AW_H3_GIC_SPI_EMAC = 82
200
};
201
202
/* Allwinner H3 general constants */
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
206
TYPE_AW_SDHOST_SUN5I);
207
+
208
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
209
+ TYPE_AW_SUN8I_EMAC);
210
}
211
212
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
213
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
214
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
215
"sd-bus", &error_abort);
216
217
+ /* EMAC */
218
+ if (nd_table[0].used) {
219
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
220
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
221
+ }
222
+ qdev_init_nofail(DEVICE(&s->emac));
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
224
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
225
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
226
+
227
/* Universal Serial Bus */
228
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
229
qdev_get_gpio_in(DEVICE(&s->gic),
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
warn_report("Security Identifier value does not include H3 prefix");
236
}
40
}
237
41
238
+ /* Setup EMAC properties */
239
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
240
+
241
/* Mark H3 object realized */
242
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
243
244
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
245
new file mode 100644
246
index XXXXXXX..XXXXXXX
247
--- /dev/null
248
+++ b/hw/net/allwinner-sun8i-emac.c
249
@@ -XXX,XX +XXX,XX @@
250
+/*
251
+ * Allwinner Sun8i Ethernet MAC emulation
252
+ *
253
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
254
+ *
255
+ * This program is free software: you can redistribute it and/or modify
256
+ * it under the terms of the GNU General Public License as published by
257
+ * the Free Software Foundation, either version 2 of the License, or
258
+ * (at your option) any later version.
259
+ *
260
+ * This program is distributed in the hope that it will be useful,
261
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
262
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
263
+ * GNU General Public License for more details.
264
+ *
265
+ * You should have received a copy of the GNU General Public License
266
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
267
+ */
268
+
269
+#include "qemu/osdep.h"
270
+#include "qemu/units.h"
271
+#include "hw/sysbus.h"
272
+#include "migration/vmstate.h"
273
+#include "net/net.h"
274
+#include "hw/irq.h"
275
+#include "hw/qdev-properties.h"
276
+#include "qemu/log.h"
277
+#include "trace.h"
278
+#include "net/checksum.h"
279
+#include "qemu/module.h"
280
+#include "exec/cpu-common.h"
281
+#include "hw/net/allwinner-sun8i-emac.h"
282
+
283
+/* EMAC register offsets */
284
+enum {
285
+ REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */
286
+ REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */
287
+ REG_INT_STA = 0x0008, /* Interrupt Status */
288
+ REG_INT_EN = 0x000C, /* Interrupt Enable */
289
+ REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
290
+ REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
291
+ REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
292
+ REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
293
+ REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
294
+ REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
295
+ REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
296
+ REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
297
+ REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
298
+ REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
299
+ REG_MII_CMD = 0x0048, /* Management Interface Command */
300
+ REG_MII_DATA = 0x004C, /* Management Interface Data */
301
+ REG_ADDR_HIGH = 0x0050, /* MAC Address High */
302
+ REG_ADDR_LOW = 0x0054, /* MAC Address Low */
303
+ REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
304
+ REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
305
+ REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
306
+ REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
307
+ REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
308
+ REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
309
+ REG_RGMII_STA = 0x00D0, /* RGMII Status */
310
+};
311
+
312
+/* EMAC register flags */
313
+enum {
314
+ BASIC_CTL0_100Mbps = (0b11 << 2),
315
+ BASIC_CTL0_FD = (1 << 0),
316
+ BASIC_CTL1_SOFTRST = (1 << 0),
317
+};
318
+
319
+enum {
320
+ INT_STA_RGMII_LINK = (1 << 16),
321
+ INT_STA_RX_EARLY = (1 << 13),
322
+ INT_STA_RX_OVERFLOW = (1 << 12),
323
+ INT_STA_RX_TIMEOUT = (1 << 11),
324
+ INT_STA_RX_DMA_STOP = (1 << 10),
325
+ INT_STA_RX_BUF_UA = (1 << 9),
326
+ INT_STA_RX = (1 << 8),
327
+ INT_STA_TX_EARLY = (1 << 5),
328
+ INT_STA_TX_UNDERFLOW = (1 << 4),
329
+ INT_STA_TX_TIMEOUT = (1 << 3),
330
+ INT_STA_TX_BUF_UA = (1 << 2),
331
+ INT_STA_TX_DMA_STOP = (1 << 1),
332
+ INT_STA_TX = (1 << 0),
333
+};
334
+
335
+enum {
336
+ INT_EN_RX_EARLY = (1 << 13),
337
+ INT_EN_RX_OVERFLOW = (1 << 12),
338
+ INT_EN_RX_TIMEOUT = (1 << 11),
339
+ INT_EN_RX_DMA_STOP = (1 << 10),
340
+ INT_EN_RX_BUF_UA = (1 << 9),
341
+ INT_EN_RX = (1 << 8),
342
+ INT_EN_TX_EARLY = (1 << 5),
343
+ INT_EN_TX_UNDERFLOW = (1 << 4),
344
+ INT_EN_TX_TIMEOUT = (1 << 3),
345
+ INT_EN_TX_BUF_UA = (1 << 2),
346
+ INT_EN_TX_DMA_STOP = (1 << 1),
347
+ INT_EN_TX = (1 << 0),
348
+};
349
+
350
+enum {
351
+ TX_CTL0_TX_EN = (1 << 31),
352
+ TX_CTL1_TX_DMA_START = (1 << 31),
353
+ TX_CTL1_TX_DMA_EN = (1 << 30),
354
+ TX_CTL1_TX_FLUSH = (1 << 0),
355
+};
356
+
357
+enum {
358
+ RX_CTL0_RX_EN = (1 << 31),
359
+ RX_CTL0_STRIP_FCS = (1 << 28),
360
+ RX_CTL0_CRC_IPV4 = (1 << 27),
361
+};
362
+
363
+enum {
364
+ RX_CTL1_RX_DMA_START = (1 << 31),
365
+ RX_CTL1_RX_DMA_EN = (1 << 30),
366
+ RX_CTL1_RX_MD = (1 << 1),
367
+};
368
+
369
+enum {
370
+ RX_FRM_FLT_DIS_ADDR = (1 << 31),
371
+};
372
+
373
+enum {
374
+ MII_CMD_PHY_ADDR_SHIFT = (12),
375
+ MII_CMD_PHY_ADDR_MASK = (0xf000),
376
+ MII_CMD_PHY_REG_SHIFT = (4),
377
+ MII_CMD_PHY_REG_MASK = (0xf0),
378
+ MII_CMD_PHY_RW = (1 << 1),
379
+ MII_CMD_PHY_BUSY = (1 << 0),
380
+};
381
+
382
+enum {
383
+ TX_DMA_STA_STOP = (0b000),
384
+ TX_DMA_STA_RUN_FETCH = (0b001),
385
+ TX_DMA_STA_WAIT_STA = (0b010),
386
+};
387
+
388
+enum {
389
+ RX_DMA_STA_STOP = (0b000),
390
+ RX_DMA_STA_RUN_FETCH = (0b001),
391
+ RX_DMA_STA_WAIT_FRM = (0b011),
392
+};
393
+
394
+/* EMAC register reset values */
395
+enum {
396
+ REG_BASIC_CTL_1_RST = 0x08000000,
397
+};
398
+
399
+/* EMAC constants */
400
+enum {
401
+ AW_SUN8I_EMAC_MIN_PKT_SZ = 64
402
+};
403
+
404
+/* Transmit/receive frame descriptor */
405
+typedef struct FrameDescriptor {
406
+ uint32_t status;
407
+ uint32_t status2;
408
+ uint32_t addr;
409
+ uint32_t next;
410
+} FrameDescriptor;
411
+
412
+/* Frame descriptor flags */
413
+enum {
414
+ DESC_STATUS_CTL = (1 << 31),
415
+ DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
416
+};
417
+
418
+/* Transmit frame descriptor flags */
419
+enum {
420
+ TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
421
+ TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
422
+ TX_DESC_STATUS2_LAST_DESC = (1 << 30),
423
+ TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
424
+};
425
+
426
+/* Receive frame descriptor flags */
427
+enum {
428
+ RX_DESC_STATUS_FIRST_DESC = (1 << 9),
429
+ RX_DESC_STATUS_LAST_DESC = (1 << 8),
430
+ RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
431
+ RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
432
+ RX_DESC_STATUS_NO_BUF = (1 << 14),
433
+ RX_DESC_STATUS_HEADER_ERR = (1 << 7),
434
+ RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
435
+ RX_DESC_STATUS_CRC_ERR = (1 << 1),
436
+ RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
437
+ RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
438
+};
439
+
440
+/* MII register offsets */
441
+enum {
442
+ MII_REG_CR = (0x0), /* Control */
443
+ MII_REG_ST = (0x1), /* Status */
444
+ MII_REG_ID_HIGH = (0x2), /* Identifier High */
445
+ MII_REG_ID_LOW = (0x3), /* Identifier Low */
446
+ MII_REG_ADV = (0x4), /* Advertised abilities */
447
+ MII_REG_LPA = (0x5), /* Link partner abilities */
448
+};
449
+
450
+/* MII register flags */
451
+enum {
452
+ MII_REG_CR_RESET = (1 << 15),
453
+ MII_REG_CR_POWERDOWN = (1 << 11),
454
+ MII_REG_CR_10Mbit = (0),
455
+ MII_REG_CR_100Mbit = (1 << 13),
456
+ MII_REG_CR_1000Mbit = (1 << 6),
457
+ MII_REG_CR_AUTO_NEG = (1 << 12),
458
+ MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
459
+ MII_REG_CR_FULLDUPLEX = (1 << 8),
460
+};
461
+
462
+enum {
463
+ MII_REG_ST_100BASE_T4 = (1 << 15),
464
+ MII_REG_ST_100BASE_X_FD = (1 << 14),
465
+ MII_REG_ST_100BASE_X_HD = (1 << 13),
466
+ MII_REG_ST_10_FD = (1 << 12),
467
+ MII_REG_ST_10_HD = (1 << 11),
468
+ MII_REG_ST_100BASE_T2_FD = (1 << 10),
469
+ MII_REG_ST_100BASE_T2_HD = (1 << 9),
470
+ MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
471
+ MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
472
+ MII_REG_ST_LINK_UP = (1 << 2),
473
+};
474
+
475
+enum {
476
+ MII_REG_LPA_10_HD = (1 << 5),
477
+ MII_REG_LPA_10_FD = (1 << 6),
478
+ MII_REG_LPA_100_HD = (1 << 7),
479
+ MII_REG_LPA_100_FD = (1 << 8),
480
+ MII_REG_LPA_PAUSE = (1 << 10),
481
+ MII_REG_LPA_ASYMPAUSE = (1 << 11),
482
+};
483
+
484
+/* MII constants */
485
+enum {
486
+ MII_PHY_ID_HIGH = 0x0044,
487
+ MII_PHY_ID_LOW = 0x1400,
488
+};
489
+
490
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
491
+ bool link_active)
492
+{
493
+ if (link_active) {
494
+ s->mii_st |= MII_REG_ST_LINK_UP;
495
+ } else {
496
+ s->mii_st &= ~MII_REG_ST_LINK_UP;
497
+ }
498
+}
499
+
500
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
501
+ bool link_active)
502
+{
503
+ s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
504
+ MII_REG_CR_FULLDUPLEX;
505
+ s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
506
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
507
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
508
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
509
+ s->mii_adv = 0;
510
+
511
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
512
+}
513
+
514
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
515
+{
516
+ uint8_t addr, reg;
517
+
518
+ addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
519
+ reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
520
+
521
+ if (addr != s->mii_phy_addr) {
522
+ return;
523
+ }
524
+
525
+ /* Read or write a PHY register? */
526
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
527
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
528
+
529
+ switch (reg) {
530
+ case MII_REG_CR:
531
+ if (s->mii_data & MII_REG_CR_RESET) {
532
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
533
+ MII_REG_ST_LINK_UP);
534
+ } else {
535
+ s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
536
+ MII_REG_CR_AUTO_NEG_RESTART);
537
+ }
538
+ break;
539
+ case MII_REG_ADV:
540
+ s->mii_adv = s->mii_data;
541
+ break;
542
+ case MII_REG_ID_HIGH:
543
+ case MII_REG_ID_LOW:
544
+ case MII_REG_LPA:
545
+ break;
546
+ default:
547
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
548
+ "unknown MII register 0x%x\n", reg);
549
+ break;
550
+ }
551
+ } else {
552
+ switch (reg) {
553
+ case MII_REG_CR:
554
+ s->mii_data = s->mii_cr;
555
+ break;
556
+ case MII_REG_ST:
557
+ s->mii_data = s->mii_st;
558
+ break;
559
+ case MII_REG_ID_HIGH:
560
+ s->mii_data = MII_PHY_ID_HIGH;
561
+ break;
562
+ case MII_REG_ID_LOW:
563
+ s->mii_data = MII_PHY_ID_LOW;
564
+ break;
565
+ case MII_REG_ADV:
566
+ s->mii_data = s->mii_adv;
567
+ break;
568
+ case MII_REG_LPA:
569
+ s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
570
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
571
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
572
+ break;
573
+ default:
574
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
575
+ "unknown MII register 0x%x\n", reg);
576
+ s->mii_data = 0;
577
+ break;
578
+ }
579
+
580
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
581
+ }
582
+}
583
+
584
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
585
+{
586
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
587
+}
588
+
589
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
590
+ size_t min_size)
591
+{
592
+ uint32_t paddr = desc->next;
593
+
594
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
595
+
596
+ if ((desc->status & DESC_STATUS_CTL) &&
597
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
598
+ return paddr;
599
+ } else {
600
+ return 0;
601
+ }
602
+}
603
+
604
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
605
+ uint32_t start_addr,
606
+ size_t min_size)
607
+{
608
+ uint32_t desc_addr = start_addr;
609
+
610
+ /* Note that the list is a cycle. Last entry points back to the head. */
611
+ while (desc_addr != 0) {
612
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
613
+
614
+ if ((desc->status & DESC_STATUS_CTL) &&
615
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
616
+ return desc_addr;
617
+ } else if (desc->next == start_addr) {
618
+ break;
619
+ } else {
620
+ desc_addr = desc->next;
621
+ }
622
+ }
623
+
624
+ return 0;
625
+}
626
+
627
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
628
+ FrameDescriptor *desc,
629
+ size_t min_size)
630
+{
631
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
632
+}
633
+
634
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
635
+ FrameDescriptor *desc,
636
+ size_t min_size)
637
+{
638
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
639
+}
640
+
641
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
642
+ uint32_t phys_addr)
643
+{
644
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
645
+}
646
+
647
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
648
+{
649
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
650
+ FrameDescriptor desc;
651
+
652
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
653
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
654
+}
655
+
656
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
657
+ const uint8_t *buf,
658
+ size_t size)
659
+{
660
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
661
+ FrameDescriptor desc;
662
+ size_t bytes_left = size;
663
+ size_t desc_bytes = 0;
664
+ size_t pad_fcs_size = 4;
665
+ size_t padding = 0;
666
+
667
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
668
+ return -1;
669
+ }
670
+
671
+ s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
672
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
673
+ if (!s->rx_desc_curr) {
674
+ s->int_sta |= INT_STA_RX_BUF_UA;
675
+ }
676
+
677
+ /* Keep filling RX descriptors until the whole frame is written */
678
+ while (s->rx_desc_curr && bytes_left > 0) {
679
+ desc.status &= ~DESC_STATUS_CTL;
680
+ desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
681
+
682
+ if (bytes_left == size) {
683
+ desc.status |= RX_DESC_STATUS_FIRST_DESC;
684
+ }
685
+
686
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
687
+ (bytes_left + pad_fcs_size)) {
688
+ desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
689
+ desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
690
+ } else {
691
+ padding = pad_fcs_size;
692
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
693
+ padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
694
+ }
695
+
696
+ desc_bytes = (bytes_left);
697
+ desc.status |= RX_DESC_STATUS_LAST_DESC;
698
+ desc.status |= (bytes_left + padding)
699
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
700
+ }
701
+
702
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
703
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
704
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
705
+ desc_bytes);
706
+
707
+ /* Check if frame needs to raise the receive interrupt */
708
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
709
+ s->int_sta |= INT_STA_RX;
710
+ }
711
+
712
+ /* Increment variables */
713
+ buf += desc_bytes;
714
+ bytes_left -= desc_bytes;
715
+
716
+ /* Move to the next descriptor */
717
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
718
+ if (!s->rx_desc_curr) {
719
+ /* Not enough buffer space available */
720
+ s->int_sta |= INT_STA_RX_BUF_UA;
721
+ s->rx_desc_curr = s->rx_desc_head;
722
+ break;
723
+ }
724
+ }
725
+
726
+ /* Report receive DMA is finished */
727
+ s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
728
+ allwinner_sun8i_emac_update_irq(s);
729
+
730
+ return size;
731
+}
732
+
733
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
734
+{
735
+ NetClientState *nc = qemu_get_queue(s->nic);
736
+ FrameDescriptor desc;
737
+ size_t bytes = 0;
738
+ size_t packet_bytes = 0;
739
+ size_t transmitted = 0;
740
+ static uint8_t packet_buf[2048];
741
+
742
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
743
+
744
+ /* Read all transmit descriptors */
745
+ while (s->tx_desc_curr != 0) {
746
+
747
+ /* Read from physical memory into packet buffer */
748
+ bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
749
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
750
+ desc.status |= TX_DESC_STATUS_LENGTH_ERR;
751
+ break;
752
+ }
753
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
754
+ packet_bytes += bytes;
755
+ desc.status &= ~DESC_STATUS_CTL;
756
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
757
+
758
+ /* After the last descriptor, send the packet */
759
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
760
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
761
+ net_checksum_calculate(packet_buf, packet_bytes);
762
+ }
763
+
764
+ qemu_send_packet(nc, packet_buf, packet_bytes);
765
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
766
+ bytes);
767
+
768
+ packet_bytes = 0;
769
+ transmitted++;
770
+ }
771
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
772
+ }
773
+
774
+ /* Raise transmit completed interrupt */
775
+ if (transmitted > 0) {
776
+ s->int_sta |= INT_STA_TX;
777
+ s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
778
+ allwinner_sun8i_emac_update_irq(s);
779
+ }
780
+}
781
+
782
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
783
+{
784
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
785
+ NetClientState *nc = qemu_get_queue(s->nic);
786
+
787
+ trace_allwinner_sun8i_emac_reset();
788
+
789
+ s->mii_cmd = 0;
790
+ s->mii_data = 0;
791
+ s->basic_ctl0 = 0;
792
+ s->basic_ctl1 = REG_BASIC_CTL_1_RST;
793
+ s->int_en = 0;
794
+ s->int_sta = 0;
795
+ s->frm_flt = 0;
796
+ s->rx_ctl0 = 0;
797
+ s->rx_ctl1 = RX_CTL1_RX_MD;
798
+ s->rx_desc_head = 0;
799
+ s->rx_desc_curr = 0;
800
+ s->tx_ctl0 = 0;
801
+ s->tx_ctl1 = 0;
802
+ s->tx_desc_head = 0;
803
+ s->tx_desc_curr = 0;
804
+ s->tx_flowctl = 0;
805
+
806
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
807
+}
808
+
809
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
810
+ unsigned size)
811
+{
812
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
813
+ uint64_t value = 0;
814
+ FrameDescriptor desc;
815
+
816
+ switch (offset) {
817
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
818
+ value = s->basic_ctl0;
819
+ break;
820
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
821
+ value = s->basic_ctl1;
822
+ break;
823
+ case REG_INT_STA: /* Interrupt Status */
824
+ value = s->int_sta;
825
+ break;
826
+ case REG_INT_EN: /* Interupt Enable */
827
+ value = s->int_en;
828
+ break;
829
+ case REG_TX_CTL_0: /* Transmit Control 0 */
830
+ value = s->tx_ctl0;
831
+ break;
832
+ case REG_TX_CTL_1: /* Transmit Control 1 */
833
+ value = s->tx_ctl1;
834
+ break;
835
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
836
+ value = s->tx_flowctl;
837
+ break;
838
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
839
+ value = s->tx_desc_head;
840
+ break;
841
+ case REG_RX_CTL_0: /* Receive Control 0 */
842
+ value = s->rx_ctl0;
843
+ break;
844
+ case REG_RX_CTL_1: /* Receive Control 1 */
845
+ value = s->rx_ctl1;
846
+ break;
847
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
848
+ value = s->rx_desc_head;
849
+ break;
850
+ case REG_FRM_FLT: /* Receive Frame Filter */
851
+ value = s->frm_flt;
852
+ break;
853
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
854
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
855
+ break;
856
+ case REG_MII_CMD: /* Management Interface Command */
857
+ value = s->mii_cmd;
858
+ break;
859
+ case REG_MII_DATA: /* Management Interface Data */
860
+ value = s->mii_data;
861
+ break;
862
+ case REG_ADDR_HIGH: /* MAC Address High */
863
+ value = *(((uint32_t *) (s->conf.macaddr.a)) + 1);
864
+ break;
865
+ case REG_ADDR_LOW: /* MAC Address Low */
866
+ value = *(uint32_t *) (s->conf.macaddr.a);
867
+ break;
868
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
869
+ break;
870
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
871
+ value = s->tx_desc_curr;
872
+ break;
873
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
874
+ if (s->tx_desc_curr != 0) {
875
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
876
+ value = desc.addr;
877
+ } else {
878
+ value = 0;
879
+ }
880
+ break;
881
+ case REG_RX_DMA_STA: /* Receive DMA Status */
882
+ break;
883
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
884
+ value = s->rx_desc_curr;
885
+ break;
886
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
887
+ if (s->rx_desc_curr != 0) {
888
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
889
+ value = desc.addr;
890
+ } else {
891
+ value = 0;
892
+ }
893
+ break;
894
+ case REG_RGMII_STA: /* RGMII Status */
895
+ break;
896
+ default:
897
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
898
+ "EMAC register 0x" TARGET_FMT_plx "\n",
899
+ offset);
900
+ }
901
+
902
+ trace_allwinner_sun8i_emac_read(offset, value);
903
+ return value;
904
+}
905
+
906
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
907
+ uint64_t value, unsigned size)
908
+{
909
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
910
+ NetClientState *nc = qemu_get_queue(s->nic);
911
+
912
+ trace_allwinner_sun8i_emac_write(offset, value);
913
+
914
+ switch (offset) {
915
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
916
+ s->basic_ctl0 = value;
917
+ break;
918
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
919
+ if (value & BASIC_CTL1_SOFTRST) {
920
+ allwinner_sun8i_emac_reset(DEVICE(s));
921
+ value &= ~BASIC_CTL1_SOFTRST;
922
+ }
923
+ s->basic_ctl1 = value;
924
+ if (allwinner_sun8i_emac_can_receive(nc)) {
925
+ qemu_flush_queued_packets(nc);
926
+ }
927
+ break;
928
+ case REG_INT_STA: /* Interrupt Status */
929
+ s->int_sta &= ~value;
930
+ allwinner_sun8i_emac_update_irq(s);
931
+ break;
932
+ case REG_INT_EN: /* Interrupt Enable */
933
+ s->int_en = value;
934
+ allwinner_sun8i_emac_update_irq(s);
935
+ break;
936
+ case REG_TX_CTL_0: /* Transmit Control 0 */
937
+ s->tx_ctl0 = value;
938
+ break;
939
+ case REG_TX_CTL_1: /* Transmit Control 1 */
940
+ s->tx_ctl1 = value;
941
+ if (value & TX_CTL1_TX_DMA_EN) {
942
+ allwinner_sun8i_emac_transmit(s);
943
+ }
944
+ break;
945
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
946
+ s->tx_flowctl = value;
947
+ break;
948
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
949
+ s->tx_desc_head = value;
950
+ s->tx_desc_curr = value;
951
+ break;
952
+ case REG_RX_CTL_0: /* Receive Control 0 */
953
+ s->rx_ctl0 = value;
954
+ break;
955
+ case REG_RX_CTL_1: /* Receive Control 1 */
956
+ s->rx_ctl1 = value | RX_CTL1_RX_MD;
957
+ if ((value & RX_CTL1_RX_DMA_EN) &&
958
+ allwinner_sun8i_emac_can_receive(nc)) {
959
+ qemu_flush_queued_packets(nc);
960
+ }
961
+ break;
962
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
963
+ s->rx_desc_head = value;
964
+ s->rx_desc_curr = value;
965
+ break;
966
+ case REG_FRM_FLT: /* Receive Frame Filter */
967
+ s->frm_flt = value;
968
+ break;
969
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
970
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
971
+ break;
972
+ case REG_MII_CMD: /* Management Interface Command */
973
+ s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
974
+ allwinner_sun8i_emac_mii_cmd(s);
975
+ break;
976
+ case REG_MII_DATA: /* Management Interface Data */
977
+ s->mii_data = value;
978
+ break;
979
+ case REG_ADDR_HIGH: /* MAC Address High */
980
+ s->conf.macaddr.a[4] = (value & 0xff);
981
+ s->conf.macaddr.a[5] = (value & 0xff00) >> 8;
982
+ break;
983
+ case REG_ADDR_LOW: /* MAC Address Low */
984
+ s->conf.macaddr.a[0] = (value & 0xff);
985
+ s->conf.macaddr.a[1] = (value & 0xff00) >> 8;
986
+ s->conf.macaddr.a[2] = (value & 0xff0000) >> 16;
987
+ s->conf.macaddr.a[3] = (value & 0xff000000) >> 24;
988
+ break;
989
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
990
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
991
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
992
+ case REG_RX_DMA_STA: /* Receive DMA Status */
993
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
994
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
995
+ case REG_RGMII_STA: /* RGMII Status */
996
+ break;
997
+ default:
998
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
999
+ "EMAC register 0x" TARGET_FMT_plx "\n",
1000
+ offset);
1001
+ }
1002
+}
1003
+
1004
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
1005
+{
1006
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
1007
+
1008
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
1009
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
1010
+}
1011
+
1012
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
1013
+ .read = allwinner_sun8i_emac_read,
1014
+ .write = allwinner_sun8i_emac_write,
1015
+ .endianness = DEVICE_NATIVE_ENDIAN,
1016
+ .valid = {
1017
+ .min_access_size = 4,
1018
+ .max_access_size = 4,
1019
+ },
1020
+ .impl.min_access_size = 4,
1021
+};
1022
+
1023
+static NetClientInfo net_allwinner_sun8i_emac_info = {
1024
+ .type = NET_CLIENT_DRIVER_NIC,
1025
+ .size = sizeof(NICState),
1026
+ .can_receive = allwinner_sun8i_emac_can_receive,
1027
+ .receive = allwinner_sun8i_emac_receive,
1028
+ .link_status_changed = allwinner_sun8i_emac_set_link,
1029
+};
1030
+
1031
+static void allwinner_sun8i_emac_init(Object *obj)
1032
+{
1033
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1034
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
1035
+
1036
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
1037
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
1038
+ sysbus_init_mmio(sbd, &s->iomem);
1039
+ sysbus_init_irq(sbd, &s->irq);
1040
+}
1041
+
1042
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
1043
+{
1044
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
1045
+
1046
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
1047
+ s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
1048
+ object_get_typename(OBJECT(dev)), dev->id, s);
1049
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1050
+}
1051
+
1052
+static Property allwinner_sun8i_emac_properties[] = {
1053
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
1054
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
1055
+ DEFINE_PROP_END_OF_LIST(),
1056
+};
1057
+
1058
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
1059
+{
1060
+ AwSun8iEmacState *s = opaque;
1061
+
1062
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
1063
+
1064
+ return 0;
1065
+}
1066
+
1067
+static const VMStateDescription vmstate_aw_emac = {
1068
+ .name = "allwinner-sun8i-emac",
1069
+ .version_id = 1,
1070
+ .minimum_version_id = 1,
1071
+ .post_load = allwinner_sun8i_emac_post_load,
1072
+ .fields = (VMStateField[]) {
1073
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
1074
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
1075
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
1076
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
1077
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
1078
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
1079
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
1080
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
1081
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
1082
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
1083
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
1084
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
1085
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
1086
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
1087
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
1088
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
1089
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
1090
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
1091
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
1092
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
1093
+ VMSTATE_END_OF_LIST()
1094
+ }
1095
+};
1096
+
1097
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
1098
+{
1099
+ DeviceClass *dc = DEVICE_CLASS(klass);
1100
+
1101
+ dc->realize = allwinner_sun8i_emac_realize;
1102
+ dc->reset = allwinner_sun8i_emac_reset;
1103
+ dc->vmsd = &vmstate_aw_emac;
1104
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
1105
+}
1106
+
1107
+static const TypeInfo allwinner_sun8i_emac_info = {
1108
+ .name = TYPE_AW_SUN8I_EMAC,
1109
+ .parent = TYPE_SYS_BUS_DEVICE,
1110
+ .instance_size = sizeof(AwSun8iEmacState),
1111
+ .instance_init = allwinner_sun8i_emac_init,
1112
+ .class_init = allwinner_sun8i_emac_class_init,
1113
+};
1114
+
1115
+static void allwinner_sun8i_emac_register_types(void)
1116
+{
1117
+ type_register_static(&allwinner_sun8i_emac_info);
1118
+}
1119
+
1120
+type_init(allwinner_sun8i_emac_register_types)
1121
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1122
index XXXXXXX..XXXXXXX 100644
1123
--- a/hw/arm/Kconfig
1124
+++ b/hw/arm/Kconfig
1125
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
1126
config ALLWINNER_H3
1127
bool
1128
select ALLWINNER_A10_PIT
1129
+ select ALLWINNER_SUN8I_EMAC
1130
select SERIAL
1131
select ARM_TIMER
1132
select ARM_GIC
1133
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/hw/net/Kconfig
1136
+++ b/hw/net/Kconfig
1137
@@ -XXX,XX +XXX,XX @@ config MIPSNET
1138
config ALLWINNER_EMAC
1139
bool
1140
1141
+config ALLWINNER_SUN8I_EMAC
1142
+ bool
1143
+
1144
config IMX_FEC
1145
bool
1146
1147
diff --git a/hw/net/trace-events b/hw/net/trace-events
1148
index XXXXXXX..XXXXXXX 100644
1149
--- a/hw/net/trace-events
1150
+++ b/hw/net/trace-events
1151
@@ -XXX,XX +XXX,XX @@
1152
# See docs/devel/tracing.txt for syntax documentation.
1153
1154
+# allwinner-sun8i-emac.c
1155
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
1156
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
1157
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1158
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1159
+allwinner_sun8i_emac_reset(void) "HW reset"
1160
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
1161
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
1162
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
1163
+
1164
# etraxfs_eth.c
1165
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
1166
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
1167
--
42
--
1168
2.20.1
43
2.20.1
1169
44
1170
45
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We plan to introduce yet another value for the gic version (nosel).
3
For BTI, we need to know if the executable is static or dynamic,
4
As we already use exotic values such as 0 and -1, let's introduce
4
which means looking for PT_INTERP earlier.
5
a dedicated enum type and let vms->gic_version take this
6
type.
7
5
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201016184207.786698-8-richard.henderson@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Message-id: 20200311131618.7187-3-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
include/hw/arm/virt.h | 11 +++++++++--
11
linux-user/elfload.c | 60 +++++++++++++++++++++++---------------------
16
hw/arm/virt.c | 30 +++++++++++++++---------------
12
1 file changed, 31 insertions(+), 29 deletions(-)
17
2 files changed, 24 insertions(+), 17 deletions(-)
18
13
19
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
14
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/virt.h
16
--- a/linux-user/elfload.c
22
+++ b/include/hw/arm/virt.h
17
+++ b/linux-user/elfload.c
23
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
18
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
24
VIRT_IOMMU_VIRTIO,
19
25
} VirtIOMMUType;
20
mmap_lock();
26
21
27
+typedef enum VirtGICType {
22
- /* Find the maximum size of the image and allocate an appropriate
28
+ VIRT_GIC_VERSION_MAX,
23
- amount of memory to handle that. */
29
+ VIRT_GIC_VERSION_HOST,
24
+ /*
30
+ VIRT_GIC_VERSION_2,
25
+ * Find the maximum size of the image and allocate an appropriate
31
+ VIRT_GIC_VERSION_3,
26
+ * amount of memory to handle that. Locate the interpreter, if any.
32
+} VirtGICType;
27
+ */
28
loaddr = -1, hiaddr = 0;
29
info->alignment = 0;
30
for (i = 0; i < ehdr->e_phnum; ++i) {
31
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
32
}
33
++info->nsegs;
34
info->alignment |= eppnt->p_align;
35
+ } else if (eppnt->p_type == PT_INTERP && pinterp_name) {
36
+ g_autofree char *interp_name = NULL;
33
+
37
+
34
typedef struct MemMapEntry {
38
+ if (*pinterp_name) {
35
hwaddr base;
39
+ errmsg = "Multiple PT_INTERP entries";
36
hwaddr size;
40
+ goto exit_errmsg;
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
41
+ }
38
bool highmem_ecam;
42
+ interp_name = g_malloc(eppnt->p_filesz);
39
bool its;
43
+ if (!interp_name) {
40
bool virt;
44
+ goto exit_perror;
41
- int32_t gic_version;
45
+ }
42
+ VirtGICType gic_version;
46
+
43
VirtIOMMUType iommu;
47
+ if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
44
uint16_t virtio_iommu_bdf;
48
+ memcpy(interp_name, bprm_buf + eppnt->p_offset,
45
struct arm_boot_info bootinfo;
49
+ eppnt->p_filesz);
46
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
50
+ } else {
47
uint32_t redist0_capacity =
51
+ retval = pread(image_fd, interp_name, eppnt->p_filesz,
48
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
52
+ eppnt->p_offset);
49
53
+ if (retval != eppnt->p_filesz) {
50
- assert(vms->gic_version == 3);
54
+ goto exit_perror;
51
+ assert(vms->gic_version == VIRT_GIC_VERSION_3);
55
+ }
52
56
+ }
53
return vms->smp_cpus > redist0_capacity ? 2 : 1;
57
+ if (interp_name[eppnt->p_filesz - 1] != 0) {
54
}
58
+ errmsg = "Invalid PT_INTERP entry";
55
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
59
+ goto exit_errmsg;
56
index XXXXXXX..XXXXXXX 100644
60
+ }
57
--- a/hw/arm/virt.c
61
+ *pinterp_name = g_steal_pointer(&interp_name);
58
+++ b/hw/arm/virt.c
59
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
60
irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
61
}
62
63
- if (vms->gic_version == 2) {
64
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
65
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
66
GIC_FDT_IRQ_PPI_CPU_WIDTH,
67
(1 << vms->smp_cpus) - 1);
68
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
70
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
71
qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
72
- if (vms->gic_version == 3) {
73
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
74
int nb_redist_regions = virt_gicv3_redist_region_count(vms);
75
76
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
77
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
78
}
62
}
79
}
63
}
80
64
81
- if (vms->gic_version == 2) {
65
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
82
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
66
if (vaddr_em > info->brk) {
83
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
67
info->brk = vaddr_em;
84
GIC_FDT_IRQ_PPI_CPU_WIDTH,
85
(1 << vms->smp_cpus) - 1);
86
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
87
* purposes are to make TCG consistent (with 64-bit KVM hosts)
88
* and to improve SGI efficiency.
89
*/
90
- if (vms->gic_version == 3) {
91
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
92
clustersz = GICV3_TARGETLIST_BITS;
93
} else {
94
clustersz = GIC_TARGETLIST_BITS;
95
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
96
/* We can probe only here because during property set
97
* KVM is not available yet
98
*/
99
- if (vms->gic_version <= 0) {
100
- /* "host" or "max" */
101
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
102
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
103
if (!kvm_enabled()) {
104
- if (vms->gic_version == 0) {
105
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
106
error_report("gic-version=host requires KVM");
107
exit(1);
108
} else {
109
/* "max": currently means 3 for TCG */
110
- vms->gic_version = 3;
111
+ vms->gic_version = VIRT_GIC_VERSION_3;
112
}
68
}
113
} else {
69
- } else if (eppnt->p_type == PT_INTERP && pinterp_name) {
114
vms->gic_version = kvm_arm_vgic_probe();
70
- g_autofree char *interp_name = NULL;
115
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
71
-
116
/* The maximum number of CPUs depends on the GIC version, or on how
72
- if (*pinterp_name) {
117
* many redistributors we can fit into the memory map.
73
- errmsg = "Multiple PT_INTERP entries";
118
*/
74
- goto exit_errmsg;
119
- if (vms->gic_version == 3) {
75
- }
120
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
76
- interp_name = g_malloc(eppnt->p_filesz);
121
virt_max_cpus =
77
- if (!interp_name) {
122
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
78
- goto exit_perror;
123
virt_max_cpus +=
79
- }
124
@@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp)
80
-
125
static char *virt_get_gic_version(Object *obj, Error **errp)
81
- if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
126
{
82
- memcpy(interp_name, bprm_buf + eppnt->p_offset,
127
VirtMachineState *vms = VIRT_MACHINE(obj);
83
- eppnt->p_filesz);
128
- const char *val = vms->gic_version == 3 ? "3" : "2";
84
- } else {
129
+ const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
85
- retval = pread(image_fd, interp_name, eppnt->p_filesz,
130
86
- eppnt->p_offset);
131
return g_strdup(val);
87
- if (retval != eppnt->p_filesz) {
132
}
88
- goto exit_perror;
133
@@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
89
- }
134
VirtMachineState *vms = VIRT_MACHINE(obj);
90
- }
135
91
- if (interp_name[eppnt->p_filesz - 1] != 0) {
136
if (!strcmp(value, "3")) {
92
- errmsg = "Invalid PT_INTERP entry";
137
- vms->gic_version = 3;
93
- goto exit_errmsg;
138
+ vms->gic_version = VIRT_GIC_VERSION_3;
94
- }
139
} else if (!strcmp(value, "2")) {
95
- *pinterp_name = g_steal_pointer(&interp_name);
140
- vms->gic_version = 2;
96
#ifdef TARGET_MIPS
141
+ vms->gic_version = VIRT_GIC_VERSION_2;
97
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
142
} else if (!strcmp(value, "host")) {
98
Mips_elf_abiflags_v0 abiflags;
143
- vms->gic_version = 0; /* Will probe later */
144
+ vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
145
} else if (!strcmp(value, "max")) {
146
- vms->gic_version = -1; /* Will probe later */
147
+ vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
148
} else {
149
error_setg(errp, "Invalid gic-version value");
150
error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
151
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
152
"physical address space above 32 bits",
153
NULL);
154
/* Default GIC type is v2 */
155
- vms->gic_version = 2;
156
+ vms->gic_version = VIRT_GIC_VERSION_2;
157
object_property_add_str(obj, "gic-version", virt_get_gic_version,
158
virt_set_gic_version, NULL);
159
object_property_set_description(obj, "gic-version",
160
--
99
--
161
2.20.1
100
2.20.1
162
101
163
102
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Restructure the finalize_gic_version with switch cases and
3
This is a bit clearer than open-coding some of this
4
clearly separate the following cases:
4
with a bare c string.
5
5
6
- KVM mode / in-kernel irqchip
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
- KVM mode / userspace irqchip
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
- TCG mode
8
Message-id: 20201016184207.786698-9-richard.henderson@linaro.org
9
10
In KVM mode / in-kernel irqchip , we explictly check whether
11
the chosen version is supported by the host. If the end-user
12
explicitly sets v2/v3 and this is not supported by the host,
13
then the user gets an explicit error message. Note that for
14
old kernels where the CREATE_DEVICE ioctl doesn't exist then
15
we will now fail if the user specifically asked for gicv2,
16
where previously we (probably) would have succeeded.
17
18
In KVM mode / userspace irqchip we immediatly output an error
19
in case the end-user explicitly selected v3. Also we warn the
20
end-user about the unexpected usage of gic-version=host in
21
that case as only userspace GICv2 is supported.
22
23
Signed-off-by: Eric Auger <eric.auger@redhat.com>
24
Reviewed-by: Andrew Jones <drjones@redhat.com>
25
Message-id: 20200311131618.7187-6-eric.auger@redhat.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
10
---
28
hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------
11
linux-user/elfload.c | 37 ++++++++++++++++++++-----------------
29
1 file changed, 67 insertions(+), 21 deletions(-)
12
1 file changed, 20 insertions(+), 17 deletions(-)
30
13
31
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
32
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/virt.c
16
--- a/linux-user/elfload.c
34
+++ b/hw/arm/virt.c
17
+++ b/linux-user/elfload.c
35
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
18
@@ -XXX,XX +XXX,XX @@
36
*/
19
#include "qemu/guest-random.h"
37
static void finalize_gic_version(VirtMachineState *vms)
20
#include "qemu/units.h"
38
{
21
#include "qemu/selfmap.h"
39
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
22
+#include "qapi/error.h"
40
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
23
41
- if (!kvm_enabled()) {
24
#ifdef _ARCH_PPC64
42
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
25
#undef ARCH_DLINFO
43
- error_report("gic-version=host requires KVM");
26
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
44
- exit(1);
27
struct elf_phdr *phdr;
45
- } else {
28
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
46
- /* "max": currently means 3 for TCG */
29
int i, retval;
47
- vms->gic_version = VIRT_GIC_VERSION_3;
30
- const char *errmsg;
31
+ Error *err = NULL;
32
33
/* First of all, some simple consistency checks */
34
- errmsg = "Invalid ELF image for this architecture";
35
if (!elf_check_ident(ehdr)) {
36
+ error_setg(&err, "Invalid ELF image for this architecture");
37
goto exit_errmsg;
38
}
39
bswap_ehdr(ehdr);
40
if (!elf_check_ehdr(ehdr)) {
41
+ error_setg(&err, "Invalid ELF image for this architecture");
42
goto exit_errmsg;
43
}
44
45
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
46
g_autofree char *interp_name = NULL;
47
48
if (*pinterp_name) {
49
- errmsg = "Multiple PT_INTERP entries";
50
+ error_setg(&err, "Multiple PT_INTERP entries");
51
goto exit_errmsg;
52
}
53
+
54
interp_name = g_malloc(eppnt->p_filesz);
55
- if (!interp_name) {
56
- goto exit_perror;
48
- }
57
- }
49
- } else {
58
50
- int probe_bitmap = kvm_arm_vgic_probe();
59
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
51
+ if (kvm_enabled()) {
60
memcpy(interp_name, bprm_buf + eppnt->p_offset,
52
+ int probe_bitmap;
61
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
53
62
retval = pread(image_fd, interp_name, eppnt->p_filesz,
54
- if (!probe_bitmap) {
63
eppnt->p_offset);
55
+ if (!kvm_irqchip_in_kernel()) {
64
if (retval != eppnt->p_filesz) {
56
+ switch (vms->gic_version) {
65
- goto exit_perror;
57
+ case VIRT_GIC_VERSION_HOST:
66
+ goto exit_read;
58
+ warn_report(
67
}
59
+ "gic-version=host not relevant with kernel-irqchip=off "
60
+ "as only userspace GICv2 is supported. Using v2 ...");
61
+ return;
62
+ case VIRT_GIC_VERSION_MAX:
63
+ case VIRT_GIC_VERSION_NOSEL:
64
+ vms->gic_version = VIRT_GIC_VERSION_2;
65
+ return;
66
+ case VIRT_GIC_VERSION_2:
67
+ return;
68
+ case VIRT_GIC_VERSION_3:
69
error_report(
70
- "Unable to determine GIC version supported by host");
71
+ "gic-version=3 is not supported with kernel-irqchip=off");
72
exit(1);
73
- } else {
74
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
75
- vms->gic_version = VIRT_GIC_VERSION_3;
76
- } else {
77
- vms->gic_version = VIRT_GIC_VERSION_2;
78
- }
79
}
68
}
80
}
69
if (interp_name[eppnt->p_filesz - 1] != 0) {
81
- } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
70
- errmsg = "Invalid PT_INTERP entry";
82
+
71
+ error_setg(&err, "Invalid PT_INTERP entry");
83
+ probe_bitmap = kvm_arm_vgic_probe();
72
goto exit_errmsg;
84
+ if (!probe_bitmap) {
73
}
85
+ error_report("Unable to determine GIC version supported by host");
74
*pinterp_name = g_steal_pointer(&interp_name);
86
+ exit(1);
75
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
87
+ }
76
(ehdr->e_type == ET_EXEC ? MAP_FIXED : 0),
88
+
77
-1, 0);
89
+ switch (vms->gic_version) {
78
if (load_addr == -1) {
90
+ case VIRT_GIC_VERSION_HOST:
79
- goto exit_perror;
91
+ case VIRT_GIC_VERSION_MAX:
80
+ goto exit_mmap;
92
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
93
+ vms->gic_version = VIRT_GIC_VERSION_3;
94
+ } else {
95
+ vms->gic_version = VIRT_GIC_VERSION_2;
96
+ }
97
+ return;
98
+ case VIRT_GIC_VERSION_NOSEL:
99
+ vms->gic_version = VIRT_GIC_VERSION_2;
100
+ break;
101
+ case VIRT_GIC_VERSION_2:
102
+ case VIRT_GIC_VERSION_3:
103
+ break;
104
+ }
105
+
106
+ /* Check chosen version is effectively supported by the host */
107
+ if (vms->gic_version == VIRT_GIC_VERSION_2 &&
108
+ !(probe_bitmap & KVM_ARM_VGIC_V2)) {
109
+ error_report("host does not support in-kernel GICv2 emulation");
110
+ exit(1);
111
+ } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
112
+ !(probe_bitmap & KVM_ARM_VGIC_V3)) {
113
+ error_report("host does not support in-kernel GICv3 emulation");
114
+ exit(1);
115
+ }
116
+ return;
117
+ }
118
+
119
+ /* TCG mode */
120
+ switch (vms->gic_version) {
121
+ case VIRT_GIC_VERSION_NOSEL:
122
vms->gic_version = VIRT_GIC_VERSION_2;
123
+ break;
124
+ case VIRT_GIC_VERSION_MAX:
125
+ vms->gic_version = VIRT_GIC_VERSION_3;
126
+ break;
127
+ case VIRT_GIC_VERSION_HOST:
128
+ error_report("gic-version=host requires KVM");
129
+ exit(1);
130
+ case VIRT_GIC_VERSION_2:
131
+ case VIRT_GIC_VERSION_3:
132
+ break;
133
}
81
}
82
load_bias = load_addr - loaddr;
83
84
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
85
image_fd, eppnt->p_offset - vaddr_po);
86
87
if (error == -1) {
88
- goto exit_perror;
89
+ goto exit_mmap;
90
}
91
}
92
93
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
94
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
95
Mips_elf_abiflags_v0 abiflags;
96
if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) {
97
- errmsg = "Invalid PT_MIPS_ABIFLAGS entry";
98
+ error_setg(&err, "Invalid PT_MIPS_ABIFLAGS entry");
99
goto exit_errmsg;
100
}
101
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
102
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
103
retval = pread(image_fd, &abiflags, sizeof(Mips_elf_abiflags_v0),
104
eppnt->p_offset);
105
if (retval != sizeof(Mips_elf_abiflags_v0)) {
106
- goto exit_perror;
107
+ goto exit_read;
108
}
109
}
110
bswap_mips_abiflags(&abiflags);
111
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
112
113
exit_read:
114
if (retval >= 0) {
115
- errmsg = "Incomplete read of file header";
116
- goto exit_errmsg;
117
+ error_setg(&err, "Incomplete read of file header");
118
+ } else {
119
+ error_setg_errno(&err, errno, "Error reading file header");
120
}
121
- exit_perror:
122
- errmsg = strerror(errno);
123
+ goto exit_errmsg;
124
+ exit_mmap:
125
+ error_setg_errno(&err, errno, "Error mapping file");
126
+ goto exit_errmsg;
127
exit_errmsg:
128
- fprintf(stderr, "%s: %s\n", image_name, errmsg);
129
+ error_reportf_err(err, "%s: ", image_name);
130
exit(-1);
134
}
131
}
135
132
136
--
133
--
137
2.20.1
134
2.20.1
138
135
139
136
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
3
This is slightly clearer than just using strerror, though
4
provided on the command line to available eSDHC controllers.
4
the different forms produced by error_setg_file_open and
5
error_setg_errno isn't entirely convenient.
5
6
6
This patch enables booting the imx25-pdk emulation from SD card.
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20201016184207.786698-10-richard.henderson@linaro.org
9
Message-id: 20200310215146.19688-2-linux@roeck-us.net
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: made commit subject consistent with other patch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
include/hw/arm/fsl-imx25.h | 9 +++++++++
12
linux-user/elfload.c | 15 ++++++++-------
15
hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++
13
1 file changed, 8 insertions(+), 7 deletions(-)
16
hw/arm/imx25_pdk.c | 16 ++++++++++++++++
17
3 files changed, 57 insertions(+)
18
14
19
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
15
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/fsl-imx25.h
17
--- a/linux-user/elfload.c
22
+++ b/include/hw/arm/fsl-imx25.h
18
+++ b/linux-user/elfload.c
23
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void load_elf_interp(const char *filename, struct image_info *info,
24
#include "hw/misc/imx_rngc.h"
20
char bprm_buf[BPRM_BUF_SIZE])
25
#include "hw/i2c/imx_i2c.h"
26
#include "hw/gpio/imx_gpio.h"
27
+#include "hw/sd/sdhci.h"
28
#include "exec/memory.h"
29
#include "target/arm/cpu.h"
30
31
@@ -XXX,XX +XXX,XX @@
32
#define FSL_IMX25_NUM_EPITS 2
33
#define FSL_IMX25_NUM_I2CS 3
34
#define FSL_IMX25_NUM_GPIOS 4
35
+#define FSL_IMX25_NUM_ESDHCS 2
36
37
typedef struct FslIMX25State {
38
/*< private >*/
39
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
40
IMXRNGCState rngc;
41
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
42
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
43
+ SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
44
MemoryRegion rom[2];
45
MemoryRegion iram;
46
MemoryRegion iram_alias;
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
#define FSL_IMX25_GPIO3_SIZE 0x4000
49
#define FSL_IMX25_RNGC_ADDR 0x53FB0000
50
#define FSL_IMX25_RNGC_SIZE 0x4000
51
+#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
52
+#define FSL_IMX25_ESDHC1_SIZE 0x4000
53
+#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
54
+#define FSL_IMX25_ESDHC2_SIZE 0x4000
55
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
56
#define FSL_IMX25_GPIO1_SIZE 0x4000
57
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
58
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
59
#define FSL_IMX25_GPIO2_IRQ 51
60
#define FSL_IMX25_GPIO3_IRQ 16
61
#define FSL_IMX25_GPIO4_IRQ 23
62
+#define FSL_IMX25_ESDHC1_IRQ 9
63
+#define FSL_IMX25_ESDHC2_IRQ 8
64
65
#endif /* FSL_IMX25_H */
66
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/fsl-imx25.c
69
+++ b/hw/arm/fsl-imx25.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "hw/qdev-properties.h"
72
#include "chardev/char.h"
73
74
+#define IMX25_ESDHC_CAPABILITIES 0x07e20000
75
+
76
static void fsl_imx25_init(Object *obj)
77
{
21
{
78
FslIMX25State *s = FSL_IMX25(obj);
22
int fd, retval;
79
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
23
+ Error *err = NULL;
80
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
24
81
TYPE_IMX_GPIO);
25
fd = open(path(filename), O_RDONLY);
26
if (fd < 0) {
27
- goto exit_perror;
28
+ error_setg_file_open(&err, errno, filename);
29
+ error_report_err(err);
30
+ exit(-1);
31
}
32
33
retval = read(fd, bprm_buf, BPRM_BUF_SIZE);
34
if (retval < 0) {
35
- goto exit_perror;
36
+ error_setg_errno(&err, errno, "Error reading file header");
37
+ error_reportf_err(err, "%s: ", filename);
38
+ exit(-1);
82
}
39
}
83
+
40
+
84
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
41
if (retval < BPRM_BUF_SIZE) {
85
+ sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
42
memset(bprm_buf + retval, 0, BPRM_BUF_SIZE - retval);
86
+ TYPE_IMX_USDHC);
43
}
87
+ }
44
45
load_elf_image(filename, fd, info, NULL, bprm_buf);
46
- return;
47
-
48
- exit_perror:
49
- fprintf(stderr, "%s: %s\n", filename, strerror(errno));
50
- exit(-1);
88
}
51
}
89
52
90
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
53
static int symfind(const void *s0, const void *s1)
91
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
92
gpio_table[i].irq));
93
}
94
95
+ /* Initialize all SDHC */
96
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
97
+ static const struct {
98
+ hwaddr addr;
99
+ unsigned int irq;
100
+ } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
101
+ { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
102
+ { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
103
+ };
104
+
105
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
106
+ &err);
107
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
108
+ "capareg", &err);
109
+ object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
110
+ if (err) {
111
+ error_propagate(errp, err);
112
+ return;
113
+ }
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->avic),
117
+ esdhc_table[i].irq));
118
+ }
119
+
120
/* initialize 2 x 16 KB ROM */
121
memory_region_init_rom(&s->rom[0], NULL,
122
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
123
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/imx25_pdk.c
126
+++ b/hw/arm/imx25_pdk.c
127
@@ -XXX,XX +XXX,XX @@
128
#include "qemu/osdep.h"
129
#include "qapi/error.h"
130
#include "cpu.h"
131
+#include "hw/qdev-properties.h"
132
#include "hw/arm/fsl-imx25.h"
133
#include "hw/boards.h"
134
#include "qemu/error-report.h"
135
@@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine)
136
imx25_pdk_binfo.board_id = 1771,
137
imx25_pdk_binfo.nb_cpus = 1;
138
139
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
140
+ BusState *bus;
141
+ DeviceState *carddev;
142
+ DriveInfo *di;
143
+ BlockBackend *blk;
144
+
145
+ di = drive_get_next(IF_SD);
146
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
147
+ bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
148
+ carddev = qdev_create(bus, TYPE_SD_CARD);
149
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
150
+ object_property_set_bool(OBJECT(carddev), true,
151
+ "realized", &error_fatal);
152
+ }
153
+
154
/*
155
* We test explicitly for qtest here as it is not done (yet?) in
156
* arm_load_kernel(). Without this the "make check" command would
157
--
54
--
158
2.20.1
55
2.20.1
159
56
160
57
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
3
This is generic support, with the code disabled for all targets.
4
processor cores. Features and specifications include DDR2/DDR3 memory,
4
5
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
various I/O modules. This commit adds support for the Allwinner H3
6
Message-id: 20201016184207.786698-11-richard.henderson@linaro.org
7
System on Chip.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
9
---
16
hw/arm/Makefile.objs | 1 +
10
linux-user/qemu.h | 4 ++
17
include/hw/arm/allwinner-h3.h | 106 +++++++++++
11
linux-user/elfload.c | 157 +++++++++++++++++++++++++++++++++++++++++++
18
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
12
2 files changed, 161 insertions(+)
19
MAINTAINERS | 7 +
13
20
default-configs/arm-softmmu.mak | 1 +
14
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
21
hw/arm/Kconfig | 8 +
22
6 files changed, 450 insertions(+)
23
create mode 100644 include/hw/arm/allwinner-h3.h
24
create mode 100644 hw/arm/allwinner-h3.c
25
26
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
27
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/Makefile.objs
16
--- a/linux-user/qemu.h
29
+++ b/hw/arm/Makefile.objs
17
+++ b/linux-user/qemu.h
30
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
18
@@ -XXX,XX +XXX,XX @@ struct image_info {
31
obj-$(CONFIG_OMAP) += omap1.o omap2.o
19
abi_ulong interpreter_loadmap_addr;
32
obj-$(CONFIG_STRONGARM) += strongarm.o
20
abi_ulong interpreter_pt_dynamic_addr;
33
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
21
struct image_info *other_info;
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
22
+
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
23
+ /* For target-specific processing of NT_GNU_PROPERTY_TYPE_0. */
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
24
+ uint32_t note_flags;
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
25
+
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
26
#ifdef TARGET_MIPS
39
new file mode 100644
27
int fp_abi;
40
index XXXXXXX..XXXXXXX
28
int interp_fp_abi;
41
--- /dev/null
29
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
42
+++ b/include/hw/arm/allwinner-h3.h
30
index XXXXXXX..XXXXXXX 100644
43
@@ -XXX,XX +XXX,XX @@
31
--- a/linux-user/elfload.c
32
+++ b/linux-user/elfload.c
33
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
34
35
#include "elf.h"
36
37
+static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
38
+ const uint32_t *data,
39
+ struct image_info *info,
40
+ Error **errp)
41
+{
42
+ g_assert_not_reached();
43
+}
44
+#define ARCH_USE_GNU_PROPERTY 0
45
+
46
struct exec
47
{
48
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
49
@@ -XXX,XX +XXX,XX @@ void probe_guest_base(const char *image_name, abi_ulong guest_loaddr,
50
"@ 0x%" PRIx64 "\n", (uint64_t)guest_base);
51
}
52
53
+enum {
54
+ /* The string "GNU\0" as a magic number. */
55
+ GNU0_MAGIC = const_le32('G' | 'N' << 8 | 'U' << 16),
56
+ NOTE_DATA_SZ = 1 * KiB,
57
+ NOTE_NAME_SZ = 4,
58
+ ELF_GNU_PROPERTY_ALIGN = ELF_CLASS == ELFCLASS32 ? 4 : 8,
59
+};
60
+
44
+/*
61
+/*
45
+ * Allwinner H3 System on Chip emulation
62
+ * Process a single gnu_property entry.
46
+ *
63
+ * Return false for error.
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
48
+ *
49
+ * This program is free software: you can redistribute it and/or modify
50
+ * it under the terms of the GNU General Public License as published by
51
+ * the Free Software Foundation, either version 2 of the License, or
52
+ * (at your option) any later version.
53
+ *
54
+ * This program is distributed in the hope that it will be useful,
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57
+ * GNU General Public License for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
64
+ */
62
+
65
+static bool parse_elf_property(const uint32_t *data, int *off, int datasz,
63
+/*
66
+ struct image_info *info, bool have_prev_type,
64
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
67
+ uint32_t *prev_type, Error **errp)
65
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
66
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
67
+ * various I/O modules.
68
+ *
69
+ * This implementation is based on the following datasheet:
70
+ *
71
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
72
+ *
73
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
74
+ *
75
+ * https://linux-sunxi.org/H3
76
+ */
77
+
78
+#ifndef HW_ARM_ALLWINNER_H3_H
79
+#define HW_ARM_ALLWINNER_H3_H
80
+
81
+#include "qom/object.h"
82
+#include "hw/arm/boot.h"
83
+#include "hw/timer/allwinner-a10-pit.h"
84
+#include "hw/intc/arm_gic.h"
85
+#include "target/arm/cpu.h"
86
+
87
+/**
88
+ * Allwinner H3 device list
89
+ *
90
+ * This enumeration is can be used refer to a particular device in the
91
+ * Allwinner H3 SoC. For example, the physical memory base address for
92
+ * each device can be found in the AwH3State object in the memmap member
93
+ * using the device enum value as index.
94
+ *
95
+ * @see AwH3State
96
+ */
97
+enum {
98
+ AW_H3_SRAM_A1,
99
+ AW_H3_SRAM_A2,
100
+ AW_H3_SRAM_C,
101
+ AW_H3_PIT,
102
+ AW_H3_UART0,
103
+ AW_H3_UART1,
104
+ AW_H3_UART2,
105
+ AW_H3_UART3,
106
+ AW_H3_GIC_DIST,
107
+ AW_H3_GIC_CPU,
108
+ AW_H3_GIC_HYP,
109
+ AW_H3_GIC_VCPU,
110
+ AW_H3_SDRAM
111
+};
112
+
113
+/** Total number of CPU cores in the H3 SoC */
114
+#define AW_H3_NUM_CPUS (4)
115
+
116
+/**
117
+ * Allwinner H3 object model
118
+ * @{
119
+ */
120
+
121
+/** Object type for the Allwinner H3 SoC */
122
+#define TYPE_AW_H3 "allwinner-h3"
123
+
124
+/** Convert input object to Allwinner H3 state object */
125
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
126
+
127
+/** @} */
128
+
129
+/**
130
+ * Allwinner H3 object
131
+ *
132
+ * This struct contains the state of all the devices
133
+ * which are currently emulated by the H3 SoC code.
134
+ */
135
+typedef struct AwH3State {
136
+ /*< private >*/
137
+ DeviceState parent_obj;
138
+ /*< public >*/
139
+
140
+ ARMCPU cpus[AW_H3_NUM_CPUS];
141
+ const hwaddr *memmap;
142
+ AwA10PITState timer;
143
+ GICState gic;
144
+ MemoryRegion sram_a1;
145
+ MemoryRegion sram_a2;
146
+ MemoryRegion sram_c;
147
+} AwH3State;
148
+
149
+#endif /* HW_ARM_ALLWINNER_H3_H */
150
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
151
new file mode 100644
152
index XXXXXXX..XXXXXXX
153
--- /dev/null
154
+++ b/hw/arm/allwinner-h3.c
155
@@ -XXX,XX +XXX,XX @@
156
+/*
157
+ * Allwinner H3 System on Chip emulation
158
+ *
159
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
160
+ *
161
+ * This program is free software: you can redistribute it and/or modify
162
+ * it under the terms of the GNU General Public License as published by
163
+ * the Free Software Foundation, either version 2 of the License, or
164
+ * (at your option) any later version.
165
+ *
166
+ * This program is distributed in the hope that it will be useful,
167
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
168
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
169
+ * GNU General Public License for more details.
170
+ *
171
+ * You should have received a copy of the GNU General Public License
172
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
173
+ */
174
+
175
+#include "qemu/osdep.h"
176
+#include "exec/address-spaces.h"
177
+#include "qapi/error.h"
178
+#include "qemu/error-report.h"
179
+#include "qemu/module.h"
180
+#include "qemu/units.h"
181
+#include "hw/qdev-core.h"
182
+#include "cpu.h"
183
+#include "hw/sysbus.h"
184
+#include "hw/char/serial.h"
185
+#include "hw/misc/unimp.h"
186
+#include "sysemu/sysemu.h"
187
+#include "hw/arm/allwinner-h3.h"
188
+
189
+/* Memory map */
190
+const hwaddr allwinner_h3_memmap[] = {
191
+ [AW_H3_SRAM_A1] = 0x00000000,
192
+ [AW_H3_SRAM_A2] = 0x00044000,
193
+ [AW_H3_SRAM_C] = 0x00010000,
194
+ [AW_H3_PIT] = 0x01c20c00,
195
+ [AW_H3_UART0] = 0x01c28000,
196
+ [AW_H3_UART1] = 0x01c28400,
197
+ [AW_H3_UART2] = 0x01c28800,
198
+ [AW_H3_UART3] = 0x01c28c00,
199
+ [AW_H3_GIC_DIST] = 0x01c81000,
200
+ [AW_H3_GIC_CPU] = 0x01c82000,
201
+ [AW_H3_GIC_HYP] = 0x01c84000,
202
+ [AW_H3_GIC_VCPU] = 0x01c86000,
203
+ [AW_H3_SDRAM] = 0x40000000
204
+};
205
+
206
+/* List of unimplemented devices */
207
+struct AwH3Unimplemented {
208
+ const char *device_name;
209
+ hwaddr base;
210
+ hwaddr size;
211
+} unimplemented[] = {
212
+ { "d-engine", 0x01000000, 4 * MiB },
213
+ { "d-inter", 0x01400000, 128 * KiB },
214
+ { "syscon", 0x01c00000, 4 * KiB },
215
+ { "dma", 0x01c02000, 4 * KiB },
216
+ { "nfdc", 0x01c03000, 4 * KiB },
217
+ { "ts", 0x01c06000, 4 * KiB },
218
+ { "keymem", 0x01c0b000, 4 * KiB },
219
+ { "lcd0", 0x01c0c000, 4 * KiB },
220
+ { "lcd1", 0x01c0d000, 4 * KiB },
221
+ { "ve", 0x01c0e000, 4 * KiB },
222
+ { "mmc0", 0x01c0f000, 4 * KiB },
223
+ { "mmc1", 0x01c10000, 4 * KiB },
224
+ { "mmc2", 0x01c11000, 4 * KiB },
225
+ { "sid", 0x01c14000, 1 * KiB },
226
+ { "crypto", 0x01c15000, 4 * KiB },
227
+ { "msgbox", 0x01c17000, 4 * KiB },
228
+ { "spinlock", 0x01c18000, 4 * KiB },
229
+ { "usb0-otg", 0x01c19000, 4 * KiB },
230
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
231
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
232
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
233
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
234
+ { "smc", 0x01c1e000, 4 * KiB },
235
+ { "ccu", 0x01c20000, 1 * KiB },
236
+ { "pio", 0x01c20800, 1 * KiB },
237
+ { "owa", 0x01c21000, 1 * KiB },
238
+ { "pwm", 0x01c21400, 1 * KiB },
239
+ { "keyadc", 0x01c21800, 1 * KiB },
240
+ { "pcm0", 0x01c22000, 1 * KiB },
241
+ { "pcm1", 0x01c22400, 1 * KiB },
242
+ { "pcm2", 0x01c22800, 1 * KiB },
243
+ { "audio", 0x01c22c00, 2 * KiB },
244
+ { "smta", 0x01c23400, 1 * KiB },
245
+ { "ths", 0x01c25000, 1 * KiB },
246
+ { "uart0", 0x01c28000, 1 * KiB },
247
+ { "uart1", 0x01c28400, 1 * KiB },
248
+ { "uart2", 0x01c28800, 1 * KiB },
249
+ { "uart3", 0x01c28c00, 1 * KiB },
250
+ { "twi0", 0x01c2ac00, 1 * KiB },
251
+ { "twi1", 0x01c2b000, 1 * KiB },
252
+ { "twi2", 0x01c2b400, 1 * KiB },
253
+ { "scr", 0x01c2c400, 1 * KiB },
254
+ { "emac", 0x01c30000, 64 * KiB },
255
+ { "gpu", 0x01c40000, 64 * KiB },
256
+ { "hstmr", 0x01c60000, 4 * KiB },
257
+ { "dramcom", 0x01c62000, 4 * KiB },
258
+ { "dramctl0", 0x01c63000, 4 * KiB },
259
+ { "dramphy0", 0x01c65000, 4 * KiB },
260
+ { "spi0", 0x01c68000, 4 * KiB },
261
+ { "spi1", 0x01c69000, 4 * KiB },
262
+ { "csi", 0x01cb0000, 320 * KiB },
263
+ { "tve", 0x01e00000, 64 * KiB },
264
+ { "hdmi", 0x01ee0000, 128 * KiB },
265
+ { "rtc", 0x01f00000, 1 * KiB },
266
+ { "r_timer", 0x01f00800, 1 * KiB },
267
+ { "r_intc", 0x01f00c00, 1 * KiB },
268
+ { "r_wdog", 0x01f01000, 1 * KiB },
269
+ { "r_prcm", 0x01f01400, 1 * KiB },
270
+ { "r_twd", 0x01f01800, 1 * KiB },
271
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
272
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
273
+ { "r_twi", 0x01f02400, 1 * KiB },
274
+ { "r_uart", 0x01f02800, 1 * KiB },
275
+ { "r_pio", 0x01f02c00, 1 * KiB },
276
+ { "r_pwm", 0x01f03800, 1 * KiB },
277
+ { "core-dbg", 0x3f500000, 128 * KiB },
278
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
279
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
280
+ { "ddr-mem", 0x40000000, 2 * GiB },
281
+ { "n-brom", 0xffff0000, 32 * KiB },
282
+ { "s-brom", 0xffff0000, 64 * KiB }
283
+};
284
+
285
+/* Per Processor Interrupts */
286
+enum {
287
+ AW_H3_GIC_PPI_MAINT = 9,
288
+ AW_H3_GIC_PPI_HYPTIMER = 10,
289
+ AW_H3_GIC_PPI_VIRTTIMER = 11,
290
+ AW_H3_GIC_PPI_SECTIMER = 13,
291
+ AW_H3_GIC_PPI_PHYSTIMER = 14
292
+};
293
+
294
+/* Shared Processor Interrupts */
295
+enum {
296
+ AW_H3_GIC_SPI_UART0 = 0,
297
+ AW_H3_GIC_SPI_UART1 = 1,
298
+ AW_H3_GIC_SPI_UART2 = 2,
299
+ AW_H3_GIC_SPI_UART3 = 3,
300
+ AW_H3_GIC_SPI_TIMER0 = 18,
301
+ AW_H3_GIC_SPI_TIMER1 = 19,
302
+};
303
+
304
+/* Allwinner H3 general constants */
305
+enum {
306
+ AW_H3_GIC_NUM_SPI = 128
307
+};
308
+
309
+static void allwinner_h3_init(Object *obj)
310
+{
68
+{
311
+ AwH3State *s = AW_H3(obj);
69
+ uint32_t pr_type, pr_datasz, step;
312
+
70
+
313
+ s->memmap = allwinner_h3_memmap;
71
+ if (*off > datasz || !QEMU_IS_ALIGNED(*off, ELF_GNU_PROPERTY_ALIGN)) {
314
+
72
+ goto error_data;
315
+ for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
73
+ }
316
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
74
+ datasz -= *off;
317
+ ARM_CPU_TYPE_NAME("cortex-a7"),
75
+ data += *off / sizeof(uint32_t);
318
+ &error_abort, NULL);
76
+
319
+ }
77
+ if (datasz < 2 * sizeof(uint32_t)) {
320
+
78
+ goto error_data;
321
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
79
+ }
322
+ TYPE_ARM_GIC);
80
+ pr_type = data[0];
323
+
81
+ pr_datasz = data[1];
324
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
82
+ data += 2;
325
+ TYPE_AW_A10_PIT);
83
+ datasz -= 2 * sizeof(uint32_t);
326
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
84
+ step = ROUND_UP(pr_datasz, ELF_GNU_PROPERTY_ALIGN);
327
+ "clk0-freq", &error_abort);
85
+ if (step > datasz) {
328
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
86
+ goto error_data;
329
+ "clk1-freq", &error_abort);
87
+ }
88
+
89
+ /* Properties are supposed to be unique and sorted on pr_type. */
90
+ if (have_prev_type && pr_type <= *prev_type) {
91
+ if (pr_type == *prev_type) {
92
+ error_setg(errp, "Duplicate property in PT_GNU_PROPERTY");
93
+ } else {
94
+ error_setg(errp, "Unsorted property in PT_GNU_PROPERTY");
95
+ }
96
+ return false;
97
+ }
98
+ *prev_type = pr_type;
99
+
100
+ if (!arch_parse_elf_property(pr_type, pr_datasz, data, info, errp)) {
101
+ return false;
102
+ }
103
+
104
+ *off += 2 * sizeof(uint32_t) + step;
105
+ return true;
106
+
107
+ error_data:
108
+ error_setg(errp, "Ill-formed property in PT_GNU_PROPERTY");
109
+ return false;
330
+}
110
+}
331
+
111
+
332
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
112
+/* Process NT_GNU_PROPERTY_TYPE_0. */
113
+static bool parse_elf_properties(int image_fd,
114
+ struct image_info *info,
115
+ const struct elf_phdr *phdr,
116
+ char bprm_buf[BPRM_BUF_SIZE],
117
+ Error **errp)
333
+{
118
+{
334
+ AwH3State *s = AW_H3(dev);
119
+ union {
335
+ unsigned i;
120
+ struct elf_note nhdr;
336
+
121
+ uint32_t data[NOTE_DATA_SZ / sizeof(uint32_t)];
337
+ /* CPUs */
122
+ } note;
338
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
123
+
339
+
124
+ int n, off, datasz;
340
+ /* Provide Power State Coordination Interface */
125
+ bool have_prev_type;
341
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
126
+ uint32_t prev_type;
342
+ QEMU_PSCI_CONDUIT_HVC);
127
+
343
+
128
+ /* Unless the arch requires properties, ignore them. */
344
+ /* Disable secondary CPUs */
129
+ if (!ARCH_USE_GNU_PROPERTY) {
345
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
130
+ return true;
346
+ i > 0);
131
+ }
347
+
132
+
348
+ /* All exception levels required */
133
+ /* If the properties are crazy large, that's too bad. */
349
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
134
+ n = phdr->p_filesz;
350
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
135
+ if (n > sizeof(note)) {
351
+
136
+ error_setg(errp, "PT_GNU_PROPERTY too large");
352
+ /* Mark realized */
137
+ return false;
353
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
138
+ }
354
+ }
139
+ if (n < sizeof(note.nhdr)) {
355
+
140
+ error_setg(errp, "PT_GNU_PROPERTY too small");
356
+ /* Generic Interrupt Controller */
141
+ return false;
357
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
142
+ }
358
+ GIC_INTERNAL);
143
+
359
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
144
+ if (phdr->p_offset + n <= BPRM_BUF_SIZE) {
360
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
145
+ memcpy(&note, bprm_buf + phdr->p_offset, n);
361
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
146
+ } else {
362
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
147
+ ssize_t len = pread(image_fd, &note, n, phdr->p_offset);
363
+ qdev_init_nofail(DEVICE(&s->gic));
148
+ if (len != n) {
364
+
149
+ error_setg_errno(errp, errno, "Error reading file header");
365
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
150
+ return false;
366
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
151
+ }
367
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
152
+ }
368
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
369
+
153
+
370
+ /*
154
+ /*
371
+ * Wire the outputs from each CPU's generic timer and the GICv3
155
+ * The contents of a valid PT_GNU_PROPERTY is a sequence
372
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
156
+ * of uint32_t -- swap them all now.
373
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
374
+ */
157
+ */
375
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
158
+#ifdef BSWAP_NEEDED
376
+ DeviceState *cpudev = DEVICE(&s->cpus[i]);
159
+ for (int i = 0; i < n / 4; i++) {
377
+ int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
160
+ bswap32s(note.data + i);
378
+ int irq;
161
+ }
379
+ /*
162
+#endif
380
+ * Mapping from the output timer irq lines from the CPU to the
163
+
381
+ * GIC PPI inputs used for this board.
164
+ /*
382
+ */
165
+ * Note that nhdr is 3 words, and that the "name" described by namesz
383
+ const int timer_irq[] = {
166
+ * immediately follows nhdr and is thus at the 4th word. Further, all
384
+ [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
167
+ * of the inputs to the kernel's round_up are multiples of 4.
385
+ [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
168
+ */
386
+ [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
169
+ if (note.nhdr.n_type != NT_GNU_PROPERTY_TYPE_0 ||
387
+ [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
170
+ note.nhdr.n_namesz != NOTE_NAME_SZ ||
388
+ };
171
+ note.data[3] != GNU0_MAGIC) {
389
+
172
+ error_setg(errp, "Invalid note in PT_GNU_PROPERTY");
390
+ /* Connect CPU timer outputs to GIC PPI inputs */
173
+ return false;
391
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
174
+ }
392
+ qdev_connect_gpio_out(cpudev, irq,
175
+ off = sizeof(note.nhdr) + NOTE_NAME_SZ;
393
+ qdev_get_gpio_in(DEVICE(&s->gic),
176
+
394
+ ppibase + timer_irq[irq]));
177
+ datasz = note.nhdr.n_descsz + off;
395
+ }
178
+ if (datasz > n) {
396
+
179
+ error_setg(errp, "Invalid note size in PT_GNU_PROPERTY");
397
+ /* Connect GIC outputs to CPU interrupt inputs */
180
+ return false;
398
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
181
+ }
399
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
182
+
400
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
183
+ have_prev_type = false;
401
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
184
+ prev_type = 0;
402
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
185
+ while (1) {
403
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
186
+ if (off == datasz) {
404
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
187
+ return true; /* end, exit ok */
405
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
188
+ }
406
+
189
+ if (!parse_elf_property(note.data, &off, datasz, info,
407
+ /* GIC maintenance signal */
190
+ have_prev_type, &prev_type, errp)) {
408
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
191
+ return false;
409
+ qdev_get_gpio_in(DEVICE(&s->gic),
192
+ }
410
+ ppibase + AW_H3_GIC_PPI_MAINT));
193
+ have_prev_type = true;
411
+ }
412
+
413
+ /* Timer */
414
+ qdev_init_nofail(DEVICE(&s->timer));
415
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
416
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
417
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
418
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
419
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
420
+
421
+ /* SRAM */
422
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
423
+ 64 * KiB, &error_abort);
424
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
425
+ 32 * KiB, &error_abort);
426
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
427
+ 44 * KiB, &error_abort);
428
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
429
+ &s->sram_a1);
430
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
431
+ &s->sram_a2);
432
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
433
+ &s->sram_c);
434
+
435
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
436
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
437
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
438
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
439
+ /* UART1 */
440
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
441
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
442
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
443
+ /* UART2 */
444
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
445
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
446
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
447
+ /* UART3 */
448
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
449
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
450
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
451
+
452
+ /* Unimplemented devices */
453
+ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
454
+ create_unimplemented_device(unimplemented[i].device_name,
455
+ unimplemented[i].base,
456
+ unimplemented[i].size);
457
+ }
194
+ }
458
+}
195
+}
459
+
196
+
460
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
197
/* Load an ELF image into the address space.
461
+{
198
462
+ DeviceClass *dc = DEVICE_CLASS(oc);
199
IMAGE_NAME is the filename of the image, to use in error messages.
463
+
200
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
464
+ dc->realize = allwinner_h3_realize;
201
goto exit_errmsg;
465
+ /* Reason: uses serial_hd() in realize function */
202
}
466
+ dc->user_creatable = false;
203
*pinterp_name = g_steal_pointer(&interp_name);
467
+}
204
+ } else if (eppnt->p_type == PT_GNU_PROPERTY) {
468
+
205
+ if (!parse_elf_properties(image_fd, info, eppnt, bprm_buf, &err)) {
469
+static const TypeInfo allwinner_h3_type_info = {
206
+ goto exit_errmsg;
470
+ .name = TYPE_AW_H3,
207
+ }
471
+ .parent = TYPE_DEVICE,
208
}
472
+ .instance_size = sizeof(AwH3State),
209
}
473
+ .instance_init = allwinner_h3_init,
210
474
+ .class_init = allwinner_h3_class_init,
475
+};
476
+
477
+static void allwinner_h3_register_types(void)
478
+{
479
+ type_register_static(&allwinner_h3_type_info);
480
+}
481
+
482
+type_init(allwinner_h3_register_types)
483
diff --git a/MAINTAINERS b/MAINTAINERS
484
index XXXXXXX..XXXXXXX 100644
485
--- a/MAINTAINERS
486
+++ b/MAINTAINERS
487
@@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner*
488
F: include/hw/*/allwinner*
489
F: hw/arm/cubieboard.c
490
491
+Allwinner-h3
492
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
493
+L: qemu-arm@nongnu.org
494
+S: Maintained
495
+F: hw/*/allwinner-h3*
496
+F: include/hw/*/allwinner-h3*
497
+
498
ARM PrimeCell and CMSDK devices
499
M: Peter Maydell <peter.maydell@linaro.org>
500
L: qemu-arm@nongnu.org
501
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
502
index XXXXXXX..XXXXXXX 100644
503
--- a/default-configs/arm-softmmu.mak
504
+++ b/default-configs/arm-softmmu.mak
505
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y
506
CONFIG_FSL_IMX7=y
507
CONFIG_FSL_IMX6UL=y
508
CONFIG_SEMIHOSTING=y
509
+CONFIG_ALLWINNER_H3=y
510
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
511
index XXXXXXX..XXXXXXX 100644
512
--- a/hw/arm/Kconfig
513
+++ b/hw/arm/Kconfig
514
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
515
select SERIAL
516
select UNIMP
517
518
+config ALLWINNER_H3
519
+ bool
520
+ select ALLWINNER_A10_PIT
521
+ select SERIAL
522
+ select ARM_TIMER
523
+ select ARM_GIC
524
+ select UNIMP
525
+
526
config RASPI
527
bool
528
select FRAMEBUFFER
529
--
211
--
530
2.20.1
212
2.20.1
531
213
532
214
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
i.MX25 supports two USB controllers. Let's wire them up.
3
Use the new generic support for NT_GNU_PROPERTY_TYPE_0.
4
4
5
With this patch, imx25-pdk can boot from both USB ports.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
6
Message-id: 20201016184207.786698-12-richard.henderson@linaro.org
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200310215146.19688-3-linux@roeck-us.net
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
include/hw/arm/fsl-imx25.h | 9 +++++++++
10
linux-user/elfload.c | 48 ++++++++++++++++++++++++++++++++++++++++++--
13
hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++
11
1 file changed, 46 insertions(+), 2 deletions(-)
14
2 files changed, 33 insertions(+)
15
12
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
13
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
15
--- a/linux-user/elfload.c
19
+++ b/include/hw/arm/fsl-imx25.h
16
+++ b/linux-user/elfload.c
20
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
21
#include "hw/i2c/imx_i2c.h"
18
22
#include "hw/gpio/imx_gpio.h"
19
#include "elf.h"
23
#include "hw/sd/sdhci.h"
20
24
+#include "hw/usb/chipidea.h"
21
+/* We must delay the following stanzas until after "elf.h". */
25
#include "exec/memory.h"
22
+#if defined(TARGET_AARCH64)
26
#include "target/arm/cpu.h"
27
28
@@ -XXX,XX +XXX,XX @@
29
#define FSL_IMX25_NUM_I2CS 3
30
#define FSL_IMX25_NUM_GPIOS 4
31
#define FSL_IMX25_NUM_ESDHCS 2
32
+#define FSL_IMX25_NUM_USBS 2
33
34
typedef struct FslIMX25State {
35
/*< private >*/
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
38
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
39
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
40
+ ChipideaState usb[FSL_IMX25_NUM_USBS];
41
MemoryRegion rom[2];
42
MemoryRegion iram;
43
MemoryRegion iram_alias;
44
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
45
#define FSL_IMX25_GPIO1_SIZE 0x4000
46
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
47
#define FSL_IMX25_GPIO2_SIZE 0x4000
48
+#define FSL_IMX25_USB1_ADDR 0x53FF4000
49
+#define FSL_IMX25_USB1_SIZE 0x0200
50
+#define FSL_IMX25_USB2_ADDR 0x53FF4400
51
+#define FSL_IMX25_USB2_SIZE 0x0200
52
#define FSL_IMX25_AVIC_ADDR 0x68000000
53
#define FSL_IMX25_AVIC_SIZE 0x4000
54
#define FSL_IMX25_IRAM_ADDR 0x78000000
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
56
#define FSL_IMX25_GPIO4_IRQ 23
57
#define FSL_IMX25_ESDHC1_IRQ 9
58
#define FSL_IMX25_ESDHC2_IRQ 8
59
+#define FSL_IMX25_USB1_IRQ 37
60
+#define FSL_IMX25_USB2_IRQ 35
61
62
#endif /* FSL_IMX25_H */
63
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/fsl-imx25.c
66
+++ b/hw/arm/fsl-imx25.c
67
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
68
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
69
TYPE_IMX_USDHC);
70
}
71
+
23
+
72
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
24
+static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
73
+ sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
25
+ const uint32_t *data,
74
+ TYPE_CHIPIDEA);
26
+ struct image_info *info,
27
+ Error **errp)
28
+{
29
+ if (pr_type == GNU_PROPERTY_AARCH64_FEATURE_1_AND) {
30
+ if (pr_datasz != sizeof(uint32_t)) {
31
+ error_setg(errp, "Ill-formed GNU_PROPERTY_AARCH64_FEATURE_1_AND");
32
+ return false;
33
+ }
34
+ /* We will extract GNU_PROPERTY_AARCH64_FEATURE_1_BTI later. */
35
+ info->note_flags = *data;
75
+ }
36
+ }
37
+ return true;
38
+}
39
+#define ARCH_USE_GNU_PROPERTY 1
76
+
40
+
41
+#else
42
+
43
static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
44
const uint32_t *data,
45
struct image_info *info,
46
@@ -XXX,XX +XXX,XX @@ static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
77
}
47
}
78
48
#define ARCH_USE_GNU_PROPERTY 0
79
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
49
80
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
50
+#endif
81
esdhc_table[i].irq));
82
}
83
84
+ /* USB */
85
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
86
+ static const struct {
87
+ hwaddr addr;
88
+ unsigned int irq;
89
+ } usb_table[FSL_IMX25_NUM_USBS] = {
90
+ { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
91
+ { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
92
+ };
93
+
51
+
94
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
52
struct exec
95
+ &error_abort);
53
{
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
54
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
97
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
55
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
98
+ qdev_get_gpio_in(DEVICE(&s->avic),
56
struct elfhdr *ehdr = (struct elfhdr *)bprm_buf;
99
+ usb_table[i].irq));
57
struct elf_phdr *phdr;
58
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
59
- int i, retval;
60
+ int i, retval, prot_exec;
61
Error *err = NULL;
62
63
/* First of all, some simple consistency checks */
64
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
65
info->brk = 0;
66
info->elf_flags = ehdr->e_flags;
67
68
+ prot_exec = PROT_EXEC;
69
+#ifdef TARGET_AARCH64
70
+ /*
71
+ * If the BTI feature is present, this indicates that the executable
72
+ * pages of the startup binary should be mapped with PROT_BTI, so that
73
+ * branch targets are enforced.
74
+ *
75
+ * The startup binary is either the interpreter or the static executable.
76
+ * The interpreter is responsible for all pages of a dynamic executable.
77
+ *
78
+ * Elf notes are backward compatible to older cpus.
79
+ * Do not enable BTI unless it is supported.
80
+ */
81
+ if ((info->note_flags & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
82
+ && (pinterp_name == NULL || *pinterp_name == 0)
83
+ && cpu_isar_feature(aa64_bti, ARM_CPU(thread_cpu))) {
84
+ prot_exec |= TARGET_PROT_BTI;
100
+ }
85
+ }
86
+#endif
101
+
87
+
102
/* initialize 2 x 16 KB ROM */
88
for (i = 0; i < ehdr->e_phnum; i++) {
103
memory_region_init_rom(&s->rom[0], NULL,
89
struct elf_phdr *eppnt = phdr + i;
104
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
90
if (eppnt->p_type == PT_LOAD) {
91
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
92
elf_prot |= PROT_WRITE;
93
}
94
if (eppnt->p_flags & PF_X) {
95
- elf_prot |= PROT_EXEC;
96
+ elf_prot |= prot_exec;
97
}
98
99
vaddr = load_bias + eppnt->p_vaddr;
105
--
100
--
106
2.20.1
101
2.20.1
107
102
108
103
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Clock Control Unit is responsible for clock signal generation,
3
The note test requires gcc 10 for -mbranch-protection=standard.
4
configuration and distribution in the Allwinner H3 System on Chip.
4
The mmap test uses PROT_BTI and does not require special compiler support.
5
This commit adds support for the Clock Control Unit which emulates
5
6
a simple read/write register interface.
6
Acked-by: Alex Bennée <alex.bennee@linaro.org>
7
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201016184207.786698-13-richard.henderson@linaro.org
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
hw/misc/Makefile.objs | 1 +
12
tests/tcg/aarch64/bti-1.c | 62 +++++++++++++++++
16
include/hw/arm/allwinner-h3.h | 3 +
13
tests/tcg/aarch64/bti-2.c | 108 ++++++++++++++++++++++++++++++
17
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
14
tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
15
tests/tcg/aarch64/Makefile.target | 10 +++
19
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
16
tests/tcg/configure.sh | 4 ++
20
5 files changed, 320 insertions(+), 1 deletion(-)
17
5 files changed, 235 insertions(+)
21
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
18
create mode 100644 tests/tcg/aarch64/bti-1.c
22
create mode 100644 hw/misc/allwinner-h3-ccu.c
19
create mode 100644 tests/tcg/aarch64/bti-2.c
23
20
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
21
25
index XXXXXXX..XXXXXXX 100644
22
diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c
26
--- a/hw/misc/Makefile.objs
27
+++ b/hw/misc/Makefile.objs
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
29
30
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
31
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/arm/boot.h"
42
#include "hw/timer/allwinner-a10-pit.h"
43
#include "hw/intc/arm_gic.h"
44
+#include "hw/misc/allwinner-h3-ccu.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
AW_H3_UART1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
ARMCPU cpus[AW_H3_NUM_CPUS];
58
const hwaddr *memmap;
59
AwA10PITState timer;
60
+ AwH3ClockCtlState ccu;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h
65
new file mode 100644
23
new file mode 100644
66
index XXXXXXX..XXXXXXX
24
index XXXXXXX..XXXXXXX
67
--- /dev/null
25
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-ccu.h
26
+++ b/tests/tcg/aarch64/bti-1.c
69
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@
70
+/*
28
+/*
71
+ * Allwinner H3 Clock Control Unit emulation
29
+ * Branch target identification, basic notskip cases.
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
30
+ */
88
+
31
+
89
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
32
+#include "bti-crt.inc.c"
90
+#define HW_MISC_ALLWINNER_H3_CCU_H
33
+
91
+
34
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
92
+#include "qom/object.h"
35
+{
93
+#include "hw/sysbus.h"
36
+ uc->uc_mcontext.pc += 8;
94
+
37
+ uc->uc_mcontext.pstate = 1;
95
+/**
38
+}
96
+ * @name Constants
39
+
97
+ * @{
40
+#define NOP "nop"
98
+ */
41
+#define BTI_N "hint #32"
99
+
42
+#define BTI_C "hint #34"
100
+/** Size of register I/O address space used by CCU device */
43
+#define BTI_J "hint #36"
101
+#define AW_H3_CCU_IOSIZE (0x400)
44
+#define BTI_JC "hint #38"
102
+
45
+
103
+/** Total number of known registers */
46
+#define BTYPE_1(DEST) \
104
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
47
+ asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
105
+
48
+ : "=r"(skipped) : : "x16")
106
+/** @} */
49
+
107
+
50
+#define BTYPE_2(DEST) \
108
+/**
51
+ asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
109
+ * @name Object model
52
+ : "=r"(skipped) : : "x16", "x30")
110
+ * @{
53
+
111
+ */
54
+#define BTYPE_3(DEST) \
112
+
55
+ asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
113
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
56
+ : "=r"(skipped) : : "x15")
114
+#define AW_H3_CCU(obj) \
57
+
115
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
58
+#define TEST(WHICH, DEST, EXPECT) \
116
+
59
+ do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0)
117
+/** @} */
60
+
118
+
61
+
119
+/**
62
+int main()
120
+ * Allwinner H3 CCU object instance state.
63
+{
121
+ */
64
+ int fail = 0;
122
+typedef struct AwH3ClockCtlState {
65
+ int skipped;
123
+ /*< private >*/
66
+
124
+ SysBusDevice parent_obj;
67
+ /* Signal-like with SA_SIGINFO. */
125
+ /*< public >*/
68
+ signal_info(SIGILL, skip2_sigill);
126
+
69
+
127
+ /** Maps I/O registers in physical memory */
70
+ TEST(BTYPE_1, NOP, 1);
128
+ MemoryRegion iomem;
71
+ TEST(BTYPE_1, BTI_N, 1);
129
+
72
+ TEST(BTYPE_1, BTI_C, 0);
130
+ /** Array of hardware registers */
73
+ TEST(BTYPE_1, BTI_J, 0);
131
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
74
+ TEST(BTYPE_1, BTI_JC, 0);
132
+
75
+
133
+} AwH3ClockCtlState;
76
+ TEST(BTYPE_2, NOP, 1);
134
+
77
+ TEST(BTYPE_2, BTI_N, 1);
135
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
78
+ TEST(BTYPE_2, BTI_C, 0);
136
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
79
+ TEST(BTYPE_2, BTI_J, 1);
137
index XXXXXXX..XXXXXXX 100644
80
+ TEST(BTYPE_2, BTI_JC, 0);
138
--- a/hw/arm/allwinner-h3.c
81
+
139
+++ b/hw/arm/allwinner-h3.c
82
+ TEST(BTYPE_3, NOP, 1);
140
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
83
+ TEST(BTYPE_3, BTI_N, 1);
141
[AW_H3_SRAM_A1] = 0x00000000,
84
+ TEST(BTYPE_3, BTI_C, 1);
142
[AW_H3_SRAM_A2] = 0x00044000,
85
+ TEST(BTYPE_3, BTI_J, 0);
143
[AW_H3_SRAM_C] = 0x00010000,
86
+ TEST(BTYPE_3, BTI_JC, 0);
144
+ [AW_H3_CCU] = 0x01c20000,
87
+
145
[AW_H3_PIT] = 0x01c20c00,
88
+ return fail;
146
[AW_H3_UART0] = 0x01c28000,
89
+}
147
[AW_H3_UART1] = 0x01c28400,
90
diff --git a/tests/tcg/aarch64/bti-2.c b/tests/tcg/aarch64/bti-2.c
148
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
149
{ "usb2-phy", 0x01c1c000, 4 * KiB },
150
{ "usb3-phy", 0x01c1d000, 4 * KiB },
151
{ "smc", 0x01c1e000, 4 * KiB },
152
- { "ccu", 0x01c20000, 1 * KiB },
153
{ "pio", 0x01c20800, 1 * KiB },
154
{ "owa", 0x01c21000, 1 * KiB },
155
{ "pwm", 0x01c21400, 1 * KiB },
156
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
157
"clk0-freq", &error_abort);
158
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
159
"clk1-freq", &error_abort);
160
+
161
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
162
+ TYPE_AW_H3_CCU);
163
}
164
165
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
166
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
168
&s->sram_c);
169
170
+ /* Clock Control Unit */
171
+ qdev_init_nofail(DEVICE(&s->ccu));
172
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
173
+
174
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
175
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
176
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
177
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
178
new file mode 100644
91
new file mode 100644
179
index XXXXXXX..XXXXXXX
92
index XXXXXXX..XXXXXXX
180
--- /dev/null
93
--- /dev/null
181
+++ b/hw/misc/allwinner-h3-ccu.c
94
+++ b/tests/tcg/aarch64/bti-2.c
182
@@ -XXX,XX +XXX,XX @@
95
@@ -XXX,XX +XXX,XX @@
183
+/*
96
+/*
184
+ * Allwinner H3 Clock Control Unit emulation
97
+ * Branch target identification, basic notskip cases.
98
+ */
99
+
100
+#include <stdio.h>
101
+#include <signal.h>
102
+#include <string.h>
103
+#include <unistd.h>
104
+#include <sys/mman.h>
105
+
106
+#ifndef PROT_BTI
107
+#define PROT_BTI 0x10
108
+#endif
109
+
110
+static void skip2_sigill(int sig, siginfo_t *info, void *vuc)
111
+{
112
+ ucontext_t *uc = vuc;
113
+ uc->uc_mcontext.pc += 8;
114
+ uc->uc_mcontext.pstate = 1;
115
+}
116
+
117
+#define NOP "nop"
118
+#define BTI_N "hint #32"
119
+#define BTI_C "hint #34"
120
+#define BTI_J "hint #36"
121
+#define BTI_JC "hint #38"
122
+
123
+#define BTYPE_1(DEST) \
124
+ "mov x1, #1\n\t" \
125
+ "adr x16, 1f\n\t" \
126
+ "br x16\n" \
127
+"1: " DEST "\n\t" \
128
+ "mov x1, #0"
129
+
130
+#define BTYPE_2(DEST) \
131
+ "mov x1, #1\n\t" \
132
+ "adr x16, 1f\n\t" \
133
+ "blr x16\n" \
134
+"1: " DEST "\n\t" \
135
+ "mov x1, #0"
136
+
137
+#define BTYPE_3(DEST) \
138
+ "mov x1, #1\n\t" \
139
+ "adr x15, 1f\n\t" \
140
+ "br x15\n" \
141
+"1: " DEST "\n\t" \
142
+ "mov x1, #0"
143
+
144
+#define TEST(WHICH, DEST, EXPECT) \
145
+ WHICH(DEST) "\n" \
146
+ ".if " #EXPECT "\n\t" \
147
+ "eor x1, x1," #EXPECT "\n" \
148
+ ".endif\n\t" \
149
+ "add x0, x0, x1\n\t"
150
+
151
+extern char test_begin[], test_end[];
152
+
153
+asm("\n"
154
+"test_begin:\n\t"
155
+ BTI_C "\n\t"
156
+ "mov x2, x30\n\t"
157
+ "mov x0, #0\n\t"
158
+
159
+ TEST(BTYPE_1, NOP, 1)
160
+ TEST(BTYPE_1, BTI_N, 1)
161
+ TEST(BTYPE_1, BTI_C, 0)
162
+ TEST(BTYPE_1, BTI_J, 0)
163
+ TEST(BTYPE_1, BTI_JC, 0)
164
+
165
+ TEST(BTYPE_2, NOP, 1)
166
+ TEST(BTYPE_2, BTI_N, 1)
167
+ TEST(BTYPE_2, BTI_C, 0)
168
+ TEST(BTYPE_2, BTI_J, 1)
169
+ TEST(BTYPE_2, BTI_JC, 0)
170
+
171
+ TEST(BTYPE_3, NOP, 1)
172
+ TEST(BTYPE_3, BTI_N, 1)
173
+ TEST(BTYPE_3, BTI_C, 1)
174
+ TEST(BTYPE_3, BTI_J, 0)
175
+ TEST(BTYPE_3, BTI_JC, 0)
176
+
177
+ "ret x2\n"
178
+"test_end:"
179
+);
180
+
181
+int main()
182
+{
183
+ struct sigaction sa;
184
+
185
+ void *p = mmap(0, getpagesize(),
186
+ PROT_EXEC | PROT_READ | PROT_WRITE | PROT_BTI,
187
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
188
+ if (p == MAP_FAILED) {
189
+ perror("mmap");
190
+ return 1;
191
+ }
192
+
193
+ memset(&sa, 0, sizeof(sa));
194
+ sa.sa_sigaction = skip2_sigill;
195
+ sa.sa_flags = SA_SIGINFO;
196
+ if (sigaction(SIGILL, &sa, NULL) < 0) {
197
+ perror("sigaction");
198
+ return 1;
199
+ }
200
+
201
+ memcpy(p, test_begin, test_end - test_begin);
202
+ return ((int (*)(void))p)();
203
+}
204
diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c
205
new file mode 100644
206
index XXXXXXX..XXXXXXX
207
--- /dev/null
208
+++ b/tests/tcg/aarch64/bti-crt.inc.c
209
@@ -XXX,XX +XXX,XX @@
210
+/*
211
+ * Minimal user-environment for testing BTI.
185
+ *
212
+ *
186
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
213
+ * Normal libc is not (yet) built with BTI support enabled,
187
+ *
214
+ * and so could generate a BTI TRAP before ever reaching main.
188
+ * This program is free software: you can redistribute it and/or modify
189
+ * it under the terms of the GNU General Public License as published by
190
+ * the Free Software Foundation, either version 2 of the License, or
191
+ * (at your option) any later version.
192
+ *
193
+ * This program is distributed in the hope that it will be useful,
194
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
195
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196
+ * GNU General Public License for more details.
197
+ *
198
+ * You should have received a copy of the GNU General Public License
199
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
200
+ */
215
+ */
201
+
216
+
202
+#include "qemu/osdep.h"
217
+#include <stdlib.h>
203
+#include "qemu/units.h"
218
+#include <signal.h>
204
+#include "hw/sysbus.h"
219
+#include <ucontext.h>
205
+#include "migration/vmstate.h"
220
+#include <asm/unistd.h>
206
+#include "qemu/log.h"
221
+
207
+#include "qemu/module.h"
222
+int main(void);
208
+#include "hw/misc/allwinner-h3-ccu.h"
223
+
209
+
224
+void _start(void)
210
+/* CCU register offsets */
225
+{
211
+enum {
226
+ exit(main());
212
+ REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
227
+}
213
+ REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
228
+
214
+ REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
229
+void exit(int ret)
215
+ REG_PLL_VE = 0x0018, /* PLL VE Control */
230
+{
216
+ REG_PLL_DDR = 0x0020, /* PLL DDR Control */
231
+ register int x0 __asm__("x0") = ret;
217
+ REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
232
+ register int x8 __asm__("x8") = __NR_exit;
218
+ REG_PLL_GPU = 0x0038, /* PLL GPU Control */
233
+
219
+ REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
234
+ asm volatile("svc #0" : : "r"(x0), "r"(x8));
220
+ REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
235
+ __builtin_unreachable();
221
+ REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
236
+}
222
+ REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
237
+
223
+ REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
238
+/*
224
+ REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
239
+ * Irritatingly, the user API struct sigaction does not match the
225
+ REG_MBUS = 0x00FC, /* MBUS Reset */
240
+ * kernel API struct sigaction. So for simplicity, isolate the
226
+ REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
241
+ * kernel ABI here, and make this act like signal.
227
+ REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
242
+ */
228
+ REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
243
+void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *))
229
+ REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
244
+{
230
+ REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
245
+ struct kernel_sigaction {
231
+ REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
246
+ void (*handler)(int, siginfo_t *, ucontext_t *);
232
+ REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
247
+ unsigned long flags;
233
+ REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
248
+ unsigned long restorer;
234
+ REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
249
+ unsigned long mask;
235
+ REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
250
+ } sa = { fn, SA_SIGINFO, 0, 0 };
236
+ REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
251
+
237
+ REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
252
+ register int x0 __asm__("x0") = sig;
238
+ REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
253
+ register void *x1 __asm__("x1") = &sa;
239
+};
254
+ register void *x2 __asm__("x2") = 0;
240
+
255
+ register int x3 __asm__("x3") = sizeof(unsigned long);
241
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
256
+ register int x8 __asm__("x8") = __NR_rt_sigaction;
242
+
257
+
243
+/* CCU register flags */
258
+ asm volatile("svc #0"
244
+enum {
259
+ : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory");
245
+ REG_DRAM_CFG_UPDATE = (1 << 16),
260
+}
246
+};
261
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
247
+
262
index XXXXXXX..XXXXXXX 100644
248
+enum {
263
--- a/tests/tcg/aarch64/Makefile.target
249
+ REG_PLL_ENABLE = (1 << 31),
264
+++ b/tests/tcg/aarch64/Makefile.target
250
+ REG_PLL_LOCK = (1 << 28),
265
@@ -XXX,XX +XXX,XX @@ run-pauth-%: QEMU_OPTS += -cpu max
251
+};
266
run-plugin-pauth-%: QEMU_OPTS += -cpu max
252
+
267
endif
253
+
268
254
+/* CCU register reset values */
269
+# BTI Tests
255
+enum {
270
+# bti-1 tests the elf notes, so we require special compiler support.
256
+ REG_PLL_CPUX_RST = 0x00001000,
271
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_BTI),)
257
+ REG_PLL_AUDIO_RST = 0x00035514,
272
+AARCH64_TESTS += bti-1
258
+ REG_PLL_VIDEO_RST = 0x03006207,
273
+bti-1: CFLAGS += -mbranch-protection=standard
259
+ REG_PLL_VE_RST = 0x03006207,
274
+bti-1: LDFLAGS += -nostdlib
260
+ REG_PLL_DDR_RST = 0x00001000,
275
+endif
261
+ REG_PLL_PERIPH0_RST = 0x00041811,
276
+# bti-2 tests PROT_BTI, so no special compiler support required.
262
+ REG_PLL_GPU_RST = 0x03006207,
277
+AARCH64_TESTS += bti-2
263
+ REG_PLL_PERIPH1_RST = 0x00041811,
278
+
264
+ REG_PLL_DE_RST = 0x03006207,
279
# Semihosting smoke test for linux-user
265
+ REG_CPUX_AXI_RST = 0x00010000,
280
AARCH64_TESTS += semihosting
266
+ REG_APB1_RST = 0x00001010,
281
run-semihosting: semihosting
267
+ REG_APB2_RST = 0x01000000,
282
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
268
+ REG_DRAM_CFG_RST = 0x00000000,
283
index XXXXXXX..XXXXXXX 100755
269
+ REG_MBUS_RST = 0x80000000,
284
--- a/tests/tcg/configure.sh
270
+ REG_PLL_TIME0_RST = 0x000000FF,
285
+++ b/tests/tcg/configure.sh
271
+ REG_PLL_TIME1_RST = 0x000000FF,
286
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
272
+ REG_PLL_CPUX_BIAS_RST = 0x08100200,
287
-march=armv8.3-a -o $TMPE $TMPC; then
273
+ REG_PLL_AUDIO_BIAS_RST = 0x10100000,
288
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
274
+ REG_PLL_VIDEO_BIAS_RST = 0x10100000,
289
fi
275
+ REG_PLL_VE_BIAS_RST = 0x10100000,
290
+ if do_compiler "$target_compiler" $target_compiler_cflags \
276
+ REG_PLL_DDR_BIAS_RST = 0x81104000,
291
+ -mbranch-protection=standard -o $TMPE $TMPC; then
277
+ REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
292
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
278
+ REG_PLL_GPU_BIAS_RST = 0x10100000,
293
+ fi
279
+ REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
294
;;
280
+ REG_PLL_DE_BIAS_RST = 0x10100000,
295
esac
281
+ REG_PLL_CPUX_TUNING_RST = 0x0A101000,
296
282
+ REG_PLL_DDR_TUNING_RST = 0x14880000,
283
+};
284
+
285
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
286
+ unsigned size)
287
+{
288
+ const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
289
+ const uint32_t idx = REG_INDEX(offset);
290
+
291
+ switch (offset) {
292
+ case 0x308 ... AW_H3_CCU_IOSIZE:
293
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
294
+ __func__, (uint32_t)offset);
295
+ return 0;
296
+ }
297
+
298
+ return s->regs[idx];
299
+}
300
+
301
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
302
+ uint64_t val, unsigned size)
303
+{
304
+ AwH3ClockCtlState *s = AW_H3_CCU(opaque);
305
+ const uint32_t idx = REG_INDEX(offset);
306
+
307
+ switch (offset) {
308
+ case REG_DRAM_CFG: /* DRAM Configuration */
309
+ val &= ~REG_DRAM_CFG_UPDATE;
310
+ break;
311
+ case REG_PLL_CPUX: /* PLL CPUX Control */
312
+ case REG_PLL_AUDIO: /* PLL Audio Control */
313
+ case REG_PLL_VIDEO: /* PLL Video Control */
314
+ case REG_PLL_VE: /* PLL VE Control */
315
+ case REG_PLL_DDR: /* PLL DDR Control */
316
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
317
+ case REG_PLL_GPU: /* PLL GPU Control */
318
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
319
+ case REG_PLL_DE: /* PLL Display Engine Control */
320
+ if (val & REG_PLL_ENABLE) {
321
+ val |= REG_PLL_LOCK;
322
+ }
323
+ break;
324
+ case 0x308 ... AW_H3_CCU_IOSIZE:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ default:
329
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
330
+ __func__, (uint32_t)offset);
331
+ break;
332
+ }
333
+
334
+ s->regs[idx] = (uint32_t) val;
335
+}
336
+
337
+static const MemoryRegionOps allwinner_h3_ccu_ops = {
338
+ .read = allwinner_h3_ccu_read,
339
+ .write = allwinner_h3_ccu_write,
340
+ .endianness = DEVICE_NATIVE_ENDIAN,
341
+ .valid = {
342
+ .min_access_size = 4,
343
+ .max_access_size = 4,
344
+ },
345
+ .impl.min_access_size = 4,
346
+};
347
+
348
+static void allwinner_h3_ccu_reset(DeviceState *dev)
349
+{
350
+ AwH3ClockCtlState *s = AW_H3_CCU(dev);
351
+
352
+ /* Set default values for registers */
353
+ s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
354
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
355
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
356
+ s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
357
+ s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
358
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
359
+ s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
360
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
361
+ s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
362
+ s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
363
+ s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
364
+ s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
365
+ s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
366
+ s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
367
+ s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
368
+ s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
369
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
370
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
371
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
372
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
373
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
374
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
375
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
376
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
377
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
378
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
379
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
380
+}
381
+
382
+static void allwinner_h3_ccu_init(Object *obj)
383
+{
384
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
385
+ AwH3ClockCtlState *s = AW_H3_CCU(obj);
386
+
387
+ /* Memory mapping */
388
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
389
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
390
+ sysbus_init_mmio(sbd, &s->iomem);
391
+}
392
+
393
+static const VMStateDescription allwinner_h3_ccu_vmstate = {
394
+ .name = "allwinner-h3-ccu",
395
+ .version_id = 1,
396
+ .minimum_version_id = 1,
397
+ .fields = (VMStateField[]) {
398
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
399
+ VMSTATE_END_OF_LIST()
400
+ }
401
+};
402
+
403
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
404
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
407
+ dc->reset = allwinner_h3_ccu_reset;
408
+ dc->vmsd = &allwinner_h3_ccu_vmstate;
409
+}
410
+
411
+static const TypeInfo allwinner_h3_ccu_info = {
412
+ .name = TYPE_AW_H3_CCU,
413
+ .parent = TYPE_SYS_BUS_DEVICE,
414
+ .instance_init = allwinner_h3_ccu_init,
415
+ .instance_size = sizeof(AwH3ClockCtlState),
416
+ .class_init = allwinner_h3_ccu_class_init,
417
+};
418
+
419
+static void allwinner_h3_ccu_register(void)
420
+{
421
+ type_register_static(&allwinner_h3_ccu_info);
422
+}
423
+
424
+type_init(allwinner_h3_ccu_register)
425
--
297
--
426
2.20.1
298
2.20.1
427
299
428
300
diff view generated by jsdifflib