1
arm queue; dunno if this will be the last before softfreeze
1
Nothing earth-shaking in here, just a lot of refactoring and cleanup
2
or not, but anyway probably the last large one. New orangepi-pc
2
and a few bugfixes. I suspect I'll have another pullreq to come in
3
board model is the big item here.
3
the early part of next week...
4
4
5
thanks
5
The following changes since commit 19591e9e0938ea5066984553c256a043bd5d822f:
6
-- PMM
7
6
8
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
7
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-08-27 16:59:02 +0100)
9
10
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
11
8
12
are available in the Git repository at:
9
are available in the Git repository at:
13
10
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200828
15
12
16
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
13
for you to fetch changes up to ed78849d9711805bda37ee026018d6ee7a606d0e:
17
14
18
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
15
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd (2020-08-28 10:02:50 +0100)
19
16
20
----------------------------------------------------------------
17
----------------------------------------------------------------
21
target-arm queue:
18
target-arm queue:
22
* Fix various bugs that might result in an assert() due to
19
* target/arm: Cleanup and refactoring preparatory to SVE2
23
incorrect hflags for M-profile CPUs
20
* armsse: Define ARMSSEClass correctly
24
* Fix Aspeed SMC Controller user-mode select handling
21
* hw/misc/unimp: Improve information provided in log messages
25
* Report correct (with-tag) address in fault address register
22
* hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
26
when TBI is enabled
23
* hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
27
* cubieboard: make sure SOC object isn't leaked
24
* hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
28
* fsl-imx25: Wire up eSDHC controllers
25
* hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
29
* fsl-imx25: Wire up USB controllers
26
* target/arm: Fill in the WnR syndrome bit in mte_check_fail
30
* New board model: orangepi-pc (OrangePi PC)
27
* target/arm: Clarify HCR_EL2 ARMCPRegInfo type
31
* ARM/KVM: if user doesn't select GIC version and the
28
* hw/arm/musicpal: Use AddressSpace for DMA transfers
32
host kernel can only provide GICv3, use that, rather
29
* hw/clock: Minor cleanups
33
than defaulting to "fail because GICv2 isn't possible"
30
* hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
34
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
35
31
36
----------------------------------------------------------------
32
----------------------------------------------------------------
37
Beata Michalska (1):
33
Eduardo Habkost (1):
38
target/arm: kvm: Inject events at the last stage of sync
34
armsse: Define ARMSSEClass correctly
39
35
40
Cédric Le Goater (2):
36
Graeme Gregory (1):
41
aspeed/smc: Add some tracing
37
hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
42
aspeed/smc: Fix User mode select/unselect scheme
43
38
44
Eric Auger (6):
39
Philippe Mathieu-Daudé (14):
45
hw/arm/virt: Document 'max' value in gic-version property description
40
hw/clock: Remove unused clock_init*() functions
46
hw/arm/virt: Introduce VirtGICType enum type
41
hw/clock: Let clock_set() return boolean value
47
hw/arm/virt: Introduce finalize_gic_version()
42
hw/clock: Only propagate clock changes if the clock is changed
48
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
43
hw/arm/musicpal: Use AddressSpace for DMA transfers
49
hw/arm/virt: kvm: Restructure finalize_gic_version()
44
target/arm: Clarify HCR_EL2 ARMCPRegInfo type
50
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
45
hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
46
hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
47
hw/arm/xilinx_zynq: Uninline cadence_uart_create()
48
hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
49
hw/qdev-clock: Uninline qdev_connect_clock_in()
50
hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
51
hw/misc/unimp: Display value after offset
52
hw/misc/unimp: Display the value with width of the access size
53
hw/misc/unimp: Display the offset with width of the region size
51
54
52
Guenter Roeck (2):
55
Richard Henderson (19):
53
hw/arm/fsl-imx25: Wire up eSDHC controllers
56
target/arm: Pass the entire mte descriptor to mte_check_fail
54
hw/arm/fsl-imx25: Wire up USB controllers
57
target/arm: Fill in the WnR syndrome bit in mte_check_fail
58
qemu/int128: Add int128_lshift
59
target/arm: Split out gen_gvec_fn_zz
60
target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
61
target/arm: Rearrange {sve,fp}_check_access assert
62
target/arm: Merge do_vector2_p into do_mov_p
63
target/arm: Clean up 4-operand predicate expansion
64
target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
65
target/arm: Split out gen_gvec_ool_zzzp
66
target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
67
target/arm: Split out gen_gvec_ool_zzp
68
target/arm: Split out gen_gvec_ool_zzz
69
target/arm: Split out gen_gvec_ool_zz
70
target/arm: Tidy SVE tszimm shift formats
71
target/arm: Generalize inl_qrdmlah_* helper functions
72
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
73
target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
74
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
55
75
56
Igor Mammedov (1):
76
include/hw/arm/armsse.h | 2 +-
57
hw/arm/cubieboard: make sure SOC object isn't leaked
77
include/hw/char/cadence_uart.h | 17 --
78
include/hw/clock.h | 30 +--
79
include/hw/misc/unimp.h | 1 +
80
include/hw/net/allwinner-sun8i-emac.h | 6 +
81
include/hw/qdev-clock.h | 8 +-
82
include/hw/sd/allwinner-sdhost.h | 6 +
83
include/qemu/int128.h | 16 ++
84
target/arm/helper-sve.h | 5 -
85
target/arm/helper.h | 28 +++
86
target/arm/translate.h | 1 +
87
target/arm/sve.decode | 35 ++-
88
hw/arm/allwinner-a10.c | 2 +
89
hw/arm/allwinner-h3.c | 4 +
90
hw/arm/armsse.c | 1 +
91
hw/arm/musicpal.c | 45 ++--
92
hw/arm/sbsa-ref.c | 2 +-
93
hw/arm/xilinx_zynq.c | 24 +-
94
hw/core/clock.c | 7 +-
95
hw/core/qdev-clock.c | 6 +
96
hw/misc/unimp.c | 14 +-
97
hw/net/allwinner-sun8i-emac.c | 46 ++--
98
hw/sd/allwinner-sdhost.c | 37 +++-
99
target/arm/helper.c | 1 -
100
target/arm/mte_helper.c | 19 +-
101
target/arm/sve_helper.c | 70 ++----
102
target/arm/translate-a64.c | 110 ++++++++--
103
target/arm/translate-sve.c | 399 ++++++++++++++--------------------
104
target/arm/vec_helper.c | 182 +++++++++++-----
105
29 files changed, 629 insertions(+), 495 deletions(-)
58
106
59
Niek Linnenbank (13):
60
hw/arm: add Allwinner H3 System-on-Chip
61
hw/arm: add Xunlong Orange Pi PC machine
62
hw/arm/allwinner-h3: add Clock Control Unit
63
hw/arm/allwinner-h3: add USB host controller
64
hw/arm/allwinner-h3: add System Control module
65
hw/arm/allwinner: add CPU Configuration module
66
hw/arm/allwinner: add Security Identifier device
67
hw/arm/allwinner: add SD/MMC host controller
68
hw/arm/allwinner-h3: add EMAC ethernet device
69
hw/arm/allwinner-h3: add Boot ROM support
70
hw/arm/allwinner-h3: add SDRAM controller device
71
hw/arm/allwinner: add RTC device support
72
docs: add Orange Pi PC document
73
74
Peter Maydell (4):
75
hw/intc/armv7m_nvic: Rebuild hflags on reset
76
target/arm: Update hflags in trans_CPS_v7m()
77
target/arm: Recalculate hflags correctly after writes to CONTROL
78
target/arm: Fix some comment typos
79
80
Philippe Mathieu-Daudé (5):
81
tests/boot_linux_console: Add a quick test for the OrangePi PC board
82
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
83
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
84
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
85
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
86
87
Richard Henderson (2):
88
target/arm: Check addresses for disabled regimes
89
target/arm: Disable clean_data_tbi for system mode
90
91
Makefile.objs | 1 +
92
hw/arm/Makefile.objs | 1 +
93
hw/misc/Makefile.objs | 5 +
94
hw/net/Makefile.objs | 1 +
95
hw/rtc/Makefile.objs | 1 +
96
hw/sd/Makefile.objs | 1 +
97
hw/usb/hcd-ehci.h | 1 +
98
include/hw/arm/allwinner-a10.h | 4 +
99
include/hw/arm/allwinner-h3.h | 161 ++++++
100
include/hw/arm/fsl-imx25.h | 18 +
101
include/hw/arm/virt.h | 12 +-
102
include/hw/misc/allwinner-cpucfg.h | 52 ++
103
include/hw/misc/allwinner-h3-ccu.h | 66 +++
104
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
105
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
106
include/hw/misc/allwinner-sid.h | 60 +++
107
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
108
include/hw/rtc/allwinner-rtc.h | 134 +++++
109
include/hw/sd/allwinner-sdhost.h | 135 +++++
110
target/arm/helper.h | 1 +
111
target/arm/kvm_arm.h | 3 +
112
hw/arm/allwinner-a10.c | 19 +
113
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
114
hw/arm/cubieboard.c | 18 +
115
hw/arm/fsl-imx25.c | 56 +++
116
hw/arm/imx25_pdk.c | 16 +
117
hw/arm/orangepi.c | 130 +++++
118
hw/arm/virt.c | 145 ++++--
119
hw/intc/armv7m_nvic.c | 6 +
120
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
121
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
122
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
123
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
124
hw/misc/allwinner-sid.c | 168 +++++++
125
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
126
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
127
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
128
hw/ssi/aspeed_smc.c | 56 ++-
129
hw/usb/hcd-ehci-sysbus.c | 17 +
130
target/arm/helper.c | 49 +-
131
target/arm/kvm.c | 14 +-
132
target/arm/kvm32.c | 15 +-
133
target/arm/kvm64.c | 15 +-
134
target/arm/translate-a64.c | 11 +
135
target/arm/translate.c | 14 +-
136
MAINTAINERS | 9 +
137
default-configs/arm-softmmu.mak | 1 +
138
docs/system/arm/orangepi.rst | 253 ++++++++++
139
docs/system/target-arm.rst | 2 +
140
hw/arm/Kconfig | 12 +
141
hw/misc/trace-events | 19 +
142
hw/net/Kconfig | 3 +
143
hw/net/trace-events | 10 +
144
hw/rtc/trace-events | 4 +
145
hw/sd/trace-events | 7 +
146
hw/ssi/trace-events | 10 +
147
tests/acceptance/boot_linux_console.py | 230 +++++++++
148
57 files changed, 5787 insertions(+), 74 deletions(-)
149
create mode 100644 include/hw/arm/allwinner-h3.h
150
create mode 100644 include/hw/misc/allwinner-cpucfg.h
151
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
152
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
153
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
154
create mode 100644 include/hw/misc/allwinner-sid.h
155
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
156
create mode 100644 include/hw/rtc/allwinner-rtc.h
157
create mode 100644 include/hw/sd/allwinner-sdhost.h
158
create mode 100644 hw/arm/allwinner-h3.c
159
create mode 100644 hw/arm/orangepi.c
160
create mode 100644 hw/misc/allwinner-cpucfg.c
161
create mode 100644 hw/misc/allwinner-h3-ccu.c
162
create mode 100644 hw/misc/allwinner-h3-dramc.c
163
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
164
create mode 100644 hw/misc/allwinner-sid.c
165
create mode 100644 hw/net/allwinner-sun8i-emac.c
166
create mode 100644 hw/rtc/allwinner-rtc.c
167
create mode 100644 hw/sd/allwinner-sdhost.c
168
create mode 100644 docs/system/arm/orangepi.rst
169
create mode 100644 hw/ssi/trace-events
170
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Graeme Gregory <graeme@nuviainc.com>
2
2
3
We plan to introduce yet another value for the gic version (nosel).
3
Fixing a typo in a previous patch that translated an "i" to a 1
4
As we already use exotic values such as 0 and -1, let's introduce
4
and therefore breaking the allocation of PCIe interrupts. This was
5
a dedicated enum type and let vms->gic_version take this
5
discovered when virtio-net-pci devices ceased to function correctly.
6
type.
7
6
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20200311131618.7187-3-eric.auger@redhat.com
11
Message-id: 20200821083853.356490-1-graeme@nuviainc.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
include/hw/arm/virt.h | 11 +++++++++--
14
hw/arm/sbsa-ref.c | 2 +-
16
hw/arm/virt.c | 30 +++++++++++++++---------------
15
1 file changed, 1 insertion(+), 1 deletion(-)
17
2 files changed, 24 insertions(+), 17 deletions(-)
18
16
19
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/virt.h
19
--- a/hw/arm/sbsa-ref.c
22
+++ b/include/hw/arm/virt.h
20
+++ b/hw/arm/sbsa-ref.c
23
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
21
@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)
24
VIRT_IOMMU_VIRTIO,
22
25
} VirtIOMMUType;
23
for (i = 0; i < GPEX_NUM_IRQS; i++) {
26
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
27
+typedef enum VirtGICType {
25
- qdev_get_gpio_in(sms->gic, irq + 1));
28
+ VIRT_GIC_VERSION_MAX,
26
+ qdev_get_gpio_in(sms->gic, irq + i));
29
+ VIRT_GIC_VERSION_HOST,
27
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
30
+ VIRT_GIC_VERSION_2,
31
+ VIRT_GIC_VERSION_3,
32
+} VirtGICType;
33
+
34
typedef struct MemMapEntry {
35
hwaddr base;
36
hwaddr size;
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
bool highmem_ecam;
39
bool its;
40
bool virt;
41
- int32_t gic_version;
42
+ VirtGICType gic_version;
43
VirtIOMMUType iommu;
44
uint16_t virtio_iommu_bdf;
45
struct arm_boot_info bootinfo;
46
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
47
uint32_t redist0_capacity =
48
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
49
50
- assert(vms->gic_version == 3);
51
+ assert(vms->gic_version == VIRT_GIC_VERSION_3);
52
53
return vms->smp_cpus > redist0_capacity ? 2 : 1;
54
}
55
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/virt.c
58
+++ b/hw/arm/virt.c
59
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
60
irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
61
}
28
}
62
29
63
- if (vms->gic_version == 2) {
64
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
65
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
66
GIC_FDT_IRQ_PPI_CPU_WIDTH,
67
(1 << vms->smp_cpus) - 1);
68
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
70
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
71
qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
72
- if (vms->gic_version == 3) {
73
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
74
int nb_redist_regions = virt_gicv3_redist_region_count(vms);
75
76
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
77
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
78
}
79
}
80
81
- if (vms->gic_version == 2) {
82
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
83
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
84
GIC_FDT_IRQ_PPI_CPU_WIDTH,
85
(1 << vms->smp_cpus) - 1);
86
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
87
* purposes are to make TCG consistent (with 64-bit KVM hosts)
88
* and to improve SGI efficiency.
89
*/
90
- if (vms->gic_version == 3) {
91
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
92
clustersz = GICV3_TARGETLIST_BITS;
93
} else {
94
clustersz = GIC_TARGETLIST_BITS;
95
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
96
/* We can probe only here because during property set
97
* KVM is not available yet
98
*/
99
- if (vms->gic_version <= 0) {
100
- /* "host" or "max" */
101
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
102
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
103
if (!kvm_enabled()) {
104
- if (vms->gic_version == 0) {
105
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
106
error_report("gic-version=host requires KVM");
107
exit(1);
108
} else {
109
/* "max": currently means 3 for TCG */
110
- vms->gic_version = 3;
111
+ vms->gic_version = VIRT_GIC_VERSION_3;
112
}
113
} else {
114
vms->gic_version = kvm_arm_vgic_probe();
115
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
116
/* The maximum number of CPUs depends on the GIC version, or on how
117
* many redistributors we can fit into the memory map.
118
*/
119
- if (vms->gic_version == 3) {
120
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
121
virt_max_cpus =
122
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
123
virt_max_cpus +=
124
@@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp)
125
static char *virt_get_gic_version(Object *obj, Error **errp)
126
{
127
VirtMachineState *vms = VIRT_MACHINE(obj);
128
- const char *val = vms->gic_version == 3 ? "3" : "2";
129
+ const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
130
131
return g_strdup(val);
132
}
133
@@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
134
VirtMachineState *vms = VIRT_MACHINE(obj);
135
136
if (!strcmp(value, "3")) {
137
- vms->gic_version = 3;
138
+ vms->gic_version = VIRT_GIC_VERSION_3;
139
} else if (!strcmp(value, "2")) {
140
- vms->gic_version = 2;
141
+ vms->gic_version = VIRT_GIC_VERSION_2;
142
} else if (!strcmp(value, "host")) {
143
- vms->gic_version = 0; /* Will probe later */
144
+ vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
145
} else if (!strcmp(value, "max")) {
146
- vms->gic_version = -1; /* Will probe later */
147
+ vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
148
} else {
149
error_setg(errp, "Invalid gic-version value");
150
error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
151
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
152
"physical address space above 32 bits",
153
NULL);
154
/* Default GIC type is v2 */
155
- vms->gic_version = 2;
156
+ vms->gic_version = VIRT_GIC_VERSION_2;
157
object_property_add_str(obj, "gic-version", virt_get_gic_version,
158
virt_set_gic_version, NULL);
159
object_property_set_description(obj, "gic-version",
160
--
30
--
161
2.20.1
31
2.20.1
162
32
163
33
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots Ubuntu Bionic on a OrangePi PC board.
3
clock_init*() inlined funtions are simple wrappers around
4
4
clock_set*() and are not used. Remove them in favor of clock_set*().
5
As it requires 1GB of storage, and is slow, this test is disabled
6
on automatic CI testing.
7
8
It is useful for workstation testing. Currently Avocado timeouts too
9
quickly, so we can't run userland commands.
10
11
The kernel image and DeviceTree blob are built by the Armbian
12
project (based on Debian):
13
https://www.armbian.com/orange-pi-pc/
14
15
The Ubuntu image is downloaded from:
16
https://dl.armbian.com/orangepipc/Bionic_current
17
18
This test can be run using:
19
20
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
21
avocado --show=app,console run -t machine:orangepi-pc \
22
tests/acceptance/boot_linux_console.py
23
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
24
console: DRAM: 1024 MiB
25
console: Failed to set core voltage! Can't set CPU frequency
26
console: Trying to boot from MMC1
27
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
28
console: CPU: Allwinner H3 (SUN8I 0000)
29
console: Model: Xunlong Orange Pi PC
30
console: DRAM: 1 GiB
31
console: MMC: mmc@1c0f000: 0
32
[...]
33
console: Uncompressing Linux... done, booting the kernel.
34
console: Booting Linux on physical CPU 0x0
35
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
36
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
37
console: CPU: div instructions available: patching division code
38
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
39
console: OF: fdt: Machine model: Xunlong Orange Pi PC
40
[...]
41
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
42
console: done.
43
console: Begin: Running /scripts/local-bottom ... done.
44
console: Begin: Running /scripts/init-bottom ... done.
45
console: systemd[1]: systemd 237 running in system mode. (...)
46
console: systemd[1]: Detected architecture arm.
47
console: Welcome to Ubuntu 18.04.3 LTS!
48
console: systemd[1]: Set hostname to <orangepipc>.
49
5
50
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
51
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
52
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200806123858.30058-2-f4bug@amsat.org
53
Tested-by: Alex Bennée <alex.bennee@linaro.org>
54
Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com
55
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
56
[NL: changed test to boot from SD card via BootROM, added check for 7z]
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
58
---
10
---
59
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
11
include/hw/clock.h | 13 -------------
60
1 file changed, 48 insertions(+)
12
1 file changed, 13 deletions(-)
61
13
62
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
14
diff --git a/include/hw/clock.h b/include/hw/clock.h
63
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
64
--- a/tests/acceptance/boot_linux_console.py
16
--- a/include/hw/clock.h
65
+++ b/tests/acceptance/boot_linux_console.py
17
+++ b/include/hw/clock.h
66
@@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern
18
@@ -XXX,XX +XXX,XX @@ static inline bool clock_is_enabled(const Clock *clk)
67
from avocado_qemu import wait_for_console_pattern
19
return clock_get(clk) != 0;
68
from avocado.utils import process
20
}
69
from avocado.utils import archive
21
70
+from avocado.utils.path import find_command, CmdNotFoundError
22
-static inline void clock_init(Clock *clk, uint64_t value)
71
23
-{
72
+P7ZIP_AVAILABLE = True
24
- clock_set(clk, value);
73
+try:
25
-}
74
+ find_command('7z')
26
-static inline void clock_init_hz(Clock *clk, uint64_t value)
75
+except CmdNotFoundError:
27
-{
76
+ P7ZIP_AVAILABLE = False
28
- clock_set_hz(clk, value);
77
29
-}
78
class BootLinuxConsole(Test):
30
-static inline void clock_init_ns(Clock *clk, uint64_t value)
79
"""
31
-{
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
32
- clock_set_ns(clk, value);
81
exec_command_and_wait_for_pattern(self, 'reboot',
33
-}
82
'reboot: Restarting system')
34
-
83
35
#endif /* QEMU_HW_CLOCK_H */
84
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
85
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
86
+ def test_arm_orangepi_bionic(self):
87
+ """
88
+ :avocado: tags=arch:arm
89
+ :avocado: tags=machine:orangepi-pc
90
+ """
91
+
92
+ # This test download a 196MB compressed image and expand it to 932MB...
93
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
94
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
95
+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
96
+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
97
+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
98
+ image_path = os.path.join(self.workdir, image_name)
99
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
100
+
101
+ self.vm.set_console()
102
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
103
+ '-nic', 'user',
104
+ '-no-reboot')
105
+ self.vm.launch()
106
+
107
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
108
+ 'console=ttyS0,115200 '
109
+ 'loglevel=7 '
110
+ 'nosmp '
111
+ 'systemd.default_timeout_start_sec=9000 '
112
+ 'systemd.mask=armbian-zram-config.service '
113
+ 'systemd.mask=armbian-ramlog.service')
114
+
115
+ self.wait_for_console_pattern('U-Boot SPL')
116
+ self.wait_for_console_pattern('Autoboot in ')
117
+ exec_command_and_wait_for_pattern(self, ' ', '=>')
118
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
119
+ kernel_command_line + "'", '=>')
120
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
121
+
122
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
123
+ 'to <orangepipc>')
124
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
125
+
126
def test_s390x_s390_ccw_virtio(self):
127
"""
128
:avocado: tags=arch:s390x
129
--
36
--
130
2.20.1
37
2.20.1
131
38
132
39
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots U-Boot then NetBSD (stored on a SD card) on
3
Let clock_set() return a boolean value whether the clock
4
a OrangePi PC board.
4
has been updated or not.
5
6
As it requires ~1.3GB of storage, it is disabled by default.
7
8
U-Boot is built by the Debian project [1], and the SD card image
9
is provided by the NetBSD organization [2].
10
11
Once the compressed SD card image is downloaded (304MB) and
12
extracted, this test is fast:
13
14
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
15
avocado --show=app,console run -t machine:orangepi-pc \
16
tests/acceptance/boot_linux_console.py
17
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
18
console: DRAM: 1024 MiB
19
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
20
console: CPU: Allwinner H3 (SUN8I 0000)
21
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
22
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
23
console: scanning usb for storage devices... 0 Storage Device(s) found
24
console: Hit any key to stop autoboot: 0
25
console: => setenv bootargs root=ld0a
26
console: => setenv kernel netbsd-GENERIC.ub
27
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
28
console: => boot
29
console: ## Booting kernel from Legacy Image at 42000000 ...
30
console: Image Name: NetBSD/earmv7hf 9.0_RC1
31
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
32
console: XIP Kernel Image (no loading done)
33
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
34
console: Starting kernel ...
35
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
36
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
37
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
38
console: [ 1.0000000] total memory = 1024 MB
39
console: [ 1.0000000] avail memory = 1003 MB
40
console: [ 1.0000000] armfdt0 (root)
41
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
42
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
43
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
44
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
45
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
46
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
47
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
48
...
49
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
50
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
51
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors
52
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
53
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log.
54
console: [ 3.1179868] boot device: ld0
55
console: [ 3.1470623] root on ld0a dumps on ld0b
56
console: [ 3.2464436] root file system type: ffs
57
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
58
console: Mon Feb 17 20:33:35 UTC 2020
59
console: Starting root file system check:
60
PASS (35.96 s)
61
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
62
JOB TIME : 36.09 s
63
64
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
65
66
This test is based on a description from Niek Linnenbank from [4].
67
68
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
69
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
70
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
71
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
72
5
73
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
74
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
75
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200806123858.30058-3-f4bug@amsat.org
76
Tested-by: Alex Bennée <alex.bennee@linaro.org>
77
Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com
78
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
---
10
---
81
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
11
include/hw/clock.h | 12 +++++++-----
82
1 file changed, 70 insertions(+)
12
hw/core/clock.c | 7 ++++++-
13
2 files changed, 13 insertions(+), 6 deletions(-)
83
14
84
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
15
diff --git a/include/hw/clock.h b/include/hw/clock.h
85
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/acceptance/boot_linux_console.py
17
--- a/include/hw/clock.h
87
+++ b/tests/acceptance/boot_linux_console.py
18
+++ b/include/hw/clock.h
88
@@ -XXX,XX +XXX,XX @@ import shutil
19
@@ -XXX,XX +XXX,XX @@ void clock_set_source(Clock *clk, Clock *src);
89
from avocado import skipUnless
20
* @value: the clock's value, 0 means unclocked
90
from avocado_qemu import Test
21
*
91
from avocado_qemu import exec_command_and_wait_for_pattern
22
* Set the local cached period value of @clk to @value.
92
+from avocado_qemu import interrupt_interactive_console_until_pattern
23
+ *
93
from avocado_qemu import wait_for_console_pattern
24
+ * @return: true if the clock is changed.
94
from avocado.utils import process
25
*/
95
from avocado.utils import archive
26
-void clock_set(Clock *clk, uint64_t value);
96
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
27
+bool clock_set(Clock *clk, uint64_t value);
97
'to <orangepipc>')
28
98
self.wait_for_console_pattern('Starting Load Kernel Modules...')
29
-static inline void clock_set_hz(Clock *clk, unsigned hz)
99
30
+static inline bool clock_set_hz(Clock *clk, unsigned hz)
100
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
31
{
101
+ def test_arm_orangepi_uboot_netbsd9(self):
32
- clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
102
+ """
33
+ return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
103
+ :avocado: tags=arch:arm
34
}
104
+ :avocado: tags=machine:orangepi-pc
35
105
+ """
36
-static inline void clock_set_ns(Clock *clk, unsigned ns)
106
+ # This test download a 304MB compressed image and expand it to 1.3GB...
37
+static inline bool clock_set_ns(Clock *clk, unsigned ns)
107
+ deb_url = ('http://snapshot.debian.org/archive/debian/'
38
{
108
+ '20200108T145233Z/pool/main/u/u-boot/'
39
- clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
109
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
40
+ return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
110
+ deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99'
41
}
111
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
42
112
+ # We use the common OrangePi PC 'plus' build of U-Boot for our secondary
43
/**
113
+ # program loader (SPL). We will then set the path to the more specific
44
diff --git a/hw/core/clock.c b/hw/core/clock.c
114
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt,
45
index XXXXXXX..XXXXXXX 100644
115
+ # before to boot NetBSD.
46
--- a/hw/core/clock.c
116
+ uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin'
47
+++ b/hw/core/clock.c
117
+ uboot_path = self.extract_from_deb(deb_path, uboot_path)
48
@@ -XXX,XX +XXX,XX @@ void clock_clear_callback(Clock *clk)
118
+ image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
49
clock_set_callback(clk, NULL, NULL);
119
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
50
}
120
+ image_hash = '2babb29d36d8360adcb39c09e31060945259917a'
51
121
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
52
-void clock_set(Clock *clk, uint64_t period)
122
+ image_path = os.path.join(self.workdir, 'armv7.img')
53
+bool clock_set(Clock *clk, uint64_t period)
123
+ image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path
54
{
124
+ archive.gzip_uncompress(image_path_gz, image_path)
55
+ if (clk->period == period) {
56
+ return false;
57
+ }
58
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
59
CLOCK_PERIOD_TO_NS(period));
60
clk->period = period;
125
+
61
+
126
+ # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc
62
+ return true;
127
+ with open(uboot_path, 'rb') as f_in:
63
}
128
+ with open(image_path, 'r+b') as f_out:
64
129
+ f_out.seek(8 * 1024)
65
static void clock_propagate_period(Clock *clk, bool call_callbacks)
130
+ shutil.copyfileobj(f_in, f_out)
131
+
132
+ # Extend image, to avoid that NetBSD thinks the partition
133
+ # inside the image is larger than device size itself
134
+ f_out.seek(0, 2)
135
+ f_out.seek(64 * 1024 * 1024, 1)
136
+ f_out.write(bytearray([0x00]))
137
+
138
+ self.vm.set_console()
139
+ self.vm.add_args('-nic', 'user',
140
+ '-drive', image_drive_args,
141
+ '-global', 'allwinner-rtc.base-year=2000',
142
+ '-no-reboot')
143
+ self.vm.launch()
144
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
145
+ interrupt_interactive_console_until_pattern(self,
146
+ 'Hit any key to stop autoboot:',
147
+ 'switch to partitions #0, OK')
148
+
149
+ exec_command_and_wait_for_pattern(self, '', '=>')
150
+ cmd = 'setenv bootargs root=ld0a'
151
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
152
+ cmd = 'setenv kernel netbsd-GENERIC.ub'
153
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
154
+ cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
155
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
156
+ cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; "
157
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
158
+ "fdt addr ${fdt_addr_r}; "
159
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
160
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
161
+
162
+ exec_command_and_wait_for_pattern(self, 'boot',
163
+ 'Booting kernel from Legacy Image')
164
+ wait_for_console_pattern(self, 'Starting kernel ...')
165
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
166
+ # Wait for user-space
167
+ wait_for_console_pattern(self, 'Starting root file system check')
168
+
169
def test_s390x_s390_ccw_virtio(self):
170
"""
171
:avocado: tags=arch:s390x
172
--
66
--
173
2.20.1
67
2.20.1
174
68
175
69
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
3
Avoid propagating the clock change when the clock does not change.
4
provided on the command line to available eSDHC controllers.
5
4
6
This patch enables booting the imx25-pdk emulation from SD card.
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
Message-id: 20200806123858.30058-4-f4bug@amsat.org
9
Message-id: 20200310215146.19688-2-linux@roeck-us.net
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: made commit subject consistent with other patch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
include/hw/arm/fsl-imx25.h | 9 +++++++++
10
include/hw/clock.h | 5 +++--
15
hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++
11
1 file changed, 3 insertions(+), 2 deletions(-)
16
hw/arm/imx25_pdk.c | 16 ++++++++++++++++
17
3 files changed, 57 insertions(+)
18
12
19
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
13
diff --git a/include/hw/clock.h b/include/hw/clock.h
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/fsl-imx25.h
15
--- a/include/hw/clock.h
22
+++ b/include/hw/arm/fsl-imx25.h
16
+++ b/include/hw/clock.h
23
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ void clock_propagate(Clock *clk);
24
#include "hw/misc/imx_rngc.h"
18
*/
25
#include "hw/i2c/imx_i2c.h"
19
static inline void clock_update(Clock *clk, uint64_t value)
26
#include "hw/gpio/imx_gpio.h"
27
+#include "hw/sd/sdhci.h"
28
#include "exec/memory.h"
29
#include "target/arm/cpu.h"
30
31
@@ -XXX,XX +XXX,XX @@
32
#define FSL_IMX25_NUM_EPITS 2
33
#define FSL_IMX25_NUM_I2CS 3
34
#define FSL_IMX25_NUM_GPIOS 4
35
+#define FSL_IMX25_NUM_ESDHCS 2
36
37
typedef struct FslIMX25State {
38
/*< private >*/
39
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
40
IMXRNGCState rngc;
41
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
42
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
43
+ SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
44
MemoryRegion rom[2];
45
MemoryRegion iram;
46
MemoryRegion iram_alias;
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
#define FSL_IMX25_GPIO3_SIZE 0x4000
49
#define FSL_IMX25_RNGC_ADDR 0x53FB0000
50
#define FSL_IMX25_RNGC_SIZE 0x4000
51
+#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
52
+#define FSL_IMX25_ESDHC1_SIZE 0x4000
53
+#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
54
+#define FSL_IMX25_ESDHC2_SIZE 0x4000
55
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
56
#define FSL_IMX25_GPIO1_SIZE 0x4000
57
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
58
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
59
#define FSL_IMX25_GPIO2_IRQ 51
60
#define FSL_IMX25_GPIO3_IRQ 16
61
#define FSL_IMX25_GPIO4_IRQ 23
62
+#define FSL_IMX25_ESDHC1_IRQ 9
63
+#define FSL_IMX25_ESDHC2_IRQ 8
64
65
#endif /* FSL_IMX25_H */
66
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/fsl-imx25.c
69
+++ b/hw/arm/fsl-imx25.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "hw/qdev-properties.h"
72
#include "chardev/char.h"
73
74
+#define IMX25_ESDHC_CAPABILITIES 0x07e20000
75
+
76
static void fsl_imx25_init(Object *obj)
77
{
20
{
78
FslIMX25State *s = FSL_IMX25(obj);
21
- clock_set(clk, value);
79
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
22
- clock_propagate(clk);
80
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
23
+ if (clock_set(clk, value)) {
81
TYPE_IMX_GPIO);
24
+ clock_propagate(clk);
82
}
83
+
84
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
85
+ sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
86
+ TYPE_IMX_USDHC);
87
+ }
25
+ }
88
}
26
}
89
27
90
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
28
static inline void clock_update_hz(Clock *clk, unsigned hz)
91
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
92
gpio_table[i].irq));
93
}
94
95
+ /* Initialize all SDHC */
96
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
97
+ static const struct {
98
+ hwaddr addr;
99
+ unsigned int irq;
100
+ } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
101
+ { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
102
+ { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
103
+ };
104
+
105
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
106
+ &err);
107
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
108
+ "capareg", &err);
109
+ object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
110
+ if (err) {
111
+ error_propagate(errp, err);
112
+ return;
113
+ }
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->avic),
117
+ esdhc_table[i].irq));
118
+ }
119
+
120
/* initialize 2 x 16 KB ROM */
121
memory_region_init_rom(&s->rom[0], NULL,
122
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
123
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/imx25_pdk.c
126
+++ b/hw/arm/imx25_pdk.c
127
@@ -XXX,XX +XXX,XX @@
128
#include "qemu/osdep.h"
129
#include "qapi/error.h"
130
#include "cpu.h"
131
+#include "hw/qdev-properties.h"
132
#include "hw/arm/fsl-imx25.h"
133
#include "hw/boards.h"
134
#include "qemu/error-report.h"
135
@@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine)
136
imx25_pdk_binfo.board_id = 1771,
137
imx25_pdk_binfo.nb_cpus = 1;
138
139
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
140
+ BusState *bus;
141
+ DeviceState *carddev;
142
+ DriveInfo *di;
143
+ BlockBackend *blk;
144
+
145
+ di = drive_get_next(IF_SD);
146
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
147
+ bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
148
+ carddev = qdev_create(bus, TYPE_SD_CARD);
149
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
150
+ object_property_set_bool(OBJECT(carddev), true,
151
+ "realized", &error_fatal);
152
+ }
153
+
154
/*
155
* We test explicitly for qtest here as it is not done (yet?) in
156
* arm_load_kernel(). Without this the "make check" command would
157
--
29
--
158
2.20.1
30
2.20.1
159
31
160
32
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
3
Allow the device to execute the DMA transfers in a different
4
for non-volatile system date and time keeping. This commit adds a generic
4
AddressSpace.
5
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
6
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
7
The following RTC functionality and features are implemented:
8
5
9
* Year-Month-Day read/write
6
We keep using the system_memory address space, but via the
10
* Hour-Minute-Second read/write
7
proper dma_memory_access() API.
11
* General Purpose storage
12
8
13
The following boards are extended with the RTC device:
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
* Cubieboard (hw/arm/cubieboard.c)
11
Message-id: 20200814125533.4047-1-f4bug@amsat.org
16
* Orange Pi PC (hw/arm/orangepi.c)
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
13
---
23
hw/rtc/Makefile.objs | 1 +
14
hw/arm/musicpal.c | 45 +++++++++++++++++++++++++++++++--------------
24
include/hw/arm/allwinner-a10.h | 2 +
15
1 file changed, 31 insertions(+), 14 deletions(-)
25
include/hw/arm/allwinner-h3.h | 3 +
26
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
27
hw/arm/allwinner-a10.c | 8 +
28
hw/arm/allwinner-h3.c | 9 +-
29
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
30
hw/rtc/trace-events | 4 +
31
8 files changed, 571 insertions(+), 1 deletion(-)
32
create mode 100644 include/hw/rtc/allwinner-rtc.h
33
create mode 100644 hw/rtc/allwinner-rtc.c
34
16
35
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
36
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/rtc/Makefile.objs
19
--- a/hw/arm/musicpal.c
38
+++ b/hw/rtc/Makefile.objs
20
+++ b/hw/arm/musicpal.c
39
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
40
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
41
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o
42
common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o
43
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o
44
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/arm/allwinner-a10.h
47
+++ b/include/hw/arm/allwinner-a10.h
48
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
49
#include "hw/ide/ahci.h"
22
#include "hw/audio/wm8750.h"
50
#include "hw/usb/hcd-ohci.h"
51
#include "hw/usb/hcd-ehci.h"
52
+#include "hw/rtc/allwinner-rtc.h"
53
54
#include "target/arm/cpu.h"
55
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
57
AwEmacState emac;
58
AllwinnerAHCIState sata;
59
AwSdHostState mmc0;
60
+ AwRtcState rtc;
61
MemoryRegion sram_a;
62
EHCISysBusState ehci[AW_A10_NUM_USB];
63
OHCISysBusState ohci[AW_A10_NUM_USB];
64
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/include/hw/arm/allwinner-h3.h
67
+++ b/include/hw/arm/allwinner-h3.h
68
@@ -XXX,XX +XXX,XX @@
69
#include "hw/misc/allwinner-sid.h"
70
#include "hw/sd/allwinner-sdhost.h"
71
#include "hw/net/allwinner-sun8i-emac.h"
72
+#include "hw/rtc/allwinner-rtc.h"
73
#include "target/arm/cpu.h"
74
#include "sysemu/block-backend.h"
23
#include "sysemu/block-backend.h"
75
24
#include "sysemu/runstate.h"
76
@@ -XXX,XX +XXX,XX @@ enum {
25
+#include "sysemu/dma.h"
77
AW_H3_GIC_CPU,
26
#include "exec/address-spaces.h"
78
AW_H3_GIC_HYP,
27
#include "ui/pixel_ops.h"
79
AW_H3_GIC_VCPU,
28
#include "qemu/cutils.h"
80
+ AW_H3_RTC,
29
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
81
AW_H3_CPUCFG,
30
82
AW_H3_SDRAM
31
MemoryRegion iomem;
83
};
32
qemu_irq irq;
84
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
33
+ MemoryRegion *dma_mr;
85
AwSidState sid;
34
+ AddressSpace dma_as;
86
AwSdHostState mmc0;
35
uint32_t smir;
87
AwSun8iEmacState emac;
36
uint32_t icr;
88
+ AwRtcState rtc;
37
uint32_t imr;
89
GICState gic;
38
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
90
MemoryRegion sram_a1;
39
NICConf conf;
91
MemoryRegion sram_a2;
40
} mv88w8618_eth_state;
92
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
41
93
new file mode 100644
42
-static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
94
index XXXXXXX..XXXXXXX
43
+static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr,
95
--- /dev/null
44
+ mv88w8618_rx_desc *desc)
96
+++ b/include/hw/rtc/allwinner-rtc.h
97
@@ -XXX,XX +XXX,XX @@
98
+/*
99
+ * Allwinner Real Time Clock emulation
100
+ *
101
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
102
+ *
103
+ * This program is free software: you can redistribute it and/or modify
104
+ * it under the terms of the GNU General Public License as published by
105
+ * the Free Software Foundation, either version 2 of the License, or
106
+ * (at your option) any later version.
107
+ *
108
+ * This program is distributed in the hope that it will be useful,
109
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
110
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
111
+ * GNU General Public License for more details.
112
+ *
113
+ * You should have received a copy of the GNU General Public License
114
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
115
+ */
116
+
117
+#ifndef HW_MISC_ALLWINNER_RTC_H
118
+#define HW_MISC_ALLWINNER_RTC_H
119
+
120
+#include "qom/object.h"
121
+#include "hw/sysbus.h"
122
+
123
+/**
124
+ * Constants
125
+ * @{
126
+ */
127
+
128
+/** Highest register address used by RTC device */
129
+#define AW_RTC_REGS_MAXADDR (0x200)
130
+
131
+/** Total number of known registers */
132
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
133
+
134
+/** @} */
135
+
136
+/**
137
+ * Object model types
138
+ * @{
139
+ */
140
+
141
+/** Generic Allwinner RTC device (abstract) */
142
+#define TYPE_AW_RTC "allwinner-rtc"
143
+
144
+/** Allwinner RTC sun4i family (A10, A12) */
145
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
146
+
147
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
148
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
149
+
150
+/** Allwinner RTC sun7i family (A20) */
151
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
152
+
153
+/** @} */
154
+
155
+/**
156
+ * Object model macros
157
+ * @{
158
+ */
159
+
160
+#define AW_RTC(obj) \
161
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
162
+#define AW_RTC_CLASS(klass) \
163
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
164
+#define AW_RTC_GET_CLASS(obj) \
165
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
166
+
167
+/** @} */
168
+
169
+/**
170
+ * Allwinner RTC per-object instance state.
171
+ */
172
+typedef struct AwRtcState {
173
+ /*< private >*/
174
+ SysBusDevice parent_obj;
175
+ /*< public >*/
176
+
177
+ /**
178
+ * Actual year represented by the device when year counter is zero
179
+ *
180
+ * Can be overridden by the user using the corresponding 'base-year'
181
+ * property. The base year used by the target OS driver can vary, for
182
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
183
+ */
184
+ int base_year;
185
+
186
+ /** Maps I/O registers in physical memory */
187
+ MemoryRegion iomem;
188
+
189
+ /** Array of hardware registers */
190
+ uint32_t regs[AW_RTC_REGS_NUM];
191
+
192
+} AwRtcState;
193
+
194
+/**
195
+ * Allwinner RTC class-level struct.
196
+ *
197
+ * This struct is filled by each sunxi device specific code
198
+ * such that the generic code can use this struct to support
199
+ * all devices.
200
+ */
201
+typedef struct AwRtcClass {
202
+ /*< private >*/
203
+ SysBusDeviceClass parent_class;
204
+ /*< public >*/
205
+
206
+ /** Defines device specific register map */
207
+ const uint8_t *regmap;
208
+
209
+ /** Size of the regmap in bytes */
210
+ size_t regmap_size;
211
+
212
+ /**
213
+ * Read device specific register
214
+ *
215
+ * @offset: register offset to read
216
+ * @return true if register read successful, false otherwise
217
+ */
218
+ bool (*read)(AwRtcState *s, uint32_t offset);
219
+
220
+ /**
221
+ * Write device specific register
222
+ *
223
+ * @offset: register offset to write
224
+ * @data: value to set in register
225
+ * @return true if register write successful, false otherwise
226
+ */
227
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
228
+
229
+} AwRtcClass;
230
+
231
+#endif /* HW_MISC_ALLWINNER_RTC_H */
232
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/arm/allwinner-a10.c
235
+++ b/hw/arm/allwinner-a10.c
236
@@ -XXX,XX +XXX,XX @@
237
#define AW_A10_EHCI_BASE 0x01c14000
238
#define AW_A10_OHCI_BASE 0x01c14400
239
#define AW_A10_SATA_BASE 0x01c18000
240
+#define AW_A10_RTC_BASE 0x01c20d00
241
242
static void aw_a10_init(Object *obj)
243
{
45
{
244
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
46
cpu_to_le32s(&desc->cmdstat);
245
47
cpu_to_le16s(&desc->bytes);
246
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
48
cpu_to_le16s(&desc->buffer_size);
247
TYPE_AW_SDHOST_SUN4I);
49
cpu_to_le32s(&desc->buffer);
248
+
50
cpu_to_le32s(&desc->next);
249
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
51
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
250
+ TYPE_AW_RTC_SUN4I);
52
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
251
}
53
}
252
54
253
static void aw_a10_realize(DeviceState *dev, Error **errp)
55
-static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
56
+static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr,
255
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
57
+ mv88w8618_rx_desc *desc)
256
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
58
{
257
"sd-bus", &error_abort);
59
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
258
+
60
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
259
+ /* RTC */
61
le32_to_cpus(&desc->cmdstat);
260
+ qdev_init_nofail(DEVICE(&s->rtc));
62
le16_to_cpus(&desc->bytes);
261
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
63
le16_to_cpus(&desc->buffer_size);
64
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
65
continue;
66
}
67
do {
68
- eth_rx_desc_get(desc_addr, &desc);
69
+ eth_rx_desc_get(&s->dma_as, desc_addr, &desc);
70
if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
71
- cpu_physical_memory_write(desc.buffer + s->vlan_header,
72
+ dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header,
73
buf, size);
74
desc.bytes = size + s->vlan_header;
75
desc.cmdstat &= ~MP_ETH_RX_OWN;
76
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
77
if (s->icr & s->imr) {
78
qemu_irq_raise(s->irq);
79
}
80
- eth_rx_desc_put(desc_addr, &desc);
81
+ eth_rx_desc_put(&s->dma_as, desc_addr, &desc);
82
return size;
83
}
84
desc_addr = desc.next;
85
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
86
return size;
262
}
87
}
263
88
264
static void aw_a10_class_init(ObjectClass *oc, void *data)
89
-static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
265
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
90
+static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr,
266
index XXXXXXX..XXXXXXX 100644
91
+ mv88w8618_tx_desc *desc)
267
--- a/hw/arm/allwinner-h3.c
92
{
268
+++ b/hw/arm/allwinner-h3.c
93
cpu_to_le32s(&desc->cmdstat);
269
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
94
cpu_to_le16s(&desc->res);
270
[AW_H3_GIC_CPU] = 0x01c82000,
95
cpu_to_le16s(&desc->bytes);
271
[AW_H3_GIC_HYP] = 0x01c84000,
96
cpu_to_le32s(&desc->buffer);
272
[AW_H3_GIC_VCPU] = 0x01c86000,
97
cpu_to_le32s(&desc->next);
273
+ [AW_H3_RTC] = 0x01f00000,
98
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
274
[AW_H3_CPUCFG] = 0x01f01c00,
99
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
275
[AW_H3_SDRAM] = 0x40000000
276
};
277
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
278
{ "csi", 0x01cb0000, 320 * KiB },
279
{ "tve", 0x01e00000, 64 * KiB },
280
{ "hdmi", 0x01ee0000, 128 * KiB },
281
- { "rtc", 0x01f00000, 1 * KiB },
282
{ "r_timer", 0x01f00800, 1 * KiB },
283
{ "r_intc", 0x01f00c00, 1 * KiB },
284
{ "r_wdog", 0x01f01000, 1 * KiB },
285
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
286
"ram-addr", &error_abort);
287
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
288
"ram-size", &error_abort);
289
+
290
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
291
+ TYPE_AW_RTC_SUN6I);
292
}
100
}
293
101
294
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
102
-static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
295
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
103
+static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr,
296
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
104
+ mv88w8618_tx_desc *desc)
297
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
105
{
298
106
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
299
+ /* RTC */
107
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
300
+ qdev_init_nofail(DEVICE(&s->rtc));
108
le32_to_cpus(&desc->cmdstat);
301
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
109
le16_to_cpus(&desc->res);
302
+
110
le16_to_cpus(&desc->bytes);
303
/* Unimplemented devices */
111
@@ -XXX,XX +XXX,XX @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
304
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
112
int len;
305
create_unimplemented_device(unimplemented[i].device_name,
113
306
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
114
do {
307
new file mode 100644
115
- eth_tx_desc_get(desc_addr, &desc);
308
index XXXXXXX..XXXXXXX
116
+ eth_tx_desc_get(&s->dma_as, desc_addr, &desc);
309
--- /dev/null
117
next_desc = desc.next;
310
+++ b/hw/rtc/allwinner-rtc.c
118
if (desc.cmdstat & MP_ETH_TX_OWN) {
311
@@ -XXX,XX +XXX,XX @@
119
len = desc.bytes;
312
+/*
120
if (len < 2048) {
313
+ * Allwinner Real Time Clock emulation
121
- cpu_physical_memory_read(desc.buffer, buf, len);
314
+ *
122
+ dma_memory_read(&s->dma_as, desc.buffer, buf, len);
315
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
123
qemu_send_packet(qemu_get_queue(s->nic), buf, len);
316
+ *
124
}
317
+ * This program is free software: you can redistribute it and/or modify
125
desc.cmdstat &= ~MP_ETH_TX_OWN;
318
+ * it under the terms of the GNU General Public License as published by
126
s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
319
+ * the Free Software Foundation, either version 2 of the License, or
127
- eth_tx_desc_put(desc_addr, &desc);
320
+ * (at your option) any later version.
128
+ eth_tx_desc_put(&s->dma_as, desc_addr, &desc);
321
+ *
129
}
322
+ * This program is distributed in the hope that it will be useful,
130
desc_addr = next_desc;
323
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
131
} while (desc_addr != s->tx_queue[queue_index]);
324
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
132
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_eth_realize(DeviceState *dev, Error **errp)
325
+ * GNU General Public License for more details.
133
{
326
+ *
134
mv88w8618_eth_state *s = MV88W8618_ETH(dev);
327
+ * You should have received a copy of the GNU General Public License
135
328
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
136
+ if (!s->dma_mr) {
329
+ */
137
+ error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set");
330
+
331
+#include "qemu/osdep.h"
332
+#include "qemu/units.h"
333
+#include "hw/sysbus.h"
334
+#include "migration/vmstate.h"
335
+#include "qemu/log.h"
336
+#include "qemu/module.h"
337
+#include "qemu-common.h"
338
+#include "hw/qdev-properties.h"
339
+#include "hw/rtc/allwinner-rtc.h"
340
+#include "trace.h"
341
+
342
+/* RTC registers */
343
+enum {
344
+ REG_LOSC = 1, /* Low Oscillator Control */
345
+ REG_YYMMDD, /* RTC Year-Month-Day */
346
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
347
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
348
+ REG_ALARM1_EN, /* Alarm1 Enable */
349
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
350
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
351
+ REG_GP0, /* General Purpose Register 0 */
352
+ REG_GP1, /* General Purpose Register 1 */
353
+ REG_GP2, /* General Purpose Register 2 */
354
+ REG_GP3, /* General Purpose Register 3 */
355
+
356
+ /* sun4i registers */
357
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
358
+ REG_CPUCFG, /* CPU Configuration Register */
359
+
360
+ /* sun6i registers */
361
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
362
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
363
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
364
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
365
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
366
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
367
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
368
+ REG_ALARM_CONFIG, /* Alarm Config */
369
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
370
+ REG_GP4, /* General Purpose Register 4 */
371
+ REG_GP5, /* General Purpose Register 5 */
372
+ REG_GP6, /* General Purpose Register 6 */
373
+ REG_GP7, /* General Purpose Register 7 */
374
+ REG_RTC_DBG, /* RTC Debug Register */
375
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
376
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
377
+ REG_IC_CHARA, /* IC Characteristics Register */
378
+};
379
+
380
+/* RTC register flags */
381
+enum {
382
+ REG_LOSC_YMD = (1 << 7),
383
+ REG_LOSC_HMS = (1 << 8),
384
+};
385
+
386
+/* RTC sun4i register map (offset to name) */
387
+const uint8_t allwinner_rtc_sun4i_regmap[] = {
388
+ [0x0000] = REG_LOSC,
389
+ [0x0004] = REG_YYMMDD,
390
+ [0x0008] = REG_HHMMSS,
391
+ [0x000C] = REG_ALARM1_DDHHMMSS,
392
+ [0x0010] = REG_ALARM1_WKHHMMSS,
393
+ [0x0014] = REG_ALARM1_EN,
394
+ [0x0018] = REG_ALARM1_IRQ_EN,
395
+ [0x001C] = REG_ALARM1_IRQ_STA,
396
+ [0x0020] = REG_GP0,
397
+ [0x0024] = REG_GP1,
398
+ [0x0028] = REG_GP2,
399
+ [0x002C] = REG_GP3,
400
+ [0x003C] = REG_CPUCFG,
401
+};
402
+
403
+/* RTC sun6i register map (offset to name) */
404
+const uint8_t allwinner_rtc_sun6i_regmap[] = {
405
+ [0x0000] = REG_LOSC,
406
+ [0x0004] = REG_LOSC_AUTOSTA,
407
+ [0x0008] = REG_INT_OSC_PRE,
408
+ [0x0010] = REG_YYMMDD,
409
+ [0x0014] = REG_HHMMSS,
410
+ [0x0020] = REG_ALARM0_COUNTER,
411
+ [0x0024] = REG_ALARM0_CUR_VLU,
412
+ [0x0028] = REG_ALARM0_ENABLE,
413
+ [0x002C] = REG_ALARM0_IRQ_EN,
414
+ [0x0030] = REG_ALARM0_IRQ_STA,
415
+ [0x0040] = REG_ALARM1_WKHHMMSS,
416
+ [0x0044] = REG_ALARM1_EN,
417
+ [0x0048] = REG_ALARM1_IRQ_EN,
418
+ [0x004C] = REG_ALARM1_IRQ_STA,
419
+ [0x0050] = REG_ALARM_CONFIG,
420
+ [0x0060] = REG_LOSC_OUT_GATING,
421
+ [0x0100] = REG_GP0,
422
+ [0x0104] = REG_GP1,
423
+ [0x0108] = REG_GP2,
424
+ [0x010C] = REG_GP3,
425
+ [0x0110] = REG_GP4,
426
+ [0x0114] = REG_GP5,
427
+ [0x0118] = REG_GP6,
428
+ [0x011C] = REG_GP7,
429
+ [0x0170] = REG_RTC_DBG,
430
+ [0x0180] = REG_GPL_HOLD_OUT,
431
+ [0x0190] = REG_VDD_RTC,
432
+ [0x01F0] = REG_IC_CHARA,
433
+};
434
+
435
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
436
+{
437
+ /* no sun4i specific registers currently implemented */
438
+ return false;
439
+}
440
+
441
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
442
+ uint32_t data)
443
+{
444
+ /* no sun4i specific registers currently implemented */
445
+ return false;
446
+}
447
+
448
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
449
+{
450
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
451
+
452
+ switch (c->regmap[offset]) {
453
+ case REG_GP4: /* General Purpose Register 4 */
454
+ case REG_GP5: /* General Purpose Register 5 */
455
+ case REG_GP6: /* General Purpose Register 6 */
456
+ case REG_GP7: /* General Purpose Register 7 */
457
+ return true;
458
+ default:
459
+ break;
460
+ }
461
+ return false;
462
+}
463
+
464
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
465
+ uint32_t data)
466
+{
467
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
468
+
469
+ switch (c->regmap[offset]) {
470
+ case REG_GP4: /* General Purpose Register 4 */
471
+ case REG_GP5: /* General Purpose Register 5 */
472
+ case REG_GP6: /* General Purpose Register 6 */
473
+ case REG_GP7: /* General Purpose Register 7 */
474
+ return true;
475
+ default:
476
+ break;
477
+ }
478
+ return false;
479
+}
480
+
481
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
482
+ unsigned size)
483
+{
484
+ AwRtcState *s = AW_RTC(opaque);
485
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
486
+ uint64_t val = 0;
487
+
488
+ if (offset >= c->regmap_size) {
489
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
490
+ __func__, (uint32_t)offset);
491
+ return 0;
492
+ }
493
+
494
+ if (!c->regmap[offset]) {
495
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
496
+ __func__, (uint32_t)offset);
497
+ return 0;
498
+ }
499
+
500
+ switch (c->regmap[offset]) {
501
+ case REG_LOSC: /* Low Oscillator Control */
502
+ val = s->regs[REG_LOSC];
503
+ s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
504
+ break;
505
+ case REG_YYMMDD: /* RTC Year-Month-Day */
506
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
507
+ case REG_GP0: /* General Purpose Register 0 */
508
+ case REG_GP1: /* General Purpose Register 1 */
509
+ case REG_GP2: /* General Purpose Register 2 */
510
+ case REG_GP3: /* General Purpose Register 3 */
511
+ val = s->regs[c->regmap[offset]];
512
+ break;
513
+ default:
514
+ if (!c->read(s, offset)) {
515
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
516
+ __func__, (uint32_t)offset);
517
+ }
518
+ val = s->regs[c->regmap[offset]];
519
+ break;
520
+ }
521
+
522
+ trace_allwinner_rtc_read(offset, val);
523
+ return val;
524
+}
525
+
526
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
527
+ uint64_t val, unsigned size)
528
+{
529
+ AwRtcState *s = AW_RTC(opaque);
530
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
531
+
532
+ if (offset >= c->regmap_size) {
533
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
534
+ __func__, (uint32_t)offset);
535
+ return;
138
+ return;
536
+ }
139
+ }
537
+
140
+
538
+ if (!c->regmap[offset]) {
141
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
539
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
142
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
540
+ __func__, (uint32_t)offset);
143
object_get_typename(OBJECT(dev)), dev->id, s);
541
+ return;
144
}
542
+ }
145
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mv88w8618_eth_vmsd = {
543
+
146
544
+ trace_allwinner_rtc_write(offset, val);
147
static Property mv88w8618_eth_properties[] = {
545
+
148
DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
546
+ switch (c->regmap[offset]) {
149
+ DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr,
547
+ case REG_YYMMDD: /* RTC Year-Month-Day */
150
+ TYPE_MEMORY_REGION, MemoryRegion *),
548
+ s->regs[REG_YYMMDD] = val;
151
DEFINE_PROP_END_OF_LIST(),
549
+ s->regs[REG_LOSC] |= REG_LOSC_YMD;
152
};
550
+ break;
153
551
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
154
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
552
+ s->regs[REG_HHMMSS] = val;
155
qemu_check_nic_model(&nd_table[0], "mv88w8618");
553
+ s->regs[REG_LOSC] |= REG_LOSC_HMS;
156
dev = qdev_new(TYPE_MV88W8618_ETH);
554
+ break;
157
qdev_set_nic_properties(dev, &nd_table[0]);
555
+ case REG_GP0: /* General Purpose Register 0 */
158
+ object_property_set_link(OBJECT(dev), "dma-memory",
556
+ case REG_GP1: /* General Purpose Register 1 */
159
+ OBJECT(get_system_memory()), &error_fatal);
557
+ case REG_GP2: /* General Purpose Register 2 */
160
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
558
+ case REG_GP3: /* General Purpose Register 3 */
161
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
559
+ s->regs[c->regmap[offset]] = val;
162
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
560
+ break;
561
+ default:
562
+ if (!c->write(s, offset, val)) {
563
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
564
+ __func__, (uint32_t)offset);
565
+ }
566
+ break;
567
+ }
568
+}
569
+
570
+static const MemoryRegionOps allwinner_rtc_ops = {
571
+ .read = allwinner_rtc_read,
572
+ .write = allwinner_rtc_write,
573
+ .endianness = DEVICE_NATIVE_ENDIAN,
574
+ .valid = {
575
+ .min_access_size = 4,
576
+ .max_access_size = 4,
577
+ },
578
+ .impl.min_access_size = 4,
579
+};
580
+
581
+static void allwinner_rtc_reset(DeviceState *dev)
582
+{
583
+ AwRtcState *s = AW_RTC(dev);
584
+ struct tm now;
585
+
586
+ /* Clear registers */
587
+ memset(s->regs, 0, sizeof(s->regs));
588
+
589
+ /* Get current datetime */
590
+ qemu_get_timedate(&now, 0);
591
+
592
+ /* Set RTC with current datetime */
593
+ if (s->base_year > 1900) {
594
+ s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
595
+ ((now.tm_mon + 1) << 8) |
596
+ now.tm_mday;
597
+ s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
598
+ (now.tm_hour << 16) |
599
+ (now.tm_min << 8) |
600
+ now.tm_sec;
601
+ }
602
+}
603
+
604
+static void allwinner_rtc_init(Object *obj)
605
+{
606
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
607
+ AwRtcState *s = AW_RTC(obj);
608
+
609
+ /* Memory mapping */
610
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
611
+ TYPE_AW_RTC, 1 * KiB);
612
+ sysbus_init_mmio(sbd, &s->iomem);
613
+}
614
+
615
+static const VMStateDescription allwinner_rtc_vmstate = {
616
+ .name = "allwinner-rtc",
617
+ .version_id = 1,
618
+ .minimum_version_id = 1,
619
+ .fields = (VMStateField[]) {
620
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
621
+ VMSTATE_END_OF_LIST()
622
+ }
623
+};
624
+
625
+static Property allwinner_rtc_properties[] = {
626
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
627
+ DEFINE_PROP_END_OF_LIST(),
628
+};
629
+
630
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
631
+{
632
+ DeviceClass *dc = DEVICE_CLASS(klass);
633
+
634
+ dc->reset = allwinner_rtc_reset;
635
+ dc->vmsd = &allwinner_rtc_vmstate;
636
+ device_class_set_props(dc, allwinner_rtc_properties);
637
+}
638
+
639
+static void allwinner_rtc_sun4i_init(Object *obj)
640
+{
641
+ AwRtcState *s = AW_RTC(obj);
642
+ s->base_year = 2010;
643
+}
644
+
645
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
646
+{
647
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
648
+
649
+ arc->regmap = allwinner_rtc_sun4i_regmap;
650
+ arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
651
+ arc->read = allwinner_rtc_sun4i_read;
652
+ arc->write = allwinner_rtc_sun4i_write;
653
+}
654
+
655
+static void allwinner_rtc_sun6i_init(Object *obj)
656
+{
657
+ AwRtcState *s = AW_RTC(obj);
658
+ s->base_year = 1970;
659
+}
660
+
661
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
662
+{
663
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
664
+
665
+ arc->regmap = allwinner_rtc_sun6i_regmap;
666
+ arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
667
+ arc->read = allwinner_rtc_sun6i_read;
668
+ arc->write = allwinner_rtc_sun6i_write;
669
+}
670
+
671
+static void allwinner_rtc_sun7i_init(Object *obj)
672
+{
673
+ AwRtcState *s = AW_RTC(obj);
674
+ s->base_year = 1970;
675
+}
676
+
677
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
678
+{
679
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
680
+ allwinner_rtc_sun4i_class_init(klass, arc);
681
+}
682
+
683
+static const TypeInfo allwinner_rtc_info = {
684
+ .name = TYPE_AW_RTC,
685
+ .parent = TYPE_SYS_BUS_DEVICE,
686
+ .instance_init = allwinner_rtc_init,
687
+ .instance_size = sizeof(AwRtcState),
688
+ .class_init = allwinner_rtc_class_init,
689
+ .class_size = sizeof(AwRtcClass),
690
+ .abstract = true,
691
+};
692
+
693
+static const TypeInfo allwinner_rtc_sun4i_info = {
694
+ .name = TYPE_AW_RTC_SUN4I,
695
+ .parent = TYPE_AW_RTC,
696
+ .class_init = allwinner_rtc_sun4i_class_init,
697
+ .instance_init = allwinner_rtc_sun4i_init,
698
+};
699
+
700
+static const TypeInfo allwinner_rtc_sun6i_info = {
701
+ .name = TYPE_AW_RTC_SUN6I,
702
+ .parent = TYPE_AW_RTC,
703
+ .class_init = allwinner_rtc_sun6i_class_init,
704
+ .instance_init = allwinner_rtc_sun6i_init,
705
+};
706
+
707
+static const TypeInfo allwinner_rtc_sun7i_info = {
708
+ .name = TYPE_AW_RTC_SUN7I,
709
+ .parent = TYPE_AW_RTC,
710
+ .class_init = allwinner_rtc_sun7i_class_init,
711
+ .instance_init = allwinner_rtc_sun7i_init,
712
+};
713
+
714
+static void allwinner_rtc_register(void)
715
+{
716
+ type_register_static(&allwinner_rtc_info);
717
+ type_register_static(&allwinner_rtc_sun4i_info);
718
+ type_register_static(&allwinner_rtc_sun6i_info);
719
+ type_register_static(&allwinner_rtc_sun7i_info);
720
+}
721
+
722
+type_init(allwinner_rtc_register)
723
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
724
index XXXXXXX..XXXXXXX 100644
725
--- a/hw/rtc/trace-events
726
+++ b/hw/rtc/trace-events
727
@@ -XXX,XX +XXX,XX @@
728
# See docs/devel/tracing.txt for syntax documentation.
729
730
+# allwinner-rtc.c
731
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
732
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
733
+
734
# sun4v-rtc.c
735
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
736
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
737
--
163
--
738
2.20.1
164
2.20.1
739
165
740
166
diff view generated by jsdifflib
1
Fix a couple of comment typos.
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
In commit ce4afed839 ("target/arm: Implement AArch32 HCR and HCR2")
4
the HCR_EL2 register has been changed from type NO_RAW (no underlying
5
state and does not support raw access for state saving/loading) to
6
type CONST (TCG can assume the value to be constant), removing the
7
read/write accessors.
8
We forgot to remove the previous type ARM_CP_NO_RAW. This is not
9
really a problem since the field is overwritten. However it makes
10
code review confuse, so remove it.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200812111223.7787-1-f4bug@amsat.org
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200303174950.3298-5-peter.maydell@linaro.org
6
---
17
---
7
target/arm/helper.c | 2 +-
18
target/arm/helper.c | 1 -
8
target/arm/translate.c | 2 +-
19
1 file changed, 1 deletion(-)
9
2 files changed, 2 insertions(+), 2 deletions(-)
10
20
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
23
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
24
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
16
26
.access = PL2_RW,
17
/*
27
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
18
* If we have triggered a EL state change we can't rely on the
28
{ .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
19
- * translator having passed it too us, we need to recompute.
29
- .type = ARM_CP_NO_RAW,
20
+ * translator having passed it to us, we need to recompute.
30
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
21
*/
31
.access = PL2_RW,
22
void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
32
.type = ARM_CP_CONST, .resetvalue = 0 },
23
{
24
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate.c
27
+++ b/target/arm/translate.c
28
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
29
30
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
31
/*
32
- * A write to any coprocessor regiser that ends a TB
33
+ * A write to any coprocessor register that ends a TB
34
* must rebuild the hflags for the next TB.
35
*/
36
TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
37
--
33
--
38
2.20.1
34
2.20.1
39
35
40
36
diff view generated by jsdifflib
1
From: Beata Michalska <beata.michalska@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
3
We need more information than just the mmu_idx in order
4
As such this should be the last step of sync to avoid potential overwriting
4
to create the proper exception syndrome. Only change the
5
of whatever changes KVM might have done.
5
function signature so far.
6
6
7
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20200813200816.3037186-2-richard.henderson@linaro.org
9
Message-id: 20200312003401.29017-2-beata.michalska@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/kvm32.c | 15 ++++++++++-----
12
target/arm/mte_helper.c | 10 +++++-----
13
target/arm/kvm64.c | 15 ++++++++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
2 files changed, 20 insertions(+), 10 deletions(-)
15
14
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
15
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
17
--- a/target/arm/mte_helper.c
19
+++ b/target/arm/kvm32.c
18
+++ b/target/arm/mte_helper.c
20
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
19
@@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
21
return ret;
20
}
21
22
/* Record a tag check failure. */
23
-static void mte_check_fail(CPUARMState *env, int mmu_idx,
24
+static void mte_check_fail(CPUARMState *env, uint32_t desc,
25
uint64_t dirty_ptr, uintptr_t ra)
26
{
27
+ int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
28
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
29
int el, reg_el, tcf, select;
30
uint64_t sctlr;
31
@@ -XXX,XX +XXX,XX @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc,
22
}
32
}
23
33
24
- ret = kvm_put_vcpu_events(cpu);
34
if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
25
- if (ret) {
35
- int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
26
- return ret;
36
- mte_check_fail(env, mmu_idx, ptr, ra);
27
- }
37
+ mte_check_fail(env, desc, ptr, ra);
28
-
29
write_cpustate_to_list(cpu, true);
30
31
if (!write_list_to_kvmstate(cpu, level)) {
32
return EINVAL;
33
}
38
}
34
39
35
+ /*
40
return useronly_clean_ptr(ptr);
36
+ * Setting VCPU events should be triggered after syncing the registers
41
@@ -XXX,XX +XXX,XX @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
37
+ * to avoid overwriting potential changes made by KVM upon calling
42
38
+ * KVM_SET_VCPU_EVENTS ioctl
43
fail_ofs = tag_first + n * TAG_GRANULE - ptr;
39
+ */
44
fail_ofs = ROUND_UP(fail_ofs, esize);
40
+ ret = kvm_put_vcpu_events(cpu);
45
- mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra);
41
+ if (ret) {
46
+ mte_check_fail(env, desc, ptr + fail_ofs, ra);
42
+ return ret;
43
+ }
44
+
45
kvm_arm_sync_mpstate_to_kvm(cpu);
46
47
return ret;
48
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/kvm64.c
51
+++ b/target/arm/kvm64.c
52
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
53
return ret;
54
}
47
}
55
48
56
- ret = kvm_put_vcpu_events(cpu);
49
done:
57
- if (ret) {
50
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)
58
- return ret;
51
fail:
59
- }
52
/* Locate the first nibble that differs. */
60
-
53
i = ctz64(mem_tag ^ ptr_tag) >> 4;
61
write_cpustate_to_list(cpu, true);
54
- mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra);
62
55
+ mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra);
63
if (!write_list_to_kvmstate(cpu, level)) {
56
64
return -EINVAL;
57
done:
65
}
58
return useronly_clean_ptr(ptr);
66
67
+ /*
68
+ * Setting VCPU events should be triggered after syncing the registers
69
+ * to avoid overwriting potential changes made by KVM upon calling
70
+ * KVM_SET_VCPU_EVENTS ioctl
71
+ */
72
+ ret = kvm_put_vcpu_events(cpu);
73
+ if (ret) {
74
+ return ret;
75
+ }
76
+
77
kvm_arm_sync_mpstate_to_kvm(cpu);
78
79
return ret;
80
--
59
--
81
2.20.1
60
2.20.1
82
61
83
62
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
At the moment if the end-user does not specify the gic-version along
3
According to AArch64.TagCheckFault, none of the other ISS values are
4
with KVM acceleration, v2 is set by default. However most of the
4
provided, so we do not need to go so far as merge_syn_data_abort.
5
systems now have GICv3 and sometimes they do not support GICv2
5
But we were missing the WnR bit.
6
compatibility.
7
6
8
This patch keeps the default v2 selection in all cases except
7
Tested-by: Andrey Konovalov <andreyknvl@google.com>
9
in the KVM accelerated mode when either
8
Reported-by: Andrey Konovalov <andreyknvl@google.com>
10
- the host does not support GICv2 in-kernel emulation or
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
- number of VCPUS exceeds 8.
10
Message-id: 20200813200816.3037186-3-richard.henderson@linaro.org
12
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Those cases did not work anyway so we do not break any compatibility.
14
Now we get v3 selected in such a case.
15
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
18
Reviewed-by: Andrew Jones <drjones@redhat.com>
19
Message-id: 20200311131618.7187-7-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
13
---
22
hw/arm/virt.c | 17 ++++++++++++++++-
14
target/arm/mte_helper.c | 9 +++++----
23
1 file changed, 16 insertions(+), 1 deletion(-)
15
1 file changed, 5 insertions(+), 4 deletions(-)
24
16
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
26
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
19
--- a/target/arm/mte_helper.c
28
+++ b/hw/arm/virt.c
20
+++ b/target/arm/mte_helper.c
29
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
21
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
30
*/
31
static void finalize_gic_version(VirtMachineState *vms)
32
{
22
{
33
+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
23
int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
24
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
25
- int el, reg_el, tcf, select;
26
+ int el, reg_el, tcf, select, is_write, syn;
27
uint64_t sctlr;
28
29
reg_el = regime_el(env, arm_mmu_idx);
30
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
31
*/
32
cpu_restore_state(env_cpu(env), ra, true);
33
env->exception.vaddress = dirty_ptr;
34
- raise_exception(env, EXCP_DATA_ABORT,
35
- syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0, 0x11),
36
- exception_target_el(env));
34
+
37
+
35
if (kvm_enabled()) {
38
+ is_write = FIELD_EX32(desc, MTEDESC, WRITE);
36
int probe_bitmap;
39
+ syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
37
40
+ raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
38
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
41
/* noreturn, but fall through to the assert anyway */
39
}
42
40
return;
43
case 0:
41
case VIRT_GIC_VERSION_NOSEL:
42
- vms->gic_version = VIRT_GIC_VERSION_2;
43
+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
44
+ vms->gic_version = VIRT_GIC_VERSION_2;
45
+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
46
+ /*
47
+ * in case the host does not support v2 in-kernel emulation or
48
+ * the end-user requested more than 8 VCPUs we now default
49
+ * to v3. In any case defaulting to v2 would be broken.
50
+ */
51
+ vms->gic_version = VIRT_GIC_VERSION_3;
52
+ } else if (max_cpus > GIC_NCPU) {
53
+ error_report("host only supports in-kernel GICv2 emulation "
54
+ "but more than 8 vcpus are requested");
55
+ exit(1);
56
+ }
57
break;
58
case VIRT_GIC_VERSION_2:
59
case VIRT_GIC_VERSION_3:
60
--
44
--
61
2.20.1
45
2.20.1
62
46
63
47
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The Allwinner System on Chip families sun4i and above contain
3
Allow the device to execute the DMA transfers in a different
4
an integrated storage controller for Secure Digital (SD) and
4
AddressSpace.
5
Multi Media Card (MMC) interfaces. This commit adds support
6
for the Allwinner SD/MMC storage controller with the following
7
emulated features:
8
5
9
* DMA transfers
6
The A10 and H3 SoC keep using the system_memory address space,
10
* Direct FIFO I/O
7
but via the proper dma_memory_access() API.
11
* Short/Long format command responses
12
* Auto-Stop command (CMD12)
13
* Insert & remove card detection
14
8
15
The following boards are extended with the SD host controller:
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
10
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
17
* Cubieboard (hw/arm/cubieboard.c)
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
18
* Orange Pi PC (hw/arm/orangepi.c)
12
Message-id: 20200814110057.307-1-f4bug@amsat.org
19
20
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
21
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
22
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
14
---
26
hw/sd/Makefile.objs | 1 +
15
include/hw/sd/allwinner-sdhost.h | 6 ++++++
27
include/hw/arm/allwinner-a10.h | 2 +
16
hw/arm/allwinner-a10.c | 2 ++
28
include/hw/arm/allwinner-h3.h | 3 +
17
hw/arm/allwinner-h3.c | 2 ++
29
include/hw/sd/allwinner-sdhost.h | 135 +++++
18
hw/sd/allwinner-sdhost.c | 37 ++++++++++++++++++++++++++------
30
hw/arm/allwinner-a10.c | 11 +
19
4 files changed, 41 insertions(+), 6 deletions(-)
31
hw/arm/allwinner-h3.c | 15 +-
32
hw/arm/cubieboard.c | 15 +
33
hw/arm/orangepi.c | 16 +
34
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
35
hw/arm/Kconfig | 1 +
36
hw/sd/trace-events | 7 +
37
11 files changed, 1059 insertions(+), 1 deletion(-)
38
create mode 100644 include/hw/sd/allwinner-sdhost.h
39
create mode 100644 hw/sd/allwinner-sdhost.c
40
20
41
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
21
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
42
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/sd/Makefile.objs
23
--- a/include/hw/sd/allwinner-sdhost.h
44
+++ b/hw/sd/Makefile.objs
45
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o
46
common-obj-$(CONFIG_SDHCI) += sdhci.o
47
common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o
48
49
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o
50
common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
51
common-obj-$(CONFIG_OMAP) += omap_mmc.o
52
common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
53
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/hw/arm/allwinner-a10.h
56
+++ b/include/hw/arm/allwinner-a10.h
57
@@ -XXX,XX +XXX,XX @@
58
#include "hw/timer/allwinner-a10-pit.h"
59
#include "hw/intc/allwinner-a10-pic.h"
60
#include "hw/net/allwinner_emac.h"
61
+#include "hw/sd/allwinner-sdhost.h"
62
#include "hw/ide/ahci.h"
63
#include "hw/usb/hcd-ohci.h"
64
#include "hw/usb/hcd-ehci.h"
65
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
66
AwA10PICState intc;
67
AwEmacState emac;
68
AllwinnerAHCIState sata;
69
+ AwSdHostState mmc0;
70
MemoryRegion sram_a;
71
EHCISysBusState ehci[AW_A10_NUM_USB];
72
OHCISysBusState ohci[AW_A10_NUM_USB];
73
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
74
index XXXXXXX..XXXXXXX 100644
75
--- a/include/hw/arm/allwinner-h3.h
76
+++ b/include/hw/arm/allwinner-h3.h
77
@@ -XXX,XX +XXX,XX @@
78
#include "hw/misc/allwinner-cpucfg.h"
79
#include "hw/misc/allwinner-h3-sysctrl.h"
80
#include "hw/misc/allwinner-sid.h"
81
+#include "hw/sd/allwinner-sdhost.h"
82
#include "target/arm/cpu.h"
83
84
/**
85
@@ -XXX,XX +XXX,XX @@ enum {
86
AW_H3_SRAM_A2,
87
AW_H3_SRAM_C,
88
AW_H3_SYSCTRL,
89
+ AW_H3_MMC0,
90
AW_H3_SID,
91
AW_H3_EHCI0,
92
AW_H3_OHCI0,
93
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
94
AwCpuCfgState cpucfg;
95
AwH3SysCtrlState sysctrl;
96
AwSidState sid;
97
+ AwSdHostState mmc0;
98
GICState gic;
99
MemoryRegion sram_a1;
100
MemoryRegion sram_a2;
101
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
102
new file mode 100644
103
index XXXXXXX..XXXXXXX
104
--- /dev/null
105
+++ b/include/hw/sd/allwinner-sdhost.h
24
+++ b/include/hw/sd/allwinner-sdhost.h
106
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSdHostState {
107
+/*
26
/** Interrupt output signal to notify CPU */
108
+ * Allwinner (sun4i and above) SD Host Controller emulation
27
qemu_irq irq;
109
+ *
28
110
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
29
+ /** Memory region where DMA transfers are done */
111
+ *
30
+ MemoryRegion *dma_mr;
112
+ * This program is free software: you can redistribute it and/or modify
113
+ * it under the terms of the GNU General Public License as published by
114
+ * the Free Software Foundation, either version 2 of the License, or
115
+ * (at your option) any later version.
116
+ *
117
+ * This program is distributed in the hope that it will be useful,
118
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
119
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
120
+ * GNU General Public License for more details.
121
+ *
122
+ * You should have received a copy of the GNU General Public License
123
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
124
+ */
125
+
31
+
126
+#ifndef HW_SD_ALLWINNER_SDHOST_H
32
+ /** Address space used internally for DMA transfers */
127
+#define HW_SD_ALLWINNER_SDHOST_H
33
+ AddressSpace dma_as;
128
+
34
+
129
+#include "qom/object.h"
35
/** Number of bytes left in current DMA transfer */
130
+#include "hw/sysbus.h"
36
uint32_t transfer_cnt;
131
+#include "hw/sd/sd.h"
37
132
+
133
+/**
134
+ * Object model types
135
+ * @{
136
+ */
137
+
138
+/** Generic Allwinner SD Host Controller (abstract) */
139
+#define TYPE_AW_SDHOST "allwinner-sdhost"
140
+
141
+/** Allwinner sun4i family (A10, A12) */
142
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
143
+
144
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
145
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
146
+
147
+/** @} */
148
+
149
+/**
150
+ * Object model macros
151
+ * @{
152
+ */
153
+
154
+#define AW_SDHOST(obj) \
155
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
156
+#define AW_SDHOST_CLASS(klass) \
157
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
158
+#define AW_SDHOST_GET_CLASS(obj) \
159
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
160
+
161
+/** @} */
162
+
163
+/**
164
+ * Allwinner SD Host Controller object instance state.
165
+ */
166
+typedef struct AwSdHostState {
167
+ /*< private >*/
168
+ SysBusDevice busdev;
169
+ /*< public >*/
170
+
171
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
172
+ SDBus sdbus;
173
+
174
+ /** Maps I/O registers in physical memory */
175
+ MemoryRegion iomem;
176
+
177
+ /** Interrupt output signal to notify CPU */
178
+ qemu_irq irq;
179
+
180
+ /** Number of bytes left in current DMA transfer */
181
+ uint32_t transfer_cnt;
182
+
183
+ /**
184
+ * @name Hardware Registers
185
+ * @{
186
+ */
187
+
188
+ uint32_t global_ctl; /**< Global Control */
189
+ uint32_t clock_ctl; /**< Clock Control */
190
+ uint32_t timeout; /**< Timeout */
191
+ uint32_t bus_width; /**< Bus Width */
192
+ uint32_t block_size; /**< Block Size */
193
+ uint32_t byte_count; /**< Byte Count */
194
+
195
+ uint32_t command; /**< Command */
196
+ uint32_t command_arg; /**< Command Argument */
197
+ uint32_t response[4]; /**< Command Response */
198
+
199
+ uint32_t irq_mask; /**< Interrupt Mask */
200
+ uint32_t irq_status; /**< Raw Interrupt Status */
201
+ uint32_t status; /**< Status */
202
+
203
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
204
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
205
+ uint32_t debug_enable; /**< Debug Enable */
206
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
207
+ uint32_t newtiming_set; /**< SD New Timing Set */
208
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
209
+ uint32_t hardware_rst; /**< Hardware Reset */
210
+ uint32_t dmac; /**< Internal DMA Controller Control */
211
+ uint32_t desc_base; /**< Descriptor List Base Address */
212
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
213
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
214
+ uint32_t card_threshold; /**< Card Threshold Control */
215
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
216
+ uint32_t response_crc; /**< Response CRC */
217
+ uint32_t data_crc[8]; /**< Data CRC */
218
+ uint32_t status_crc; /**< Status CRC */
219
+
220
+ /** @} */
221
+
222
+} AwSdHostState;
223
+
224
+/**
225
+ * Allwinner SD Host Controller class-level struct.
226
+ *
227
+ * This struct is filled by each sunxi device specific code
228
+ * such that the generic code can use this struct to support
229
+ * all devices.
230
+ */
231
+typedef struct AwSdHostClass {
232
+ /*< private >*/
233
+ SysBusDeviceClass parent_class;
234
+ /*< public >*/
235
+
236
+ /** Maximum buffer size in bytes per DMA descriptor */
237
+ size_t max_desc_size;
238
+
239
+} AwSdHostClass;
240
+
241
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
242
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
38
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
243
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/arm/allwinner-a10.c
40
--- a/hw/arm/allwinner-a10.c
245
+++ b/hw/arm/allwinner-a10.c
41
+++ b/hw/arm/allwinner-a10.c
246
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
247
#include "hw/boards.h"
248
#include "hw/usb/hcd-ohci.h"
249
250
+#define AW_A10_MMC0_BASE 0x01c0f000
251
#define AW_A10_PIC_REG_BASE 0x01c20400
252
#define AW_A10_PIT_REG_BASE 0x01c20c00
253
#define AW_A10_UART0_REG_BASE 0x01c28000
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
255
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
256
}
257
}
43
}
258
+
44
259
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
45
/* SD/MMC */
260
+ TYPE_AW_SDHOST_SUN4I);
46
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
261
}
47
+ OBJECT(get_system_memory()), &error_fatal);
262
48
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
263
static void aw_a10_realize(DeviceState *dev, Error **errp)
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
264
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
265
qdev_get_gpio_in(dev, 64 + i));
266
}
267
}
268
+
269
+ /* SD/MMC */
270
+ qdev_init_nofail(DEVICE(&s->mmc0));
271
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
272
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
273
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
274
+ "sd-bus", &error_abort);
275
}
276
277
static void aw_a10_class_init(ObjectClass *oc, void *data)
278
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
51
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
279
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
280
--- a/hw/arm/allwinner-h3.c
53
--- a/hw/arm/allwinner-h3.c
281
+++ b/hw/arm/allwinner-h3.c
54
+++ b/hw/arm/allwinner-h3.c
282
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
283
[AW_H3_SRAM_A2] = 0x00044000,
284
[AW_H3_SRAM_C] = 0x00010000,
285
[AW_H3_SYSCTRL] = 0x01c00000,
286
+ [AW_H3_MMC0] = 0x01c0f000,
287
[AW_H3_SID] = 0x01c14000,
288
[AW_H3_EHCI0] = 0x01c1a000,
289
[AW_H3_OHCI0] = 0x01c1a400,
290
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
291
{ "lcd0", 0x01c0c000, 4 * KiB },
292
{ "lcd1", 0x01c0d000, 4 * KiB },
293
{ "ve", 0x01c0e000, 4 * KiB },
294
- { "mmc0", 0x01c0f000, 4 * KiB },
295
{ "mmc1", 0x01c10000, 4 * KiB },
296
{ "mmc2", 0x01c11000, 4 * KiB },
297
{ "crypto", 0x01c15000, 4 * KiB },
298
@@ -XXX,XX +XXX,XX @@ enum {
299
AW_H3_GIC_SPI_UART3 = 3,
300
AW_H3_GIC_SPI_TIMER0 = 18,
301
AW_H3_GIC_SPI_TIMER1 = 19,
302
+ AW_H3_GIC_SPI_MMC0 = 60,
303
AW_H3_GIC_SPI_EHCI0 = 72,
304
AW_H3_GIC_SPI_OHCI0 = 73,
305
AW_H3_GIC_SPI_EHCI1 = 74,
306
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
307
TYPE_AW_SID);
308
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
309
"identifier", &error_abort);
310
+
311
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
312
+ TYPE_AW_SDHOST_SUN5I);
313
}
314
315
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
316
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
55
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
317
qdev_init_nofail(DEVICE(&s->sid));
318
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
56
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
319
57
320
+ /* SD/MMC */
58
/* SD/MMC */
321
+ qdev_init_nofail(DEVICE(&s->mmc0));
59
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
60
+ OBJECT(get_system_memory()), &error_fatal);
323
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
61
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
324
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
62
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
325
+
63
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
326
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
64
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
327
+ "sd-bus", &error_abort);
328
+
329
/* Universal Serial Bus */
330
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
331
qdev_get_gpio_in(DEVICE(&s->gic),
332
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
333
index XXXXXXX..XXXXXXX 100644
65
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/cubieboard.c
66
--- a/hw/sd/allwinner-sdhost.c
335
+++ b/hw/arm/cubieboard.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "sysemu/sysemu.h"
338
#include "hw/sysbus.h"
339
#include "hw/boards.h"
340
+#include "hw/qdev-properties.h"
341
#include "hw/arm/allwinner-a10.h"
342
343
static struct arm_boot_info cubieboard_binfo = {
344
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
345
{
346
AwA10State *a10;
347
Error *err = NULL;
348
+ DriveInfo *di;
349
+ BlockBackend *blk;
350
+ BusState *bus;
351
+ DeviceState *carddev;
352
353
/* BIOS is not supported by this board */
354
if (bios_name) {
355
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
356
exit(1);
357
}
358
359
+ /* Retrieve SD bus */
360
+ di = drive_get_next(IF_SD);
361
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
362
+ bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
363
+
364
+ /* Plug in SD card */
365
+ carddev = qdev_create(bus, TYPE_SD_CARD);
366
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
367
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
368
+
369
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
370
machine->ram);
371
372
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
373
index XXXXXXX..XXXXXXX 100644
374
--- a/hw/arm/orangepi.c
375
+++ b/hw/arm/orangepi.c
376
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = {
377
static void orangepi_init(MachineState *machine)
378
{
379
AwH3State *h3;
380
+ DriveInfo *di;
381
+ BlockBackend *blk;
382
+ BusState *bus;
383
+ DeviceState *carddev;
384
385
/* BIOS is not supported by this board */
386
if (bios_name) {
387
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
388
/* Mark H3 object realized */
389
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
390
391
+ /* Retrieve SD bus */
392
+ di = drive_get_next(IF_SD);
393
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
394
+ bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
395
+
396
+ /* Plug in SD card */
397
+ carddev = qdev_create(bus, TYPE_SD_CARD);
398
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
399
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
400
+
401
/* SDRAM */
402
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
403
machine->ram);
404
@@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc)
405
{
406
mc->desc = "Orange Pi PC";
407
mc->init = orangepi_init;
408
+ mc->block_default_type = IF_SD;
409
+ mc->units_per_default_bus = 1;
410
mc->min_cpus = AW_H3_NUM_CPUS;
411
mc->max_cpus = AW_H3_NUM_CPUS;
412
mc->default_cpus = AW_H3_NUM_CPUS;
413
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
414
new file mode 100644
415
index XXXXXXX..XXXXXXX
416
--- /dev/null
417
+++ b/hw/sd/allwinner-sdhost.c
67
+++ b/hw/sd/allwinner-sdhost.c
418
@@ -XXX,XX +XXX,XX @@
68
@@ -XXX,XX +XXX,XX @@
419
+/*
69
#include "qemu/log.h"
420
+ * Allwinner (sun4i and above) SD Host Controller emulation
70
#include "qemu/module.h"
421
+ *
71
#include "qemu/units.h"
422
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
72
+#include "qapi/error.h"
423
+ *
73
#include "sysemu/blockdev.h"
424
+ * This program is free software: you can redistribute it and/or modify
74
+#include "sysemu/dma.h"
425
+ * it under the terms of the GNU General Public License as published by
75
+#include "hw/qdev-properties.h"
426
+ * the Free Software Foundation, either version 2 of the License, or
76
#include "hw/irq.h"
427
+ * (at your option) any later version.
77
#include "hw/sd/allwinner-sdhost.h"
428
+ *
78
#include "migration/vmstate.h"
429
+ * This program is distributed in the hope that it will be useful,
79
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
430
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
80
uint8_t buf[1024];
431
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
81
432
+ * GNU General Public License for more details.
82
/* Read descriptor */
433
+ *
83
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
434
+ * You should have received a copy of the GNU General Public License
84
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
435
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
85
if (desc->size == 0) {
436
+ */
86
desc->size = klass->max_desc_size;
437
+
87
} else if (desc->size > klass->max_desc_size) {
438
+#include "qemu/osdep.h"
88
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
439
+#include "qemu/log.h"
89
440
+#include "qemu/module.h"
90
/* Write to SD bus */
441
+#include "qemu/units.h"
91
if (is_write) {
442
+#include "sysemu/blockdev.h"
92
- cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
443
+#include "hw/irq.h"
93
- buf, buf_bytes);
444
+#include "hw/sd/allwinner-sdhost.h"
94
+ dma_memory_read(&s->dma_as,
445
+#include "migration/vmstate.h"
95
+ (desc->addr & DESC_SIZE_MASK) + num_done,
446
+#include "trace.h"
96
+ buf, buf_bytes);
447
+
97
sdbus_write_data(&s->sdbus, buf, buf_bytes);
448
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
98
449
+#define AW_SDHOST_BUS(obj) \
99
/* Read from SD bus */
450
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
100
} else {
451
+
101
sdbus_read_data(&s->sdbus, buf, buf_bytes);
452
+/* SD Host register offsets */
102
- cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
453
+enum {
103
- buf, buf_bytes);
454
+ REG_SD_GCTL = 0x00, /* Global Control */
104
+ dma_memory_write(&s->dma_as,
455
+ REG_SD_CKCR = 0x04, /* Clock Control */
105
+ (desc->addr & DESC_SIZE_MASK) + num_done,
456
+ REG_SD_TMOR = 0x08, /* Timeout */
106
+ buf, buf_bytes);
457
+ REG_SD_BWDR = 0x0C, /* Bus Width */
107
}
458
+ REG_SD_BKSR = 0x10, /* Block Size */
108
num_done += buf_bytes;
459
+ REG_SD_BYCR = 0x14, /* Byte Count */
109
}
460
+ REG_SD_CMDR = 0x18, /* Command */
110
461
+ REG_SD_CAGR = 0x1C, /* Command Argument */
111
/* Clear hold flag and flush descriptor */
462
+ REG_SD_RESP0 = 0x20, /* Response Zero */
112
desc->status &= ~DESC_STATUS_HOLD;
463
+ REG_SD_RESP1 = 0x24, /* Response One */
113
- cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
464
+ REG_SD_RESP2 = 0x28, /* Response Two */
114
+ dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc));
465
+ REG_SD_RESP3 = 0x2C, /* Response Three */
115
466
+ REG_SD_IMKR = 0x30, /* Interrupt Mask */
116
return num_done;
467
+ REG_SD_MISR = 0x34, /* Masked Interrupt Status */
117
}
468
+ REG_SD_RISR = 0x38, /* Raw Interrupt Status */
118
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_allwinner_sdhost = {
469
+ REG_SD_STAR = 0x3C, /* Status */
119
}
470
+ REG_SD_FWLR = 0x40, /* FIFO Water Level */
120
};
471
+ REG_SD_FUNS = 0x44, /* FIFO Function Select */
121
472
+ REG_SD_DBGC = 0x50, /* Debug Enable */
122
+static Property allwinner_sdhost_properties[] = {
473
+ REG_SD_A12A = 0x58, /* Auto command 12 argument */
123
+ DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
474
+ REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
124
+ TYPE_MEMORY_REGION, MemoryRegion *),
475
+ REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
125
+ DEFINE_PROP_END_OF_LIST(),
476
+ REG_SD_HWRST = 0x78, /* Hardware Reset Register */
477
+ REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
478
+ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
479
+ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
480
+ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
481
+ REG_SD_THLDC = 0x100, /* Card Threshold Control */
482
+ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
483
+ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
484
+ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
485
+ REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
486
+ REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
487
+ REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
488
+ REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
489
+ REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
490
+ REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
491
+ REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
492
+ REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
493
+ REG_SD_FIFO = 0x200, /* Read/Write FIFO */
494
+};
126
+};
495
+
127
+
496
+/* SD Host register flags */
128
static void allwinner_sdhost_init(Object *obj)
497
+enum {
129
{
498
+ SD_GCTL_FIFO_AC_MOD = (1 << 31),
130
AwSdHostState *s = AW_SDHOST(obj);
499
+ SD_GCTL_DDR_MOD_SEL = (1 << 10),
131
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
500
+ SD_GCTL_CD_DBC_ENB = (1 << 8),
132
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
501
+ SD_GCTL_DMA_ENB = (1 << 5),
133
}
502
+ SD_GCTL_INT_ENB = (1 << 4),
134
503
+ SD_GCTL_DMA_RST = (1 << 2),
135
+static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
504
+ SD_GCTL_FIFO_RST = (1 << 1),
505
+ SD_GCTL_SOFT_RST = (1 << 0),
506
+};
507
+
508
+enum {
509
+ SD_CMDR_LOAD = (1 << 31),
510
+ SD_CMDR_CLKCHANGE = (1 << 21),
511
+ SD_CMDR_WRITE = (1 << 10),
512
+ SD_CMDR_AUTOSTOP = (1 << 12),
513
+ SD_CMDR_DATA = (1 << 9),
514
+ SD_CMDR_RESPONSE_LONG = (1 << 7),
515
+ SD_CMDR_RESPONSE = (1 << 6),
516
+ SD_CMDR_CMDID_MASK = (0x3f),
517
+};
518
+
519
+enum {
520
+ SD_RISR_CARD_REMOVE = (1 << 31),
521
+ SD_RISR_CARD_INSERT = (1 << 30),
522
+ SD_RISR_SDIO_INTR = (1 << 16),
523
+ SD_RISR_AUTOCMD_DONE = (1 << 14),
524
+ SD_RISR_DATA_COMPLETE = (1 << 3),
525
+ SD_RISR_CMD_COMPLETE = (1 << 2),
526
+ SD_RISR_NO_RESPONSE = (1 << 1),
527
+};
528
+
529
+enum {
530
+ SD_STAR_CARD_PRESENT = (1 << 8),
531
+};
532
+
533
+enum {
534
+ SD_IDST_INT_SUMMARY = (1 << 8),
535
+ SD_IDST_RECEIVE_IRQ = (1 << 1),
536
+ SD_IDST_TRANSMIT_IRQ = (1 << 0),
537
+ SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
538
+ SD_IDST_WR_MASK = (0x3ff),
539
+};
540
+
541
+/* SD Host register reset values */
542
+enum {
543
+ REG_SD_GCTL_RST = 0x00000300,
544
+ REG_SD_CKCR_RST = 0x0,
545
+ REG_SD_TMOR_RST = 0xFFFFFF40,
546
+ REG_SD_BWDR_RST = 0x0,
547
+ REG_SD_BKSR_RST = 0x00000200,
548
+ REG_SD_BYCR_RST = 0x00000200,
549
+ REG_SD_CMDR_RST = 0x0,
550
+ REG_SD_CAGR_RST = 0x0,
551
+ REG_SD_RESP_RST = 0x0,
552
+ REG_SD_IMKR_RST = 0x0,
553
+ REG_SD_MISR_RST = 0x0,
554
+ REG_SD_RISR_RST = 0x0,
555
+ REG_SD_STAR_RST = 0x00000100,
556
+ REG_SD_FWLR_RST = 0x000F0000,
557
+ REG_SD_FUNS_RST = 0x0,
558
+ REG_SD_DBGC_RST = 0x0,
559
+ REG_SD_A12A_RST = 0x0000FFFF,
560
+ REG_SD_NTSR_RST = 0x00000001,
561
+ REG_SD_SDBG_RST = 0x0,
562
+ REG_SD_HWRST_RST = 0x00000001,
563
+ REG_SD_DMAC_RST = 0x0,
564
+ REG_SD_DLBA_RST = 0x0,
565
+ REG_SD_IDST_RST = 0x0,
566
+ REG_SD_IDIE_RST = 0x0,
567
+ REG_SD_THLDC_RST = 0x0,
568
+ REG_SD_DSBD_RST = 0x0,
569
+ REG_SD_RES_CRC_RST = 0x0,
570
+ REG_SD_DATA_CRC_RST = 0x0,
571
+ REG_SD_CRC_STA_RST = 0x0,
572
+ REG_SD_FIFO_RST = 0x0,
573
+};
574
+
575
+/* Data transfer descriptor for DMA */
576
+typedef struct TransferDescriptor {
577
+ uint32_t status; /* Status flags */
578
+ uint32_t size; /* Data buffer size */
579
+ uint32_t addr; /* Data buffer address */
580
+ uint32_t next; /* Physical address of next descriptor */
581
+} TransferDescriptor;
582
+
583
+/* Data transfer descriptor flags */
584
+enum {
585
+ DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
586
+ DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
587
+ DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
588
+ DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
589
+ DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
590
+ DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
591
+ DESC_SIZE_MASK = (0xfffffffc)
592
+};
593
+
594
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
595
+{
596
+ uint32_t irq;
597
+
598
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
599
+ irq = s->irq_status & s->irq_mask;
600
+ } else {
601
+ irq = 0;
602
+ }
603
+
604
+ trace_allwinner_sdhost_update_irq(irq);
605
+ qemu_set_irq(s->irq, irq);
606
+}
607
+
608
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
609
+ uint32_t bytes)
610
+{
611
+ if (s->transfer_cnt > bytes) {
612
+ s->transfer_cnt -= bytes;
613
+ } else {
614
+ s->transfer_cnt = 0;
615
+ }
616
+
617
+ if (!s->transfer_cnt) {
618
+ s->irq_status |= SD_RISR_DATA_COMPLETE;
619
+ }
620
+}
621
+
622
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
623
+{
136
+{
624
+ AwSdHostState *s = AW_SDHOST(dev);
137
+ AwSdHostState *s = AW_SDHOST(dev);
625
+
138
+
626
+ trace_allwinner_sdhost_set_inserted(inserted);
139
+ if (!s->dma_mr) {
627
+
140
+ error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
628
+ if (inserted) {
629
+ s->irq_status |= SD_RISR_CARD_INSERT;
630
+ s->irq_status &= ~SD_RISR_CARD_REMOVE;
631
+ s->status |= SD_STAR_CARD_PRESENT;
632
+ } else {
633
+ s->irq_status &= ~SD_RISR_CARD_INSERT;
634
+ s->irq_status |= SD_RISR_CARD_REMOVE;
635
+ s->status &= ~SD_STAR_CARD_PRESENT;
636
+ }
637
+
638
+ allwinner_sdhost_update_irq(s);
639
+}
640
+
641
+static void allwinner_sdhost_send_command(AwSdHostState *s)
642
+{
643
+ SDRequest request;
644
+ uint8_t resp[16];
645
+ int rlen;
646
+
647
+ /* Auto clear load flag */
648
+ s->command &= ~SD_CMDR_LOAD;
649
+
650
+ /* Clock change does not actually interact with the SD bus */
651
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
652
+
653
+ /* Prepare request */
654
+ request.cmd = s->command & SD_CMDR_CMDID_MASK;
655
+ request.arg = s->command_arg;
656
+
657
+ /* Send request to SD bus */
658
+ rlen = sdbus_do_command(&s->sdbus, &request, resp);
659
+ if (rlen < 0) {
660
+ goto error;
661
+ }
662
+
663
+ /* If the command has a response, store it in the response registers */
664
+ if ((s->command & SD_CMDR_RESPONSE)) {
665
+ if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
666
+ s->response[0] = ldl_be_p(&resp[0]);
667
+ s->response[1] = s->response[2] = s->response[3] = 0;
668
+
669
+ } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
670
+ s->response[0] = ldl_be_p(&resp[12]);
671
+ s->response[1] = ldl_be_p(&resp[8]);
672
+ s->response[2] = ldl_be_p(&resp[4]);
673
+ s->response[3] = ldl_be_p(&resp[0]);
674
+ } else {
675
+ goto error;
676
+ }
677
+ }
678
+ }
679
+
680
+ /* Set interrupt status bits */
681
+ s->irq_status |= SD_RISR_CMD_COMPLETE;
682
+ return;
683
+
684
+error:
685
+ s->irq_status |= SD_RISR_NO_RESPONSE;
686
+}
687
+
688
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
689
+{
690
+ /*
691
+ * The stop command (CMD12) ensures the SD bus
692
+ * returns to the transfer state.
693
+ */
694
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
695
+ /* First save current command registers */
696
+ uint32_t saved_cmd = s->command;
697
+ uint32_t saved_arg = s->command_arg;
698
+
699
+ /* Prepare stop command (CMD12) */
700
+ s->command &= ~SD_CMDR_CMDID_MASK;
701
+ s->command |= 12; /* CMD12 */
702
+ s->command_arg = 0;
703
+
704
+ /* Put the command on SD bus */
705
+ allwinner_sdhost_send_command(s);
706
+
707
+ /* Restore command values */
708
+ s->command = saved_cmd;
709
+ s->command_arg = saved_arg;
710
+
711
+ /* Set IRQ status bit for automatic stop done */
712
+ s->irq_status |= SD_RISR_AUTOCMD_DONE;
713
+ }
714
+}
715
+
716
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
717
+ hwaddr desc_addr,
718
+ TransferDescriptor *desc,
719
+ bool is_write, uint32_t max_bytes)
720
+{
721
+ AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
722
+ uint32_t num_done = 0;
723
+ uint32_t num_bytes = max_bytes;
724
+ uint8_t buf[1024];
725
+
726
+ /* Read descriptor */
727
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
728
+ if (desc->size == 0) {
729
+ desc->size = klass->max_desc_size;
730
+ } else if (desc->size > klass->max_desc_size) {
731
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
732
+ " is out-of-bounds: %" PRIu32 " > %zu",
733
+ __func__, desc->size, klass->max_desc_size);
734
+ desc->size = klass->max_desc_size;
735
+ }
736
+ if (desc->size < num_bytes) {
737
+ num_bytes = desc->size;
738
+ }
739
+
740
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
741
+ is_write, max_bytes);
742
+
743
+ while (num_done < num_bytes) {
744
+ /* Try to completely fill the local buffer */
745
+ uint32_t buf_bytes = num_bytes - num_done;
746
+ if (buf_bytes > sizeof(buf)) {
747
+ buf_bytes = sizeof(buf);
748
+ }
749
+
750
+ /* Write to SD bus */
751
+ if (is_write) {
752
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
753
+ buf, buf_bytes);
754
+
755
+ for (uint32_t i = 0; i < buf_bytes; i++) {
756
+ sdbus_write_data(&s->sdbus, buf[i]);
757
+ }
758
+
759
+ /* Read from SD bus */
760
+ } else {
761
+ for (uint32_t i = 0; i < buf_bytes; i++) {
762
+ buf[i] = sdbus_read_data(&s->sdbus);
763
+ }
764
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
765
+ buf, buf_bytes);
766
+ }
767
+ num_done += buf_bytes;
768
+ }
769
+
770
+ /* Clear hold flag and flush descriptor */
771
+ desc->status &= ~DESC_STATUS_HOLD;
772
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
773
+
774
+ return num_done;
775
+}
776
+
777
+static void allwinner_sdhost_dma(AwSdHostState *s)
778
+{
779
+ TransferDescriptor desc;
780
+ hwaddr desc_addr = s->desc_base;
781
+ bool is_write = (s->command & SD_CMDR_WRITE);
782
+ uint32_t bytes_done = 0;
783
+
784
+ /* Check if DMA can be performed */
785
+ if (s->byte_count == 0 || s->block_size == 0 ||
786
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
787
+ return;
141
+ return;
788
+ }
142
+ }
789
+
143
+
790
+ /*
144
+ address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
791
+ * For read operations, data must be available on the SD bus
792
+ * If not, it is an error and we should not act at all
793
+ */
794
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
795
+ return;
796
+ }
797
+
798
+ /* Process the DMA descriptors until all data is copied */
799
+ while (s->byte_count > 0) {
800
+ bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
801
+ is_write, s->byte_count);
802
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
803
+
804
+ if (bytes_done <= s->byte_count) {
805
+ s->byte_count -= bytes_done;
806
+ } else {
807
+ s->byte_count = 0;
808
+ }
809
+
810
+ if (desc.status & DESC_STATUS_LAST) {
811
+ break;
812
+ } else {
813
+ desc_addr = desc.next;
814
+ }
815
+ }
816
+
817
+ /* Raise IRQ to signal DMA is completed */
818
+ s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
819
+
820
+ /* Update DMAC bits */
821
+ s->dmac_status |= SD_IDST_INT_SUMMARY;
822
+
823
+ if (is_write) {
824
+ s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
825
+ } else {
826
+ s->dmac_status |= SD_IDST_RECEIVE_IRQ;
827
+ }
828
+}
145
+}
829
+
146
+
830
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
147
static void allwinner_sdhost_reset(DeviceState *dev)
831
+ unsigned size)
148
{
832
+{
149
AwSdHostState *s = AW_SDHOST(dev);
833
+ AwSdHostState *s = AW_SDHOST(opaque);
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
834
+ uint32_t res = 0;
151
835
+
152
dc->reset = allwinner_sdhost_reset;
836
+ switch (offset) {
153
dc->vmsd = &vmstate_allwinner_sdhost;
837
+ case REG_SD_GCTL: /* Global Control */
154
+ dc->realize = allwinner_sdhost_realize;
838
+ res = s->global_ctl;
155
+ device_class_set_props(dc, allwinner_sdhost_properties);
839
+ break;
156
}
840
+ case REG_SD_CKCR: /* Clock Control */
157
841
+ res = s->clock_ctl;
158
static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
842
+ break;
843
+ case REG_SD_TMOR: /* Timeout */
844
+ res = s->timeout;
845
+ break;
846
+ case REG_SD_BWDR: /* Bus Width */
847
+ res = s->bus_width;
848
+ break;
849
+ case REG_SD_BKSR: /* Block Size */
850
+ res = s->block_size;
851
+ break;
852
+ case REG_SD_BYCR: /* Byte Count */
853
+ res = s->byte_count;
854
+ break;
855
+ case REG_SD_CMDR: /* Command */
856
+ res = s->command;
857
+ break;
858
+ case REG_SD_CAGR: /* Command Argument */
859
+ res = s->command_arg;
860
+ break;
861
+ case REG_SD_RESP0: /* Response Zero */
862
+ res = s->response[0];
863
+ break;
864
+ case REG_SD_RESP1: /* Response One */
865
+ res = s->response[1];
866
+ break;
867
+ case REG_SD_RESP2: /* Response Two */
868
+ res = s->response[2];
869
+ break;
870
+ case REG_SD_RESP3: /* Response Three */
871
+ res = s->response[3];
872
+ break;
873
+ case REG_SD_IMKR: /* Interrupt Mask */
874
+ res = s->irq_mask;
875
+ break;
876
+ case REG_SD_MISR: /* Masked Interrupt Status */
877
+ res = s->irq_status & s->irq_mask;
878
+ break;
879
+ case REG_SD_RISR: /* Raw Interrupt Status */
880
+ res = s->irq_status;
881
+ break;
882
+ case REG_SD_STAR: /* Status */
883
+ res = s->status;
884
+ break;
885
+ case REG_SD_FWLR: /* FIFO Water Level */
886
+ res = s->fifo_wlevel;
887
+ break;
888
+ case REG_SD_FUNS: /* FIFO Function Select */
889
+ res = s->fifo_func_sel;
890
+ break;
891
+ case REG_SD_DBGC: /* Debug Enable */
892
+ res = s->debug_enable;
893
+ break;
894
+ case REG_SD_A12A: /* Auto command 12 argument */
895
+ res = s->auto12_arg;
896
+ break;
897
+ case REG_SD_NTSR: /* SD NewTiming Set */
898
+ res = s->newtiming_set;
899
+ break;
900
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
901
+ res = s->newtiming_debug;
902
+ break;
903
+ case REG_SD_HWRST: /* Hardware Reset Register */
904
+ res = s->hardware_rst;
905
+ break;
906
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
907
+ res = s->dmac;
908
+ break;
909
+ case REG_SD_DLBA: /* Descriptor List Base Address */
910
+ res = s->desc_base;
911
+ break;
912
+ case REG_SD_IDST: /* Internal DMA Controller Status */
913
+ res = s->dmac_status;
914
+ break;
915
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
916
+ res = s->dmac_irq;
917
+ break;
918
+ case REG_SD_THLDC: /* Card Threshold Control */
919
+ res = s->card_threshold;
920
+ break;
921
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
922
+ res = s->startbit_detect;
923
+ break;
924
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
925
+ res = s->response_crc;
926
+ break;
927
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
928
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
929
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
930
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
931
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
932
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
933
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
934
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
935
+ res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
936
+ break;
937
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
938
+ res = s->status_crc;
939
+ break;
940
+ case REG_SD_FIFO: /* Read/Write FIFO */
941
+ if (sdbus_data_ready(&s->sdbus)) {
942
+ res = sdbus_read_data(&s->sdbus);
943
+ res |= sdbus_read_data(&s->sdbus) << 8;
944
+ res |= sdbus_read_data(&s->sdbus) << 16;
945
+ res |= sdbus_read_data(&s->sdbus) << 24;
946
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
947
+ allwinner_sdhost_auto_stop(s);
948
+ allwinner_sdhost_update_irq(s);
949
+ } else {
950
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
951
+ __func__);
952
+ }
953
+ break;
954
+ default:
955
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
956
+ HWADDR_PRIx"\n", __func__, offset);
957
+ res = 0;
958
+ break;
959
+ }
960
+
961
+ trace_allwinner_sdhost_read(offset, res, size);
962
+ return res;
963
+}
964
+
965
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
966
+ uint64_t value, unsigned size)
967
+{
968
+ AwSdHostState *s = AW_SDHOST(opaque);
969
+
970
+ trace_allwinner_sdhost_write(offset, value, size);
971
+
972
+ switch (offset) {
973
+ case REG_SD_GCTL: /* Global Control */
974
+ s->global_ctl = value;
975
+ s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
976
+ SD_GCTL_SOFT_RST);
977
+ allwinner_sdhost_update_irq(s);
978
+ break;
979
+ case REG_SD_CKCR: /* Clock Control */
980
+ s->clock_ctl = value;
981
+ break;
982
+ case REG_SD_TMOR: /* Timeout */
983
+ s->timeout = value;
984
+ break;
985
+ case REG_SD_BWDR: /* Bus Width */
986
+ s->bus_width = value;
987
+ break;
988
+ case REG_SD_BKSR: /* Block Size */
989
+ s->block_size = value;
990
+ break;
991
+ case REG_SD_BYCR: /* Byte Count */
992
+ s->byte_count = value;
993
+ s->transfer_cnt = value;
994
+ break;
995
+ case REG_SD_CMDR: /* Command */
996
+ s->command = value;
997
+ if (value & SD_CMDR_LOAD) {
998
+ allwinner_sdhost_send_command(s);
999
+ allwinner_sdhost_dma(s);
1000
+ allwinner_sdhost_auto_stop(s);
1001
+ }
1002
+ allwinner_sdhost_update_irq(s);
1003
+ break;
1004
+ case REG_SD_CAGR: /* Command Argument */
1005
+ s->command_arg = value;
1006
+ break;
1007
+ case REG_SD_RESP0: /* Response Zero */
1008
+ s->response[0] = value;
1009
+ break;
1010
+ case REG_SD_RESP1: /* Response One */
1011
+ s->response[1] = value;
1012
+ break;
1013
+ case REG_SD_RESP2: /* Response Two */
1014
+ s->response[2] = value;
1015
+ break;
1016
+ case REG_SD_RESP3: /* Response Three */
1017
+ s->response[3] = value;
1018
+ break;
1019
+ case REG_SD_IMKR: /* Interrupt Mask */
1020
+ s->irq_mask = value;
1021
+ allwinner_sdhost_update_irq(s);
1022
+ break;
1023
+ case REG_SD_MISR: /* Masked Interrupt Status */
1024
+ case REG_SD_RISR: /* Raw Interrupt Status */
1025
+ s->irq_status &= ~value;
1026
+ allwinner_sdhost_update_irq(s);
1027
+ break;
1028
+ case REG_SD_STAR: /* Status */
1029
+ s->status &= ~value;
1030
+ allwinner_sdhost_update_irq(s);
1031
+ break;
1032
+ case REG_SD_FWLR: /* FIFO Water Level */
1033
+ s->fifo_wlevel = value;
1034
+ break;
1035
+ case REG_SD_FUNS: /* FIFO Function Select */
1036
+ s->fifo_func_sel = value;
1037
+ break;
1038
+ case REG_SD_DBGC: /* Debug Enable */
1039
+ s->debug_enable = value;
1040
+ break;
1041
+ case REG_SD_A12A: /* Auto command 12 argument */
1042
+ s->auto12_arg = value;
1043
+ break;
1044
+ case REG_SD_NTSR: /* SD NewTiming Set */
1045
+ s->newtiming_set = value;
1046
+ break;
1047
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
1048
+ s->newtiming_debug = value;
1049
+ break;
1050
+ case REG_SD_HWRST: /* Hardware Reset Register */
1051
+ s->hardware_rst = value;
1052
+ break;
1053
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
1054
+ s->dmac = value;
1055
+ allwinner_sdhost_update_irq(s);
1056
+ break;
1057
+ case REG_SD_DLBA: /* Descriptor List Base Address */
1058
+ s->desc_base = value;
1059
+ break;
1060
+ case REG_SD_IDST: /* Internal DMA Controller Status */
1061
+ s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
1062
+ allwinner_sdhost_update_irq(s);
1063
+ break;
1064
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
1065
+ s->dmac_irq = value;
1066
+ allwinner_sdhost_update_irq(s);
1067
+ break;
1068
+ case REG_SD_THLDC: /* Card Threshold Control */
1069
+ s->card_threshold = value;
1070
+ break;
1071
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
1072
+ s->startbit_detect = value;
1073
+ break;
1074
+ case REG_SD_FIFO: /* Read/Write FIFO */
1075
+ sdbus_write_data(&s->sdbus, value & 0xff);
1076
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
1077
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
1078
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
1079
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
1080
+ allwinner_sdhost_auto_stop(s);
1081
+ allwinner_sdhost_update_irq(s);
1082
+ break;
1083
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
1084
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
1085
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
1086
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
1087
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
1088
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
1089
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
1090
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
1091
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
1092
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
1093
+ break;
1094
+ default:
1095
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
1096
+ HWADDR_PRIx"\n", __func__, offset);
1097
+ break;
1098
+ }
1099
+}
1100
+
1101
+static const MemoryRegionOps allwinner_sdhost_ops = {
1102
+ .read = allwinner_sdhost_read,
1103
+ .write = allwinner_sdhost_write,
1104
+ .endianness = DEVICE_NATIVE_ENDIAN,
1105
+ .valid = {
1106
+ .min_access_size = 4,
1107
+ .max_access_size = 4,
1108
+ },
1109
+ .impl.min_access_size = 4,
1110
+};
1111
+
1112
+static const VMStateDescription vmstate_allwinner_sdhost = {
1113
+ .name = "allwinner-sdhost",
1114
+ .version_id = 1,
1115
+ .minimum_version_id = 1,
1116
+ .fields = (VMStateField[]) {
1117
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
1118
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
1119
+ VMSTATE_UINT32(timeout, AwSdHostState),
1120
+ VMSTATE_UINT32(bus_width, AwSdHostState),
1121
+ VMSTATE_UINT32(block_size, AwSdHostState),
1122
+ VMSTATE_UINT32(byte_count, AwSdHostState),
1123
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
1124
+ VMSTATE_UINT32(command, AwSdHostState),
1125
+ VMSTATE_UINT32(command_arg, AwSdHostState),
1126
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
1127
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
1128
+ VMSTATE_UINT32(irq_status, AwSdHostState),
1129
+ VMSTATE_UINT32(status, AwSdHostState),
1130
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
1131
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
1132
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
1133
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
1134
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
1135
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
1136
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
1137
+ VMSTATE_UINT32(dmac, AwSdHostState),
1138
+ VMSTATE_UINT32(desc_base, AwSdHostState),
1139
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
1140
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
1141
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
1142
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
1143
+ VMSTATE_UINT32(response_crc, AwSdHostState),
1144
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
1145
+ VMSTATE_UINT32(status_crc, AwSdHostState),
1146
+ VMSTATE_END_OF_LIST()
1147
+ }
1148
+};
1149
+
1150
+static void allwinner_sdhost_init(Object *obj)
1151
+{
1152
+ AwSdHostState *s = AW_SDHOST(obj);
1153
+
1154
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1155
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
1156
+
1157
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
1158
+ TYPE_AW_SDHOST, 4 * KiB);
1159
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
1160
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
1161
+}
1162
+
1163
+static void allwinner_sdhost_reset(DeviceState *dev)
1164
+{
1165
+ AwSdHostState *s = AW_SDHOST(dev);
1166
+
1167
+ s->global_ctl = REG_SD_GCTL_RST;
1168
+ s->clock_ctl = REG_SD_CKCR_RST;
1169
+ s->timeout = REG_SD_TMOR_RST;
1170
+ s->bus_width = REG_SD_BWDR_RST;
1171
+ s->block_size = REG_SD_BKSR_RST;
1172
+ s->byte_count = REG_SD_BYCR_RST;
1173
+ s->transfer_cnt = 0;
1174
+
1175
+ s->command = REG_SD_CMDR_RST;
1176
+ s->command_arg = REG_SD_CAGR_RST;
1177
+
1178
+ for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
1179
+ s->response[i] = REG_SD_RESP_RST;
1180
+ }
1181
+
1182
+ s->irq_mask = REG_SD_IMKR_RST;
1183
+ s->irq_status = REG_SD_RISR_RST;
1184
+ s->status = REG_SD_STAR_RST;
1185
+
1186
+ s->fifo_wlevel = REG_SD_FWLR_RST;
1187
+ s->fifo_func_sel = REG_SD_FUNS_RST;
1188
+ s->debug_enable = REG_SD_DBGC_RST;
1189
+ s->auto12_arg = REG_SD_A12A_RST;
1190
+ s->newtiming_set = REG_SD_NTSR_RST;
1191
+ s->newtiming_debug = REG_SD_SDBG_RST;
1192
+ s->hardware_rst = REG_SD_HWRST_RST;
1193
+ s->dmac = REG_SD_DMAC_RST;
1194
+ s->desc_base = REG_SD_DLBA_RST;
1195
+ s->dmac_status = REG_SD_IDST_RST;
1196
+ s->dmac_irq = REG_SD_IDIE_RST;
1197
+ s->card_threshold = REG_SD_THLDC_RST;
1198
+ s->startbit_detect = REG_SD_DSBD_RST;
1199
+ s->response_crc = REG_SD_RES_CRC_RST;
1200
+
1201
+ for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
1202
+ s->data_crc[i] = REG_SD_DATA_CRC_RST;
1203
+ }
1204
+
1205
+ s->status_crc = REG_SD_CRC_STA_RST;
1206
+}
1207
+
1208
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
1209
+{
1210
+ SDBusClass *sbc = SD_BUS_CLASS(klass);
1211
+
1212
+ sbc->set_inserted = allwinner_sdhost_set_inserted;
1213
+}
1214
+
1215
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
1216
+{
1217
+ DeviceClass *dc = DEVICE_CLASS(klass);
1218
+
1219
+ dc->reset = allwinner_sdhost_reset;
1220
+ dc->vmsd = &vmstate_allwinner_sdhost;
1221
+}
1222
+
1223
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
1224
+{
1225
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1226
+ sc->max_desc_size = 8 * KiB;
1227
+}
1228
+
1229
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
1230
+{
1231
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1232
+ sc->max_desc_size = 64 * KiB;
1233
+}
1234
+
1235
+static TypeInfo allwinner_sdhost_info = {
1236
+ .name = TYPE_AW_SDHOST,
1237
+ .parent = TYPE_SYS_BUS_DEVICE,
1238
+ .instance_init = allwinner_sdhost_init,
1239
+ .instance_size = sizeof(AwSdHostState),
1240
+ .class_init = allwinner_sdhost_class_init,
1241
+ .class_size = sizeof(AwSdHostClass),
1242
+ .abstract = true,
1243
+};
1244
+
1245
+static const TypeInfo allwinner_sdhost_sun4i_info = {
1246
+ .name = TYPE_AW_SDHOST_SUN4I,
1247
+ .parent = TYPE_AW_SDHOST,
1248
+ .class_init = allwinner_sdhost_sun4i_class_init,
1249
+};
1250
+
1251
+static const TypeInfo allwinner_sdhost_sun5i_info = {
1252
+ .name = TYPE_AW_SDHOST_SUN5I,
1253
+ .parent = TYPE_AW_SDHOST,
1254
+ .class_init = allwinner_sdhost_sun5i_class_init,
1255
+};
1256
+
1257
+static const TypeInfo allwinner_sdhost_bus_info = {
1258
+ .name = TYPE_AW_SDHOST_BUS,
1259
+ .parent = TYPE_SD_BUS,
1260
+ .instance_size = sizeof(SDBus),
1261
+ .class_init = allwinner_sdhost_bus_class_init,
1262
+};
1263
+
1264
+static void allwinner_sdhost_register_types(void)
1265
+{
1266
+ type_register_static(&allwinner_sdhost_info);
1267
+ type_register_static(&allwinner_sdhost_sun4i_info);
1268
+ type_register_static(&allwinner_sdhost_sun5i_info);
1269
+ type_register_static(&allwinner_sdhost_bus_info);
1270
+}
1271
+
1272
+type_init(allwinner_sdhost_register_types)
1273
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1274
index XXXXXXX..XXXXXXX 100644
1275
--- a/hw/arm/Kconfig
1276
+++ b/hw/arm/Kconfig
1277
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
1278
select UNIMP
1279
select USB_OHCI
1280
select USB_EHCI_SYSBUS
1281
+ select SD
1282
1283
config RASPI
1284
bool
1285
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
1286
index XXXXXXX..XXXXXXX 100644
1287
--- a/hw/sd/trace-events
1288
+++ b/hw/sd/trace-events
1289
@@ -XXX,XX +XXX,XX @@
1290
# See docs/devel/tracing.txt for syntax documentation.
1291
1292
+# allwinner-sdhost.c
1293
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
1294
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32
1295
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1296
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1297
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
1298
+
1299
# bcm2835_sdhost.c
1300
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1301
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1302
--
159
--
1303
2.20.1
160
2.20.1
1304
161
1305
162
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
3
Allow the device to execute the DMA transfers in a different
4
which provides 10M/100M/1000M Ethernet connectivity. This commit
4
AddressSpace.
5
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
5
6
including emulation for the following functionality:
6
The H3 SoC keeps using the system_memory address space,
7
7
but via the proper dma_memory_access() API.
8
* DMA transfers
8
9
* MII interface
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
* Transmit CRC calculation
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20200814122907.27732-1-f4bug@amsat.org
14
Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
15
---
17
hw/net/Makefile.objs | 1 +
16
include/hw/net/allwinner-sun8i-emac.h | 6 ++++
18
include/hw/arm/allwinner-h3.h | 3 +
17
hw/arm/allwinner-h3.c | 2 ++
19
include/hw/net/allwinner-sun8i-emac.h | 99 +++
18
hw/net/allwinner-sun8i-emac.c | 46 +++++++++++++++++----------
20
hw/arm/allwinner-h3.c | 16 +-
19
3 files changed, 38 insertions(+), 16 deletions(-)
21
hw/arm/orangepi.c | 3 +
20
22
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
21
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
23
hw/arm/Kconfig | 1 +
24
hw/net/Kconfig | 3 +
25
hw/net/trace-events | 10 +
26
9 files changed, 1006 insertions(+), 1 deletion(-)
27
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
28
create mode 100644 hw/net/allwinner-sun8i-emac.c
29
30
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
31
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/net/Makefile.objs
23
--- a/include/hw/net/allwinner-sun8i-emac.h
33
+++ b/hw/net/Makefile.objs
34
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
35
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
36
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
37
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
38
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
39
common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
40
41
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
42
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/include/hw/arm/allwinner-h3.h
45
+++ b/include/hw/arm/allwinner-h3.h
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "hw/misc/allwinner-sid.h"
49
#include "hw/sd/allwinner-sdhost.h"
50
+#include "hw/net/allwinner-sun8i-emac.h"
51
#include "target/arm/cpu.h"
52
53
/**
54
@@ -XXX,XX +XXX,XX @@ enum {
55
AW_H3_UART1,
56
AW_H3_UART2,
57
AW_H3_UART3,
58
+ AW_H3_EMAC,
59
AW_H3_GIC_DIST,
60
AW_H3_GIC_CPU,
61
AW_H3_GIC_HYP,
62
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
63
AwH3SysCtrlState sysctrl;
64
AwSidState sid;
65
AwSdHostState mmc0;
66
+ AwSun8iEmacState emac;
67
GICState gic;
68
MemoryRegion sram_a1;
69
MemoryRegion sram_a2;
70
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
71
new file mode 100644
72
index XXXXXXX..XXXXXXX
73
--- /dev/null
74
+++ b/include/hw/net/allwinner-sun8i-emac.h
24
+++ b/include/hw/net/allwinner-sun8i-emac.h
75
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSun8iEmacState {
76
+/*
26
/** Interrupt output signal to notify CPU */
77
+ * Allwinner Sun8i Ethernet MAC emulation
27
qemu_irq irq;
78
+ *
28
79
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
29
+ /** Memory region where DMA transfers are done */
80
+ *
30
+ MemoryRegion *dma_mr;
81
+ * This program is free software: you can redistribute it and/or modify
31
+
82
+ * it under the terms of the GNU General Public License as published by
32
+ /** Address space used internally for DMA transfers */
83
+ * the Free Software Foundation, either version 2 of the License, or
33
+ AddressSpace dma_as;
84
+ * (at your option) any later version.
34
+
85
+ *
35
/** Generic Network Interface Controller (NIC) for networking API */
86
+ * This program is distributed in the hope that it will be useful,
36
NICState *nic;
87
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
37
88
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89
+ * GNU General Public License for more details.
90
+ *
91
+ * You should have received a copy of the GNU General Public License
92
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
93
+ */
94
+
95
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
96
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
97
+
98
+#include "qom/object.h"
99
+#include "net/net.h"
100
+#include "hw/sysbus.h"
101
+
102
+/**
103
+ * Object model
104
+ * @{
105
+ */
106
+
107
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
108
+#define AW_SUN8I_EMAC(obj) \
109
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
110
+
111
+/** @} */
112
+
113
+/**
114
+ * Allwinner Sun8i EMAC object instance state
115
+ */
116
+typedef struct AwSun8iEmacState {
117
+ /*< private >*/
118
+ SysBusDevice parent_obj;
119
+ /*< public >*/
120
+
121
+ /** Maps I/O registers in physical memory */
122
+ MemoryRegion iomem;
123
+
124
+ /** Interrupt output signal to notify CPU */
125
+ qemu_irq irq;
126
+
127
+ /** Generic Network Interface Controller (NIC) for networking API */
128
+ NICState *nic;
129
+
130
+ /** Generic Network Interface Controller (NIC) configuration */
131
+ NICConf conf;
132
+
133
+ /**
134
+ * @name Media Independent Interface (MII)
135
+ * @{
136
+ */
137
+
138
+ uint8_t mii_phy_addr; /**< PHY address */
139
+ uint32_t mii_cr; /**< Control */
140
+ uint32_t mii_st; /**< Status */
141
+ uint32_t mii_adv; /**< Advertised Abilities */
142
+
143
+ /** @} */
144
+
145
+ /**
146
+ * @name Hardware Registers
147
+ * @{
148
+ */
149
+
150
+ uint32_t basic_ctl0; /**< Basic Control 0 */
151
+ uint32_t basic_ctl1; /**< Basic Control 1 */
152
+ uint32_t int_en; /**< Interrupt Enable */
153
+ uint32_t int_sta; /**< Interrupt Status */
154
+ uint32_t frm_flt; /**< Receive Frame Filter */
155
+
156
+ uint32_t rx_ctl0; /**< Receive Control 0 */
157
+ uint32_t rx_ctl1; /**< Receive Control 1 */
158
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
159
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
160
+
161
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
162
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
163
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
164
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
165
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
166
+
167
+ uint32_t mii_cmd; /**< Management Interface Command */
168
+ uint32_t mii_data; /**< Management Interface Data */
169
+
170
+ /** @} */
171
+
172
+} AwSun8iEmacState;
173
+
174
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
175
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
38
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
176
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/arm/allwinner-h3.c
40
--- a/hw/arm/allwinner-h3.c
178
+++ b/hw/arm/allwinner-h3.c
41
+++ b/hw/arm/allwinner-h3.c
179
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
180
[AW_H3_UART1] = 0x01c28400,
181
[AW_H3_UART2] = 0x01c28800,
182
[AW_H3_UART3] = 0x01c28c00,
183
+ [AW_H3_EMAC] = 0x01c30000,
184
[AW_H3_GIC_DIST] = 0x01c81000,
185
[AW_H3_GIC_CPU] = 0x01c82000,
186
[AW_H3_GIC_HYP] = 0x01c84000,
187
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
188
{ "twi1", 0x01c2b000, 1 * KiB },
189
{ "twi2", 0x01c2b400, 1 * KiB },
190
{ "scr", 0x01c2c400, 1 * KiB },
191
- { "emac", 0x01c30000, 64 * KiB },
192
{ "gpu", 0x01c40000, 64 * KiB },
193
{ "hstmr", 0x01c60000, 4 * KiB },
194
{ "dramcom", 0x01c62000, 4 * KiB },
195
@@ -XXX,XX +XXX,XX @@ enum {
196
AW_H3_GIC_SPI_OHCI2 = 77,
197
AW_H3_GIC_SPI_EHCI3 = 78,
198
AW_H3_GIC_SPI_OHCI3 = 79,
199
+ AW_H3_GIC_SPI_EMAC = 82
200
};
201
202
/* Allwinner H3 general constants */
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
206
TYPE_AW_SDHOST_SUN5I);
207
+
208
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
209
+ TYPE_AW_SUN8I_EMAC);
210
}
211
212
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
213
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
42
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
214
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
43
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
215
"sd-bus", &error_abort);
44
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
216
45
}
217
+ /* EMAC */
46
+ object_property_set_link(OBJECT(&s->emac), "dma-memory",
218
+ if (nd_table[0].used) {
47
+ OBJECT(get_system_memory()), &error_fatal);
219
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
48
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
220
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
221
+ }
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
222
+ qdev_init_nofail(DEVICE(&s->emac));
51
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
224
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
225
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
226
+
227
/* Universal Serial Bus */
228
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
229
qdev_get_gpio_in(DEVICE(&s->gic),
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
53
--- a/hw/net/allwinner-sun8i-emac.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
warn_report("Security Identifier value does not include H3 prefix");
236
}
237
238
+ /* Setup EMAC properties */
239
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
240
+
241
/* Mark H3 object realized */
242
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
243
244
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
245
new file mode 100644
246
index XXXXXXX..XXXXXXX
247
--- /dev/null
248
+++ b/hw/net/allwinner-sun8i-emac.c
54
+++ b/hw/net/allwinner-sun8i-emac.c
249
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@
250
+/*
56
251
+ * Allwinner Sun8i Ethernet MAC emulation
57
#include "qemu/osdep.h"
252
+ *
58
#include "qemu/units.h"
253
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
59
+#include "qapi/error.h"
254
+ *
60
#include "hw/sysbus.h"
255
+ * This program is free software: you can redistribute it and/or modify
61
#include "migration/vmstate.h"
256
+ * it under the terms of the GNU General Public License as published by
62
#include "net/net.h"
257
+ * the Free Software Foundation, either version 2 of the License, or
63
@@ -XXX,XX +XXX,XX @@
258
+ * (at your option) any later version.
64
#include "net/checksum.h"
259
+ *
65
#include "qemu/module.h"
260
+ * This program is distributed in the hope that it will be useful,
66
#include "exec/cpu-common.h"
261
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
67
+#include "sysemu/dma.h"
262
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
68
#include "hw/net/allwinner-sun8i-emac.h"
263
+ * GNU General Public License for more details.
69
264
+ *
70
/* EMAC register offsets */
265
+ * You should have received a copy of the GNU General Public License
71
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
266
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
72
qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
267
+ */
73
}
268
+
74
269
+#include "qemu/osdep.h"
75
-static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
270
+#include "qemu/units.h"
76
+static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
271
+#include "hw/sysbus.h"
77
+ FrameDescriptor *desc,
272
+#include "migration/vmstate.h"
78
size_t min_size)
273
+#include "net/net.h"
79
{
274
+#include "hw/irq.h"
80
uint32_t paddr = desc->next;
275
+#include "hw/qdev-properties.h"
81
276
+#include "qemu/log.h"
82
- cpu_physical_memory_read(paddr, desc, sizeof(*desc));
277
+#include "trace.h"
83
+ dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
278
+#include "net/checksum.h"
84
279
+#include "qemu/module.h"
85
if ((desc->status & DESC_STATUS_CTL) &&
280
+#include "exec/cpu-common.h"
86
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
281
+#include "hw/net/allwinner-sun8i-emac.h"
87
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
282
+
88
}
283
+/* EMAC register offsets */
89
}
284
+enum {
90
285
+ REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */
91
-static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
286
+ REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */
92
+static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
287
+ REG_INT_STA = 0x0008, /* Interrupt Status */
93
+ FrameDescriptor *desc,
288
+ REG_INT_EN = 0x000C, /* Interrupt Enable */
94
uint32_t start_addr,
289
+ REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
95
size_t min_size)
290
+ REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
96
{
291
+ REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
97
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
292
+ REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
98
293
+ REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
99
/* Note that the list is a cycle. Last entry points back to the head. */
294
+ REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
100
while (desc_addr != 0) {
295
+ REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
101
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
296
+ REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
102
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
297
+ REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
103
298
+ REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
104
if ((desc->status & DESC_STATUS_CTL) &&
299
+ REG_MII_CMD = 0x0048, /* Management Interface Command */
105
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
300
+ REG_MII_DATA = 0x004C, /* Management Interface Data */
106
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
301
+ REG_ADDR_HIGH = 0x0050, /* MAC Address High */
107
FrameDescriptor *desc,
302
+ REG_ADDR_LOW = 0x0054, /* MAC Address Low */
108
size_t min_size)
303
+ REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
109
{
304
+ REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
110
- return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
305
+ REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
111
+ return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
306
+ REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
112
}
307
+ REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
113
308
+ REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
114
static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
309
+ REG_RGMII_STA = 0x00D0, /* RGMII Status */
115
FrameDescriptor *desc,
310
+};
116
size_t min_size)
311
+
117
{
312
+/* EMAC register flags */
118
- return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
313
+enum {
119
+ return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
314
+ BASIC_CTL0_100Mbps = (0b11 << 2),
120
}
315
+ BASIC_CTL0_FD = (1 << 0),
121
316
+ BASIC_CTL1_SOFTRST = (1 << 0),
122
-static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
317
+};
123
+static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
318
+
124
+ FrameDescriptor *desc,
319
+enum {
125
uint32_t phys_addr)
320
+ INT_STA_RGMII_LINK = (1 << 16),
126
{
321
+ INT_STA_RX_EARLY = (1 << 13),
127
- cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
322
+ INT_STA_RX_OVERFLOW = (1 << 12),
128
+ dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
323
+ INT_STA_RX_TIMEOUT = (1 << 11),
129
}
324
+ INT_STA_RX_DMA_STOP = (1 << 10),
130
325
+ INT_STA_RX_BUF_UA = (1 << 9),
131
static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
326
+ INT_STA_RX = (1 << 8),
132
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
327
+ INT_STA_TX_EARLY = (1 << 5),
133
<< RX_DESC_STATUS_FRM_LEN_SHIFT;
328
+ INT_STA_TX_UNDERFLOW = (1 << 4),
134
}
329
+ INT_STA_TX_TIMEOUT = (1 << 3),
135
330
+ INT_STA_TX_BUF_UA = (1 << 2),
136
- cpu_physical_memory_write(desc.addr, buf, desc_bytes);
331
+ INT_STA_TX_DMA_STOP = (1 << 1),
137
- allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
332
+ INT_STA_TX = (1 << 0),
138
+ dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
333
+};
139
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
334
+
140
trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
335
+enum {
141
desc_bytes);
336
+ INT_EN_RX_EARLY = (1 << 13),
142
337
+ INT_EN_RX_OVERFLOW = (1 << 12),
143
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
338
+ INT_EN_RX_TIMEOUT = (1 << 11),
144
bytes_left -= desc_bytes;
339
+ INT_EN_RX_DMA_STOP = (1 << 10),
145
340
+ INT_EN_RX_BUF_UA = (1 << 9),
146
/* Move to the next descriptor */
341
+ INT_EN_RX = (1 << 8),
147
- s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
342
+ INT_EN_TX_EARLY = (1 << 5),
148
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
343
+ INT_EN_TX_UNDERFLOW = (1 << 4),
149
if (!s->rx_desc_curr) {
344
+ INT_EN_TX_TIMEOUT = (1 << 3),
150
/* Not enough buffer space available */
345
+ INT_EN_TX_BUF_UA = (1 << 2),
151
s->int_sta |= INT_STA_RX_BUF_UA;
346
+ INT_EN_TX_DMA_STOP = (1 << 1),
152
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
347
+ INT_EN_TX = (1 << 0),
153
desc.status |= TX_DESC_STATUS_LENGTH_ERR;
348
+};
154
break;
349
+
155
}
350
+enum {
156
- cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
351
+ TX_CTL0_TX_EN = (1 << 31),
157
+ dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
352
+ TX_CTL1_TX_DMA_START = (1 << 31),
158
packet_bytes += bytes;
353
+ TX_CTL1_TX_DMA_EN = (1 << 30),
159
desc.status &= ~DESC_STATUS_CTL;
354
+ TX_CTL1_TX_FLUSH = (1 << 0),
160
- allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
355
+};
161
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
356
+
162
357
+enum {
163
/* After the last descriptor, send the packet */
358
+ RX_CTL0_RX_EN = (1 << 31),
164
if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
359
+ RX_CTL0_STRIP_FCS = (1 << 28),
165
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
360
+ RX_CTL0_CRC_IPV4 = (1 << 27),
166
packet_bytes = 0;
361
+};
167
transmitted++;
362
+
168
}
363
+enum {
169
- s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
364
+ RX_CTL1_RX_DMA_START = (1 << 31),
170
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
365
+ RX_CTL1_RX_DMA_EN = (1 << 30),
171
}
366
+ RX_CTL1_RX_MD = (1 << 1),
172
367
+};
173
/* Raise transmit completed interrupt */
368
+
174
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
369
+enum {
175
break;
370
+ RX_FRM_FLT_DIS_ADDR = (1 << 31),
176
case REG_TX_CUR_BUF: /* Transmit Current Buffer */
371
+};
177
if (s->tx_desc_curr != 0) {
372
+
178
- cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
373
+enum {
179
+ dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
374
+ MII_CMD_PHY_ADDR_SHIFT = (12),
180
value = desc.addr;
375
+ MII_CMD_PHY_ADDR_MASK = (0xf000),
181
} else {
376
+ MII_CMD_PHY_REG_SHIFT = (4),
182
value = 0;
377
+ MII_CMD_PHY_REG_MASK = (0xf0),
183
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
378
+ MII_CMD_PHY_RW = (1 << 1),
184
break;
379
+ MII_CMD_PHY_BUSY = (1 << 0),
185
case REG_RX_CUR_BUF: /* Receive Current Buffer */
380
+};
186
if (s->rx_desc_curr != 0) {
381
+
187
- cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
382
+enum {
188
+ dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
383
+ TX_DMA_STA_STOP = (0b000),
189
value = desc.addr;
384
+ TX_DMA_STA_RUN_FETCH = (0b001),
190
} else {
385
+ TX_DMA_STA_WAIT_STA = (0b010),
191
value = 0;
386
+};
192
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
387
+
193
{
388
+enum {
194
AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
389
+ RX_DMA_STA_STOP = (0b000),
195
390
+ RX_DMA_STA_RUN_FETCH = (0b001),
196
+ if (!s->dma_mr) {
391
+ RX_DMA_STA_WAIT_FRM = (0b011),
197
+ error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set");
392
+};
393
+
394
+/* EMAC register reset values */
395
+enum {
396
+ REG_BASIC_CTL_1_RST = 0x08000000,
397
+};
398
+
399
+/* EMAC constants */
400
+enum {
401
+ AW_SUN8I_EMAC_MIN_PKT_SZ = 64
402
+};
403
+
404
+/* Transmit/receive frame descriptor */
405
+typedef struct FrameDescriptor {
406
+ uint32_t status;
407
+ uint32_t status2;
408
+ uint32_t addr;
409
+ uint32_t next;
410
+} FrameDescriptor;
411
+
412
+/* Frame descriptor flags */
413
+enum {
414
+ DESC_STATUS_CTL = (1 << 31),
415
+ DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
416
+};
417
+
418
+/* Transmit frame descriptor flags */
419
+enum {
420
+ TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
421
+ TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
422
+ TX_DESC_STATUS2_LAST_DESC = (1 << 30),
423
+ TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
424
+};
425
+
426
+/* Receive frame descriptor flags */
427
+enum {
428
+ RX_DESC_STATUS_FIRST_DESC = (1 << 9),
429
+ RX_DESC_STATUS_LAST_DESC = (1 << 8),
430
+ RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
431
+ RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
432
+ RX_DESC_STATUS_NO_BUF = (1 << 14),
433
+ RX_DESC_STATUS_HEADER_ERR = (1 << 7),
434
+ RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
435
+ RX_DESC_STATUS_CRC_ERR = (1 << 1),
436
+ RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
437
+ RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
438
+};
439
+
440
+/* MII register offsets */
441
+enum {
442
+ MII_REG_CR = (0x0), /* Control */
443
+ MII_REG_ST = (0x1), /* Status */
444
+ MII_REG_ID_HIGH = (0x2), /* Identifier High */
445
+ MII_REG_ID_LOW = (0x3), /* Identifier Low */
446
+ MII_REG_ADV = (0x4), /* Advertised abilities */
447
+ MII_REG_LPA = (0x5), /* Link partner abilities */
448
+};
449
+
450
+/* MII register flags */
451
+enum {
452
+ MII_REG_CR_RESET = (1 << 15),
453
+ MII_REG_CR_POWERDOWN = (1 << 11),
454
+ MII_REG_CR_10Mbit = (0),
455
+ MII_REG_CR_100Mbit = (1 << 13),
456
+ MII_REG_CR_1000Mbit = (1 << 6),
457
+ MII_REG_CR_AUTO_NEG = (1 << 12),
458
+ MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
459
+ MII_REG_CR_FULLDUPLEX = (1 << 8),
460
+};
461
+
462
+enum {
463
+ MII_REG_ST_100BASE_T4 = (1 << 15),
464
+ MII_REG_ST_100BASE_X_FD = (1 << 14),
465
+ MII_REG_ST_100BASE_X_HD = (1 << 13),
466
+ MII_REG_ST_10_FD = (1 << 12),
467
+ MII_REG_ST_10_HD = (1 << 11),
468
+ MII_REG_ST_100BASE_T2_FD = (1 << 10),
469
+ MII_REG_ST_100BASE_T2_HD = (1 << 9),
470
+ MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
471
+ MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
472
+ MII_REG_ST_LINK_UP = (1 << 2),
473
+};
474
+
475
+enum {
476
+ MII_REG_LPA_10_HD = (1 << 5),
477
+ MII_REG_LPA_10_FD = (1 << 6),
478
+ MII_REG_LPA_100_HD = (1 << 7),
479
+ MII_REG_LPA_100_FD = (1 << 8),
480
+ MII_REG_LPA_PAUSE = (1 << 10),
481
+ MII_REG_LPA_ASYMPAUSE = (1 << 11),
482
+};
483
+
484
+/* MII constants */
485
+enum {
486
+ MII_PHY_ID_HIGH = 0x0044,
487
+ MII_PHY_ID_LOW = 0x1400,
488
+};
489
+
490
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
491
+ bool link_active)
492
+{
493
+ if (link_active) {
494
+ s->mii_st |= MII_REG_ST_LINK_UP;
495
+ } else {
496
+ s->mii_st &= ~MII_REG_ST_LINK_UP;
497
+ }
498
+}
499
+
500
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
501
+ bool link_active)
502
+{
503
+ s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
504
+ MII_REG_CR_FULLDUPLEX;
505
+ s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
506
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
507
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
508
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
509
+ s->mii_adv = 0;
510
+
511
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
512
+}
513
+
514
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
515
+{
516
+ uint8_t addr, reg;
517
+
518
+ addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
519
+ reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
520
+
521
+ if (addr != s->mii_phy_addr) {
522
+ return;
198
+ return;
523
+ }
199
+ }
524
+
200
+
525
+ /* Read or write a PHY register? */
201
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
526
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
202
+
527
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
203
qemu_macaddr_default_if_unset(&s->conf.macaddr);
528
+
204
s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
529
+ switch (reg) {
205
object_get_typename(OBJECT(dev)), dev->id, s);
530
+ case MII_REG_CR:
206
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
531
+ if (s->mii_data & MII_REG_CR_RESET) {
207
static Property allwinner_sun8i_emac_properties[] = {
532
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
208
DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
533
+ MII_REG_ST_LINK_UP);
209
DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
534
+ } else {
210
+ DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr,
535
+ s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
211
+ TYPE_MEMORY_REGION, MemoryRegion *),
536
+ MII_REG_CR_AUTO_NEG_RESTART);
212
DEFINE_PROP_END_OF_LIST(),
537
+ }
213
};
538
+ break;
214
539
+ case MII_REG_ADV:
540
+ s->mii_adv = s->mii_data;
541
+ break;
542
+ case MII_REG_ID_HIGH:
543
+ case MII_REG_ID_LOW:
544
+ case MII_REG_LPA:
545
+ break;
546
+ default:
547
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
548
+ "unknown MII register 0x%x\n", reg);
549
+ break;
550
+ }
551
+ } else {
552
+ switch (reg) {
553
+ case MII_REG_CR:
554
+ s->mii_data = s->mii_cr;
555
+ break;
556
+ case MII_REG_ST:
557
+ s->mii_data = s->mii_st;
558
+ break;
559
+ case MII_REG_ID_HIGH:
560
+ s->mii_data = MII_PHY_ID_HIGH;
561
+ break;
562
+ case MII_REG_ID_LOW:
563
+ s->mii_data = MII_PHY_ID_LOW;
564
+ break;
565
+ case MII_REG_ADV:
566
+ s->mii_data = s->mii_adv;
567
+ break;
568
+ case MII_REG_LPA:
569
+ s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
570
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
571
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
572
+ break;
573
+ default:
574
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
575
+ "unknown MII register 0x%x\n", reg);
576
+ s->mii_data = 0;
577
+ break;
578
+ }
579
+
580
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
581
+ }
582
+}
583
+
584
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
585
+{
586
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
587
+}
588
+
589
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
590
+ size_t min_size)
591
+{
592
+ uint32_t paddr = desc->next;
593
+
594
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
595
+
596
+ if ((desc->status & DESC_STATUS_CTL) &&
597
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
598
+ return paddr;
599
+ } else {
600
+ return 0;
601
+ }
602
+}
603
+
604
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
605
+ uint32_t start_addr,
606
+ size_t min_size)
607
+{
608
+ uint32_t desc_addr = start_addr;
609
+
610
+ /* Note that the list is a cycle. Last entry points back to the head. */
611
+ while (desc_addr != 0) {
612
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
613
+
614
+ if ((desc->status & DESC_STATUS_CTL) &&
615
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
616
+ return desc_addr;
617
+ } else if (desc->next == start_addr) {
618
+ break;
619
+ } else {
620
+ desc_addr = desc->next;
621
+ }
622
+ }
623
+
624
+ return 0;
625
+}
626
+
627
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
628
+ FrameDescriptor *desc,
629
+ size_t min_size)
630
+{
631
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
632
+}
633
+
634
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
635
+ FrameDescriptor *desc,
636
+ size_t min_size)
637
+{
638
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
639
+}
640
+
641
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
642
+ uint32_t phys_addr)
643
+{
644
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
645
+}
646
+
647
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
648
+{
649
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
650
+ FrameDescriptor desc;
651
+
652
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
653
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
654
+}
655
+
656
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
657
+ const uint8_t *buf,
658
+ size_t size)
659
+{
660
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
661
+ FrameDescriptor desc;
662
+ size_t bytes_left = size;
663
+ size_t desc_bytes = 0;
664
+ size_t pad_fcs_size = 4;
665
+ size_t padding = 0;
666
+
667
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
668
+ return -1;
669
+ }
670
+
671
+ s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
672
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
673
+ if (!s->rx_desc_curr) {
674
+ s->int_sta |= INT_STA_RX_BUF_UA;
675
+ }
676
+
677
+ /* Keep filling RX descriptors until the whole frame is written */
678
+ while (s->rx_desc_curr && bytes_left > 0) {
679
+ desc.status &= ~DESC_STATUS_CTL;
680
+ desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
681
+
682
+ if (bytes_left == size) {
683
+ desc.status |= RX_DESC_STATUS_FIRST_DESC;
684
+ }
685
+
686
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
687
+ (bytes_left + pad_fcs_size)) {
688
+ desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
689
+ desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
690
+ } else {
691
+ padding = pad_fcs_size;
692
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
693
+ padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
694
+ }
695
+
696
+ desc_bytes = (bytes_left);
697
+ desc.status |= RX_DESC_STATUS_LAST_DESC;
698
+ desc.status |= (bytes_left + padding)
699
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
700
+ }
701
+
702
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
703
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
704
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
705
+ desc_bytes);
706
+
707
+ /* Check if frame needs to raise the receive interrupt */
708
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
709
+ s->int_sta |= INT_STA_RX;
710
+ }
711
+
712
+ /* Increment variables */
713
+ buf += desc_bytes;
714
+ bytes_left -= desc_bytes;
715
+
716
+ /* Move to the next descriptor */
717
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
718
+ if (!s->rx_desc_curr) {
719
+ /* Not enough buffer space available */
720
+ s->int_sta |= INT_STA_RX_BUF_UA;
721
+ s->rx_desc_curr = s->rx_desc_head;
722
+ break;
723
+ }
724
+ }
725
+
726
+ /* Report receive DMA is finished */
727
+ s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
728
+ allwinner_sun8i_emac_update_irq(s);
729
+
730
+ return size;
731
+}
732
+
733
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
734
+{
735
+ NetClientState *nc = qemu_get_queue(s->nic);
736
+ FrameDescriptor desc;
737
+ size_t bytes = 0;
738
+ size_t packet_bytes = 0;
739
+ size_t transmitted = 0;
740
+ static uint8_t packet_buf[2048];
741
+
742
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
743
+
744
+ /* Read all transmit descriptors */
745
+ while (s->tx_desc_curr != 0) {
746
+
747
+ /* Read from physical memory into packet buffer */
748
+ bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
749
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
750
+ desc.status |= TX_DESC_STATUS_LENGTH_ERR;
751
+ break;
752
+ }
753
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
754
+ packet_bytes += bytes;
755
+ desc.status &= ~DESC_STATUS_CTL;
756
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
757
+
758
+ /* After the last descriptor, send the packet */
759
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
760
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
761
+ net_checksum_calculate(packet_buf, packet_bytes);
762
+ }
763
+
764
+ qemu_send_packet(nc, packet_buf, packet_bytes);
765
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
766
+ bytes);
767
+
768
+ packet_bytes = 0;
769
+ transmitted++;
770
+ }
771
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
772
+ }
773
+
774
+ /* Raise transmit completed interrupt */
775
+ if (transmitted > 0) {
776
+ s->int_sta |= INT_STA_TX;
777
+ s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
778
+ allwinner_sun8i_emac_update_irq(s);
779
+ }
780
+}
781
+
782
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
783
+{
784
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
785
+ NetClientState *nc = qemu_get_queue(s->nic);
786
+
787
+ trace_allwinner_sun8i_emac_reset();
788
+
789
+ s->mii_cmd = 0;
790
+ s->mii_data = 0;
791
+ s->basic_ctl0 = 0;
792
+ s->basic_ctl1 = REG_BASIC_CTL_1_RST;
793
+ s->int_en = 0;
794
+ s->int_sta = 0;
795
+ s->frm_flt = 0;
796
+ s->rx_ctl0 = 0;
797
+ s->rx_ctl1 = RX_CTL1_RX_MD;
798
+ s->rx_desc_head = 0;
799
+ s->rx_desc_curr = 0;
800
+ s->tx_ctl0 = 0;
801
+ s->tx_ctl1 = 0;
802
+ s->tx_desc_head = 0;
803
+ s->tx_desc_curr = 0;
804
+ s->tx_flowctl = 0;
805
+
806
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
807
+}
808
+
809
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
810
+ unsigned size)
811
+{
812
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
813
+ uint64_t value = 0;
814
+ FrameDescriptor desc;
815
+
816
+ switch (offset) {
817
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
818
+ value = s->basic_ctl0;
819
+ break;
820
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
821
+ value = s->basic_ctl1;
822
+ break;
823
+ case REG_INT_STA: /* Interrupt Status */
824
+ value = s->int_sta;
825
+ break;
826
+ case REG_INT_EN: /* Interupt Enable */
827
+ value = s->int_en;
828
+ break;
829
+ case REG_TX_CTL_0: /* Transmit Control 0 */
830
+ value = s->tx_ctl0;
831
+ break;
832
+ case REG_TX_CTL_1: /* Transmit Control 1 */
833
+ value = s->tx_ctl1;
834
+ break;
835
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
836
+ value = s->tx_flowctl;
837
+ break;
838
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
839
+ value = s->tx_desc_head;
840
+ break;
841
+ case REG_RX_CTL_0: /* Receive Control 0 */
842
+ value = s->rx_ctl0;
843
+ break;
844
+ case REG_RX_CTL_1: /* Receive Control 1 */
845
+ value = s->rx_ctl1;
846
+ break;
847
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
848
+ value = s->rx_desc_head;
849
+ break;
850
+ case REG_FRM_FLT: /* Receive Frame Filter */
851
+ value = s->frm_flt;
852
+ break;
853
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
854
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
855
+ break;
856
+ case REG_MII_CMD: /* Management Interface Command */
857
+ value = s->mii_cmd;
858
+ break;
859
+ case REG_MII_DATA: /* Management Interface Data */
860
+ value = s->mii_data;
861
+ break;
862
+ case REG_ADDR_HIGH: /* MAC Address High */
863
+ value = *(((uint32_t *) (s->conf.macaddr.a)) + 1);
864
+ break;
865
+ case REG_ADDR_LOW: /* MAC Address Low */
866
+ value = *(uint32_t *) (s->conf.macaddr.a);
867
+ break;
868
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
869
+ break;
870
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
871
+ value = s->tx_desc_curr;
872
+ break;
873
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
874
+ if (s->tx_desc_curr != 0) {
875
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
876
+ value = desc.addr;
877
+ } else {
878
+ value = 0;
879
+ }
880
+ break;
881
+ case REG_RX_DMA_STA: /* Receive DMA Status */
882
+ break;
883
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
884
+ value = s->rx_desc_curr;
885
+ break;
886
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
887
+ if (s->rx_desc_curr != 0) {
888
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
889
+ value = desc.addr;
890
+ } else {
891
+ value = 0;
892
+ }
893
+ break;
894
+ case REG_RGMII_STA: /* RGMII Status */
895
+ break;
896
+ default:
897
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
898
+ "EMAC register 0x" TARGET_FMT_plx "\n",
899
+ offset);
900
+ }
901
+
902
+ trace_allwinner_sun8i_emac_read(offset, value);
903
+ return value;
904
+}
905
+
906
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
907
+ uint64_t value, unsigned size)
908
+{
909
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
910
+ NetClientState *nc = qemu_get_queue(s->nic);
911
+
912
+ trace_allwinner_sun8i_emac_write(offset, value);
913
+
914
+ switch (offset) {
915
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
916
+ s->basic_ctl0 = value;
917
+ break;
918
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
919
+ if (value & BASIC_CTL1_SOFTRST) {
920
+ allwinner_sun8i_emac_reset(DEVICE(s));
921
+ value &= ~BASIC_CTL1_SOFTRST;
922
+ }
923
+ s->basic_ctl1 = value;
924
+ if (allwinner_sun8i_emac_can_receive(nc)) {
925
+ qemu_flush_queued_packets(nc);
926
+ }
927
+ break;
928
+ case REG_INT_STA: /* Interrupt Status */
929
+ s->int_sta &= ~value;
930
+ allwinner_sun8i_emac_update_irq(s);
931
+ break;
932
+ case REG_INT_EN: /* Interrupt Enable */
933
+ s->int_en = value;
934
+ allwinner_sun8i_emac_update_irq(s);
935
+ break;
936
+ case REG_TX_CTL_0: /* Transmit Control 0 */
937
+ s->tx_ctl0 = value;
938
+ break;
939
+ case REG_TX_CTL_1: /* Transmit Control 1 */
940
+ s->tx_ctl1 = value;
941
+ if (value & TX_CTL1_TX_DMA_EN) {
942
+ allwinner_sun8i_emac_transmit(s);
943
+ }
944
+ break;
945
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
946
+ s->tx_flowctl = value;
947
+ break;
948
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
949
+ s->tx_desc_head = value;
950
+ s->tx_desc_curr = value;
951
+ break;
952
+ case REG_RX_CTL_0: /* Receive Control 0 */
953
+ s->rx_ctl0 = value;
954
+ break;
955
+ case REG_RX_CTL_1: /* Receive Control 1 */
956
+ s->rx_ctl1 = value | RX_CTL1_RX_MD;
957
+ if ((value & RX_CTL1_RX_DMA_EN) &&
958
+ allwinner_sun8i_emac_can_receive(nc)) {
959
+ qemu_flush_queued_packets(nc);
960
+ }
961
+ break;
962
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
963
+ s->rx_desc_head = value;
964
+ s->rx_desc_curr = value;
965
+ break;
966
+ case REG_FRM_FLT: /* Receive Frame Filter */
967
+ s->frm_flt = value;
968
+ break;
969
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
970
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
971
+ break;
972
+ case REG_MII_CMD: /* Management Interface Command */
973
+ s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
974
+ allwinner_sun8i_emac_mii_cmd(s);
975
+ break;
976
+ case REG_MII_DATA: /* Management Interface Data */
977
+ s->mii_data = value;
978
+ break;
979
+ case REG_ADDR_HIGH: /* MAC Address High */
980
+ s->conf.macaddr.a[4] = (value & 0xff);
981
+ s->conf.macaddr.a[5] = (value & 0xff00) >> 8;
982
+ break;
983
+ case REG_ADDR_LOW: /* MAC Address Low */
984
+ s->conf.macaddr.a[0] = (value & 0xff);
985
+ s->conf.macaddr.a[1] = (value & 0xff00) >> 8;
986
+ s->conf.macaddr.a[2] = (value & 0xff0000) >> 16;
987
+ s->conf.macaddr.a[3] = (value & 0xff000000) >> 24;
988
+ break;
989
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
990
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
991
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
992
+ case REG_RX_DMA_STA: /* Receive DMA Status */
993
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
994
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
995
+ case REG_RGMII_STA: /* RGMII Status */
996
+ break;
997
+ default:
998
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
999
+ "EMAC register 0x" TARGET_FMT_plx "\n",
1000
+ offset);
1001
+ }
1002
+}
1003
+
1004
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
1005
+{
1006
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
1007
+
1008
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
1009
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
1010
+}
1011
+
1012
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
1013
+ .read = allwinner_sun8i_emac_read,
1014
+ .write = allwinner_sun8i_emac_write,
1015
+ .endianness = DEVICE_NATIVE_ENDIAN,
1016
+ .valid = {
1017
+ .min_access_size = 4,
1018
+ .max_access_size = 4,
1019
+ },
1020
+ .impl.min_access_size = 4,
1021
+};
1022
+
1023
+static NetClientInfo net_allwinner_sun8i_emac_info = {
1024
+ .type = NET_CLIENT_DRIVER_NIC,
1025
+ .size = sizeof(NICState),
1026
+ .can_receive = allwinner_sun8i_emac_can_receive,
1027
+ .receive = allwinner_sun8i_emac_receive,
1028
+ .link_status_changed = allwinner_sun8i_emac_set_link,
1029
+};
1030
+
1031
+static void allwinner_sun8i_emac_init(Object *obj)
1032
+{
1033
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1034
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
1035
+
1036
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
1037
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
1038
+ sysbus_init_mmio(sbd, &s->iomem);
1039
+ sysbus_init_irq(sbd, &s->irq);
1040
+}
1041
+
1042
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
1043
+{
1044
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
1045
+
1046
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
1047
+ s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
1048
+ object_get_typename(OBJECT(dev)), dev->id, s);
1049
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1050
+}
1051
+
1052
+static Property allwinner_sun8i_emac_properties[] = {
1053
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
1054
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
1055
+ DEFINE_PROP_END_OF_LIST(),
1056
+};
1057
+
1058
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
1059
+{
1060
+ AwSun8iEmacState *s = opaque;
1061
+
1062
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
1063
+
1064
+ return 0;
1065
+}
1066
+
1067
+static const VMStateDescription vmstate_aw_emac = {
1068
+ .name = "allwinner-sun8i-emac",
1069
+ .version_id = 1,
1070
+ .minimum_version_id = 1,
1071
+ .post_load = allwinner_sun8i_emac_post_load,
1072
+ .fields = (VMStateField[]) {
1073
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
1074
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
1075
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
1076
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
1077
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
1078
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
1079
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
1080
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
1081
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
1082
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
1083
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
1084
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
1085
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
1086
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
1087
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
1088
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
1089
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
1090
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
1091
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
1092
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
1093
+ VMSTATE_END_OF_LIST()
1094
+ }
1095
+};
1096
+
1097
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
1098
+{
1099
+ DeviceClass *dc = DEVICE_CLASS(klass);
1100
+
1101
+ dc->realize = allwinner_sun8i_emac_realize;
1102
+ dc->reset = allwinner_sun8i_emac_reset;
1103
+ dc->vmsd = &vmstate_aw_emac;
1104
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
1105
+}
1106
+
1107
+static const TypeInfo allwinner_sun8i_emac_info = {
1108
+ .name = TYPE_AW_SUN8I_EMAC,
1109
+ .parent = TYPE_SYS_BUS_DEVICE,
1110
+ .instance_size = sizeof(AwSun8iEmacState),
1111
+ .instance_init = allwinner_sun8i_emac_init,
1112
+ .class_init = allwinner_sun8i_emac_class_init,
1113
+};
1114
+
1115
+static void allwinner_sun8i_emac_register_types(void)
1116
+{
1117
+ type_register_static(&allwinner_sun8i_emac_info);
1118
+}
1119
+
1120
+type_init(allwinner_sun8i_emac_register_types)
1121
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1122
index XXXXXXX..XXXXXXX 100644
1123
--- a/hw/arm/Kconfig
1124
+++ b/hw/arm/Kconfig
1125
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
1126
config ALLWINNER_H3
1127
bool
1128
select ALLWINNER_A10_PIT
1129
+ select ALLWINNER_SUN8I_EMAC
1130
select SERIAL
1131
select ARM_TIMER
1132
select ARM_GIC
1133
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/hw/net/Kconfig
1136
+++ b/hw/net/Kconfig
1137
@@ -XXX,XX +XXX,XX @@ config MIPSNET
1138
config ALLWINNER_EMAC
1139
bool
1140
1141
+config ALLWINNER_SUN8I_EMAC
1142
+ bool
1143
+
1144
config IMX_FEC
1145
bool
1146
1147
diff --git a/hw/net/trace-events b/hw/net/trace-events
1148
index XXXXXXX..XXXXXXX 100644
1149
--- a/hw/net/trace-events
1150
+++ b/hw/net/trace-events
1151
@@ -XXX,XX +XXX,XX @@
1152
# See docs/devel/tracing.txt for syntax documentation.
1153
1154
+# allwinner-sun8i-emac.c
1155
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
1156
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
1157
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1158
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1159
+allwinner_sun8i_emac_reset(void) "HW reset"
1160
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
1161
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
1162
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
1163
+
1164
# etraxfs_eth.c
1165
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
1166
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
1167
--
215
--
1168
2.20.1
216
2.20.1
1169
217
1170
218
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Mention 'max' value in the gic-version property description.
3
As we want to call qdev_connect_clock_in() before the device
4
is realized, we need to uninline cadence_uart_create() first.
4
5
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20200803105647.22223-2-f4bug@amsat.org
8
Message-id: 20200311131618.7187-2-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/arm/virt.c | 3 ++-
11
include/hw/char/cadence_uart.h | 17 -----------------
12
1 file changed, 2 insertions(+), 1 deletion(-)
12
hw/arm/xilinx_zynq.c | 14 ++++++++++++--
13
2 files changed, 12 insertions(+), 19 deletions(-)
13
14
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
17
--- a/include/hw/char/cadence_uart.h
17
+++ b/hw/arm/virt.c
18
+++ b/include/hw/char/cadence_uart.h
18
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
virt_set_gic_version, NULL);
20
Clock *refclk;
20
object_property_set_description(obj, "gic-version",
21
} CadenceUARTState;
21
"Set GIC version. "
22
22
- "Valid values are 2, 3 and host", NULL);
23
-static inline DeviceState *cadence_uart_create(hwaddr addr,
23
+ "Valid values are 2, 3, host and max",
24
- qemu_irq irq,
24
+ NULL);
25
- Chardev *chr)
25
26
-{
26
vms->highmem_ecam = !vmc->no_highmem_ecam;
27
- DeviceState *dev;
28
- SysBusDevice *s;
29
-
30
- dev = qdev_new(TYPE_CADENCE_UART);
31
- s = SYS_BUS_DEVICE(dev);
32
- qdev_prop_set_chr(dev, "chardev", chr);
33
- sysbus_realize_and_unref(s, &error_fatal);
34
- sysbus_mmio_map(s, 0, addr);
35
- sysbus_connect_irq(s, 0, irq);
36
-
37
- return dev;
38
-}
39
-
40
#endif
41
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/xilinx_zynq.c
44
+++ b/hw/arm/xilinx_zynq.c
45
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
46
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
47
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
48
49
- dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
50
+ dev = qdev_new(TYPE_CADENCE_UART);
51
+ busdev = SYS_BUS_DEVICE(dev);
52
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
53
+ sysbus_realize_and_unref(busdev, &error_fatal);
54
+ sysbus_mmio_map(busdev, 0, 0xE0000000);
55
+ sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
56
qdev_connect_clock_in(dev, "refclk",
57
qdev_get_clock_out(slcr, "uart0_ref_clk"));
58
- dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
59
+ dev = qdev_new(TYPE_CADENCE_UART);
60
+ busdev = SYS_BUS_DEVICE(dev);
61
+ qdev_prop_set_chr(dev, "chardev", serial_hd(1));
62
+ sysbus_realize_and_unref(busdev, &error_fatal);
63
+ sysbus_mmio_map(busdev, 0, 0xE0001000);
64
+ sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
65
qdev_connect_clock_in(dev, "refclk",
66
qdev_get_clock_out(slcr, "uart1_ref_clk"));
27
67
28
--
68
--
29
2.20.1
69
2.20.1
30
70
31
71
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The kernel image and DeviceTree blob are built by the Armbian
3
Clock canonical name is set in device_set_realized (see the block
4
project (based on Debian):
4
added to hw/core/qdev.c in commit 0e6934f264).
5
https://www.armbian.com/orange-pi-pc/
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
6
8
7
The SD image is from the kernelci.org project:
9
Fix by calling qdev_connect_clock_in() before realizing.
8
https://kernelci.org/faq/#the-code
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
16
console: Uncompressing Linux... done, booting the kernel.
17
console: Booting Linux on physical CPU 0x0
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
19
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
20
[...]
21
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
22
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
23
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
24
console: ledtrig-cpu: registered to indicate activity on CPUs
25
console: hidraw: raw HID events driver (C) Jiri Kosina
26
console: usbcore: registered new interface driver usbhid
27
console: usbhid: USB HID core driver
28
console: Initializing XFRM netlink socket
29
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
30
console: NET: Registered protocol family 10
31
console: mmc0: host does not support reading read-only switch, assuming write-enable
32
console: mmc0: Problem switching card into high-speed mode!
33
console: mmc0: new SD card at address 4567
34
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
35
[...]
36
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
37
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
38
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
39
console: Run /sbin/init as init process
40
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
41
console: Starting syslogd: OK
42
console: Starting klogd: OK
43
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
44
console: /bin/sh: can't access tty; job control turned off
45
console: cat /proc/partitions
46
console: / # cat /proc/partitions
47
console: major minor #blocks name
48
console: 1 0 4096 ram0
49
console: 1 1 4096 ram1
50
console: 1 2 4096 ram2
51
console: 1 3 4096 ram3
52
console: 179 0 61440 mmcblk0
53
console: reboot
54
console: / # reboot
55
console: umount: devtmpfs busy - remounted read-only
56
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
57
console: The system is going down NOW!
58
console: Sent SIGTERM to all processes
59
console: Sent SIGKILL to all processes
60
console: Requesting system reboot
61
console: reboot: Restarting system
62
JOB TIME : 68.64 s
63
10
64
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
65
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
66
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20200803105647.22223-3-f4bug@amsat.org
67
Tested-by: Alex Bennée <alex.bennee@linaro.org>
68
Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com
69
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
70
[NL: extend test with ethernet device checks]
71
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
72
---
15
---
73
tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++
16
hw/arm/xilinx_zynq.c | 18 +++++++++---------
74
1 file changed, 47 insertions(+)
17
1 file changed, 9 insertions(+), 9 deletions(-)
75
18
76
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
19
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
77
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
78
--- a/tests/acceptance/boot_linux_console.py
21
--- a/hw/arm/xilinx_zynq.c
79
+++ b/tests/acceptance/boot_linux_console.py
22
+++ b/hw/arm/xilinx_zynq.c
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
23
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
81
exec_command_and_wait_for_pattern(self, 'reboot',
24
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
82
'reboot: Restarting system')
25
0);
83
26
84
+ def test_arm_orangepi_sd(self):
27
- /* Create slcr, keep a pointer to connect clocks */
85
+ """
28
- slcr = qdev_new("xilinx,zynq_slcr");
86
+ :avocado: tags=arch:arm
29
- sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
87
+ :avocado: tags=machine:orangepi-pc
30
- sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
88
+ """
31
-
89
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
32
/* Create the main clock source, and feed slcr with it */
90
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
33
zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
91
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
34
object_property_add_child(OBJECT(zynq_machine), "ps_clk",
92
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
35
OBJECT(zynq_machine->ps_clk));
93
+ kernel_path = self.extract_from_deb(deb_path,
36
object_unref(OBJECT(zynq_machine->ps_clk));
94
+ '/boot/vmlinuz-4.20.7-sunxi')
37
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
95
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
96
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
97
+ rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
98
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
99
+ rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061'
100
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
101
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
102
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
103
+
38
+
104
+ self.vm.set_console()
39
+ /* Create slcr, keep a pointer to connect clocks */
105
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
40
+ slcr = qdev_new("xilinx,zynq_slcr");
106
+ 'console=ttyS0,115200 '
41
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
107
+ 'root=/dev/mmcblk0 rootwait rw '
42
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
108
+ 'panic=-1 noreboot')
43
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
109
+ self.vm.add_args('-kernel', kernel_path,
44
110
+ '-dtb', dtb_path,
45
dev = qdev_new(TYPE_A9MPCORE_PRIV);
111
+ '-drive', 'file=' + rootfs_path + ',if=sd,format=raw',
46
qdev_prop_set_uint32(dev, "num-cpu", 1);
112
+ '-append', kernel_command_line,
47
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
113
+ '-no-reboot')
48
dev = qdev_new(TYPE_CADENCE_UART);
114
+ self.vm.launch()
49
busdev = SYS_BUS_DEVICE(dev);
115
+ shell_ready = "/bin/sh: can't access tty; job control turned off"
50
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
116
+ self.wait_for_console_pattern(shell_ready)
51
+ qdev_connect_clock_in(dev, "refclk",
117
+
52
+ qdev_get_clock_out(slcr, "uart0_ref_clk"));
118
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
53
sysbus_realize_and_unref(busdev, &error_fatal);
119
+ 'Allwinner sun8i Family')
54
sysbus_mmio_map(busdev, 0, 0xE0000000);
120
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
55
sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
121
+ 'mmcblk0')
56
- qdev_connect_clock_in(dev, "refclk",
122
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
57
- qdev_get_clock_out(slcr, "uart0_ref_clk"));
123
+ 'eth0: Link is Up')
58
dev = qdev_new(TYPE_CADENCE_UART);
124
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
59
busdev = SYS_BUS_DEVICE(dev);
125
+ 'udhcpc: lease of 10.0.2.15 obtained')
60
qdev_prop_set_chr(dev, "chardev", serial_hd(1));
126
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
61
+ qdev_connect_clock_in(dev, "refclk",
127
+ '3 packets transmitted, 3 packets received, 0% packet loss')
62
+ qdev_get_clock_out(slcr, "uart1_ref_clk"));
128
+ exec_command_and_wait_for_pattern(self, 'reboot',
63
sysbus_realize_and_unref(busdev, &error_fatal);
129
+ 'reboot: Restarting system')
64
sysbus_mmio_map(busdev, 0, 0xE0001000);
130
+
65
sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
131
def test_s390x_s390_ccw_virtio(self):
66
- qdev_connect_clock_in(dev, "refclk",
132
"""
67
- qdev_get_clock_out(slcr, "uart1_ref_clk"));
133
:avocado: tags=arch:s390x
68
69
sysbus_create_varargs("cadence_ttc", 0xF8001000,
70
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
134
--
71
--
135
2.20.1
72
2.20.1
136
73
137
74
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
A real Allwinner H3 SoC contains a Boot ROM which is the
3
We want to assert the device is not realized. To avoid overloading
4
first code that runs right after the SoC is powered on.
4
this header including "hw/qdev-core.h", uninline the function first.
5
The Boot ROM is responsible for loading user code (e.g. a bootloader)
6
from any of the supported external devices and writing the downloaded
7
code to internal SRAM. After loading the SoC begins executing the code
8
written to SRAM.
9
5
10
This commits adds emulation of the Boot ROM firmware setup functionality
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
8
Message-id: 20200803105647.22223-4-f4bug@amsat.org
13
sizes larger than 32KiB. For reference, this behaviour is documented
14
by the Linux Sunxi project wiki at:
15
16
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
10
---
23
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
11
include/hw/qdev-clock.h | 6 +-----
24
hw/arm/allwinner-h3.c | 17 +++++++++++++++++
12
hw/core/qdev-clock.c | 5 +++++
25
hw/arm/orangepi.c | 5 +++++
13
2 files changed, 6 insertions(+), 5 deletions(-)
26
3 files changed, 43 insertions(+)
27
14
28
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
15
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
29
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-h3.h
17
--- a/include/hw/qdev-clock.h
31
+++ b/include/hw/arm/allwinner-h3.h
18
+++ b/include/hw/qdev-clock.h
32
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
33
#include "hw/sd/allwinner-sdhost.h"
20
* Set the source clock of input clock @name of device @dev to @source.
34
#include "hw/net/allwinner-sun8i-emac.h"
21
* @source period update will be propagated to @name clock.
35
#include "target/arm/cpu.h"
22
*/
36
+#include "sysemu/block-backend.h"
23
-static inline void qdev_connect_clock_in(DeviceState *dev, const char *name,
24
- Clock *source)
25
-{
26
- clock_set_source(qdev_get_clock_in(dev, name), source);
27
-}
28
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
37
29
38
/**
30
/**
39
* Allwinner H3 device list
31
* qdev_alias_clock:
40
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
32
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
41
MemoryRegion sram_c;
33
index XXXXXXX..XXXXXXX 100644
42
} AwH3State;
34
--- a/hw/core/qdev-clock.c
43
35
+++ b/hw/core/qdev-clock.c
44
+/**
36
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
45
+ * Emulate Boot ROM firmware setup functionality.
37
46
+ *
38
return ncl->clock;
47
+ * A real Allwinner H3 SoC contains a Boot ROM
39
}
48
+ * which is the first code that runs right after
49
+ * the SoC is powered on. The Boot ROM is responsible
50
+ * for loading user code (e.g. a bootloader) from any
51
+ * of the supported external devices and writing the
52
+ * downloaded code to internal SRAM. After loading the SoC
53
+ * begins executing the code written to SRAM.
54
+ *
55
+ * This function emulates the Boot ROM by copying 32 KiB
56
+ * of data from the given block device and writes it to
57
+ * the start of the first internal SRAM memory.
58
+ *
59
+ * @s: Allwinner H3 state object pointer
60
+ * @blk: Block backend device object pointer
61
+ */
62
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
63
+
40
+
64
#endif /* HW_ARM_ALLWINNER_H3_H */
41
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
65
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/arm/allwinner-h3.c
68
+++ b/hw/arm/allwinner-h3.c
69
@@ -XXX,XX +XXX,XX @@
70
#include "hw/char/serial.h"
71
#include "hw/misc/unimp.h"
72
#include "hw/usb/hcd-ehci.h"
73
+#include "hw/loader.h"
74
#include "sysemu/sysemu.h"
75
#include "hw/arm/allwinner-h3.h"
76
77
@@ -XXX,XX +XXX,XX @@ enum {
78
AW_H3_GIC_NUM_SPI = 128
79
};
80
81
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
82
+{
42
+{
83
+ const int64_t rom_size = 32 * KiB;
43
+ clock_set_source(qdev_get_clock_in(dev, name), source);
84
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
85
+
86
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
87
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
88
+ __func__);
89
+ return;
90
+ }
91
+
92
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
93
+ rom_size, s->memmap[AW_H3_SRAM_A1],
94
+ NULL, NULL, NULL, NULL, false);
95
+}
44
+}
96
+
97
static void allwinner_h3_init(Object *obj)
98
{
99
AwH3State *s = AW_H3(obj);
100
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/orangepi.c
103
+++ b/hw/arm/orangepi.c
104
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
105
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
106
machine->ram);
107
108
+ /* Load target kernel or start using BootROM */
109
+ if (!machine->kernel_filename && blk_is_available(blk)) {
110
+ /* Use Boot ROM to copy data from SD card to SRAM */
111
+ allwinner_h3_bootrom_setup(h3, blk);
112
+ }
113
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
114
orangepi_binfo.ram_size = machine->ram_size;
115
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
116
--
45
--
117
2.20.1
46
2.20.1
118
47
119
48
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
Clock canonical name is set in device_set_realized (see the block
4
the serial output is working.
4
added to hw/core/qdev.c in commit 0e6934f264).
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
5
8
6
The kernel image and DeviceTree blob are built by the Armbian
9
Add a comment to document qdev_connect_clock_in() must be called
7
project (based on Debian):
10
before the device is realized, and assert this condition.
8
https://www.armbian.com/orange-pi-pc/
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ make check-venv
16
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
17
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
18
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
19
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
20
console: Uncompressing Linux... done, booting the kernel.
21
console: Booting Linux on physical CPU 0x0
22
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
23
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
24
console: CPU: div instructions available: patching division code
25
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
26
console: OF: fdt: Machine model: Xunlong Orange Pi PC
27
console: Memory policy: Data cache writealloc
28
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
29
console: cma: Failed to reserve 128 MiB
30
console: psci: probing for conduit method from DT.
31
console: psci: PSCIv0.2 detected in firmware.
32
console: psci: Using standard PSCI v0.2 function IDs
33
console: psci: Trusted OS migration not required
34
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
35
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
36
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
37
console: Kernel command line: printk.time=0 console=ttyS0,115200
38
PASS (8.59 s)
39
JOB TIME : 8.81 s
40
11
41
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
42
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
43
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20200803105647.22223-5-f4bug@amsat.org
44
Tested-by: Alex Bennée <alex.bennee@linaro.org>
45
Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com
46
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
16
---
49
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
17
include/hw/qdev-clock.h | 2 ++
50
1 file changed, 25 insertions(+)
18
hw/core/qdev-clock.c | 1 +
19
2 files changed, 3 insertions(+)
51
20
52
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
21
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
53
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
54
--- a/tests/acceptance/boot_linux_console.py
23
--- a/include/hw/qdev-clock.h
55
+++ b/tests/acceptance/boot_linux_console.py
24
+++ b/include/hw/qdev-clock.h
56
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
25
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
57
exec_command_and_wait_for_pattern(self, 'reboot',
26
*
58
'reboot: Restarting system')
27
* Set the source clock of input clock @name of device @dev to @source.
59
28
* @source period update will be propagated to @name clock.
60
+ def test_arm_orangepi(self):
29
+ *
61
+ """
30
+ * Must be called before @dev is realized.
62
+ :avocado: tags=arch:arm
31
*/
63
+ :avocado: tags=machine:orangepi-pc
32
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
64
+ """
33
65
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
34
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
66
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
35
index XXXXXXX..XXXXXXX 100644
67
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
36
--- a/hw/core/qdev-clock.c
68
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
37
+++ b/hw/core/qdev-clock.c
69
+ kernel_path = self.extract_from_deb(deb_path,
38
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
70
+ '/boot/vmlinuz-4.20.7-sunxi')
39
71
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
40
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
72
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
41
{
73
+
42
+ assert(!dev->realized);
74
+ self.vm.set_console()
43
clock_set_source(qdev_get_clock_in(dev, name), source);
75
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
44
}
76
+ 'console=ttyS0,115200n8 '
77
+ 'earlycon=uart,mmio32,0x1c28000')
78
+ self.vm.add_args('-kernel', kernel_path,
79
+ '-dtb', dtb_path,
80
+ '-append', kernel_command_line)
81
+ self.vm.launch()
82
+ console_pattern = 'Kernel command line: %s' % kernel_command_line
83
+ self.wait_for_console_pattern(console_pattern)
84
+
85
def test_s390x_s390_ccw_virtio(self):
86
"""
87
:avocado: tags=arch:s390x
88
--
45
--
89
2.20.1
46
2.20.1
90
47
91
48
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The Xunlong Orange Pi PC machine is a functional ARM machine
3
To better align the read/write accesses, display the value after
4
based on the Allwinner H3 System-on-Chip. It supports mainline
4
the offset (read accesses only display the offset).
5
Linux, U-Boot, NetBSD and is covered by acceptance tests.
6
5
7
This commit adds a documentation text file with a description
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
of the machine and instructions for the user.
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
8
Message-id: 20200812190206.31595-2-f4bug@amsat.org
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com
13
[PMM: moved file into docs/system/arm to match the reorg
14
of the arm target part of the docs; tweaked heading to
15
match other boards]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
10
---
18
MAINTAINERS | 1 +
11
hw/misc/unimp.c | 8 ++++----
19
docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++
12
1 file changed, 4 insertions(+), 4 deletions(-)
20
docs/system/target-arm.rst | 2 +
21
3 files changed, 256 insertions(+)
22
create mode 100644 docs/system/arm/orangepi.rst
23
13
24
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
16
--- a/hw/misc/unimp.c
27
+++ b/MAINTAINERS
17
+++ b/hw/misc/unimp.c
28
@@ -XXX,XX +XXX,XX @@ S: Maintained
18
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
29
F: hw/*/allwinner-h3*
19
{
30
F: include/hw/*/allwinner-h3*
20
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
31
F: hw/arm/orangepi.c
21
32
+F: docs/system/orangepi.rst
22
- qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
33
23
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
34
ARM PrimeCell and CMSDK devices
24
"(size %d, offset 0x%" HWADDR_PRIx ")\n",
35
M: Peter Maydell <peter.maydell@linaro.org>
25
s->name, size, offset);
36
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
26
return 0;
37
new file mode 100644
27
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
38
index XXXXXXX..XXXXXXX
28
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
39
--- /dev/null
29
40
+++ b/docs/system/arm/orangepi.rst
30
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
41
@@ -XXX,XX +XXX,XX @@
31
- "(size %d, value 0x%" PRIx64
42
+Orange Pi PC (``orangepi-pc``)
32
- ", offset 0x%" HWADDR_PRIx ")\n",
43
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
33
- s->name, size, value, offset);
44
+
34
+ "(size %d, offset 0x%" HWADDR_PRIx
45
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
35
+ ", value 0x%" PRIx64 ")\n",
46
+based embedded computer with mainline support in both U-Boot
36
+ s->name, size, offset, value);
47
+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
37
}
48
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
38
49
+various other I/O.
39
static const MemoryRegionOps unimp_ops = {
50
+
51
+Supported devices
52
+"""""""""""""""""
53
+
54
+The Orange Pi PC machine supports the following devices:
55
+
56
+ * SMP (Quad Core Cortex-A7)
57
+ * Generic Interrupt Controller configuration
58
+ * SRAM mappings
59
+ * SDRAM controller
60
+ * Real Time Clock
61
+ * Timer device (re-used from Allwinner A10)
62
+ * UART
63
+ * SD/MMC storage controller
64
+ * EMAC ethernet
65
+ * USB 2.0 interfaces
66
+ * Clock Control Unit
67
+ * System Control module
68
+ * Security Identifier device
69
+
70
+Limitations
71
+"""""""""""
72
+
73
+Currently, Orange Pi PC does *not* support the following features:
74
+
75
+- Graphical output via HDMI, GPU and/or the Display Engine
76
+- Audio output
77
+- Hardware Watchdog
78
+
79
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
80
+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``
81
+
82
+Boot options
83
+""""""""""""
84
+
85
+The Orange Pi PC machine can start using the standard -kernel functionality
86
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC
87
+machine can also emulate the BootROM which is present on an actual Allwinner H3
88
+based SoC, which loads the bootloader from a SD card, specified via the -sd argument
89
+to qemu-system-arm.
90
+
91
+Machine-specific options
92
+""""""""""""""""""""""""
93
+
94
+The following machine-specific options are supported:
95
+
96
+- allwinner-rtc.base-year=YYYY
97
+
98
+ The Allwinner RTC device is automatically created by the Orange Pi PC machine
99
+ and uses a default base year value which can be overridden using the 'base-year' property.
100
+ The base year is the actual represented year when the RTC year value is zero.
101
+ This option can be used in case the target operating system driver uses a different
102
+ base year value. The minimum value for the base year is 1900.
103
+
104
+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff
105
+
106
+ The Security Identifier value can be read by the guest.
107
+ For example, U-Boot uses it to determine a unique MAC address.
108
+
109
+The above machine-specific options can be specified in qemu-system-arm
110
+via the '-global' argument, for example:
111
+
112
+.. code-block:: bash
113
+
114
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
115
+ -global allwinner-rtc.base-year=2000
116
+
117
+Running mainline Linux
118
+""""""""""""""""""""""
119
+
120
+Mainline Linux kernels from 4.19 up to latest master are known to work.
121
+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,
122
+simply configure the kernel using the sunxi_defconfig configuration:
123
+
124
+.. code-block:: bash
125
+
126
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper
127
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig
128
+
129
+To be able to use USB storage, you need to manually enable the corresponding
130
+configuration item. Start the kconfig configuration tool:
131
+
132
+.. code-block:: bash
133
+
134
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig
135
+
136
+Navigate to the following item, enable it and save your configuration:
137
+
138
+ Device Drivers > USB support > USB Mass Storage support
139
+
140
+Build the Linux kernel with:
141
+
142
+.. code-block:: bash
143
+
144
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make
145
+
146
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:
147
+
148
+.. code-block:: bash
149
+
150
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
151
+ -kernel /path/to/linux/arch/arm/boot/zImage \
152
+ -append 'console=ttyS0,115200' \
153
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
154
+
155
+Orange Pi PC images
156
+"""""""""""""""""""
157
+
158
+Note that the mainline kernel does not have a root filesystem. You may provide it
159
+with an official Orange Pi PC image from the official website:
160
+
161
+ http://www.orangepi.org/downloadresources/
162
+
163
+Another possibility is to run an Armbian image for Orange Pi PC which
164
+can be downloaded from:
165
+
166
+ https://www.armbian.com/orange-pi-pc/
167
+
168
+Alternatively, you can also choose to build you own image with buildroot
169
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.
170
+
171
+You can choose to attach the selected image either as an SD card or as USB mass storage.
172
+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd
173
+argument and provide the proper root= kernel parameter:
174
+
175
+.. code-block:: bash
176
+
177
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
178
+ -kernel /path/to/linux/arch/arm/boot/zImage \
179
+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \
180
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
181
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
182
+
183
+To attach the image as an USB mass storage device to the machine,
184
+simply append to the command:
185
+
186
+.. code-block:: bash
187
+
188
+ -drive if=none,id=stick,file=myimage.img \
189
+ -device usb-storage,bus=usb-bus.0,drive=stick
190
+
191
+Instead of providing a custom Linux kernel via the -kernel command you may also
192
+choose to let the Orange Pi PC machine load the bootloader from SD card, just like
193
+a real board would do using the BootROM. Simply pass the selected image via the -sd
194
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
195
+
196
+.. code-block:: bash
197
+
198
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
199
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
200
+
201
+Note that both the official Orange Pi PC images and Armbian images start
202
+a lot of userland programs via systemd. Depending on the host hardware and OS,
203
+they may be slow to emulate, especially due to emulating the 4 cores.
204
+To help reduce the performance slow down due to emulating the 4 cores, you can
205
+give the following kernel parameters via U-Boot (or via -append):
206
+
207
+.. code-block:: bash
208
+
209
+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'
210
+
211
+Running U-Boot
212
+""""""""""""""
213
+
214
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
215
+using similar commands as describe above for Linux. Note that it is recommended
216
+for development/testing to select the following configuration setting in U-Boot:
217
+
218
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
219
+
220
+To start U-Boot using the Orange Pi PC machine, provide the
221
+u-boot binary to the -kernel argument:
222
+
223
+.. code-block:: bash
224
+
225
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
226
+ -kernel /path/to/uboot/u-boot -sd disk.img
227
+
228
+Use the following U-boot commands to load and boot a Linux kernel from SD card:
229
+
230
+.. code-block:: bash
231
+
232
+ => setenv bootargs console=ttyS0,115200
233
+ => ext2load mmc 0 0x42000000 zImage
234
+ => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
235
+ => bootz 0x42000000 - 0x43000000
236
+
237
+Running NetBSD
238
+""""""""""""""
239
+
240
+The NetBSD operating system also includes support for Allwinner H3 based boards,
241
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC
242
+board and provides a fully working system with serial console, networking and storage.
243
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
244
+
245
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz
246
+
247
+The image requires manually installing U-Boot in the image. Build U-Boot with
248
+the orangepi_pc_defconfig configuration as described in the previous section.
249
+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:
250
+
251
+.. code-block:: bash
252
+
253
+ $ gunzip armv7.img.gz
254
+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc
255
+
256
+Finally, before starting the machine the SD image must be extended such
257
+that the NetBSD kernel will not conclude the NetBSD partition is larger than
258
+the emulated SD card:
259
+
260
+.. code-block:: bash
261
+
262
+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img
263
+
264
+Start the machine using the following command:
265
+
266
+.. code-block:: bash
267
+
268
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
269
+ -sd armv7.img -global allwinner-rtc.base-year=2000
270
+
271
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
272
+and set the following environment variables before booting:
273
+
274
+.. code-block:: bash
275
+
276
+ => setenv bootargs root=ld0a
277
+ => setenv kernel netbsd-GENERIC.ub
278
+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
279
+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'
280
+
281
+Optionally you may save the environment variables to SD card with 'saveenv'.
282
+To continue booting simply give the 'boot' command and NetBSD boots.
283
+
284
+Orange Pi PC acceptance tests
285
+"""""""""""""""""""""""""""""
286
+
287
+The Orange Pi PC machine has several acceptance tests included.
288
+To run the whole set of tests, build QEMU from source and simply
289
+provide the following command:
290
+
291
+.. code-block:: bash
292
+
293
+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \
294
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
295
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
296
index XXXXXXX..XXXXXXX 100644
297
--- a/docs/system/target-arm.rst
298
+++ b/docs/system/target-arm.rst
299
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
300
``qemu-system-aarch64 --machine help``.
301
302
.. toctree::
303
+ :maxdepth: 1
304
305
arm/integratorcp
306
arm/versatile
307
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
308
arm/stellaris
309
arm/musicpal
310
arm/sx1
311
+ arm/orangepi
312
313
Arm CPU features
314
================
315
--
40
--
316
2.20.1
41
2.20.1
317
42
318
43
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Restructure the finalize_gic_version with switch cases and
3
To quickly notice the access size, display the value with the
4
clearly separate the following cases:
4
width of the access (i.e. 16-bit access is displayed 0x0000,
5
while 8-bit access 0x00).
5
6
6
- KVM mode / in-kernel irqchip
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
- KVM mode / userspace irqchip
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
- TCG mode
9
Message-id: 20200812190206.31595-3-f4bug@amsat.org
9
10
In KVM mode / in-kernel irqchip , we explictly check whether
11
the chosen version is supported by the host. If the end-user
12
explicitly sets v2/v3 and this is not supported by the host,
13
then the user gets an explicit error message. Note that for
14
old kernels where the CREATE_DEVICE ioctl doesn't exist then
15
we will now fail if the user specifically asked for gicv2,
16
where previously we (probably) would have succeeded.
17
18
In KVM mode / userspace irqchip we immediatly output an error
19
in case the end-user explicitly selected v3. Also we warn the
20
end-user about the unexpected usage of gic-version=host in
21
that case as only userspace GICv2 is supported.
22
23
Signed-off-by: Eric Auger <eric.auger@redhat.com>
24
Reviewed-by: Andrew Jones <drjones@redhat.com>
25
Message-id: 20200311131618.7187-6-eric.auger@redhat.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
11
---
28
hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------
12
hw/misc/unimp.c | 4 ++--
29
1 file changed, 67 insertions(+), 21 deletions(-)
13
1 file changed, 2 insertions(+), 2 deletions(-)
30
14
31
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
32
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/virt.c
17
--- a/hw/misc/unimp.c
34
+++ b/hw/arm/virt.c
18
+++ b/hw/misc/unimp.c
35
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
19
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
36
*/
20
37
static void finalize_gic_version(VirtMachineState *vms)
21
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
38
{
22
"(size %d, offset 0x%" HWADDR_PRIx
39
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
23
- ", value 0x%" PRIx64 ")\n",
40
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
24
- s->name, size, offset, value);
41
- if (!kvm_enabled()) {
25
+ ", value 0x%0*" PRIx64 ")\n",
42
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
26
+ s->name, size, offset, size << 1, value);
43
- error_report("gic-version=host requires KVM");
44
- exit(1);
45
- } else {
46
- /* "max": currently means 3 for TCG */
47
- vms->gic_version = VIRT_GIC_VERSION_3;
48
- }
49
- } else {
50
- int probe_bitmap = kvm_arm_vgic_probe();
51
+ if (kvm_enabled()) {
52
+ int probe_bitmap;
53
54
- if (!probe_bitmap) {
55
+ if (!kvm_irqchip_in_kernel()) {
56
+ switch (vms->gic_version) {
57
+ case VIRT_GIC_VERSION_HOST:
58
+ warn_report(
59
+ "gic-version=host not relevant with kernel-irqchip=off "
60
+ "as only userspace GICv2 is supported. Using v2 ...");
61
+ return;
62
+ case VIRT_GIC_VERSION_MAX:
63
+ case VIRT_GIC_VERSION_NOSEL:
64
+ vms->gic_version = VIRT_GIC_VERSION_2;
65
+ return;
66
+ case VIRT_GIC_VERSION_2:
67
+ return;
68
+ case VIRT_GIC_VERSION_3:
69
error_report(
70
- "Unable to determine GIC version supported by host");
71
+ "gic-version=3 is not supported with kernel-irqchip=off");
72
exit(1);
73
- } else {
74
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
75
- vms->gic_version = VIRT_GIC_VERSION_3;
76
- } else {
77
- vms->gic_version = VIRT_GIC_VERSION_2;
78
- }
79
}
80
}
81
- } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
82
+
83
+ probe_bitmap = kvm_arm_vgic_probe();
84
+ if (!probe_bitmap) {
85
+ error_report("Unable to determine GIC version supported by host");
86
+ exit(1);
87
+ }
88
+
89
+ switch (vms->gic_version) {
90
+ case VIRT_GIC_VERSION_HOST:
91
+ case VIRT_GIC_VERSION_MAX:
92
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
93
+ vms->gic_version = VIRT_GIC_VERSION_3;
94
+ } else {
95
+ vms->gic_version = VIRT_GIC_VERSION_2;
96
+ }
97
+ return;
98
+ case VIRT_GIC_VERSION_NOSEL:
99
+ vms->gic_version = VIRT_GIC_VERSION_2;
100
+ break;
101
+ case VIRT_GIC_VERSION_2:
102
+ case VIRT_GIC_VERSION_3:
103
+ break;
104
+ }
105
+
106
+ /* Check chosen version is effectively supported by the host */
107
+ if (vms->gic_version == VIRT_GIC_VERSION_2 &&
108
+ !(probe_bitmap & KVM_ARM_VGIC_V2)) {
109
+ error_report("host does not support in-kernel GICv2 emulation");
110
+ exit(1);
111
+ } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
112
+ !(probe_bitmap & KVM_ARM_VGIC_V3)) {
113
+ error_report("host does not support in-kernel GICv3 emulation");
114
+ exit(1);
115
+ }
116
+ return;
117
+ }
118
+
119
+ /* TCG mode */
120
+ switch (vms->gic_version) {
121
+ case VIRT_GIC_VERSION_NOSEL:
122
vms->gic_version = VIRT_GIC_VERSION_2;
123
+ break;
124
+ case VIRT_GIC_VERSION_MAX:
125
+ vms->gic_version = VIRT_GIC_VERSION_3;
126
+ break;
127
+ case VIRT_GIC_VERSION_HOST:
128
+ error_report("gic-version=host requires KVM");
129
+ exit(1);
130
+ case VIRT_GIC_VERSION_2:
131
+ case VIRT_GIC_VERSION_3:
132
+ break;
133
}
134
}
27
}
135
28
29
static const MemoryRegionOps unimp_ops = {
136
--
30
--
137
2.20.1
31
2.20.1
138
32
139
33
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
To have a better idea of how big is the region where the offset
4
the serial output is working.
4
belongs, display the value with the width of the region size
5
(i.e. a region of 0x1000 bytes uses 0x000 format).
5
6
6
The kernel image and DeviceTree blob are built by the Armbian
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
project (based on Debian):
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
https://www.armbian.com/orange-pi-pc/
9
Message-id: 20200812190206.31595-4-f4bug@amsat.org
9
10
The cpio image used comes from the linux-build-test project:
11
https://github.com/groeck/linux-build-test
12
13
If ARM is a target being built, "make check-acceptance" will
14
automatically include this test by the use of the "arch:arm" tags.
15
16
Alternatively, this test can be run using:
17
18
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
19
console: Uncompressing Linux... done, booting the kernel.
20
console: Booting Linux on physical CPU 0x0
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
23
console: CPU: div instructions available: patching division code
24
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
25
console: OF: fdt: Machine model: Xunlong Orange Pi PC
26
[...]
27
console: Trying to unpack rootfs image as initramfs...
28
console: Freeing initrd memory: 3256K
29
console: Freeing unused kernel memory: 1024K
30
console: Run /init as init process
31
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
32
console: Starting logging: OK
33
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
34
console: done.
35
console: Starting network: OK
36
console: Found console ttyS0
37
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
38
console: Boot successful.
39
console: cat /proc/cpuinfo
40
console: / # cat /proc/cpuinfo
41
console: processor : 0
42
console: model name : ARMv7 Processor rev 5 (v7l)
43
console: BogoMIPS : 125.00
44
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
45
console: CPU implementer : 0x41
46
console: CPU architecture: 7
47
console: CPU variant : 0x0
48
console: CPU part : 0xc07
49
console: CPU revision : 5
50
[...]
51
console: processor : 3
52
console: model name : ARMv7 Processor rev 5 (v7l)
53
console: BogoMIPS : 125.00
54
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
55
console: CPU implementer : 0x41
56
console: CPU architecture: 7
57
console: CPU variant : 0x0
58
console: CPU part : 0xc07
59
console: CPU revision : 5
60
console: Hardware : Allwinner sun8i Family
61
console: Revision : 0000
62
console: Serial : 0000000000000000
63
console: cat /proc/iomem
64
console: / # cat /proc/iomem
65
console: 01000000-010fffff : clock@1000000
66
console: 01c00000-01c00fff : system-control@1c00000
67
console: 01c02000-01c02fff : dma-controller@1c02000
68
[...]
69
console: reboot
70
console: / # reboot
71
console: / # Found console ttyS0
72
console: Stopping network: OK
73
console: hrtimer: interrupt took 21852064 ns
74
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
75
console: done.
76
console: Stopping logging: OK
77
console: umount: devtmpfs busy - remounted read-only
78
console: umount: can't unmount /: Invalid argument
79
console: The system is going down NOW!
80
console: Sent SIGTERM to all processes
81
console: Sent SIGKILL to all processes
82
console: Requesting system reboot
83
console: reboot: Restarting system
84
PASS (48.32 s)
85
JOB TIME : 49.16 s
86
87
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
88
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
89
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
90
Tested-by: Alex Bennée <alex.bennee@linaro.org>
91
Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com
92
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
93
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94
---
11
---
95
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
12
include/hw/misc/unimp.h | 1 +
96
1 file changed, 40 insertions(+)
13
hw/misc/unimp.c | 10 ++++++----
14
2 files changed, 7 insertions(+), 4 deletions(-)
97
15
98
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
16
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
99
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
100
--- a/tests/acceptance/boot_linux_console.py
18
--- a/include/hw/misc/unimp.h
101
+++ b/tests/acceptance/boot_linux_console.py
19
+++ b/include/hw/misc/unimp.h
102
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
20
@@ -XXX,XX +XXX,XX @@
103
console_pattern = 'Kernel command line: %s' % kernel_command_line
21
typedef struct {
104
self.wait_for_console_pattern(console_pattern)
22
SysBusDevice parent_obj;
105
23
MemoryRegion iomem;
106
+ def test_arm_orangepi_initrd(self):
24
+ unsigned offset_fmt_width;
107
+ """
25
char *name;
108
+ :avocado: tags=arch:arm
26
uint64_t size;
109
+ :avocado: tags=machine:orangepi-pc
27
} UnimplementedDeviceState;
110
+ """
28
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
111
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
29
index XXXXXXX..XXXXXXX 100644
112
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
30
--- a/hw/misc/unimp.c
113
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
31
+++ b/hw/misc/unimp.c
114
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
32
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
115
+ kernel_path = self.extract_from_deb(deb_path,
33
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
116
+ '/boot/vmlinuz-4.20.7-sunxi')
34
117
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
35
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
118
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
36
- "(size %d, offset 0x%" HWADDR_PRIx ")\n",
119
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
37
- s->name, size, offset);
120
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
38
+ "(size %d, offset 0x%0*" HWADDR_PRIx ")\n",
121
+ 'arm/rootfs-armv7a.cpio.gz')
39
+ s->name, size, s->offset_fmt_width, offset);
122
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
40
return 0;
123
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
41
}
124
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
42
125
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
43
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
44
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
45
46
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
47
- "(size %d, offset 0x%" HWADDR_PRIx
48
+ "(size %d, offset 0x%0*" HWADDR_PRIx
49
", value 0x%0*" PRIx64 ")\n",
50
- s->name, size, offset, size << 1, value);
51
+ s->name, size, s->offset_fmt_width, offset, size << 1, value);
52
}
53
54
static const MemoryRegionOps unimp_ops = {
55
@@ -XXX,XX +XXX,XX @@ static void unimp_realize(DeviceState *dev, Error **errp)
56
return;
57
}
58
59
+ s->offset_fmt_width = DIV_ROUND_UP(64 - clz64(s->size - 1), 4);
126
+
60
+
127
+ self.vm.set_console()
61
memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
128
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
62
s->name, s->size);
129
+ 'console=ttyS0,115200 '
63
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
130
+ 'panic=-1 noreboot')
131
+ self.vm.add_args('-kernel', kernel_path,
132
+ '-dtb', dtb_path,
133
+ '-initrd', initrd_path,
134
+ '-append', kernel_command_line,
135
+ '-no-reboot')
136
+ self.vm.launch()
137
+ self.wait_for_console_pattern('Boot successful.')
138
+
139
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
140
+ 'Allwinner sun8i Family')
141
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
142
+ 'system-control@1c00000')
143
+ exec_command_and_wait_for_pattern(self, 'reboot',
144
+ 'reboot: Restarting system')
145
+
146
def test_s390x_s390_ccw_virtio(self):
147
"""
148
:avocado: tags=arch:s390x
149
--
64
--
150
2.20.1
65
2.20.1
151
66
152
67
diff view generated by jsdifflib
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Eduardo Habkost <ehabkost@redhat.com>
2
2
3
SOC object returned by object_new() is leaked in current code.
3
TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but
4
Set SOC parent explicitly to board and then unref to SOC object
4
ARMSSEClass::parent_class is declared as DeviceClass.
5
to make sure that refererence returned by object_new() is taken
6
care of.
7
5
8
The SOC object will be kept alive by its parent (machine) and
6
It never caused any problems by pure luck:
9
will be automatically freed when MachineState is destroyed.
10
7
11
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
8
We were not setting class_size for TYPE_ARM_SSE, so class_size of
12
Reported-by: Andrew Jones <drjones@redhat.com>
9
TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)).
13
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
This made the system allocate enough memory for TYPE_ARM_SSE
14
Message-id: 20200303091254.22373-1-imammedo@redhat.com
11
devices even though ARMSSEClass was too small for a sysbus
12
device.
13
14
Additionally, the ARMSSEClass::info field ended up at the same
15
offset as SysBusDeviceClass::explicit_ofw_unit_address. This
16
would make sysbus_get_fw_dev_path() crash for the device.
17
Luckily, sysbus_get_fw_dev_path() never gets called for
18
TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used
19
by the boot device code, and TYPE_ARM_SSE devices don't appear at
20
the fw_boot_order list.
21
22
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
23
Message-id: 20200826181006.4097163-1-ehabkost@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
26
---
18
hw/arm/cubieboard.c | 3 +++
27
include/hw/arm/armsse.h | 2 +-
19
1 file changed, 3 insertions(+)
28
hw/arm/armsse.c | 1 +
29
2 files changed, 2 insertions(+), 1 deletion(-)
20
30
21
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
31
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
22
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/cubieboard.c
33
--- a/include/hw/arm/armsse.h
24
+++ b/hw/arm/cubieboard.c
34
+++ b/include/hw/arm/armsse.h
25
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
35
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
26
}
36
typedef struct ARMSSEInfo ARMSSEInfo;
27
37
28
a10 = AW_A10(object_new(TYPE_AW_A10));
38
typedef struct ARMSSEClass {
29
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),
39
- DeviceClass parent_class;
30
+ &error_abort);
40
+ SysBusDeviceClass parent_class;
31
+ object_unref(OBJECT(a10));
41
const ARMSSEInfo *info;
32
42
} ARMSSEClass;
33
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
43
34
if (err != NULL) {
44
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/armsse.c
47
+++ b/hw/arm/armsse.c
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo armsse_info = {
49
.name = TYPE_ARMSSE,
50
.parent = TYPE_SYS_BUS_DEVICE,
51
.instance_size = sizeof(ARMSSE),
52
+ .class_size = sizeof(ARMSSEClass),
53
.instance_init = armsse_init,
54
.abstract = true,
55
.interfaces = (InterfaceInfo[]) {
35
--
56
--
36
2.20.1
57
2.20.1
37
58
38
59
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Let's move the code which freezes which gic-version to
3
Add left-shift to match the existing right-shift.
4
be applied in a dedicated function. We also now set by
5
default the VIRT_GIC_VERSION_NO_SET. This eventually
6
turns into the legacy v2 choice in the finalize() function.
7
4
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
7
Message-id: 20200815013145.539409-2-richard.henderson@linaro.org
11
Message-id: 20200311131618.7187-4-eric.auger@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
include/hw/arm/virt.h | 1 +
10
include/qemu/int128.h | 16 ++++++++++++++++
15
hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------
11
1 file changed, 16 insertions(+)
16
2 files changed, 34 insertions(+), 21 deletions(-)
17
12
18
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
13
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/virt.h
15
--- a/include/qemu/int128.h
21
+++ b/include/hw/arm/virt.h
16
+++ b/include/qemu/int128.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType {
17
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
23
VIRT_GIC_VERSION_HOST,
18
return a >> n;
24
VIRT_GIC_VERSION_2,
19
}
25
VIRT_GIC_VERSION_3,
20
26
+ VIRT_GIC_VERSION_NOSEL,
21
+static inline Int128 int128_lshift(Int128 a, int n)
27
} VirtGICType;
22
+{
28
23
+ return a << n;
29
typedef struct MemMapEntry {
24
+}
30
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
25
+
31
index XXXXXXX..XXXXXXX 100644
26
static inline Int128 int128_add(Int128 a, Int128 b)
32
--- a/hw/arm/virt.c
27
{
33
+++ b/hw/arm/virt.c
28
return a + b;
34
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
29
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
35
}
30
}
36
}
31
}
37
32
38
+/*
33
+static inline Int128 int128_lshift(Int128 a, int n)
39
+ * finalize_gic_version - Determines the final gic_version
40
+ * according to the gic-version property
41
+ *
42
+ * Default GIC type is v2
43
+ */
44
+static void finalize_gic_version(VirtMachineState *vms)
45
+{
34
+{
46
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
35
+ uint64_t l = a.lo << (n & 63);
47
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
36
+ if (n >= 64) {
48
+ if (!kvm_enabled()) {
37
+ return int128_make128(0, l);
49
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
38
+ } else if (n > 0) {
50
+ error_report("gic-version=host requires KVM");
39
+ return int128_make128(l, (a.hi << n) | (a.lo >> (64 - n)));
51
+ exit(1);
52
+ } else {
53
+ /* "max": currently means 3 for TCG */
54
+ vms->gic_version = VIRT_GIC_VERSION_3;
55
+ }
56
+ } else {
57
+ vms->gic_version = kvm_arm_vgic_probe();
58
+ if (!vms->gic_version) {
59
+ error_report(
60
+ "Unable to determine GIC version supported by host");
61
+ exit(1);
62
+ }
63
+ }
64
+ } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
65
+ vms->gic_version = VIRT_GIC_VERSION_2;
66
+ }
40
+ }
41
+ return a;
67
+}
42
+}
68
+
43
+
69
static void machvirt_init(MachineState *machine)
44
static inline Int128 int128_add(Int128 a, Int128 b)
70
{
45
{
71
VirtMachineState *vms = VIRT_MACHINE(machine);
46
uint64_t lo = a.lo + b.lo;
72
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
73
/* We can probe only here because during property set
74
* KVM is not available yet
75
*/
76
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
77
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
78
- if (!kvm_enabled()) {
79
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
80
- error_report("gic-version=host requires KVM");
81
- exit(1);
82
- } else {
83
- /* "max": currently means 3 for TCG */
84
- vms->gic_version = VIRT_GIC_VERSION_3;
85
- }
86
- } else {
87
- vms->gic_version = kvm_arm_vgic_probe();
88
- if (!vms->gic_version) {
89
- error_report(
90
- "Unable to determine GIC version supported by host");
91
- exit(1);
92
- }
93
- }
94
- }
95
+ finalize_gic_version(vms);
96
97
if (!cpu_type_valid(machine->cpu_type)) {
98
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
99
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
100
"Set on/off to enable/disable using "
101
"physical address space above 32 bits",
102
NULL);
103
- /* Default GIC type is v2 */
104
- vms->gic_version = VIRT_GIC_VERSION_2;
105
+ vms->gic_version = VIRT_GIC_VERSION_NOSEL;
106
object_property_add_str(obj, "gic-version", virt_get_gic_version,
107
virt_set_gic_version, NULL);
108
object_property_set_description(obj, "gic-version",
109
--
47
--
110
2.20.1
48
2.20.1
111
49
112
50
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
i.MX25 supports two USB controllers. Let's wire them up.
3
Model the new function on gen_gvec_fn2 in translate-a64.c, but
4
indicating which kind of register and in which order. Since there
5
is only one user of do_vector2_z, fold it into do_mov_z.
4
6
5
With this patch, imx25-pdk can boot from both USB ports.
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200310215146.19688-3-linux@roeck-us.net
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
include/hw/arm/fsl-imx25.h | 9 +++++++++
12
target/arm/translate-sve.c | 19 ++++++++++---------
13
hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++
13
1 file changed, 10 insertions(+), 9 deletions(-)
14
2 files changed, 33 insertions(+)
15
14
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
17
--- a/target/arm/translate-sve.c
19
+++ b/include/hw/arm/fsl-imx25.h
18
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
21
#include "hw/i2c/imx_i2c.h"
20
}
22
#include "hw/gpio/imx_gpio.h"
21
23
#include "hw/sd/sdhci.h"
22
/* Invoke a vector expander on two Zregs. */
24
+#include "hw/usb/chipidea.h"
23
-static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
25
#include "exec/memory.h"
24
- int esz, int rd, int rn)
26
#include "target/arm/cpu.h"
27
28
@@ -XXX,XX +XXX,XX @@
29
#define FSL_IMX25_NUM_I2CS 3
30
#define FSL_IMX25_NUM_GPIOS 4
31
#define FSL_IMX25_NUM_ESDHCS 2
32
+#define FSL_IMX25_NUM_USBS 2
33
34
typedef struct FslIMX25State {
35
/*< private >*/
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
38
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
39
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
40
+ ChipideaState usb[FSL_IMX25_NUM_USBS];
41
MemoryRegion rom[2];
42
MemoryRegion iram;
43
MemoryRegion iram_alias;
44
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
45
#define FSL_IMX25_GPIO1_SIZE 0x4000
46
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
47
#define FSL_IMX25_GPIO2_SIZE 0x4000
48
+#define FSL_IMX25_USB1_ADDR 0x53FF4000
49
+#define FSL_IMX25_USB1_SIZE 0x0200
50
+#define FSL_IMX25_USB2_ADDR 0x53FF4400
51
+#define FSL_IMX25_USB2_SIZE 0x0200
52
#define FSL_IMX25_AVIC_ADDR 0x68000000
53
#define FSL_IMX25_AVIC_SIZE 0x4000
54
#define FSL_IMX25_IRAM_ADDR 0x78000000
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
56
#define FSL_IMX25_GPIO4_IRQ 23
57
#define FSL_IMX25_ESDHC1_IRQ 9
58
#define FSL_IMX25_ESDHC2_IRQ 8
59
+#define FSL_IMX25_USB1_IRQ 37
60
+#define FSL_IMX25_USB2_IRQ 35
61
62
#endif /* FSL_IMX25_H */
63
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/fsl-imx25.c
66
+++ b/hw/arm/fsl-imx25.c
67
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
68
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
69
TYPE_IMX_USDHC);
70
}
71
+
25
+
72
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
26
+static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
73
+ sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
27
+ int esz, int rd, int rn)
74
+ TYPE_CHIPIDEA);
28
{
29
- if (sve_access_check(s)) {
30
- unsigned vsz = vec_full_reg_size(s);
31
- gvec_fn(esz, vec_full_reg_offset(s, rd),
32
- vec_full_reg_offset(s, rn), vsz, vsz);
33
- }
34
- return true;
35
+ unsigned vsz = vec_full_reg_size(s);
36
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
37
+ vec_full_reg_offset(s, rn), vsz, vsz);
38
}
39
40
/* Invoke a vector expander on three Zregs. */
41
@@ -XXX,XX +XXX,XX @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
42
/* Invoke a vector move on two Zregs. */
43
static bool do_mov_z(DisasContext *s, int rd, int rn)
44
{
45
- return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
46
+ if (sve_access_check(s)) {
47
+ gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
75
+ }
48
+ }
76
+
49
+ return true;
77
}
50
}
78
51
79
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
52
/* Initialize a Zreg with replications of a 64-bit immediate. */
80
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
81
esdhc_table[i].irq));
82
}
83
84
+ /* USB */
85
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
86
+ static const struct {
87
+ hwaddr addr;
88
+ unsigned int irq;
89
+ } usb_table[FSL_IMX25_NUM_USBS] = {
90
+ { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
91
+ { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
92
+ };
93
+
94
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
95
+ &error_abort);
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
97
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
98
+ qdev_get_gpio_in(DEVICE(&s->avic),
99
+ usb_table[i].irq));
100
+ }
101
+
102
/* initialize 2 x 16 KB ROM */
103
memory_region_init_rom(&s->rom[0], NULL,
104
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
105
--
53
--
106
2.20.1
54
2.20.1
107
55
108
56
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Aspeed SMC Controller can operate in different modes : Read, Fast
3
Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
4
Read, Write and User modes. When the User mode is configured, it
4
indicating which kind of register and in which order.
5
selects automatically the SPI slave device until the CE_STOP_ACTIVE
6
bit is set to 1. When any other modes are configured the device is
7
unselected. The HW logic handles the chip select automatically when
8
the flash is accessed through its AHB window.
9
5
10
When configuring the CEx Control Register, the User mode logic to
6
Model do_zzz_fn on the other do_foo functions that take an
11
select and unselect the slave is incorrect and data corruption can be
7
argument set and verify sve enabled.
12
seen on machines using two chips, witherspoon and romulus.
13
8
14
Rework the handler setting the CEx Control Register to fix this issue.
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
11
Message-id: 20200815013145.539409-4-richard.henderson@linaro.org
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
18
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
19
Message-id: 20200206112645.21275-3-clg@kaod.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
13
---
22
hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++----------------
14
target/arm/translate-sve.c | 43 +++++++++++++++++++++-----------------
23
hw/ssi/trace-events | 1 +
15
1 file changed, 24 insertions(+), 19 deletions(-)
24
2 files changed, 24 insertions(+), 16 deletions(-)
25
16
26
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
27
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/aspeed_smc.c
19
--- a/target/arm/translate-sve.c
29
+++ b/hw/ssi/aspeed_smc.c
20
+++ b/target/arm/translate-sve.c
30
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
21
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
31
}
32
}
22
}
33
23
34
-static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
24
/* Invoke a vector expander on three Zregs. */
35
+static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
25
-static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
26
- int esz, int rd, int rn, int rm)
27
+static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
28
+ int esz, int rd, int rn, int rm)
36
{
29
{
37
- const AspeedSMCState *s = fl->controller;
30
- if (sve_access_check(s)) {
38
+ AspeedSMCState *s = fl->controller;
31
- unsigned vsz = vec_full_reg_size(s);
39
32
- gvec_fn(esz, vec_full_reg_offset(s, rd),
40
- return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
33
- vec_full_reg_offset(s, rn),
41
+ trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
34
- vec_full_reg_offset(s, rm), vsz, vsz);
35
- }
36
- return true;
37
+ unsigned vsz = vec_full_reg_size(s);
38
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
39
+ vec_full_reg_offset(s, rn),
40
+ vec_full_reg_offset(s, rm), vsz, vsz);
41
}
42
43
/* Invoke a vector move on two Zregs. */
44
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
45
*** SVE Logical - Unpredicated Group
46
*/
47
48
+static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
49
+{
50
+ if (sve_access_check(s)) {
51
+ gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
52
+ }
53
+ return true;
54
+}
42
+
55
+
43
+ qemu_set_irq(s->cs_lines[fl->id], unselect);
56
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
57
{
58
- return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
59
+ return do_zzz_fn(s, a, tcg_gen_gvec_and);
44
}
60
}
45
61
46
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
62
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
47
{
63
{
48
- AspeedSMCState *s = fl->controller;
64
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
49
-
65
+ return do_zzz_fn(s, a, tcg_gen_gvec_or);
50
- s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
51
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
52
+ aspeed_smc_flash_do_select(fl, false);
53
}
66
}
54
67
55
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
68
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
56
{
69
{
57
- AspeedSMCState *s = fl->controller;
70
- return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
58
-
71
+ return do_zzz_fn(s, a, tcg_gen_gvec_xor);
59
- s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
60
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
61
+ aspeed_smc_flash_do_select(fl, true);
62
}
72
}
63
73
64
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
74
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
65
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = {
66
},
67
};
68
69
-static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
70
+static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
71
{
75
{
72
AspeedSMCState *s = fl->controller;
76
- return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
73
+ bool unselect;
77
+ return do_zzz_fn(s, a, tcg_gen_gvec_andc);
74
75
- s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START;
76
+ /* User mode selects the CS, other modes unselect */
77
+ unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
78
79
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
80
+ /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
81
+ if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
82
+ value & CTRL_CE_STOP_ACTIVE) {
83
+ unselect = true;
84
+ }
85
+
86
+ s->regs[s->r_ctrl0 + fl->id] = value;
87
+
88
+ s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
89
+
90
+ aspeed_smc_flash_do_select(fl, unselect);
91
}
78
}
92
79
93
static void aspeed_smc_reset(DeviceState *d)
80
/*
94
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
81
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
95
s->regs[addr] = value;
82
96
} else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
83
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
97
int cs = addr - s->r_ctrl0;
84
{
98
- s->regs[addr] = value;
85
- return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
99
- aspeed_smc_flash_update_cs(&s->flashes[cs]);
86
+ return do_zzz_fn(s, a, tcg_gen_gvec_add);
100
+ aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
87
}
101
} else if (addr >= R_SEG_ADDR0 &&
88
102
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
89
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
103
int cs = addr - R_SEG_ADDR0;
90
{
104
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
91
- return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
105
index XXXXXXX..XXXXXXX 100644
92
+ return do_zzz_fn(s, a, tcg_gen_gvec_sub);
106
--- a/hw/ssi/trace-events
93
}
107
+++ b/hw/ssi/trace-events
94
108
@@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int
95
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
109
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
96
{
110
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
97
- return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
111
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
98
+ return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
112
+aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
99
}
100
101
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
104
+ return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
105
}
106
107
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
108
{
109
- return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
110
+ return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
111
}
112
113
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
114
{
115
- return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
116
+ return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
117
}
118
119
/*
113
--
120
--
114
2.20.1
121
2.20.1
115
122
116
123
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We must include the tag in the FAR_ELx register when raising
3
We want to ensure that access is checked by the time we ask
4
an addressing exception. Which means that we should not clear
4
for a specific fp/vector register. We want to ensure that
5
out the tag during translation.
5
we do not emit two lots of code to raise an exception.
6
6
7
We cannot at present comply with this for user mode, so we
7
But sometimes it's difficult to cleanly organize the code
8
retain the clean_data_tbi function for the moment, though it
8
such that we never pass through sve_check_access exactly once.
9
no longer does what it says on the tin for system mode. This
9
Allow multiple calls so long as the result is true, that is,
10
function is to be replaced with MTE, so don't worry about the
10
no exception to be raised.
11
slight misnaming.
12
11
13
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200308012946.16303-3-richard.henderson@linaro.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200815013145.539409-5-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
16
---
19
target/arm/translate-a64.c | 11 +++++++++++
17
target/arm/translate.h | 1 +
20
1 file changed, 11 insertions(+)
18
target/arm/translate-a64.c | 27 ++++++++++++++++-----------
19
2 files changed, 17 insertions(+), 11 deletions(-)
21
20
21
diff --git a/target/arm/translate.h b/target/arm/translate.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/translate.h
24
+++ b/target/arm/translate.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
26
* that it is set at the point where we actually touch the FP regs.
27
*/
28
bool fp_access_checked;
29
+ bool sve_access_checked;
30
/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
31
* single-step support).
32
*/
22
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
33
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-a64.c
35
--- a/target/arm/translate-a64.c
25
+++ b/target/arm/translate-a64.c
36
+++ b/target/arm/translate-a64.c
26
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
37
@@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
27
static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
38
* unallocated-encoding checks (otherwise the syndrome information
39
* for the resulting exception will be incorrect).
40
*/
41
-static inline bool fp_access_check(DisasContext *s)
42
+static bool fp_access_check(DisasContext *s)
28
{
43
{
29
TCGv_i64 clean = new_tmp_a64(s);
44
- assert(!s->fp_access_checked);
30
+ /*
45
- s->fp_access_checked = true;
31
+ * In order to get the correct value in the FAR_ELx register,
46
+ if (s->fp_excp_el) {
32
+ * we must present the memory subsystem with the "dirty" address
47
+ assert(!s->fp_access_checked);
33
+ * including the TBI. In system mode we can make this work via
48
+ s->fp_access_checked = true;
34
+ * the TLB, dropping the TBI during translation. But for user-only
49
35
+ * mode we don't have that option, and must remove the top byte now.
50
- if (!s->fp_excp_el) {
36
+ */
51
- return true;
37
+#ifdef CONFIG_USER_ONLY
52
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
38
gen_top_byte_ignore(s, clean, addr, s->tbid);
53
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
39
+#else
54
+ return false;
40
+ tcg_gen_mov_i64(clean, addr);
55
}
41
+#endif
56
-
42
return clean;
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
58
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
59
- return false;
60
+ s->fp_access_checked = true;
61
+ return true;
43
}
62
}
44
63
64
/* Check that SVE access is enabled. If it is, return true.
65
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
66
bool sve_access_check(DisasContext *s)
67
{
68
if (s->sve_excp_el) {
69
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
70
- s->sve_excp_el);
71
+ assert(!s->sve_access_checked);
72
+ s->sve_access_checked = true;
73
+
74
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
75
+ syn_sve_access_trap(), s->sve_excp_el);
76
return false;
77
}
78
+ s->sve_access_checked = true;
79
return fp_access_check(s);
80
}
81
82
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
83
s->base.pc_next += 4;
84
85
s->fp_access_checked = false;
86
+ s->sve_access_checked = false;
87
88
if (dc_isar_feature(aa64_bti, s)) {
89
if (s->base.num_insns == 1) {
45
--
90
--
46
2.20.1
91
2.20.1
47
92
48
93
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert kvm_arm_vgic_probe() so that it returns a
3
This is the only user of the function.
4
bitmap of supported in-kernel emulation VGIC versions instead
5
of the max version: at the moment values can be v2 and v3.
6
This allows to expose the case where the host GICv3 also
7
supports GICv2 emulation. This will be useful to choose the
8
default version in KVM accelerated mode.
9
4
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200815013145.539409-6-richard.henderson@linaro.org
13
Message-id: 20200311131618.7187-5-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
9
---
16
target/arm/kvm_arm.h | 3 +++
10
target/arm/translate-sve.c | 19 ++++++-------------
17
hw/arm/virt.c | 11 +++++++++--
11
1 file changed, 6 insertions(+), 13 deletions(-)
18
target/arm/kvm.c | 14 ++++++++------
19
3 files changed, 20 insertions(+), 8 deletions(-)
20
12
21
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/kvm_arm.h
15
--- a/target/arm/translate-sve.c
24
+++ b/target/arm/kvm_arm.h
16
+++ b/target/arm/translate-sve.c
25
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
26
#include "exec/memory.h"
18
tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
27
#include "qemu/error-report.h"
19
}
28
20
29
+#define KVM_ARM_VGIC_V2 (1 << 0)
21
-/* Invoke a vector expander on two Pregs. */
30
+#define KVM_ARM_VGIC_V3 (1 << 1)
22
-static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn,
31
+
23
- int esz, int rd, int rn)
32
/**
24
-{
33
* kvm_arm_vcpu_init:
25
- if (sve_access_check(s)) {
34
* @cs: CPUState
26
- unsigned psz = pred_gvec_reg_size(s);
35
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
27
- gvec_fn(esz, pred_full_reg_offset(s, rd),
36
index XXXXXXX..XXXXXXX 100644
28
- pred_full_reg_offset(s, rn), psz, psz);
37
--- a/hw/arm/virt.c
29
- }
38
+++ b/hw/arm/virt.c
30
- return true;
39
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
31
-}
40
vms->gic_version = VIRT_GIC_VERSION_3;
32
-
41
}
33
/* Invoke a vector expander on three Pregs. */
42
} else {
34
static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
43
- vms->gic_version = kvm_arm_vgic_probe();
35
int esz, int rd, int rn, int rm)
44
- if (!vms->gic_version) {
36
@@ -XXX,XX +XXX,XX @@ static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
45
+ int probe_bitmap = kvm_arm_vgic_probe();
37
/* Invoke a vector move on two Pregs. */
46
+
38
static bool do_mov_p(DisasContext *s, int rd, int rn)
47
+ if (!probe_bitmap) {
48
error_report(
49
"Unable to determine GIC version supported by host");
50
exit(1);
51
+ } else {
52
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
53
+ vms->gic_version = VIRT_GIC_VERSION_3;
54
+ } else {
55
+ vms->gic_version = VIRT_GIC_VERSION_2;
56
+ }
57
}
58
}
59
} else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
60
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/kvm.c
63
+++ b/target/arm/kvm.c
64
@@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s)
65
66
int kvm_arm_vgic_probe(void)
67
{
39
{
68
+ int val = 0;
40
- return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn);
69
+
41
+ if (sve_access_check(s)) {
70
if (kvm_create_device(kvm_state,
42
+ unsigned psz = pred_gvec_reg_size(s);
71
KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
43
+ tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd),
72
- return 3;
44
+ pred_full_reg_offset(s, rn), psz, psz);
73
- } else if (kvm_create_device(kvm_state,
74
- KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
75
- return 2;
76
- } else {
77
- return 0;
78
+ val |= KVM_ARM_VGIC_V3;
79
}
80
+ if (kvm_create_device(kvm_state,
81
+ KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
82
+ val |= KVM_ARM_VGIC_V2;
83
+ }
45
+ }
84
+ return val;
46
+ return true;
85
}
47
}
86
48
87
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level)
49
/* Set the cpu flags as per a return from an SVE helper. */
88
--
50
--
89
2.20.1
51
2.20.1
90
52
91
53
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
3
Move the check for !S into do_pppp_flags, which allows to merge in
4
based embedded computer with mainline support in both U-Boot
4
do_vecop4_p. Split out gen_gvec_fn_ppp without sve_access_check,
5
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
5
to mirror gen_gvec_fn_zzz.
6
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
6
7
various other I/O. This commit add support for the Xunlong
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Orange Pi PC machine.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
9
Message-id: 20200815013145.539409-7-richard.henderson@linaro.org
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Acked-by: Igor Mammedov <imammedo@redhat.com>
16
Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
hw/arm/Makefile.objs | 2 +-
12
target/arm/translate-sve.c | 111 ++++++++++++++-----------------------
20
hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 43 insertions(+), 68 deletions(-)
21
MAINTAINERS | 1 +
14
22
3 files changed, 94 insertions(+), 1 deletion(-)
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
23
create mode 100644 hw/arm/orangepi.c
24
25
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/Makefile.objs
17
--- a/target/arm/translate-sve.c
28
+++ b/hw/arm/Makefile.objs
18
+++ b/target/arm/translate-sve.c
29
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
30
obj-$(CONFIG_OMAP) += omap1.o omap2.o
20
}
31
obj-$(CONFIG_STRONGARM) += strongarm.o
21
32
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
22
/* Invoke a vector expander on three Pregs. */
33
-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
23
-static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
24
- int esz, int rd, int rn, int rm)
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
25
+static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
26
+ int rd, int rn, int rm)
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
27
{
38
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
28
- if (sve_access_check(s)) {
39
new file mode 100644
29
- unsigned psz = pred_gvec_reg_size(s);
40
index XXXXXXX..XXXXXXX
30
- gvec_fn(esz, pred_full_reg_offset(s, rd),
41
--- /dev/null
31
- pred_full_reg_offset(s, rn),
42
+++ b/hw/arm/orangepi.c
32
- pred_full_reg_offset(s, rm), psz, psz);
43
@@ -XXX,XX +XXX,XX @@
33
- }
44
+/*
34
- return true;
45
+ * Orange Pi emulation
35
-}
46
+ *
36
-
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
37
-/* Invoke a vector operation on four Pregs. */
48
+ *
38
-static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
49
+ * This program is free software: you can redistribute it and/or modify
39
- int rd, int rn, int rm, int rg)
50
+ * it under the terms of the GNU General Public License as published by
40
-{
51
+ * the Free Software Foundation, either version 2 of the License, or
41
- if (sve_access_check(s)) {
52
+ * (at your option) any later version.
42
- unsigned psz = pred_gvec_reg_size(s);
53
+ *
43
- tcg_gen_gvec_4(pred_full_reg_offset(s, rd),
54
+ * This program is distributed in the hope that it will be useful,
44
- pred_full_reg_offset(s, rn),
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
45
- pred_full_reg_offset(s, rm),
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46
- pred_full_reg_offset(s, rg),
57
+ * GNU General Public License for more details.
47
- psz, psz, gvec_op);
58
+ *
48
- }
59
+ * You should have received a copy of the GNU General Public License
49
- return true;
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
50
+ unsigned psz = pred_gvec_reg_size(s);
61
+ */
51
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
62
+
52
+ pred_full_reg_offset(s, rn),
63
+#include "qemu/osdep.h"
53
+ pred_full_reg_offset(s, rm), psz, psz);
64
+#include "qemu/units.h"
54
}
65
+#include "exec/address-spaces.h"
55
66
+#include "qapi/error.h"
56
/* Invoke a vector move on two Pregs. */
67
+#include "cpu.h"
57
@@ -XXX,XX +XXX,XX @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a,
68
+#include "hw/sysbus.h"
58
int mofs = pred_full_reg_offset(s, a->rm);
69
+#include "hw/boards.h"
59
int gofs = pred_full_reg_offset(s, a->pg);
70
+#include "hw/qdev-properties.h"
60
71
+#include "hw/arm/allwinner-h3.h"
61
+ if (!a->s) {
72
+#include "sysemu/sysemu.h"
62
+ tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op);
73
+
63
+ return true;
74
+static struct arm_boot_info orangepi_binfo = {
75
+ .nb_cpus = AW_H3_NUM_CPUS,
76
+};
77
+
78
+static void orangepi_init(MachineState *machine)
79
+{
80
+ AwH3State *h3;
81
+
82
+ /* BIOS is not supported by this board */
83
+ if (bios_name) {
84
+ error_report("BIOS not supported for this machine");
85
+ exit(1);
86
+ }
64
+ }
87
+
65
+
88
+ /* This board has fixed size RAM */
66
if (psz == 8) {
89
+ if (machine->ram_size != 1 * GiB) {
67
/* Do the operation and the flags generation in temps. */
90
+ error_report("This machine can only be used with 1GiB of RAM");
68
TCGv_i64 pd = tcg_temp_new_i64();
91
+ exit(1);
69
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
92
+ }
70
.fno = gen_helper_sve_and_pppp,
93
+
71
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
94
+ /* Only allow Cortex-A7 for this board */
72
};
95
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
73
- if (a->s) {
96
+ error_report("This board can only be used with cortex-a7 CPU");
74
- return do_pppp_flags(s, a, &op);
97
+ exit(1);
75
- } else if (a->rn == a->rm) {
98
+ }
76
- if (a->pg == a->rn) {
99
+
77
- return do_mov_p(s, a->rd, a->rn);
100
+ h3 = AW_H3(object_new(TYPE_AW_H3));
78
- } else {
101
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(h3),
79
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->pg);
102
+ &error_abort);
80
+
103
+ object_unref(OBJECT(h3));
81
+ if (!a->s) {
104
+
82
+ if (!sve_access_check(s)) {
105
+ /* Setup timer properties */
83
+ return true;
106
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
84
+ }
107
+ &error_abort);
85
+ if (a->rn == a->rm) {
108
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
86
+ if (a->pg == a->rn) {
109
+ &error_abort);
87
+ do_mov_p(s, a->rd, a->rn);
110
+
88
+ } else {
111
+ /* Mark H3 object realized */
89
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
112
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
90
+ }
113
+
91
+ return true;
114
+ /* SDRAM */
92
+ } else if (a->pg == a->rn || a->pg == a->rm) {
115
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
93
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
116
+ machine->ram);
94
+ return true;
117
+
95
}
118
+ orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
96
- } else if (a->pg == a->rn || a->pg == a->rm) {
119
+ orangepi_binfo.ram_size = machine->ram_size;
97
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
120
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
98
- } else {
121
+}
99
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
122
+
100
}
123
+static void orangepi_machine_init(MachineClass *mc)
101
+ return do_pppp_flags(s, a, &op);
124
+{
102
}
125
+ mc->desc = "Orange Pi PC";
103
126
+ mc->init = orangepi_init;
104
static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
127
+ mc->min_cpus = AW_H3_NUM_CPUS;
105
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
128
+ mc->max_cpus = AW_H3_NUM_CPUS;
106
.fno = gen_helper_sve_bic_pppp,
129
+ mc->default_cpus = AW_H3_NUM_CPUS;
107
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
130
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
108
};
131
+ mc->default_ram_size = 1 * GiB;
109
- if (a->s) {
132
+ mc->default_ram_id = "orangepi.ram";
110
- return do_pppp_flags(s, a, &op);
133
+}
111
- } else if (a->pg == a->rn) {
134
+
112
- return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
135
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
113
- } else {
136
diff --git a/MAINTAINERS b/MAINTAINERS
114
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
137
index XXXXXXX..XXXXXXX 100644
115
+
138
--- a/MAINTAINERS
116
+ if (!a->s && a->pg == a->rn) {
139
+++ b/MAINTAINERS
117
+ if (sve_access_check(s)) {
140
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
118
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
141
S: Maintained
119
+ }
142
F: hw/*/allwinner-h3*
120
+ return true;
143
F: include/hw/*/allwinner-h3*
121
}
144
+F: hw/arm/orangepi.c
122
+ return do_pppp_flags(s, a, &op);
145
123
}
146
ARM PrimeCell and CMSDK devices
124
147
M: Peter Maydell <peter.maydell@linaro.org>
125
static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
126
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
127
.fno = gen_helper_sve_eor_pppp,
128
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
129
};
130
- if (a->s) {
131
- return do_pppp_flags(s, a, &op);
132
- } else {
133
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
134
- }
135
+ return do_pppp_flags(s, a, &op);
136
}
137
138
static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
139
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
140
.fno = gen_helper_sve_sel_pppp,
141
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
142
};
143
+
144
if (a->s) {
145
return false;
146
- } else {
147
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
148
}
149
+ return do_pppp_flags(s, a, &op);
150
}
151
152
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
153
@@ -XXX,XX +XXX,XX @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a)
154
.fno = gen_helper_sve_orr_pppp,
155
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
156
};
157
- if (a->s) {
158
- return do_pppp_flags(s, a, &op);
159
- } else if (a->pg == a->rn && a->rn == a->rm) {
160
+
161
+ if (!a->s && a->pg == a->rn && a->rn == a->rm) {
162
return do_mov_p(s, a->rd, a->rn);
163
- } else {
164
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
165
}
166
+ return do_pppp_flags(s, a, &op);
167
}
168
169
static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
170
@@ -XXX,XX +XXX,XX @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a)
171
.fno = gen_helper_sve_orn_pppp,
172
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
173
};
174
- if (a->s) {
175
- return do_pppp_flags(s, a, &op);
176
- } else {
177
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
178
- }
179
+ return do_pppp_flags(s, a, &op);
180
}
181
182
static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
183
@@ -XXX,XX +XXX,XX @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a)
184
.fno = gen_helper_sve_nor_pppp,
185
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
186
};
187
- if (a->s) {
188
- return do_pppp_flags(s, a, &op);
189
- } else {
190
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
191
- }
192
+ return do_pppp_flags(s, a, &op);
193
}
194
195
static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
196
@@ -XXX,XX +XXX,XX @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a)
197
.fno = gen_helper_sve_nand_pppp,
198
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
199
};
200
- if (a->s) {
201
- return do_pppp_flags(s, a, &op);
202
- } else {
203
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
204
- }
205
+ return do_pppp_flags(s, a, &op);
206
}
207
208
/*
148
--
209
--
149
2.20.1
210
2.20.1
150
211
151
212
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In the Allwinner H3 SoC the SDRAM controller is responsible
3
The gvec operation was added after the initial implementation
4
for interfacing with the external Synchronous Dynamic Random
4
of the SEL instruction and was missed in the conversion.
5
Access Memory (SDRAM). Types of memory that the SDRAM controller
6
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
7
adds emulation support of the Allwinner H3 SDRAM controller.
8
5
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
8
Message-id: 20200815013145.539409-8-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/misc/Makefile.objs | 1 +
11
target/arm/translate-sve.c | 31 ++++++++-----------------------
15
include/hw/arm/allwinner-h3.h | 5 +
12
1 file changed, 8 insertions(+), 23 deletions(-)
16
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
17
hw/arm/allwinner-h3.c | 19 +-
18
hw/arm/orangepi.c | 6 +
19
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
20
hw/misc/trace-events | 10 +
21
7 files changed, 502 insertions(+), 3 deletions(-)
22
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
23
create mode 100644 hw/misc/allwinner-h3-dramc.c
24
13
25
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
26
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/misc/Makefile.objs
16
--- a/target/arm/translate-sve.c
28
+++ b/hw/misc/Makefile.objs
17
+++ b/target/arm/translate-sve.c
29
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
18
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
30
19
return do_pppp_flags(s, a, &op);
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
32
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
33
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o
34
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
37
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/arm/allwinner-h3.h
40
+++ b/include/hw/arm/allwinner-h3.h
41
@@ -XXX,XX +XXX,XX @@
42
#include "hw/intc/arm_gic.h"
43
#include "hw/misc/allwinner-h3-ccu.h"
44
#include "hw/misc/allwinner-cpucfg.h"
45
+#include "hw/misc/allwinner-h3-dramc.h"
46
#include "hw/misc/allwinner-h3-sysctrl.h"
47
#include "hw/misc/allwinner-sid.h"
48
#include "hw/sd/allwinner-sdhost.h"
49
@@ -XXX,XX +XXX,XX @@ enum {
50
AW_H3_UART2,
51
AW_H3_UART3,
52
AW_H3_EMAC,
53
+ AW_H3_DRAMCOM,
54
+ AW_H3_DRAMCTL,
55
+ AW_H3_DRAMPHY,
56
AW_H3_GIC_DIST,
57
AW_H3_GIC_CPU,
58
AW_H3_GIC_HYP,
59
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
AwCpuCfgState cpucfg;
63
+ AwH3DramCtlState dramc;
64
AwH3SysCtrlState sysctrl;
65
AwSidState sid;
66
AwSdHostState mmc0;
67
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h
68
new file mode 100644
69
index XXXXXXX..XXXXXXX
70
--- /dev/null
71
+++ b/include/hw/misc/allwinner-h3-dramc.h
72
@@ -XXX,XX +XXX,XX @@
73
+/*
74
+ * Allwinner H3 SDRAM Controller emulation
75
+ *
76
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
77
+ *
78
+ * This program is free software: you can redistribute it and/or modify
79
+ * it under the terms of the GNU General Public License as published by
80
+ * the Free Software Foundation, either version 2 of the License, or
81
+ * (at your option) any later version.
82
+ *
83
+ * This program is distributed in the hope that it will be useful,
84
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
85
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
86
+ * GNU General Public License for more details.
87
+ *
88
+ * You should have received a copy of the GNU General Public License
89
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
90
+ */
91
+
92
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
93
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
94
+
95
+#include "qom/object.h"
96
+#include "hw/sysbus.h"
97
+#include "exec/hwaddr.h"
98
+
99
+/**
100
+ * Constants
101
+ * @{
102
+ */
103
+
104
+/** Highest register address used by DRAMCOM module */
105
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
106
+
107
+/** Total number of known DRAMCOM registers */
108
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
109
+ sizeof(uint32_t))
110
+
111
+/** Highest register address used by DRAMCTL module */
112
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
113
+
114
+/** Total number of known DRAMCTL registers */
115
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
116
+ sizeof(uint32_t))
117
+
118
+/** Highest register address used by DRAMPHY module */
119
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
120
+
121
+/** Total number of known DRAMPHY registers */
122
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
123
+ sizeof(uint32_t))
124
+
125
+/** @} */
126
+
127
+/**
128
+ * Object model
129
+ * @{
130
+ */
131
+
132
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
133
+#define AW_H3_DRAMC(obj) \
134
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
135
+
136
+/** @} */
137
+
138
+/**
139
+ * Allwinner H3 SDRAM Controller object instance state.
140
+ */
141
+typedef struct AwH3DramCtlState {
142
+ /*< private >*/
143
+ SysBusDevice parent_obj;
144
+ /*< public >*/
145
+
146
+ /** Physical base address for start of RAM */
147
+ hwaddr ram_addr;
148
+
149
+ /** Total RAM size in megabytes */
150
+ uint32_t ram_size;
151
+
152
+ /**
153
+ * @name Memory Regions
154
+ * @{
155
+ */
156
+
157
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
158
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
159
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
160
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
161
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
162
+
163
+ /** @} */
164
+
165
+ /**
166
+ * @name Hardware Registers
167
+ * @{
168
+ */
169
+
170
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
171
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
172
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
173
+
174
+ /** @} */
175
+
176
+} AwH3DramCtlState;
177
+
178
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
179
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/hw/arm/allwinner-h3.c
182
+++ b/hw/arm/allwinner-h3.c
183
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
184
[AW_H3_UART2] = 0x01c28800,
185
[AW_H3_UART3] = 0x01c28c00,
186
[AW_H3_EMAC] = 0x01c30000,
187
+ [AW_H3_DRAMCOM] = 0x01c62000,
188
+ [AW_H3_DRAMCTL] = 0x01c63000,
189
+ [AW_H3_DRAMPHY] = 0x01c65000,
190
[AW_H3_GIC_DIST] = 0x01c81000,
191
[AW_H3_GIC_CPU] = 0x01c82000,
192
[AW_H3_GIC_HYP] = 0x01c84000,
193
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
194
{ "scr", 0x01c2c400, 1 * KiB },
195
{ "gpu", 0x01c40000, 64 * KiB },
196
{ "hstmr", 0x01c60000, 4 * KiB },
197
- { "dramcom", 0x01c62000, 4 * KiB },
198
- { "dramctl0", 0x01c63000, 4 * KiB },
199
- { "dramphy0", 0x01c65000, 4 * KiB },
200
{ "spi0", 0x01c68000, 4 * KiB },
201
{ "spi1", 0x01c69000, 4 * KiB },
202
{ "csi", 0x01cb0000, 320 * KiB },
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
206
TYPE_AW_SUN8I_EMAC);
207
+
208
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
209
+ TYPE_AW_H3_DRAMC);
210
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
211
+ "ram-addr", &error_abort);
212
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
213
+ "ram-size", &error_abort);
214
}
20
}
215
21
216
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
22
-static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
217
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
23
-{
218
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
24
- tcg_gen_and_i64(pn, pn, pg);
219
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
25
- tcg_gen_andc_i64(pm, pm, pg);
220
26
- tcg_gen_or_i64(pd, pn, pm);
221
+ /* DRAMC */
27
-}
222
+ qdev_init_nofail(DEVICE(&s->dramc));
28
-
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
29
-static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn,
224
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
30
- TCGv_vec pm, TCGv_vec pg)
225
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
31
-{
226
+
32
- tcg_gen_and_vec(vece, pn, pn, pg);
227
/* Unimplemented devices */
33
- tcg_gen_andc_vec(vece, pm, pm, pg);
228
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
34
- tcg_gen_or_vec(vece, pd, pn, pm);
229
create_unimplemented_device(unimplemented[i].device_name,
35
-}
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
36
-
231
index XXXXXXX..XXXXXXX 100644
37
static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
232
--- a/hw/arm/orangepi.c
38
{
233
+++ b/hw/arm/orangepi.c
39
- static const GVecGen4 op = {
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
40
- .fni8 = gen_sel_pg_i64,
235
/* Setup EMAC properties */
41
- .fniv = gen_sel_pg_vec,
236
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
42
- .fno = gen_helper_sve_sel_pppp,
237
43
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
238
+ /* DRAMC */
44
- };
239
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
45
-
240
+ "ram-addr", &error_abort);
46
if (a->s) {
241
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",
47
return false;
242
+ &error_abort);
48
}
243
+
49
- return do_pppp_flags(s, a, &op);
244
/* Mark H3 object realized */
50
+ if (sve_access_check(s)) {
245
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
51
+ unsigned psz = pred_gvec_reg_size(s);
246
52
+ tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd),
247
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
53
+ pred_full_reg_offset(s, a->pg),
248
new file mode 100644
54
+ pred_full_reg_offset(s, a->rn),
249
index XXXXXXX..XXXXXXX
55
+ pred_full_reg_offset(s, a->rm), psz, psz);
250
--- /dev/null
251
+++ b/hw/misc/allwinner-h3-dramc.c
252
@@ -XXX,XX +XXX,XX @@
253
+/*
254
+ * Allwinner H3 SDRAM Controller emulation
255
+ *
256
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
257
+ *
258
+ * This program is free software: you can redistribute it and/or modify
259
+ * it under the terms of the GNU General Public License as published by
260
+ * the Free Software Foundation, either version 2 of the License, or
261
+ * (at your option) any later version.
262
+ *
263
+ * This program is distributed in the hope that it will be useful,
264
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
265
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
266
+ * GNU General Public License for more details.
267
+ *
268
+ * You should have received a copy of the GNU General Public License
269
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "qemu/units.h"
274
+#include "qemu/error-report.h"
275
+#include "hw/sysbus.h"
276
+#include "migration/vmstate.h"
277
+#include "qemu/log.h"
278
+#include "qemu/module.h"
279
+#include "exec/address-spaces.h"
280
+#include "hw/qdev-properties.h"
281
+#include "qapi/error.h"
282
+#include "hw/misc/allwinner-h3-dramc.h"
283
+#include "trace.h"
284
+
285
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
286
+
287
+/* DRAMCOM register offsets */
288
+enum {
289
+ REG_DRAMCOM_CR = 0x0000, /* Control Register */
290
+};
291
+
292
+/* DRAMCTL register offsets */
293
+enum {
294
+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
295
+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
296
+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */
297
+};
298
+
299
+/* DRAMCTL register flags */
300
+enum {
301
+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
302
+};
303
+
304
+enum {
305
+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
306
+};
307
+
308
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
309
+ uint8_t bank_bits, uint16_t page_size)
310
+{
311
+ /*
312
+ * This function simulates row addressing behavior when bootloader
313
+ * software attempts to detect the amount of available SDRAM. In U-Boot
314
+ * the controller is configured with the widest row addressing available.
315
+ * Then a pattern is written to RAM at an offset on the row boundary size.
316
+ * If the value read back equals the value read back from the
317
+ * start of RAM, the bootloader knows the amount of row bits.
318
+ *
319
+ * This function inserts a mirrored memory region when the configured row
320
+ * bits are not matching the actual emulated memory, to simulate the
321
+ * same behavior on hardware as expected by the bootloader.
322
+ */
323
+ uint8_t row_bits_actual = 0;
324
+
325
+ /* Calculate the actual row bits using the ram_size property */
326
+ for (uint8_t i = 8; i < 12; i++) {
327
+ if (1 << i == s->ram_size) {
328
+ row_bits_actual = i + 3;
329
+ break;
330
+ }
331
+ }
56
+ }
332
+
57
+ return true;
333
+ if (s->ram_size == (1 << (row_bits - 3))) {
58
}
334
+ /* When row bits is the expected value, remove the mirror */
59
335
+ memory_region_set_enabled(&s->row_mirror_alias, false);
60
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
336
+ trace_allwinner_h3_dramc_rowmirror_disable();
337
+
338
+ } else if (row_bits_actual) {
339
+ /* Row bits not matching ram_size, install the rows mirror */
340
+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
341
+ bank_bits)) * page_size);
342
+
343
+ memory_region_set_enabled(&s->row_mirror_alias, true);
344
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
345
+
346
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
347
+ }
348
+}
349
+
350
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
351
+ unsigned size)
352
+{
353
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
354
+ const uint32_t idx = REG_INDEX(offset);
355
+
356
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
357
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
358
+ __func__, (uint32_t)offset);
359
+ return 0;
360
+ }
361
+
362
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
363
+
364
+ return s->dramcom[idx];
365
+}
366
+
367
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
368
+ uint64_t val, unsigned size)
369
+{
370
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
371
+ const uint32_t idx = REG_INDEX(offset);
372
+
373
+ trace_allwinner_h3_dramcom_write(offset, val, size);
374
+
375
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
376
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
377
+ __func__, (uint32_t)offset);
378
+ return;
379
+ }
380
+
381
+ switch (offset) {
382
+ case REG_DRAMCOM_CR: /* Control Register */
383
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
384
+ ((val >> 2) & 0x1) + 2,
385
+ 1 << (((val >> 8) & 0xf) + 3));
386
+ break;
387
+ default:
388
+ break;
389
+ };
390
+
391
+ s->dramcom[idx] = (uint32_t) val;
392
+}
393
+
394
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
395
+ unsigned size)
396
+{
397
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
398
+ const uint32_t idx = REG_INDEX(offset);
399
+
400
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
401
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
402
+ __func__, (uint32_t)offset);
403
+ return 0;
404
+ }
405
+
406
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
407
+
408
+ return s->dramctl[idx];
409
+}
410
+
411
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
412
+ uint64_t val, unsigned size)
413
+{
414
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
415
+ const uint32_t idx = REG_INDEX(offset);
416
+
417
+ trace_allwinner_h3_dramctl_write(offset, val, size);
418
+
419
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
420
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
421
+ __func__, (uint32_t)offset);
422
+ return;
423
+ }
424
+
425
+ switch (offset) {
426
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
427
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
428
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
429
+ break;
430
+ default:
431
+ break;
432
+ }
433
+
434
+ s->dramctl[idx] = (uint32_t) val;
435
+}
436
+
437
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
438
+ unsigned size)
439
+{
440
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
441
+ const uint32_t idx = REG_INDEX(offset);
442
+
443
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
445
+ __func__, (uint32_t)offset);
446
+ return 0;
447
+ }
448
+
449
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
450
+
451
+ return s->dramphy[idx];
452
+}
453
+
454
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
455
+ uint64_t val, unsigned size)
456
+{
457
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
458
+ const uint32_t idx = REG_INDEX(offset);
459
+
460
+ trace_allwinner_h3_dramphy_write(offset, val, size);
461
+
462
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
463
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
464
+ __func__, (uint32_t)offset);
465
+ return;
466
+ }
467
+
468
+ s->dramphy[idx] = (uint32_t) val;
469
+}
470
+
471
+static const MemoryRegionOps allwinner_h3_dramcom_ops = {
472
+ .read = allwinner_h3_dramcom_read,
473
+ .write = allwinner_h3_dramcom_write,
474
+ .endianness = DEVICE_NATIVE_ENDIAN,
475
+ .valid = {
476
+ .min_access_size = 4,
477
+ .max_access_size = 4,
478
+ },
479
+ .impl.min_access_size = 4,
480
+};
481
+
482
+static const MemoryRegionOps allwinner_h3_dramctl_ops = {
483
+ .read = allwinner_h3_dramctl_read,
484
+ .write = allwinner_h3_dramctl_write,
485
+ .endianness = DEVICE_NATIVE_ENDIAN,
486
+ .valid = {
487
+ .min_access_size = 4,
488
+ .max_access_size = 4,
489
+ },
490
+ .impl.min_access_size = 4,
491
+};
492
+
493
+static const MemoryRegionOps allwinner_h3_dramphy_ops = {
494
+ .read = allwinner_h3_dramphy_read,
495
+ .write = allwinner_h3_dramphy_write,
496
+ .endianness = DEVICE_NATIVE_ENDIAN,
497
+ .valid = {
498
+ .min_access_size = 4,
499
+ .max_access_size = 4,
500
+ },
501
+ .impl.min_access_size = 4,
502
+};
503
+
504
+static void allwinner_h3_dramc_reset(DeviceState *dev)
505
+{
506
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
507
+
508
+ /* Set default values for registers */
509
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
510
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
511
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
512
+}
513
+
514
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
515
+{
516
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
517
+
518
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
519
+ for (uint8_t i = 8; i < 13; i++) {
520
+ if (1 << i == s->ram_size) {
521
+ break;
522
+ } else if (i == 12) {
523
+ error_report("%s: ram-size %u MiB is not supported",
524
+ __func__, s->ram_size);
525
+ exit(1);
526
+ }
527
+ }
528
+
529
+ /* Setup row mirror mappings */
530
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
531
+ "allwinner-h3-dramc.row-mirror",
532
+ 4 * KiB, &error_abort);
533
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
534
+ &s->row_mirror, 10);
535
+
536
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
537
+ "allwinner-h3-dramc.row-mirror-alias",
538
+ &s->row_mirror, 0, 4 * KiB);
539
+ memory_region_add_subregion_overlap(get_system_memory(),
540
+ s->ram_addr + 1 * MiB,
541
+ &s->row_mirror_alias, 10);
542
+ memory_region_set_enabled(&s->row_mirror_alias, false);
543
+}
544
+
545
+static void allwinner_h3_dramc_init(Object *obj)
546
+{
547
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
548
+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);
549
+
550
+ /* DRAMCOM registers */
551
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
552
+ &allwinner_h3_dramcom_ops, s,
553
+ TYPE_AW_H3_DRAMC, 4 * KiB);
554
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
555
+
556
+ /* DRAMCTL registers */
557
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
558
+ &allwinner_h3_dramctl_ops, s,
559
+ TYPE_AW_H3_DRAMC, 4 * KiB);
560
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
561
+
562
+ /* DRAMPHY registers */
563
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
564
+ &allwinner_h3_dramphy_ops, s,
565
+ TYPE_AW_H3_DRAMC, 4 * KiB);
566
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
567
+}
568
+
569
+static Property allwinner_h3_dramc_properties[] = {
570
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
571
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
572
+ DEFINE_PROP_END_OF_LIST()
573
+};
574
+
575
+static const VMStateDescription allwinner_h3_dramc_vmstate = {
576
+ .name = "allwinner-h3-dramc",
577
+ .version_id = 1,
578
+ .minimum_version_id = 1,
579
+ .fields = (VMStateField[]) {
580
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
581
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
582
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
583
+ VMSTATE_END_OF_LIST()
584
+ }
585
+};
586
+
587
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
588
+{
589
+ DeviceClass *dc = DEVICE_CLASS(klass);
590
+
591
+ dc->reset = allwinner_h3_dramc_reset;
592
+ dc->vmsd = &allwinner_h3_dramc_vmstate;
593
+ dc->realize = allwinner_h3_dramc_realize;
594
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
595
+}
596
+
597
+static const TypeInfo allwinner_h3_dramc_info = {
598
+ .name = TYPE_AW_H3_DRAMC,
599
+ .parent = TYPE_SYS_BUS_DEVICE,
600
+ .instance_init = allwinner_h3_dramc_init,
601
+ .instance_size = sizeof(AwH3DramCtlState),
602
+ .class_init = allwinner_h3_dramc_class_init,
603
+};
604
+
605
+static void allwinner_h3_dramc_register(void)
606
+{
607
+ type_register_static(&allwinner_h3_dramc_info);
608
+}
609
+
610
+type_init(allwinner_h3_dramc_register)
611
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
612
index XXXXXXX..XXXXXXX 100644
613
--- a/hw/misc/trace-events
614
+++ b/hw/misc/trace-events
615
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
616
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
617
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
618
619
+# allwinner-h3-dramc.c
620
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
621
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
622
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
623
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
624
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
625
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
626
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
627
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
628
+
629
# allwinner-sid.c
630
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
631
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
632
--
61
--
633
2.20.1
62
2.20.1
634
63
635
64
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
3
Model after gen_gvec_fn_zzz et al.
4
connections which provide software access using the Enhanced
5
Host Controller Interface (EHCI) and Open Host Controller
6
Interface (OHCI) interfaces. This commit adds support for
7
both interfaces in the Allwinner H3 System on Chip.
8
4
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20200815013145.539409-9-richard.henderson@linaro.org
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
9
---
17
hw/usb/hcd-ehci.h | 1 +
10
target/arm/translate-sve.c | 35 ++++++++++++++++-------------------
18
include/hw/arm/allwinner-h3.h | 8 +++++++
11
1 file changed, 16 insertions(+), 19 deletions(-)
19
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
20
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
21
hw/arm/Kconfig | 2 ++
22
5 files changed, 72 insertions(+)
23
12
24
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/usb/hcd-ehci.h
15
--- a/target/arm/translate-sve.c
27
+++ b/hw/usb/hcd-ehci.h
16
+++ b/target/arm/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState {
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
29
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
18
return size_for_gvec(pred_full_reg_size(s));
30
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
19
}
31
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
20
32
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
21
-/* Invoke a vector expander on two Zregs. */
33
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
22
+/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
34
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
23
+static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
35
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
24
+ int rd, int rn, int rm, int pg, int data)
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@ enum {
41
AW_H3_SRAM_A1,
42
AW_H3_SRAM_A2,
43
AW_H3_SRAM_C,
44
+ AW_H3_EHCI0,
45
+ AW_H3_OHCI0,
46
+ AW_H3_EHCI1,
47
+ AW_H3_OHCI1,
48
+ AW_H3_EHCI2,
49
+ AW_H3_OHCI2,
50
+ AW_H3_EHCI3,
51
+ AW_H3_OHCI3,
52
AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/allwinner-h3.c
58
+++ b/hw/arm/allwinner-h3.c
59
@@ -XXX,XX +XXX,XX @@
60
#include "hw/sysbus.h"
61
#include "hw/char/serial.h"
62
#include "hw/misc/unimp.h"
63
+#include "hw/usb/hcd-ehci.h"
64
#include "sysemu/sysemu.h"
65
#include "hw/arm/allwinner-h3.h"
66
67
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
68
[AW_H3_SRAM_A1] = 0x00000000,
69
[AW_H3_SRAM_A2] = 0x00044000,
70
[AW_H3_SRAM_C] = 0x00010000,
71
+ [AW_H3_EHCI0] = 0x01c1a000,
72
+ [AW_H3_OHCI0] = 0x01c1a400,
73
+ [AW_H3_EHCI1] = 0x01c1b000,
74
+ [AW_H3_OHCI1] = 0x01c1b400,
75
+ [AW_H3_EHCI2] = 0x01c1c000,
76
+ [AW_H3_OHCI2] = 0x01c1c400,
77
+ [AW_H3_EHCI3] = 0x01c1d000,
78
+ [AW_H3_OHCI3] = 0x01c1d400,
79
[AW_H3_CCU] = 0x01c20000,
80
[AW_H3_PIT] = 0x01c20c00,
81
[AW_H3_UART0] = 0x01c28000,
82
@@ -XXX,XX +XXX,XX @@ enum {
83
AW_H3_GIC_SPI_UART3 = 3,
84
AW_H3_GIC_SPI_TIMER0 = 18,
85
AW_H3_GIC_SPI_TIMER1 = 19,
86
+ AW_H3_GIC_SPI_EHCI0 = 72,
87
+ AW_H3_GIC_SPI_OHCI0 = 73,
88
+ AW_H3_GIC_SPI_EHCI1 = 74,
89
+ AW_H3_GIC_SPI_OHCI1 = 75,
90
+ AW_H3_GIC_SPI_EHCI2 = 76,
91
+ AW_H3_GIC_SPI_OHCI2 = 77,
92
+ AW_H3_GIC_SPI_EHCI3 = 78,
93
+ AW_H3_GIC_SPI_OHCI3 = 79,
94
};
95
96
/* Allwinner H3 general constants */
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
98
qdev_init_nofail(DEVICE(&s->ccu));
99
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
100
101
+ /* Universal Serial Bus */
102
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
103
+ qdev_get_gpio_in(DEVICE(&s->gic),
104
+ AW_H3_GIC_SPI_EHCI0));
105
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
106
+ qdev_get_gpio_in(DEVICE(&s->gic),
107
+ AW_H3_GIC_SPI_EHCI1));
108
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
109
+ qdev_get_gpio_in(DEVICE(&s->gic),
110
+ AW_H3_GIC_SPI_EHCI2));
111
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
112
+ qdev_get_gpio_in(DEVICE(&s->gic),
113
+ AW_H3_GIC_SPI_EHCI3));
114
+
115
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
116
+ qdev_get_gpio_in(DEVICE(&s->gic),
117
+ AW_H3_GIC_SPI_OHCI0));
118
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
119
+ qdev_get_gpio_in(DEVICE(&s->gic),
120
+ AW_H3_GIC_SPI_OHCI1));
121
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
122
+ qdev_get_gpio_in(DEVICE(&s->gic),
123
+ AW_H3_GIC_SPI_OHCI2));
124
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
125
+ qdev_get_gpio_in(DEVICE(&s->gic),
126
+ AW_H3_GIC_SPI_OHCI3));
127
+
128
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
129
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
130
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
131
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/usb/hcd-ehci-sysbus.c
134
+++ b/hw/usb/hcd-ehci-sysbus.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = {
136
.class_init = ehci_exynos4210_class_init,
137
};
138
139
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
140
+{
25
+{
141
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
26
+ unsigned vsz = vec_full_reg_size(s);
142
+ DeviceClass *dc = DEVICE_CLASS(oc);
27
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
143
+
28
+ vec_full_reg_offset(s, rn),
144
+ sec->capsbase = 0x0;
29
+ vec_full_reg_offset(s, rm),
145
+ sec->opregbase = 0x10;
30
+ pred_full_reg_offset(s, pg),
146
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
31
+ vsz, vsz, data, fn);
147
+}
32
+}
148
+
33
149
+static const TypeInfo ehci_aw_h3_type_info = {
34
+/* Invoke a vector expander on two Zregs. */
150
+ .name = TYPE_AW_H3_EHCI,
35
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
151
+ .parent = TYPE_SYS_BUS_EHCI,
36
int esz, int rd, int rn)
152
+ .class_init = ehci_aw_h3_class_init,
153
+};
154
+
155
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
156
{
37
{
157
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
38
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
158
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
39
159
type_register_static(&ehci_type_info);
40
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
160
type_register_static(&ehci_platform_type_info);
41
{
161
type_register_static(&ehci_exynos4210_type_info);
42
- unsigned vsz = vec_full_reg_size(s);
162
+ type_register_static(&ehci_aw_h3_type_info);
43
if (fn == NULL) {
163
type_register_static(&ehci_tegra2_type_info);
44
return false;
164
type_register_static(&ehci_ppc4xx_type_info);
45
}
165
type_register_static(&ehci_fusbh200_type_info);
46
if (sve_access_check(s)) {
166
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
47
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
167
index XXXXXXX..XXXXXXX 100644
48
- vec_full_reg_offset(s, a->rn),
168
--- a/hw/arm/Kconfig
49
- vec_full_reg_offset(s, a->rm),
169
+++ b/hw/arm/Kconfig
50
- pred_full_reg_offset(s, a->pg),
170
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
51
- vsz, vsz, 0, fn);
171
select ARM_TIMER
52
+ gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
172
select ARM_GIC
53
}
173
select UNIMP
54
return true;
174
+ select USB_OHCI
55
}
175
+ select USB_EHCI_SYSBUS
56
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
176
57
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
177
config RASPI
58
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
178
bool
59
};
60
- unsigned vsz = vec_full_reg_size(s);
61
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
62
- vec_full_reg_offset(s, rn),
63
- vec_full_reg_offset(s, rm),
64
- pred_full_reg_offset(s, pg),
65
- vsz, vsz, 0, fns[esz]);
66
+ gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
67
}
68
69
#define DO_ZPZZ(NAME, name) \
70
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
71
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
72
{
73
if (sve_access_check(s)) {
74
- unsigned vsz = vec_full_reg_size(s);
75
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
76
- vec_full_reg_offset(s, a->rn),
77
- vec_full_reg_offset(s, a->rm),
78
- pred_full_reg_offset(s, a->pg),
79
- vsz, vsz, a->esz, gen_helper_sve_splice);
80
+ gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
81
+ a->rd, a->rn, a->rm, a->pg, 0);
82
}
83
return true;
84
}
179
--
85
--
180
2.20.1
86
2.20.1
181
87
182
88
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
3
The existing clr functions have only one vector argument, and so
4
processor cores. Features and specifications include DDR2/DDR3 memory,
4
can only clear in place. The existing movz functions have two
5
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
5
vector arguments, and so can clear while moving. Merge them, with
6
various I/O modules. This commit adds support for the Allwinner H3
6
a flag that controls the sense of active vs inactive elements
7
System on Chip.
7
being cleared.
8
8
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20200815013145.539409-10-richard.henderson@linaro.org
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
13
---
16
hw/arm/Makefile.objs | 1 +
14
target/arm/helper-sve.h | 5 ---
17
include/hw/arm/allwinner-h3.h | 106 +++++++++++
15
target/arm/sve_helper.c | 70 ++++++++------------------------------
18
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
16
target/arm/translate-sve.c | 53 +++++++++++------------------
19
MAINTAINERS | 7 +
17
3 files changed, 34 insertions(+), 94 deletions(-)
20
default-configs/arm-softmmu.mak | 1 +
18
21
hw/arm/Kconfig | 8 +
19
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
22
6 files changed, 450 insertions(+)
23
create mode 100644 include/hw/arm/allwinner-h3.h
24
create mode 100644 hw/arm/allwinner-h3.c
25
26
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
27
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/Makefile.objs
21
--- a/target/arm/helper-sve.h
29
+++ b/hw/arm/Makefile.objs
22
+++ b/target/arm/helper-sve.h
30
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
31
obj-$(CONFIG_OMAP) += omap1.o omap2.o
24
DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
32
obj-$(CONFIG_STRONGARM) += strongarm.o
25
DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
33
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
26
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
27
-DEF_HELPER_FLAGS_3(sve_clr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
28
-DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
29
-DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
30
-DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
31
-
39
new file mode 100644
32
DEF_HELPER_FLAGS_4(sve_movz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
40
index XXXXXXX..XXXXXXX
33
DEF_HELPER_FLAGS_4(sve_movz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
41
--- /dev/null
34
DEF_HELPER_FLAGS_4(sve_movz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
42
+++ b/include/hw/arm/allwinner-h3.h
35
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
43
@@ -XXX,XX +XXX,XX @@
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/sve_helper.c
38
+++ b/target/arm/sve_helper.c
39
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)
40
return flags;
41
}
42
43
-/* Store zero into every active element of Zd. We will use this for two
44
- * and three-operand predicated instructions for which logic dictates a
45
- * zero result. In particular, logical shift by element size, which is
46
- * otherwise undefined on the host.
47
- *
48
- * For element sizes smaller than uint64_t, we use tables to expand
49
- * the N bits of the controlling predicate to a byte mask, and clear
50
- * those bytes.
44
+/*
51
+/*
45
+ * Allwinner H3 System on Chip emulation
52
+ * Copy Zn into Zd, and store zero into inactive elements.
46
+ *
53
+ * If inv, store zeros into the active elements.
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
54
*/
48
+ *
55
-void HELPER(sve_clr_b)(void *vd, void *vg, uint32_t desc)
49
+ * This program is free software: you can redistribute it and/or modify
56
-{
50
+ * it under the terms of the GNU General Public License as published by
57
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
51
+ * the Free Software Foundation, either version 2 of the License, or
58
- uint64_t *d = vd;
52
+ * (at your option) any later version.
59
- uint8_t *pg = vg;
53
+ *
60
- for (i = 0; i < opr_sz; i += 1) {
54
+ * This program is distributed in the hope that it will be useful,
61
- d[i] &= ~expand_pred_b(pg[H1(i)]);
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
62
- }
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
63
-}
57
+ * GNU General Public License for more details.
64
-
58
+ *
65
-void HELPER(sve_clr_h)(void *vd, void *vg, uint32_t desc)
59
+ * You should have received a copy of the GNU General Public License
66
-{
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
67
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
61
+ */
68
- uint64_t *d = vd;
62
+
69
- uint8_t *pg = vg;
70
- for (i = 0; i < opr_sz; i += 1) {
71
- d[i] &= ~expand_pred_h(pg[H1(i)]);
72
- }
73
-}
74
-
75
-void HELPER(sve_clr_s)(void *vd, void *vg, uint32_t desc)
76
-{
77
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
78
- uint64_t *d = vd;
79
- uint8_t *pg = vg;
80
- for (i = 0; i < opr_sz; i += 1) {
81
- d[i] &= ~expand_pred_s(pg[H1(i)]);
82
- }
83
-}
84
-
85
-void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc)
86
-{
87
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
88
- uint64_t *d = vd;
89
- uint8_t *pg = vg;
90
- for (i = 0; i < opr_sz; i += 1) {
91
- if (pg[H1(i)] & 1) {
92
- d[i] = 0;
93
- }
94
- }
95
-}
96
-
97
-/* Copy Zn into Zd, and store zero into inactive elements. */
98
void HELPER(sve_movz_b)(void *vd, void *vn, void *vg, uint32_t desc)
99
{
100
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
101
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
102
uint64_t *d = vd, *n = vn;
103
uint8_t *pg = vg;
104
+
105
for (i = 0; i < opr_sz; i += 1) {
106
- d[i] = n[i] & expand_pred_b(pg[H1(i)]);
107
+ d[i] = n[i] & (expand_pred_b(pg[H1(i)]) ^ inv);
108
}
109
}
110
111
void HELPER(sve_movz_h)(void *vd, void *vn, void *vg, uint32_t desc)
112
{
113
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
114
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
115
uint64_t *d = vd, *n = vn;
116
uint8_t *pg = vg;
117
+
118
for (i = 0; i < opr_sz; i += 1) {
119
- d[i] = n[i] & expand_pred_h(pg[H1(i)]);
120
+ d[i] = n[i] & (expand_pred_h(pg[H1(i)]) ^ inv);
121
}
122
}
123
124
void HELPER(sve_movz_s)(void *vd, void *vn, void *vg, uint32_t desc)
125
{
126
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
127
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
128
uint64_t *d = vd, *n = vn;
129
uint8_t *pg = vg;
130
+
131
for (i = 0; i < opr_sz; i += 1) {
132
- d[i] = n[i] & expand_pred_s(pg[H1(i)]);
133
+ d[i] = n[i] & (expand_pred_s(pg[H1(i)]) ^ inv);
134
}
135
}
136
137
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc)
138
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
139
uint64_t *d = vd, *n = vn;
140
uint8_t *pg = vg;
141
+ uint8_t inv = simd_data(desc);
142
+
143
for (i = 0; i < opr_sz; i += 1) {
144
- d[i] = n[i] & -(uint64_t)(pg[H1(i)] & 1);
145
+ d[i] = n[i] & -(uint64_t)((pg[H1(i)] ^ inv) & 1);
146
}
147
}
148
149
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-sve.c
152
+++ b/target/arm/translate-sve.c
153
@@ -XXX,XX +XXX,XX @@ static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
154
*** SVE Shift by Immediate - Predicated Group
155
*/
156
157
-/* Store zero into every active element of Zd. We will use this for two
158
- * and three-operand predicated instructions for which logic dictates a
159
- * zero result.
63
+/*
160
+/*
64
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
161
+ * Copy Zn into Zd, storing zeros into inactive elements.
65
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
162
+ * If invert, store zeros into the active elements.
66
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
163
*/
67
+ * various I/O modules.
164
-static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz)
68
+ *
165
-{
69
+ * This implementation is based on the following datasheet:
166
- static gen_helper_gvec_2 * const fns[4] = {
70
+ *
167
- gen_helper_sve_clr_b, gen_helper_sve_clr_h,
71
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
168
- gen_helper_sve_clr_s, gen_helper_sve_clr_d,
72
+ *
169
- };
73
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
170
- if (sve_access_check(s)) {
74
+ *
171
- unsigned vsz = vec_full_reg_size(s);
75
+ * https://linux-sunxi.org/H3
172
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
76
+ */
173
- pred_full_reg_offset(s, pg),
77
+
174
- vsz, vsz, 0, fns[esz]);
78
+#ifndef HW_ARM_ALLWINNER_H3_H
175
- }
79
+#define HW_ARM_ALLWINNER_H3_H
176
- return true;
80
+
177
-}
81
+#include "qom/object.h"
178
-
82
+#include "hw/arm/boot.h"
179
-/* Copy Zn into Zd, storing zeros into inactive elements. */
83
+#include "hw/timer/allwinner-a10-pit.h"
180
-static void do_movz_zpz(DisasContext *s, int rd, int rn, int pg, int esz)
84
+#include "hw/intc/arm_gic.h"
181
+static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
85
+#include "target/arm/cpu.h"
182
+ int esz, bool invert)
86
+
183
{
87
+/**
184
static gen_helper_gvec_3 * const fns[4] = {
88
+ * Allwinner H3 device list
185
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
89
+ *
186
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
90
+ * This enumeration is can be used refer to a particular device in the
187
};
91
+ * Allwinner H3 SoC. For example, the physical memory base address for
188
- unsigned vsz = vec_full_reg_size(s);
92
+ * each device can be found in the AwH3State object in the memmap member
189
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
93
+ * using the device enum value as index.
190
- vec_full_reg_offset(s, rn),
94
+ *
191
- pred_full_reg_offset(s, pg),
95
+ * @see AwH3State
192
- vsz, vsz, 0, fns[esz]);
96
+ */
193
+
97
+enum {
194
+ if (sve_access_check(s)) {
98
+ AW_H3_SRAM_A1,
195
+ unsigned vsz = vec_full_reg_size(s);
99
+ AW_H3_SRAM_A2,
196
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
100
+ AW_H3_SRAM_C,
197
+ vec_full_reg_offset(s, rn),
101
+ AW_H3_PIT,
198
+ pred_full_reg_offset(s, pg),
102
+ AW_H3_UART0,
199
+ vsz, vsz, invert, fns[esz]);
103
+ AW_H3_UART1,
104
+ AW_H3_UART2,
105
+ AW_H3_UART3,
106
+ AW_H3_GIC_DIST,
107
+ AW_H3_GIC_CPU,
108
+ AW_H3_GIC_HYP,
109
+ AW_H3_GIC_VCPU,
110
+ AW_H3_SDRAM
111
+};
112
+
113
+/** Total number of CPU cores in the H3 SoC */
114
+#define AW_H3_NUM_CPUS (4)
115
+
116
+/**
117
+ * Allwinner H3 object model
118
+ * @{
119
+ */
120
+
121
+/** Object type for the Allwinner H3 SoC */
122
+#define TYPE_AW_H3 "allwinner-h3"
123
+
124
+/** Convert input object to Allwinner H3 state object */
125
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
126
+
127
+/** @} */
128
+
129
+/**
130
+ * Allwinner H3 object
131
+ *
132
+ * This struct contains the state of all the devices
133
+ * which are currently emulated by the H3 SoC code.
134
+ */
135
+typedef struct AwH3State {
136
+ /*< private >*/
137
+ DeviceState parent_obj;
138
+ /*< public >*/
139
+
140
+ ARMCPU cpus[AW_H3_NUM_CPUS];
141
+ const hwaddr *memmap;
142
+ AwA10PITState timer;
143
+ GICState gic;
144
+ MemoryRegion sram_a1;
145
+ MemoryRegion sram_a2;
146
+ MemoryRegion sram_c;
147
+} AwH3State;
148
+
149
+#endif /* HW_ARM_ALLWINNER_H3_H */
150
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
151
new file mode 100644
152
index XXXXXXX..XXXXXXX
153
--- /dev/null
154
+++ b/hw/arm/allwinner-h3.c
155
@@ -XXX,XX +XXX,XX @@
156
+/*
157
+ * Allwinner H3 System on Chip emulation
158
+ *
159
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
160
+ *
161
+ * This program is free software: you can redistribute it and/or modify
162
+ * it under the terms of the GNU General Public License as published by
163
+ * the Free Software Foundation, either version 2 of the License, or
164
+ * (at your option) any later version.
165
+ *
166
+ * This program is distributed in the hope that it will be useful,
167
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
168
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
169
+ * GNU General Public License for more details.
170
+ *
171
+ * You should have received a copy of the GNU General Public License
172
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
173
+ */
174
+
175
+#include "qemu/osdep.h"
176
+#include "exec/address-spaces.h"
177
+#include "qapi/error.h"
178
+#include "qemu/error-report.h"
179
+#include "qemu/module.h"
180
+#include "qemu/units.h"
181
+#include "hw/qdev-core.h"
182
+#include "cpu.h"
183
+#include "hw/sysbus.h"
184
+#include "hw/char/serial.h"
185
+#include "hw/misc/unimp.h"
186
+#include "sysemu/sysemu.h"
187
+#include "hw/arm/allwinner-h3.h"
188
+
189
+/* Memory map */
190
+const hwaddr allwinner_h3_memmap[] = {
191
+ [AW_H3_SRAM_A1] = 0x00000000,
192
+ [AW_H3_SRAM_A2] = 0x00044000,
193
+ [AW_H3_SRAM_C] = 0x00010000,
194
+ [AW_H3_PIT] = 0x01c20c00,
195
+ [AW_H3_UART0] = 0x01c28000,
196
+ [AW_H3_UART1] = 0x01c28400,
197
+ [AW_H3_UART2] = 0x01c28800,
198
+ [AW_H3_UART3] = 0x01c28c00,
199
+ [AW_H3_GIC_DIST] = 0x01c81000,
200
+ [AW_H3_GIC_CPU] = 0x01c82000,
201
+ [AW_H3_GIC_HYP] = 0x01c84000,
202
+ [AW_H3_GIC_VCPU] = 0x01c86000,
203
+ [AW_H3_SDRAM] = 0x40000000
204
+};
205
+
206
+/* List of unimplemented devices */
207
+struct AwH3Unimplemented {
208
+ const char *device_name;
209
+ hwaddr base;
210
+ hwaddr size;
211
+} unimplemented[] = {
212
+ { "d-engine", 0x01000000, 4 * MiB },
213
+ { "d-inter", 0x01400000, 128 * KiB },
214
+ { "syscon", 0x01c00000, 4 * KiB },
215
+ { "dma", 0x01c02000, 4 * KiB },
216
+ { "nfdc", 0x01c03000, 4 * KiB },
217
+ { "ts", 0x01c06000, 4 * KiB },
218
+ { "keymem", 0x01c0b000, 4 * KiB },
219
+ { "lcd0", 0x01c0c000, 4 * KiB },
220
+ { "lcd1", 0x01c0d000, 4 * KiB },
221
+ { "ve", 0x01c0e000, 4 * KiB },
222
+ { "mmc0", 0x01c0f000, 4 * KiB },
223
+ { "mmc1", 0x01c10000, 4 * KiB },
224
+ { "mmc2", 0x01c11000, 4 * KiB },
225
+ { "sid", 0x01c14000, 1 * KiB },
226
+ { "crypto", 0x01c15000, 4 * KiB },
227
+ { "msgbox", 0x01c17000, 4 * KiB },
228
+ { "spinlock", 0x01c18000, 4 * KiB },
229
+ { "usb0-otg", 0x01c19000, 4 * KiB },
230
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
231
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
232
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
233
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
234
+ { "smc", 0x01c1e000, 4 * KiB },
235
+ { "ccu", 0x01c20000, 1 * KiB },
236
+ { "pio", 0x01c20800, 1 * KiB },
237
+ { "owa", 0x01c21000, 1 * KiB },
238
+ { "pwm", 0x01c21400, 1 * KiB },
239
+ { "keyadc", 0x01c21800, 1 * KiB },
240
+ { "pcm0", 0x01c22000, 1 * KiB },
241
+ { "pcm1", 0x01c22400, 1 * KiB },
242
+ { "pcm2", 0x01c22800, 1 * KiB },
243
+ { "audio", 0x01c22c00, 2 * KiB },
244
+ { "smta", 0x01c23400, 1 * KiB },
245
+ { "ths", 0x01c25000, 1 * KiB },
246
+ { "uart0", 0x01c28000, 1 * KiB },
247
+ { "uart1", 0x01c28400, 1 * KiB },
248
+ { "uart2", 0x01c28800, 1 * KiB },
249
+ { "uart3", 0x01c28c00, 1 * KiB },
250
+ { "twi0", 0x01c2ac00, 1 * KiB },
251
+ { "twi1", 0x01c2b000, 1 * KiB },
252
+ { "twi2", 0x01c2b400, 1 * KiB },
253
+ { "scr", 0x01c2c400, 1 * KiB },
254
+ { "emac", 0x01c30000, 64 * KiB },
255
+ { "gpu", 0x01c40000, 64 * KiB },
256
+ { "hstmr", 0x01c60000, 4 * KiB },
257
+ { "dramcom", 0x01c62000, 4 * KiB },
258
+ { "dramctl0", 0x01c63000, 4 * KiB },
259
+ { "dramphy0", 0x01c65000, 4 * KiB },
260
+ { "spi0", 0x01c68000, 4 * KiB },
261
+ { "spi1", 0x01c69000, 4 * KiB },
262
+ { "csi", 0x01cb0000, 320 * KiB },
263
+ { "tve", 0x01e00000, 64 * KiB },
264
+ { "hdmi", 0x01ee0000, 128 * KiB },
265
+ { "rtc", 0x01f00000, 1 * KiB },
266
+ { "r_timer", 0x01f00800, 1 * KiB },
267
+ { "r_intc", 0x01f00c00, 1 * KiB },
268
+ { "r_wdog", 0x01f01000, 1 * KiB },
269
+ { "r_prcm", 0x01f01400, 1 * KiB },
270
+ { "r_twd", 0x01f01800, 1 * KiB },
271
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
272
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
273
+ { "r_twi", 0x01f02400, 1 * KiB },
274
+ { "r_uart", 0x01f02800, 1 * KiB },
275
+ { "r_pio", 0x01f02c00, 1 * KiB },
276
+ { "r_pwm", 0x01f03800, 1 * KiB },
277
+ { "core-dbg", 0x3f500000, 128 * KiB },
278
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
279
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
280
+ { "ddr-mem", 0x40000000, 2 * GiB },
281
+ { "n-brom", 0xffff0000, 32 * KiB },
282
+ { "s-brom", 0xffff0000, 64 * KiB }
283
+};
284
+
285
+/* Per Processor Interrupts */
286
+enum {
287
+ AW_H3_GIC_PPI_MAINT = 9,
288
+ AW_H3_GIC_PPI_HYPTIMER = 10,
289
+ AW_H3_GIC_PPI_VIRTTIMER = 11,
290
+ AW_H3_GIC_PPI_SECTIMER = 13,
291
+ AW_H3_GIC_PPI_PHYSTIMER = 14
292
+};
293
+
294
+/* Shared Processor Interrupts */
295
+enum {
296
+ AW_H3_GIC_SPI_UART0 = 0,
297
+ AW_H3_GIC_SPI_UART1 = 1,
298
+ AW_H3_GIC_SPI_UART2 = 2,
299
+ AW_H3_GIC_SPI_UART3 = 3,
300
+ AW_H3_GIC_SPI_TIMER0 = 18,
301
+ AW_H3_GIC_SPI_TIMER1 = 19,
302
+};
303
+
304
+/* Allwinner H3 general constants */
305
+enum {
306
+ AW_H3_GIC_NUM_SPI = 128
307
+};
308
+
309
+static void allwinner_h3_init(Object *obj)
310
+{
311
+ AwH3State *s = AW_H3(obj);
312
+
313
+ s->memmap = allwinner_h3_memmap;
314
+
315
+ for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
316
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
317
+ ARM_CPU_TYPE_NAME("cortex-a7"),
318
+ &error_abort, NULL);
319
+ }
200
+ }
320
+
201
+ return true;
321
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
202
}
322
+ TYPE_ARM_GIC);
203
323
+
204
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
324
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
205
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
325
+ TYPE_AW_A10_PIT);
206
/* Shift by element size is architecturally valid.
326
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
207
For logical shifts, it is a zeroing operation. */
327
+ "clk0-freq", &error_abort);
208
if (a->imm >= (8 << a->esz)) {
328
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
209
- return do_clr_zp(s, a->rd, a->pg, a->esz);
329
+ "clk1-freq", &error_abort);
210
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
330
+}
211
} else {
331
+
212
return do_zpzi_ool(s, a, fns[a->esz]);
332
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
213
}
333
+{
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
334
+ AwH3State *s = AW_H3(dev);
215
/* Shift by element size is architecturally valid.
335
+ unsigned i;
216
For logical shifts, it is a zeroing operation. */
336
+
217
if (a->imm >= (8 << a->esz)) {
337
+ /* CPUs */
218
- return do_clr_zp(s, a->rd, a->pg, a->esz);
338
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
219
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
339
+
220
} else {
340
+ /* Provide Power State Coordination Interface */
221
return do_zpzi_ool(s, a, fns[a->esz]);
341
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
222
}
342
+ QEMU_PSCI_CONDUIT_HVC);
223
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
343
+
224
/* Shift by element size is architecturally valid. For arithmetic
344
+ /* Disable secondary CPUs */
225
right shift for division, it is a zeroing operation. */
345
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
226
if (a->imm >= (8 << a->esz)) {
346
+ i > 0);
227
- return do_clr_zp(s, a->rd, a->pg, a->esz);
347
+
228
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
348
+ /* All exception levels required */
229
} else {
349
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
230
return do_zpzi_ool(s, a, fns[a->esz]);
350
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
231
}
351
+
232
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
352
+ /* Mark realized */
233
353
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
234
/* Zero the inactive elements. */
354
+ }
235
gen_set_label(over);
355
+
236
- do_movz_zpz(s, a->rd, a->rd, a->pg, esz);
356
+ /* Generic Interrupt Controller */
237
- return true;
357
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
238
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false);
358
+ GIC_INTERNAL);
239
}
359
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
240
360
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
241
static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
361
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
242
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
362
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
243
363
+ qdev_init_nofail(DEVICE(&s->gic));
244
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
364
+
245
{
365
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
246
- if (sve_access_check(s)) {
366
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
247
- do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);
367
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
248
- }
368
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
249
- return true;
369
+
250
+ return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
370
+ /*
251
}
371
+ * Wire the outputs from each CPU's generic timer and the GICv3
372
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
373
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
374
+ */
375
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
376
+ DeviceState *cpudev = DEVICE(&s->cpus[i]);
377
+ int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
378
+ int irq;
379
+ /*
380
+ * Mapping from the output timer irq lines from the CPU to the
381
+ * GIC PPI inputs used for this board.
382
+ */
383
+ const int timer_irq[] = {
384
+ [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
385
+ [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
386
+ [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
387
+ [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
388
+ };
389
+
390
+ /* Connect CPU timer outputs to GIC PPI inputs */
391
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
392
+ qdev_connect_gpio_out(cpudev, irq,
393
+ qdev_get_gpio_in(DEVICE(&s->gic),
394
+ ppibase + timer_irq[irq]));
395
+ }
396
+
397
+ /* Connect GIC outputs to CPU interrupt inputs */
398
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
399
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
400
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
401
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
402
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
403
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
404
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
405
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
406
+
407
+ /* GIC maintenance signal */
408
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
409
+ qdev_get_gpio_in(DEVICE(&s->gic),
410
+ ppibase + AW_H3_GIC_PPI_MAINT));
411
+ }
412
+
413
+ /* Timer */
414
+ qdev_init_nofail(DEVICE(&s->timer));
415
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
416
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
417
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
418
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
419
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
420
+
421
+ /* SRAM */
422
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
423
+ 64 * KiB, &error_abort);
424
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
425
+ 32 * KiB, &error_abort);
426
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
427
+ 44 * KiB, &error_abort);
428
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
429
+ &s->sram_a1);
430
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
431
+ &s->sram_a2);
432
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
433
+ &s->sram_c);
434
+
435
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
436
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
437
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
438
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
439
+ /* UART1 */
440
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
441
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
442
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
443
+ /* UART2 */
444
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
445
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
446
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
447
+ /* UART3 */
448
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
449
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
450
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
451
+
452
+ /* Unimplemented devices */
453
+ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
454
+ create_unimplemented_device(unimplemented[i].device_name,
455
+ unimplemented[i].base,
456
+ unimplemented[i].size);
457
+ }
458
+}
459
+
460
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
461
+{
462
+ DeviceClass *dc = DEVICE_CLASS(oc);
463
+
464
+ dc->realize = allwinner_h3_realize;
465
+ /* Reason: uses serial_hd() in realize function */
466
+ dc->user_creatable = false;
467
+}
468
+
469
+static const TypeInfo allwinner_h3_type_info = {
470
+ .name = TYPE_AW_H3,
471
+ .parent = TYPE_DEVICE,
472
+ .instance_size = sizeof(AwH3State),
473
+ .instance_init = allwinner_h3_init,
474
+ .class_init = allwinner_h3_class_init,
475
+};
476
+
477
+static void allwinner_h3_register_types(void)
478
+{
479
+ type_register_static(&allwinner_h3_type_info);
480
+}
481
+
482
+type_init(allwinner_h3_register_types)
483
diff --git a/MAINTAINERS b/MAINTAINERS
484
index XXXXXXX..XXXXXXX 100644
485
--- a/MAINTAINERS
486
+++ b/MAINTAINERS
487
@@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner*
488
F: include/hw/*/allwinner*
489
F: hw/arm/cubieboard.c
490
491
+Allwinner-h3
492
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
493
+L: qemu-arm@nongnu.org
494
+S: Maintained
495
+F: hw/*/allwinner-h3*
496
+F: include/hw/*/allwinner-h3*
497
+
498
ARM PrimeCell and CMSDK devices
499
M: Peter Maydell <peter.maydell@linaro.org>
500
L: qemu-arm@nongnu.org
501
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
502
index XXXXXXX..XXXXXXX 100644
503
--- a/default-configs/arm-softmmu.mak
504
+++ b/default-configs/arm-softmmu.mak
505
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y
506
CONFIG_FSL_IMX7=y
507
CONFIG_FSL_IMX6UL=y
508
CONFIG_SEMIHOSTING=y
509
+CONFIG_ALLWINNER_H3=y
510
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
511
index XXXXXXX..XXXXXXX 100644
512
--- a/hw/arm/Kconfig
513
+++ b/hw/arm/Kconfig
514
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
515
select SERIAL
516
select UNIMP
517
518
+config ALLWINNER_H3
519
+ bool
520
+ select ALLWINNER_A10_PIT
521
+ select SERIAL
522
+ select ARM_TIMER
523
+ select ARM_GIC
524
+ select UNIMP
525
+
526
config RASPI
527
bool
528
select FRAMEBUFFER
529
--
252
--
530
2.20.1
253
2.20.1
531
254
532
255
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Security Identifier device found in various Allwinner System on Chip
3
Model after gen_gvec_fn_zzz et al.
4
designs gives applications a per-board unique identifier. This commit
5
adds support for the Allwinner Security Identifier using a 128-bit
6
UUID value as input.
7
4
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com
7
Message-id: 20200815013145.539409-11-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
hw/misc/Makefile.objs | 1 +
10
target/arm/translate-sve.c | 29 ++++++++++++++---------------
14
include/hw/arm/allwinner-h3.h | 3 +
11
1 file changed, 14 insertions(+), 15 deletions(-)
15
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
16
hw/arm/allwinner-h3.c | 11 ++-
17
hw/arm/orangepi.c | 8 ++
18
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
19
hw/misc/trace-events | 4 +
20
7 files changed, 254 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-sid.h
22
create mode 100644 hw/misc/allwinner-sid.c
23
12
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
15
--- a/target/arm/translate-sve.c
27
+++ b/hw/misc/Makefile.objs
16
+++ b/target/arm/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
29
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
18
return size_for_gvec(pred_full_reg_size(s));
30
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/misc/allwinner-h3-ccu.h"
42
#include "hw/misc/allwinner-cpucfg.h"
43
#include "hw/misc/allwinner-h3-sysctrl.h"
44
+#include "hw/misc/allwinner-sid.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A2,
50
AW_H3_SRAM_C,
51
AW_H3_SYSCTRL,
52
+ AW_H3_SID,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
AwH3ClockCtlState ccu;
58
AwCpuCfgState cpucfg;
59
AwH3SysCtrlState sysctrl;
60
+ AwSidState sid;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-sid.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner Security ID emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
89
+#ifndef HW_MISC_ALLWINNER_SID_H
90
+#define HW_MISC_ALLWINNER_SID_H
91
+
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
94
+#include "qemu/uuid.h"
95
+
96
+/**
97
+ * Object model
98
+ * @{
99
+ */
100
+
101
+#define TYPE_AW_SID "allwinner-sid"
102
+#define AW_SID(obj) \
103
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
104
+
105
+/** @} */
106
+
107
+/**
108
+ * Allwinner Security ID object instance state
109
+ */
110
+typedef struct AwSidState {
111
+ /*< private >*/
112
+ SysBusDevice parent_obj;
113
+ /*< public >*/
114
+
115
+ /** Maps I/O registers in physical memory */
116
+ MemoryRegion iomem;
117
+
118
+ /** Control register defines how and what to read */
119
+ uint32_t control;
120
+
121
+ /** RdKey register contains the data retrieved by the device */
122
+ uint32_t rdkey;
123
+
124
+ /** Stores the emulated device identifier */
125
+ QemuUUID identifier;
126
+
127
+} AwSidState;
128
+
129
+#endif /* HW_MISC_ALLWINNER_SID_H */
130
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/arm/allwinner-h3.c
133
+++ b/hw/arm/allwinner-h3.c
134
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
135
[AW_H3_SRAM_A2] = 0x00044000,
136
[AW_H3_SRAM_C] = 0x00010000,
137
[AW_H3_SYSCTRL] = 0x01c00000,
138
+ [AW_H3_SID] = 0x01c14000,
139
[AW_H3_EHCI0] = 0x01c1a000,
140
[AW_H3_OHCI0] = 0x01c1a400,
141
[AW_H3_EHCI1] = 0x01c1b000,
142
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
143
{ "mmc0", 0x01c0f000, 4 * KiB },
144
{ "mmc1", 0x01c10000, 4 * KiB },
145
{ "mmc2", 0x01c11000, 4 * KiB },
146
- { "sid", 0x01c14000, 1 * KiB },
147
{ "crypto", 0x01c15000, 4 * KiB },
148
{ "msgbox", 0x01c17000, 4 * KiB },
149
{ "spinlock", 0x01c18000, 4 * KiB },
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
151
152
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
153
TYPE_AW_CPUCFG);
154
+
155
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
156
+ TYPE_AW_SID);
157
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
158
+ "identifier", &error_abort);
159
}
19
}
160
20
161
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
21
+/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
162
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
22
+static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
163
qdev_init_nofail(DEVICE(&s->cpucfg));
23
+ int rd, int rn, int pg, int data)
164
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
165
166
+ /* Security Identifier */
167
+ qdev_init_nofail(DEVICE(&s->sid));
168
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
169
+
170
/* Universal Serial Bus */
171
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
172
qdev_get_gpio_in(DEVICE(&s->gic),
173
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/orangepi.c
176
+++ b/hw/arm/orangepi.c
177
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
178
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
179
&error_abort);
180
181
+ /* Setup SID properties. Currently using a default fixed SID identifier. */
182
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
183
+ qdev_prop_set_string(DEVICE(h3), "identifier",
184
+ "02c00081-1111-2222-3333-000044556677");
185
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) {
186
+ warn_report("Security Identifier value does not include H3 prefix");
187
+ }
188
+
189
/* Mark H3 object realized */
190
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
191
192
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
193
new file mode 100644
194
index XXXXXXX..XXXXXXX
195
--- /dev/null
196
+++ b/hw/misc/allwinner-sid.c
197
@@ -XXX,XX +XXX,XX @@
198
+/*
199
+ * Allwinner Security ID emulation
200
+ *
201
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
202
+ *
203
+ * This program is free software: you can redistribute it and/or modify
204
+ * it under the terms of the GNU General Public License as published by
205
+ * the Free Software Foundation, either version 2 of the License, or
206
+ * (at your option) any later version.
207
+ *
208
+ * This program is distributed in the hope that it will be useful,
209
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
210
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
211
+ * GNU General Public License for more details.
212
+ *
213
+ * You should have received a copy of the GNU General Public License
214
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
215
+ */
216
+
217
+#include "qemu/osdep.h"
218
+#include "qemu/units.h"
219
+#include "hw/sysbus.h"
220
+#include "migration/vmstate.h"
221
+#include "qemu/log.h"
222
+#include "qemu/module.h"
223
+#include "qemu/guest-random.h"
224
+#include "qapi/error.h"
225
+#include "hw/qdev-properties.h"
226
+#include "hw/misc/allwinner-sid.h"
227
+#include "trace.h"
228
+
229
+/* SID register offsets */
230
+enum {
231
+ REG_PRCTL = 0x40, /* Control */
232
+ REG_RDKEY = 0x60, /* Read Key */
233
+};
234
+
235
+/* SID register flags */
236
+enum {
237
+ REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */
238
+ REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */
239
+};
240
+
241
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
242
+ unsigned size)
243
+{
24
+{
244
+ const AwSidState *s = AW_SID(opaque);
25
+ unsigned vsz = vec_full_reg_size(s);
245
+ uint64_t val = 0;
26
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
246
+
27
+ vec_full_reg_offset(s, rn),
247
+ switch (offset) {
28
+ pred_full_reg_offset(s, pg),
248
+ case REG_PRCTL: /* Control */
29
+ vsz, vsz, data, fn);
249
+ val = s->control;
250
+ break;
251
+ case REG_RDKEY: /* Read Key */
252
+ val = s->rdkey;
253
+ break;
254
+ default:
255
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
256
+ __func__, (uint32_t)offset);
257
+ return 0;
258
+ }
259
+
260
+ trace_allwinner_sid_read(offset, val, size);
261
+
262
+ return val;
263
+}
30
+}
264
+
31
+
265
+static void allwinner_sid_write(void *opaque, hwaddr offset,
32
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
266
+ uint64_t val, unsigned size)
33
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
267
+{
34
int rd, int rn, int rm, int pg, int data)
268
+ AwSidState *s = AW_SID(opaque);
35
@@ -XXX,XX +XXX,XX @@ static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
269
+
36
return false;
270
+ trace_allwinner_sid_write(offset, val, size);
37
}
271
+
38
if (sve_access_check(s)) {
272
+ switch (offset) {
39
- unsigned vsz = vec_full_reg_size(s);
273
+ case REG_PRCTL: /* Control */
40
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
274
+ s->control = val;
41
- vec_full_reg_offset(s, a->rn),
275
+
42
- pred_full_reg_offset(s, a->pg),
276
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
43
- vsz, vsz, 0, fn);
277
+ (s->control & REG_PRCTL_WRITE)) {
44
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
278
+ uint32_t id = s->control >> 16;
45
}
279
+
46
return true;
280
+ if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) {
47
}
281
+ s->rdkey = ldl_be_p(&s->identifier.data[id]);
48
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
282
+ }
49
};
283
+ }
50
284
+ s->control &= ~REG_PRCTL_WRITE;
51
if (sve_access_check(s)) {
285
+ break;
52
- unsigned vsz = vec_full_reg_size(s);
286
+ case REG_RDKEY: /* Read Key */
53
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
287
+ break;
54
- vec_full_reg_offset(s, rn),
288
+ default:
55
- pred_full_reg_offset(s, pg),
289
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
56
- vsz, vsz, invert, fns[esz]);
290
+ __func__, (uint32_t)offset);
57
+ gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
291
+ break;
58
}
292
+ }
59
return true;
293
+}
60
}
294
+
61
@@ -XXX,XX +XXX,XX @@ static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
295
+static const MemoryRegionOps allwinner_sid_ops = {
62
gen_helper_gvec_3 *fn)
296
+ .read = allwinner_sid_read,
63
{
297
+ .write = allwinner_sid_write,
64
if (sve_access_check(s)) {
298
+ .endianness = DEVICE_NATIVE_ENDIAN,
65
- unsigned vsz = vec_full_reg_size(s);
299
+ .valid = {
66
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
300
+ .min_access_size = 4,
67
- vec_full_reg_offset(s, a->rn),
301
+ .max_access_size = 4,
68
- pred_full_reg_offset(s, a->pg),
302
+ },
69
- vsz, vsz, a->imm, fn);
303
+ .impl.min_access_size = 4,
70
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
304
+};
71
}
305
+
72
return true;
306
+static void allwinner_sid_reset(DeviceState *dev)
73
}
307
+{
308
+ AwSidState *s = AW_SID(dev);
309
+
310
+ /* Set default values for registers */
311
+ s->control = 0;
312
+ s->rdkey = 0;
313
+}
314
+
315
+static void allwinner_sid_init(Object *obj)
316
+{
317
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
318
+ AwSidState *s = AW_SID(obj);
319
+
320
+ /* Memory mapping */
321
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
322
+ TYPE_AW_SID, 1 * KiB);
323
+ sysbus_init_mmio(sbd, &s->iomem);
324
+}
325
+
326
+static Property allwinner_sid_properties[] = {
327
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
328
+ DEFINE_PROP_END_OF_LIST()
329
+};
330
+
331
+static const VMStateDescription allwinner_sid_vmstate = {
332
+ .name = "allwinner-sid",
333
+ .version_id = 1,
334
+ .minimum_version_id = 1,
335
+ .fields = (VMStateField[]) {
336
+ VMSTATE_UINT32(control, AwSidState),
337
+ VMSTATE_UINT32(rdkey, AwSidState),
338
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1),
339
+ VMSTATE_END_OF_LIST()
340
+ }
341
+};
342
+
343
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
344
+{
345
+ DeviceClass *dc = DEVICE_CLASS(klass);
346
+
347
+ dc->reset = allwinner_sid_reset;
348
+ dc->vmsd = &allwinner_sid_vmstate;
349
+ device_class_set_props(dc, allwinner_sid_properties);
350
+}
351
+
352
+static const TypeInfo allwinner_sid_info = {
353
+ .name = TYPE_AW_SID,
354
+ .parent = TYPE_SYS_BUS_DEVICE,
355
+ .instance_init = allwinner_sid_init,
356
+ .instance_size = sizeof(AwSidState),
357
+ .class_init = allwinner_sid_class_init,
358
+};
359
+
360
+static void allwinner_sid_register(void)
361
+{
362
+ type_register_static(&allwinner_sid_info);
363
+}
364
+
365
+type_init(allwinner_sid_register)
366
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
367
index XXXXXXX..XXXXXXX 100644
368
--- a/hw/misc/trace-events
369
+++ b/hw/misc/trace-events
370
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
371
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
372
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
373
374
+# allwinner-sid.c
375
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
376
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
377
+
378
# eccmemctl.c
379
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
380
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
381
--
74
--
382
2.20.1
75
2.20.1
383
76
384
77
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Various Allwinner System on Chip designs contain multiple processors
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
that can be configured and reset using the generic CPU Configuration
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
module interface. This commit adds support for the Allwinner CPU
5
Message-id: 20200815013145.539409-12-richard.henderson@linaro.org
6
configuration interface which emulates the following features:
7
8
* CPU reset
9
* CPU status
10
11
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
7
---
16
hw/misc/Makefile.objs | 1 +
8
target/arm/translate-sve.c | 53 +++++++++++++-------------------------
17
include/hw/arm/allwinner-h3.h | 3 +
9
1 file changed, 18 insertions(+), 35 deletions(-)
18
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
19
hw/arm/allwinner-h3.c | 9 +-
20
hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++
21
hw/misc/trace-events | 5 +
22
6 files changed, 351 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/misc/allwinner-cpucfg.h
24
create mode 100644 hw/misc/allwinner-cpucfg.c
25
10
26
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
27
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/misc/Makefile.objs
13
--- a/target/arm/translate-sve.c
29
+++ b/hw/misc/Makefile.objs
14
+++ b/target/arm/translate-sve.c
30
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
31
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
16
return size_for_gvec(pred_full_reg_size(s));
32
33
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
37
common-obj-$(CONFIG_NSERIES) += cbus.o
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/allwinner-h3.h
41
+++ b/include/hw/arm/allwinner-h3.h
42
@@ -XXX,XX +XXX,XX @@
43
#include "hw/timer/allwinner-a10-pit.h"
44
#include "hw/intc/arm_gic.h"
45
#include "hw/misc/allwinner-h3-ccu.h"
46
+#include "hw/misc/allwinner-cpucfg.h"
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "target/arm/cpu.h"
49
50
@@ -XXX,XX +XXX,XX @@ enum {
51
AW_H3_GIC_CPU,
52
AW_H3_GIC_HYP,
53
AW_H3_GIC_VCPU,
54
+ AW_H3_CPUCFG,
55
AW_H3_SDRAM
56
};
57
58
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
59
const hwaddr *memmap;
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
+ AwCpuCfgState cpucfg;
63
AwH3SysCtrlState sysctrl;
64
GICState gic;
65
MemoryRegion sram_a1;
66
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h
67
new file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- /dev/null
70
+++ b/include/hw/misc/allwinner-cpucfg.h
71
@@ -XXX,XX +XXX,XX @@
72
+/*
73
+ * Allwinner CPU Configuration Module emulation
74
+ *
75
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
76
+ *
77
+ * This program is free software: you can redistribute it and/or modify
78
+ * it under the terms of the GNU General Public License as published by
79
+ * the Free Software Foundation, either version 2 of the License, or
80
+ * (at your option) any later version.
81
+ *
82
+ * This program is distributed in the hope that it will be useful,
83
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
84
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
85
+ * GNU General Public License for more details.
86
+ *
87
+ * You should have received a copy of the GNU General Public License
88
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
89
+ */
90
+
91
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
92
+#define HW_MISC_ALLWINNER_CPUCFG_H
93
+
94
+#include "qom/object.h"
95
+#include "hw/sysbus.h"
96
+
97
+/**
98
+ * Object model
99
+ * @{
100
+ */
101
+
102
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
103
+#define AW_CPUCFG(obj) \
104
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
105
+
106
+/** @} */
107
+
108
+/**
109
+ * Allwinner CPU Configuration Module instance state
110
+ */
111
+typedef struct AwCpuCfgState {
112
+ /*< private >*/
113
+ SysBusDevice parent_obj;
114
+ /*< public >*/
115
+
116
+ MemoryRegion iomem;
117
+ uint32_t gen_ctrl;
118
+ uint32_t super_standby;
119
+ uint32_t entry_addr;
120
+
121
+} AwCpuCfgState;
122
+
123
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
124
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/arm/allwinner-h3.c
127
+++ b/hw/arm/allwinner-h3.c
128
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
129
[AW_H3_GIC_CPU] = 0x01c82000,
130
[AW_H3_GIC_HYP] = 0x01c84000,
131
[AW_H3_GIC_VCPU] = 0x01c86000,
132
+ [AW_H3_CPUCFG] = 0x01f01c00,
133
[AW_H3_SDRAM] = 0x40000000
134
};
135
136
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
137
{ "r_wdog", 0x01f01000, 1 * KiB },
138
{ "r_prcm", 0x01f01400, 1 * KiB },
139
{ "r_twd", 0x01f01800, 1 * KiB },
140
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
141
{ "r_cir-rx", 0x01f02000, 1 * KiB },
142
{ "r_twi", 0x01f02400, 1 * KiB },
143
{ "r_uart", 0x01f02800, 1 * KiB },
144
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
145
146
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
147
TYPE_AW_H3_SYSCTRL);
148
+
149
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
150
+ TYPE_AW_CPUCFG);
151
}
17
}
152
18
153
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
19
+/* Invoke an out-of-line helper on 3 Zregs. */
154
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
20
+static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
155
qdev_init_nofail(DEVICE(&s->sysctrl));
21
+ int rd, int rn, int rm, int data)
156
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
157
158
+ /* CPU Configuration */
159
+ qdev_init_nofail(DEVICE(&s->cpucfg));
160
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
161
+
162
/* Universal Serial Bus */
163
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
164
qdev_get_gpio_in(DEVICE(&s->gic),
165
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
166
new file mode 100644
167
index XXXXXXX..XXXXXXX
168
--- /dev/null
169
+++ b/hw/misc/allwinner-cpucfg.c
170
@@ -XXX,XX +XXX,XX @@
171
+/*
172
+ * Allwinner CPU Configuration Module emulation
173
+ *
174
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
175
+ *
176
+ * This program is free software: you can redistribute it and/or modify
177
+ * it under the terms of the GNU General Public License as published by
178
+ * the Free Software Foundation, either version 2 of the License, or
179
+ * (at your option) any later version.
180
+ *
181
+ * This program is distributed in the hope that it will be useful,
182
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
183
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
184
+ * GNU General Public License for more details.
185
+ *
186
+ * You should have received a copy of the GNU General Public License
187
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
188
+ */
189
+
190
+#include "qemu/osdep.h"
191
+#include "qemu/units.h"
192
+#include "hw/sysbus.h"
193
+#include "migration/vmstate.h"
194
+#include "qemu/log.h"
195
+#include "qemu/module.h"
196
+#include "qemu/error-report.h"
197
+#include "qemu/timer.h"
198
+#include "hw/core/cpu.h"
199
+#include "target/arm/arm-powerctl.h"
200
+#include "target/arm/cpu.h"
201
+#include "hw/misc/allwinner-cpucfg.h"
202
+#include "trace.h"
203
+
204
+/* CPUCFG register offsets */
205
+enum {
206
+ REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
207
+ REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
208
+ REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
209
+ REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
210
+ REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
211
+ REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
212
+ REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
213
+ REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
214
+ REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
215
+ REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
216
+ REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
217
+ REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
218
+ REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
219
+ REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
220
+ REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
221
+ REG_GEN_CTRL = 0x0184, /* General Control */
222
+ REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */
223
+ REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */
224
+ REG_DBG_EXTERN = 0x01E4, /* Debug External */
225
+ REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
226
+ REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
227
+ REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
228
+};
229
+
230
+/* CPUCFG register flags */
231
+enum {
232
+ CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)),
233
+ CPUX_STATUS_SMP = (1 << 0),
234
+ CPU_SYS_RESET_RELEASED = (1 << 0),
235
+ CLK_GATING_ENABLE = ((1 << 8) | 0xF),
236
+};
237
+
238
+/* CPUCFG register reset values */
239
+enum {
240
+ REG_CLK_GATING_RST = 0x0000010F,
241
+ REG_GEN_CTRL_RST = 0x00000020,
242
+ REG_SUPER_STANDBY_RST = 0x0,
243
+ REG_CNT64_CTRL_RST = 0x0,
244
+};
245
+
246
+/* CPUCFG constants */
247
+enum {
248
+ CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
249
+};
250
+
251
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
252
+{
22
+{
253
+ int ret;
23
+ unsigned vsz = vec_full_reg_size(s);
254
+
24
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
255
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
25
+ vec_full_reg_offset(s, rn),
256
+
26
+ vec_full_reg_offset(s, rm),
257
+ ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
27
+ vsz, vsz, data, fn);
258
+ if (!target_cpu) {
259
+ /*
260
+ * Called with a bogus value for cpu_id. Guest error will
261
+ * already have been logged, we can simply return here.
262
+ */
263
+ return;
264
+ }
265
+ bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
266
+
267
+ ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
268
+ CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64);
269
+ if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
270
+ error_report("%s: failed to bring up CPU %d: err %d",
271
+ __func__, cpu_id, ret);
272
+ return;
273
+ }
274
+}
28
+}
275
+
29
+
276
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
30
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
277
+ unsigned size)
31
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
278
+{
32
int rd, int rn, int pg, int data)
279
+ const AwCpuCfgState *s = AW_CPUCFG(opaque);
33
@@ -XXX,XX +XXX,XX @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
280
+ uint64_t val = 0;
34
return false;
281
+
35
}
282
+ switch (offset) {
36
if (sve_access_check(s)) {
283
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
37
- unsigned vsz = vec_full_reg_size(s);
284
+ case REG_CPU_SYS_RST: /* CPU System Reset */
38
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
285
+ val = CPU_SYS_RESET_RELEASED;
39
- vec_full_reg_offset(s, a->rn),
286
+ break;
40
- vec_full_reg_offset(s, a->rm),
287
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
41
- vsz, vsz, 0, fn);
288
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
42
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
289
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
43
}
290
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
44
return true;
291
+ val = CPUX_RESET_RELEASED;
45
}
292
+ break;
46
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
293
+ case REG_CPU0_CTRL: /* CPU#0 Control */
47
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
294
+ case REG_CPU1_CTRL: /* CPU#1 Control */
48
{
295
+ case REG_CPU2_CTRL: /* CPU#2 Control */
49
if (sve_access_check(s)) {
296
+ case REG_CPU3_CTRL: /* CPU#3 Control */
50
- unsigned vsz = vec_full_reg_size(s);
297
+ val = 0;
51
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
298
+ break;
52
- vec_full_reg_offset(s, a->rn),
299
+ case REG_CPU0_STATUS: /* CPU#0 Status */
53
- vec_full_reg_offset(s, a->rm),
300
+ case REG_CPU1_STATUS: /* CPU#1 Status */
54
- vsz, vsz, a->imm, fn);
301
+ case REG_CPU2_STATUS: /* CPU#2 Status */
55
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
302
+ case REG_CPU3_STATUS: /* CPU#3 Status */
56
}
303
+ val = CPUX_STATUS_SMP;
57
return true;
304
+ break;
58
}
305
+ case REG_CLK_GATING: /* CPU Clock Gating */
59
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
306
+ val = CLK_GATING_ENABLE;
60
return false;
307
+ break;
61
}
308
+ case REG_GEN_CTRL: /* General Control */
62
if (sve_access_check(s)) {
309
+ val = s->gen_ctrl;
63
- unsigned vsz = vec_full_reg_size(s);
310
+ break;
64
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
311
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
65
- vec_full_reg_offset(s, a->rn),
312
+ val = s->super_standby;
66
- vec_full_reg_offset(s, a->rm),
313
+ break;
67
- vsz, vsz, 0, fns[a->esz]);
314
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
68
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
315
+ val = s->entry_addr;
69
}
316
+ break;
70
return true;
317
+ case REG_DBG_EXTERN: /* Debug External */
71
}
318
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
72
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
319
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
73
};
320
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
74
321
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
75
if (sve_access_check(s)) {
322
+ __func__, (uint32_t)offset);
76
- unsigned vsz = vec_full_reg_size(s);
323
+ break;
77
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
324
+ default:
78
- vec_full_reg_offset(s, a->rn),
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
79
- vec_full_reg_offset(s, a->rm),
326
+ __func__, (uint32_t)offset);
80
- vsz, vsz, 0, fns[a->esz]);
327
+ break;
81
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
328
+ }
82
}
329
+
83
return true;
330
+ trace_allwinner_cpucfg_read(offset, val, size);
84
}
331
+
85
@@ -XXX,XX +XXX,XX @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
332
+ return val;
86
gen_helper_gvec_3 *fn)
333
+}
87
{
334
+
88
if (sve_access_check(s)) {
335
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
89
- unsigned vsz = vec_full_reg_size(s);
336
+ uint64_t val, unsigned size)
90
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
337
+{
91
- vec_full_reg_offset(s, a->rn),
338
+ AwCpuCfgState *s = AW_CPUCFG(opaque);
92
- vec_full_reg_offset(s, a->rm),
339
+
93
- vsz, vsz, data, fn);
340
+ trace_allwinner_cpucfg_write(offset, val, size);
94
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
341
+
95
}
342
+ switch (offset) {
96
return true;
343
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
97
}
344
+ case REG_CPU_SYS_RST: /* CPU System Reset */
98
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
345
+ break;
99
};
346
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
100
347
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
101
if (sve_access_check(s)) {
348
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
102
- unsigned vsz = vec_full_reg_size(s);
349
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
103
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
350
+ if (val) {
104
- vec_full_reg_offset(s, a->rn),
351
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6);
105
- vec_full_reg_offset(s, a->rm),
352
+ }
106
- vsz, vsz, 0, fns[a->u][a->sz]);
353
+ break;
107
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, 0);
354
+ case REG_CPU0_CTRL: /* CPU#0 Control */
108
}
355
+ case REG_CPU1_CTRL: /* CPU#1 Control */
109
return true;
356
+ case REG_CPU2_CTRL: /* CPU#2 Control */
110
}
357
+ case REG_CPU3_CTRL: /* CPU#3 Control */
111
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
358
+ case REG_CPU0_STATUS: /* CPU#0 Status */
112
};
359
+ case REG_CPU1_STATUS: /* CPU#1 Status */
113
360
+ case REG_CPU2_STATUS: /* CPU#2 Status */
114
if (sve_access_check(s)) {
361
+ case REG_CPU3_STATUS: /* CPU#3 Status */
115
- unsigned vsz = vec_full_reg_size(s);
362
+ case REG_CLK_GATING: /* CPU Clock Gating */
116
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
363
+ break;
117
- vec_full_reg_offset(s, a->rn),
364
+ case REG_GEN_CTRL: /* General Control */
118
- vec_full_reg_offset(s, a->rm),
365
+ s->gen_ctrl = val;
119
- vsz, vsz, a->index, fns[a->u][a->sz]);
366
+ break;
120
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->index);
367
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
121
}
368
+ s->super_standby = val;
122
return true;
369
+ break;
123
}
370
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
371
+ s->entry_addr = val;
372
+ break;
373
+ case REG_DBG_EXTERN: /* Debug External */
374
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
375
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
376
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
377
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
378
+ __func__, (uint32_t)offset);
379
+ break;
380
+ default:
381
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
382
+ __func__, (uint32_t)offset);
383
+ break;
384
+ }
385
+}
386
+
387
+static const MemoryRegionOps allwinner_cpucfg_ops = {
388
+ .read = allwinner_cpucfg_read,
389
+ .write = allwinner_cpucfg_write,
390
+ .endianness = DEVICE_NATIVE_ENDIAN,
391
+ .valid = {
392
+ .min_access_size = 4,
393
+ .max_access_size = 4,
394
+ },
395
+ .impl.min_access_size = 4,
396
+};
397
+
398
+static void allwinner_cpucfg_reset(DeviceState *dev)
399
+{
400
+ AwCpuCfgState *s = AW_CPUCFG(dev);
401
+
402
+ /* Set default values for registers */
403
+ s->gen_ctrl = REG_GEN_CTRL_RST;
404
+ s->super_standby = REG_SUPER_STANDBY_RST;
405
+ s->entry_addr = 0;
406
+}
407
+
408
+static void allwinner_cpucfg_init(Object *obj)
409
+{
410
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
411
+ AwCpuCfgState *s = AW_CPUCFG(obj);
412
+
413
+ /* Memory mapping */
414
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
415
+ TYPE_AW_CPUCFG, 1 * KiB);
416
+ sysbus_init_mmio(sbd, &s->iomem);
417
+}
418
+
419
+static const VMStateDescription allwinner_cpucfg_vmstate = {
420
+ .name = "allwinner-cpucfg",
421
+ .version_id = 1,
422
+ .minimum_version_id = 1,
423
+ .fields = (VMStateField[]) {
424
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
425
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
426
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
427
+ VMSTATE_END_OF_LIST()
428
+ }
429
+};
430
+
431
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
432
+{
433
+ DeviceClass *dc = DEVICE_CLASS(klass);
434
+
435
+ dc->reset = allwinner_cpucfg_reset;
436
+ dc->vmsd = &allwinner_cpucfg_vmstate;
437
+}
438
+
439
+static const TypeInfo allwinner_cpucfg_info = {
440
+ .name = TYPE_AW_CPUCFG,
441
+ .parent = TYPE_SYS_BUS_DEVICE,
442
+ .instance_init = allwinner_cpucfg_init,
443
+ .instance_size = sizeof(AwCpuCfgState),
444
+ .class_init = allwinner_cpucfg_class_init,
445
+};
446
+
447
+static void allwinner_cpucfg_register(void)
448
+{
449
+ type_register_static(&allwinner_cpucfg_info);
450
+}
451
+
452
+type_init(allwinner_cpucfg_register)
453
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
454
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/misc/trace-events
456
+++ b/hw/misc/trace-events
457
@@ -XXX,XX +XXX,XX @@
458
# See docs/devel/tracing.txt for syntax documentation.
459
460
+# allwinner-cpucfg.c
461
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32
462
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
463
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
464
+
465
# eccmemctl.c
466
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
467
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
468
--
124
--
469
2.20.1
125
2.20.1
470
126
471
127
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner H3 System on Chip has an System Control
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
module that provides system wide generic controls and
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
device information. This commit adds support for the
5
Message-id: 20200815013145.539409-13-richard.henderson@linaro.org
6
Allwinner H3 System Control module.
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
7
---
15
hw/misc/Makefile.objs | 1 +
8
target/arm/translate-sve.c | 20 ++++++++++++--------
16
include/hw/arm/allwinner-h3.h | 3 +
9
1 file changed, 12 insertions(+), 8 deletions(-)
17
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
19
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
20
5 files changed, 219 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
22
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
23
10
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
13
--- a/target/arm/translate-sve.c
27
+++ b/hw/misc/Makefile.objs
14
+++ b/target/arm/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
29
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
16
return size_for_gvec(pred_full_reg_size(s));
30
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/timer/allwinner-a10-pit.h"
42
#include "hw/intc/arm_gic.h"
43
#include "hw/misc/allwinner-h3-ccu.h"
44
+#include "hw/misc/allwinner-h3-sysctrl.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_SYSCTRL,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
const hwaddr *memmap;
58
AwA10PITState timer;
59
AwH3ClockCtlState ccu;
60
+ AwH3SysCtrlState sysctrl;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner H3 System Control emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
89
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
90
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
91
+
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
94
+
95
+/**
96
+ * @name Constants
97
+ * @{
98
+ */
99
+
100
+/** Highest register address used by System Control device */
101
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
105
+ sizeof(uint32_t)) + 1)
106
+
107
+/** @} */
108
+
109
+/**
110
+ * @name Object model
111
+ * @{
112
+ */
113
+
114
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
115
+#define AW_H3_SYSCTRL(obj) \
116
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
117
+
118
+/** @} */
119
+
120
+/**
121
+ * Allwinner H3 System Control object instance state
122
+ */
123
+typedef struct AwH3SysCtrlState {
124
+ /*< private >*/
125
+ SysBusDevice parent_obj;
126
+ /*< public >*/
127
+
128
+ /** Maps I/O registers in physical memory */
129
+ MemoryRegion iomem;
130
+
131
+ /** Array of hardware registers */
132
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
133
+
134
+} AwH3SysCtrlState;
135
+
136
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
137
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/hw/arm/allwinner-h3.c
140
+++ b/hw/arm/allwinner-h3.c
141
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
142
[AW_H3_SRAM_A1] = 0x00000000,
143
[AW_H3_SRAM_A2] = 0x00044000,
144
[AW_H3_SRAM_C] = 0x00010000,
145
+ [AW_H3_SYSCTRL] = 0x01c00000,
146
[AW_H3_EHCI0] = 0x01c1a000,
147
[AW_H3_OHCI0] = 0x01c1a400,
148
[AW_H3_EHCI1] = 0x01c1b000,
149
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
150
} unimplemented[] = {
151
{ "d-engine", 0x01000000, 4 * MiB },
152
{ "d-inter", 0x01400000, 128 * KiB },
153
- { "syscon", 0x01c00000, 4 * KiB },
154
{ "dma", 0x01c02000, 4 * KiB },
155
{ "nfdc", 0x01c03000, 4 * KiB },
156
{ "ts", 0x01c06000, 4 * KiB },
157
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
158
159
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
160
TYPE_AW_H3_CCU);
161
+
162
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
163
+ TYPE_AW_H3_SYSCTRL);
164
}
17
}
165
18
166
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
19
+/* Invoke an out-of-line helper on 2 Zregs. */
167
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
20
+static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
168
qdev_init_nofail(DEVICE(&s->ccu));
21
+ int rd, int rn, int data)
169
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
170
171
+ /* System Control */
172
+ qdev_init_nofail(DEVICE(&s->sysctrl));
173
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
174
+
175
/* Universal Serial Bus */
176
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
177
qdev_get_gpio_in(DEVICE(&s->gic),
178
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
179
new file mode 100644
180
index XXXXXXX..XXXXXXX
181
--- /dev/null
182
+++ b/hw/misc/allwinner-h3-sysctrl.c
183
@@ -XXX,XX +XXX,XX @@
184
+/*
185
+ * Allwinner H3 System Control emulation
186
+ *
187
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
188
+ *
189
+ * This program is free software: you can redistribute it and/or modify
190
+ * it under the terms of the GNU General Public License as published by
191
+ * the Free Software Foundation, either version 2 of the License, or
192
+ * (at your option) any later version.
193
+ *
194
+ * This program is distributed in the hope that it will be useful,
195
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
196
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
197
+ * GNU General Public License for more details.
198
+ *
199
+ * You should have received a copy of the GNU General Public License
200
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
201
+ */
202
+
203
+#include "qemu/osdep.h"
204
+#include "qemu/units.h"
205
+#include "hw/sysbus.h"
206
+#include "migration/vmstate.h"
207
+#include "qemu/log.h"
208
+#include "qemu/module.h"
209
+#include "hw/misc/allwinner-h3-sysctrl.h"
210
+
211
+/* System Control register offsets */
212
+enum {
213
+ REG_VER = 0x24, /* Version */
214
+ REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
215
+};
216
+
217
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
218
+
219
+/* System Control register reset values */
220
+enum {
221
+ REG_VER_RST = 0x0,
222
+ REG_EMAC_PHY_CLK_RST = 0x58000,
223
+};
224
+
225
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
226
+ unsigned size)
227
+{
22
+{
228
+ const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
23
+ unsigned vsz = vec_full_reg_size(s);
229
+ const uint32_t idx = REG_INDEX(offset);
24
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
230
+
25
+ vec_full_reg_offset(s, rn),
231
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
26
+ vsz, vsz, data, fn);
232
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
233
+ __func__, (uint32_t)offset);
234
+ return 0;
235
+ }
236
+
237
+ return s->regs[idx];
238
+}
27
+}
239
+
28
+
240
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
29
/* Invoke an out-of-line helper on 3 Zregs. */
241
+ uint64_t val, unsigned size)
30
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
242
+{
31
int rd, int rn, int rm, int data)
243
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
32
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
244
+ const uint32_t idx = REG_INDEX(offset);
33
return false;
245
+
34
}
246
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
35
if (sve_access_check(s)) {
247
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
36
- unsigned vsz = vec_full_reg_size(s);
248
+ __func__, (uint32_t)offset);
37
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
249
+ return;
38
- vec_full_reg_offset(s, a->rn),
250
+ }
39
- vsz, vsz, 0, fns[a->esz]);
251
+
40
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
252
+ switch (offset) {
41
}
253
+ case REG_VER: /* Version */
42
return true;
254
+ break;
43
}
255
+ default:
44
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
256
+ s->regs[idx] = (uint32_t) val;
45
};
257
+ break;
46
258
+ }
47
if (sve_access_check(s)) {
259
+}
48
- unsigned vsz = vec_full_reg_size(s);
260
+
49
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
261
+static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
50
- vec_full_reg_offset(s, a->rn),
262
+ .read = allwinner_h3_sysctrl_read,
51
- vsz, vsz, 0, fns[a->esz]);
263
+ .write = allwinner_h3_sysctrl_write,
52
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
264
+ .endianness = DEVICE_NATIVE_ENDIAN,
53
}
265
+ .valid = {
54
return true;
266
+ .min_access_size = 4,
55
}
267
+ .max_access_size = 4,
268
+ },
269
+ .impl.min_access_size = 4,
270
+};
271
+
272
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
273
+{
274
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
275
+
276
+ /* Set default values for registers */
277
+ s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
278
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
279
+}
280
+
281
+static void allwinner_h3_sysctrl_init(Object *obj)
282
+{
283
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
284
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
285
+
286
+ /* Memory mapping */
287
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
288
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
289
+ sysbus_init_mmio(sbd, &s->iomem);
290
+}
291
+
292
+static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
293
+ .name = "allwinner-h3-sysctrl",
294
+ .version_id = 1,
295
+ .minimum_version_id = 1,
296
+ .fields = (VMStateField[]) {
297
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
298
+ VMSTATE_END_OF_LIST()
299
+ }
300
+};
301
+
302
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
303
+{
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
305
+
306
+ dc->reset = allwinner_h3_sysctrl_reset;
307
+ dc->vmsd = &allwinner_h3_sysctrl_vmstate;
308
+}
309
+
310
+static const TypeInfo allwinner_h3_sysctrl_info = {
311
+ .name = TYPE_AW_H3_SYSCTRL,
312
+ .parent = TYPE_SYS_BUS_DEVICE,
313
+ .instance_init = allwinner_h3_sysctrl_init,
314
+ .instance_size = sizeof(AwH3SysCtrlState),
315
+ .class_init = allwinner_h3_sysctrl_class_init,
316
+};
317
+
318
+static void allwinner_h3_sysctrl_register(void)
319
+{
320
+ type_register_static(&allwinner_h3_sysctrl_info);
321
+}
322
+
323
+type_init(allwinner_h3_sysctrl_register)
324
--
56
--
325
2.20.1
57
2.20.1
326
58
327
59
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We fail to validate the upper bits of a virtual address on a
3
Rather than require the user to fill in the immediate (shl or shr),
4
translation disabled regime, as per AArch64.TranslateAddressS1Off.
4
create full formats that include the immediate.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200308012946.16303-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-14-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++-
11
target/arm/sve.decode | 35 ++++++++++++++++-------------------
12
1 file changed, 34 insertions(+), 1 deletion(-)
12
1 file changed, 16 insertions(+), 19 deletions(-)
13
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
16
--- a/target/arm/sve.decode
17
+++ b/target/arm/helper.c
17
+++ b/target/arm/sve.decode
18
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
18
@@ -XXX,XX +XXX,XX @@
19
/* Definitely a real MMU, not an MPU */
19
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
20
20
21
if (regime_translation_disabled(env, mmu_idx)) {
21
# Two register operand, one immediate operand, with predicate,
22
- /* MMU disabled. */
22
-# element size encoded as TSZHL. User must fill in imm.
23
+ /*
23
-@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
24
+ * MMU disabled. S1 addresses within aa64 translation regimes are
24
- &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
25
+ * still checked for bounds -- see AArch64.TranslateAddressS1Off.
25
+# element size encoded as TSZHL.
26
+ */
26
+@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
27
+ if (mmu_idx != ARMMMUIdx_Stage2) {
27
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
28
+ int r_el = regime_el(env, mmu_idx);
28
+@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
29
+ if (arm_el_is_aa64(env, r_el)) {
29
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
30
+ int pamax = arm_pamax(env_archcpu(env));
30
31
+ uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
31
# Similarly without predicate.
32
+ int addrtop, tbi;
32
-@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
33
+
33
- &rri_esz esz=%tszimm16_esz
34
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
34
+@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
35
+ if (access_type == MMU_INST_FETCH) {
35
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
36
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
36
+@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
37
+ }
37
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
38
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
38
39
+ addrtop = (tbi ? 55 : 63);
39
# Two register operand, one immediate operand, with 4-bit predicate.
40
+
40
# User must fill in imm.
41
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
41
@@ -XXX,XX +XXX,XX @@ UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
42
+ fi->type = ARMFault_AddressSize;
42
### SVE Shift by Immediate - Predicated Group
43
+ fi->level = 0;
43
44
+ fi->stage2 = false;
44
# SVE bitwise shift by immediate (predicated)
45
+ return 1;
45
-ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
46
+ }
46
- @rdn_pg_tszimm imm=%tszimm_shr
47
+
47
-LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
48
+ /*
48
- @rdn_pg_tszimm imm=%tszimm_shr
49
+ * When TBI is disabled, we've just validated that all of the
49
-LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
50
+ * bits above PAMax are zero, so logically we only need to
50
- @rdn_pg_tszimm imm=%tszimm_shl
51
+ * clear the top byte for TBI. But it's clearer to follow
51
-ASRD 00000100 .. 000 100 100 ... .. ... ..... \
52
+ * the pseudocode set of addrdesc.paddress.
52
- @rdn_pg_tszimm imm=%tszimm_shr
53
+ */
53
+ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
54
+ address = extract64(address, 0, 52);
54
+LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
55
+ }
55
+LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
56
+ }
56
+ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
57
*phys_ptr = address;
57
58
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
58
# SVE bitwise shift by vector (predicated)
59
*page_size = TARGET_PAGE_SIZE;
59
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
60
@@ -XXX,XX +XXX,XX @@ RDVL 00000100 101 11111 01010 imm:s6 rd:5
61
### SVE Bitwise Shift - Unpredicated Group
62
63
# SVE bitwise shift by immediate (unpredicated)
64
-ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
65
- @rd_rn_tszimm imm=%tszimm16_shr
66
-LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
67
- @rd_rn_tszimm imm=%tszimm16_shr
68
-LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
69
- @rd_rn_tszimm imm=%tszimm16_shl
70
+ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
71
+LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
72
+LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
73
74
# SVE bitwise shift by wide elements (unpredicated)
75
# Note esz != 3
60
--
76
--
61
2.20.1
77
2.20.1
62
78
63
79
diff view generated by jsdifflib
1
Some of an M-profile CPU's cached hflags state depends on state that's
1
From: Richard Henderson <richard.henderson@linaro.org>
2
in our NVIC object. We already do an hflags rebuild when the NVIC
3
registers are written, but we also need to do this on NVIC reset,
4
because there's no guarantee that this will happen before the
5
CPU reset.
6
2
7
This fixes an assertion due to mismatched hflags which happens if
3
Unify add/sub helpers and add a parameter for rounding.
8
the CPU is reset from inside a HardFault handler.
4
This will allow saturating non-rounding to reuse this code.
9
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
[PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-15-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200303174950.3298-2-peter.maydell@linaro.org
13
---
11
---
14
hw/intc/armv7m_nvic.c | 6 ++++++
12
target/arm/vec_helper.c | 80 +++++++++++++++--------------------------
15
1 file changed, 6 insertions(+)
13
1 file changed, 29 insertions(+), 51 deletions(-)
16
14
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
17
--- a/target/arm/vec_helper.c
20
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/vec_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
19
@@ -XXX,XX +XXX,XX @@
22
s->itns[i] = true;
20
#endif
23
}
21
22
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
23
-static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
24
- int16_t src3, uint32_t *sat)
25
+static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3,
26
+ bool neg, bool round, uint32_t *sat)
27
{
28
- /* Simplify:
29
+ /*
30
+ * Simplify:
31
* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
32
* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
33
*/
34
int32_t ret = (int32_t)src1 * src2;
35
- ret = ((int32_t)src3 << 15) + ret + (1 << 14);
36
+ if (neg) {
37
+ ret = -ret;
38
+ }
39
+ ret += ((int32_t)src3 << 15) + (round << 14);
40
ret >>= 15;
41
+
42
if (ret != (int16_t)ret) {
43
*sat = 1;
44
- ret = (ret < 0 ? -0x8000 : 0x7fff);
45
+ ret = (ret < 0 ? INT16_MIN : INT16_MAX);
24
}
46
}
47
return ret;
48
}
49
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
50
uint32_t src2, uint32_t src3)
51
{
52
uint32_t *sat = &env->vfp.qc[0];
53
- uint16_t e1 = inl_qrdmlah_s16(src1, src2, src3, sat);
54
- uint16_t e2 = inl_qrdmlah_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
55
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat);
56
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
57
+ false, true, sat);
58
return deposit32(e1, 16, 16, e2);
59
}
60
61
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
62
uintptr_t i;
63
64
for (i = 0; i < opr_sz / 2; ++i) {
65
- d[i] = inl_qrdmlah_s16(n[i], m[i], d[i], vq);
66
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq);
67
}
68
clear_tail(d, opr_sz, simd_maxsz(desc));
69
}
70
71
-/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
72
-static int16_t inl_qrdmlsh_s16(int16_t src1, int16_t src2,
73
- int16_t src3, uint32_t *sat)
74
-{
75
- /* Similarly, using subtraction:
76
- * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
77
- * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
78
- */
79
- int32_t ret = (int32_t)src1 * src2;
80
- ret = ((int32_t)src3 << 15) - ret + (1 << 14);
81
- ret >>= 15;
82
- if (ret != (int16_t)ret) {
83
- *sat = 1;
84
- ret = (ret < 0 ? -0x8000 : 0x7fff);
85
- }
86
- return ret;
87
-}
88
-
89
uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
90
uint32_t src2, uint32_t src3)
91
{
92
uint32_t *sat = &env->vfp.qc[0];
93
- uint16_t e1 = inl_qrdmlsh_s16(src1, src2, src3, sat);
94
- uint16_t e2 = inl_qrdmlsh_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
95
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat);
96
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
97
+ true, true, sat);
98
return deposit32(e1, 16, 16, e2);
99
}
100
101
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
102
uintptr_t i;
103
104
for (i = 0; i < opr_sz / 2; ++i) {
105
- d[i] = inl_qrdmlsh_s16(n[i], m[i], d[i], vq);
106
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq);
107
}
108
clear_tail(d, opr_sz, simd_maxsz(desc));
109
}
110
111
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
112
-static int32_t inl_qrdmlah_s32(int32_t src1, int32_t src2,
113
- int32_t src3, uint32_t *sat)
114
+static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
115
+ bool neg, bool round, uint32_t *sat)
116
{
117
/* Simplify similarly to int_qrdmlah_s16 above. */
118
int64_t ret = (int64_t)src1 * src2;
119
- ret = ((int64_t)src3 << 31) + ret + (1 << 30);
120
+ if (neg) {
121
+ ret = -ret;
122
+ }
123
+ ret += ((int64_t)src3 << 31) + (round << 30);
124
ret >>= 31;
25
+
125
+
26
+ /*
126
if (ret != (int32_t)ret) {
27
+ * We updated state that affects the CPU's MMUidx and thus its hflags;
127
*sat = 1;
28
+ * and we can't guarantee that we run before the CPU reset function.
128
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
29
+ */
129
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
30
+ arm_rebuild_hflags(&s->cpu->env);
130
int32_t src2, int32_t src3)
131
{
132
uint32_t *sat = &env->vfp.qc[0];
133
- return inl_qrdmlah_s32(src1, src2, src3, sat);
134
+ return do_sqrdmlah_s(src1, src2, src3, false, true, sat);
31
}
135
}
32
136
33
static void nvic_systick_trigger(void *opaque, int n, int level)
137
void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
138
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
139
uintptr_t i;
140
141
for (i = 0; i < opr_sz / 4; ++i) {
142
- d[i] = inl_qrdmlah_s32(n[i], m[i], d[i], vq);
143
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq);
144
}
145
clear_tail(d, opr_sz, simd_maxsz(desc));
146
}
147
148
-/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
149
-static int32_t inl_qrdmlsh_s32(int32_t src1, int32_t src2,
150
- int32_t src3, uint32_t *sat)
151
-{
152
- /* Simplify similarly to int_qrdmlsh_s16 above. */
153
- int64_t ret = (int64_t)src1 * src2;
154
- ret = ((int64_t)src3 << 31) - ret + (1 << 30);
155
- ret >>= 31;
156
- if (ret != (int32_t)ret) {
157
- *sat = 1;
158
- ret = (ret < 0 ? INT32_MIN : INT32_MAX);
159
- }
160
- return ret;
161
-}
162
-
163
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
164
int32_t src2, int32_t src3)
165
{
166
uint32_t *sat = &env->vfp.qc[0];
167
- return inl_qrdmlsh_s32(src1, src2, src3, sat);
168
+ return do_sqrdmlah_s(src1, src2, src3, true, true, sat);
169
}
170
171
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
172
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
173
uintptr_t i;
174
175
for (i = 0; i < opr_sz / 4; ++i) {
176
- d[i] = inl_qrdmlsh_s32(n[i], m[i], d[i], vq);
177
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq);
178
}
179
clear_tail(d, opr_sz, simd_maxsz(desc));
180
}
34
--
181
--
35
2.20.1
182
2.20.1
36
183
37
184
diff view generated by jsdifflib
Deleted patch
1
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
2
(it changes the NegPri bit). We update the hflags after calls
3
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
4
in trans_CPS_v7m().
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200303174950.3298-3-peter.maydell@linaro.org
9
---
10
target/arm/translate.c | 5 ++++-
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
18
19
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
20
{
21
- TCGv_i32 tmp, addr;
22
+ TCGv_i32 tmp, addr, el;
23
24
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
25
return false;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
27
gen_helper_v7m_msr(cpu_env, addr, tmp);
28
tcg_temp_free_i32(addr);
29
}
30
+ el = tcg_const_i32(s->current_el);
31
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
32
+ tcg_temp_free_i32(el);
33
tcg_temp_free_i32(tmp);
34
gen_lookup_tb(s);
35
return true;
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Joel Stanley <joel@jms.id.au>
5
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20200206112645.21275-2-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
7
---
10
Makefile.objs | 1 +
8
target/arm/helper.h | 4 ++++
11
hw/ssi/aspeed_smc.c | 17 +++++++++++++++++
9
target/arm/translate-a64.c | 16 ++++++++++++++++
12
hw/ssi/trace-events | 9 +++++++++
10
target/arm/vec_helper.c | 29 +++++++++++++++++++++++++----
13
3 files changed, 27 insertions(+)
11
3 files changed, 45 insertions(+), 4 deletions(-)
14
create mode 100644 hw/ssi/trace-events
15
12
16
diff --git a/Makefile.objs b/Makefile.objs
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/Makefile.objs
15
--- a/target/arm/helper.h
19
+++ b/Makefile.objs
16
+++ b/target/arm/helper.h
20
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
21
trace-events-subdirs += hw/sd
18
DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
22
trace-events-subdirs += hw/sparc
19
DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
23
trace-events-subdirs += hw/sparc64
20
24
+trace-events-subdirs += hw/ssi
21
+DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
25
trace-events-subdirs += hw/timer
22
+DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
26
trace-events-subdirs += hw/tpm
23
+DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
27
trace-events-subdirs += hw/usb
24
+
28
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
25
#ifdef TARGET_AARCH64
26
#include "helper-a64.h"
27
#include "helper-sve.h"
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/ssi/aspeed_smc.c
30
--- a/target/arm/translate-a64.c
31
+++ b/hw/ssi/aspeed_smc.c
31
+++ b/target/arm/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
33
#include "qapi/error.h"
33
data, gen_helper_gvec_fmlal_idx_a64);
34
#include "exec/address-spaces.h"
34
}
35
#include "qemu/units.h"
35
return;
36
+#include "trace.h"
37
38
#include "hw/irq.h"
39
#include "hw/qdev-properties.h"
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
41
42
s->ctrl->reg_to_segment(s, new, &seg);
43
44
+ trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
45
+
36
+
46
/* The start address of CS0 is read-only */
37
+ case 0x08: /* MUL */
47
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
38
+ if (!is_long && !is_scalar) {
48
qemu_log_mask(LOG_GUEST_ERROR,
39
+ static gen_helper_gvec_3 * const fns[3] = {
49
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
40
+ gen_helper_gvec_mul_idx_h,
50
__func__, aspeed_smc_flash_mode(fl));
41
+ gen_helper_gvec_mul_idx_s,
42
+ gen_helper_gvec_mul_idx_d,
43
+ };
44
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
45
+ vec_full_reg_offset(s, rn),
46
+ vec_full_reg_offset(s, rm),
47
+ is_q ? 16 : 8, vec_full_reg_size(s),
48
+ index, fns[size - 1]);
49
+ return;
50
+ }
51
+ break;
51
}
52
}
52
53
53
+ trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
54
if (size == 3) {
54
+ aspeed_smc_flash_mode(fl));
55
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
55
return ret;
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/vec_helper.c
58
+++ b/target/arm/vec_helper.c
59
@@ -XXX,XX +XXX,XX @@ DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
60
*/
61
62
#define DO_MUL_IDX(NAME, TYPE, H) \
63
+void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
64
+{ \
65
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
66
+ intptr_t idx = simd_data(desc); \
67
+ TYPE *d = vd, *n = vn, *m = vm; \
68
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
69
+ TYPE mm = m[H(i + idx)]; \
70
+ for (j = 0; j < segment; j++) { \
71
+ d[i + j] = n[i + j] * mm; \
72
+ } \
73
+ } \
74
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
75
+}
76
+
77
+DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2)
78
+DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4)
79
+DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
80
+
81
+#undef DO_MUL_IDX
82
+
83
+#define DO_FMUL_IDX(NAME, TYPE, H) \
84
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
85
{ \
86
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
87
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
88
clear_tail(d, oprsz, simd_maxsz(desc)); \
56
}
89
}
57
90
58
@@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
91
-DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
59
AspeedSMCState *s = fl->controller;
92
-DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
60
uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
93
-DO_MUL_IDX(gvec_fmul_idx_d, float64, )
61
94
+DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2)
62
+ trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
95
+DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4)
63
+ (uint8_t) data & 0xff);
96
+DO_FMUL_IDX(gvec_fmul_idx_d, float64, )
64
+
97
65
if (s->snoop_index == SNOOP_OFF) {
98
-#undef DO_MUL_IDX
66
return false; /* Do nothing */
99
+#undef DO_FMUL_IDX
67
100
68
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
101
#define DO_FMLA_IDX(NAME, TYPE, H) \
69
AspeedSMCState *s = fl->controller;
102
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
70
int i;
71
72
+ trace_aspeed_smc_flash_write(fl->id, addr, size, data,
73
+ aspeed_smc_flash_mode(fl));
74
+
75
if (!aspeed_smc_is_writable(fl)) {
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
77
HWADDR_PRIx "\n", __func__, addr);
78
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
79
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
80
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
81
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
82
+
83
+ trace_aspeed_smc_read(addr, size, s->regs[addr]);
84
+
85
return s->regs[addr];
86
} else {
87
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
88
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
89
__func__, s->regs[R_DMA_FLASH_ADDR]);
90
return;
91
}
92
+ trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
93
94
/*
95
* When the DMA is on-going, the DMA registers are updated
96
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
97
98
addr >>= 2;
99
100
+ trace_aspeed_smc_write(addr, size, data);
101
+
102
if (addr == s->r_conf ||
103
(addr >= s->r_timings &&
104
addr < s->r_timings + s->ctrl->nregs_timings) ||
105
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
106
new file mode 100644
107
index XXXXXXX..XXXXXXX
108
--- /dev/null
109
+++ b/hw/ssi/trace-events
110
@@ -XXX,XX +XXX,XX @@
111
+# aspeed_smc.c
112
+
113
+aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
114
+aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
115
+aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
116
+aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
117
+aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
118
+aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
119
+aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
120
--
103
--
121
2.20.1
104
2.20.1
122
105
123
106
diff view generated by jsdifflib
1
A write to the CONTROL register can change our current EL (by
1
From: Richard Henderson <richard.henderson@linaro.org>
2
writing to the nPRIV bit). That means that we can't assume
3
that s->current_el is still valid in trans_MSR_v7m() when
4
we try to rebuild the hflags.
5
2
6
Add a new helper rebuild_hflags_m32_newel() which, like the
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
existing rebuild_hflags_a32_newel(), recalculates the current
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
EL from scratch, and use it in trans_MSR_v7m().
5
Message-id: 20200815013145.539409-20-richard.henderson@linaro.org
9
10
This fixes an assertion about an hflags mismatch when the
11
guest changes privilege by writing to CONTROL.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200303174950.3298-4-peter.maydell@linaro.org
16
---
7
---
17
target/arm/helper.h | 1 +
8
target/arm/helper.h | 14 ++++++++++++++
18
target/arm/helper.c | 12 ++++++++++++
9
target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
19
target/arm/translate.c | 7 +++----
10
target/arm/vec_helper.c | 25 +++++++++++++++++++++++++
20
3 files changed, 16 insertions(+), 4 deletions(-)
11
3 files changed, 73 insertions(+)
21
12
22
diff --git a/target/arm/helper.h b/target/arm/helper.h
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.h
15
--- a/target/arm/helper.h
25
+++ b/target/arm/helper.h
16
+++ b/target/arm/helper.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
27
DEF_HELPER_2(get_user_reg, i32, env, i32)
18
DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
28
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
19
DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
29
20
30
+DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env)
21
+DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG,
31
DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
22
+ void, ptr, ptr, ptr, ptr, i32)
32
DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
23
+DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG,
33
DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
24
+ void, ptr, ptr, ptr, ptr, i32)
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
+DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG,
26
+ void, ptr, ptr, ptr, ptr, i32)
27
+
28
+DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG,
29
+ void, ptr, ptr, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
31
+ void, ptr, ptr, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
33
+ void, ptr, ptr, ptr, ptr, i32)
34
+
35
#ifdef TARGET_AARCH64
36
#include "helper-a64.h"
37
#include "helper-sve.h"
38
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
40
--- a/target/arm/translate-a64.c
37
+++ b/target/arm/helper.c
41
+++ b/target/arm/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env)
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
39
env->hflags = rebuild_hflags_internal(env);
43
return;
40
}
44
}
41
45
break;
42
+/*
46
+
43
+ * If we have triggered a EL state change we can't rely on the
47
+ case 0x10: /* MLA */
44
+ * translator having passed it to us, we need to recompute.
48
+ if (!is_long && !is_scalar) {
45
+ */
49
+ static gen_helper_gvec_4 * const fns[3] = {
46
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
50
+ gen_helper_gvec_mla_idx_h,
47
+{
51
+ gen_helper_gvec_mla_idx_s,
48
+ int el = arm_current_el(env);
52
+ gen_helper_gvec_mla_idx_d,
49
+ int fp_el = fp_exception_el(env, el);
53
+ };
50
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
54
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
51
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
55
+ vec_full_reg_offset(s, rn),
56
+ vec_full_reg_offset(s, rm),
57
+ vec_full_reg_offset(s, rd),
58
+ is_q ? 16 : 8, vec_full_reg_size(s),
59
+ index, fns[size - 1]);
60
+ return;
61
+ }
62
+ break;
63
+
64
+ case 0x14: /* MLS */
65
+ if (!is_long && !is_scalar) {
66
+ static gen_helper_gvec_4 * const fns[3] = {
67
+ gen_helper_gvec_mls_idx_h,
68
+ gen_helper_gvec_mls_idx_s,
69
+ gen_helper_gvec_mls_idx_d,
70
+ };
71
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
72
+ vec_full_reg_offset(s, rn),
73
+ vec_full_reg_offset(s, rm),
74
+ vec_full_reg_offset(s, rd),
75
+ is_q ? 16 : 8, vec_full_reg_size(s),
76
+ index, fns[size - 1]);
77
+ return;
78
+ }
79
+ break;
80
}
81
82
if (size == 3) {
83
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/vec_helper.c
86
+++ b/target/arm/vec_helper.c
87
@@ -XXX,XX +XXX,XX @@ DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
88
89
#undef DO_MUL_IDX
90
91
+#define DO_MLA_IDX(NAME, TYPE, OP, H) \
92
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
93
+{ \
94
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
95
+ intptr_t idx = simd_data(desc); \
96
+ TYPE *d = vd, *n = vn, *m = vm, *a = va; \
97
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
98
+ TYPE mm = m[H(i + idx)]; \
99
+ for (j = 0; j < segment; j++) { \
100
+ d[i + j] = a[i + j] OP n[i + j] * mm; \
101
+ } \
102
+ } \
103
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
52
+}
104
+}
53
+
105
+
54
void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
106
+DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2)
55
{
107
+DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4)
56
int fp_el = fp_exception_el(env, el);
108
+DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, )
57
diff --git a/target/arm/translate.c b/target/arm/translate.c
109
+
58
index XXXXXXX..XXXXXXX 100644
110
+DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2)
59
--- a/target/arm/translate.c
111
+DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4)
60
+++ b/target/arm/translate.c
112
+DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
61
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
113
+
62
114
+#undef DO_MLA_IDX
63
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
115
+
64
{
116
#define DO_FMUL_IDX(NAME, TYPE, H) \
65
- TCGv_i32 addr, reg, el;
117
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
66
+ TCGv_i32 addr, reg;
118
{ \
67
68
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
69
return false;
70
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
71
gen_helper_v7m_msr(cpu_env, addr, reg);
72
tcg_temp_free_i32(addr);
73
tcg_temp_free_i32(reg);
74
- el = tcg_const_i32(s->current_el);
75
- gen_helper_rebuild_hflags_m32(cpu_env, el);
76
- tcg_temp_free_i32(el);
77
+ /* If we wrote to CONTROL, the EL might have changed */
78
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
79
gen_lookup_tb(s);
80
return true;
81
}
82
--
119
--
83
2.20.1
120
2.20.1
84
121
85
122
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Clock Control Unit is responsible for clock signal generation,
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
configuration and distribution in the Allwinner H3 System on Chip.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
This commit adds support for the Clock Control Unit which emulates
5
Message-id: 20200815013145.539409-21-richard.henderson@linaro.org
6
a simple read/write register interface.
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
7
---
15
hw/misc/Makefile.objs | 1 +
8
target/arm/helper.h | 10 ++++++++
16
include/hw/arm/allwinner-h3.h | 3 +
9
target/arm/translate-a64.c | 33 ++++++++++++++++++--------
17
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
10
target/arm/vec_helper.c | 48 ++++++++++++++++++++++++++++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
11
3 files changed, 81 insertions(+), 10 deletions(-)
19
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
20
5 files changed, 320 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
22
create mode 100644 hw/misc/allwinner-h3-ccu.c
23
12
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
15
--- a/target/arm/helper.h
27
+++ b/hw/misc/Makefile.objs
16
+++ b/target/arm/helper.h
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
29
18
DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
30
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
19
void, ptr, ptr, ptr, ptr, i32)
31
20
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
21
+DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG,
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
22
+ void, ptr, ptr, ptr, ptr, i32)
34
common-obj-$(CONFIG_NSERIES) += cbus.o
23
+DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG,
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
24
+ void, ptr, ptr, ptr, ptr, i32)
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
25
+
26
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG,
27
+ void, ptr, ptr, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG,
29
+ void, ptr, ptr, ptr, ptr, i32)
30
+
31
#ifdef TARGET_AARCH64
32
#include "helper-a64.h"
33
#include "helper-sve.h"
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
37
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
36
--- a/target/arm/translate-a64.c
39
+++ b/include/hw/arm/allwinner-h3.h
37
+++ b/target/arm/translate-a64.c
40
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
41
#include "hw/arm/boot.h"
39
tcg_temp_free_ptr(fpst);
42
#include "hw/timer/allwinner-a10-pit.h"
40
}
43
#include "hw/intc/arm_gic.h"
41
44
+#include "hw/misc/allwinner-h3-ccu.h"
42
+/* Expand a 3-operand + qc + operation using an out-of-line helper. */
45
#include "target/arm/cpu.h"
43
+static void gen_gvec_op3_qc(DisasContext *s, bool is_q, int rd, int rn,
46
44
+ int rm, gen_helper_gvec_3_ptr *fn)
47
/**
45
+{
48
@@ -XXX,XX +XXX,XX @@ enum {
46
+ TCGv_ptr qc_ptr = tcg_temp_new_ptr();
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
AW_H3_UART1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
ARMCPU cpus[AW_H3_NUM_CPUS];
58
const hwaddr *memmap;
59
AwA10PITState timer;
60
+ AwH3ClockCtlState ccu;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-ccu.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner H3 Clock Control Unit emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
47
+
89
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
48
+ tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc));
90
+#define HW_MISC_ALLWINNER_H3_CCU_H
49
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
91
+
50
+ vec_full_reg_offset(s, rn),
92
+#include "qom/object.h"
51
+ vec_full_reg_offset(s, rm), qc_ptr,
93
+#include "hw/sysbus.h"
52
+ is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
94
+
53
+ tcg_temp_free_ptr(qc_ptr);
95
+/**
96
+ * @name Constants
97
+ * @{
98
+ */
99
+
100
+/** Size of register I/O address space used by CCU device */
101
+#define AW_H3_CCU_IOSIZE (0x400)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
105
+
106
+/** @} */
107
+
108
+/**
109
+ * @name Object model
110
+ * @{
111
+ */
112
+
113
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
114
+#define AW_H3_CCU(obj) \
115
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
116
+
117
+/** @} */
118
+
119
+/**
120
+ * Allwinner H3 CCU object instance state.
121
+ */
122
+typedef struct AwH3ClockCtlState {
123
+ /*< private >*/
124
+ SysBusDevice parent_obj;
125
+ /*< public >*/
126
+
127
+ /** Maps I/O registers in physical memory */
128
+ MemoryRegion iomem;
129
+
130
+ /** Array of hardware registers */
131
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
132
+
133
+} AwH3ClockCtlState;
134
+
135
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
136
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/arm/allwinner-h3.c
139
+++ b/hw/arm/allwinner-h3.c
140
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
141
[AW_H3_SRAM_A1] = 0x00000000,
142
[AW_H3_SRAM_A2] = 0x00044000,
143
[AW_H3_SRAM_C] = 0x00010000,
144
+ [AW_H3_CCU] = 0x01c20000,
145
[AW_H3_PIT] = 0x01c20c00,
146
[AW_H3_UART0] = 0x01c28000,
147
[AW_H3_UART1] = 0x01c28400,
148
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
149
{ "usb2-phy", 0x01c1c000, 4 * KiB },
150
{ "usb3-phy", 0x01c1d000, 4 * KiB },
151
{ "smc", 0x01c1e000, 4 * KiB },
152
- { "ccu", 0x01c20000, 1 * KiB },
153
{ "pio", 0x01c20800, 1 * KiB },
154
{ "owa", 0x01c21000, 1 * KiB },
155
{ "pwm", 0x01c21400, 1 * KiB },
156
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
157
"clk0-freq", &error_abort);
158
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
159
"clk1-freq", &error_abort);
160
+
161
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
162
+ TYPE_AW_H3_CCU);
163
}
164
165
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
166
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
168
&s->sram_c);
169
170
+ /* Clock Control Unit */
171
+ qdev_init_nofail(DEVICE(&s->ccu));
172
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
173
+
174
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
175
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
176
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
177
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
178
new file mode 100644
179
index XXXXXXX..XXXXXXX
180
--- /dev/null
181
+++ b/hw/misc/allwinner-h3-ccu.c
182
@@ -XXX,XX +XXX,XX @@
183
+/*
184
+ * Allwinner H3 Clock Control Unit emulation
185
+ *
186
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
187
+ *
188
+ * This program is free software: you can redistribute it and/or modify
189
+ * it under the terms of the GNU General Public License as published by
190
+ * the Free Software Foundation, either version 2 of the License, or
191
+ * (at your option) any later version.
192
+ *
193
+ * This program is distributed in the hope that it will be useful,
194
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
195
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196
+ * GNU General Public License for more details.
197
+ *
198
+ * You should have received a copy of the GNU General Public License
199
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
200
+ */
201
+
202
+#include "qemu/osdep.h"
203
+#include "qemu/units.h"
204
+#include "hw/sysbus.h"
205
+#include "migration/vmstate.h"
206
+#include "qemu/log.h"
207
+#include "qemu/module.h"
208
+#include "hw/misc/allwinner-h3-ccu.h"
209
+
210
+/* CCU register offsets */
211
+enum {
212
+ REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
213
+ REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
214
+ REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
215
+ REG_PLL_VE = 0x0018, /* PLL VE Control */
216
+ REG_PLL_DDR = 0x0020, /* PLL DDR Control */
217
+ REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
218
+ REG_PLL_GPU = 0x0038, /* PLL GPU Control */
219
+ REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
220
+ REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
221
+ REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
222
+ REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
223
+ REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
224
+ REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
225
+ REG_MBUS = 0x00FC, /* MBUS Reset */
226
+ REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
227
+ REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
228
+ REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
229
+ REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
230
+ REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
231
+ REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
232
+ REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
233
+ REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
234
+ REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
235
+ REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
236
+ REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
237
+ REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
238
+ REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
239
+};
240
+
241
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
242
+
243
+/* CCU register flags */
244
+enum {
245
+ REG_DRAM_CFG_UPDATE = (1 << 16),
246
+};
247
+
248
+enum {
249
+ REG_PLL_ENABLE = (1 << 31),
250
+ REG_PLL_LOCK = (1 << 28),
251
+};
252
+
253
+
254
+/* CCU register reset values */
255
+enum {
256
+ REG_PLL_CPUX_RST = 0x00001000,
257
+ REG_PLL_AUDIO_RST = 0x00035514,
258
+ REG_PLL_VIDEO_RST = 0x03006207,
259
+ REG_PLL_VE_RST = 0x03006207,
260
+ REG_PLL_DDR_RST = 0x00001000,
261
+ REG_PLL_PERIPH0_RST = 0x00041811,
262
+ REG_PLL_GPU_RST = 0x03006207,
263
+ REG_PLL_PERIPH1_RST = 0x00041811,
264
+ REG_PLL_DE_RST = 0x03006207,
265
+ REG_CPUX_AXI_RST = 0x00010000,
266
+ REG_APB1_RST = 0x00001010,
267
+ REG_APB2_RST = 0x01000000,
268
+ REG_DRAM_CFG_RST = 0x00000000,
269
+ REG_MBUS_RST = 0x80000000,
270
+ REG_PLL_TIME0_RST = 0x000000FF,
271
+ REG_PLL_TIME1_RST = 0x000000FF,
272
+ REG_PLL_CPUX_BIAS_RST = 0x08100200,
273
+ REG_PLL_AUDIO_BIAS_RST = 0x10100000,
274
+ REG_PLL_VIDEO_BIAS_RST = 0x10100000,
275
+ REG_PLL_VE_BIAS_RST = 0x10100000,
276
+ REG_PLL_DDR_BIAS_RST = 0x81104000,
277
+ REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
278
+ REG_PLL_GPU_BIAS_RST = 0x10100000,
279
+ REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
280
+ REG_PLL_DE_BIAS_RST = 0x10100000,
281
+ REG_PLL_CPUX_TUNING_RST = 0x0A101000,
282
+ REG_PLL_DDR_TUNING_RST = 0x14880000,
283
+};
284
+
285
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
286
+ unsigned size)
287
+{
288
+ const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
289
+ const uint32_t idx = REG_INDEX(offset);
290
+
291
+ switch (offset) {
292
+ case 0x308 ... AW_H3_CCU_IOSIZE:
293
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
294
+ __func__, (uint32_t)offset);
295
+ return 0;
296
+ }
297
+
298
+ return s->regs[idx];
299
+}
54
+}
300
+
55
+
301
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
56
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
302
+ uint64_t val, unsigned size)
57
* than the 32 bit equivalent.
58
*/
59
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
60
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
61
}
62
return;
63
+ case 0x16: /* SQDMULH, SQRDMULH */
64
+ {
65
+ static gen_helper_gvec_3_ptr * const fns[2][2] = {
66
+ { gen_helper_neon_sqdmulh_h, gen_helper_neon_sqrdmulh_h },
67
+ { gen_helper_neon_sqdmulh_s, gen_helper_neon_sqrdmulh_s },
68
+ };
69
+ gen_gvec_op3_qc(s, is_q, rd, rn, rm, fns[size - 1][u]);
70
+ }
71
+ return;
72
case 0x11:
73
if (!u) { /* CMTST */
74
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size);
75
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
76
genenvfn = fns[size][u];
77
break;
78
}
79
- case 0x16: /* SQDMULH, SQRDMULH */
80
- {
81
- static NeonGenTwoOpEnvFn * const fns[2][2] = {
82
- { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
83
- { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
84
- };
85
- assert(size == 1 || size == 2);
86
- genenvfn = fns[size - 1][u];
87
- break;
88
- }
89
default:
90
g_assert_not_reached();
91
}
92
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/vec_helper.c
95
+++ b/target/arm/vec_helper.c
96
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
97
clear_tail(d, opr_sz, simd_maxsz(desc));
98
}
99
100
+void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm,
101
+ void *vq, uint32_t desc)
303
+{
102
+{
304
+ AwH3ClockCtlState *s = AW_H3_CCU(opaque);
103
+ intptr_t i, opr_sz = simd_oprsz(desc);
305
+ const uint32_t idx = REG_INDEX(offset);
104
+ int16_t *d = vd, *n = vn, *m = vm;
306
+
105
+
307
+ switch (offset) {
106
+ for (i = 0; i < opr_sz / 2; ++i) {
308
+ case REG_DRAM_CFG: /* DRAM Configuration */
107
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq);
309
+ val &= ~REG_DRAM_CFG_UPDATE;
310
+ break;
311
+ case REG_PLL_CPUX: /* PLL CPUX Control */
312
+ case REG_PLL_AUDIO: /* PLL Audio Control */
313
+ case REG_PLL_VIDEO: /* PLL Video Control */
314
+ case REG_PLL_VE: /* PLL VE Control */
315
+ case REG_PLL_DDR: /* PLL DDR Control */
316
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
317
+ case REG_PLL_GPU: /* PLL GPU Control */
318
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
319
+ case REG_PLL_DE: /* PLL Display Engine Control */
320
+ if (val & REG_PLL_ENABLE) {
321
+ val |= REG_PLL_LOCK;
322
+ }
323
+ break;
324
+ case 0x308 ... AW_H3_CCU_IOSIZE:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ default:
329
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
330
+ __func__, (uint32_t)offset);
331
+ break;
332
+ }
108
+ }
333
+
109
+ clear_tail(d, opr_sz, simd_maxsz(desc));
334
+ s->regs[idx] = (uint32_t) val;
335
+}
110
+}
336
+
111
+
337
+static const MemoryRegionOps allwinner_h3_ccu_ops = {
112
+void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm,
338
+ .read = allwinner_h3_ccu_read,
113
+ void *vq, uint32_t desc)
339
+ .write = allwinner_h3_ccu_write,
114
+{
340
+ .endianness = DEVICE_NATIVE_ENDIAN,
115
+ intptr_t i, opr_sz = simd_oprsz(desc);
341
+ .valid = {
116
+ int16_t *d = vd, *n = vn, *m = vm;
342
+ .min_access_size = 4,
343
+ .max_access_size = 4,
344
+ },
345
+ .impl.min_access_size = 4,
346
+};
347
+
117
+
348
+static void allwinner_h3_ccu_reset(DeviceState *dev)
118
+ for (i = 0; i < opr_sz / 2; ++i) {
349
+{
119
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq);
350
+ AwH3ClockCtlState *s = AW_H3_CCU(dev);
120
+ }
351
+
121
+ clear_tail(d, opr_sz, simd_maxsz(desc));
352
+ /* Set default values for registers */
353
+ s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
354
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
355
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
356
+ s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
357
+ s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
358
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
359
+ s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
360
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
361
+ s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
362
+ s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
363
+ s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
364
+ s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
365
+ s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
366
+ s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
367
+ s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
368
+ s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
369
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
370
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
371
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
372
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
373
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
374
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
375
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
376
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
377
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
378
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
379
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
380
+}
122
+}
381
+
123
+
382
+static void allwinner_h3_ccu_init(Object *obj)
124
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
125
static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
126
bool neg, bool round, uint32_t *sat)
127
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
128
clear_tail(d, opr_sz, simd_maxsz(desc));
129
}
130
131
+void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm,
132
+ void *vq, uint32_t desc)
383
+{
133
+{
384
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
134
+ intptr_t i, opr_sz = simd_oprsz(desc);
385
+ AwH3ClockCtlState *s = AW_H3_CCU(obj);
135
+ int32_t *d = vd, *n = vn, *m = vm;
386
+
136
+
387
+ /* Memory mapping */
137
+ for (i = 0; i < opr_sz / 4; ++i) {
388
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
138
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq);
389
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
139
+ }
390
+ sysbus_init_mmio(sbd, &s->iomem);
140
+ clear_tail(d, opr_sz, simd_maxsz(desc));
391
+}
141
+}
392
+
142
+
393
+static const VMStateDescription allwinner_h3_ccu_vmstate = {
143
+void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm,
394
+ .name = "allwinner-h3-ccu",
144
+ void *vq, uint32_t desc)
395
+ .version_id = 1,
145
+{
396
+ .minimum_version_id = 1,
146
+ intptr_t i, opr_sz = simd_oprsz(desc);
397
+ .fields = (VMStateField[]) {
147
+ int32_t *d = vd, *n = vn, *m = vm;
398
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
148
+
399
+ VMSTATE_END_OF_LIST()
149
+ for (i = 0; i < opr_sz / 4; ++i) {
150
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq);
400
+ }
151
+ }
401
+};
152
+ clear_tail(d, opr_sz, simd_maxsz(desc));
402
+
403
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
404
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
407
+ dc->reset = allwinner_h3_ccu_reset;
408
+ dc->vmsd = &allwinner_h3_ccu_vmstate;
409
+}
153
+}
410
+
154
+
411
+static const TypeInfo allwinner_h3_ccu_info = {
155
/* Integer 8 and 16-bit dot-product.
412
+ .name = TYPE_AW_H3_CCU,
156
*
413
+ .parent = TYPE_SYS_BUS_DEVICE,
157
* Note that for the loops herein, host endianness does not matter
414
+ .instance_init = allwinner_h3_ccu_init,
415
+ .instance_size = sizeof(AwH3ClockCtlState),
416
+ .class_init = allwinner_h3_ccu_class_init,
417
+};
418
+
419
+static void allwinner_h3_ccu_register(void)
420
+{
421
+ type_register_static(&allwinner_h3_ccu_info);
422
+}
423
+
424
+type_init(allwinner_h3_ccu_register)
425
--
158
--
426
2.20.1
159
2.20.1
427
160
428
161
diff view generated by jsdifflib