1
arm queue; dunno if this will be the last before softfreeze
1
The following changes since commit c88f1ffc19e38008a1c33ae039482a860aa7418c:
2
or not, but anyway probably the last large one. New orangepi-pc
3
board model is the big item here.
4
2
5
thanks
3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-05-08 14:29:18 +0100)
6
-- PMM
7
8
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
9
10
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200511
15
8
16
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
9
for you to fetch changes up to 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694:
17
10
18
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
11
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) (2020-05-11 14:22:54 +0100)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
target-arm queue:
14
target-arm queue:
22
* Fix various bugs that might result in an assert() due to
15
aspeed: Add boot stub for smp booting
23
incorrect hflags for M-profile CPUs
16
target/arm: Drop access_el3_aa32ns_aa64any()
24
* Fix Aspeed SMC Controller user-mode select handling
17
aspeed: Support AST2600A1 silicon revision
25
* Report correct (with-tag) address in fault address register
18
aspeed: sdmc: Implement AST2600 locking behaviour
26
when TBI is enabled
19
nrf51: Tracing cleanups
27
* cubieboard: make sure SOC object isn't leaked
20
target/arm: Improve handling of SVE loads and stores
28
* fsl-imx25: Wire up eSDHC controllers
21
target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds
29
* fsl-imx25: Wire up USB controllers
22
hw/arm/musicpal: Map the UART devices unconditionally
30
* New board model: orangepi-pc (OrangePi PC)
23
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
31
* ARM/KVM: if user doesn't select GIC version and the
24
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
32
host kernel can only provide GICv3, use that, rather
33
than defaulting to "fail because GICv2 isn't possible"
34
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
35
25
36
----------------------------------------------------------------
26
----------------------------------------------------------------
37
Beata Michalska (1):
27
Edgar E. Iglesias (1):
38
target/arm: kvm: Inject events at the last stage of sync
28
target/arm: Drop access_el3_aa32ns_aa64any()
39
29
40
Cédric Le Goater (2):
30
Joel Stanley (3):
41
aspeed/smc: Add some tracing
31
aspeed: Add boot stub for smp booting
42
aspeed/smc: Fix User mode select/unselect scheme
32
aspeed: Support AST2600A1 silicon revision
33
aspeed: sdmc: Implement AST2600 locking behaviour
43
34
44
Eric Auger (6):
35
Philippe Mathieu-Daudé (8):
45
hw/arm/virt: Document 'max' value in gic-version property description
36
hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
46
hw/arm/virt: Introduce VirtGICType enum type
37
hw/timer/nrf51_timer: Display timer ID in trace events
47
hw/arm/virt: Introduce finalize_gic_version()
38
hw/timer/nrf51_timer: Add trace event of counter value update
48
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
39
target/arm/kvm: Inline set_feature() calls
49
hw/arm/virt: kvm: Restructure finalize_gic_version()
40
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
50
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
41
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
42
target/arm: Restrict TCG cpus to TCG accel
43
hw/arm/musicpal: Map the UART devices unconditionally
51
44
52
Guenter Roeck (2):
45
Richard Henderson (21):
53
hw/arm/fsl-imx25: Wire up eSDHC controllers
46
exec: Add block comments for watchpoint routines
54
hw/arm/fsl-imx25: Wire up USB controllers
47
exec: Fix cpu_watchpoint_address_matches address length
48
accel/tcg: Add block comment for probe_access
49
accel/tcg: Adjust probe_access call to page_check_range
50
accel/tcg: Add probe_access_flags
51
accel/tcg: Add endian-specific cpu_{ld, st}* operations
52
target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
53
target/arm: Drop manual handling of set/clear_helper_retaddr
54
target/arm: Add sve infrastructure for page lookup
55
target/arm: Adjust interface of sve_ld1_host_fn
56
target/arm: Use SVEContLdSt in sve_ld1_r
57
target/arm: Handle watchpoints in sve_ld1_r
58
target/arm: Use SVEContLdSt for multi-register contiguous loads
59
target/arm: Update contiguous first-fault and no-fault loads
60
target/arm: Use SVEContLdSt for contiguous stores
61
target/arm: Reuse sve_probe_page for gather first-fault loads
62
target/arm: Reuse sve_probe_page for scatter stores
63
target/arm: Reuse sve_probe_page for gather loads
64
target/arm: Remove sve_memopidx
65
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
66
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
55
67
56
Igor Mammedov (1):
68
Thomas Huth (1):
57
hw/arm/cubieboard: make sure SOC object isn't leaked
69
target/arm: Make set_feature() available for other files
58
70
59
Niek Linnenbank (13):
71
docs/devel/loads-stores.rst | 39 +-
60
hw/arm: add Allwinner H3 System-on-Chip
72
include/exec/cpu-all.h | 13 +-
61
hw/arm: add Xunlong Orange Pi PC machine
73
include/exec/cpu_ldst.h | 283 +++--
62
hw/arm/allwinner-h3: add Clock Control Unit
74
include/exec/exec-all.h | 39 +
63
hw/arm/allwinner-h3: add USB host controller
75
include/hw/arm/nrf51.h | 3 +-
64
hw/arm/allwinner-h3: add System Control module
76
include/hw/core/cpu.h | 23 +
65
hw/arm/allwinner: add CPU Configuration module
77
include/hw/i2c/microbit_i2c.h | 2 +-
66
hw/arm/allwinner: add Security Identifier device
78
include/hw/misc/aspeed_scu.h | 1 +
67
hw/arm/allwinner: add SD/MMC host controller
79
include/hw/timer/nrf51_timer.h | 1 +
68
hw/arm/allwinner-h3: add EMAC ethernet device
80
target/arm/cpu.h | 10 +
69
hw/arm/allwinner-h3: add Boot ROM support
81
target/arm/helper-sve.h | 45 +-
70
hw/arm/allwinner-h3: add SDRAM controller device
82
target/arm/internals.h | 5 -
71
hw/arm/allwinner: add RTC device support
83
accel/tcg/cputlb.c | 413 ++++---
72
docs: add Orange Pi PC document
84
accel/tcg/user-exec.c | 256 ++++-
85
exec.c | 2 +-
86
hw/arm/aspeed.c | 73 +-
87
hw/arm/aspeed_ast2600.c | 6 +-
88
hw/arm/musicpal.c | 12 +-
89
hw/arm/nrf51_soc.c | 9 +-
90
hw/i2c/microbit_i2c.c | 2 +-
91
hw/misc/aspeed_scu.c | 11 +-
92
hw/misc/aspeed_sdmc.c | 55 +-
93
hw/timer/nrf51_timer.c | 14 +-
94
target/arm/cpu.c | 662 +----------
95
target/arm/cpu64.c | 18 +-
96
target/arm/cpu_tcg.c | 664 +++++++++++
97
target/arm/helper.c | 30 +-
98
target/arm/kvm32.c | 13 +-
99
target/arm/kvm64.c | 22 +-
100
target/arm/sve_helper.c | 2398 +++++++++++++++++++++-------------------
101
target/arm/translate-sve.c | 93 +-
102
hw/timer/trace-events | 5 +-
103
target/arm/Makefile.objs | 1 +
104
33 files changed, 2975 insertions(+), 2248 deletions(-)
105
create mode 100644 target/arm/cpu_tcg.c
73
106
74
Peter Maydell (4):
75
hw/intc/armv7m_nvic: Rebuild hflags on reset
76
target/arm: Update hflags in trans_CPS_v7m()
77
target/arm: Recalculate hflags correctly after writes to CONTROL
78
target/arm: Fix some comment typos
79
80
Philippe Mathieu-Daudé (5):
81
tests/boot_linux_console: Add a quick test for the OrangePi PC board
82
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
83
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
84
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
85
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
86
87
Richard Henderson (2):
88
target/arm: Check addresses for disabled regimes
89
target/arm: Disable clean_data_tbi for system mode
90
91
Makefile.objs | 1 +
92
hw/arm/Makefile.objs | 1 +
93
hw/misc/Makefile.objs | 5 +
94
hw/net/Makefile.objs | 1 +
95
hw/rtc/Makefile.objs | 1 +
96
hw/sd/Makefile.objs | 1 +
97
hw/usb/hcd-ehci.h | 1 +
98
include/hw/arm/allwinner-a10.h | 4 +
99
include/hw/arm/allwinner-h3.h | 161 ++++++
100
include/hw/arm/fsl-imx25.h | 18 +
101
include/hw/arm/virt.h | 12 +-
102
include/hw/misc/allwinner-cpucfg.h | 52 ++
103
include/hw/misc/allwinner-h3-ccu.h | 66 +++
104
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
105
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
106
include/hw/misc/allwinner-sid.h | 60 +++
107
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
108
include/hw/rtc/allwinner-rtc.h | 134 +++++
109
include/hw/sd/allwinner-sdhost.h | 135 +++++
110
target/arm/helper.h | 1 +
111
target/arm/kvm_arm.h | 3 +
112
hw/arm/allwinner-a10.c | 19 +
113
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
114
hw/arm/cubieboard.c | 18 +
115
hw/arm/fsl-imx25.c | 56 +++
116
hw/arm/imx25_pdk.c | 16 +
117
hw/arm/orangepi.c | 130 +++++
118
hw/arm/virt.c | 145 ++++--
119
hw/intc/armv7m_nvic.c | 6 +
120
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
121
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
122
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
123
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
124
hw/misc/allwinner-sid.c | 168 +++++++
125
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
126
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
127
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
128
hw/ssi/aspeed_smc.c | 56 ++-
129
hw/usb/hcd-ehci-sysbus.c | 17 +
130
target/arm/helper.c | 49 +-
131
target/arm/kvm.c | 14 +-
132
target/arm/kvm32.c | 15 +-
133
target/arm/kvm64.c | 15 +-
134
target/arm/translate-a64.c | 11 +
135
target/arm/translate.c | 14 +-
136
MAINTAINERS | 9 +
137
default-configs/arm-softmmu.mak | 1 +
138
docs/system/arm/orangepi.rst | 253 ++++++++++
139
docs/system/target-arm.rst | 2 +
140
hw/arm/Kconfig | 12 +
141
hw/misc/trace-events | 19 +
142
hw/net/Kconfig | 3 +
143
hw/net/trace-events | 10 +
144
hw/rtc/trace-events | 4 +
145
hw/sd/trace-events | 7 +
146
hw/ssi/trace-events | 10 +
147
tests/acceptance/boot_linux_console.py | 230 +++++++++
148
57 files changed, 5787 insertions(+), 74 deletions(-)
149
create mode 100644 include/hw/arm/allwinner-h3.h
150
create mode 100644 include/hw/misc/allwinner-cpucfg.h
151
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
152
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
153
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
154
create mode 100644 include/hw/misc/allwinner-sid.h
155
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
156
create mode 100644 include/hw/rtc/allwinner-rtc.h
157
create mode 100644 include/hw/sd/allwinner-sdhost.h
158
create mode 100644 hw/arm/allwinner-h3.c
159
create mode 100644 hw/arm/orangepi.c
160
create mode 100644 hw/misc/allwinner-cpucfg.c
161
create mode 100644 hw/misc/allwinner-h3-ccu.c
162
create mode 100644 hw/misc/allwinner-h3-dramc.c
163
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
164
create mode 100644 hw/misc/allwinner-sid.c
165
create mode 100644 hw/net/allwinner-sun8i-emac.c
166
create mode 100644 hw/rtc/allwinner-rtc.c
167
create mode 100644 hw/sd/allwinner-sdhost.c
168
create mode 100644 docs/system/arm/orangepi.rst
169
create mode 100644 hw/ssi/trace-events
170
diff view generated by jsdifflib
Deleted patch
1
Some of an M-profile CPU's cached hflags state depends on state that's
2
in our NVIC object. We already do an hflags rebuild when the NVIC
3
registers are written, but we also need to do this on NVIC reset,
4
because there's no guarantee that this will happen before the
5
CPU reset.
6
1
7
This fixes an assertion due to mismatched hflags which happens if
8
the CPU is reset from inside a HardFault handler.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200303174950.3298-2-peter.maydell@linaro.org
13
---
14
hw/intc/armv7m_nvic.c | 6 ++++++
15
1 file changed, 6 insertions(+)
16
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
20
+++ b/hw/intc/armv7m_nvic.c
21
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
22
s->itns[i] = true;
23
}
24
}
25
+
26
+ /*
27
+ * We updated state that affects the CPU's MMUidx and thus its hflags;
28
+ * and we can't guarantee that we run before the CPU reset function.
29
+ */
30
+ arm_rebuild_hflags(&s->cpu->env);
31
}
32
33
static void nvic_systick_trigger(void *opaque, int n, int level)
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
Deleted patch
1
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
2
(it changes the NegPri bit). We update the hflags after calls
3
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
4
in trans_CPS_v7m().
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200303174950.3298-3-peter.maydell@linaro.org
9
---
10
target/arm/translate.c | 5 ++++-
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
18
19
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
20
{
21
- TCGv_i32 tmp, addr;
22
+ TCGv_i32 tmp, addr, el;
23
24
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
25
return false;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
27
gen_helper_v7m_msr(cpu_env, addr, tmp);
28
tcg_temp_free_i32(addr);
29
}
30
+ el = tcg_const_i32(s->current_el);
31
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
32
+ tcg_temp_free_i32(el);
33
tcg_temp_free_i32(tmp);
34
gen_lookup_tb(s);
35
return true;
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
Various Allwinner System on Chip designs contain multiple processors
3
This is a boot stub that is similar to the code u-boot runs, allowing
4
that can be configured and reset using the generic CPU Configuration
4
the kernel to boot the secondary CPU.
5
module interface. This commit adds support for the Allwinner CPU
6
configuration interface which emulates the following features:
7
5
8
* CPU reset
6
u-boot works as follows:
9
* CPU status
10
7
11
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
1. Initialises the SMP mailbox area in the SCU at 0x1e6e2180 with default values
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
13
Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com
10
2. Copies a stub named 'mailbox_insn' from flash to the SCU, just above the
11
mailbox area
12
13
3. Sets AST_SMP_MBOX_FIELD_READY to a magic value to indicate the
14
secondary can begin execution from the stub
15
16
4. The stub waits until the AST_SMP_MBOX_FIELD_GOSIGN register is set to
17
a magic value
18
19
5. Jumps to the address in AST_SMP_MBOX_FIELD_ENTRY, starting Linux
20
21
Linux indicates it is ready by writing the address of its entrypoint
22
function to AST_SMP_MBOX_FIELD_ENTRY and the 'go' magic number to
23
AST_SMP_MBOX_FIELD_GOSIGN. The secondary CPU sees this at step 4 and
24
breaks out of it's loop.
25
26
To be compatible, a fixed qemu stub is loaded into the mailbox area. As
27
qemu can ensure the stub is loaded before execution starts, we do not
28
need to emulate the AST_SMP_MBOX_FIELD_READY behaviour of u-boot. The
29
secondary CPU's program counter points to the beginning of the stub,
30
allowing qemu to start secondaries at step four.
31
32
Reboot behaviour is preserved by resetting AST_SMP_MBOX_FIELD_GOSIGN
33
when the secondaries are reset.
34
35
This is only configured when the system is booted with -kernel and qemu
36
does not execute u-boot first.
37
38
Reviewed-by: Cédric Le Goater <clg@kaod.org>
39
Tested-by: Cédric Le Goater <clg@kaod.org>
40
Signed-off-by: Joel Stanley <joel@jms.id.au>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
42
---
16
hw/misc/Makefile.objs | 1 +
43
hw/arm/aspeed.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++
17
include/hw/arm/allwinner-h3.h | 3 +
44
1 file changed, 65 insertions(+)
18
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
19
hw/arm/allwinner-h3.c | 9 +-
20
hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++
21
hw/misc/trace-events | 5 +
22
6 files changed, 351 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/misc/allwinner-cpucfg.h
24
create mode 100644 hw/misc/allwinner-cpucfg.c
25
45
26
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
46
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
27
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/misc/Makefile.objs
48
--- a/hw/arm/aspeed.c
29
+++ b/hw/misc/Makefile.objs
49
+++ b/hw/arm/aspeed.c
30
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
50
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps max_ram_ops = {
31
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
51
.endianness = DEVICE_NATIVE_ENDIAN,
32
33
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
37
common-obj-$(CONFIG_NSERIES) += cbus.o
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/allwinner-h3.h
41
+++ b/include/hw/arm/allwinner-h3.h
42
@@ -XXX,XX +XXX,XX @@
43
#include "hw/timer/allwinner-a10-pit.h"
44
#include "hw/intc/arm_gic.h"
45
#include "hw/misc/allwinner-h3-ccu.h"
46
+#include "hw/misc/allwinner-cpucfg.h"
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "target/arm/cpu.h"
49
50
@@ -XXX,XX +XXX,XX @@ enum {
51
AW_H3_GIC_CPU,
52
AW_H3_GIC_HYP,
53
AW_H3_GIC_VCPU,
54
+ AW_H3_CPUCFG,
55
AW_H3_SDRAM
56
};
52
};
57
53
58
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
54
+#define AST_SMP_MAILBOX_BASE 0x1e6e2180
59
const hwaddr *memmap;
55
+#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
60
AwA10PITState timer;
56
+#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
61
AwH3ClockCtlState ccu;
57
+#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
62
+ AwCpuCfgState cpucfg;
58
+#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
63
AwH3SysCtrlState sysctrl;
59
+#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
64
GICState gic;
60
+#define AST_SMP_MBOX_GOSIGN 0xabbaab00
65
MemoryRegion sram_a1;
66
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h
67
new file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- /dev/null
70
+++ b/include/hw/misc/allwinner-cpucfg.h
71
@@ -XXX,XX +XXX,XX @@
72
+/*
73
+ * Allwinner CPU Configuration Module emulation
74
+ *
75
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
76
+ *
77
+ * This program is free software: you can redistribute it and/or modify
78
+ * it under the terms of the GNU General Public License as published by
79
+ * the Free Software Foundation, either version 2 of the License, or
80
+ * (at your option) any later version.
81
+ *
82
+ * This program is distributed in the hope that it will be useful,
83
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
84
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
85
+ * GNU General Public License for more details.
86
+ *
87
+ * You should have received a copy of the GNU General Public License
88
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
89
+ */
90
+
61
+
91
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
62
+static void aspeed_write_smpboot(ARMCPU *cpu,
92
+#define HW_MISC_ALLWINNER_CPUCFG_H
63
+ const struct arm_boot_info *info)
64
+{
65
+ static const uint32_t poll_mailbox_ready[] = {
66
+ /*
67
+ * r2 = per-cpu go sign value
68
+ * r1 = AST_SMP_MBOX_FIELD_ENTRY
69
+ * r0 = AST_SMP_MBOX_FIELD_GOSIGN
70
+ */
71
+ 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
72
+ 0xe21000ff, /* ands r0, r0, #255 */
73
+ 0xe59f201c, /* ldr r2, [pc, #28] */
74
+ 0xe1822000, /* orr r2, r2, r0 */
93
+
75
+
94
+#include "qom/object.h"
76
+ 0xe59f1018, /* ldr r1, [pc, #24] */
95
+#include "hw/sysbus.h"
77
+ 0xe59f0018, /* ldr r0, [pc, #24] */
96
+
78
+
97
+/**
79
+ 0xe320f002, /* wfe */
98
+ * Object model
80
+ 0xe5904000, /* ldr r4, [r0] */
99
+ * @{
81
+ 0xe1520004, /* cmp r2, r4 */
100
+ */
82
+ 0x1afffffb, /* bne <wfe> */
83
+ 0xe591f000, /* ldr pc, [r1] */
84
+ AST_SMP_MBOX_GOSIGN,
85
+ AST_SMP_MBOX_FIELD_ENTRY,
86
+ AST_SMP_MBOX_FIELD_GOSIGN,
87
+ };
101
+
88
+
102
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
89
+ rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
103
+#define AW_CPUCFG(obj) \
90
+ sizeof(poll_mailbox_ready),
104
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
91
+ info->smp_loader_start);
105
+
106
+/** @} */
107
+
108
+/**
109
+ * Allwinner CPU Configuration Module instance state
110
+ */
111
+typedef struct AwCpuCfgState {
112
+ /*< private >*/
113
+ SysBusDevice parent_obj;
114
+ /*< public >*/
115
+
116
+ MemoryRegion iomem;
117
+ uint32_t gen_ctrl;
118
+ uint32_t super_standby;
119
+ uint32_t entry_addr;
120
+
121
+} AwCpuCfgState;
122
+
123
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
124
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/arm/allwinner-h3.c
127
+++ b/hw/arm/allwinner-h3.c
128
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
129
[AW_H3_GIC_CPU] = 0x01c82000,
130
[AW_H3_GIC_HYP] = 0x01c84000,
131
[AW_H3_GIC_VCPU] = 0x01c86000,
132
+ [AW_H3_CPUCFG] = 0x01f01c00,
133
[AW_H3_SDRAM] = 0x40000000
134
};
135
136
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
137
{ "r_wdog", 0x01f01000, 1 * KiB },
138
{ "r_prcm", 0x01f01400, 1 * KiB },
139
{ "r_twd", 0x01f01800, 1 * KiB },
140
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
141
{ "r_cir-rx", 0x01f02000, 1 * KiB },
142
{ "r_twi", 0x01f02400, 1 * KiB },
143
{ "r_uart", 0x01f02800, 1 * KiB },
144
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
145
146
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
147
TYPE_AW_H3_SYSCTRL);
148
+
149
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
150
+ TYPE_AW_CPUCFG);
151
}
152
153
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
154
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
155
qdev_init_nofail(DEVICE(&s->sysctrl));
156
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
157
158
+ /* CPU Configuration */
159
+ qdev_init_nofail(DEVICE(&s->cpucfg));
160
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
161
+
162
/* Universal Serial Bus */
163
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
164
qdev_get_gpio_in(DEVICE(&s->gic),
165
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
166
new file mode 100644
167
index XXXXXXX..XXXXXXX
168
--- /dev/null
169
+++ b/hw/misc/allwinner-cpucfg.c
170
@@ -XXX,XX +XXX,XX @@
171
+/*
172
+ * Allwinner CPU Configuration Module emulation
173
+ *
174
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
175
+ *
176
+ * This program is free software: you can redistribute it and/or modify
177
+ * it under the terms of the GNU General Public License as published by
178
+ * the Free Software Foundation, either version 2 of the License, or
179
+ * (at your option) any later version.
180
+ *
181
+ * This program is distributed in the hope that it will be useful,
182
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
183
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
184
+ * GNU General Public License for more details.
185
+ *
186
+ * You should have received a copy of the GNU General Public License
187
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
188
+ */
189
+
190
+#include "qemu/osdep.h"
191
+#include "qemu/units.h"
192
+#include "hw/sysbus.h"
193
+#include "migration/vmstate.h"
194
+#include "qemu/log.h"
195
+#include "qemu/module.h"
196
+#include "qemu/error-report.h"
197
+#include "qemu/timer.h"
198
+#include "hw/core/cpu.h"
199
+#include "target/arm/arm-powerctl.h"
200
+#include "target/arm/cpu.h"
201
+#include "hw/misc/allwinner-cpucfg.h"
202
+#include "trace.h"
203
+
204
+/* CPUCFG register offsets */
205
+enum {
206
+ REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
207
+ REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
208
+ REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
209
+ REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
210
+ REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
211
+ REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
212
+ REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */
213
+ REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
214
+ REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
215
+ REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */
216
+ REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
217
+ REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
218
+ REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */
219
+ REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */
220
+ REG_CLK_GATING = 0x0144, /* CPU Clock Gating */
221
+ REG_GEN_CTRL = 0x0184, /* General Control */
222
+ REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */
223
+ REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */
224
+ REG_DBG_EXTERN = 0x01E4, /* Debug External */
225
+ REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
226
+ REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
227
+ REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
228
+};
229
+
230
+/* CPUCFG register flags */
231
+enum {
232
+ CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)),
233
+ CPUX_STATUS_SMP = (1 << 0),
234
+ CPU_SYS_RESET_RELEASED = (1 << 0),
235
+ CLK_GATING_ENABLE = ((1 << 8) | 0xF),
236
+};
237
+
238
+/* CPUCFG register reset values */
239
+enum {
240
+ REG_CLK_GATING_RST = 0x0000010F,
241
+ REG_GEN_CTRL_RST = 0x00000020,
242
+ REG_SUPER_STANDBY_RST = 0x0,
243
+ REG_CNT64_CTRL_RST = 0x0,
244
+};
245
+
246
+/* CPUCFG constants */
247
+enum {
248
+ CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */
249
+};
250
+
251
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
252
+{
253
+ int ret;
254
+
255
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
256
+
257
+ ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id));
258
+ if (!target_cpu) {
259
+ /*
260
+ * Called with a bogus value for cpu_id. Guest error will
261
+ * already have been logged, we can simply return here.
262
+ */
263
+ return;
264
+ }
265
+ bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64);
266
+
267
+ ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0,
268
+ CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64);
269
+ if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) {
270
+ error_report("%s: failed to bring up CPU %d: err %d",
271
+ __func__, cpu_id, ret);
272
+ return;
273
+ }
274
+}
92
+}
275
+
93
+
276
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
94
+static void aspeed_reset_secondary(ARMCPU *cpu,
277
+ unsigned size)
95
+ const struct arm_boot_info *info)
278
+{
96
+{
279
+ const AwCpuCfgState *s = AW_CPUCFG(opaque);
97
+ AddressSpace *as = arm_boot_address_space(cpu, info);
280
+ uint64_t val = 0;
98
+ CPUState *cs = CPU(cpu);
281
+
99
+
282
+ switch (offset) {
100
+ /* info->smp_bootreg_addr */
283
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
101
+ address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
284
+ case REG_CPU_SYS_RST: /* CPU System Reset */
102
+ MEMTXATTRS_UNSPECIFIED, NULL);
285
+ val = CPU_SYS_RESET_RELEASED;
103
+ cpu_set_pc(cs, info->smp_loader_start);
286
+ break;
104
+}
287
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
105
+
288
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
106
#define FIRMWARE_ADDR 0x0
289
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
107
290
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
108
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
291
+ val = CPUX_RESET_RELEASED;
109
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
292
+ break;
110
}
293
+ case REG_CPU0_CTRL: /* CPU#0 Control */
111
}
294
+ case REG_CPU1_CTRL: /* CPU#1 Control */
112
295
+ case REG_CPU2_CTRL: /* CPU#2 Control */
113
+ if (machine->kernel_filename && bmc->soc.num_cpus > 1) {
296
+ case REG_CPU3_CTRL: /* CPU#3 Control */
114
+ /* With no u-boot we must set up a boot stub for the secondary CPU */
297
+ val = 0;
115
+ MemoryRegion *smpboot = g_new(MemoryRegion, 1);
298
+ break;
116
+ memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot",
299
+ case REG_CPU0_STATUS: /* CPU#0 Status */
117
+ 0x80, &error_abort);
300
+ case REG_CPU1_STATUS: /* CPU#1 Status */
118
+ memory_region_add_subregion(get_system_memory(),
301
+ case REG_CPU2_STATUS: /* CPU#2 Status */
119
+ AST_SMP_MAILBOX_BASE, smpboot);
302
+ case REG_CPU3_STATUS: /* CPU#3 Status */
120
+
303
+ val = CPUX_STATUS_SMP;
121
+ aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
304
+ break;
122
+ aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
305
+ case REG_CLK_GATING: /* CPU Clock Gating */
123
+ aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
306
+ val = CLK_GATING_ENABLE;
307
+ break;
308
+ case REG_GEN_CTRL: /* General Control */
309
+ val = s->gen_ctrl;
310
+ break;
311
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
312
+ val = s->super_standby;
313
+ break;
314
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
315
+ val = s->entry_addr;
316
+ break;
317
+ case REG_DBG_EXTERN: /* Debug External */
318
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
319
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
320
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
321
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
322
+ __func__, (uint32_t)offset);
323
+ break;
324
+ default:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ }
124
+ }
329
+
125
+
330
+ trace_allwinner_cpucfg_read(offset, val, size);
126
aspeed_board_binfo.ram_size = ram_size;
331
+
127
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
332
+ return val;
128
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
333
+}
334
+
335
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
336
+ uint64_t val, unsigned size)
337
+{
338
+ AwCpuCfgState *s = AW_CPUCFG(opaque);
339
+
340
+ trace_allwinner_cpucfg_write(offset, val, size);
341
+
342
+ switch (offset) {
343
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
344
+ case REG_CPU_SYS_RST: /* CPU System Reset */
345
+ break;
346
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
347
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
348
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
349
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
350
+ if (val) {
351
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6);
352
+ }
353
+ break;
354
+ case REG_CPU0_CTRL: /* CPU#0 Control */
355
+ case REG_CPU1_CTRL: /* CPU#1 Control */
356
+ case REG_CPU2_CTRL: /* CPU#2 Control */
357
+ case REG_CPU3_CTRL: /* CPU#3 Control */
358
+ case REG_CPU0_STATUS: /* CPU#0 Status */
359
+ case REG_CPU1_STATUS: /* CPU#1 Status */
360
+ case REG_CPU2_STATUS: /* CPU#2 Status */
361
+ case REG_CPU3_STATUS: /* CPU#3 Status */
362
+ case REG_CLK_GATING: /* CPU Clock Gating */
363
+ break;
364
+ case REG_GEN_CTRL: /* General Control */
365
+ s->gen_ctrl = val;
366
+ break;
367
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
368
+ s->super_standby = val;
369
+ break;
370
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
371
+ s->entry_addr = val;
372
+ break;
373
+ case REG_DBG_EXTERN: /* Debug External */
374
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
375
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
376
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
377
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
378
+ __func__, (uint32_t)offset);
379
+ break;
380
+ default:
381
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
382
+ __func__, (uint32_t)offset);
383
+ break;
384
+ }
385
+}
386
+
387
+static const MemoryRegionOps allwinner_cpucfg_ops = {
388
+ .read = allwinner_cpucfg_read,
389
+ .write = allwinner_cpucfg_write,
390
+ .endianness = DEVICE_NATIVE_ENDIAN,
391
+ .valid = {
392
+ .min_access_size = 4,
393
+ .max_access_size = 4,
394
+ },
395
+ .impl.min_access_size = 4,
396
+};
397
+
398
+static void allwinner_cpucfg_reset(DeviceState *dev)
399
+{
400
+ AwCpuCfgState *s = AW_CPUCFG(dev);
401
+
402
+ /* Set default values for registers */
403
+ s->gen_ctrl = REG_GEN_CTRL_RST;
404
+ s->super_standby = REG_SUPER_STANDBY_RST;
405
+ s->entry_addr = 0;
406
+}
407
+
408
+static void allwinner_cpucfg_init(Object *obj)
409
+{
410
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
411
+ AwCpuCfgState *s = AW_CPUCFG(obj);
412
+
413
+ /* Memory mapping */
414
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
415
+ TYPE_AW_CPUCFG, 1 * KiB);
416
+ sysbus_init_mmio(sbd, &s->iomem);
417
+}
418
+
419
+static const VMStateDescription allwinner_cpucfg_vmstate = {
420
+ .name = "allwinner-cpucfg",
421
+ .version_id = 1,
422
+ .minimum_version_id = 1,
423
+ .fields = (VMStateField[]) {
424
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
425
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
426
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
427
+ VMSTATE_END_OF_LIST()
428
+ }
429
+};
430
+
431
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
432
+{
433
+ DeviceClass *dc = DEVICE_CLASS(klass);
434
+
435
+ dc->reset = allwinner_cpucfg_reset;
436
+ dc->vmsd = &allwinner_cpucfg_vmstate;
437
+}
438
+
439
+static const TypeInfo allwinner_cpucfg_info = {
440
+ .name = TYPE_AW_CPUCFG,
441
+ .parent = TYPE_SYS_BUS_DEVICE,
442
+ .instance_init = allwinner_cpucfg_init,
443
+ .instance_size = sizeof(AwCpuCfgState),
444
+ .class_init = allwinner_cpucfg_class_init,
445
+};
446
+
447
+static void allwinner_cpucfg_register(void)
448
+{
449
+ type_register_static(&allwinner_cpucfg_info);
450
+}
451
+
452
+type_init(allwinner_cpucfg_register)
453
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
454
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/misc/trace-events
456
+++ b/hw/misc/trace-events
457
@@ -XXX,XX +XXX,XX @@
458
# See docs/devel/tracing.txt for syntax documentation.
459
460
+# allwinner-cpucfg.c
461
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32
462
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
463
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
464
+
465
# eccmemctl.c
466
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
467
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
468
--
129
--
469
2.20.1
130
2.20.1
470
131
471
132
diff view generated by jsdifflib
1
Fix a couple of comment typos.
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
Calling access_el3_aa32ns() works for AArch32 only cores
4
but it does not handle 32-bit EL2 on top of 64-bit EL3
5
for mixed 32/64-bit cores.
6
7
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
8
and only use the latter.
9
10
Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
11
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Message-id: 20200505141729.31930-2-edgar.iglesias@gmail.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200303174950.3298-5-peter.maydell@linaro.org
6
---
16
---
7
target/arm/helper.c | 2 +-
17
target/arm/helper.c | 30 +++++++-----------------------
8
target/arm/translate.c | 2 +-
18
1 file changed, 7 insertions(+), 23 deletions(-)
9
2 files changed, 2 insertions(+), 2 deletions(-)
10
19
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
22
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
24
@@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu)
25
}
16
26
17
/*
27
/*
18
* If we have triggered a EL state change we can't rely on the
28
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
19
- * translator having passed it too us, we need to recompute.
29
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
20
+ * translator having passed it to us, we need to recompute.
30
- *
31
- * access_el3_aa32ns: Used to check AArch32 register views.
32
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
33
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
21
*/
34
*/
22
void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
35
static CPAccessResult access_el3_aa32ns(CPUARMState *env,
36
const ARMCPRegInfo *ri,
37
bool isread)
23
{
38
{
24
diff --git a/target/arm/translate.c b/target/arm/translate.c
39
- bool secure = arm_is_secure_below_el3(env);
25
index XXXXXXX..XXXXXXX 100644
40
-
26
--- a/target/arm/translate.c
41
- assert(!arm_el_is_aa64(env, 3));
27
+++ b/target/arm/translate.c
42
- if (secure) {
28
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
43
+ if (!is_a64(env) && arm_current_el(env) == 3 &&
29
44
+ arm_is_secure_below_el3(env)) {
30
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
45
return CP_ACCESS_TRAP_UNCATEGORIZED;
31
/*
46
}
32
- * A write to any coprocessor regiser that ends a TB
47
return CP_ACCESS_OK;
33
+ * A write to any coprocessor register that ends a TB
48
}
34
* must rebuild the hflags for the next TB.
49
35
*/
50
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
36
TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
51
- const ARMCPRegInfo *ri,
52
- bool isread)
53
-{
54
- if (!arm_el_is_aa64(env, 3)) {
55
- return access_el3_aa32ns(env, ri, isread);
56
- }
57
- return CP_ACCESS_OK;
58
-}
59
-
60
/* Some secure-only AArch32 registers trap to EL3 if used from
61
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
62
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
64
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
65
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
66
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
67
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
68
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
69
.type = ARM_CP_CONST, .resetvalue = 0 },
70
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
71
.cp = 15, .opc1 = 6, .crm = 2,
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
73
.type = ARM_CP_CONST, .resetvalue = 0 },
74
{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
76
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
77
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
.type = ARM_CP_CONST, .resetvalue = 0 },
79
{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
80
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
ARMCPRegInfo vpidr_regs[] = {
83
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
84
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
85
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
86
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
87
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
88
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
89
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
91
- .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
92
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
93
.type = ARM_CP_NO_RAW,
94
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
95
REGINFO_SENTINEL
37
--
96
--
38
2.20.1
97
2.20.1
39
98
40
99
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
3
There are minimal differences from Qemu's point of view between the A0
4
connections which provide software access using the Enhanced
4
and A1 silicon revisions.
5
Host Controller Interface (EHCI) and Open Host Controller
6
Interface (OHCI) interfaces. This commit adds support for
7
both interfaces in the Allwinner H3 System on Chip.
8
5
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
As the A1 exercises different code paths in u-boot it is desirable to
10
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
7
emulate that instead.
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
13
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
14
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20200504093703.261135-1-joel@jms.id.au
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
14
---
17
hw/usb/hcd-ehci.h | 1 +
15
include/hw/misc/aspeed_scu.h | 1 +
18
include/hw/arm/allwinner-h3.h | 8 +++++++
16
hw/arm/aspeed.c | 8 ++++----
19
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
17
hw/arm/aspeed_ast2600.c | 6 +++---
20
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
18
hw/misc/aspeed_scu.c | 11 +++++------
21
hw/arm/Kconfig | 2 ++
19
4 files changed, 13 insertions(+), 13 deletions(-)
22
5 files changed, 72 insertions(+)
23
20
24
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
21
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/usb/hcd-ehci.h
23
--- a/include/hw/misc/aspeed_scu.h
27
+++ b/hw/usb/hcd-ehci.h
24
+++ b/include/hw/misc/aspeed_scu.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState {
25
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
29
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
26
#define AST2500_A0_SILICON_REV 0x04000303U
30
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
27
#define AST2500_A1_SILICON_REV 0x04010303U
31
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
28
#define AST2600_A0_SILICON_REV 0x05000303U
32
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
29
+#define AST2600_A1_SILICON_REV 0x05010303U
33
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
30
34
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
31
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
35
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
32
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
33
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
37
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
35
--- a/hw/arm/aspeed.c
39
+++ b/include/hw/arm/allwinner-h3.h
36
+++ b/hw/arm/aspeed.c
40
@@ -XXX,XX +XXX,XX @@ enum {
37
@@ -XXX,XX +XXX,XX @@ struct AspeedBoardState {
41
AW_H3_SRAM_A1,
38
42
AW_H3_SRAM_A2,
39
/* Tacoma hardware value */
43
AW_H3_SRAM_C,
40
#define TACOMA_BMC_HW_STRAP1 0x00000000
44
+ AW_H3_EHCI0,
41
-#define TACOMA_BMC_HW_STRAP2 0x00000000
45
+ AW_H3_OHCI0,
42
+#define TACOMA_BMC_HW_STRAP2 0x00000040
46
+ AW_H3_EHCI1,
43
47
+ AW_H3_OHCI1,
44
/*
48
+ AW_H3_EHCI2,
45
* The max ram region is for firmwares that scan the address space
49
+ AW_H3_OHCI2,
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
50
+ AW_H3_EHCI3,
47
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
51
+ AW_H3_OHCI3,
48
52
AW_H3_CCU,
49
mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
53
AW_H3_PIT,
50
- amc->soc_name = "ast2600-a0";
54
AW_H3_UART0,
51
+ amc->soc_name = "ast2600-a1";
55
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
52
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
53
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
54
amc->fmc_model = "w25q512jv";
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
56
MachineClass *mc = MACHINE_CLASS(oc);
57
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
58
59
- mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
60
- amc->soc_name = "ast2600-a0";
61
+ mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
62
+ amc->soc_name = "ast2600-a1";
63
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
64
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
65
amc->fmc_model = "mx66l1g45g";
66
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
56
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/allwinner-h3.c
68
--- a/hw/arm/aspeed_ast2600.c
58
+++ b/hw/arm/allwinner-h3.c
69
+++ b/hw/arm/aspeed_ast2600.c
59
@@ -XXX,XX +XXX,XX @@
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
60
#include "hw/sysbus.h"
71
61
#include "hw/char/serial.h"
72
dc->realize = aspeed_soc_ast2600_realize;
62
#include "hw/misc/unimp.h"
73
63
+#include "hw/usb/hcd-ehci.h"
74
- sc->name = "ast2600-a0";
64
#include "sysemu/sysemu.h"
75
+ sc->name = "ast2600-a1";
65
#include "hw/arm/allwinner-h3.h"
76
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
66
77
- sc->silicon_rev = AST2600_A0_SILICON_REV;
67
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
78
+ sc->silicon_rev = AST2600_A1_SILICON_REV;
68
[AW_H3_SRAM_A1] = 0x00000000,
79
sc->sram_size = 0x10000;
69
[AW_H3_SRAM_A2] = 0x00044000,
80
sc->spis_num = 2;
70
[AW_H3_SRAM_C] = 0x00010000,
81
sc->ehcis_num = 2;
71
+ [AW_H3_EHCI0] = 0x01c1a000,
82
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
72
+ [AW_H3_OHCI0] = 0x01c1a400,
83
}
73
+ [AW_H3_EHCI1] = 0x01c1b000,
84
74
+ [AW_H3_OHCI1] = 0x01c1b400,
85
static const TypeInfo aspeed_soc_ast2600_type_info = {
75
+ [AW_H3_EHCI2] = 0x01c1c000,
86
- .name = "ast2600-a0",
76
+ [AW_H3_OHCI2] = 0x01c1c400,
87
+ .name = "ast2600-a1",
77
+ [AW_H3_EHCI3] = 0x01c1d000,
88
.parent = TYPE_ASPEED_SOC,
78
+ [AW_H3_OHCI3] = 0x01c1d400,
89
.instance_size = sizeof(AspeedSoCState),
79
[AW_H3_CCU] = 0x01c20000,
90
.instance_init = aspeed_soc_ast2600_init,
80
[AW_H3_PIT] = 0x01c20c00,
91
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
81
[AW_H3_UART0] = 0x01c28000,
92
index XXXXXXX..XXXXXXX 100644
82
@@ -XXX,XX +XXX,XX @@ enum {
93
--- a/hw/misc/aspeed_scu.c
83
AW_H3_GIC_SPI_UART3 = 3,
94
+++ b/hw/misc/aspeed_scu.c
84
AW_H3_GIC_SPI_TIMER0 = 18,
95
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = {
85
AW_H3_GIC_SPI_TIMER1 = 19,
96
AST2500_A0_SILICON_REV,
86
+ AW_H3_GIC_SPI_EHCI0 = 72,
97
AST2500_A1_SILICON_REV,
87
+ AW_H3_GIC_SPI_OHCI0 = 73,
98
AST2600_A0_SILICON_REV,
88
+ AW_H3_GIC_SPI_EHCI1 = 74,
99
+ AST2600_A1_SILICON_REV,
89
+ AW_H3_GIC_SPI_OHCI1 = 75,
90
+ AW_H3_GIC_SPI_EHCI2 = 76,
91
+ AW_H3_GIC_SPI_OHCI2 = 77,
92
+ AW_H3_GIC_SPI_EHCI3 = 78,
93
+ AW_H3_GIC_SPI_OHCI3 = 79,
94
};
100
};
95
101
96
/* Allwinner H3 general constants */
102
bool is_supported_silicon_rev(uint32_t silicon_rev)
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
103
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
98
qdev_init_nofail(DEVICE(&s->ccu));
104
.valid.unaligned = false,
99
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
100
101
+ /* Universal Serial Bus */
102
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
103
+ qdev_get_gpio_in(DEVICE(&s->gic),
104
+ AW_H3_GIC_SPI_EHCI0));
105
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
106
+ qdev_get_gpio_in(DEVICE(&s->gic),
107
+ AW_H3_GIC_SPI_EHCI1));
108
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
109
+ qdev_get_gpio_in(DEVICE(&s->gic),
110
+ AW_H3_GIC_SPI_EHCI2));
111
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
112
+ qdev_get_gpio_in(DEVICE(&s->gic),
113
+ AW_H3_GIC_SPI_EHCI3));
114
+
115
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
116
+ qdev_get_gpio_in(DEVICE(&s->gic),
117
+ AW_H3_GIC_SPI_OHCI0));
118
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
119
+ qdev_get_gpio_in(DEVICE(&s->gic),
120
+ AW_H3_GIC_SPI_OHCI1));
121
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
122
+ qdev_get_gpio_in(DEVICE(&s->gic),
123
+ AW_H3_GIC_SPI_OHCI2));
124
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
125
+ qdev_get_gpio_in(DEVICE(&s->gic),
126
+ AW_H3_GIC_SPI_OHCI3));
127
+
128
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
129
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
130
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
131
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/usb/hcd-ehci-sysbus.c
134
+++ b/hw/usb/hcd-ehci-sysbus.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = {
136
.class_init = ehci_exynos4210_class_init,
137
};
105
};
138
106
139
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
107
-static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
140
+{
108
- [AST2600_SILICON_REV] = AST2600_SILICON_REV,
141
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
109
- [AST2600_SILICON_REV2] = AST2600_SILICON_REV,
142
+ DeviceClass *dc = DEVICE_CLASS(oc);
110
- [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
143
+
111
+static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
144
+ sec->capsbase = 0x0;
112
+ [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
145
+ sec->opregbase = 0x10;
113
[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
146
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
114
- [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
147
+}
115
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
148
+
116
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
149
+static const TypeInfo ehci_aw_h3_type_info = {
117
[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
150
+ .name = TYPE_AW_H3_EHCI,
118
[AST2600_HPLL_PARAM] = 0x1000405F,
151
+ .parent = TYPE_SYS_BUS_EHCI,
119
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
152
+ .class_init = ehci_aw_h3_class_init,
120
153
+};
121
dc->desc = "ASPEED 2600 System Control Unit";
154
+
122
dc->reset = aspeed_ast2600_scu_reset;
155
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
123
- asc->resets = ast2600_a0_resets;
156
{
124
+ asc->resets = ast2600_a1_resets;
157
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
125
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
158
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
126
asc->apb_divider = 4;
159
type_register_static(&ehci_type_info);
127
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
160
type_register_static(&ehci_platform_type_info);
161
type_register_static(&ehci_exynos4210_type_info);
162
+ type_register_static(&ehci_aw_h3_type_info);
163
type_register_static(&ehci_tegra2_type_info);
164
type_register_static(&ehci_ppc4xx_type_info);
165
type_register_static(&ehci_fusbh200_type_info);
166
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
167
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/arm/Kconfig
169
+++ b/hw/arm/Kconfig
170
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
171
select ARM_TIMER
172
select ARM_GIC
173
select UNIMP
174
+ select USB_OHCI
175
+ select USB_EHCI_SYSBUS
176
177
config RASPI
178
bool
179
--
128
--
180
2.20.1
129
2.20.1
181
130
182
131
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
In the Allwinner H3 SoC the SDRAM controller is responsible
3
The AST2600 handles this differently with the extra 'hardlock' state, so
4
for interfacing with the external Synchronous Dynamic Random
4
move the testing to the soc specific class' write callback.
5
Access Memory (SDRAM). Types of memory that the SDRAM controller
6
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
7
adds emulation support of the Allwinner H3 SDRAM controller.
8
5
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
11
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
8
Message-id: 20200505090136.341426-1-joel@jms.id.au
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/misc/Makefile.objs | 1 +
11
hw/misc/aspeed_sdmc.c | 55 +++++++++++++++++++++++++++++++++++--------
15
include/hw/arm/allwinner-h3.h | 5 +
12
1 file changed, 45 insertions(+), 10 deletions(-)
16
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
17
hw/arm/allwinner-h3.c | 19 +-
18
hw/arm/orangepi.c | 6 +
19
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
20
hw/misc/trace-events | 10 +
21
7 files changed, 502 insertions(+), 3 deletions(-)
22
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
23
create mode 100644 hw/misc/allwinner-h3-dramc.c
24
13
25
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
26
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/misc/Makefile.objs
16
--- a/hw/misc/aspeed_sdmc.c
28
+++ b/hw/misc/Makefile.objs
17
+++ b/hw/misc/aspeed_sdmc.c
29
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
30
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
32
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
33
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o
34
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
35
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
36
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
37
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/arm/allwinner-h3.h
40
+++ b/include/hw/arm/allwinner-h3.h
41
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@
42
#include "hw/intc/arm_gic.h"
19
43
#include "hw/misc/allwinner-h3-ccu.h"
20
/* Protection Key Register */
44
#include "hw/misc/allwinner-cpucfg.h"
21
#define R_PROT (0x00 / 4)
45
+#include "hw/misc/allwinner-h3-dramc.h"
22
+#define PROT_UNLOCKED 0x01
46
#include "hw/misc/allwinner-h3-sysctrl.h"
23
+#define PROT_HARDLOCKED 0x10 /* AST2600 */
47
#include "hw/misc/allwinner-sid.h"
24
+#define PROT_SOFTLOCKED 0x00
48
#include "hw/sd/allwinner-sdhost.h"
49
@@ -XXX,XX +XXX,XX @@ enum {
50
AW_H3_UART2,
51
AW_H3_UART3,
52
AW_H3_EMAC,
53
+ AW_H3_DRAMCOM,
54
+ AW_H3_DRAMCTL,
55
+ AW_H3_DRAMPHY,
56
AW_H3_GIC_DIST,
57
AW_H3_GIC_CPU,
58
AW_H3_GIC_HYP,
59
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
60
AwA10PITState timer;
61
AwH3ClockCtlState ccu;
62
AwCpuCfgState cpucfg;
63
+ AwH3DramCtlState dramc;
64
AwH3SysCtrlState sysctrl;
65
AwSidState sid;
66
AwSdHostState mmc0;
67
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h
68
new file mode 100644
69
index XXXXXXX..XXXXXXX
70
--- /dev/null
71
+++ b/include/hw/misc/allwinner-h3-dramc.h
72
@@ -XXX,XX +XXX,XX @@
73
+/*
74
+ * Allwinner H3 SDRAM Controller emulation
75
+ *
76
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
77
+ *
78
+ * This program is free software: you can redistribute it and/or modify
79
+ * it under the terms of the GNU General Public License as published by
80
+ * the Free Software Foundation, either version 2 of the License, or
81
+ * (at your option) any later version.
82
+ *
83
+ * This program is distributed in the hope that it will be useful,
84
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
85
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
86
+ * GNU General Public License for more details.
87
+ *
88
+ * You should have received a copy of the GNU General Public License
89
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
90
+ */
91
+
25
+
92
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
26
#define PROT_KEY_UNLOCK 0xFC600309
93
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
27
+#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
94
+
28
95
+#include "qom/object.h"
29
/* Configuration Register */
96
+#include "hw/sysbus.h"
30
#define R_CONF (0x04 / 4)
97
+#include "exec/hwaddr.h"
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
98
+
32
return;
99
+/**
33
}
100
+ * Constants
34
101
+ * @{
35
- if (addr == R_PROT) {
102
+ */
36
- s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
103
+
37
- return;
104
+/** Highest register address used by DRAMCOM module */
38
- }
105
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
39
-
106
+
40
- if (!s->regs[R_PROT]) {
107
+/** Total number of known DRAMCOM registers */
41
- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
108
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
42
- return;
109
+ sizeof(uint32_t))
43
- }
110
+
44
-
111
+/** Highest register address used by DRAMCTL module */
45
asc->write(s, addr, data);
112
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
113
+
114
+/** Total number of known DRAMCTL registers */
115
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
116
+ sizeof(uint32_t))
117
+
118
+/** Highest register address used by DRAMPHY module */
119
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
120
+
121
+/** Total number of known DRAMPHY registers */
122
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
123
+ sizeof(uint32_t))
124
+
125
+/** @} */
126
+
127
+/**
128
+ * Object model
129
+ * @{
130
+ */
131
+
132
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
133
+#define AW_H3_DRAMC(obj) \
134
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
135
+
136
+/** @} */
137
+
138
+/**
139
+ * Allwinner H3 SDRAM Controller object instance state.
140
+ */
141
+typedef struct AwH3DramCtlState {
142
+ /*< private >*/
143
+ SysBusDevice parent_obj;
144
+ /*< public >*/
145
+
146
+ /** Physical base address for start of RAM */
147
+ hwaddr ram_addr;
148
+
149
+ /** Total RAM size in megabytes */
150
+ uint32_t ram_size;
151
+
152
+ /**
153
+ * @name Memory Regions
154
+ * @{
155
+ */
156
+
157
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
158
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
159
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
160
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
161
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
162
+
163
+ /** @} */
164
+
165
+ /**
166
+ * @name Hardware Registers
167
+ * @{
168
+ */
169
+
170
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
171
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
172
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
173
+
174
+ /** @} */
175
+
176
+} AwH3DramCtlState;
177
+
178
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
179
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/hw/arm/allwinner-h3.c
182
+++ b/hw/arm/allwinner-h3.c
183
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
184
[AW_H3_UART2] = 0x01c28800,
185
[AW_H3_UART3] = 0x01c28c00,
186
[AW_H3_EMAC] = 0x01c30000,
187
+ [AW_H3_DRAMCOM] = 0x01c62000,
188
+ [AW_H3_DRAMCTL] = 0x01c63000,
189
+ [AW_H3_DRAMPHY] = 0x01c65000,
190
[AW_H3_GIC_DIST] = 0x01c81000,
191
[AW_H3_GIC_CPU] = 0x01c82000,
192
[AW_H3_GIC_HYP] = 0x01c84000,
193
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
194
{ "scr", 0x01c2c400, 1 * KiB },
195
{ "gpu", 0x01c40000, 64 * KiB },
196
{ "hstmr", 0x01c60000, 4 * KiB },
197
- { "dramcom", 0x01c62000, 4 * KiB },
198
- { "dramctl0", 0x01c63000, 4 * KiB },
199
- { "dramphy0", 0x01c65000, 4 * KiB },
200
{ "spi0", 0x01c68000, 4 * KiB },
201
{ "spi1", 0x01c69000, 4 * KiB },
202
{ "csi", 0x01cb0000, 320 * KiB },
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
206
TYPE_AW_SUN8I_EMAC);
207
+
208
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
209
+ TYPE_AW_H3_DRAMC);
210
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
211
+ "ram-addr", &error_abort);
212
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
213
+ "ram-size", &error_abort);
214
}
46
}
215
47
216
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
48
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
217
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
49
static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
218
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
50
uint32_t data)
219
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
51
{
220
52
+ if (reg == R_PROT) {
221
+ /* DRAMC */
53
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
222
+ qdev_init_nofail(DEVICE(&s->dramc));
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
224
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
225
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
226
+
227
/* Unimplemented devices */
228
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
229
create_unimplemented_device(unimplemented[i].device_name,
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/hw/arm/orangepi.c
233
+++ b/hw/arm/orangepi.c
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
235
/* Setup EMAC properties */
236
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
237
238
+ /* DRAMC */
239
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
240
+ "ram-addr", &error_abort);
241
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",
242
+ &error_abort);
243
+
244
/* Mark H3 object realized */
245
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
246
247
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
248
new file mode 100644
249
index XXXXXXX..XXXXXXX
250
--- /dev/null
251
+++ b/hw/misc/allwinner-h3-dramc.c
252
@@ -XXX,XX +XXX,XX @@
253
+/*
254
+ * Allwinner H3 SDRAM Controller emulation
255
+ *
256
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
257
+ *
258
+ * This program is free software: you can redistribute it and/or modify
259
+ * it under the terms of the GNU General Public License as published by
260
+ * the Free Software Foundation, either version 2 of the License, or
261
+ * (at your option) any later version.
262
+ *
263
+ * This program is distributed in the hope that it will be useful,
264
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
265
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
266
+ * GNU General Public License for more details.
267
+ *
268
+ * You should have received a copy of the GNU General Public License
269
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "qemu/units.h"
274
+#include "qemu/error-report.h"
275
+#include "hw/sysbus.h"
276
+#include "migration/vmstate.h"
277
+#include "qemu/log.h"
278
+#include "qemu/module.h"
279
+#include "exec/address-spaces.h"
280
+#include "hw/qdev-properties.h"
281
+#include "qapi/error.h"
282
+#include "hw/misc/allwinner-h3-dramc.h"
283
+#include "trace.h"
284
+
285
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
286
+
287
+/* DRAMCOM register offsets */
288
+enum {
289
+ REG_DRAMCOM_CR = 0x0000, /* Control Register */
290
+};
291
+
292
+/* DRAMCTL register offsets */
293
+enum {
294
+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
295
+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
296
+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */
297
+};
298
+
299
+/* DRAMCTL register flags */
300
+enum {
301
+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
302
+};
303
+
304
+enum {
305
+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
306
+};
307
+
308
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
309
+ uint8_t bank_bits, uint16_t page_size)
310
+{
311
+ /*
312
+ * This function simulates row addressing behavior when bootloader
313
+ * software attempts to detect the amount of available SDRAM. In U-Boot
314
+ * the controller is configured with the widest row addressing available.
315
+ * Then a pattern is written to RAM at an offset on the row boundary size.
316
+ * If the value read back equals the value read back from the
317
+ * start of RAM, the bootloader knows the amount of row bits.
318
+ *
319
+ * This function inserts a mirrored memory region when the configured row
320
+ * bits are not matching the actual emulated memory, to simulate the
321
+ * same behavior on hardware as expected by the bootloader.
322
+ */
323
+ uint8_t row_bits_actual = 0;
324
+
325
+ /* Calculate the actual row bits using the ram_size property */
326
+ for (uint8_t i = 8; i < 12; i++) {
327
+ if (1 << i == s->ram_size) {
328
+ row_bits_actual = i + 3;
329
+ break;
330
+ }
331
+ }
332
+
333
+ if (s->ram_size == (1 << (row_bits - 3))) {
334
+ /* When row bits is the expected value, remove the mirror */
335
+ memory_region_set_enabled(&s->row_mirror_alias, false);
336
+ trace_allwinner_h3_dramc_rowmirror_disable();
337
+
338
+ } else if (row_bits_actual) {
339
+ /* Row bits not matching ram_size, install the rows mirror */
340
+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
341
+ bank_bits)) * page_size);
342
+
343
+ memory_region_set_enabled(&s->row_mirror_alias, true);
344
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
345
+
346
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
347
+ }
348
+}
349
+
350
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
351
+ unsigned size)
352
+{
353
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
354
+ const uint32_t idx = REG_INDEX(offset);
355
+
356
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
357
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
358
+ __func__, (uint32_t)offset);
359
+ return 0;
360
+ }
361
+
362
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
363
+
364
+ return s->dramcom[idx];
365
+}
366
+
367
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
368
+ uint64_t val, unsigned size)
369
+{
370
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
371
+ const uint32_t idx = REG_INDEX(offset);
372
+
373
+ trace_allwinner_h3_dramcom_write(offset, val, size);
374
+
375
+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
376
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
377
+ __func__, (uint32_t)offset);
378
+ return;
54
+ return;
379
+ }
55
+ }
380
+
56
+
381
+ switch (offset) {
57
+ if (!s->regs[R_PROT]) {
382
+ case REG_DRAMCOM_CR: /* Control Register */
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
383
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
384
+ ((val >> 2) & 0x1) + 2,
385
+ 1 << (((val >> 8) & 0xf) + 3));
386
+ break;
387
+ default:
388
+ break;
389
+ };
390
+
391
+ s->dramcom[idx] = (uint32_t) val;
392
+}
393
+
394
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
395
+ unsigned size)
396
+{
397
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
398
+ const uint32_t idx = REG_INDEX(offset);
399
+
400
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
401
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
402
+ __func__, (uint32_t)offset);
403
+ return 0;
404
+ }
405
+
406
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
407
+
408
+ return s->dramctl[idx];
409
+}
410
+
411
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
412
+ uint64_t val, unsigned size)
413
+{
414
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
415
+ const uint32_t idx = REG_INDEX(offset);
416
+
417
+ trace_allwinner_h3_dramctl_write(offset, val, size);
418
+
419
+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
420
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
421
+ __func__, (uint32_t)offset);
422
+ return;
59
+ return;
423
+ }
60
+ }
424
+
61
+
425
+ switch (offset) {
62
switch (reg) {
426
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
63
case R_CONF:
427
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
64
data = aspeed_2400_sdmc_compute_conf(s, data);
428
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
65
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
429
+ break;
66
static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
430
+ default:
67
uint32_t data)
431
+ break;
68
{
432
+ }
69
+ if (reg == R_PROT) {
433
+
70
+ s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
434
+ s->dramctl[idx] = (uint32_t) val;
435
+}
436
+
437
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
438
+ unsigned size)
439
+{
440
+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
441
+ const uint32_t idx = REG_INDEX(offset);
442
+
443
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
445
+ __func__, (uint32_t)offset);
446
+ return 0;
447
+ }
448
+
449
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
450
+
451
+ return s->dramphy[idx];
452
+}
453
+
454
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
455
+ uint64_t val, unsigned size)
456
+{
457
+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
458
+ const uint32_t idx = REG_INDEX(offset);
459
+
460
+ trace_allwinner_h3_dramphy_write(offset, val, size);
461
+
462
+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
463
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
464
+ __func__, (uint32_t)offset);
465
+ return;
71
+ return;
466
+ }
72
+ }
467
+
73
+
468
+ s->dramphy[idx] = (uint32_t) val;
74
+ if (!s->regs[R_PROT]) {
469
+}
75
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
470
+
76
+ return;
471
+static const MemoryRegionOps allwinner_h3_dramcom_ops = {
472
+ .read = allwinner_h3_dramcom_read,
473
+ .write = allwinner_h3_dramcom_write,
474
+ .endianness = DEVICE_NATIVE_ENDIAN,
475
+ .valid = {
476
+ .min_access_size = 4,
477
+ .max_access_size = 4,
478
+ },
479
+ .impl.min_access_size = 4,
480
+};
481
+
482
+static const MemoryRegionOps allwinner_h3_dramctl_ops = {
483
+ .read = allwinner_h3_dramctl_read,
484
+ .write = allwinner_h3_dramctl_write,
485
+ .endianness = DEVICE_NATIVE_ENDIAN,
486
+ .valid = {
487
+ .min_access_size = 4,
488
+ .max_access_size = 4,
489
+ },
490
+ .impl.min_access_size = 4,
491
+};
492
+
493
+static const MemoryRegionOps allwinner_h3_dramphy_ops = {
494
+ .read = allwinner_h3_dramphy_read,
495
+ .write = allwinner_h3_dramphy_write,
496
+ .endianness = DEVICE_NATIVE_ENDIAN,
497
+ .valid = {
498
+ .min_access_size = 4,
499
+ .max_access_size = 4,
500
+ },
501
+ .impl.min_access_size = 4,
502
+};
503
+
504
+static void allwinner_h3_dramc_reset(DeviceState *dev)
505
+{
506
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
507
+
508
+ /* Set default values for registers */
509
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
510
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
511
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
512
+}
513
+
514
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
515
+{
516
+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);
517
+
518
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
519
+ for (uint8_t i = 8; i < 13; i++) {
520
+ if (1 << i == s->ram_size) {
521
+ break;
522
+ } else if (i == 12) {
523
+ error_report("%s: ram-size %u MiB is not supported",
524
+ __func__, s->ram_size);
525
+ exit(1);
526
+ }
527
+ }
77
+ }
528
+
78
+
529
+ /* Setup row mirror mappings */
79
switch (reg) {
530
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
80
case R_CONF:
531
+ "allwinner-h3-dramc.row-mirror",
81
data = aspeed_2500_sdmc_compute_conf(s, data);
532
+ 4 * KiB, &error_abort);
82
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
533
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
83
static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
534
+ &s->row_mirror, 10);
84
uint32_t data)
85
{
86
+ if (s->regs[R_PROT] == PROT_HARDLOCKED) {
87
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
88
+ __func__);
89
+ return;
90
+ }
535
+
91
+
536
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
92
+ if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
537
+ "allwinner-h3-dramc.row-mirror-alias",
93
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
538
+ &s->row_mirror, 0, 4 * KiB);
94
+ return;
539
+ memory_region_add_subregion_overlap(get_system_memory(),
95
+ }
540
+ s->ram_addr + 1 * MiB,
541
+ &s->row_mirror_alias, 10);
542
+ memory_region_set_enabled(&s->row_mirror_alias, false);
543
+}
544
+
96
+
545
+static void allwinner_h3_dramc_init(Object *obj)
97
switch (reg) {
546
+{
98
+ case R_PROT:
547
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
99
+ if (data == PROT_KEY_UNLOCK) {
548
+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);
100
+ data = PROT_UNLOCKED;
549
+
101
+ } else if (data == PROT_KEY_HARDLOCK) {
550
+ /* DRAMCOM registers */
102
+ data = PROT_HARDLOCKED;
551
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
103
+ } else {
552
+ &allwinner_h3_dramcom_ops, s,
104
+ data = PROT_SOFTLOCKED;
553
+ TYPE_AW_H3_DRAMC, 4 * KiB);
105
+ }
554
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
106
+ break;
555
+
107
case R_CONF:
556
+ /* DRAMCTL registers */
108
data = aspeed_2600_sdmc_compute_conf(s, data);
557
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
109
break;
558
+ &allwinner_h3_dramctl_ops, s,
559
+ TYPE_AW_H3_DRAMC, 4 * KiB);
560
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
561
+
562
+ /* DRAMPHY registers */
563
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
564
+ &allwinner_h3_dramphy_ops, s,
565
+ TYPE_AW_H3_DRAMC, 4 * KiB);
566
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
567
+}
568
+
569
+static Property allwinner_h3_dramc_properties[] = {
570
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
571
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
572
+ DEFINE_PROP_END_OF_LIST()
573
+};
574
+
575
+static const VMStateDescription allwinner_h3_dramc_vmstate = {
576
+ .name = "allwinner-h3-dramc",
577
+ .version_id = 1,
578
+ .minimum_version_id = 1,
579
+ .fields = (VMStateField[]) {
580
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
581
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
582
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
583
+ VMSTATE_END_OF_LIST()
584
+ }
585
+};
586
+
587
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
588
+{
589
+ DeviceClass *dc = DEVICE_CLASS(klass);
590
+
591
+ dc->reset = allwinner_h3_dramc_reset;
592
+ dc->vmsd = &allwinner_h3_dramc_vmstate;
593
+ dc->realize = allwinner_h3_dramc_realize;
594
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
595
+}
596
+
597
+static const TypeInfo allwinner_h3_dramc_info = {
598
+ .name = TYPE_AW_H3_DRAMC,
599
+ .parent = TYPE_SYS_BUS_DEVICE,
600
+ .instance_init = allwinner_h3_dramc_init,
601
+ .instance_size = sizeof(AwH3DramCtlState),
602
+ .class_init = allwinner_h3_dramc_class_init,
603
+};
604
+
605
+static void allwinner_h3_dramc_register(void)
606
+{
607
+ type_register_static(&allwinner_h3_dramc_info);
608
+}
609
+
610
+type_init(allwinner_h3_dramc_register)
611
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
612
index XXXXXXX..XXXXXXX 100644
613
--- a/hw/misc/trace-events
614
+++ b/hw/misc/trace-events
615
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
616
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
617
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
618
619
+# allwinner-h3-dramc.c
620
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
621
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64
622
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
623
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
624
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
625
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
626
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
627
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
628
+
629
# allwinner-sid.c
630
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
631
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
632
--
110
--
633
2.20.1
111
2.20.1
634
112
635
113
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots U-Boot then NetBSD (stored on a SD card) on
3
On the NRF51 series, all peripherals have a fixed I/O size
4
a OrangePi PC board.
4
of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it.
5
6
As it requires ~1.3GB of storage, it is disabled by default.
7
8
U-Boot is built by the Debian project [1], and the SD card image
9
is provided by the NetBSD organization [2].
10
11
Once the compressed SD card image is downloaded (304MB) and
12
extracted, this test is fast:
13
14
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
15
avocado --show=app,console run -t machine:orangepi-pc \
16
tests/acceptance/boot_linux_console.py
17
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
18
console: DRAM: 1024 MiB
19
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
20
console: CPU: Allwinner H3 (SUN8I 0000)
21
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
22
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
23
console: scanning usb for storage devices... 0 Storage Device(s) found
24
console: Hit any key to stop autoboot: 0
25
console: => setenv bootargs root=ld0a
26
console: => setenv kernel netbsd-GENERIC.ub
27
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
28
console: => boot
29
console: ## Booting kernel from Legacy Image at 42000000 ...
30
console: Image Name: NetBSD/earmv7hf 9.0_RC1
31
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
32
console: XIP Kernel Image (no loading done)
33
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
34
console: Starting kernel ...
35
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
36
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
37
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
38
console: [ 1.0000000] total memory = 1024 MB
39
console: [ 1.0000000] avail memory = 1003 MB
40
console: [ 1.0000000] armfdt0 (root)
41
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
42
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
43
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
44
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
45
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
46
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
47
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
48
...
49
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
50
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
51
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors
52
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
53
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log.
54
console: [ 3.1179868] boot device: ld0
55
console: [ 3.1470623] root on ld0a dumps on ld0b
56
console: [ 3.2464436] root file system type: ffs
57
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
58
console: Mon Feb 17 20:33:35 UTC 2020
59
console: Starting root file system check:
60
PASS (35.96 s)
61
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
62
JOB TIME : 36.09 s
63
64
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
65
66
This test is based on a description from Niek Linnenbank from [4].
67
68
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
69
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
70
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
71
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
72
5
73
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
74
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
75
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200504072822.18799-2-f4bug@amsat.org
76
Tested-by: Alex Bennée <alex.bennee@linaro.org>
77
Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com
78
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
---
10
---
81
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
11
include/hw/arm/nrf51.h | 3 +--
82
1 file changed, 70 insertions(+)
12
include/hw/i2c/microbit_i2c.h | 2 +-
13
hw/arm/nrf51_soc.c | 4 ++--
14
hw/i2c/microbit_i2c.c | 2 +-
15
hw/timer/nrf51_timer.c | 2 +-
16
5 files changed, 6 insertions(+), 7 deletions(-)
83
17
84
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
18
diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h
85
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/acceptance/boot_linux_console.py
20
--- a/include/hw/arm/nrf51.h
87
+++ b/tests/acceptance/boot_linux_console.py
21
+++ b/include/hw/arm/nrf51.h
88
@@ -XXX,XX +XXX,XX @@ import shutil
22
@@ -XXX,XX +XXX,XX @@
89
from avocado import skipUnless
23
#define NRF51_IOMEM_BASE 0x40000000
90
from avocado_qemu import Test
24
#define NRF51_IOMEM_SIZE 0x20000000
91
from avocado_qemu import exec_command_and_wait_for_pattern
25
92
+from avocado_qemu import interrupt_interactive_console_until_pattern
26
+#define NRF51_PERIPHERAL_SIZE 0x00001000
93
from avocado_qemu import wait_for_console_pattern
27
#define NRF51_UART_BASE 0x40002000
94
from avocado.utils import process
28
#define NRF51_TWI_BASE 0x40003000
95
from avocado.utils import archive
29
-#define NRF51_TWI_SIZE 0x00001000
96
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
30
#define NRF51_TIMER_BASE 0x40008000
97
'to <orangepipc>')
31
-#define NRF51_TIMER_SIZE 0x00001000
98
self.wait_for_console_pattern('Starting Load Kernel Modules...')
32
#define NRF51_RNG_BASE 0x4000D000
99
33
#define NRF51_NVMC_BASE 0x4001E000
100
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
34
#define NRF51_GPIO_BASE 0x50000000
101
+ def test_arm_orangepi_uboot_netbsd9(self):
35
diff --git a/include/hw/i2c/microbit_i2c.h b/include/hw/i2c/microbit_i2c.h
102
+ """
36
index XXXXXXX..XXXXXXX 100644
103
+ :avocado: tags=arch:arm
37
--- a/include/hw/i2c/microbit_i2c.h
104
+ :avocado: tags=machine:orangepi-pc
38
+++ b/include/hw/i2c/microbit_i2c.h
105
+ """
39
@@ -XXX,XX +XXX,XX @@
106
+ # This test download a 304MB compressed image and expand it to 1.3GB...
40
#define MICROBIT_I2C(obj) \
107
+ deb_url = ('http://snapshot.debian.org/archive/debian/'
41
OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C)
108
+ '20200108T145233Z/pool/main/u/u-boot/'
42
109
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
43
-#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t))
110
+ deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99'
44
+#define MICROBIT_I2C_NREGS (NRF51_PERIPHERAL_SIZE / sizeof(uint32_t))
111
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
45
112
+ # We use the common OrangePi PC 'plus' build of U-Boot for our secondary
46
typedef struct {
113
+ # program loader (SPL). We will then set the path to the more specific
47
SysBusDevice parent_obj;
114
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt,
48
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
115
+ # before to boot NetBSD.
49
index XXXXXXX..XXXXXXX 100644
116
+ uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin'
50
--- a/hw/arm/nrf51_soc.c
117
+ uboot_path = self.extract_from_deb(deb_path, uboot_path)
51
+++ b/hw/arm/nrf51_soc.c
118
+ image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
52
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
119
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
53
return;
120
+ image_hash = '2babb29d36d8360adcb39c09e31060945259917a'
54
}
121
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
55
122
+ image_path = os.path.join(self.workdir, 'armv7.img')
56
- base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
123
+ image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path
57
+ base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
124
+ archive.gzip_uncompress(image_path_gz, image_path)
58
125
+
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
126
+ # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
127
+ with open(uboot_path, 'rb') as f_in:
61
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
128
+ with open(image_path, 'r+b') as f_out:
62
129
+ f_out.seek(8 * 1024)
63
/* STUB Peripherals */
130
+ shutil.copyfileobj(f_in, f_out)
64
memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
131
+
65
- "nrf51_soc.clock", 0x1000);
132
+ # Extend image, to avoid that NetBSD thinks the partition
66
+ "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
133
+ # inside the image is larger than device size itself
67
memory_region_add_subregion_overlap(&s->container,
134
+ f_out.seek(0, 2)
68
NRF51_IOMEM_BASE, &s->clock, -1);
135
+ f_out.seek(64 * 1024 * 1024, 1)
69
136
+ f_out.write(bytearray([0x00]))
70
diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c
137
+
71
index XXXXXXX..XXXXXXX 100644
138
+ self.vm.set_console()
72
--- a/hw/i2c/microbit_i2c.c
139
+ self.vm.add_args('-nic', 'user',
73
+++ b/hw/i2c/microbit_i2c.c
140
+ '-drive', image_drive_args,
74
@@ -XXX,XX +XXX,XX @@ static void microbit_i2c_realize(DeviceState *dev, Error **errp)
141
+ '-global', 'allwinner-rtc.base-year=2000',
75
MicrobitI2CState *s = MICROBIT_I2C(dev);
142
+ '-no-reboot')
76
143
+ self.vm.launch()
77
memory_region_init_io(&s->iomem, OBJECT(s), &microbit_i2c_ops, s,
144
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
78
- "microbit.twi", NRF51_TWI_SIZE);
145
+ interrupt_interactive_console_until_pattern(self,
79
+ "microbit.twi", NRF51_PERIPHERAL_SIZE);
146
+ 'Hit any key to stop autoboot:',
80
sysbus_init_mmio(sbd, &s->iomem);
147
+ 'switch to partitions #0, OK')
81
}
148
+
82
149
+ exec_command_and_wait_for_pattern(self, '', '=>')
83
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
150
+ cmd = 'setenv bootargs root=ld0a'
84
index XXXXXXX..XXXXXXX 100644
151
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
85
--- a/hw/timer/nrf51_timer.c
152
+ cmd = 'setenv kernel netbsd-GENERIC.ub'
86
+++ b/hw/timer/nrf51_timer.c
153
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
87
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_init(Object *obj)
154
+ cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
88
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
155
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
89
156
+ cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; "
90
memory_region_init_io(&s->iomem, obj, &rng_ops, s,
157
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
91
- TYPE_NRF51_TIMER, NRF51_TIMER_SIZE);
158
+ "fdt addr ${fdt_addr_r}; "
92
+ TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
159
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
93
sysbus_init_mmio(sbd, &s->iomem);
160
+ exec_command_and_wait_for_pattern(self, cmd, '=>')
94
sysbus_init_irq(sbd, &s->irq);
161
+
95
162
+ exec_command_and_wait_for_pattern(self, 'boot',
163
+ 'Booting kernel from Legacy Image')
164
+ wait_for_console_pattern(self, 'Starting kernel ...')
165
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
166
+ # Wait for user-space
167
+ wait_for_console_pattern(self, 'Starting root file system check')
168
+
169
def test_s390x_s390_ccw_virtio(self):
170
"""
171
:avocado: tags=arch:s390x
172
--
96
--
173
2.20.1
97
2.20.1
174
98
175
99
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots Ubuntu Bionic on a OrangePi PC board.
3
The NRF51 series SoC have 3 timer peripherals, each having
4
4
4 counters. To help differentiate which peripheral is accessed,
5
As it requires 1GB of storage, and is slow, this test is disabled
5
display the timer ID in the trace events.
6
on automatic CI testing.
7
8
It is useful for workstation testing. Currently Avocado timeouts too
9
quickly, so we can't run userland commands.
10
11
The kernel image and DeviceTree blob are built by the Armbian
12
project (based on Debian):
13
https://www.armbian.com/orange-pi-pc/
14
15
The Ubuntu image is downloaded from:
16
https://dl.armbian.com/orangepipc/Bionic_current
17
18
This test can be run using:
19
20
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
21
avocado --show=app,console run -t machine:orangepi-pc \
22
tests/acceptance/boot_linux_console.py
23
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
24
console: DRAM: 1024 MiB
25
console: Failed to set core voltage! Can't set CPU frequency
26
console: Trying to boot from MMC1
27
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
28
console: CPU: Allwinner H3 (SUN8I 0000)
29
console: Model: Xunlong Orange Pi PC
30
console: DRAM: 1 GiB
31
console: MMC: mmc@1c0f000: 0
32
[...]
33
console: Uncompressing Linux... done, booting the kernel.
34
console: Booting Linux on physical CPU 0x0
35
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
36
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
37
console: CPU: div instructions available: patching division code
38
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
39
console: OF: fdt: Machine model: Xunlong Orange Pi PC
40
[...]
41
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
42
console: done.
43
console: Begin: Running /scripts/local-bottom ... done.
44
console: Begin: Running /scripts/init-bottom ... done.
45
console: systemd[1]: systemd 237 running in system mode. (...)
46
console: systemd[1]: Detected architecture arm.
47
console: Welcome to Ubuntu 18.04.3 LTS!
48
console: systemd[1]: Set hostname to <orangepipc>.
49
6
50
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
51
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
52
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200504072822.18799-4-f4bug@amsat.org
53
Tested-by: Alex Bennée <alex.bennee@linaro.org>
54
Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com
55
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
56
[NL: changed test to boot from SD card via BootROM, added check for 7z]
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
58
---
11
---
59
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
12
include/hw/timer/nrf51_timer.h | 1 +
60
1 file changed, 48 insertions(+)
13
hw/arm/nrf51_soc.c | 5 +++++
14
hw/timer/nrf51_timer.c | 11 +++++++++--
15
hw/timer/trace-events | 4 ++--
16
4 files changed, 17 insertions(+), 4 deletions(-)
61
17
62
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
18
diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h
63
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
64
--- a/tests/acceptance/boot_linux_console.py
20
--- a/include/hw/timer/nrf51_timer.h
65
+++ b/tests/acceptance/boot_linux_console.py
21
+++ b/include/hw/timer/nrf51_timer.h
66
@@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern
22
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51TimerState {
67
from avocado_qemu import wait_for_console_pattern
23
MemoryRegion iomem;
68
from avocado.utils import process
24
qemu_irq irq;
69
from avocado.utils import archive
25
70
+from avocado.utils.path import find_command, CmdNotFoundError
26
+ uint8_t id;
71
27
QEMUTimer timer;
72
+P7ZIP_AVAILABLE = True
28
int64_t timer_start_ns;
73
+try:
29
int64_t update_counter_ns;
74
+ find_command('7z')
30
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
75
+except CmdNotFoundError:
31
index XXXXXXX..XXXXXXX 100644
76
+ P7ZIP_AVAILABLE = False
32
--- a/hw/arm/nrf51_soc.c
77
33
+++ b/hw/arm/nrf51_soc.c
78
class BootLinuxConsole(Test):
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
79
"""
35
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
36
/* TIMER */
81
exec_command_and_wait_for_pattern(self, 'reboot',
37
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
82
'reboot: Restarting system')
38
+ object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
83
39
+ if (err) {
84
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
40
+ error_propagate(errp, err);
85
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
41
+ return;
86
+ def test_arm_orangepi_bionic(self):
42
+ }
87
+ """
43
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
88
+ :avocado: tags=arch:arm
44
if (err) {
89
+ :avocado: tags=machine:orangepi-pc
45
error_propagate(errp, err);
90
+ """
46
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/timer/nrf51_timer.c
49
+++ b/hw/timer/nrf51_timer.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "hw/arm/nrf51.h"
52
#include "hw/irq.h"
53
#include "hw/timer/nrf51_timer.h"
54
+#include "hw/qdev-properties.h"
55
#include "migration/vmstate.h"
56
#include "trace.h"
57
58
@@ -XXX,XX +XXX,XX @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
59
__func__, offset);
60
}
61
62
- trace_nrf51_timer_read(offset, r, size);
63
+ trace_nrf51_timer_read(s->id, offset, r, size);
64
65
return r;
66
}
67
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
68
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
69
size_t idx;
70
71
- trace_nrf51_timer_write(offset, value, size);
72
+ trace_nrf51_timer_write(s->id, offset, value, size);
73
74
switch (offset) {
75
case NRF51_TIMER_TASK_START:
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nrf51_timer = {
77
}
78
};
79
80
+static Property nrf51_timer_properties[] = {
81
+ DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
82
+ DEFINE_PROP_END_OF_LIST(),
83
+};
91
+
84
+
92
+ # This test download a 196MB compressed image and expand it to 932MB...
85
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
93
+ image_url = ('https://dl.armbian.com/orangepipc/archive/'
86
{
94
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
87
DeviceClass *dc = DEVICE_CLASS(klass);
95
+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'
88
96
+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)
89
dc->reset = nrf51_timer_reset;
97
+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'
90
dc->vmsd = &vmstate_nrf51_timer;
98
+ image_path = os.path.join(self.workdir, image_name)
91
+ device_class_set_props(dc, nrf51_timer_properties);
99
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
92
}
100
+
93
101
+ self.vm.set_console()
94
static const TypeInfo nrf51_timer_info = {
102
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
95
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
103
+ '-nic', 'user',
96
index XXXXXXX..XXXXXXX 100644
104
+ '-no-reboot')
97
--- a/hw/timer/trace-events
105
+ self.vm.launch()
98
+++ b/hw/timer/trace-events
106
+
99
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK
107
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
100
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
108
+ 'console=ttyS0,115200 '
101
109
+ 'loglevel=7 '
102
# nrf51_timer.c
110
+ 'nosmp '
103
-nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
111
+ 'systemd.default_timeout_start_sec=9000 '
104
-nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
112
+ 'systemd.mask=armbian-zram-config.service '
105
+nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
113
+ 'systemd.mask=armbian-ramlog.service')
106
+nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
114
+
107
115
+ self.wait_for_console_pattern('U-Boot SPL')
108
# bcm2835_systmr.c
116
+ self.wait_for_console_pattern('Autoboot in ')
109
bcm2835_systmr_irq(bool enable) "timer irq state %u"
117
+ exec_command_and_wait_for_pattern(self, ' ', '=>')
118
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
119
+ kernel_command_line + "'", '=>')
120
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
121
+
122
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
123
+ 'to <orangepipc>')
124
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
125
+
126
def test_s390x_s390_ccw_virtio(self):
127
"""
128
:avocado: tags=arch:s390x
129
--
110
--
130
2.20.1
111
2.20.1
131
112
132
113
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The kernel image and DeviceTree blob are built by the Armbian
3
Add trace event to display timer's counter value updates.
4
project (based on Debian):
5
https://www.armbian.com/orange-pi-pc/
6
7
The SD image is from the kernelci.org project:
8
https://kernelci.org/faq/#the-code
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
16
console: Uncompressing Linux... done, booting the kernel.
17
console: Booting Linux on physical CPU 0x0
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
19
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
20
[...]
21
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
22
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
23
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
24
console: ledtrig-cpu: registered to indicate activity on CPUs
25
console: hidraw: raw HID events driver (C) Jiri Kosina
26
console: usbcore: registered new interface driver usbhid
27
console: usbhid: USB HID core driver
28
console: Initializing XFRM netlink socket
29
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
30
console: NET: Registered protocol family 10
31
console: mmc0: host does not support reading read-only switch, assuming write-enable
32
console: mmc0: Problem switching card into high-speed mode!
33
console: mmc0: new SD card at address 4567
34
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
35
[...]
36
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
37
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
38
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
39
console: Run /sbin/init as init process
40
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
41
console: Starting syslogd: OK
42
console: Starting klogd: OK
43
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
44
console: /bin/sh: can't access tty; job control turned off
45
console: cat /proc/partitions
46
console: / # cat /proc/partitions
47
console: major minor #blocks name
48
console: 1 0 4096 ram0
49
console: 1 1 4096 ram1
50
console: 1 2 4096 ram2
51
console: 1 3 4096 ram3
52
console: 179 0 61440 mmcblk0
53
console: reboot
54
console: / # reboot
55
console: umount: devtmpfs busy - remounted read-only
56
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
57
console: The system is going down NOW!
58
console: Sent SIGTERM to all processes
59
console: Sent SIGKILL to all processes
60
console: Requesting system reboot
61
console: reboot: Restarting system
62
JOB TIME : 68.64 s
63
4
64
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
65
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
66
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200504072822.18799-5-f4bug@amsat.org
67
Tested-by: Alex Bennée <alex.bennee@linaro.org>
68
Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com
69
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
70
[NL: extend test with ethernet device checks]
71
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
72
---
9
---
73
tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++
10
hw/timer/nrf51_timer.c | 1 +
74
1 file changed, 47 insertions(+)
11
hw/timer/trace-events | 1 +
12
2 files changed, 2 insertions(+)
75
13
76
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
14
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
77
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
78
--- a/tests/acceptance/boot_linux_console.py
16
--- a/hw/timer/nrf51_timer.c
79
+++ b/tests/acceptance/boot_linux_console.py
17
+++ b/hw/timer/nrf51_timer.c
80
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
18
@@ -XXX,XX +XXX,XX @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
81
exec_command_and_wait_for_pattern(self, 'reboot',
19
82
'reboot: Restarting system')
20
idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
83
21
s->cc[idx] = s->counter;
84
+ def test_arm_orangepi_sd(self):
22
+ trace_nrf51_timer_set_count(s->id, idx, s->counter);
85
+ """
23
}
86
+ :avocado: tags=arch:arm
24
break;
87
+ :avocado: tags=machine:orangepi-pc
25
case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
88
+ """
26
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
89
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
27
index XXXXXXX..XXXXXXX 100644
90
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
28
--- a/hw/timer/trace-events
91
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
29
+++ b/hw/timer/trace-events
92
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
30
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
93
+ kernel_path = self.extract_from_deb(deb_path,
31
# nrf51_timer.c
94
+ '/boot/vmlinuz-4.20.7-sunxi')
32
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
95
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
33
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
96
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
34
+nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
97
+ rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
35
98
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
36
# bcm2835_systmr.c
99
+ rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061'
37
bcm2835_systmr_irq(bool enable) "timer irq state %u"
100
+ rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
101
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
102
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
103
+
104
+ self.vm.set_console()
105
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
106
+ 'console=ttyS0,115200 '
107
+ 'root=/dev/mmcblk0 rootwait rw '
108
+ 'panic=-1 noreboot')
109
+ self.vm.add_args('-kernel', kernel_path,
110
+ '-dtb', dtb_path,
111
+ '-drive', 'file=' + rootfs_path + ',if=sd,format=raw',
112
+ '-append', kernel_command_line,
113
+ '-no-reboot')
114
+ self.vm.launch()
115
+ shell_ready = "/bin/sh: can't access tty; job control turned off"
116
+ self.wait_for_console_pattern(shell_ready)
117
+
118
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
119
+ 'Allwinner sun8i Family')
120
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
121
+ 'mmcblk0')
122
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
123
+ 'eth0: Link is Up')
124
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
125
+ 'udhcpc: lease of 10.0.2.15 obtained')
126
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
127
+ '3 packets transmitted, 3 packets received, 0% packet loss')
128
+ exec_command_and_wait_for_pattern(self, 'reboot',
129
+ 'reboot: Restarting system')
130
+
131
def test_s390x_s390_ccw_virtio(self):
132
"""
133
:avocado: tags=arch:s390x
134
--
38
--
135
2.20.1
39
2.20.1
136
40
137
41
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
At the moment if the end-user does not specify the gic-version along
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
with KVM acceleration, v2 is set by default. However most of the
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
systems now have GICv3 and sometimes they do not support GICv2
5
Message-id: 20200508154359.7494-2-richard.henderson@linaro.org
6
compatibility.
7
8
This patch keeps the default v2 selection in all cases except
9
in the KVM accelerated mode when either
10
- the host does not support GICv2 in-kernel emulation or
11
- number of VCPUS exceeds 8.
12
13
Those cases did not work anyway so we do not break any compatibility.
14
Now we get v3 selected in such a case.
15
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
18
Reviewed-by: Andrew Jones <drjones@redhat.com>
19
Message-id: 20200311131618.7187-7-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
7
---
22
hw/arm/virt.c | 17 ++++++++++++++++-
8
include/hw/core/cpu.h | 23 +++++++++++++++++++++++
23
1 file changed, 16 insertions(+), 1 deletion(-)
9
1 file changed, 23 insertions(+)
24
10
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
11
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
26
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
13
--- a/include/hw/core/cpu.h
28
+++ b/hw/arm/virt.c
14
+++ b/include/hw/core/cpu.h
29
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
15
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
30
*/
16
vaddr len, int flags);
31
static void finalize_gic_version(VirtMachineState *vms)
17
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
32
{
18
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
33
+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
34
+
19
+
35
if (kvm_enabled()) {
20
+/**
36
int probe_bitmap;
21
+ * cpu_check_watchpoint:
37
22
+ * @cpu: cpu context
38
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
23
+ * @addr: guest virtual address
39
}
24
+ * @len: access length
40
return;
25
+ * @attrs: memory access attributes
41
case VIRT_GIC_VERSION_NOSEL:
26
+ * @flags: watchpoint access type
42
- vms->gic_version = VIRT_GIC_VERSION_2;
27
+ * @ra: unwind return address
43
+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
28
+ *
44
+ vms->gic_version = VIRT_GIC_VERSION_2;
29
+ * Check for a watchpoint hit in [addr, addr+len) of the type
45
+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
30
+ * specified by @flags. Exit via exception with a hit.
46
+ /*
31
+ */
47
+ * in case the host does not support v2 in-kernel emulation or
32
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
48
+ * the end-user requested more than 8 VCPUs we now default
33
MemTxAttrs attrs, int flags, uintptr_t ra);
49
+ * to v3. In any case defaulting to v2 would be broken.
34
+
50
+ */
35
+/**
51
+ vms->gic_version = VIRT_GIC_VERSION_3;
36
+ * cpu_watchpoint_address_matches:
52
+ } else if (max_cpus > GIC_NCPU) {
37
+ * @cpu: cpu context
53
+ error_report("host only supports in-kernel GICv2 emulation "
38
+ * @addr: guest virtual address
54
+ "but more than 8 vcpus are requested");
39
+ * @len: access length
55
+ exit(1);
40
+ *
56
+ }
41
+ * Return the watchpoint flags that apply to [addr, addr+len).
57
break;
42
+ * If no watchpoint is registered for the range, the result is 0.
58
case VIRT_GIC_VERSION_2:
43
+ */
59
case VIRT_GIC_VERSION_3:
44
int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
45
#endif
46
60
--
47
--
61
2.20.1
48
2.20.1
62
49
63
50
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Xunlong Orange Pi PC machine is a functional ARM machine
3
The only caller of cpu_watchpoint_address_matches passes
4
based on the Allwinner H3 System-on-Chip. It supports mainline
4
TARGET_PAGE_SIZE, so the bug is not currently visible.
5
Linux, U-Boot, NetBSD and is covered by acceptance tests.
6
5
7
This commit adds a documentation text file with a description
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
of the machine and instructions for the user.
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20200508154359.7494-3-richard.henderson@linaro.org
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com
13
[PMM: moved file into docs/system/arm to match the reorg
14
of the arm target part of the docs; tweaked heading to
15
match other boards]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
11
---
18
MAINTAINERS | 1 +
12
exec.c | 2 +-
19
docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
20
docs/system/target-arm.rst | 2 +
21
3 files changed, 256 insertions(+)
22
create mode 100644 docs/system/arm/orangepi.rst
23
14
24
diff --git a/MAINTAINERS b/MAINTAINERS
15
diff --git a/exec.c b/exec.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
17
--- a/exec.c
27
+++ b/MAINTAINERS
18
+++ b/exec.c
28
@@ -XXX,XX +XXX,XX @@ S: Maintained
19
@@ -XXX,XX +XXX,XX @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
29
F: hw/*/allwinner-h3*
20
int ret = 0;
30
F: include/hw/*/allwinner-h3*
21
31
F: hw/arm/orangepi.c
22
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
32
+F: docs/system/orangepi.rst
23
- if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
33
24
+ if (watchpoint_address_matches(wp, addr, len)) {
34
ARM PrimeCell and CMSDK devices
25
ret |= wp->flags;
35
M: Peter Maydell <peter.maydell@linaro.org>
26
}
36
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
27
}
37
new file mode 100644
38
index XXXXXXX..XXXXXXX
39
--- /dev/null
40
+++ b/docs/system/arm/orangepi.rst
41
@@ -XXX,XX +XXX,XX @@
42
+Orange Pi PC (``orangepi-pc``)
43
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
44
+
45
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
46
+based embedded computer with mainline support in both U-Boot
47
+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
48
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
49
+various other I/O.
50
+
51
+Supported devices
52
+"""""""""""""""""
53
+
54
+The Orange Pi PC machine supports the following devices:
55
+
56
+ * SMP (Quad Core Cortex-A7)
57
+ * Generic Interrupt Controller configuration
58
+ * SRAM mappings
59
+ * SDRAM controller
60
+ * Real Time Clock
61
+ * Timer device (re-used from Allwinner A10)
62
+ * UART
63
+ * SD/MMC storage controller
64
+ * EMAC ethernet
65
+ * USB 2.0 interfaces
66
+ * Clock Control Unit
67
+ * System Control module
68
+ * Security Identifier device
69
+
70
+Limitations
71
+"""""""""""
72
+
73
+Currently, Orange Pi PC does *not* support the following features:
74
+
75
+- Graphical output via HDMI, GPU and/or the Display Engine
76
+- Audio output
77
+- Hardware Watchdog
78
+
79
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
80
+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``
81
+
82
+Boot options
83
+""""""""""""
84
+
85
+The Orange Pi PC machine can start using the standard -kernel functionality
86
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC
87
+machine can also emulate the BootROM which is present on an actual Allwinner H3
88
+based SoC, which loads the bootloader from a SD card, specified via the -sd argument
89
+to qemu-system-arm.
90
+
91
+Machine-specific options
92
+""""""""""""""""""""""""
93
+
94
+The following machine-specific options are supported:
95
+
96
+- allwinner-rtc.base-year=YYYY
97
+
98
+ The Allwinner RTC device is automatically created by the Orange Pi PC machine
99
+ and uses a default base year value which can be overridden using the 'base-year' property.
100
+ The base year is the actual represented year when the RTC year value is zero.
101
+ This option can be used in case the target operating system driver uses a different
102
+ base year value. The minimum value for the base year is 1900.
103
+
104
+- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff
105
+
106
+ The Security Identifier value can be read by the guest.
107
+ For example, U-Boot uses it to determine a unique MAC address.
108
+
109
+The above machine-specific options can be specified in qemu-system-arm
110
+via the '-global' argument, for example:
111
+
112
+.. code-block:: bash
113
+
114
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
115
+ -global allwinner-rtc.base-year=2000
116
+
117
+Running mainline Linux
118
+""""""""""""""""""""""
119
+
120
+Mainline Linux kernels from 4.19 up to latest master are known to work.
121
+To build a Linux mainline kernel that can be booted by the Orange Pi PC machine,
122
+simply configure the kernel using the sunxi_defconfig configuration:
123
+
124
+.. code-block:: bash
125
+
126
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper
127
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig
128
+
129
+To be able to use USB storage, you need to manually enable the corresponding
130
+configuration item. Start the kconfig configuration tool:
131
+
132
+.. code-block:: bash
133
+
134
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig
135
+
136
+Navigate to the following item, enable it and save your configuration:
137
+
138
+ Device Drivers > USB support > USB Mass Storage support
139
+
140
+Build the Linux kernel with:
141
+
142
+.. code-block:: bash
143
+
144
+ $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make
145
+
146
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use:
147
+
148
+.. code-block:: bash
149
+
150
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
151
+ -kernel /path/to/linux/arch/arm/boot/zImage \
152
+ -append 'console=ttyS0,115200' \
153
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
154
+
155
+Orange Pi PC images
156
+"""""""""""""""""""
157
+
158
+Note that the mainline kernel does not have a root filesystem. You may provide it
159
+with an official Orange Pi PC image from the official website:
160
+
161
+ http://www.orangepi.org/downloadresources/
162
+
163
+Another possibility is to run an Armbian image for Orange Pi PC which
164
+can be downloaded from:
165
+
166
+ https://www.armbian.com/orange-pi-pc/
167
+
168
+Alternatively, you can also choose to build you own image with buildroot
169
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more information.
170
+
171
+You can choose to attach the selected image either as an SD card or as USB mass storage.
172
+For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd
173
+argument and provide the proper root= kernel parameter:
174
+
175
+.. code-block:: bash
176
+
177
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
178
+ -kernel /path/to/linux/arch/arm/boot/zImage \
179
+ -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \
180
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
181
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
182
+
183
+To attach the image as an USB mass storage device to the machine,
184
+simply append to the command:
185
+
186
+.. code-block:: bash
187
+
188
+ -drive if=none,id=stick,file=myimage.img \
189
+ -device usb-storage,bus=usb-bus.0,drive=stick
190
+
191
+Instead of providing a custom Linux kernel via the -kernel command you may also
192
+choose to let the Orange Pi PC machine load the bootloader from SD card, just like
193
+a real board would do using the BootROM. Simply pass the selected image via the -sd
194
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
195
+
196
+.. code-block:: bash
197
+
198
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
199
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
200
+
201
+Note that both the official Orange Pi PC images and Armbian images start
202
+a lot of userland programs via systemd. Depending on the host hardware and OS,
203
+they may be slow to emulate, especially due to emulating the 4 cores.
204
+To help reduce the performance slow down due to emulating the 4 cores, you can
205
+give the following kernel parameters via U-Boot (or via -append):
206
+
207
+.. code-block:: bash
208
+
209
+ => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200'
210
+
211
+Running U-Boot
212
+""""""""""""""
213
+
214
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
215
+using similar commands as describe above for Linux. Note that it is recommended
216
+for development/testing to select the following configuration setting in U-Boot:
217
+
218
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
219
+
220
+To start U-Boot using the Orange Pi PC machine, provide the
221
+u-boot binary to the -kernel argument:
222
+
223
+.. code-block:: bash
224
+
225
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
226
+ -kernel /path/to/uboot/u-boot -sd disk.img
227
+
228
+Use the following U-boot commands to load and boot a Linux kernel from SD card:
229
+
230
+.. code-block:: bash
231
+
232
+ => setenv bootargs console=ttyS0,115200
233
+ => ext2load mmc 0 0x42000000 zImage
234
+ => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
235
+ => bootz 0x42000000 - 0x43000000
236
+
237
+Running NetBSD
238
+""""""""""""""
239
+
240
+The NetBSD operating system also includes support for Allwinner H3 based boards,
241
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC
242
+board and provides a fully working system with serial console, networking and storage.
243
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
244
+
245
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz
246
+
247
+The image requires manually installing U-Boot in the image. Build U-Boot with
248
+the orangepi_pc_defconfig configuration as described in the previous section.
249
+Next, unzip the NetBSD image and write the U-Boot binary including SPL using:
250
+
251
+.. code-block:: bash
252
+
253
+ $ gunzip armv7.img.gz
254
+ $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc
255
+
256
+Finally, before starting the machine the SD image must be extended such
257
+that the NetBSD kernel will not conclude the NetBSD partition is larger than
258
+the emulated SD card:
259
+
260
+.. code-block:: bash
261
+
262
+ $ dd if=/dev/zero bs=1M count=64 >> armv7.img
263
+
264
+Start the machine using the following command:
265
+
266
+.. code-block:: bash
267
+
268
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
269
+ -sd armv7.img -global allwinner-rtc.base-year=2000
270
+
271
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
272
+and set the following environment variables before booting:
273
+
274
+.. code-block:: bash
275
+
276
+ => setenv bootargs root=ld0a
277
+ => setenv kernel netbsd-GENERIC.ub
278
+ => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
279
+ => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}'
280
+
281
+Optionally you may save the environment variables to SD card with 'saveenv'.
282
+To continue booting simply give the 'boot' command and NetBSD boots.
283
+
284
+Orange Pi PC acceptance tests
285
+"""""""""""""""""""""""""""""
286
+
287
+The Orange Pi PC machine has several acceptance tests included.
288
+To run the whole set of tests, build QEMU from source and simply
289
+provide the following command:
290
+
291
+.. code-block:: bash
292
+
293
+ $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \
294
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
295
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
296
index XXXXXXX..XXXXXXX 100644
297
--- a/docs/system/target-arm.rst
298
+++ b/docs/system/target-arm.rst
299
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
300
``qemu-system-aarch64 --machine help``.
301
302
.. toctree::
303
+ :maxdepth: 1
304
305
arm/integratorcp
306
arm/versatile
307
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
308
arm/stellaris
309
arm/musicpal
310
arm/sx1
311
+ arm/orangepi
312
313
Arm CPU features
314
================
315
--
28
--
316
2.20.1
29
2.20.1
317
30
318
31
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Mention 'max' value in the gic-version property description.
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
5
Message-id: 20200508154359.7494-4-richard.henderson@linaro.org
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20200311131618.7187-2-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
hw/arm/virt.c | 3 ++-
8
include/exec/exec-all.h | 17 +++++++++++++++++
12
1 file changed, 2 insertions(+), 1 deletion(-)
9
1 file changed, 17 insertions(+)
13
10
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
11
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
13
--- a/include/exec/exec-all.h
17
+++ b/hw/arm/virt.c
14
+++ b/include/exec/exec-all.h
18
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
15
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
19
virt_set_gic_version, NULL);
16
{
20
object_property_set_description(obj, "gic-version",
17
}
21
"Set GIC version. "
18
#endif
22
- "Valid values are 2, 3 and host", NULL);
19
+/**
23
+ "Valid values are 2, 3, host and max",
20
+ * probe_access:
24
+ NULL);
21
+ * @env: CPUArchState
25
22
+ * @addr: guest virtual address to look up
26
vms->highmem_ecam = !vmc->no_highmem_ecam;
23
+ * @size: size of the access
24
+ * @access_type: read, write or execute permission
25
+ * @mmu_idx: MMU index to use for lookup
26
+ * @retaddr: return address for unwinding
27
+ *
28
+ * Look up the guest virtual address @addr. Raise an exception if the
29
+ * page does not satisfy @access_type. Raise an exception if the
30
+ * access (@addr, @size) hits a watchpoint. For writes, mark a clean
31
+ * page as dirty.
32
+ *
33
+ * Finally, return the host address for a page that is backed by RAM,
34
+ * or NULL if the page requires I/O.
35
+ */
36
void *probe_access(CPUArchState *env, target_ulong addr, int size,
37
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
27
38
28
--
39
--
29
2.20.1
40
2.20.1
30
41
31
42
diff view generated by jsdifflib
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
SOC object returned by object_new() is leaked in current code.
3
We have validated that addr+size does not cross a page boundary.
4
Set SOC parent explicitly to board and then unref to SOC object
4
Therefore we need to validate exactly one page. We can achieve
5
to make sure that refererence returned by object_new() is taken
5
that passing any value 1 <= x <= size to page_check_range.
6
care of.
7
6
8
The SOC object will be kept alive by its parent (machine) and
7
Passing 1 will simplify the next patch.
9
will be automatically freed when MachineState is destroyed.
10
8
11
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reported-by: Andrew Jones <drjones@redhat.com>
10
Message-id: 20200508154359.7494-5-richard.henderson@linaro.org
13
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Message-id: 20200303091254.22373-1-imammedo@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
13
---
18
hw/arm/cubieboard.c | 3 +++
14
accel/tcg/user-exec.c | 2 +-
19
1 file changed, 3 insertions(+)
15
1 file changed, 1 insertion(+), 1 deletion(-)
20
16
21
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
17
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/cubieboard.c
19
--- a/accel/tcg/user-exec.c
24
+++ b/hw/arm/cubieboard.c
20
+++ b/accel/tcg/user-exec.c
25
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
21
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
22
g_assert_not_reached();
26
}
23
}
27
24
28
a10 = AW_A10(object_new(TYPE_AW_A10));
25
- if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) {
29
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),
26
+ if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
30
+ &error_abort);
27
CPUState *cpu = env_cpu(env);
31
+ object_unref(OBJECT(a10));
28
CPUClass *cc = CPU_GET_CLASS(cpu);
32
29
cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
33
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
34
if (err != NULL) {
35
--
30
--
36
2.20.1
31
2.20.1
37
32
38
33
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner System on Chip families sun4i and above contain
3
This new interface will allow targets to probe for a page
4
an integrated storage controller for Secure Digital (SD) and
4
and then handle watchpoints themselves. This will be most
5
Multi Media Card (MMC) interfaces. This commit adds support
5
useful for vector predicated memory operations, where one
6
for the Allwinner SD/MMC storage controller with the following
6
page lookup can be used for many operations, and one test
7
emulated features:
7
can avoid many watchpoint checks.
8
8
9
* DMA transfers
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
* Direct FIFO I/O
10
Message-id: 20200508154359.7494-6-richard.henderson@linaro.org
11
* Short/Long format command responses
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
* Auto-Stop command (CMD12)
13
* Insert & remove card detection
14
15
The following boards are extended with the SD host controller:
16
17
* Cubieboard (hw/arm/cubieboard.c)
18
* Orange Pi PC (hw/arm/orangepi.c)
19
20
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
21
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
22
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
13
---
26
hw/sd/Makefile.objs | 1 +
14
include/exec/cpu-all.h | 13 ++-
27
include/hw/arm/allwinner-a10.h | 2 +
15
include/exec/exec-all.h | 22 +++++
28
include/hw/arm/allwinner-h3.h | 3 +
16
accel/tcg/cputlb.c | 177 ++++++++++++++++++++--------------------
29
include/hw/sd/allwinner-sdhost.h | 135 +++++
17
accel/tcg/user-exec.c | 43 ++++++++--
30
hw/arm/allwinner-a10.c | 11 +
18
4 files changed, 158 insertions(+), 97 deletions(-)
31
hw/arm/allwinner-h3.c | 15 +-
19
32
hw/arm/cubieboard.c | 15 +
20
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
33
hw/arm/orangepi.c | 16 +
34
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
35
hw/arm/Kconfig | 1 +
36
hw/sd/trace-events | 7 +
37
11 files changed, 1059 insertions(+), 1 deletion(-)
38
create mode 100644 include/hw/sd/allwinner-sdhost.h
39
create mode 100644 hw/sd/allwinner-sdhost.c
40
41
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
42
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/sd/Makefile.objs
22
--- a/include/exec/cpu-all.h
44
+++ b/hw/sd/Makefile.objs
23
+++ b/include/exec/cpu-all.h
45
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o
24
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env);
46
common-obj-$(CONFIG_SDHCI) += sdhci.o
25
| CPU_INTERRUPT_TGT_EXT_3 \
47
common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o
26
| CPU_INTERRUPT_TGT_EXT_4)
48
27
49
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o
28
-#if !defined(CONFIG_USER_ONLY)
50
common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
29
+#ifdef CONFIG_USER_ONLY
51
common-obj-$(CONFIG_OMAP) += omap_mmc.o
30
+
52
common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
31
+/*
53
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
32
+ * Allow some level of source compatibility with softmmu. We do not
33
+ * support any of the more exotic features, so only invalid pages may
34
+ * be signaled by probe_access_flags().
35
+ */
36
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
37
+#define TLB_MMIO 0
38
+#define TLB_WATCHPOINT 0
39
+
40
+#else
41
42
/*
43
* Flags stored in the low bits of the TLB virtual address.
44
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
54
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
55
--- a/include/hw/arm/allwinner-a10.h
46
--- a/include/exec/exec-all.h
56
+++ b/include/hw/arm/allwinner-a10.h
47
+++ b/include/exec/exec-all.h
57
@@ -XXX,XX +XXX,XX @@
48
@@ -XXX,XX +XXX,XX @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
58
#include "hw/timer/allwinner-a10-pit.h"
49
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
59
#include "hw/intc/allwinner-a10-pic.h"
50
}
60
#include "hw/net/allwinner_emac.h"
51
61
+#include "hw/sd/allwinner-sdhost.h"
52
+/**
62
#include "hw/ide/ahci.h"
53
+ * probe_access_flags:
63
#include "hw/usb/hcd-ohci.h"
54
+ * @env: CPUArchState
64
#include "hw/usb/hcd-ehci.h"
55
+ * @addr: guest virtual address to look up
65
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
56
+ * @access_type: read, write or execute permission
66
AwA10PICState intc;
57
+ * @mmu_idx: MMU index to use for lookup
67
AwEmacState emac;
58
+ * @nonfault: suppress the fault
68
AllwinnerAHCIState sata;
59
+ * @phost: return value for host address
69
+ AwSdHostState mmc0;
60
+ * @retaddr: return address for unwinding
70
MemoryRegion sram_a;
61
+ *
71
EHCISysBusState ehci[AW_A10_NUM_USB];
62
+ * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
72
OHCISysBusState ohci[AW_A10_NUM_USB];
63
+ * the page, and storing the host address for RAM in @phost.
73
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
64
+ *
65
+ * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
66
+ * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
67
+ * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
68
+ * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
69
+ */
70
+int probe_access_flags(CPUArchState *env, target_ulong addr,
71
+ MMUAccessType access_type, int mmu_idx,
72
+ bool nonfault, void **phost, uintptr_t retaddr);
73
+
74
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
75
76
/* Estimated block size for TB allocation. */
77
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
74
index XXXXXXX..XXXXXXX 100644
78
index XXXXXXX..XXXXXXX 100644
75
--- a/include/hw/arm/allwinner-h3.h
79
--- a/accel/tcg/cputlb.c
76
+++ b/include/hw/arm/allwinner-h3.h
80
+++ b/accel/tcg/cputlb.c
77
@@ -XXX,XX +XXX,XX @@
81
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
78
#include "hw/misc/allwinner-cpucfg.h"
82
}
79
#include "hw/misc/allwinner-h3-sysctrl.h"
83
}
80
#include "hw/misc/allwinner-sid.h"
84
81
+#include "hw/sd/allwinner-sdhost.h"
85
-/*
82
#include "target/arm/cpu.h"
86
- * Probe for whether the specified guest access is permitted. If it is not
83
87
- * permitted then an exception will be taken in the same way as if this
84
/**
88
- * were a real access (and we will not return).
85
@@ -XXX,XX +XXX,XX @@ enum {
89
- * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
86
AW_H3_SRAM_A2,
90
- * returns the address of the host page similar to tlb_vaddr_to_host().
87
AW_H3_SRAM_C,
91
- */
88
AW_H3_SYSCTRL,
92
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
89
+ AW_H3_MMC0,
93
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
90
AW_H3_SID,
94
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
91
AW_H3_EHCI0,
95
+ int fault_size, MMUAccessType access_type,
92
AW_H3_OHCI0,
96
+ int mmu_idx, bool nonfault,
93
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
97
+ void **phost, uintptr_t retaddr)
94
AwCpuCfgState cpucfg;
98
{
95
AwH3SysCtrlState sysctrl;
99
uintptr_t index = tlb_index(env, mmu_idx, addr);
96
AwSidState sid;
100
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
97
+ AwSdHostState mmc0;
101
- target_ulong tlb_addr;
98
GICState gic;
102
- size_t elt_ofs;
99
MemoryRegion sram_a1;
103
- int wp_access;
100
MemoryRegion sram_a2;
104
-
101
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
105
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
102
new file mode 100644
106
-
103
index XXXXXXX..XXXXXXX
107
- switch (access_type) {
104
--- /dev/null
108
- case MMU_DATA_LOAD:
105
+++ b/include/hw/sd/allwinner-sdhost.h
109
- elt_ofs = offsetof(CPUTLBEntry, addr_read);
106
@@ -XXX,XX +XXX,XX @@
110
- wp_access = BP_MEM_READ;
107
+/*
111
- break;
108
+ * Allwinner (sun4i and above) SD Host Controller emulation
112
- case MMU_DATA_STORE:
109
+ *
113
- elt_ofs = offsetof(CPUTLBEntry, addr_write);
110
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
114
- wp_access = BP_MEM_WRITE;
111
+ *
115
- break;
112
+ * This program is free software: you can redistribute it and/or modify
116
- case MMU_INST_FETCH:
113
+ * it under the terms of the GNU General Public License as published by
117
- elt_ofs = offsetof(CPUTLBEntry, addr_code);
114
+ * the Free Software Foundation, either version 2 of the License, or
118
- wp_access = BP_MEM_READ;
115
+ * (at your option) any later version.
119
- break;
116
+ *
120
- default:
117
+ * This program is distributed in the hope that it will be useful,
121
- g_assert_not_reached();
118
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
122
- }
119
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
123
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
120
+ * GNU General Public License for more details.
124
-
121
+ *
125
- if (unlikely(!tlb_hit(tlb_addr, addr))) {
122
+ * You should have received a copy of the GNU General Public License
126
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs,
123
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
127
- addr & TARGET_PAGE_MASK)) {
124
+ */
128
- tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr);
125
+
129
- /* TLB resize via tlb_fill may have moved the entry. */
126
+#ifndef HW_SD_ALLWINNER_SDHOST_H
130
- index = tlb_index(env, mmu_idx, addr);
127
+#define HW_SD_ALLWINNER_SDHOST_H
131
- entry = tlb_entry(env, mmu_idx, addr);
128
+
132
- }
129
+#include "qom/object.h"
133
- tlb_addr = tlb_read_ofs(entry, elt_ofs);
130
+#include "hw/sysbus.h"
134
- }
131
+#include "hw/sd/sd.h"
135
-
132
+
136
- if (!size) {
133
+/**
137
- return NULL;
134
+ * Object model types
138
- }
135
+ * @{
139
-
136
+ */
140
- if (unlikely(tlb_addr & TLB_FLAGS_MASK)) {
137
+
141
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
138
+/** Generic Allwinner SD Host Controller (abstract) */
142
-
139
+#define TYPE_AW_SDHOST "allwinner-sdhost"
143
- /* Reject I/O access, or other required slow-path. */
140
+
144
- if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) {
141
+/** Allwinner sun4i family (A10, A12) */
145
- return NULL;
142
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
146
- }
143
+
147
-
144
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
148
- /* Handle watchpoints. */
145
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
149
- if (tlb_addr & TLB_WATCHPOINT) {
146
+
150
- cpu_check_watchpoint(env_cpu(env), addr, size,
147
+/** @} */
151
- iotlbentry->attrs, wp_access, retaddr);
148
+
152
- }
149
+/**
153
-
150
+ * Object model macros
154
- /* Handle clean RAM pages. */
151
+ * @{
155
- if (tlb_addr & TLB_NOTDIRTY) {
152
+ */
156
- notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
153
+
157
- }
154
+#define AW_SDHOST(obj) \
158
- }
155
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
159
-
156
+#define AW_SDHOST_CLASS(klass) \
160
- return (void *)((uintptr_t)addr + entry->addend);
157
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
161
-}
158
+#define AW_SDHOST_GET_CLASS(obj) \
162
-
159
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
163
-void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
160
+
164
- MMUAccessType access_type, int mmu_idx)
161
+/** @} */
165
-{
162
+
166
- CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
163
+/**
167
- target_ulong tlb_addr, page;
164
+ * Allwinner SD Host Controller object instance state.
168
+ target_ulong tlb_addr, page_addr;
165
+ */
169
size_t elt_ofs;
166
+typedef struct AwSdHostState {
170
+ int flags;
167
+ /*< private >*/
171
168
+ SysBusDevice busdev;
172
switch (access_type) {
169
+ /*< public >*/
173
case MMU_DATA_LOAD:
170
+
174
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
171
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
175
default:
172
+ SDBus sdbus;
176
g_assert_not_reached();
173
+
177
}
174
+ /** Maps I/O registers in physical memory */
178
-
175
+ MemoryRegion iomem;
179
- page = addr & TARGET_PAGE_MASK;
176
+
180
tlb_addr = tlb_read_ofs(entry, elt_ofs);
177
+ /** Interrupt output signal to notify CPU */
181
178
+ qemu_irq irq;
182
- if (!tlb_hit_page(tlb_addr, page)) {
179
+
183
- uintptr_t index = tlb_index(env, mmu_idx, addr);
180
+ /** Number of bytes left in current DMA transfer */
184
-
181
+ uint32_t transfer_cnt;
185
- if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) {
182
+
186
+ page_addr = addr & TARGET_PAGE_MASK;
183
+ /**
187
+ if (!tlb_hit_page(tlb_addr, page_addr)) {
184
+ * @name Hardware Registers
188
+ if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
185
+ * @{
189
CPUState *cs = env_cpu(env);
186
+ */
190
CPUClass *cc = CPU_GET_CLASS(cs);
187
+
191
188
+ uint32_t global_ctl; /**< Global Control */
192
- if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) {
189
+ uint32_t clock_ctl; /**< Clock Control */
193
+ if (!cc->tlb_fill(cs, addr, fault_size, access_type,
190
+ uint32_t timeout; /**< Timeout */
194
+ mmu_idx, nonfault, retaddr)) {
191
+ uint32_t bus_width; /**< Bus Width */
195
/* Non-faulting page table read failed. */
192
+ uint32_t block_size; /**< Block Size */
196
- return NULL;
193
+ uint32_t byte_count; /**< Byte Count */
197
+ *phost = NULL;
194
+
198
+ return TLB_INVALID_MASK;
195
+ uint32_t command; /**< Command */
199
}
196
+ uint32_t command_arg; /**< Command Argument */
200
197
+ uint32_t response[4]; /**< Command Response */
201
/* TLB resize via tlb_fill may have moved the entry. */
198
+
202
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
199
+ uint32_t irq_mask; /**< Interrupt Mask */
200
+ uint32_t irq_status; /**< Raw Interrupt Status */
201
+ uint32_t status; /**< Status */
202
+
203
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
204
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
205
+ uint32_t debug_enable; /**< Debug Enable */
206
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
207
+ uint32_t newtiming_set; /**< SD New Timing Set */
208
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
209
+ uint32_t hardware_rst; /**< Hardware Reset */
210
+ uint32_t dmac; /**< Internal DMA Controller Control */
211
+ uint32_t desc_base; /**< Descriptor List Base Address */
212
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
213
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
214
+ uint32_t card_threshold; /**< Card Threshold Control */
215
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
216
+ uint32_t response_crc; /**< Response CRC */
217
+ uint32_t data_crc[8]; /**< Data CRC */
218
+ uint32_t status_crc; /**< Status CRC */
219
+
220
+ /** @} */
221
+
222
+} AwSdHostState;
223
+
224
+/**
225
+ * Allwinner SD Host Controller class-level struct.
226
+ *
227
+ * This struct is filled by each sunxi device specific code
228
+ * such that the generic code can use this struct to support
229
+ * all devices.
230
+ */
231
+typedef struct AwSdHostClass {
232
+ /*< private >*/
233
+ SysBusDeviceClass parent_class;
234
+ /*< public >*/
235
+
236
+ /** Maximum buffer size in bytes per DMA descriptor */
237
+ size_t max_desc_size;
238
+
239
+} AwSdHostClass;
240
+
241
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
242
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/arm/allwinner-a10.c
245
+++ b/hw/arm/allwinner-a10.c
246
@@ -XXX,XX +XXX,XX @@
247
#include "hw/boards.h"
248
#include "hw/usb/hcd-ohci.h"
249
250
+#define AW_A10_MMC0_BASE 0x01c0f000
251
#define AW_A10_PIC_REG_BASE 0x01c20400
252
#define AW_A10_PIT_REG_BASE 0x01c20c00
253
#define AW_A10_UART0_REG_BASE 0x01c28000
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
255
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
256
}
203
}
257
}
204
tlb_addr = tlb_read_ofs(entry, elt_ofs);
258
+
205
}
259
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
206
+ flags = tlb_addr & TLB_FLAGS_MASK;
260
+ TYPE_AW_SDHOST_SUN4I);
207
261
}
208
- if (tlb_addr & ~TARGET_PAGE_MASK) {
262
209
- /* IO access */
263
static void aw_a10_realize(DeviceState *dev, Error **errp)
210
+ /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
264
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
211
+ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
265
qdev_get_gpio_in(dev, 64 + i));
212
+ *phost = NULL;
266
}
213
+ return TLB_MMIO;
267
}
268
+
269
+ /* SD/MMC */
270
+ qdev_init_nofail(DEVICE(&s->mmc0));
271
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
272
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
273
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
274
+ "sd-bus", &error_abort);
275
}
276
277
static void aw_a10_class_init(ObjectClass *oc, void *data)
278
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
279
index XXXXXXX..XXXXXXX 100644
280
--- a/hw/arm/allwinner-h3.c
281
+++ b/hw/arm/allwinner-h3.c
282
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
283
[AW_H3_SRAM_A2] = 0x00044000,
284
[AW_H3_SRAM_C] = 0x00010000,
285
[AW_H3_SYSCTRL] = 0x01c00000,
286
+ [AW_H3_MMC0] = 0x01c0f000,
287
[AW_H3_SID] = 0x01c14000,
288
[AW_H3_EHCI0] = 0x01c1a000,
289
[AW_H3_OHCI0] = 0x01c1a400,
290
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
291
{ "lcd0", 0x01c0c000, 4 * KiB },
292
{ "lcd1", 0x01c0d000, 4 * KiB },
293
{ "ve", 0x01c0e000, 4 * KiB },
294
- { "mmc0", 0x01c0f000, 4 * KiB },
295
{ "mmc1", 0x01c10000, 4 * KiB },
296
{ "mmc2", 0x01c11000, 4 * KiB },
297
{ "crypto", 0x01c15000, 4 * KiB },
298
@@ -XXX,XX +XXX,XX @@ enum {
299
AW_H3_GIC_SPI_UART3 = 3,
300
AW_H3_GIC_SPI_TIMER0 = 18,
301
AW_H3_GIC_SPI_TIMER1 = 19,
302
+ AW_H3_GIC_SPI_MMC0 = 60,
303
AW_H3_GIC_SPI_EHCI0 = 72,
304
AW_H3_GIC_SPI_OHCI0 = 73,
305
AW_H3_GIC_SPI_EHCI1 = 74,
306
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
307
TYPE_AW_SID);
308
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
309
"identifier", &error_abort);
310
+
311
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
312
+ TYPE_AW_SDHOST_SUN5I);
313
}
314
315
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
316
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
317
qdev_init_nofail(DEVICE(&s->sid));
318
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
319
320
+ /* SD/MMC */
321
+ qdev_init_nofail(DEVICE(&s->mmc0));
322
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
323
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
324
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
325
+
326
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
327
+ "sd-bus", &error_abort);
328
+
329
/* Universal Serial Bus */
330
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
331
qdev_get_gpio_in(DEVICE(&s->gic),
332
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/cubieboard.c
335
+++ b/hw/arm/cubieboard.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "sysemu/sysemu.h"
338
#include "hw/sysbus.h"
339
#include "hw/boards.h"
340
+#include "hw/qdev-properties.h"
341
#include "hw/arm/allwinner-a10.h"
342
343
static struct arm_boot_info cubieboard_binfo = {
344
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
345
{
346
AwA10State *a10;
347
Error *err = NULL;
348
+ DriveInfo *di;
349
+ BlockBackend *blk;
350
+ BusState *bus;
351
+ DeviceState *carddev;
352
353
/* BIOS is not supported by this board */
354
if (bios_name) {
355
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
356
exit(1);
357
}
358
359
+ /* Retrieve SD bus */
360
+ di = drive_get_next(IF_SD);
361
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
362
+ bus = qdev_get_child_bus(DEVICE(a10), "sd-bus");
363
+
364
+ /* Plug in SD card */
365
+ carddev = qdev_create(bus, TYPE_SD_CARD);
366
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
367
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
368
+
369
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
370
machine->ram);
371
372
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
373
index XXXXXXX..XXXXXXX 100644
374
--- a/hw/arm/orangepi.c
375
+++ b/hw/arm/orangepi.c
376
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = {
377
static void orangepi_init(MachineState *machine)
378
{
379
AwH3State *h3;
380
+ DriveInfo *di;
381
+ BlockBackend *blk;
382
+ BusState *bus;
383
+ DeviceState *carddev;
384
385
/* BIOS is not supported by this board */
386
if (bios_name) {
387
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
388
/* Mark H3 object realized */
389
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
390
391
+ /* Retrieve SD bus */
392
+ di = drive_get_next(IF_SD);
393
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
394
+ bus = qdev_get_child_bus(DEVICE(h3), "sd-bus");
395
+
396
+ /* Plug in SD card */
397
+ carddev = qdev_create(bus, TYPE_SD_CARD);
398
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
399
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
400
+
401
/* SDRAM */
402
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
403
machine->ram);
404
@@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc)
405
{
406
mc->desc = "Orange Pi PC";
407
mc->init = orangepi_init;
408
+ mc->block_default_type = IF_SD;
409
+ mc->units_per_default_bus = 1;
410
mc->min_cpus = AW_H3_NUM_CPUS;
411
mc->max_cpus = AW_H3_NUM_CPUS;
412
mc->default_cpus = AW_H3_NUM_CPUS;
413
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
414
new file mode 100644
415
index XXXXXXX..XXXXXXX
416
--- /dev/null
417
+++ b/hw/sd/allwinner-sdhost.c
418
@@ -XXX,XX +XXX,XX @@
419
+/*
420
+ * Allwinner (sun4i and above) SD Host Controller emulation
421
+ *
422
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
423
+ *
424
+ * This program is free software: you can redistribute it and/or modify
425
+ * it under the terms of the GNU General Public License as published by
426
+ * the Free Software Foundation, either version 2 of the License, or
427
+ * (at your option) any later version.
428
+ *
429
+ * This program is distributed in the hope that it will be useful,
430
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
431
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
432
+ * GNU General Public License for more details.
433
+ *
434
+ * You should have received a copy of the GNU General Public License
435
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
436
+ */
437
+
438
+#include "qemu/osdep.h"
439
+#include "qemu/log.h"
440
+#include "qemu/module.h"
441
+#include "qemu/units.h"
442
+#include "sysemu/blockdev.h"
443
+#include "hw/irq.h"
444
+#include "hw/sd/allwinner-sdhost.h"
445
+#include "migration/vmstate.h"
446
+#include "trace.h"
447
+
448
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
449
+#define AW_SDHOST_BUS(obj) \
450
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
451
+
452
+/* SD Host register offsets */
453
+enum {
454
+ REG_SD_GCTL = 0x00, /* Global Control */
455
+ REG_SD_CKCR = 0x04, /* Clock Control */
456
+ REG_SD_TMOR = 0x08, /* Timeout */
457
+ REG_SD_BWDR = 0x0C, /* Bus Width */
458
+ REG_SD_BKSR = 0x10, /* Block Size */
459
+ REG_SD_BYCR = 0x14, /* Byte Count */
460
+ REG_SD_CMDR = 0x18, /* Command */
461
+ REG_SD_CAGR = 0x1C, /* Command Argument */
462
+ REG_SD_RESP0 = 0x20, /* Response Zero */
463
+ REG_SD_RESP1 = 0x24, /* Response One */
464
+ REG_SD_RESP2 = 0x28, /* Response Two */
465
+ REG_SD_RESP3 = 0x2C, /* Response Three */
466
+ REG_SD_IMKR = 0x30, /* Interrupt Mask */
467
+ REG_SD_MISR = 0x34, /* Masked Interrupt Status */
468
+ REG_SD_RISR = 0x38, /* Raw Interrupt Status */
469
+ REG_SD_STAR = 0x3C, /* Status */
470
+ REG_SD_FWLR = 0x40, /* FIFO Water Level */
471
+ REG_SD_FUNS = 0x44, /* FIFO Function Select */
472
+ REG_SD_DBGC = 0x50, /* Debug Enable */
473
+ REG_SD_A12A = 0x58, /* Auto command 12 argument */
474
+ REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
475
+ REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
476
+ REG_SD_HWRST = 0x78, /* Hardware Reset Register */
477
+ REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
478
+ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
479
+ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
480
+ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
481
+ REG_SD_THLDC = 0x100, /* Card Threshold Control */
482
+ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
483
+ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
484
+ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
485
+ REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
486
+ REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
487
+ REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
488
+ REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
489
+ REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
490
+ REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
491
+ REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
492
+ REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
493
+ REG_SD_FIFO = 0x200, /* Read/Write FIFO */
494
+};
495
+
496
+/* SD Host register flags */
497
+enum {
498
+ SD_GCTL_FIFO_AC_MOD = (1 << 31),
499
+ SD_GCTL_DDR_MOD_SEL = (1 << 10),
500
+ SD_GCTL_CD_DBC_ENB = (1 << 8),
501
+ SD_GCTL_DMA_ENB = (1 << 5),
502
+ SD_GCTL_INT_ENB = (1 << 4),
503
+ SD_GCTL_DMA_RST = (1 << 2),
504
+ SD_GCTL_FIFO_RST = (1 << 1),
505
+ SD_GCTL_SOFT_RST = (1 << 0),
506
+};
507
+
508
+enum {
509
+ SD_CMDR_LOAD = (1 << 31),
510
+ SD_CMDR_CLKCHANGE = (1 << 21),
511
+ SD_CMDR_WRITE = (1 << 10),
512
+ SD_CMDR_AUTOSTOP = (1 << 12),
513
+ SD_CMDR_DATA = (1 << 9),
514
+ SD_CMDR_RESPONSE_LONG = (1 << 7),
515
+ SD_CMDR_RESPONSE = (1 << 6),
516
+ SD_CMDR_CMDID_MASK = (0x3f),
517
+};
518
+
519
+enum {
520
+ SD_RISR_CARD_REMOVE = (1 << 31),
521
+ SD_RISR_CARD_INSERT = (1 << 30),
522
+ SD_RISR_SDIO_INTR = (1 << 16),
523
+ SD_RISR_AUTOCMD_DONE = (1 << 14),
524
+ SD_RISR_DATA_COMPLETE = (1 << 3),
525
+ SD_RISR_CMD_COMPLETE = (1 << 2),
526
+ SD_RISR_NO_RESPONSE = (1 << 1),
527
+};
528
+
529
+enum {
530
+ SD_STAR_CARD_PRESENT = (1 << 8),
531
+};
532
+
533
+enum {
534
+ SD_IDST_INT_SUMMARY = (1 << 8),
535
+ SD_IDST_RECEIVE_IRQ = (1 << 1),
536
+ SD_IDST_TRANSMIT_IRQ = (1 << 0),
537
+ SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
538
+ SD_IDST_WR_MASK = (0x3ff),
539
+};
540
+
541
+/* SD Host register reset values */
542
+enum {
543
+ REG_SD_GCTL_RST = 0x00000300,
544
+ REG_SD_CKCR_RST = 0x0,
545
+ REG_SD_TMOR_RST = 0xFFFFFF40,
546
+ REG_SD_BWDR_RST = 0x0,
547
+ REG_SD_BKSR_RST = 0x00000200,
548
+ REG_SD_BYCR_RST = 0x00000200,
549
+ REG_SD_CMDR_RST = 0x0,
550
+ REG_SD_CAGR_RST = 0x0,
551
+ REG_SD_RESP_RST = 0x0,
552
+ REG_SD_IMKR_RST = 0x0,
553
+ REG_SD_MISR_RST = 0x0,
554
+ REG_SD_RISR_RST = 0x0,
555
+ REG_SD_STAR_RST = 0x00000100,
556
+ REG_SD_FWLR_RST = 0x000F0000,
557
+ REG_SD_FUNS_RST = 0x0,
558
+ REG_SD_DBGC_RST = 0x0,
559
+ REG_SD_A12A_RST = 0x0000FFFF,
560
+ REG_SD_NTSR_RST = 0x00000001,
561
+ REG_SD_SDBG_RST = 0x0,
562
+ REG_SD_HWRST_RST = 0x00000001,
563
+ REG_SD_DMAC_RST = 0x0,
564
+ REG_SD_DLBA_RST = 0x0,
565
+ REG_SD_IDST_RST = 0x0,
566
+ REG_SD_IDIE_RST = 0x0,
567
+ REG_SD_THLDC_RST = 0x0,
568
+ REG_SD_DSBD_RST = 0x0,
569
+ REG_SD_RES_CRC_RST = 0x0,
570
+ REG_SD_DATA_CRC_RST = 0x0,
571
+ REG_SD_CRC_STA_RST = 0x0,
572
+ REG_SD_FIFO_RST = 0x0,
573
+};
574
+
575
+/* Data transfer descriptor for DMA */
576
+typedef struct TransferDescriptor {
577
+ uint32_t status; /* Status flags */
578
+ uint32_t size; /* Data buffer size */
579
+ uint32_t addr; /* Data buffer address */
580
+ uint32_t next; /* Physical address of next descriptor */
581
+} TransferDescriptor;
582
+
583
+/* Data transfer descriptor flags */
584
+enum {
585
+ DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
586
+ DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
587
+ DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
588
+ DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
589
+ DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
590
+ DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
591
+ DESC_SIZE_MASK = (0xfffffffc)
592
+};
593
+
594
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
595
+{
596
+ uint32_t irq;
597
+
598
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
599
+ irq = s->irq_status & s->irq_mask;
600
+ } else {
601
+ irq = 0;
602
+ }
214
+ }
603
+
215
+
604
+ trace_allwinner_sdhost_update_irq(irq);
216
+ /* Everything else is RAM. */
605
+ qemu_set_irq(s->irq, irq);
217
+ *phost = (void *)((uintptr_t)addr + entry->addend);
606
+}
218
+ return flags;
607
+
219
+}
608
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
220
+
609
+ uint32_t bytes)
221
+int probe_access_flags(CPUArchState *env, target_ulong addr,
610
+{
222
+ MMUAccessType access_type, int mmu_idx,
611
+ if (s->transfer_cnt > bytes) {
223
+ bool nonfault, void **phost, uintptr_t retaddr)
612
+ s->transfer_cnt -= bytes;
224
+{
613
+ } else {
225
+ int flags;
614
+ s->transfer_cnt = 0;
226
+
227
+ flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
228
+ nonfault, phost, retaddr);
229
+
230
+ /* Handle clean RAM pages. */
231
+ if (unlikely(flags & TLB_NOTDIRTY)) {
232
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
233
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
234
+
235
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
236
+ flags &= ~TLB_NOTDIRTY;
615
+ }
237
+ }
616
+
238
+
617
+ if (!s->transfer_cnt) {
239
+ return flags;
618
+ s->irq_status |= SD_RISR_DATA_COMPLETE;
240
+}
619
+ }
241
+
620
+}
242
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
621
+
243
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
622
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
244
+{
623
+{
245
+ void *host;
624
+ AwSdHostState *s = AW_SDHOST(dev);
246
+ int flags;
625
+
247
+
626
+ trace_allwinner_sdhost_set_inserted(inserted);
248
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
627
+
249
+
628
+ if (inserted) {
250
+ flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
629
+ s->irq_status |= SD_RISR_CARD_INSERT;
251
+ false, &host, retaddr);
630
+ s->irq_status &= ~SD_RISR_CARD_REMOVE;
252
+
631
+ s->status |= SD_STAR_CARD_PRESENT;
253
+ /* Per the interface, size == 0 merely faults the access. */
632
+ } else {
254
+ if (size == 0) {
633
+ s->irq_status &= ~SD_RISR_CARD_INSERT;
255
return NULL;
634
+ s->irq_status |= SD_RISR_CARD_REMOVE;
256
}
635
+ s->status &= ~SD_STAR_CARD_PRESENT;
257
636
+ }
258
- return (void *)((uintptr_t)addr + entry->addend);
637
+
259
+ if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
638
+ allwinner_sdhost_update_irq(s);
260
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
639
+}
261
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
640
+
262
+
641
+static void allwinner_sdhost_send_command(AwSdHostState *s)
263
+ /* Handle watchpoints. */
642
+{
264
+ if (flags & TLB_WATCHPOINT) {
643
+ SDRequest request;
265
+ int wp_access = (access_type == MMU_DATA_STORE
644
+ uint8_t resp[16];
266
+ ? BP_MEM_WRITE : BP_MEM_READ);
645
+ int rlen;
267
+ cpu_check_watchpoint(env_cpu(env), addr, size,
646
+
268
+ iotlbentry->attrs, wp_access, retaddr);
647
+ /* Auto clear load flag */
648
+ s->command &= ~SD_CMDR_LOAD;
649
+
650
+ /* Clock change does not actually interact with the SD bus */
651
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
652
+
653
+ /* Prepare request */
654
+ request.cmd = s->command & SD_CMDR_CMDID_MASK;
655
+ request.arg = s->command_arg;
656
+
657
+ /* Send request to SD bus */
658
+ rlen = sdbus_do_command(&s->sdbus, &request, resp);
659
+ if (rlen < 0) {
660
+ goto error;
661
+ }
269
+ }
662
+
270
+
663
+ /* If the command has a response, store it in the response registers */
271
+ /* Handle clean RAM pages. */
664
+ if ((s->command & SD_CMDR_RESPONSE)) {
272
+ if (flags & TLB_NOTDIRTY) {
665
+ if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
273
+ notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
666
+ s->response[0] = ldl_be_p(&resp[0]);
667
+ s->response[1] = s->response[2] = s->response[3] = 0;
668
+
669
+ } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
670
+ s->response[0] = ldl_be_p(&resp[12]);
671
+ s->response[1] = ldl_be_p(&resp[8]);
672
+ s->response[2] = ldl_be_p(&resp[4]);
673
+ s->response[3] = ldl_be_p(&resp[0]);
674
+ } else {
675
+ goto error;
676
+ }
677
+ }
274
+ }
678
+ }
275
+ }
679
+
276
+
680
+ /* Set interrupt status bits */
277
+ return host;
681
+ s->irq_status |= SD_RISR_CMD_COMPLETE;
278
}
682
+ return;
279
683
+
280
+void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
684
+error:
281
+ MMUAccessType access_type, int mmu_idx)
685
+ s->irq_status |= SD_RISR_NO_RESPONSE;
282
+{
686
+}
283
+ void *host;
687
+
284
+ int flags;
688
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
285
+
689
+{
286
+ flags = probe_access_internal(env, addr, 0, access_type,
690
+ /*
287
+ mmu_idx, true, &host, 0);
691
+ * The stop command (CMD12) ensures the SD bus
288
+
692
+ * returns to the transfer state.
289
+ /* No combination of flags are expected by the caller. */
693
+ */
290
+ return flags ? NULL : host;
694
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
291
+}
695
+ /* First save current command registers */
292
696
+ uint32_t saved_cmd = s->command;
293
#ifdef CONFIG_PLUGIN
697
+ uint32_t saved_arg = s->command_arg;
294
/*
698
+
295
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
699
+ /* Prepare stop command (CMD12) */
296
index XXXXXXX..XXXXXXX 100644
700
+ s->command &= ~SD_CMDR_CMDID_MASK;
297
--- a/accel/tcg/user-exec.c
701
+ s->command |= 12; /* CMD12 */
298
+++ b/accel/tcg/user-exec.c
702
+ s->command_arg = 0;
299
@@ -XXX,XX +XXX,XX @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
703
+
300
g_assert_not_reached();
704
+ /* Put the command on SD bus */
301
}
705
+ allwinner_sdhost_send_command(s);
302
706
+
303
-void *probe_access(CPUArchState *env, target_ulong addr, int size,
707
+ /* Restore command values */
304
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
708
+ s->command = saved_cmd;
305
+static int probe_access_internal(CPUArchState *env, target_ulong addr,
709
+ s->command_arg = saved_arg;
306
+ int fault_size, MMUAccessType access_type,
710
+
307
+ bool nonfault, uintptr_t ra)
711
+ /* Set IRQ status bit for automatic stop done */
308
{
712
+ s->irq_status |= SD_RISR_AUTOCMD_DONE;
309
int flags;
713
+ }
310
714
+}
311
- g_assert(-(addr | TARGET_PAGE_MASK) >= size);
715
+
312
-
716
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
313
switch (access_type) {
717
+ hwaddr desc_addr,
314
case MMU_DATA_STORE:
718
+ TransferDescriptor *desc,
315
flags = PAGE_WRITE;
719
+ bool is_write, uint32_t max_bytes)
316
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
720
+{
317
}
721
+ AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
318
722
+ uint32_t num_done = 0;
319
if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) {
723
+ uint32_t num_bytes = max_bytes;
320
- CPUState *cpu = env_cpu(env);
724
+ uint8_t buf[1024];
321
- CPUClass *cc = CPU_GET_CLASS(cpu);
725
+
322
- cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false,
726
+ /* Read descriptor */
323
- retaddr);
727
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
324
- g_assert_not_reached();
728
+ if (desc->size == 0) {
325
+ if (nonfault) {
729
+ desc->size = klass->max_desc_size;
326
+ return TLB_INVALID_MASK;
730
+ } else if (desc->size > klass->max_desc_size) {
327
+ } else {
731
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
328
+ CPUState *cpu = env_cpu(env);
732
+ " is out-of-bounds: %" PRIu32 " > %zu",
329
+ CPUClass *cc = CPU_GET_CLASS(cpu);
733
+ __func__, desc->size, klass->max_desc_size);
330
+ cc->tlb_fill(cpu, addr, fault_size, access_type,
734
+ desc->size = klass->max_desc_size;
331
+ MMU_USER_IDX, false, ra);
735
+ }
332
+ g_assert_not_reached();
736
+ if (desc->size < num_bytes) {
737
+ num_bytes = desc->size;
738
+ }
739
+
740
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
741
+ is_write, max_bytes);
742
+
743
+ while (num_done < num_bytes) {
744
+ /* Try to completely fill the local buffer */
745
+ uint32_t buf_bytes = num_bytes - num_done;
746
+ if (buf_bytes > sizeof(buf)) {
747
+ buf_bytes = sizeof(buf);
748
+ }
333
+ }
749
+
334
}
750
+ /* Write to SD bus */
335
+ return 0;
751
+ if (is_write) {
336
+}
752
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
337
+
753
+ buf, buf_bytes);
338
+int probe_access_flags(CPUArchState *env, target_ulong addr,
754
+
339
+ MMUAccessType access_type, int mmu_idx,
755
+ for (uint32_t i = 0; i < buf_bytes; i++) {
340
+ bool nonfault, void **phost, uintptr_t ra)
756
+ sdbus_write_data(&s->sdbus, buf[i]);
341
+{
757
+ }
342
+ int flags;
758
+
343
+
759
+ /* Read from SD bus */
344
+ flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
760
+ } else {
345
+ *phost = flags ? NULL : g2h(addr);
761
+ for (uint32_t i = 0; i < buf_bytes; i++) {
346
+ return flags;
762
+ buf[i] = sdbus_read_data(&s->sdbus);
347
+}
763
+ }
348
+
764
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
349
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
765
+ buf, buf_bytes);
350
+ MMUAccessType access_type, int mmu_idx, uintptr_t ra)
766
+ }
351
+{
767
+ num_done += buf_bytes;
352
+ int flags;
768
+ }
353
+
769
+
354
+ g_assert(-(addr | TARGET_PAGE_MASK) >= size);
770
+ /* Clear hold flag and flush descriptor */
355
+ flags = probe_access_internal(env, addr, size, access_type, false, ra);
771
+ desc->status &= ~DESC_STATUS_HOLD;
356
+ g_assert(flags == 0);
772
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
357
773
+
358
return size ? g2h(addr) : NULL;
774
+ return num_done;
359
}
775
+}
776
+
777
+static void allwinner_sdhost_dma(AwSdHostState *s)
778
+{
779
+ TransferDescriptor desc;
780
+ hwaddr desc_addr = s->desc_base;
781
+ bool is_write = (s->command & SD_CMDR_WRITE);
782
+ uint32_t bytes_done = 0;
783
+
784
+ /* Check if DMA can be performed */
785
+ if (s->byte_count == 0 || s->block_size == 0 ||
786
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
787
+ return;
788
+ }
789
+
790
+ /*
791
+ * For read operations, data must be available on the SD bus
792
+ * If not, it is an error and we should not act at all
793
+ */
794
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
795
+ return;
796
+ }
797
+
798
+ /* Process the DMA descriptors until all data is copied */
799
+ while (s->byte_count > 0) {
800
+ bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
801
+ is_write, s->byte_count);
802
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
803
+
804
+ if (bytes_done <= s->byte_count) {
805
+ s->byte_count -= bytes_done;
806
+ } else {
807
+ s->byte_count = 0;
808
+ }
809
+
810
+ if (desc.status & DESC_STATUS_LAST) {
811
+ break;
812
+ } else {
813
+ desc_addr = desc.next;
814
+ }
815
+ }
816
+
817
+ /* Raise IRQ to signal DMA is completed */
818
+ s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
819
+
820
+ /* Update DMAC bits */
821
+ s->dmac_status |= SD_IDST_INT_SUMMARY;
822
+
823
+ if (is_write) {
824
+ s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
825
+ } else {
826
+ s->dmac_status |= SD_IDST_RECEIVE_IRQ;
827
+ }
828
+}
829
+
830
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
831
+ unsigned size)
832
+{
833
+ AwSdHostState *s = AW_SDHOST(opaque);
834
+ uint32_t res = 0;
835
+
836
+ switch (offset) {
837
+ case REG_SD_GCTL: /* Global Control */
838
+ res = s->global_ctl;
839
+ break;
840
+ case REG_SD_CKCR: /* Clock Control */
841
+ res = s->clock_ctl;
842
+ break;
843
+ case REG_SD_TMOR: /* Timeout */
844
+ res = s->timeout;
845
+ break;
846
+ case REG_SD_BWDR: /* Bus Width */
847
+ res = s->bus_width;
848
+ break;
849
+ case REG_SD_BKSR: /* Block Size */
850
+ res = s->block_size;
851
+ break;
852
+ case REG_SD_BYCR: /* Byte Count */
853
+ res = s->byte_count;
854
+ break;
855
+ case REG_SD_CMDR: /* Command */
856
+ res = s->command;
857
+ break;
858
+ case REG_SD_CAGR: /* Command Argument */
859
+ res = s->command_arg;
860
+ break;
861
+ case REG_SD_RESP0: /* Response Zero */
862
+ res = s->response[0];
863
+ break;
864
+ case REG_SD_RESP1: /* Response One */
865
+ res = s->response[1];
866
+ break;
867
+ case REG_SD_RESP2: /* Response Two */
868
+ res = s->response[2];
869
+ break;
870
+ case REG_SD_RESP3: /* Response Three */
871
+ res = s->response[3];
872
+ break;
873
+ case REG_SD_IMKR: /* Interrupt Mask */
874
+ res = s->irq_mask;
875
+ break;
876
+ case REG_SD_MISR: /* Masked Interrupt Status */
877
+ res = s->irq_status & s->irq_mask;
878
+ break;
879
+ case REG_SD_RISR: /* Raw Interrupt Status */
880
+ res = s->irq_status;
881
+ break;
882
+ case REG_SD_STAR: /* Status */
883
+ res = s->status;
884
+ break;
885
+ case REG_SD_FWLR: /* FIFO Water Level */
886
+ res = s->fifo_wlevel;
887
+ break;
888
+ case REG_SD_FUNS: /* FIFO Function Select */
889
+ res = s->fifo_func_sel;
890
+ break;
891
+ case REG_SD_DBGC: /* Debug Enable */
892
+ res = s->debug_enable;
893
+ break;
894
+ case REG_SD_A12A: /* Auto command 12 argument */
895
+ res = s->auto12_arg;
896
+ break;
897
+ case REG_SD_NTSR: /* SD NewTiming Set */
898
+ res = s->newtiming_set;
899
+ break;
900
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
901
+ res = s->newtiming_debug;
902
+ break;
903
+ case REG_SD_HWRST: /* Hardware Reset Register */
904
+ res = s->hardware_rst;
905
+ break;
906
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
907
+ res = s->dmac;
908
+ break;
909
+ case REG_SD_DLBA: /* Descriptor List Base Address */
910
+ res = s->desc_base;
911
+ break;
912
+ case REG_SD_IDST: /* Internal DMA Controller Status */
913
+ res = s->dmac_status;
914
+ break;
915
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
916
+ res = s->dmac_irq;
917
+ break;
918
+ case REG_SD_THLDC: /* Card Threshold Control */
919
+ res = s->card_threshold;
920
+ break;
921
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
922
+ res = s->startbit_detect;
923
+ break;
924
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
925
+ res = s->response_crc;
926
+ break;
927
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
928
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
929
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
930
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
931
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
932
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
933
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
934
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
935
+ res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
936
+ break;
937
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
938
+ res = s->status_crc;
939
+ break;
940
+ case REG_SD_FIFO: /* Read/Write FIFO */
941
+ if (sdbus_data_ready(&s->sdbus)) {
942
+ res = sdbus_read_data(&s->sdbus);
943
+ res |= sdbus_read_data(&s->sdbus) << 8;
944
+ res |= sdbus_read_data(&s->sdbus) << 16;
945
+ res |= sdbus_read_data(&s->sdbus) << 24;
946
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
947
+ allwinner_sdhost_auto_stop(s);
948
+ allwinner_sdhost_update_irq(s);
949
+ } else {
950
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
951
+ __func__);
952
+ }
953
+ break;
954
+ default:
955
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
956
+ HWADDR_PRIx"\n", __func__, offset);
957
+ res = 0;
958
+ break;
959
+ }
960
+
961
+ trace_allwinner_sdhost_read(offset, res, size);
962
+ return res;
963
+}
964
+
965
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
966
+ uint64_t value, unsigned size)
967
+{
968
+ AwSdHostState *s = AW_SDHOST(opaque);
969
+
970
+ trace_allwinner_sdhost_write(offset, value, size);
971
+
972
+ switch (offset) {
973
+ case REG_SD_GCTL: /* Global Control */
974
+ s->global_ctl = value;
975
+ s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
976
+ SD_GCTL_SOFT_RST);
977
+ allwinner_sdhost_update_irq(s);
978
+ break;
979
+ case REG_SD_CKCR: /* Clock Control */
980
+ s->clock_ctl = value;
981
+ break;
982
+ case REG_SD_TMOR: /* Timeout */
983
+ s->timeout = value;
984
+ break;
985
+ case REG_SD_BWDR: /* Bus Width */
986
+ s->bus_width = value;
987
+ break;
988
+ case REG_SD_BKSR: /* Block Size */
989
+ s->block_size = value;
990
+ break;
991
+ case REG_SD_BYCR: /* Byte Count */
992
+ s->byte_count = value;
993
+ s->transfer_cnt = value;
994
+ break;
995
+ case REG_SD_CMDR: /* Command */
996
+ s->command = value;
997
+ if (value & SD_CMDR_LOAD) {
998
+ allwinner_sdhost_send_command(s);
999
+ allwinner_sdhost_dma(s);
1000
+ allwinner_sdhost_auto_stop(s);
1001
+ }
1002
+ allwinner_sdhost_update_irq(s);
1003
+ break;
1004
+ case REG_SD_CAGR: /* Command Argument */
1005
+ s->command_arg = value;
1006
+ break;
1007
+ case REG_SD_RESP0: /* Response Zero */
1008
+ s->response[0] = value;
1009
+ break;
1010
+ case REG_SD_RESP1: /* Response One */
1011
+ s->response[1] = value;
1012
+ break;
1013
+ case REG_SD_RESP2: /* Response Two */
1014
+ s->response[2] = value;
1015
+ break;
1016
+ case REG_SD_RESP3: /* Response Three */
1017
+ s->response[3] = value;
1018
+ break;
1019
+ case REG_SD_IMKR: /* Interrupt Mask */
1020
+ s->irq_mask = value;
1021
+ allwinner_sdhost_update_irq(s);
1022
+ break;
1023
+ case REG_SD_MISR: /* Masked Interrupt Status */
1024
+ case REG_SD_RISR: /* Raw Interrupt Status */
1025
+ s->irq_status &= ~value;
1026
+ allwinner_sdhost_update_irq(s);
1027
+ break;
1028
+ case REG_SD_STAR: /* Status */
1029
+ s->status &= ~value;
1030
+ allwinner_sdhost_update_irq(s);
1031
+ break;
1032
+ case REG_SD_FWLR: /* FIFO Water Level */
1033
+ s->fifo_wlevel = value;
1034
+ break;
1035
+ case REG_SD_FUNS: /* FIFO Function Select */
1036
+ s->fifo_func_sel = value;
1037
+ break;
1038
+ case REG_SD_DBGC: /* Debug Enable */
1039
+ s->debug_enable = value;
1040
+ break;
1041
+ case REG_SD_A12A: /* Auto command 12 argument */
1042
+ s->auto12_arg = value;
1043
+ break;
1044
+ case REG_SD_NTSR: /* SD NewTiming Set */
1045
+ s->newtiming_set = value;
1046
+ break;
1047
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
1048
+ s->newtiming_debug = value;
1049
+ break;
1050
+ case REG_SD_HWRST: /* Hardware Reset Register */
1051
+ s->hardware_rst = value;
1052
+ break;
1053
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
1054
+ s->dmac = value;
1055
+ allwinner_sdhost_update_irq(s);
1056
+ break;
1057
+ case REG_SD_DLBA: /* Descriptor List Base Address */
1058
+ s->desc_base = value;
1059
+ break;
1060
+ case REG_SD_IDST: /* Internal DMA Controller Status */
1061
+ s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
1062
+ allwinner_sdhost_update_irq(s);
1063
+ break;
1064
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
1065
+ s->dmac_irq = value;
1066
+ allwinner_sdhost_update_irq(s);
1067
+ break;
1068
+ case REG_SD_THLDC: /* Card Threshold Control */
1069
+ s->card_threshold = value;
1070
+ break;
1071
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
1072
+ s->startbit_detect = value;
1073
+ break;
1074
+ case REG_SD_FIFO: /* Read/Write FIFO */
1075
+ sdbus_write_data(&s->sdbus, value & 0xff);
1076
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
1077
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
1078
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
1079
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
1080
+ allwinner_sdhost_auto_stop(s);
1081
+ allwinner_sdhost_update_irq(s);
1082
+ break;
1083
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
1084
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
1085
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
1086
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
1087
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
1088
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
1089
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
1090
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
1091
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
1092
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
1093
+ break;
1094
+ default:
1095
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
1096
+ HWADDR_PRIx"\n", __func__, offset);
1097
+ break;
1098
+ }
1099
+}
1100
+
1101
+static const MemoryRegionOps allwinner_sdhost_ops = {
1102
+ .read = allwinner_sdhost_read,
1103
+ .write = allwinner_sdhost_write,
1104
+ .endianness = DEVICE_NATIVE_ENDIAN,
1105
+ .valid = {
1106
+ .min_access_size = 4,
1107
+ .max_access_size = 4,
1108
+ },
1109
+ .impl.min_access_size = 4,
1110
+};
1111
+
1112
+static const VMStateDescription vmstate_allwinner_sdhost = {
1113
+ .name = "allwinner-sdhost",
1114
+ .version_id = 1,
1115
+ .minimum_version_id = 1,
1116
+ .fields = (VMStateField[]) {
1117
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
1118
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
1119
+ VMSTATE_UINT32(timeout, AwSdHostState),
1120
+ VMSTATE_UINT32(bus_width, AwSdHostState),
1121
+ VMSTATE_UINT32(block_size, AwSdHostState),
1122
+ VMSTATE_UINT32(byte_count, AwSdHostState),
1123
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
1124
+ VMSTATE_UINT32(command, AwSdHostState),
1125
+ VMSTATE_UINT32(command_arg, AwSdHostState),
1126
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
1127
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
1128
+ VMSTATE_UINT32(irq_status, AwSdHostState),
1129
+ VMSTATE_UINT32(status, AwSdHostState),
1130
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
1131
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
1132
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
1133
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
1134
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
1135
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
1136
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
1137
+ VMSTATE_UINT32(dmac, AwSdHostState),
1138
+ VMSTATE_UINT32(desc_base, AwSdHostState),
1139
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
1140
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
1141
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
1142
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
1143
+ VMSTATE_UINT32(response_crc, AwSdHostState),
1144
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
1145
+ VMSTATE_UINT32(status_crc, AwSdHostState),
1146
+ VMSTATE_END_OF_LIST()
1147
+ }
1148
+};
1149
+
1150
+static void allwinner_sdhost_init(Object *obj)
1151
+{
1152
+ AwSdHostState *s = AW_SDHOST(obj);
1153
+
1154
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1155
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
1156
+
1157
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
1158
+ TYPE_AW_SDHOST, 4 * KiB);
1159
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
1160
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
1161
+}
1162
+
1163
+static void allwinner_sdhost_reset(DeviceState *dev)
1164
+{
1165
+ AwSdHostState *s = AW_SDHOST(dev);
1166
+
1167
+ s->global_ctl = REG_SD_GCTL_RST;
1168
+ s->clock_ctl = REG_SD_CKCR_RST;
1169
+ s->timeout = REG_SD_TMOR_RST;
1170
+ s->bus_width = REG_SD_BWDR_RST;
1171
+ s->block_size = REG_SD_BKSR_RST;
1172
+ s->byte_count = REG_SD_BYCR_RST;
1173
+ s->transfer_cnt = 0;
1174
+
1175
+ s->command = REG_SD_CMDR_RST;
1176
+ s->command_arg = REG_SD_CAGR_RST;
1177
+
1178
+ for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
1179
+ s->response[i] = REG_SD_RESP_RST;
1180
+ }
1181
+
1182
+ s->irq_mask = REG_SD_IMKR_RST;
1183
+ s->irq_status = REG_SD_RISR_RST;
1184
+ s->status = REG_SD_STAR_RST;
1185
+
1186
+ s->fifo_wlevel = REG_SD_FWLR_RST;
1187
+ s->fifo_func_sel = REG_SD_FUNS_RST;
1188
+ s->debug_enable = REG_SD_DBGC_RST;
1189
+ s->auto12_arg = REG_SD_A12A_RST;
1190
+ s->newtiming_set = REG_SD_NTSR_RST;
1191
+ s->newtiming_debug = REG_SD_SDBG_RST;
1192
+ s->hardware_rst = REG_SD_HWRST_RST;
1193
+ s->dmac = REG_SD_DMAC_RST;
1194
+ s->desc_base = REG_SD_DLBA_RST;
1195
+ s->dmac_status = REG_SD_IDST_RST;
1196
+ s->dmac_irq = REG_SD_IDIE_RST;
1197
+ s->card_threshold = REG_SD_THLDC_RST;
1198
+ s->startbit_detect = REG_SD_DSBD_RST;
1199
+ s->response_crc = REG_SD_RES_CRC_RST;
1200
+
1201
+ for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
1202
+ s->data_crc[i] = REG_SD_DATA_CRC_RST;
1203
+ }
1204
+
1205
+ s->status_crc = REG_SD_CRC_STA_RST;
1206
+}
1207
+
1208
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
1209
+{
1210
+ SDBusClass *sbc = SD_BUS_CLASS(klass);
1211
+
1212
+ sbc->set_inserted = allwinner_sdhost_set_inserted;
1213
+}
1214
+
1215
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
1216
+{
1217
+ DeviceClass *dc = DEVICE_CLASS(klass);
1218
+
1219
+ dc->reset = allwinner_sdhost_reset;
1220
+ dc->vmsd = &vmstate_allwinner_sdhost;
1221
+}
1222
+
1223
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
1224
+{
1225
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1226
+ sc->max_desc_size = 8 * KiB;
1227
+}
1228
+
1229
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
1230
+{
1231
+ AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
1232
+ sc->max_desc_size = 64 * KiB;
1233
+}
1234
+
1235
+static TypeInfo allwinner_sdhost_info = {
1236
+ .name = TYPE_AW_SDHOST,
1237
+ .parent = TYPE_SYS_BUS_DEVICE,
1238
+ .instance_init = allwinner_sdhost_init,
1239
+ .instance_size = sizeof(AwSdHostState),
1240
+ .class_init = allwinner_sdhost_class_init,
1241
+ .class_size = sizeof(AwSdHostClass),
1242
+ .abstract = true,
1243
+};
1244
+
1245
+static const TypeInfo allwinner_sdhost_sun4i_info = {
1246
+ .name = TYPE_AW_SDHOST_SUN4I,
1247
+ .parent = TYPE_AW_SDHOST,
1248
+ .class_init = allwinner_sdhost_sun4i_class_init,
1249
+};
1250
+
1251
+static const TypeInfo allwinner_sdhost_sun5i_info = {
1252
+ .name = TYPE_AW_SDHOST_SUN5I,
1253
+ .parent = TYPE_AW_SDHOST,
1254
+ .class_init = allwinner_sdhost_sun5i_class_init,
1255
+};
1256
+
1257
+static const TypeInfo allwinner_sdhost_bus_info = {
1258
+ .name = TYPE_AW_SDHOST_BUS,
1259
+ .parent = TYPE_SD_BUS,
1260
+ .instance_size = sizeof(SDBus),
1261
+ .class_init = allwinner_sdhost_bus_class_init,
1262
+};
1263
+
1264
+static void allwinner_sdhost_register_types(void)
1265
+{
1266
+ type_register_static(&allwinner_sdhost_info);
1267
+ type_register_static(&allwinner_sdhost_sun4i_info);
1268
+ type_register_static(&allwinner_sdhost_sun5i_info);
1269
+ type_register_static(&allwinner_sdhost_bus_info);
1270
+}
1271
+
1272
+type_init(allwinner_sdhost_register_types)
1273
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1274
index XXXXXXX..XXXXXXX 100644
1275
--- a/hw/arm/Kconfig
1276
+++ b/hw/arm/Kconfig
1277
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
1278
select UNIMP
1279
select USB_OHCI
1280
select USB_EHCI_SYSBUS
1281
+ select SD
1282
1283
config RASPI
1284
bool
1285
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
1286
index XXXXXXX..XXXXXXX 100644
1287
--- a/hw/sd/trace-events
1288
+++ b/hw/sd/trace-events
1289
@@ -XXX,XX +XXX,XX @@
1290
# See docs/devel/tracing.txt for syntax documentation.
1291
1292
+# allwinner-sdhost.c
1293
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
1294
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32
1295
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1296
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
1297
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
1298
+
1299
# bcm2835_sdhost.c
1300
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1301
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1302
--
360
--
1303
2.20.1
361
2.20.1
1304
362
1305
363
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
3
We currently have target-endian versions of these operations,
4
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
4
but no easy way to force a specific endianness. This can be
5
Reviewed-by: Joel Stanley <joel@jms.id.au>
5
helpful if the target has endian-specific operations, or a mode
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
that swaps endianness.
7
Message-id: 20200206112645.21275-2-clg@kaod.org
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-7-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
Makefile.objs | 1 +
13
docs/devel/loads-stores.rst | 39 +++--
11
hw/ssi/aspeed_smc.c | 17 +++++++++++++++++
14
include/exec/cpu_ldst.h | 283 +++++++++++++++++++++++++++---------
12
hw/ssi/trace-events | 9 +++++++++
15
accel/tcg/cputlb.c | 236 ++++++++++++++++++++++--------
13
3 files changed, 27 insertions(+)
16
accel/tcg/user-exec.c | 211 ++++++++++++++++++++++-----
14
create mode 100644 hw/ssi/trace-events
17
4 files changed, 587 insertions(+), 182 deletions(-)
15
18
16
diff --git a/Makefile.objs b/Makefile.objs
19
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/Makefile.objs
21
--- a/docs/devel/loads-stores.rst
19
+++ b/Makefile.objs
22
+++ b/docs/devel/loads-stores.rst
20
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi
23
@@ -XXX,XX +XXX,XX @@ function, which is a return address into the generated code.
21
trace-events-subdirs += hw/sd
24
22
trace-events-subdirs += hw/sparc
25
Function names follow the pattern:
23
trace-events-subdirs += hw/sparc64
26
24
+trace-events-subdirs += hw/ssi
27
-load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
25
trace-events-subdirs += hw/timer
28
+load: ``cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
26
trace-events-subdirs += hw/tpm
29
27
trace-events-subdirs += hw/usb
30
-store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
28
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
31
+store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
32
33
``sign``
34
- (empty) : for 32 or 64 bit sizes
35
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
36
- ``l`` : 32 bits
37
- ``q`` : 64 bits
38
39
+``end``
40
+ - (empty) : for target endian, or 8 bit sizes
41
+ - ``_be`` : big endian
42
+ - ``_le`` : little endian
43
+
44
Regexes for git grep:
45
- - ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
46
- - ``\<cpu_st[bwlq]_mmuidx_ra\>``
47
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``
48
+ - ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``
49
50
``cpu_{ld,st}*_data_ra``
51
~~~~~~~~~~~~~~~~~~~~~~~~
52
@@ -XXX,XX +XXX,XX @@ be performed with a context other than the default.
53
54
Function names follow the pattern:
55
56
-load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
57
+load: ``cpu_ld{sign}{size}{end}_data_ra(env, ptr, ra)``
58
59
-store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
60
+store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
61
62
``sign``
63
- (empty) : for 32 or 64 bit sizes
64
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
65
- ``l`` : 32 bits
66
- ``q`` : 64 bits
67
68
+``end``
69
+ - (empty) : for target endian, or 8 bit sizes
70
+ - ``_be`` : big endian
71
+ - ``_le`` : little endian
72
+
73
Regexes for git grep:
74
- - ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
75
- - ``\<cpu_st[bwlq]_data_ra\>``
76
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``
77
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``
78
79
``cpu_{ld,st}*_data``
80
~~~~~~~~~~~~~~~~~~~~~
81
@@ -XXX,XX +XXX,XX @@ the CPU state anyway.
82
83
Function names follow the pattern:
84
85
-load: ``cpu_ld{sign}{size}_data(env, ptr)``
86
+load: ``cpu_ld{sign}{size}{end}_data(env, ptr)``
87
88
-store: ``cpu_st{size}_data(env, ptr, val)``
89
+store: ``cpu_st{size}{end}_data(env, ptr, val)``
90
91
``sign``
92
- (empty) : for 32 or 64 bit sizes
93
@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}_data(env, ptr, val)``
94
- ``l`` : 32 bits
95
- ``q`` : 64 bits
96
97
+``end``
98
+ - (empty) : for target endian, or 8 bit sizes
99
+ - ``_be`` : big endian
100
+ - ``_le`` : little endian
101
+
102
Regexes for git grep
103
- - ``\<cpu_ld[us]\?[bwlq]_data\>``
104
- - ``\<cpu_st[bwlq]_data\+\>``
105
+ - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``
106
+ - ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``
107
108
``cpu_ld*_code``
109
~~~~~~~~~~~~~~~~
110
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
29
index XXXXXXX..XXXXXXX 100644
111
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/ssi/aspeed_smc.c
112
--- a/include/exec/cpu_ldst.h
31
+++ b/hw/ssi/aspeed_smc.c
113
+++ b/include/exec/cpu_ldst.h
32
@@ -XXX,XX +XXX,XX @@
114
@@ -XXX,XX +XXX,XX @@
33
#include "qapi/error.h"
115
*
34
#include "exec/address-spaces.h"
116
* The syntax for the accessors is:
35
#include "qemu/units.h"
117
*
36
+#include "trace.h"
118
- * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
37
119
- * cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
38
#include "hw/irq.h"
120
- * cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
39
#include "hw/qdev-properties.h"
121
+ * load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
122
+ * cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
41
123
+ * cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
42
s->ctrl->reg_to_segment(s, new, &seg);
124
*
43
125
- * store: cpu_st{size}_{mmusuffix}(env, ptr, val)
44
+ trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
126
- * cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
45
+
127
- * cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
46
/* The start address of CS0 is read-only */
128
+ * store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
47
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
129
+ * cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
48
qemu_log_mask(LOG_GUEST_ERROR,
130
+ * cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
49
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
131
*
50
__func__, aspeed_smc_flash_mode(fl));
132
* sign is:
51
}
133
* (empty): for 32 and 64 bit sizes
52
134
@@ -XXX,XX +XXX,XX @@
53
+ trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
135
* l: 32 bits
54
+ aspeed_smc_flash_mode(fl));
136
* q: 64 bits
137
*
138
+ * end is:
139
+ * (empty): for target native endian, or for 8 bit access
140
+ * _be: for forced big endian
141
+ * _le: for forced little endian
142
+ *
143
* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
144
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
145
* the index to use; the "data" and "code" suffixes take the index from
146
@@ -XXX,XX +XXX,XX @@ typedef target_ulong abi_ptr;
147
#endif
148
149
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
150
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
151
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
152
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
153
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
154
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
155
156
-uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
157
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
158
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
159
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
160
-int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
161
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
162
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
163
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
164
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
165
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
166
+
167
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
168
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
169
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
170
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
171
+
172
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
173
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
174
+
175
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
176
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
177
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
178
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
179
+
180
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
181
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
182
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
183
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
184
185
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
186
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
187
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
188
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
189
+
190
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
191
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
192
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
193
+
194
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
195
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
196
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
197
198
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
199
- uint32_t val, uintptr_t retaddr);
200
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
201
- uint32_t val, uintptr_t retaddr);
202
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
203
- uint32_t val, uintptr_t retaddr);
204
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
205
- uint64_t val, uintptr_t retaddr);
206
+ uint32_t val, uintptr_t ra);
207
+
208
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
209
+ uint32_t val, uintptr_t ra);
210
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
211
+ uint32_t val, uintptr_t ra);
212
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
213
+ uint64_t val, uintptr_t ra);
214
+
215
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
216
+ uint32_t val, uintptr_t ra);
217
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
218
+ uint32_t val, uintptr_t ra);
219
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
220
+ uint64_t val, uintptr_t ra);
221
222
#if defined(CONFIG_USER_ONLY)
223
224
@@ -XXX,XX +XXX,XX @@ static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
225
return cpu_ldub_data_ra(env, addr, ra);
226
}
227
228
-static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
229
- int mmu_idx, uintptr_t ra)
230
-{
231
- return cpu_lduw_data_ra(env, addr, ra);
232
-}
233
-
234
-static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
235
- int mmu_idx, uintptr_t ra)
236
-{
237
- return cpu_ldl_data_ra(env, addr, ra);
238
-}
239
-
240
-static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
241
- int mmu_idx, uintptr_t ra)
242
-{
243
- return cpu_ldq_data_ra(env, addr, ra);
244
-}
245
-
246
static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
247
int mmu_idx, uintptr_t ra)
248
{
249
return cpu_ldsb_data_ra(env, addr, ra);
250
}
251
252
-static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
253
- int mmu_idx, uintptr_t ra)
254
+static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
255
+ int mmu_idx, uintptr_t ra)
256
{
257
- return cpu_ldsw_data_ra(env, addr, ra);
258
+ return cpu_lduw_be_data_ra(env, addr, ra);
259
+}
260
+
261
+static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
262
+ int mmu_idx, uintptr_t ra)
263
+{
264
+ return cpu_ldsw_be_data_ra(env, addr, ra);
265
+}
266
+
267
+static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
268
+ int mmu_idx, uintptr_t ra)
269
+{
270
+ return cpu_ldl_be_data_ra(env, addr, ra);
271
+}
272
+
273
+static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
274
+ int mmu_idx, uintptr_t ra)
275
+{
276
+ return cpu_ldq_be_data_ra(env, addr, ra);
277
+}
278
+
279
+static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
280
+ int mmu_idx, uintptr_t ra)
281
+{
282
+ return cpu_lduw_le_data_ra(env, addr, ra);
283
+}
284
+
285
+static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
286
+ int mmu_idx, uintptr_t ra)
287
+{
288
+ return cpu_ldsw_le_data_ra(env, addr, ra);
289
+}
290
+
291
+static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
292
+ int mmu_idx, uintptr_t ra)
293
+{
294
+ return cpu_ldl_le_data_ra(env, addr, ra);
295
+}
296
+
297
+static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
298
+ int mmu_idx, uintptr_t ra)
299
+{
300
+ return cpu_ldq_le_data_ra(env, addr, ra);
301
}
302
303
static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
304
@@ -XXX,XX +XXX,XX @@ static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
305
cpu_stb_data_ra(env, addr, val, ra);
306
}
307
308
-static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
309
- uint32_t val, int mmu_idx, uintptr_t ra)
310
+static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
311
+ uint32_t val, int mmu_idx,
312
+ uintptr_t ra)
313
{
314
- cpu_stw_data_ra(env, addr, val, ra);
315
+ cpu_stw_be_data_ra(env, addr, val, ra);
316
}
317
318
-static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
319
- uint32_t val, int mmu_idx, uintptr_t ra)
320
+static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
321
+ uint32_t val, int mmu_idx,
322
+ uintptr_t ra)
323
{
324
- cpu_stl_data_ra(env, addr, val, ra);
325
+ cpu_stl_be_data_ra(env, addr, val, ra);
326
}
327
328
-static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
329
- uint64_t val, int mmu_idx, uintptr_t ra)
330
+static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
331
+ uint64_t val, int mmu_idx,
332
+ uintptr_t ra)
333
{
334
- cpu_stq_data_ra(env, addr, val, ra);
335
+ cpu_stq_be_data_ra(env, addr, val, ra);
336
+}
337
+
338
+static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
339
+ uint32_t val, int mmu_idx,
340
+ uintptr_t ra)
341
+{
342
+ cpu_stw_le_data_ra(env, addr, val, ra);
343
+}
344
+
345
+static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
346
+ uint32_t val, int mmu_idx,
347
+ uintptr_t ra)
348
+{
349
+ cpu_stl_le_data_ra(env, addr, val, ra);
350
+}
351
+
352
+static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
353
+ uint64_t val, int mmu_idx,
354
+ uintptr_t ra)
355
+{
356
+ cpu_stq_le_data_ra(env, addr, val, ra);
357
}
358
359
#else
360
@@ -XXX,XX +XXX,XX @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
361
362
uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
363
int mmu_idx, uintptr_t ra);
364
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
365
- int mmu_idx, uintptr_t ra);
366
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
367
- int mmu_idx, uintptr_t ra);
368
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
369
- int mmu_idx, uintptr_t ra);
370
-
371
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
372
int mmu_idx, uintptr_t ra);
373
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
374
- int mmu_idx, uintptr_t ra);
375
+
376
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
377
+ int mmu_idx, uintptr_t ra);
378
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
379
+ int mmu_idx, uintptr_t ra);
380
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
381
+ int mmu_idx, uintptr_t ra);
382
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
383
+ int mmu_idx, uintptr_t ra);
384
+
385
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
386
+ int mmu_idx, uintptr_t ra);
387
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
388
+ int mmu_idx, uintptr_t ra);
389
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
390
+ int mmu_idx, uintptr_t ra);
391
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
392
+ int mmu_idx, uintptr_t ra);
393
394
void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
395
int mmu_idx, uintptr_t retaddr);
396
-void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
397
- int mmu_idx, uintptr_t retaddr);
398
-void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
399
- int mmu_idx, uintptr_t retaddr);
400
-void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
401
- int mmu_idx, uintptr_t retaddr);
402
+
403
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
404
+ int mmu_idx, uintptr_t retaddr);
405
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
406
+ int mmu_idx, uintptr_t retaddr);
407
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
408
+ int mmu_idx, uintptr_t retaddr);
409
+
410
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
411
+ int mmu_idx, uintptr_t retaddr);
412
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
413
+ int mmu_idx, uintptr_t retaddr);
414
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
415
+ int mmu_idx, uintptr_t retaddr);
416
417
#endif /* defined(CONFIG_USER_ONLY) */
418
419
+#ifdef TARGET_WORDS_BIGENDIAN
420
+# define cpu_lduw_data cpu_lduw_be_data
421
+# define cpu_ldsw_data cpu_ldsw_be_data
422
+# define cpu_ldl_data cpu_ldl_be_data
423
+# define cpu_ldq_data cpu_ldq_be_data
424
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
425
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
426
+# define cpu_ldl_data_ra cpu_ldl_be_data_ra
427
+# define cpu_ldq_data_ra cpu_ldq_be_data_ra
428
+# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
429
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
430
+# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
431
+# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
432
+# define cpu_stw_data cpu_stw_be_data
433
+# define cpu_stl_data cpu_stl_be_data
434
+# define cpu_stq_data cpu_stq_be_data
435
+# define cpu_stw_data_ra cpu_stw_be_data_ra
436
+# define cpu_stl_data_ra cpu_stl_be_data_ra
437
+# define cpu_stq_data_ra cpu_stq_be_data_ra
438
+# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
439
+# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
440
+# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
441
+#else
442
+# define cpu_lduw_data cpu_lduw_le_data
443
+# define cpu_ldsw_data cpu_ldsw_le_data
444
+# define cpu_ldl_data cpu_ldl_le_data
445
+# define cpu_ldq_data cpu_ldq_le_data
446
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
447
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
448
+# define cpu_ldl_data_ra cpu_ldl_le_data_ra
449
+# define cpu_ldq_data_ra cpu_ldq_le_data_ra
450
+# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
451
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
452
+# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
453
+# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
454
+# define cpu_stw_data cpu_stw_le_data
455
+# define cpu_stl_data cpu_stl_le_data
456
+# define cpu_stq_data cpu_stq_le_data
457
+# define cpu_stw_data_ra cpu_stw_le_data_ra
458
+# define cpu_stl_data_ra cpu_stl_le_data_ra
459
+# define cpu_stq_data_ra cpu_stq_le_data_ra
460
+# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
461
+# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
462
+# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
463
+#endif
464
+
465
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
466
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
467
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
468
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
469
index XXXXXXX..XXXXXXX 100644
470
--- a/accel/tcg/cputlb.c
471
+++ b/accel/tcg/cputlb.c
472
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
473
full_ldub_mmu);
474
}
475
476
-uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
477
- int mmu_idx, uintptr_t ra)
478
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
479
+ int mmu_idx, uintptr_t ra)
480
{
481
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUW,
482
- MO_TE == MO_LE
483
- ? full_le_lduw_mmu : full_be_lduw_mmu);
484
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
485
}
486
487
-int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
488
- int mmu_idx, uintptr_t ra)
489
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
490
+ int mmu_idx, uintptr_t ra)
491
{
492
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_TESW,
493
- MO_TE == MO_LE
494
- ? full_le_lduw_mmu : full_be_lduw_mmu);
495
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
496
+ full_be_lduw_mmu);
497
}
498
499
-uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
500
- int mmu_idx, uintptr_t ra)
501
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
502
+ int mmu_idx, uintptr_t ra)
503
{
504
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUL,
505
- MO_TE == MO_LE
506
- ? full_le_ldul_mmu : full_be_ldul_mmu);
507
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
508
}
509
510
-uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
511
- int mmu_idx, uintptr_t ra)
512
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
513
+ int mmu_idx, uintptr_t ra)
514
{
515
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEQ,
516
- MO_TE == MO_LE
517
- ? helper_le_ldq_mmu : helper_be_ldq_mmu);
518
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
519
+}
520
+
521
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
522
+ int mmu_idx, uintptr_t ra)
523
+{
524
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
525
+}
526
+
527
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
528
+ int mmu_idx, uintptr_t ra)
529
+{
530
+ return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
531
+ full_le_lduw_mmu);
532
+}
533
+
534
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
535
+ int mmu_idx, uintptr_t ra)
536
+{
537
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
538
+}
539
+
540
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
541
+ int mmu_idx, uintptr_t ra)
542
+{
543
+ return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
544
}
545
546
uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
547
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
548
return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
549
}
550
551
-uint32_t cpu_lduw_data_ra(CPUArchState *env, target_ulong ptr,
552
- uintptr_t retaddr)
553
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
554
+ uintptr_t retaddr)
555
{
556
- return cpu_lduw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
557
+ return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
558
}
559
560
-int cpu_ldsw_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
561
+int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
562
{
563
- return cpu_ldsw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
564
+ return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
565
}
566
567
-uint32_t cpu_ldl_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
568
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
569
+ uintptr_t retaddr)
570
{
571
- return cpu_ldl_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
572
+ return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
573
}
574
575
-uint64_t cpu_ldq_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
576
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
577
+ uintptr_t retaddr)
578
{
579
- return cpu_ldq_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
580
+ return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
581
+}
582
+
583
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
584
+ uintptr_t retaddr)
585
+{
586
+ return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
587
+}
588
+
589
+int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
590
+{
591
+ return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
592
+}
593
+
594
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
595
+ uintptr_t retaddr)
596
+{
597
+ return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
598
+}
599
+
600
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
601
+ uintptr_t retaddr)
602
+{
603
+ return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
604
}
605
606
uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
607
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
608
return cpu_ldsb_data_ra(env, ptr, 0);
609
}
610
611
-uint32_t cpu_lduw_data(CPUArchState *env, target_ulong ptr)
612
+uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
613
{
614
- return cpu_lduw_data_ra(env, ptr, 0);
615
+ return cpu_lduw_be_data_ra(env, ptr, 0);
616
}
617
618
-int cpu_ldsw_data(CPUArchState *env, target_ulong ptr)
619
+int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
620
{
621
- return cpu_ldsw_data_ra(env, ptr, 0);
622
+ return cpu_ldsw_be_data_ra(env, ptr, 0);
623
}
624
625
-uint32_t cpu_ldl_data(CPUArchState *env, target_ulong ptr)
626
+uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
627
{
628
- return cpu_ldl_data_ra(env, ptr, 0);
629
+ return cpu_ldl_be_data_ra(env, ptr, 0);
630
}
631
632
-uint64_t cpu_ldq_data(CPUArchState *env, target_ulong ptr)
633
+uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
634
{
635
- return cpu_ldq_data_ra(env, ptr, 0);
636
+ return cpu_ldq_be_data_ra(env, ptr, 0);
637
+}
638
+
639
+uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
640
+{
641
+ return cpu_lduw_le_data_ra(env, ptr, 0);
642
+}
643
+
644
+int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
645
+{
646
+ return cpu_ldsw_le_data_ra(env, ptr, 0);
647
+}
648
+
649
+uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
650
+{
651
+ return cpu_ldl_le_data_ra(env, ptr, 0);
652
+}
653
+
654
+uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
655
+{
656
+ return cpu_ldq_le_data_ra(env, ptr, 0);
657
}
658
659
/*
660
@@ -XXX,XX +XXX,XX @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
661
cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
662
}
663
664
-void cpu_stw_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
665
- int mmu_idx, uintptr_t retaddr)
666
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
667
+ int mmu_idx, uintptr_t retaddr)
668
{
669
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUW);
670
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
671
}
672
673
-void cpu_stl_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
674
- int mmu_idx, uintptr_t retaddr)
675
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
676
+ int mmu_idx, uintptr_t retaddr)
677
{
678
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUL);
679
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
680
}
681
682
-void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
683
- int mmu_idx, uintptr_t retaddr)
684
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
685
+ int mmu_idx, uintptr_t retaddr)
686
{
687
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
688
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
689
+}
690
+
691
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
692
+ int mmu_idx, uintptr_t retaddr)
693
+{
694
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
695
+}
696
+
697
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
698
+ int mmu_idx, uintptr_t retaddr)
699
+{
700
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
701
+}
702
+
703
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
704
+ int mmu_idx, uintptr_t retaddr)
705
+{
706
+ cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
707
}
708
709
void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
710
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
711
cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
712
}
713
714
-void cpu_stw_data_ra(CPUArchState *env, target_ulong ptr,
715
- uint32_t val, uintptr_t retaddr)
716
+void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
717
+ uint32_t val, uintptr_t retaddr)
718
{
719
- cpu_stw_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
720
+ cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
721
}
722
723
-void cpu_stl_data_ra(CPUArchState *env, target_ulong ptr,
724
- uint32_t val, uintptr_t retaddr)
725
+void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
726
+ uint32_t val, uintptr_t retaddr)
727
{
728
- cpu_stl_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
729
+ cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
730
}
731
732
-void cpu_stq_data_ra(CPUArchState *env, target_ulong ptr,
733
- uint64_t val, uintptr_t retaddr)
734
+void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
735
+ uint64_t val, uintptr_t retaddr)
736
{
737
- cpu_stq_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
738
+ cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
739
+}
740
+
741
+void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
742
+ uint32_t val, uintptr_t retaddr)
743
+{
744
+ cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
745
+}
746
+
747
+void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
748
+ uint32_t val, uintptr_t retaddr)
749
+{
750
+ cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
751
+}
752
+
753
+void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
754
+ uint64_t val, uintptr_t retaddr)
755
+{
756
+ cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
757
}
758
759
void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
760
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
761
cpu_stb_data_ra(env, ptr, val, 0);
762
}
763
764
-void cpu_stw_data(CPUArchState *env, target_ulong ptr, uint32_t val)
765
+void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
766
{
767
- cpu_stw_data_ra(env, ptr, val, 0);
768
+ cpu_stw_be_data_ra(env, ptr, val, 0);
769
}
770
771
-void cpu_stl_data(CPUArchState *env, target_ulong ptr, uint32_t val)
772
+void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
773
{
774
- cpu_stl_data_ra(env, ptr, val, 0);
775
+ cpu_stl_be_data_ra(env, ptr, val, 0);
776
}
777
778
-void cpu_stq_data(CPUArchState *env, target_ulong ptr, uint64_t val)
779
+void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
780
{
781
- cpu_stq_data_ra(env, ptr, val, 0);
782
+ cpu_stq_be_data_ra(env, ptr, val, 0);
783
+}
784
+
785
+void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
786
+{
787
+ cpu_stw_le_data_ra(env, ptr, val, 0);
788
+}
789
+
790
+void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
791
+{
792
+ cpu_stl_le_data_ra(env, ptr, val, 0);
793
+}
794
+
795
+void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
796
+{
797
+ cpu_stq_le_data_ra(env, ptr, val, 0);
798
}
799
800
/* First set of helpers allows passing in of OI and RETADDR. This makes
801
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
802
index XXXXXXX..XXXXXXX 100644
803
--- a/accel/tcg/user-exec.c
804
+++ b/accel/tcg/user-exec.c
805
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
55
return ret;
806
return ret;
56
}
807
}
57
808
58
@@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
809
-uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
59
AspeedSMCState *s = fl->controller;
810
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
60
uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
811
{
61
812
uint32_t ret;
62
+ trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
813
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
63
+ (uint8_t) data & 0xff);
814
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
64
+
815
65
if (s->snoop_index == SNOOP_OFF) {
816
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
66
return false; /* Do nothing */
817
- ret = lduw_p(g2h(ptr));
67
818
+ ret = lduw_be_p(g2h(ptr));
68
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
819
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
69
AspeedSMCState *s = fl->controller;
820
return ret;
70
int i;
821
}
71
822
72
+ trace_aspeed_smc_flash_write(fl->id, addr, size, data,
823
-int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
73
+ aspeed_smc_flash_mode(fl));
824
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
74
+
825
{
75
if (!aspeed_smc_is_writable(fl)) {
826
int ret;
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
827
- uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
77
HWADDR_PRIx "\n", __func__, addr);
828
+ uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
78
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
829
79
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
830
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
80
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
831
- ret = ldsw_p(g2h(ptr));
81
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
832
+ ret = ldsw_be_p(g2h(ptr));
82
+
833
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
83
+ trace_aspeed_smc_read(addr, size, s->regs[addr]);
834
return ret;
84
+
835
}
85
return s->regs[addr];
836
86
} else {
837
-uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
87
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
838
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
88
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
839
{
89
__func__, s->regs[R_DMA_FLASH_ADDR]);
840
uint32_t ret;
90
return;
841
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
91
}
842
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
92
+ trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
843
93
844
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
94
/*
845
- ret = ldl_p(g2h(ptr));
95
* When the DMA is on-going, the DMA registers are updated
846
+ ret = ldl_be_p(g2h(ptr));
96
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
847
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
97
848
return ret;
98
addr >>= 2;
849
}
99
850
100
+ trace_aspeed_smc_write(addr, size, data);
851
-uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
101
+
852
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
102
if (addr == s->r_conf ||
853
{
103
(addr >= s->r_timings &&
854
uint64_t ret;
104
addr < s->r_timings + s->ctrl->nregs_timings) ||
855
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
105
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
856
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
106
new file mode 100644
857
107
index XXXXXXX..XXXXXXX
858
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
108
--- /dev/null
859
- ret = ldq_p(g2h(ptr));
109
+++ b/hw/ssi/trace-events
860
+ ret = ldq_be_p(g2h(ptr));
110
@@ -XXX,XX +XXX,XX @@
861
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
111
+# aspeed_smc.c
862
+ return ret;
112
+
863
+}
113
+aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
864
+
114
+aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
865
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
115
+aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
866
+{
116
+aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
867
+ uint32_t ret;
117
+aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
868
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
118
+aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
869
+
119
+aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
870
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
871
+ ret = lduw_le_p(g2h(ptr));
872
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
873
+ return ret;
874
+}
875
+
876
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
877
+{
878
+ int ret;
879
+ uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
880
+
881
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
882
+ ret = ldsw_le_p(g2h(ptr));
883
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
884
+ return ret;
885
+}
886
+
887
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
888
+{
889
+ uint32_t ret;
890
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
891
+
892
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
893
+ ret = ldl_le_p(g2h(ptr));
894
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
895
+ return ret;
896
+}
897
+
898
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
899
+{
900
+ uint64_t ret;
901
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
902
+
903
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
904
+ ret = ldq_le_p(g2h(ptr));
905
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
906
return ret;
907
}
908
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
909
return ret;
910
}
911
912
-uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
913
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
914
{
915
uint32_t ret;
916
917
set_helper_retaddr(retaddr);
918
- ret = cpu_lduw_data(env, ptr);
919
+ ret = cpu_lduw_be_data(env, ptr);
920
clear_helper_retaddr();
921
return ret;
922
}
923
924
-int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
925
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
926
{
927
int ret;
928
929
set_helper_retaddr(retaddr);
930
- ret = cpu_ldsw_data(env, ptr);
931
+ ret = cpu_ldsw_be_data(env, ptr);
932
clear_helper_retaddr();
933
return ret;
934
}
935
936
-uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
937
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
938
{
939
uint32_t ret;
940
941
set_helper_retaddr(retaddr);
942
- ret = cpu_ldl_data(env, ptr);
943
+ ret = cpu_ldl_be_data(env, ptr);
944
clear_helper_retaddr();
945
return ret;
946
}
947
948
-uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
949
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
950
{
951
uint64_t ret;
952
953
set_helper_retaddr(retaddr);
954
- ret = cpu_ldq_data(env, ptr);
955
+ ret = cpu_ldq_be_data(env, ptr);
956
+ clear_helper_retaddr();
957
+ return ret;
958
+}
959
+
960
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
961
+{
962
+ uint32_t ret;
963
+
964
+ set_helper_retaddr(retaddr);
965
+ ret = cpu_lduw_le_data(env, ptr);
966
+ clear_helper_retaddr();
967
+ return ret;
968
+}
969
+
970
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
971
+{
972
+ int ret;
973
+
974
+ set_helper_retaddr(retaddr);
975
+ ret = cpu_ldsw_le_data(env, ptr);
976
+ clear_helper_retaddr();
977
+ return ret;
978
+}
979
+
980
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
981
+{
982
+ uint32_t ret;
983
+
984
+ set_helper_retaddr(retaddr);
985
+ ret = cpu_ldl_le_data(env, ptr);
986
+ clear_helper_retaddr();
987
+ return ret;
988
+}
989
+
990
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
991
+{
992
+ uint64_t ret;
993
+
994
+ set_helper_retaddr(retaddr);
995
+ ret = cpu_ldq_le_data(env, ptr);
996
clear_helper_retaddr();
997
return ret;
998
}
999
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1000
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1001
}
1002
1003
-void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1004
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1005
{
1006
- uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
1007
+ uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
1008
1009
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1010
- stw_p(g2h(ptr), val);
1011
+ stw_be_p(g2h(ptr), val);
1012
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1013
}
1014
1015
-void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1016
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1017
{
1018
- uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
1019
+ uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
1020
1021
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1022
- stl_p(g2h(ptr), val);
1023
+ stl_be_p(g2h(ptr), val);
1024
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1025
}
1026
1027
-void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1028
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1029
{
1030
- uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
1031
+ uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
1032
1033
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1034
- stq_p(g2h(ptr), val);
1035
+ stq_be_p(g2h(ptr), val);
1036
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1037
+}
1038
+
1039
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1040
+{
1041
+ uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
1042
+
1043
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1044
+ stw_le_p(g2h(ptr), val);
1045
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1046
+}
1047
+
1048
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
1049
+{
1050
+ uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
1051
+
1052
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1053
+ stl_le_p(g2h(ptr), val);
1054
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1055
+}
1056
+
1057
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
1058
+{
1059
+ uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
1060
+
1061
+ trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
1062
+ stq_le_p(g2h(ptr), val);
1063
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
1064
}
1065
1066
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
1067
clear_helper_retaddr();
1068
}
1069
1070
-void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
1071
- uint32_t val, uintptr_t retaddr)
1072
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
1073
+ uint32_t val, uintptr_t retaddr)
1074
{
1075
set_helper_retaddr(retaddr);
1076
- cpu_stw_data(env, ptr, val);
1077
+ cpu_stw_be_data(env, ptr, val);
1078
clear_helper_retaddr();
1079
}
1080
1081
-void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
1082
- uint32_t val, uintptr_t retaddr)
1083
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
1084
+ uint32_t val, uintptr_t retaddr)
1085
{
1086
set_helper_retaddr(retaddr);
1087
- cpu_stl_data(env, ptr, val);
1088
+ cpu_stl_be_data(env, ptr, val);
1089
clear_helper_retaddr();
1090
}
1091
1092
-void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
1093
- uint64_t val, uintptr_t retaddr)
1094
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
1095
+ uint64_t val, uintptr_t retaddr)
1096
{
1097
set_helper_retaddr(retaddr);
1098
- cpu_stq_data(env, ptr, val);
1099
+ cpu_stq_be_data(env, ptr, val);
1100
+ clear_helper_retaddr();
1101
+}
1102
+
1103
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
1104
+ uint32_t val, uintptr_t retaddr)
1105
+{
1106
+ set_helper_retaddr(retaddr);
1107
+ cpu_stw_le_data(env, ptr, val);
1108
+ clear_helper_retaddr();
1109
+}
1110
+
1111
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
1112
+ uint32_t val, uintptr_t retaddr)
1113
+{
1114
+ set_helper_retaddr(retaddr);
1115
+ cpu_stl_le_data(env, ptr, val);
1116
+ clear_helper_retaddr();
1117
+}
1118
+
1119
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
1120
+ uint64_t val, uintptr_t retaddr)
1121
+{
1122
+ set_helper_retaddr(retaddr);
1123
+ cpu_stq_le_data(env, ptr, val);
1124
clear_helper_retaddr();
1125
}
1126
120
--
1127
--
121
2.20.1
1128
2.20.1
122
1129
123
1130
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We must include the tag in the FAR_ELx register when raising
3
Use the "normal" memory access functions, rather than the
4
an addressing exception. Which means that we should not clear
4
softmmu internal helper functions directly.
5
out the tag during translation.
5
6
6
Since fb901c905dc3, cpu_mem_index is now a simple extract
7
We cannot at present comply with this for user mode, so we
7
from env->hflags and not a large computation. Which means
8
retain the clean_data_tbi function for the moment, though it
8
that it's now more work to pass around this value than it
9
no longer does what it says on the tin for system mode. This
9
is to recompute it.
10
function is to be replaced with MTE, so don't worry about the
10
11
slight misnaming.
11
This only adjusts the primitives, and does not clean up
12
12
all of the uses within sve_helper.c.
13
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200308012946.16303-3-richard.henderson@linaro.org
16
Message-id: 20200508154359.7494-8-richard.henderson@linaro.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
18
---
19
target/arm/translate-a64.c | 11 +++++++++++
19
target/arm/sve_helper.c | 221 ++++++++++++++++------------------------
20
1 file changed, 11 insertions(+)
20
1 file changed, 86 insertions(+), 135 deletions(-)
21
21
22
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
22
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
23
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-a64.c
24
--- a/target/arm/sve_helper.c
25
+++ b/target/arm/translate-a64.c
25
+++ b/target/arm/sve_helper.c
26
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
26
@@ -XXX,XX +XXX,XX @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
27
static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
27
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
28
{
28
* The controlling predicate is known to be true.
29
TCGv_i64 clean = new_tmp_a64(s);
29
*/
30
+ /*
30
-typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
31
+ * In order to get the correct value in the FAR_ELx register,
31
- target_ulong vaddr, TCGMemOpIdx oi, uintptr_t ra);
32
+ * we must present the memory subsystem with the "dirty" address
32
-typedef sve_ld1_tlb_fn sve_st1_tlb_fn;
33
+ * including the TBI. In system mode we can make this work via
33
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
34
+ * the TLB, dropping the TBI during translation. But for user-only
34
+ target_ulong vaddr, uintptr_t retaddr);
35
+ * mode we don't have that option, and must remove the top byte now.
35
36
+ */
36
/*
37
+#ifdef CONFIG_USER_ONLY
37
* Generate the above primitives.
38
gen_top_byte_ignore(s, clean, addr, s->tbid);
38
@@ -XXX,XX +XXX,XX @@ static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
39
+#else
39
return mem_off; \
40
+ tcg_gen_mov_i64(clean, addr);
41
+#endif
42
return clean;
43
}
40
}
44
41
42
-#ifdef CONFIG_SOFTMMU
43
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
44
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
45
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
46
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
47
+ target_ulong addr, uintptr_t ra) \
48
{ \
49
- TYPEM val = TLB(env, addr, oi, ra); \
50
- *(TYPEE *)(vd + H(reg_off)) = val; \
51
+ *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra); \
52
}
53
-#else
54
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
55
+
56
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
57
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
58
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
59
+ target_ulong addr, uintptr_t ra) \
60
{ \
61
- TYPEM val = HOST(g2h(addr)); \
62
- *(TYPEE *)(vd + H(reg_off)) = val; \
63
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
64
}
65
-#endif
66
67
#define DO_LD_PRIM_1(NAME, H, TE, TM) \
68
DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
69
- DO_LD_TLB(NAME, H, TE, TM, ldub_p, 0, helper_ret_ldub_mmu)
70
+ DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
71
72
DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
73
DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
74
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
75
DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
76
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
77
78
-#define DO_LD_PRIM_2(NAME, end, MOEND, H, TE, TM, PH, PT) \
79
- DO_LD_HOST(NAME##_##end, H, TE, TM, PH##_##end##_p) \
80
- DO_LD_TLB(NAME##_##end, H, TE, TM, PH##_##end##_p, \
81
- MOEND, helper_##end##_##PT##_mmu)
82
+#define DO_ST_PRIM_1(NAME, H, TE, TM) \
83
+ DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
84
85
-DO_LD_PRIM_2(ld1hh, le, MO_LE, H1_2, uint16_t, uint16_t, lduw, lduw)
86
-DO_LD_PRIM_2(ld1hsu, le, MO_LE, H1_4, uint32_t, uint16_t, lduw, lduw)
87
-DO_LD_PRIM_2(ld1hss, le, MO_LE, H1_4, uint32_t, int16_t, lduw, lduw)
88
-DO_LD_PRIM_2(ld1hdu, le, MO_LE, , uint64_t, uint16_t, lduw, lduw)
89
-DO_LD_PRIM_2(ld1hds, le, MO_LE, , uint64_t, int16_t, lduw, lduw)
90
+DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
91
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
92
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
93
+DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
94
95
-DO_LD_PRIM_2(ld1ss, le, MO_LE, H1_4, uint32_t, uint32_t, ldl, ldul)
96
-DO_LD_PRIM_2(ld1sdu, le, MO_LE, , uint64_t, uint32_t, ldl, ldul)
97
-DO_LD_PRIM_2(ld1sds, le, MO_LE, , uint64_t, int32_t, ldl, ldul)
98
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
99
+ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
100
+ DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
101
+ DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
102
+ DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
103
104
-DO_LD_PRIM_2(ld1dd, le, MO_LE, , uint64_t, uint64_t, ldq, ldq)
105
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
106
+ DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
107
+ DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
108
109
-DO_LD_PRIM_2(ld1hh, be, MO_BE, H1_2, uint16_t, uint16_t, lduw, lduw)
110
-DO_LD_PRIM_2(ld1hsu, be, MO_BE, H1_4, uint32_t, uint16_t, lduw, lduw)
111
-DO_LD_PRIM_2(ld1hss, be, MO_BE, H1_4, uint32_t, int16_t, lduw, lduw)
112
-DO_LD_PRIM_2(ld1hdu, be, MO_BE, , uint64_t, uint16_t, lduw, lduw)
113
-DO_LD_PRIM_2(ld1hds, be, MO_BE, , uint64_t, int16_t, lduw, lduw)
114
+DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
115
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
116
+DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
117
+DO_LD_PRIM_2(hdu, , uint64_t, uint16_t, lduw)
118
+DO_LD_PRIM_2(hds, , uint64_t, int16_t, lduw)
119
120
-DO_LD_PRIM_2(ld1ss, be, MO_BE, H1_4, uint32_t, uint32_t, ldl, ldul)
121
-DO_LD_PRIM_2(ld1sdu, be, MO_BE, , uint64_t, uint32_t, ldl, ldul)
122
-DO_LD_PRIM_2(ld1sds, be, MO_BE, , uint64_t, int32_t, ldl, ldul)
123
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
124
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
125
+DO_ST_PRIM_2(hd, , uint64_t, uint16_t, stw)
126
127
-DO_LD_PRIM_2(ld1dd, be, MO_BE, , uint64_t, uint64_t, ldq, ldq)
128
+DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
129
+DO_LD_PRIM_2(sdu, , uint64_t, uint32_t, ldl)
130
+DO_LD_PRIM_2(sds, , uint64_t, int32_t, ldl)
131
+
132
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
133
+DO_ST_PRIM_2(sd, , uint64_t, uint32_t, stl)
134
+
135
+DO_LD_PRIM_2(dd, , uint64_t, uint64_t, ldq)
136
+DO_ST_PRIM_2(dd, , uint64_t, uint64_t, stq)
137
138
#undef DO_LD_TLB
139
+#undef DO_ST_TLB
140
#undef DO_LD_HOST
141
#undef DO_LD_PRIM_1
142
+#undef DO_ST_PRIM_1
143
#undef DO_LD_PRIM_2
144
+#undef DO_ST_PRIM_2
145
146
/*
147
* Skip through a sequence of inactive elements in the guarding predicate @vg,
148
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
149
uint32_t desc, const uintptr_t retaddr,
150
const int esz, const int msz,
151
sve_ld1_host_fn *host_fn,
152
- sve_ld1_tlb_fn *tlb_fn)
153
+ sve_ldst1_tlb_fn *tlb_fn)
154
{
155
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
156
const int mmu_idx = get_mmuidx(oi);
157
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
158
* on I/O memory, it may succeed but not bring in the TLB entry.
159
* But even then we have still made forward progress.
160
*/
161
- tlb_fn(env, &scratch, reg_off, addr + mem_off, oi, retaddr);
162
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
163
reg_off += 1 << esz;
164
}
165
#endif
166
@@ -XXX,XX +XXX,XX @@ DO_LD1_2(ld1dd, 3, 3)
167
*/
168
static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
169
uint32_t desc, int size, uintptr_t ra,
170
- sve_ld1_tlb_fn *tlb_fn)
171
+ sve_ldst1_tlb_fn *tlb_fn)
172
{
173
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
174
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
175
intptr_t i, oprsz = simd_oprsz(desc);
176
ARMVectorReg scratch[2] = { };
177
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
178
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
179
do {
180
if (pg & 1) {
181
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
182
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
183
+ tlb_fn(env, &scratch[0], i, addr, ra);
184
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
185
}
186
i += size, pg >>= size;
187
addr += 2 * size;
188
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
189
190
static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
191
uint32_t desc, int size, uintptr_t ra,
192
- sve_ld1_tlb_fn *tlb_fn)
193
+ sve_ldst1_tlb_fn *tlb_fn)
194
{
195
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
196
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
197
intptr_t i, oprsz = simd_oprsz(desc);
198
ARMVectorReg scratch[3] = { };
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
200
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
201
do {
202
if (pg & 1) {
203
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
204
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
205
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
206
+ tlb_fn(env, &scratch[0], i, addr, ra);
207
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
208
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
209
}
210
i += size, pg >>= size;
211
addr += 3 * size;
212
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
213
214
static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
215
uint32_t desc, int size, uintptr_t ra,
216
- sve_ld1_tlb_fn *tlb_fn)
217
+ sve_ldst1_tlb_fn *tlb_fn)
218
{
219
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
220
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
221
intptr_t i, oprsz = simd_oprsz(desc);
222
ARMVectorReg scratch[4] = { };
223
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
224
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
225
do {
226
if (pg & 1) {
227
- tlb_fn(env, &scratch[0], i, addr, oi, ra);
228
- tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
229
- tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
230
- tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra);
231
+ tlb_fn(env, &scratch[0], i, addr, ra);
232
+ tlb_fn(env, &scratch[1], i, addr + size, ra);
233
+ tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
234
+ tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
235
}
236
i += size, pg >>= size;
237
addr += 4 * size;
238
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
239
uint32_t desc, const uintptr_t retaddr,
240
const int esz, const int msz,
241
sve_ld1_host_fn *host_fn,
242
- sve_ld1_tlb_fn *tlb_fn)
243
+ sve_ldst1_tlb_fn *tlb_fn)
244
{
245
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
246
const int mmu_idx = get_mmuidx(oi);
247
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
248
* Perform one normal read, which will fault or not.
249
* But it is likely to bring the page into the tlb.
250
*/
251
- tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr);
252
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
253
254
/* After any fault, zero any leading predicated false elts. */
255
swap_memzero(vd, reg_off);
256
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, 3, 3)
257
#undef DO_LDFF1_LDNF1_1
258
#undef DO_LDFF1_LDNF1_2
259
260
-/*
261
- * Store contiguous data, protected by a governing predicate.
262
- */
263
-
264
-#ifdef CONFIG_SOFTMMU
265
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
266
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
267
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
268
-{ \
269
- TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra); \
270
-}
271
-#else
272
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
273
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
274
- target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
275
-{ \
276
- HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off))); \
277
-}
278
-#endif
279
-
280
-DO_ST_TLB(st1bb, H1, uint8_t, stb_p, 0, helper_ret_stb_mmu)
281
-DO_ST_TLB(st1bh, H1_2, uint16_t, stb_p, 0, helper_ret_stb_mmu)
282
-DO_ST_TLB(st1bs, H1_4, uint32_t, stb_p, 0, helper_ret_stb_mmu)
283
-DO_ST_TLB(st1bd, , uint64_t, stb_p, 0, helper_ret_stb_mmu)
284
-
285
-DO_ST_TLB(st1hh_le, H1_2, uint16_t, stw_le_p, MO_LE, helper_le_stw_mmu)
286
-DO_ST_TLB(st1hs_le, H1_4, uint32_t, stw_le_p, MO_LE, helper_le_stw_mmu)
287
-DO_ST_TLB(st1hd_le, , uint64_t, stw_le_p, MO_LE, helper_le_stw_mmu)
288
-
289
-DO_ST_TLB(st1ss_le, H1_4, uint32_t, stl_le_p, MO_LE, helper_le_stl_mmu)
290
-DO_ST_TLB(st1sd_le, , uint64_t, stl_le_p, MO_LE, helper_le_stl_mmu)
291
-
292
-DO_ST_TLB(st1dd_le, , uint64_t, stq_le_p, MO_LE, helper_le_stq_mmu)
293
-
294
-DO_ST_TLB(st1hh_be, H1_2, uint16_t, stw_be_p, MO_BE, helper_be_stw_mmu)
295
-DO_ST_TLB(st1hs_be, H1_4, uint32_t, stw_be_p, MO_BE, helper_be_stw_mmu)
296
-DO_ST_TLB(st1hd_be, , uint64_t, stw_be_p, MO_BE, helper_be_stw_mmu)
297
-
298
-DO_ST_TLB(st1ss_be, H1_4, uint32_t, stl_be_p, MO_BE, helper_be_stl_mmu)
299
-DO_ST_TLB(st1sd_be, , uint64_t, stl_be_p, MO_BE, helper_be_stl_mmu)
300
-
301
-DO_ST_TLB(st1dd_be, , uint64_t, stq_be_p, MO_BE, helper_be_stq_mmu)
302
-
303
-#undef DO_ST_TLB
304
-
305
/*
306
* Common helpers for all contiguous 1,2,3,4-register predicated stores.
307
*/
308
static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
309
uint32_t desc, const uintptr_t ra,
310
const int esize, const int msize,
311
- sve_st1_tlb_fn *tlb_fn)
312
+ sve_ldst1_tlb_fn *tlb_fn)
313
{
314
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
315
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
316
intptr_t i, oprsz = simd_oprsz(desc);
317
void *vd = &env->vfp.zregs[rd];
318
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
319
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
320
do {
321
if (pg & 1) {
322
- tlb_fn(env, vd, i, addr, oi, ra);
323
+ tlb_fn(env, vd, i, addr, ra);
324
}
325
i += esize, pg >>= esize;
326
addr += msize;
327
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
328
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
329
uint32_t desc, const uintptr_t ra,
330
const int esize, const int msize,
331
- sve_st1_tlb_fn *tlb_fn)
332
+ sve_ldst1_tlb_fn *tlb_fn)
333
{
334
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
335
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
336
intptr_t i, oprsz = simd_oprsz(desc);
337
void *d1 = &env->vfp.zregs[rd];
338
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
339
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
340
do {
341
if (pg & 1) {
342
- tlb_fn(env, d1, i, addr, oi, ra);
343
- tlb_fn(env, d2, i, addr + msize, oi, ra);
344
+ tlb_fn(env, d1, i, addr, ra);
345
+ tlb_fn(env, d2, i, addr + msize, ra);
346
}
347
i += esize, pg >>= esize;
348
addr += 2 * msize;
349
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
350
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
351
uint32_t desc, const uintptr_t ra,
352
const int esize, const int msize,
353
- sve_st1_tlb_fn *tlb_fn)
354
+ sve_ldst1_tlb_fn *tlb_fn)
355
{
356
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
357
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
358
intptr_t i, oprsz = simd_oprsz(desc);
359
void *d1 = &env->vfp.zregs[rd];
360
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
361
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
362
do {
363
if (pg & 1) {
364
- tlb_fn(env, d1, i, addr, oi, ra);
365
- tlb_fn(env, d2, i, addr + msize, oi, ra);
366
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
367
+ tlb_fn(env, d1, i, addr, ra);
368
+ tlb_fn(env, d2, i, addr + msize, ra);
369
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
370
}
371
i += esize, pg >>= esize;
372
addr += 3 * msize;
373
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
374
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
375
uint32_t desc, const uintptr_t ra,
376
const int esize, const int msize,
377
- sve_st1_tlb_fn *tlb_fn)
378
+ sve_ldst1_tlb_fn *tlb_fn)
379
{
380
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
381
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
382
intptr_t i, oprsz = simd_oprsz(desc);
383
void *d1 = &env->vfp.zregs[rd];
384
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
385
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
386
do {
387
if (pg & 1) {
388
- tlb_fn(env, d1, i, addr, oi, ra);
389
- tlb_fn(env, d2, i, addr + msize, oi, ra);
390
- tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
391
- tlb_fn(env, d4, i, addr + 3 * msize, oi, ra);
392
+ tlb_fn(env, d1, i, addr, ra);
393
+ tlb_fn(env, d2, i, addr + msize, ra);
394
+ tlb_fn(env, d3, i, addr + 2 * msize, ra);
395
+ tlb_fn(env, d4, i, addr + 3 * msize, ra);
396
}
397
i += esize, pg >>= esize;
398
addr += 4 * msize;
399
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
400
401
static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
402
target_ulong base, uint32_t desc, uintptr_t ra,
403
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
404
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
405
{
406
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
407
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
408
intptr_t i, oprsz = simd_oprsz(desc);
409
ARMVectorReg scratch = { };
410
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
411
do {
412
if (likely(pg & 1)) {
413
target_ulong off = off_fn(vm, i);
414
- tlb_fn(env, &scratch, i, base + (off << scale), oi, ra);
415
+ tlb_fn(env, &scratch, i, base + (off << scale), ra);
416
}
417
i += 4, pg >>= 4;
418
} while (i & 15);
419
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
420
421
static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
422
target_ulong base, uint32_t desc, uintptr_t ra,
423
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
424
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
425
{
426
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
427
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
428
intptr_t i, oprsz = simd_oprsz(desc) / 8;
429
ARMVectorReg scratch = { };
430
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
431
uint8_t pg = *(uint8_t *)(vg + H1(i));
432
if (likely(pg & 1)) {
433
target_ulong off = off_fn(vm, i * 8);
434
- tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
435
+ tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
436
}
437
}
438
clear_helper_retaddr();
439
@@ -XXX,XX +XXX,XX @@ DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
440
*/
441
static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
442
target_ulong base, uint32_t desc, uintptr_t ra,
443
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
444
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
445
sve_ld1_nf_fn *nonfault_fn)
446
{
447
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
448
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
449
set_helper_retaddr(ra);
450
addr = off_fn(vm, reg_off);
451
addr = base + (addr << scale);
452
- tlb_fn(env, vd, reg_off, addr, oi, ra);
453
+ tlb_fn(env, vd, reg_off, addr, ra);
454
455
/* The rest of the reads will be non-faulting. */
456
clear_helper_retaddr();
457
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
458
459
static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
460
target_ulong base, uint32_t desc, uintptr_t ra,
461
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
462
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
463
sve_ld1_nf_fn *nonfault_fn)
464
{
465
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
466
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
467
set_helper_retaddr(ra);
468
addr = off_fn(vm, reg_off);
469
addr = base + (addr << scale);
470
- tlb_fn(env, vd, reg_off, addr, oi, ra);
471
+ tlb_fn(env, vd, reg_off, addr, ra);
472
473
/* The rest of the reads will be non-faulting. */
474
clear_helper_retaddr();
475
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd)
476
477
static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
478
target_ulong base, uint32_t desc, uintptr_t ra,
479
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
480
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
481
{
482
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
483
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
484
intptr_t i, oprsz = simd_oprsz(desc);
485
486
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
487
do {
488
if (likely(pg & 1)) {
489
target_ulong off = off_fn(vm, i);
490
- tlb_fn(env, vd, i, base + (off << scale), oi, ra);
491
+ tlb_fn(env, vd, i, base + (off << scale), ra);
492
}
493
i += 4, pg >>= 4;
494
} while (i & 15);
495
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
496
497
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
498
target_ulong base, uint32_t desc, uintptr_t ra,
499
- zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
500
+ zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
501
{
502
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
503
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
504
intptr_t i, oprsz = simd_oprsz(desc) / 8;
505
506
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
507
uint8_t pg = *(uint8_t *)(vg + H1(i));
508
if (likely(pg & 1)) {
509
target_ulong off = off_fn(vm, i * 8);
510
- tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
511
+ tlb_fn(env, vd, i * 8, base + (off << scale), ra);
512
}
513
}
514
clear_helper_retaddr();
45
--
515
--
46
2.20.1
516
2.20.1
47
517
48
518
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We fail to validate the upper bits of a virtual address on a
3
Since we converted back to cpu_*_data_ra, we do not need to
4
translation disabled regime, as per AArch64.TranslateAddressS1Off.
4
do this ourselves.
5
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200308012946.16303-2-richard.henderson@linaro.org
8
Message-id: 20200508154359.7494-9-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++-
11
target/arm/sve_helper.c | 38 --------------------------------------
12
1 file changed, 34 insertions(+), 1 deletion(-)
12
1 file changed, 38 deletions(-)
13
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
16
--- a/target/arm/sve_helper.c
17
+++ b/target/arm/helper.c
17
+++ b/target/arm/sve_helper.c
18
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
18
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
19
/* Definitely a real MMU, not an MPU */
19
return MIN(split, mem_max - mem_off) + mem_off;
20
20
}
21
if (regime_translation_disabled(env, mmu_idx)) {
21
22
- /* MMU disabled. */
22
-#ifndef CONFIG_USER_ONLY
23
+ /*
23
-/* These are normally defined only for CONFIG_USER_ONLY in <exec/cpu_ldst.h> */
24
+ * MMU disabled. S1 addresses within aa64 translation regimes are
24
-static inline void set_helper_retaddr(uintptr_t ra) { }
25
+ * still checked for bounds -- see AArch64.TranslateAddressS1Off.
25
-static inline void clear_helper_retaddr(void) { }
26
+ */
26
-#endif
27
+ if (mmu_idx != ARMMMUIdx_Stage2) {
27
-
28
+ int r_el = regime_el(env, mmu_idx);
28
/*
29
+ if (arm_el_is_aa64(env, r_el)) {
29
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
30
+ int pamax = arm_pamax(env_archcpu(env));
30
* which is always non-null. Elide the useless test.
31
+ uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
31
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
32
+ int addrtop, tbi;
32
return;
33
+
33
}
34
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
34
mem_off = reg_off >> diffsz;
35
+ if (access_type == MMU_INST_FETCH) {
35
- set_helper_retaddr(retaddr);
36
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
36
37
+ }
37
/*
38
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
38
* If the (remaining) load is entirely within a single page, then:
39
+ addrtop = (tbi ? 55 : 63);
39
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
40
+
40
if (test_host_page(host)) {
41
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
41
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
42
+ fi->type = ARMFault_AddressSize;
42
tcg_debug_assert(mem_off == mem_max);
43
+ fi->level = 0;
43
- clear_helper_retaddr();
44
+ fi->stage2 = false;
44
/* After having taken any fault, zero leading inactive elements. */
45
+ return 1;
45
swap_memzero(vd, reg_off);
46
+ }
46
return;
47
+
47
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
48
+ /*
48
}
49
+ * When TBI is disabled, we've just validated that all of the
49
#endif
50
+ * bits above PAMax are zero, so logically we only need to
50
51
+ * clear the top byte for TBI. But it's clearer to follow
51
- clear_helper_retaddr();
52
+ * the pseudocode set of addrdesc.paddress.
52
memcpy(vd, &scratch, reg_max);
53
+ */
53
}
54
+ address = extract64(address, 0, 52);
54
55
+ }
55
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
56
+ }
56
intptr_t i, oprsz = simd_oprsz(desc);
57
*phys_ptr = address;
57
ARMVectorReg scratch[2] = { };
58
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
58
59
*page_size = TARGET_PAGE_SIZE;
59
- set_helper_retaddr(ra);
60
for (i = 0; i < oprsz; ) {
61
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
62
do {
63
@@ -XXX,XX +XXX,XX @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
64
addr += 2 * size;
65
} while (i & 15);
66
}
67
- clear_helper_retaddr();
68
69
/* Wait until all exceptions have been raised to write back. */
70
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
71
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
72
intptr_t i, oprsz = simd_oprsz(desc);
73
ARMVectorReg scratch[3] = { };
74
75
- set_helper_retaddr(ra);
76
for (i = 0; i < oprsz; ) {
77
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
78
do {
79
@@ -XXX,XX +XXX,XX @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
80
addr += 3 * size;
81
} while (i & 15);
82
}
83
- clear_helper_retaddr();
84
85
/* Wait until all exceptions have been raised to write back. */
86
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
87
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
88
intptr_t i, oprsz = simd_oprsz(desc);
89
ARMVectorReg scratch[4] = { };
90
91
- set_helper_retaddr(ra);
92
for (i = 0; i < oprsz; ) {
93
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
94
do {
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
96
addr += 4 * size;
97
} while (i & 15);
98
}
99
- clear_helper_retaddr();
100
101
/* Wait until all exceptions have been raised to write back. */
102
memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
103
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
104
return;
105
}
106
mem_off = reg_off >> diffsz;
107
- set_helper_retaddr(retaddr);
108
109
/*
110
* If the (remaining) load is entirely within a single page, then:
111
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
112
if (test_host_page(host)) {
113
mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
114
tcg_debug_assert(mem_off == mem_max);
115
- clear_helper_retaddr();
116
/* After any fault, zero any leading inactive elements. */
117
swap_memzero(vd, reg_off);
118
return;
119
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
120
}
121
#endif
122
123
- clear_helper_retaddr();
124
record_fault(env, reg_off, reg_max);
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
128
intptr_t i, oprsz = simd_oprsz(desc);
129
void *vd = &env->vfp.zregs[rd];
130
131
- set_helper_retaddr(ra);
132
for (i = 0; i < oprsz; ) {
133
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
134
do {
135
@@ -XXX,XX +XXX,XX @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
136
addr += msize;
137
} while (i & 15);
138
}
139
- clear_helper_retaddr();
140
}
141
142
static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
143
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
144
void *d1 = &env->vfp.zregs[rd];
145
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
146
147
- set_helper_retaddr(ra);
148
for (i = 0; i < oprsz; ) {
149
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
150
do {
151
@@ -XXX,XX +XXX,XX @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
152
addr += 2 * msize;
153
} while (i & 15);
154
}
155
- clear_helper_retaddr();
156
}
157
158
static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
159
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
160
void *d2 = &env->vfp.zregs[(rd + 1) & 31];
161
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
162
163
- set_helper_retaddr(ra);
164
for (i = 0; i < oprsz; ) {
165
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
166
do {
167
@@ -XXX,XX +XXX,XX @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
168
addr += 3 * msize;
169
} while (i & 15);
170
}
171
- clear_helper_retaddr();
172
}
173
174
static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
175
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
176
void *d3 = &env->vfp.zregs[(rd + 2) & 31];
177
void *d4 = &env->vfp.zregs[(rd + 3) & 31];
178
179
- set_helper_retaddr(ra);
180
for (i = 0; i < oprsz; ) {
181
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
182
do {
183
@@ -XXX,XX +XXX,XX @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
184
addr += 4 * msize;
185
} while (i & 15);
186
}
187
- clear_helper_retaddr();
188
}
189
190
#define DO_STN_1(N, NAME, ESIZE) \
191
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
192
intptr_t i, oprsz = simd_oprsz(desc);
193
ARMVectorReg scratch = { };
194
195
- set_helper_retaddr(ra);
196
for (i = 0; i < oprsz; ) {
197
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
198
do {
199
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
200
i += 4, pg >>= 4;
201
} while (i & 15);
202
}
203
- clear_helper_retaddr();
204
205
/* Wait until all exceptions have been raised to write back. */
206
memcpy(vd, &scratch, oprsz);
207
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
208
intptr_t i, oprsz = simd_oprsz(desc) / 8;
209
ARMVectorReg scratch = { };
210
211
- set_helper_retaddr(ra);
212
for (i = 0; i < oprsz; i++) {
213
uint8_t pg = *(uint8_t *)(vg + H1(i));
214
if (likely(pg & 1)) {
215
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
216
tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
217
}
218
}
219
- clear_helper_retaddr();
220
221
/* Wait until all exceptions have been raised to write back. */
222
memcpy(vd, &scratch, oprsz * 8);
223
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
224
reg_off = find_next_active(vg, 0, reg_max, MO_32);
225
if (likely(reg_off < reg_max)) {
226
/* Perform one normal read, which will fault or not. */
227
- set_helper_retaddr(ra);
228
addr = off_fn(vm, reg_off);
229
addr = base + (addr << scale);
230
tlb_fn(env, vd, reg_off, addr, ra);
231
232
/* The rest of the reads will be non-faulting. */
233
- clear_helper_retaddr();
234
}
235
236
/* After any fault, zero the leading predicated false elements. */
237
@@ -XXX,XX +XXX,XX @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
238
reg_off = find_next_active(vg, 0, reg_max, MO_64);
239
if (likely(reg_off < reg_max)) {
240
/* Perform one normal read, which will fault or not. */
241
- set_helper_retaddr(ra);
242
addr = off_fn(vm, reg_off);
243
addr = base + (addr << scale);
244
tlb_fn(env, vd, reg_off, addr, ra);
245
246
/* The rest of the reads will be non-faulting. */
247
- clear_helper_retaddr();
248
}
249
250
/* After any fault, zero the leading predicated false elements. */
251
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
252
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
253
intptr_t i, oprsz = simd_oprsz(desc);
254
255
- set_helper_retaddr(ra);
256
for (i = 0; i < oprsz; ) {
257
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
258
do {
259
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
260
i += 4, pg >>= 4;
261
} while (i & 15);
262
}
263
- clear_helper_retaddr();
264
}
265
266
static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
267
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
268
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
269
intptr_t i, oprsz = simd_oprsz(desc) / 8;
270
271
- set_helper_retaddr(ra);
272
for (i = 0; i < oprsz; i++) {
273
uint8_t pg = *(uint8_t *)(vg + H1(i));
274
if (likely(pg & 1)) {
275
@@ -XXX,XX +XXX,XX @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
276
tlb_fn(env, vd, i * 8, base + (off << scale), ra);
277
}
278
}
279
- clear_helper_retaddr();
280
}
281
282
#define DO_ST1_ZPZ_S(MEM, OFS) \
60
--
283
--
61
2.20.1
284
2.20.1
62
285
63
286
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Security Identifier device found in various Allwinner System on Chip
3
For contiguous predicated memory operations, we want to
4
designs gives applications a per-board unique identifier. This commit
4
minimize the number of tlb lookups performed. We have
5
adds support for the Allwinner Security Identifier using a 128-bit
5
open-coded this for sve_ld1_r, but for correctness with
6
UUID value as input.
6
MTE we will need this for all of the memory operations.
7
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Create a structure that holds the bounds of active elements,
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
and metadata for two pages. Add routines to find those
10
Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com
10
active elements, lookup the pages, and run watchpoints
11
for those pages.
12
13
Temporarily mark the functions unused to avoid Werror.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200508154359.7494-10-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
19
---
13
hw/misc/Makefile.objs | 1 +
20
target/arm/sve_helper.c | 263 +++++++++++++++++++++++++++++++++++++++-
14
include/hw/arm/allwinner-h3.h | 3 +
21
1 file changed, 261 insertions(+), 2 deletions(-)
15
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
22
16
hw/arm/allwinner-h3.c | 11 ++-
23
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
17
hw/arm/orangepi.c | 8 ++
18
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
19
hw/misc/trace-events | 4 +
20
7 files changed, 254 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-sid.h
22
create mode 100644 hw/misc/allwinner-sid.c
23
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
25
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
25
--- a/target/arm/sve_helper.c
27
+++ b/hw/misc/Makefile.objs
26
+++ b/target/arm/sve_helper.c
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc)
29
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
28
}
30
obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o
29
}
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
30
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o
31
-/* Big-endian hosts need to frob the byte indicies. If the copy
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
32
+/* Big-endian hosts need to frob the byte indices. If the copy
34
common-obj-$(CONFIG_NSERIES) += cbus.o
33
* happens to be 8-byte aligned, then no frobbing necessary.
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
34
*/
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
35
static void swap_memmove(void *vd, void *vs, size_t n)
37
index XXXXXXX..XXXXXXX 100644
36
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
38
--- a/include/hw/arm/allwinner-h3.h
37
/*
39
+++ b/include/hw/arm/allwinner-h3.h
38
* Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
40
@@ -XXX,XX +XXX,XX @@
39
* Memory is valid through @host + @mem_max. The register element
41
#include "hw/misc/allwinner-h3-ccu.h"
40
- * indicies are inferred from @mem_ofs, as modified by the types for
42
#include "hw/misc/allwinner-cpucfg.h"
41
+ * indices are inferred from @mem_ofs, as modified by the types for
43
#include "hw/misc/allwinner-h3-sysctrl.h"
42
* which the helper is built. Return the @mem_ofs of the first element
44
+#include "hw/misc/allwinner-sid.h"
43
* not loaded (which is @mem_max if they are all loaded).
45
#include "target/arm/cpu.h"
44
*
46
45
@@ -XXX,XX +XXX,XX @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
47
/**
46
return MIN(split, mem_max - mem_off) + mem_off;
48
@@ -XXX,XX +XXX,XX @@ enum {
47
}
49
AW_H3_SRAM_A2,
48
50
AW_H3_SRAM_C,
51
AW_H3_SYSCTRL,
52
+ AW_H3_SID,
53
AW_H3_EHCI0,
54
AW_H3_OHCI0,
55
AW_H3_EHCI1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
AwH3ClockCtlState ccu;
58
AwCpuCfgState cpucfg;
59
AwH3SysCtrlState sysctrl;
60
+ AwSidState sid;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-sid.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
49
+/*
71
+ * Allwinner Security ID emulation
50
+ * Resolve the guest virtual address to info->host and info->flags.
72
+ *
51
+ * If @nofault, return false if the page is invalid, otherwise
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
52
+ * exit via page fault exception.
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
53
+ */
88
+
54
+
89
+#ifndef HW_MISC_ALLWINNER_SID_H
55
+typedef struct {
90
+#define HW_MISC_ALLWINNER_SID_H
56
+ void *host;
91
+
57
+ int flags;
92
+#include "qom/object.h"
58
+ MemTxAttrs attrs;
93
+#include "hw/sysbus.h"
59
+} SVEHostPage;
94
+#include "qemu/uuid.h"
60
+
95
+
61
+static bool sve_probe_page(SVEHostPage *info, bool nofault,
96
+/**
62
+ CPUARMState *env, target_ulong addr,
97
+ * Object model
63
+ int mem_off, MMUAccessType access_type,
98
+ * @{
64
+ int mmu_idx, uintptr_t retaddr)
65
+{
66
+ int flags;
67
+
68
+ addr += mem_off;
69
+ flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
70
+ &info->host, retaddr);
71
+ info->flags = flags;
72
+
73
+ if (flags & TLB_INVALID_MASK) {
74
+ g_assert(nofault);
75
+ return false;
76
+ }
77
+
78
+ /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
79
+ info->host -= mem_off;
80
+
81
+#ifdef CONFIG_USER_ONLY
82
+ memset(&info->attrs, 0, sizeof(info->attrs));
83
+#else
84
+ /*
85
+ * Find the iotlbentry for addr and return the transaction attributes.
86
+ * This *must* be present in the TLB because we just found the mapping.
87
+ */
88
+ {
89
+ uintptr_t index = tlb_index(env, mmu_idx, addr);
90
+
91
+# ifdef CONFIG_DEBUG_TCG
92
+ CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
93
+ target_ulong comparator = (access_type == MMU_DATA_LOAD
94
+ ? entry->addr_read
95
+ : tlb_addr_write(entry));
96
+ g_assert(tlb_hit(comparator, addr));
97
+# endif
98
+
99
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
100
+ info->attrs = iotlbentry->attrs;
101
+ }
102
+#endif
103
+
104
+ return true;
105
+}
106
+
107
+
108
+/*
109
+ * Analyse contiguous data, protected by a governing predicate.
99
+ */
110
+ */
100
+
111
+
101
+#define TYPE_AW_SID "allwinner-sid"
112
+typedef enum {
102
+#define AW_SID(obj) \
113
+ FAULT_NO,
103
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
114
+ FAULT_FIRST,
104
+
115
+ FAULT_ALL,
105
+/** @} */
116
+} SVEContFault;
106
+
117
+
107
+/**
118
+typedef struct {
108
+ * Allwinner Security ID object instance state
119
+ /*
120
+ * First and last element wholly contained within the two pages.
121
+ * mem_off_first[0] and reg_off_first[0] are always set >= 0.
122
+ * reg_off_last[0] may be < 0 if the first element crosses pages.
123
+ * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1]
124
+ * are set >= 0 only if there are complete elements on a second page.
125
+ *
126
+ * The reg_off_* offsets are relative to the internal vector register.
127
+ * The mem_off_first offset is relative to the memory address; the
128
+ * two offsets are different when a load operation extends, a store
129
+ * operation truncates, or for multi-register operations.
130
+ */
131
+ int16_t mem_off_first[2];
132
+ int16_t reg_off_first[2];
133
+ int16_t reg_off_last[2];
134
+
135
+ /*
136
+ * One element that is misaligned and spans both pages,
137
+ * or -1 if there is no such active element.
138
+ */
139
+ int16_t mem_off_split;
140
+ int16_t reg_off_split;
141
+
142
+ /*
143
+ * The byte offset at which the entire operation crosses a page boundary.
144
+ * Set >= 0 if and only if the entire operation spans two pages.
145
+ */
146
+ int16_t page_split;
147
+
148
+ /* TLB data for the two pages. */
149
+ SVEHostPage page[2];
150
+} SVEContLdSt;
151
+
152
+/*
153
+ * Find first active element on each page, and a loose bound for the
154
+ * final element on each page. Identify any single element that spans
155
+ * the page boundary. Return true if there are any active elements.
109
+ */
156
+ */
110
+typedef struct AwSidState {
157
+static bool __attribute__((unused))
111
+ /*< private >*/
158
+sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
112
+ SysBusDevice parent_obj;
159
+ intptr_t reg_max, int esz, int msize)
113
+ /*< public >*/
114
+
115
+ /** Maps I/O registers in physical memory */
116
+ MemoryRegion iomem;
117
+
118
+ /** Control register defines how and what to read */
119
+ uint32_t control;
120
+
121
+ /** RdKey register contains the data retrieved by the device */
122
+ uint32_t rdkey;
123
+
124
+ /** Stores the emulated device identifier */
125
+ QemuUUID identifier;
126
+
127
+} AwSidState;
128
+
129
+#endif /* HW_MISC_ALLWINNER_SID_H */
130
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/arm/allwinner-h3.c
133
+++ b/hw/arm/allwinner-h3.c
134
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
135
[AW_H3_SRAM_A2] = 0x00044000,
136
[AW_H3_SRAM_C] = 0x00010000,
137
[AW_H3_SYSCTRL] = 0x01c00000,
138
+ [AW_H3_SID] = 0x01c14000,
139
[AW_H3_EHCI0] = 0x01c1a000,
140
[AW_H3_OHCI0] = 0x01c1a400,
141
[AW_H3_EHCI1] = 0x01c1b000,
142
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
143
{ "mmc0", 0x01c0f000, 4 * KiB },
144
{ "mmc1", 0x01c10000, 4 * KiB },
145
{ "mmc2", 0x01c11000, 4 * KiB },
146
- { "sid", 0x01c14000, 1 * KiB },
147
{ "crypto", 0x01c15000, 4 * KiB },
148
{ "msgbox", 0x01c17000, 4 * KiB },
149
{ "spinlock", 0x01c18000, 4 * KiB },
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
151
152
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
153
TYPE_AW_CPUCFG);
154
+
155
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
156
+ TYPE_AW_SID);
157
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
158
+ "identifier", &error_abort);
159
}
160
161
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
162
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
163
qdev_init_nofail(DEVICE(&s->cpucfg));
164
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
165
166
+ /* Security Identifier */
167
+ qdev_init_nofail(DEVICE(&s->sid));
168
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
169
+
170
/* Universal Serial Bus */
171
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
172
qdev_get_gpio_in(DEVICE(&s->gic),
173
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/orangepi.c
176
+++ b/hw/arm/orangepi.c
177
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
178
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
179
&error_abort);
180
181
+ /* Setup SID properties. Currently using a default fixed SID identifier. */
182
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
183
+ qdev_prop_set_string(DEVICE(h3), "identifier",
184
+ "02c00081-1111-2222-3333-000044556677");
185
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) {
186
+ warn_report("Security Identifier value does not include H3 prefix");
187
+ }
188
+
189
/* Mark H3 object realized */
190
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
191
192
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
193
new file mode 100644
194
index XXXXXXX..XXXXXXX
195
--- /dev/null
196
+++ b/hw/misc/allwinner-sid.c
197
@@ -XXX,XX +XXX,XX @@
198
+/*
199
+ * Allwinner Security ID emulation
200
+ *
201
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
202
+ *
203
+ * This program is free software: you can redistribute it and/or modify
204
+ * it under the terms of the GNU General Public License as published by
205
+ * the Free Software Foundation, either version 2 of the License, or
206
+ * (at your option) any later version.
207
+ *
208
+ * This program is distributed in the hope that it will be useful,
209
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
210
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
211
+ * GNU General Public License for more details.
212
+ *
213
+ * You should have received a copy of the GNU General Public License
214
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
215
+ */
216
+
217
+#include "qemu/osdep.h"
218
+#include "qemu/units.h"
219
+#include "hw/sysbus.h"
220
+#include "migration/vmstate.h"
221
+#include "qemu/log.h"
222
+#include "qemu/module.h"
223
+#include "qemu/guest-random.h"
224
+#include "qapi/error.h"
225
+#include "hw/qdev-properties.h"
226
+#include "hw/misc/allwinner-sid.h"
227
+#include "trace.h"
228
+
229
+/* SID register offsets */
230
+enum {
231
+ REG_PRCTL = 0x40, /* Control */
232
+ REG_RDKEY = 0x60, /* Read Key */
233
+};
234
+
235
+/* SID register flags */
236
+enum {
237
+ REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */
238
+ REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */
239
+};
240
+
241
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
242
+ unsigned size)
243
+{
160
+{
244
+ const AwSidState *s = AW_SID(opaque);
161
+ const int esize = 1 << esz;
245
+ uint64_t val = 0;
162
+ const uint64_t pg_mask = pred_esz_masks[esz];
246
+
163
+ intptr_t reg_off_first = -1, reg_off_last = -1, reg_off_split;
247
+ switch (offset) {
164
+ intptr_t mem_off_last, mem_off_split;
248
+ case REG_PRCTL: /* Control */
165
+ intptr_t page_split, elt_split;
249
+ val = s->control;
166
+ intptr_t i;
250
+ break;
167
+
251
+ case REG_RDKEY: /* Read Key */
168
+ /* Set all of the element indices to -1, and the TLB data to 0. */
252
+ val = s->rdkey;
169
+ memset(info, -1, offsetof(SVEContLdSt, page));
253
+ break;
170
+ memset(info->page, 0, sizeof(info->page));
254
+ default:
171
+
255
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
172
+ /* Gross scan over the entire predicate to find bounds. */
256
+ __func__, (uint32_t)offset);
173
+ i = 0;
257
+ return 0;
174
+ do {
258
+ }
175
+ uint64_t pg = vg[i] & pg_mask;
259
+
176
+ if (pg) {
260
+ trace_allwinner_sid_read(offset, val, size);
177
+ reg_off_last = i * 64 + 63 - clz64(pg);
261
+
178
+ if (reg_off_first < 0) {
262
+ return val;
179
+ reg_off_first = i * 64 + ctz64(pg);
263
+}
264
+
265
+static void allwinner_sid_write(void *opaque, hwaddr offset,
266
+ uint64_t val, unsigned size)
267
+{
268
+ AwSidState *s = AW_SID(opaque);
269
+
270
+ trace_allwinner_sid_write(offset, val, size);
271
+
272
+ switch (offset) {
273
+ case REG_PRCTL: /* Control */
274
+ s->control = val;
275
+
276
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
277
+ (s->control & REG_PRCTL_WRITE)) {
278
+ uint32_t id = s->control >> 16;
279
+
280
+ if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) {
281
+ s->rdkey = ldl_be_p(&s->identifier.data[id]);
282
+ }
180
+ }
283
+ }
181
+ }
284
+ s->control &= ~REG_PRCTL_WRITE;
182
+ } while (++i * 64 < reg_max);
285
+ break;
183
+
286
+ case REG_RDKEY: /* Read Key */
184
+ if (unlikely(reg_off_first < 0)) {
287
+ break;
185
+ /* No active elements, no pages touched. */
288
+ default:
186
+ return false;
289
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
187
+ }
290
+ __func__, (uint32_t)offset);
188
+ tcg_debug_assert(reg_off_last >= 0 && reg_off_last < reg_max);
291
+ break;
189
+
292
+ }
190
+ info->reg_off_first[0] = reg_off_first;
191
+ info->mem_off_first[0] = (reg_off_first >> esz) * msize;
192
+ mem_off_last = (reg_off_last >> esz) * msize;
193
+
194
+ page_split = -(addr | TARGET_PAGE_MASK);
195
+ if (likely(mem_off_last + msize <= page_split)) {
196
+ /* The entire operation fits within a single page. */
197
+ info->reg_off_last[0] = reg_off_last;
198
+ return true;
199
+ }
200
+
201
+ info->page_split = page_split;
202
+ elt_split = page_split / msize;
203
+ reg_off_split = elt_split << esz;
204
+ mem_off_split = elt_split * msize;
205
+
206
+ /*
207
+ * This is the last full element on the first page, but it is not
208
+ * necessarily active. If there is no full element, i.e. the first
209
+ * active element is the one that's split, this value remains -1.
210
+ * It is useful as iteration bounds.
211
+ */
212
+ if (elt_split != 0) {
213
+ info->reg_off_last[0] = reg_off_split - esize;
214
+ }
215
+
216
+ /* Determine if an unaligned element spans the pages. */
217
+ if (page_split % msize != 0) {
218
+ /* It is helpful to know if the split element is active. */
219
+ if ((vg[reg_off_split >> 6] >> (reg_off_split & 63)) & 1) {
220
+ info->reg_off_split = reg_off_split;
221
+ info->mem_off_split = mem_off_split;
222
+
223
+ if (reg_off_split == reg_off_last) {
224
+ /* The page crossing element is last. */
225
+ return true;
226
+ }
227
+ }
228
+ reg_off_split += esize;
229
+ mem_off_split += msize;
230
+ }
231
+
232
+ /*
233
+ * We do want the first active element on the second page, because
234
+ * this may affect the address reported in an exception.
235
+ */
236
+ reg_off_split = find_next_active(vg, reg_off_split, reg_max, esz);
237
+ tcg_debug_assert(reg_off_split <= reg_off_last);
238
+ info->reg_off_first[1] = reg_off_split;
239
+ info->mem_off_first[1] = (reg_off_split >> esz) * msize;
240
+ info->reg_off_last[1] = reg_off_last;
241
+ return true;
293
+}
242
+}
294
+
243
+
295
+static const MemoryRegionOps allwinner_sid_ops = {
244
+/*
296
+ .read = allwinner_sid_read,
245
+ * Resolve the guest virtual addresses to info->page[].
297
+ .write = allwinner_sid_write,
246
+ * Control the generation of page faults with @fault. Return false if
298
+ .endianness = DEVICE_NATIVE_ENDIAN,
247
+ * there is no work to do, which can only happen with @fault == FAULT_NO.
299
+ .valid = {
248
+ */
300
+ .min_access_size = 4,
249
+static bool __attribute__((unused))
301
+ .max_access_size = 4,
250
+sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
302
+ },
251
+ target_ulong addr, MMUAccessType access_type,
303
+ .impl.min_access_size = 4,
252
+ uintptr_t retaddr)
304
+};
305
+
306
+static void allwinner_sid_reset(DeviceState *dev)
307
+{
253
+{
308
+ AwSidState *s = AW_SID(dev);
254
+ int mmu_idx = cpu_mmu_index(env, false);
309
+
255
+ int mem_off = info->mem_off_first[0];
310
+ /* Set default values for registers */
256
+ bool nofault = fault == FAULT_NO;
311
+ s->control = 0;
257
+ bool have_work = true;
312
+ s->rdkey = 0;
258
+
259
+ if (!sve_probe_page(&info->page[0], nofault, env, addr, mem_off,
260
+ access_type, mmu_idx, retaddr)) {
261
+ /* No work to be done. */
262
+ return false;
263
+ }
264
+
265
+ if (likely(info->page_split < 0)) {
266
+ /* The entire operation was on the one page. */
267
+ return true;
268
+ }
269
+
270
+ /*
271
+ * If the second page is invalid, then we want the fault address to be
272
+ * the first byte on that page which is accessed.
273
+ */
274
+ if (info->mem_off_split >= 0) {
275
+ /*
276
+ * There is an element split across the pages. The fault address
277
+ * should be the first byte of the second page.
278
+ */
279
+ mem_off = info->page_split;
280
+ /*
281
+ * If the split element is also the first active element
282
+ * of the vector, then: For first-fault we should continue
283
+ * to generate faults for the second page. For no-fault,
284
+ * we have work only if the second page is valid.
285
+ */
286
+ if (info->mem_off_first[0] < info->mem_off_split) {
287
+ nofault = FAULT_FIRST;
288
+ have_work = false;
289
+ }
290
+ } else {
291
+ /*
292
+ * There is no element split across the pages. The fault address
293
+ * should be the first active element on the second page.
294
+ */
295
+ mem_off = info->mem_off_first[1];
296
+ /*
297
+ * There must have been one active element on the first page,
298
+ * so we're out of first-fault territory.
299
+ */
300
+ nofault = fault != FAULT_ALL;
301
+ }
302
+
303
+ have_work |= sve_probe_page(&info->page[1], nofault, env, addr, mem_off,
304
+ access_type, mmu_idx, retaddr);
305
+ return have_work;
313
+}
306
+}
314
+
307
+
315
+static void allwinner_sid_init(Object *obj)
308
/*
316
+{
309
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
317
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
310
* which is always non-null. Elide the useless test.
318
+ AwSidState *s = AW_SID(obj);
319
+
320
+ /* Memory mapping */
321
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
322
+ TYPE_AW_SID, 1 * KiB);
323
+ sysbus_init_mmio(sbd, &s->iomem);
324
+}
325
+
326
+static Property allwinner_sid_properties[] = {
327
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
328
+ DEFINE_PROP_END_OF_LIST()
329
+};
330
+
331
+static const VMStateDescription allwinner_sid_vmstate = {
332
+ .name = "allwinner-sid",
333
+ .version_id = 1,
334
+ .minimum_version_id = 1,
335
+ .fields = (VMStateField[]) {
336
+ VMSTATE_UINT32(control, AwSidState),
337
+ VMSTATE_UINT32(rdkey, AwSidState),
338
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1),
339
+ VMSTATE_END_OF_LIST()
340
+ }
341
+};
342
+
343
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
344
+{
345
+ DeviceClass *dc = DEVICE_CLASS(klass);
346
+
347
+ dc->reset = allwinner_sid_reset;
348
+ dc->vmsd = &allwinner_sid_vmstate;
349
+ device_class_set_props(dc, allwinner_sid_properties);
350
+}
351
+
352
+static const TypeInfo allwinner_sid_info = {
353
+ .name = TYPE_AW_SID,
354
+ .parent = TYPE_SYS_BUS_DEVICE,
355
+ .instance_init = allwinner_sid_init,
356
+ .instance_size = sizeof(AwSidState),
357
+ .class_init = allwinner_sid_class_init,
358
+};
359
+
360
+static void allwinner_sid_register(void)
361
+{
362
+ type_register_static(&allwinner_sid_info);
363
+}
364
+
365
+type_init(allwinner_sid_register)
366
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
367
index XXXXXXX..XXXXXXX 100644
368
--- a/hw/misc/trace-events
369
+++ b/hw/misc/trace-events
370
@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad
371
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
372
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
373
374
+# allwinner-sid.c
375
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
376
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
377
+
378
# eccmemctl.c
379
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
380
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
381
--
311
--
382
2.20.1
312
2.20.1
383
313
384
314
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
i.MX25 supports two USB controllers. Let's wire them up.
3
The current interface includes a loop; change it to load a
4
4
single element. We will then be able to use the function
5
With this patch, imx25-pdk can boot from both USB ports.
5
for ld{2,3,4} where individual vector elements are not adjacent.
6
6
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
Replace each call with the simplest possible loop over active
8
Message-id: 20200310215146.19688-3-linux@roeck-us.net
8
elements.
9
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200508154359.7494-11-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
include/hw/arm/fsl-imx25.h | 9 +++++++++
15
target/arm/sve_helper.c | 124 ++++++++++++++++++++--------------------
13
hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++
16
1 file changed, 63 insertions(+), 61 deletions(-)
14
2 files changed, 33 insertions(+)
17
15
18
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
20
--- a/target/arm/sve_helper.c
19
+++ b/include/hw/arm/fsl-imx25.h
21
+++ b/target/arm/sve_helper.c
20
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
21
#include "hw/i2c/imx_i2c.h"
23
*/
22
#include "hw/gpio/imx_gpio.h"
24
23
#include "hw/sd/sdhci.h"
25
/*
24
+#include "hw/usb/chipidea.h"
26
- * Load elements into @vd, controlled by @vg, from @host + @mem_ofs.
25
#include "exec/memory.h"
27
- * Memory is valid through @host + @mem_max. The register element
26
#include "target/arm/cpu.h"
28
- * indices are inferred from @mem_ofs, as modified by the types for
27
29
- * which the helper is built. Return the @mem_ofs of the first element
28
@@ -XXX,XX +XXX,XX @@
30
- * not loaded (which is @mem_max if they are all loaded).
29
#define FSL_IMX25_NUM_I2CS 3
31
- *
30
#define FSL_IMX25_NUM_GPIOS 4
32
- * For softmmu, we have fully validated the guest page. For user-only,
31
#define FSL_IMX25_NUM_ESDHCS 2
33
- * we cannot fully validate without taking the mmap lock, but since we
32
+#define FSL_IMX25_NUM_USBS 2
34
- * know the access is within one host page, if any access is valid they
33
35
- * all must be valid. However, when @vg is all false, it may be that
34
typedef struct FslIMX25State {
36
- * no access is valid.
35
/*< private >*/
37
+ * Load one element into @vd + @reg_off from @host.
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
38
+ * The controlling predicate is known to be true.
37
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
39
*/
38
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
40
-typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
39
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
41
- intptr_t mem_ofs, intptr_t mem_max);
40
+ ChipideaState usb[FSL_IMX25_NUM_USBS];
42
+typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
41
MemoryRegion rom[2];
43
42
MemoryRegion iram;
44
/*
43
MemoryRegion iram_alias;
45
* Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
44
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
46
@@ -XXX,XX +XXX,XX @@ typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
45
#define FSL_IMX25_GPIO1_SIZE 0x4000
47
*/
46
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
48
47
#define FSL_IMX25_GPIO2_SIZE 0x4000
49
#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
48
+#define FSL_IMX25_USB1_ADDR 0x53FF4000
50
-static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host, \
49
+#define FSL_IMX25_USB1_SIZE 0x0200
51
- intptr_t mem_off, const intptr_t mem_max) \
50
+#define FSL_IMX25_USB2_ADDR 0x53FF4400
52
-{ \
51
+#define FSL_IMX25_USB2_SIZE 0x0200
53
- intptr_t reg_off = mem_off * (sizeof(TYPEE) / sizeof(TYPEM)); \
52
#define FSL_IMX25_AVIC_ADDR 0x68000000
54
- uint64_t *pg = vg; \
53
#define FSL_IMX25_AVIC_SIZE 0x4000
55
- while (mem_off + sizeof(TYPEM) <= mem_max) { \
54
#define FSL_IMX25_IRAM_ADDR 0x78000000
56
- TYPEM val = 0; \
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
57
- if (likely((pg[reg_off >> 6] >> (reg_off & 63)) & 1)) { \
56
#define FSL_IMX25_GPIO4_IRQ 23
58
- val = HOST(host + mem_off); \
57
#define FSL_IMX25_ESDHC1_IRQ 9
59
- } \
58
#define FSL_IMX25_ESDHC2_IRQ 8
60
- *(TYPEE *)(vd + H(reg_off)) = val; \
59
+#define FSL_IMX25_USB1_IRQ 37
61
- mem_off += sizeof(TYPEM), reg_off += sizeof(TYPEE); \
60
+#define FSL_IMX25_USB2_IRQ 35
62
- } \
61
63
- return mem_off; \
62
#endif /* FSL_IMX25_H */
64
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
63
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
65
+{ \
64
index XXXXXXX..XXXXXXX 100644
66
+ TYPEM val = HOST(host); \
65
--- a/hw/arm/fsl-imx25.c
67
+ *(TYPEE *)(vd + H(reg_off)) = val; \
66
+++ b/hw/arm/fsl-imx25.c
67
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
68
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
69
TYPE_IMX_USDHC);
70
}
71
+
72
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
73
+ sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
74
+ TYPE_CHIPIDEA);
75
+ }
76
+
77
}
68
}
78
69
79
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
70
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
80
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
71
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
81
esdhc_table[i].irq));
72
static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
82
}
73
uint32_t desc, const uintptr_t retaddr,
83
74
const int esz, const int msz,
84
+ /* USB */
75
- sve_ld1_host_fn *host_fn,
85
+ for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
76
+ sve_ldst1_host_fn *host_fn,
86
+ static const struct {
77
sve_ldst1_tlb_fn *tlb_fn)
87
+ hwaddr addr;
78
{
88
+ unsigned int irq;
79
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
89
+ } usb_table[FSL_IMX25_NUM_USBS] = {
80
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
90
+ { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
81
if (likely(split == mem_max)) {
91
+ { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
82
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
92
+ };
83
if (test_host_page(host)) {
93
+
84
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
94
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
85
- tcg_debug_assert(mem_off == mem_max);
95
+ &error_abort);
86
+ intptr_t i = reg_off;
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
87
+ host -= mem_off;
97
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
88
+ do {
98
+ qdev_get_gpio_in(DEVICE(&s->avic),
89
+ host_fn(vd, i, host + (i >> diffsz));
99
+ usb_table[i].irq));
90
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
100
+ }
91
+ } while (i < reg_max);
101
+
92
/* After having taken any fault, zero leading inactive elements. */
102
/* initialize 2 x 16 KB ROM */
93
swap_memzero(vd, reg_off);
103
memory_region_init_rom(&s->rom[0], NULL,
94
return;
104
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
95
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
96
*/
97
#ifdef CONFIG_USER_ONLY
98
swap_memzero(&scratch, reg_off);
99
- host_fn(&scratch, vg, g2h(addr), mem_off, mem_max);
100
+ host = g2h(addr);
101
+ do {
102
+ host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
103
+ reg_off += 1 << esz;
104
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
105
+ } while (reg_off < reg_max);
106
#else
107
memset(&scratch, 0, reg_max);
108
goto start;
109
@@ -XXX,XX +XXX,XX @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
110
host = tlb_vaddr_to_host(env, addr + mem_off,
111
MMU_DATA_LOAD, mmu_idx);
112
if (host) {
113
- mem_off = host_fn(&scratch, vg, host - mem_off,
114
- mem_off, split);
115
- reg_off = mem_off << diffsz;
116
+ host -= mem_off;
117
+ do {
118
+ host_fn(&scratch, reg_off, host + mem_off);
119
+ reg_off += 1 << esz;
120
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
121
+ mem_off = reg_off >> diffsz;
122
+ } while (split - mem_off >= (1 << msz));
123
continue;
124
}
125
}
126
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
127
static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
128
uint32_t desc, const uintptr_t retaddr,
129
const int esz, const int msz,
130
- sve_ld1_host_fn *host_fn,
131
+ sve_ldst1_host_fn *host_fn,
132
sve_ldst1_tlb_fn *tlb_fn)
133
{
134
const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
135
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
136
const int diffsz = esz - msz;
137
const intptr_t reg_max = simd_oprsz(desc);
138
const intptr_t mem_max = reg_max >> diffsz;
139
- intptr_t split, reg_off, mem_off;
140
+ intptr_t split, reg_off, mem_off, i;
141
void *host;
142
143
/* Skip to the first active element. */
144
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
145
if (likely(split == mem_max)) {
146
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
147
if (test_host_page(host)) {
148
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
149
- tcg_debug_assert(mem_off == mem_max);
150
+ i = reg_off;
151
+ host -= mem_off;
152
+ do {
153
+ host_fn(vd, i, host + (i >> diffsz));
154
+ i = find_next_active(vg, i + (1 << esz), reg_max, esz);
155
+ } while (i < reg_max);
156
/* After any fault, zero any leading inactive elements. */
157
swap_memzero(vd, reg_off);
158
return;
159
}
160
}
161
162
-#ifdef CONFIG_USER_ONLY
163
- /*
164
- * The page(s) containing this first element at ADDR+MEM_OFF must
165
- * be valid. Considering that this first element may be misaligned
166
- * and cross a page boundary itself, take the rest of the page from
167
- * the last byte of the element.
168
- */
169
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
170
- mem_off = host_fn(vd, vg, g2h(addr), mem_off, split);
171
-
172
- /* After any fault, zero any leading inactive elements. */
173
- swap_memzero(vd, reg_off);
174
- reg_off = mem_off << diffsz;
175
-#else
176
/*
177
* Perform one normal read, which will fault or not.
178
* But it is likely to bring the page into the tlb.
179
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
180
if (split >= (1 << msz)) {
181
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
182
if (host) {
183
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
184
- reg_off = mem_off << diffsz;
185
+ host -= mem_off;
186
+ do {
187
+ host_fn(vd, reg_off, host + mem_off);
188
+ reg_off += 1 << esz;
189
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
190
+ mem_off = reg_off >> diffsz;
191
+ } while (split - mem_off >= (1 << msz));
192
}
193
}
194
-#endif
195
196
record_fault(env, reg_off, reg_max);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
199
*/
200
static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
201
uint32_t desc, const int esz, const int msz,
202
- sve_ld1_host_fn *host_fn)
203
+ sve_ldst1_host_fn *host_fn)
204
{
205
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
206
void *vd = &env->vfp.zregs[rd];
207
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
208
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
209
if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
210
/* The entire operation is valid and will not fault. */
211
- host_fn(vd, vg, host, 0, mem_max);
212
+ reg_off = 0;
213
+ do {
214
+ mem_off = reg_off >> diffsz;
215
+ host_fn(vd, reg_off, host + mem_off);
216
+ reg_off += 1 << esz;
217
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
218
+ } while (reg_off < reg_max);
219
return;
220
}
221
#endif
222
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
223
if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
224
/* At least one load is valid; take the rest of the page. */
225
split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
226
- mem_off = host_fn(vd, vg, host, mem_off, split);
227
- reg_off = mem_off << diffsz;
228
+ do {
229
+ host_fn(vd, reg_off, host + mem_off);
230
+ reg_off += 1 << esz;
231
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
232
+ mem_off = reg_off >> diffsz;
233
+ } while (split - mem_off >= (1 << msz));
234
}
235
#else
236
/*
237
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
238
host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
239
split = max_for_page(addr, mem_off, mem_max);
240
if (host && split >= (1 << msz)) {
241
- mem_off = host_fn(vd, vg, host - mem_off, mem_off, split);
242
- reg_off = mem_off << diffsz;
243
+ host -= mem_off;
244
+ do {
245
+ host_fn(vd, reg_off, host + mem_off);
246
+ reg_off += 1 << esz;
247
+ reg_off = find_next_active(vg, reg_off, reg_max, esz);
248
+ mem_off = reg_off >> diffsz;
249
+ } while (split - mem_off >= (1 << msz));
250
}
251
#endif
252
105
--
253
--
106
2.20.1
254
2.20.1
107
255
108
256
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
3
First use of the new helper functions, so we can remove the
4
provided on the command line to available eSDHC controllers.
4
unused markup. No longer need a scratch for user-only, as
5
5
we completely probe the page set before reading; system mode
6
This patch enables booting the imx25-pdk emulation from SD card.
6
still requires a scratch for MMIO.
7
7
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200310215146.19688-2-linux@roeck-us.net
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: made commit subject consistent with other patch]
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200508154359.7494-12-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
include/hw/arm/fsl-imx25.h | 9 +++++++++
13
target/arm/sve_helper.c | 188 +++++++++++++++++++++-------------------
15
hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++
14
1 file changed, 97 insertions(+), 91 deletions(-)
16
hw/arm/imx25_pdk.c | 16 ++++++++++++++++
15
17
3 files changed, 57 insertions(+)
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
19
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/fsl-imx25.h
18
--- a/target/arm/sve_helper.c
22
+++ b/include/hw/arm/fsl-imx25.h
19
+++ b/target/arm/sve_helper.c
23
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
#include "hw/misc/imx_rngc.h"
21
* final element on each page. Identify any single element that spans
25
#include "hw/i2c/imx_i2c.h"
22
* the page boundary. Return true if there are any active elements.
26
#include "hw/gpio/imx_gpio.h"
23
*/
27
+#include "hw/sd/sdhci.h"
24
-static bool __attribute__((unused))
28
#include "exec/memory.h"
25
-sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
29
#include "target/arm/cpu.h"
26
- intptr_t reg_max, int esz, int msize)
30
27
+static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr,
31
@@ -XXX,XX +XXX,XX @@
28
+ uint64_t *vg, intptr_t reg_max,
32
#define FSL_IMX25_NUM_EPITS 2
29
+ int esz, int msize)
33
#define FSL_IMX25_NUM_I2CS 3
34
#define FSL_IMX25_NUM_GPIOS 4
35
+#define FSL_IMX25_NUM_ESDHCS 2
36
37
typedef struct FslIMX25State {
38
/*< private >*/
39
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
40
IMXRNGCState rngc;
41
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
42
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
43
+ SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
44
MemoryRegion rom[2];
45
MemoryRegion iram;
46
MemoryRegion iram_alias;
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
#define FSL_IMX25_GPIO3_SIZE 0x4000
49
#define FSL_IMX25_RNGC_ADDR 0x53FB0000
50
#define FSL_IMX25_RNGC_SIZE 0x4000
51
+#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
52
+#define FSL_IMX25_ESDHC1_SIZE 0x4000
53
+#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
54
+#define FSL_IMX25_ESDHC2_SIZE 0x4000
55
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
56
#define FSL_IMX25_GPIO1_SIZE 0x4000
57
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
58
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
59
#define FSL_IMX25_GPIO2_IRQ 51
60
#define FSL_IMX25_GPIO3_IRQ 16
61
#define FSL_IMX25_GPIO4_IRQ 23
62
+#define FSL_IMX25_ESDHC1_IRQ 9
63
+#define FSL_IMX25_ESDHC2_IRQ 8
64
65
#endif /* FSL_IMX25_H */
66
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/fsl-imx25.c
69
+++ b/hw/arm/fsl-imx25.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "hw/qdev-properties.h"
72
#include "chardev/char.h"
73
74
+#define IMX25_ESDHC_CAPABILITIES 0x07e20000
75
+
76
static void fsl_imx25_init(Object *obj)
77
{
30
{
78
FslIMX25State *s = FSL_IMX25(obj);
31
const int esize = 1 << esz;
79
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
32
const uint64_t pg_mask = pred_esz_masks[esz];
80
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
33
@@ -XXX,XX +XXX,XX @@ sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg,
81
TYPE_IMX_GPIO);
34
* Control the generation of page faults with @fault. Return false if
35
* there is no work to do, which can only happen with @fault == FAULT_NO.
36
*/
37
-static bool __attribute__((unused))
38
-sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env,
39
- target_ulong addr, MMUAccessType access_type,
40
- uintptr_t retaddr)
41
+static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
42
+ CPUARMState *env, target_ulong addr,
43
+ MMUAccessType access_type, uintptr_t retaddr)
44
{
45
int mmu_idx = cpu_mmu_index(env, false);
46
int mem_off = info->mem_off_first[0];
47
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
48
/*
49
* Common helper for all contiguous one-register predicated loads.
50
*/
51
-static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
52
- uint32_t desc, const uintptr_t retaddr,
53
- const int esz, const int msz,
54
- sve_ldst1_host_fn *host_fn,
55
- sve_ldst1_tlb_fn *tlb_fn)
56
+static inline QEMU_ALWAYS_INLINE
57
+void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
58
+ uint32_t desc, const uintptr_t retaddr,
59
+ const int esz, const int msz,
60
+ sve_ldst1_host_fn *host_fn,
61
+ sve_ldst1_tlb_fn *tlb_fn)
62
{
63
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
64
- const int mmu_idx = get_mmuidx(oi);
65
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
66
void *vd = &env->vfp.zregs[rd];
67
- const int diffsz = esz - msz;
68
const intptr_t reg_max = simd_oprsz(desc);
69
- const intptr_t mem_max = reg_max >> diffsz;
70
- ARMVectorReg scratch;
71
+ intptr_t reg_off, reg_last, mem_off;
72
+ SVEContLdSt info;
73
void *host;
74
- intptr_t split, reg_off, mem_off;
75
+ int flags;
76
77
- /* Find the first active element. */
78
- reg_off = find_next_active(vg, 0, reg_max, esz);
79
- if (unlikely(reg_off == reg_max)) {
80
+ /* Find the active elements. */
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
82
/* The entire predicate was false; no load occurs. */
83
memset(vd, 0, reg_max);
84
return;
82
}
85
}
83
+
86
- mem_off = reg_off >> diffsz;
84
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
87
85
+ sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
88
- /*
86
+ TYPE_IMX_USDHC);
89
- * If the (remaining) load is entirely within a single page, then:
90
- * For softmmu, and the tlb hits, then no faults will occur;
91
- * For user-only, either the first load will fault or none will.
92
- * We can thus perform the load directly to the destination and
93
- * Vd will be unmodified on any exception path.
94
- */
95
- split = max_for_page(addr, mem_off, mem_max);
96
- if (likely(split == mem_max)) {
97
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
98
- if (test_host_page(host)) {
99
- intptr_t i = reg_off;
100
- host -= mem_off;
101
- do {
102
- host_fn(vd, i, host + (i >> diffsz));
103
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
104
- } while (i < reg_max);
105
- /* After having taken any fault, zero leading inactive elements. */
106
- swap_memzero(vd, reg_off);
107
- return;
108
- }
109
- }
110
+ /* Probe the page(s). Exit with exception for any invalid page. */
111
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
112
113
- /*
114
- * Perform the predicated read into a temporary, thus ensuring
115
- * if the load of the last element faults, Vd is not modified.
116
- */
117
+ flags = info.page[0].flags | info.page[1].flags;
118
+ if (unlikely(flags != 0)) {
119
#ifdef CONFIG_USER_ONLY
120
- swap_memzero(&scratch, reg_off);
121
- host = g2h(addr);
122
- do {
123
- host_fn(&scratch, reg_off, host + (reg_off >> diffsz));
124
- reg_off += 1 << esz;
125
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
126
- } while (reg_off < reg_max);
127
+ g_assert_not_reached();
128
#else
129
- memset(&scratch, 0, reg_max);
130
- goto start;
131
- while (1) {
132
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
133
- if (reg_off >= reg_max) {
134
- break;
135
- }
136
- mem_off = reg_off >> diffsz;
137
- split = max_for_page(addr, mem_off, mem_max);
138
+ /*
139
+ * At least one page includes MMIO (or watchpoints).
140
+ * Any bus operation can fail with cpu_transaction_failed,
141
+ * which for ARM will raise SyncExternal. Perform the load
142
+ * into scratch memory to preserve register state until the end.
143
+ */
144
+ ARMVectorReg scratch;
145
146
- start:
147
- if (split - mem_off >= (1 << msz)) {
148
- /* At least one whole element on this page. */
149
- host = tlb_vaddr_to_host(env, addr + mem_off,
150
- MMU_DATA_LOAD, mmu_idx);
151
- if (host) {
152
- host -= mem_off;
153
- do {
154
- host_fn(&scratch, reg_off, host + mem_off);
155
- reg_off += 1 << esz;
156
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
157
- mem_off = reg_off >> diffsz;
158
- } while (split - mem_off >= (1 << msz));
159
- continue;
160
+ memset(&scratch, 0, reg_max);
161
+ mem_off = info.mem_off_first[0];
162
+ reg_off = info.reg_off_first[0];
163
+ reg_last = info.reg_off_last[1];
164
+ if (reg_last < 0) {
165
+ reg_last = info.reg_off_split;
166
+ if (reg_last < 0) {
167
+ reg_last = info.reg_off_last[0];
168
}
169
}
170
171
- /*
172
- * Perform one normal read. This may fault, longjmping out to the
173
- * main loop in order to raise an exception. It may succeed, and
174
- * as a side-effect load the TLB entry for the next round. Finally,
175
- * in the extremely unlikely case we're performing this operation
176
- * on I/O memory, it may succeed but not bring in the TLB entry.
177
- * But even then we have still made forward progress.
178
- */
179
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
180
- reg_off += 1 << esz;
181
- }
182
-#endif
183
+ do {
184
+ uint64_t pg = vg[reg_off >> 6];
185
+ do {
186
+ if ((pg >> (reg_off & 63)) & 1) {
187
+ tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
188
+ }
189
+ reg_off += 1 << esz;
190
+ mem_off += 1 << msz;
191
+ } while (reg_off & 63);
192
+ } while (reg_off <= reg_last);
193
194
- memcpy(vd, &scratch, reg_max);
195
+ memcpy(vd, &scratch, reg_max);
196
+ return;
197
+#endif
198
+ }
199
+
200
+ /* The entire operation is in RAM, on valid pages. */
201
+
202
+ memset(vd, 0, reg_max);
203
+ mem_off = info.mem_off_first[0];
204
+ reg_off = info.reg_off_first[0];
205
+ reg_last = info.reg_off_last[0];
206
+ host = info.page[0].host;
207
+
208
+ while (reg_off <= reg_last) {
209
+ uint64_t pg = vg[reg_off >> 6];
210
+ do {
211
+ if ((pg >> (reg_off & 63)) & 1) {
212
+ host_fn(vd, reg_off, host + mem_off);
213
+ }
214
+ reg_off += 1 << esz;
215
+ mem_off += 1 << msz;
216
+ } while (reg_off <= reg_last && (reg_off & 63));
217
+ }
218
+
219
+ /*
220
+ * Use the slow path to manage the cross-page misalignment.
221
+ * But we know this is RAM and cannot trap.
222
+ */
223
+ mem_off = info.mem_off_split;
224
+ if (unlikely(mem_off >= 0)) {
225
+ tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
226
+ }
227
+
228
+ mem_off = info.mem_off_first[1];
229
+ if (unlikely(mem_off >= 0)) {
230
+ reg_off = info.reg_off_first[1];
231
+ reg_last = info.reg_off_last[1];
232
+ host = info.page[1].host;
233
+
234
+ do {
235
+ uint64_t pg = vg[reg_off >> 6];
236
+ do {
237
+ if ((pg >> (reg_off & 63)) & 1) {
238
+ host_fn(vd, reg_off, host + mem_off);
239
+ }
240
+ reg_off += 1 << esz;
241
+ mem_off += 1 << msz;
242
+ } while (reg_off & 63);
243
+ } while (reg_off <= reg_last);
87
+ }
244
+ }
88
}
245
}
89
246
90
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
247
#define DO_LD1_1(NAME, ESZ) \
91
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
92
gpio_table[i].irq));
93
}
94
95
+ /* Initialize all SDHC */
96
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
97
+ static const struct {
98
+ hwaddr addr;
99
+ unsigned int irq;
100
+ } esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
101
+ { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
102
+ { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
103
+ };
104
+
105
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
106
+ &err);
107
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
108
+ "capareg", &err);
109
+ object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
110
+ if (err) {
111
+ error_propagate(errp, err);
112
+ return;
113
+ }
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->avic),
117
+ esdhc_table[i].irq));
118
+ }
119
+
120
/* initialize 2 x 16 KB ROM */
121
memory_region_init_rom(&s->rom[0], NULL,
122
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
123
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/imx25_pdk.c
126
+++ b/hw/arm/imx25_pdk.c
127
@@ -XXX,XX +XXX,XX @@
128
#include "qemu/osdep.h"
129
#include "qapi/error.h"
130
#include "cpu.h"
131
+#include "hw/qdev-properties.h"
132
#include "hw/arm/fsl-imx25.h"
133
#include "hw/boards.h"
134
#include "qemu/error-report.h"
135
@@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine)
136
imx25_pdk_binfo.board_id = 1771,
137
imx25_pdk_binfo.nb_cpus = 1;
138
139
+ for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
140
+ BusState *bus;
141
+ DeviceState *carddev;
142
+ DriveInfo *di;
143
+ BlockBackend *blk;
144
+
145
+ di = drive_get_next(IF_SD);
146
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
147
+ bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
148
+ carddev = qdev_create(bus, TYPE_SD_CARD);
149
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
150
+ object_property_set_bool(OBJECT(carddev), true,
151
+ "realized", &error_fatal);
152
+ }
153
+
154
/*
155
* We test explicitly for qtest here as it is not done (yet?) in
156
* arm_load_kernel(). Without this the "make check" command would
157
--
248
--
158
2.20.1
249
2.20.1
159
250
160
251
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
3
Handle all of the watchpoints for active elements all at once,
4
based embedded computer with mainline support in both U-Boot
4
before we've modified the vector register. This removes the
5
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
5
TLB_WATCHPOINT bit from page[].flags, which means that we can
6
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
6
use the normal fast path via RAM.
7
various other I/O. This commit add support for the Xunlong
8
Orange Pi PC machine.
9
7
10
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20200508154359.7494-13-richard.henderson@linaro.org
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Acked-by: Igor Mammedov <imammedo@redhat.com>
16
Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
12
---
19
hw/arm/Makefile.objs | 2 +-
13
target/arm/sve_helper.c | 72 ++++++++++++++++++++++++++++++++++++++++-
20
hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
14
1 file changed, 71 insertions(+), 1 deletion(-)
21
MAINTAINERS | 1 +
22
3 files changed, 94 insertions(+), 1 deletion(-)
23
create mode 100644 hw/arm/orangepi.c
24
15
25
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
26
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/Makefile.objs
18
--- a/target/arm/sve_helper.c
28
+++ b/hw/arm/Makefile.objs
19
+++ b/target/arm/sve_helper.c
29
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
20
@@ -XXX,XX +XXX,XX @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
30
obj-$(CONFIG_OMAP) += omap1.o omap2.o
21
return have_work;
31
obj-$(CONFIG_STRONGARM) += strongarm.o
22
}
32
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
23
33
-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
24
+static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o
25
+ uint64_t *vg, target_ulong addr,
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
26
+ int esize, int msize, int wp_access,
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
27
+ uintptr_t retaddr)
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
28
+{
38
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
29
+#ifndef CONFIG_USER_ONLY
39
new file mode 100644
30
+ intptr_t mem_off, reg_off, reg_last;
40
index XXXXXXX..XXXXXXX
31
+ int flags0 = info->page[0].flags;
41
--- /dev/null
32
+ int flags1 = info->page[1].flags;
42
+++ b/hw/arm/orangepi.c
43
@@ -XXX,XX +XXX,XX @@
44
+/*
45
+ * Orange Pi emulation
46
+ *
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
48
+ *
49
+ * This program is free software: you can redistribute it and/or modify
50
+ * it under the terms of the GNU General Public License as published by
51
+ * the Free Software Foundation, either version 2 of the License, or
52
+ * (at your option) any later version.
53
+ *
54
+ * This program is distributed in the hope that it will be useful,
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57
+ * GNU General Public License for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
62
+
33
+
63
+#include "qemu/osdep.h"
34
+ if (likely(!((flags0 | flags1) & TLB_WATCHPOINT))) {
64
+#include "qemu/units.h"
35
+ return;
65
+#include "exec/address-spaces.h"
66
+#include "qapi/error.h"
67
+#include "cpu.h"
68
+#include "hw/sysbus.h"
69
+#include "hw/boards.h"
70
+#include "hw/qdev-properties.h"
71
+#include "hw/arm/allwinner-h3.h"
72
+#include "sysemu/sysemu.h"
73
+
74
+static struct arm_boot_info orangepi_binfo = {
75
+ .nb_cpus = AW_H3_NUM_CPUS,
76
+};
77
+
78
+static void orangepi_init(MachineState *machine)
79
+{
80
+ AwH3State *h3;
81
+
82
+ /* BIOS is not supported by this board */
83
+ if (bios_name) {
84
+ error_report("BIOS not supported for this machine");
85
+ exit(1);
86
+ }
36
+ }
87
+
37
+
88
+ /* This board has fixed size RAM */
38
+ /* Indicate that watchpoints are handled. */
89
+ if (machine->ram_size != 1 * GiB) {
39
+ info->page[0].flags = flags0 & ~TLB_WATCHPOINT;
90
+ error_report("This machine can only be used with 1GiB of RAM");
40
+ info->page[1].flags = flags1 & ~TLB_WATCHPOINT;
91
+ exit(1);
41
+
42
+ if (flags0 & TLB_WATCHPOINT) {
43
+ mem_off = info->mem_off_first[0];
44
+ reg_off = info->reg_off_first[0];
45
+ reg_last = info->reg_off_last[0];
46
+
47
+ while (reg_off <= reg_last) {
48
+ uint64_t pg = vg[reg_off >> 6];
49
+ do {
50
+ if ((pg >> (reg_off & 63)) & 1) {
51
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
52
+ msize, info->page[0].attrs,
53
+ wp_access, retaddr);
54
+ }
55
+ reg_off += esize;
56
+ mem_off += msize;
57
+ } while (reg_off <= reg_last && (reg_off & 63));
58
+ }
92
+ }
59
+ }
93
+
60
+
94
+ /* Only allow Cortex-A7 for this board */
61
+ mem_off = info->mem_off_split;
95
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
62
+ if (mem_off >= 0) {
96
+ error_report("This board can only be used with cortex-a7 CPU");
63
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off, msize,
97
+ exit(1);
64
+ info->page[0].attrs, wp_access, retaddr);
98
+ }
65
+ }
99
+
66
+
100
+ h3 = AW_H3(object_new(TYPE_AW_H3));
67
+ mem_off = info->mem_off_first[1];
101
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(h3),
68
+ if ((flags1 & TLB_WATCHPOINT) && mem_off >= 0) {
102
+ &error_abort);
69
+ reg_off = info->reg_off_first[1];
103
+ object_unref(OBJECT(h3));
70
+ reg_last = info->reg_off_last[1];
104
+
71
+
105
+ /* Setup timer properties */
72
+ do {
106
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
73
+ uint64_t pg = vg[reg_off >> 6];
107
+ &error_abort);
74
+ do {
108
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
75
+ if ((pg >> (reg_off & 63)) & 1) {
109
+ &error_abort);
76
+ cpu_check_watchpoint(env_cpu(env), addr + mem_off,
110
+
77
+ msize, info->page[1].attrs,
111
+ /* Mark H3 object realized */
78
+ wp_access, retaddr);
112
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
79
+ }
113
+
80
+ reg_off += esize;
114
+ /* SDRAM */
81
+ mem_off += msize;
115
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
82
+ } while (reg_off & 63);
116
+ machine->ram);
83
+ } while (reg_off <= reg_last);
117
+
84
+ }
118
+ orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
85
+#endif
119
+ orangepi_binfo.ram_size = machine->ram_size;
120
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
121
+}
86
+}
122
+
87
+
123
+static void orangepi_machine_init(MachineClass *mc)
88
/*
124
+{
89
* The result of tlb_vaddr_to_host for user-only is just g2h(x),
125
+ mc->desc = "Orange Pi PC";
90
* which is always non-null. Elide the useless test.
126
+ mc->init = orangepi_init;
91
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
127
+ mc->min_cpus = AW_H3_NUM_CPUS;
92
/* Probe the page(s). Exit with exception for any invalid page. */
128
+ mc->max_cpus = AW_H3_NUM_CPUS;
93
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
129
+ mc->default_cpus = AW_H3_NUM_CPUS;
94
130
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
95
+ /* Handle watchpoints for all active elements. */
131
+ mc->default_ram_size = 1 * GiB;
96
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
132
+ mc->default_ram_id = "orangepi.ram";
97
+ BP_MEM_READ, retaddr);
133
+}
134
+
98
+
135
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
99
+ /* TODO: MTE check. */
136
diff --git a/MAINTAINERS b/MAINTAINERS
100
+
137
index XXXXXXX..XXXXXXX 100644
101
flags = info.page[0].flags | info.page[1].flags;
138
--- a/MAINTAINERS
102
if (unlikely(flags != 0)) {
139
+++ b/MAINTAINERS
103
#ifdef CONFIG_USER_ONLY
140
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
104
g_assert_not_reached();
141
S: Maintained
105
#else
142
F: hw/*/allwinner-h3*
106
/*
143
F: include/hw/*/allwinner-h3*
107
- * At least one page includes MMIO (or watchpoints).
144
+F: hw/arm/orangepi.c
108
+ * At least one page includes MMIO.
145
109
* Any bus operation can fail with cpu_transaction_failed,
146
ARM PrimeCell and CMSDK devices
110
* which for ARM will raise SyncExternal. Perform the load
147
M: Peter Maydell <peter.maydell@linaro.org>
111
* into scratch memory to preserve register state until the end.
148
--
112
--
149
2.20.1
113
2.20.1
150
114
151
115
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
A real Allwinner H3 SoC contains a Boot ROM which is the
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
first code that runs right after the SoC is powered on.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
The Boot ROM is responsible for loading user code (e.g. a bootloader)
5
Message-id: 20200508154359.7494-14-richard.henderson@linaro.org
6
from any of the supported external devices and writing the downloaded
7
code to internal SRAM. After loading the SoC begins executing the code
8
written to SRAM.
9
10
This commits adds emulation of the Boot ROM firmware setup functionality
11
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
12
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
13
sizes larger than 32KiB. For reference, this behaviour is documented
14
by the Linux Sunxi project wiki at:
15
16
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
7
---
23
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
8
target/arm/sve_helper.c | 223 ++++++++++++++--------------------------
24
hw/arm/allwinner-h3.c | 17 +++++++++++++++++
9
1 file changed, 79 insertions(+), 144 deletions(-)
25
hw/arm/orangepi.c | 5 +++++
26
3 files changed, 43 insertions(+)
27
10
28
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
29
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-h3.h
13
--- a/target/arm/sve_helper.c
31
+++ b/include/hw/arm/allwinner-h3.h
14
+++ b/target/arm/sve_helper.c
32
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static inline bool test_host_page(void *host)
33
#include "hw/sd/allwinner-sdhost.h"
16
}
34
#include "hw/net/allwinner-sun8i-emac.h"
17
35
#include "target/arm/cpu.h"
18
/*
36
+#include "sysemu/block-backend.h"
19
- * Common helper for all contiguous one-register predicated loads.
37
20
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
38
/**
21
*/
39
* Allwinner H3 device list
22
static inline QEMU_ALWAYS_INLINE
40
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
23
-void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
41
MemoryRegion sram_c;
24
+void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
42
} AwH3State;
25
uint32_t desc, const uintptr_t retaddr,
43
26
- const int esz, const int msz,
44
+/**
27
+ const int esz, const int msz, const int N,
45
+ * Emulate Boot ROM firmware setup functionality.
28
sve_ldst1_host_fn *host_fn,
46
+ *
29
sve_ldst1_tlb_fn *tlb_fn)
47
+ * A real Allwinner H3 SoC contains a Boot ROM
30
{
48
+ * which is the first code that runs right after
31
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
49
+ * the SoC is powered on. The Boot ROM is responsible
32
- void *vd = &env->vfp.zregs[rd];
50
+ * for loading user code (e.g. a bootloader) from any
33
const intptr_t reg_max = simd_oprsz(desc);
51
+ * of the supported external devices and writing the
34
intptr_t reg_off, reg_last, mem_off;
52
+ * downloaded code to internal SRAM. After loading the SoC
35
SVEContLdSt info;
53
+ * begins executing the code written to SRAM.
36
void *host;
54
+ *
37
- int flags;
55
+ * This function emulates the Boot ROM by copying 32 KiB
38
+ int flags, i;
56
+ * of data from the given block device and writes it to
39
57
+ * the start of the first internal SRAM memory.
40
/* Find the active elements. */
58
+ *
41
- if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
59
+ * @s: Allwinner H3 state object pointer
42
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
60
+ * @blk: Block backend device object pointer
43
/* The entire predicate was false; no load occurs. */
61
+ */
44
- memset(vd, 0, reg_max);
62
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
45
+ for (i = 0; i < N; ++i) {
63
+
46
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
64
#endif /* HW_ARM_ALLWINNER_H3_H */
47
+ }
65
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
48
return;
66
index XXXXXXX..XXXXXXX 100644
49
}
67
--- a/hw/arm/allwinner-h3.c
50
68
+++ b/hw/arm/allwinner-h3.c
51
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
69
@@ -XXX,XX +XXX,XX @@
52
sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, retaddr);
70
#include "hw/char/serial.h"
53
71
#include "hw/misc/unimp.h"
54
/* Handle watchpoints for all active elements. */
72
#include "hw/usb/hcd-ehci.h"
55
- sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, 1 << msz,
73
+#include "hw/loader.h"
56
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
74
#include "sysemu/sysemu.h"
57
BP_MEM_READ, retaddr);
75
#include "hw/arm/allwinner-h3.h"
58
76
59
/* TODO: MTE check. */
77
@@ -XXX,XX +XXX,XX @@ enum {
60
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
78
AW_H3_GIC_NUM_SPI = 128
61
* which for ARM will raise SyncExternal. Perform the load
79
};
62
* into scratch memory to preserve register state until the end.
80
63
*/
81
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
64
- ARMVectorReg scratch;
82
+{
65
+ ARMVectorReg scratch[4] = { };
83
+ const int64_t rom_size = 32 * KiB;
66
84
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
67
- memset(&scratch, 0, reg_max);
85
+
68
mem_off = info.mem_off_first[0];
86
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
69
reg_off = info.reg_off_first[0];
87
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
70
reg_last = info.reg_off_last[1];
88
+ __func__);
71
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
89
+ return;
72
uint64_t pg = vg[reg_off >> 6];
73
do {
74
if ((pg >> (reg_off & 63)) & 1) {
75
- tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
76
+ for (i = 0; i < N; ++i) {
77
+ tlb_fn(env, &scratch[i], reg_off,
78
+ addr + mem_off + (i << msz), retaddr);
79
+ }
80
}
81
reg_off += 1 << esz;
82
- mem_off += 1 << msz;
83
+ mem_off += N << msz;
84
} while (reg_off & 63);
85
} while (reg_off <= reg_last);
86
87
- memcpy(vd, &scratch, reg_max);
88
+ for (i = 0; i < N; ++i) {
89
+ memcpy(&env->vfp.zregs[(rd + i) & 31], &scratch[i], reg_max);
90
+ }
91
return;
92
#endif
93
}
94
95
/* The entire operation is in RAM, on valid pages. */
96
97
- memset(vd, 0, reg_max);
98
+ for (i = 0; i < N; ++i) {
99
+ memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max);
90
+ }
100
+ }
91
+
101
+
92
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
102
mem_off = info.mem_off_first[0];
93
+ rom_size, s->memmap[AW_H3_SRAM_A1],
103
reg_off = info.reg_off_first[0];
94
+ NULL, NULL, NULL, NULL, false);
104
reg_last = info.reg_off_last[0];
95
+}
105
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
96
+
106
uint64_t pg = vg[reg_off >> 6];
97
static void allwinner_h3_init(Object *obj)
107
do {
98
{
108
if ((pg >> (reg_off & 63)) & 1) {
99
AwH3State *s = AW_H3(obj);
109
- host_fn(vd, reg_off, host + mem_off);
100
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
110
+ for (i = 0; i < N; ++i) {
101
index XXXXXXX..XXXXXXX 100644
111
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
102
--- a/hw/arm/orangepi.c
112
+ host + mem_off + (i << msz));
103
+++ b/hw/arm/orangepi.c
113
+ }
104
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
114
}
105
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
115
reg_off += 1 << esz;
106
machine->ram);
116
- mem_off += 1 << msz;
107
117
+ mem_off += N << msz;
108
+ /* Load target kernel or start using BootROM */
118
} while (reg_off <= reg_last && (reg_off & 63));
109
+ if (!machine->kernel_filename && blk_is_available(blk)) {
119
}
110
+ /* Use Boot ROM to copy data from SD card to SRAM */
120
111
+ allwinner_h3_bootrom_setup(h3, blk);
121
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
112
+ }
122
*/
113
orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
123
mem_off = info.mem_off_split;
114
orangepi_binfo.ram_size = machine->ram_size;
124
if (unlikely(mem_off >= 0)) {
115
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
125
- tlb_fn(env, vd, info.reg_off_split, addr + mem_off, retaddr);
126
+ reg_off = info.reg_off_split;
127
+ for (i = 0; i < N; ++i) {
128
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
129
+ addr + mem_off + (i << msz), retaddr);
130
+ }
131
}
132
133
mem_off = info.mem_off_first[1];
134
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
135
uint64_t pg = vg[reg_off >> 6];
136
do {
137
if ((pg >> (reg_off & 63)) & 1) {
138
- host_fn(vd, reg_off, host + mem_off);
139
+ for (i = 0; i < N; ++i) {
140
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
141
+ host + mem_off + (i << msz));
142
+ }
143
}
144
reg_off += 1 << esz;
145
- mem_off += 1 << msz;
146
+ mem_off += N << msz;
147
} while (reg_off & 63);
148
} while (reg_off <= reg_last);
149
}
150
@@ -XXX,XX +XXX,XX @@ void sve_ld1_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
151
void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
152
target_ulong addr, uint32_t desc) \
153
{ \
154
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
155
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, \
156
sve_##NAME##_host, sve_##NAME##_tlb); \
157
}
158
159
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \
160
void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \
161
target_ulong addr, uint32_t desc) \
162
{ \
163
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
164
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
165
sve_##NAME##_le_host, sve_##NAME##_le_tlb); \
166
} \
167
void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \
168
target_ulong addr, uint32_t desc) \
169
{ \
170
- sve_ld1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
171
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \
172
sve_##NAME##_be_host, sve_##NAME##_be_tlb); \
173
}
174
175
-DO_LD1_1(ld1bb, 0)
176
-DO_LD1_1(ld1bhu, 1)
177
-DO_LD1_1(ld1bhs, 1)
178
-DO_LD1_1(ld1bsu, 2)
179
-DO_LD1_1(ld1bss, 2)
180
-DO_LD1_1(ld1bdu, 3)
181
-DO_LD1_1(ld1bds, 3)
182
+DO_LD1_1(ld1bb, MO_8)
183
+DO_LD1_1(ld1bhu, MO_16)
184
+DO_LD1_1(ld1bhs, MO_16)
185
+DO_LD1_1(ld1bsu, MO_32)
186
+DO_LD1_1(ld1bss, MO_32)
187
+DO_LD1_1(ld1bdu, MO_64)
188
+DO_LD1_1(ld1bds, MO_64)
189
190
-DO_LD1_2(ld1hh, 1, 1)
191
-DO_LD1_2(ld1hsu, 2, 1)
192
-DO_LD1_2(ld1hss, 2, 1)
193
-DO_LD1_2(ld1hdu, 3, 1)
194
-DO_LD1_2(ld1hds, 3, 1)
195
+DO_LD1_2(ld1hh, MO_16, MO_16)
196
+DO_LD1_2(ld1hsu, MO_32, MO_16)
197
+DO_LD1_2(ld1hss, MO_32, MO_16)
198
+DO_LD1_2(ld1hdu, MO_64, MO_16)
199
+DO_LD1_2(ld1hds, MO_64, MO_16)
200
201
-DO_LD1_2(ld1ss, 2, 2)
202
-DO_LD1_2(ld1sdu, 3, 2)
203
-DO_LD1_2(ld1sds, 3, 2)
204
+DO_LD1_2(ld1ss, MO_32, MO_32)
205
+DO_LD1_2(ld1sdu, MO_64, MO_32)
206
+DO_LD1_2(ld1sds, MO_64, MO_32)
207
208
-DO_LD1_2(ld1dd, 3, 3)
209
+DO_LD1_2(ld1dd, MO_64, MO_64)
210
211
#undef DO_LD1_1
212
#undef DO_LD1_2
213
214
-/*
215
- * Common helpers for all contiguous 2,3,4-register predicated loads.
216
- */
217
-static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
218
- uint32_t desc, int size, uintptr_t ra,
219
- sve_ldst1_tlb_fn *tlb_fn)
220
-{
221
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
222
- intptr_t i, oprsz = simd_oprsz(desc);
223
- ARMVectorReg scratch[2] = { };
224
-
225
- for (i = 0; i < oprsz; ) {
226
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
227
- do {
228
- if (pg & 1) {
229
- tlb_fn(env, &scratch[0], i, addr, ra);
230
- tlb_fn(env, &scratch[1], i, addr + size, ra);
231
- }
232
- i += size, pg >>= size;
233
- addr += 2 * size;
234
- } while (i & 15);
235
- }
236
-
237
- /* Wait until all exceptions have been raised to write back. */
238
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
239
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
240
-}
241
-
242
-static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
243
- uint32_t desc, int size, uintptr_t ra,
244
- sve_ldst1_tlb_fn *tlb_fn)
245
-{
246
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
247
- intptr_t i, oprsz = simd_oprsz(desc);
248
- ARMVectorReg scratch[3] = { };
249
-
250
- for (i = 0; i < oprsz; ) {
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
252
- do {
253
- if (pg & 1) {
254
- tlb_fn(env, &scratch[0], i, addr, ra);
255
- tlb_fn(env, &scratch[1], i, addr + size, ra);
256
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
257
- }
258
- i += size, pg >>= size;
259
- addr += 3 * size;
260
- } while (i & 15);
261
- }
262
-
263
- /* Wait until all exceptions have been raised to write back. */
264
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
265
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
266
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
267
-}
268
-
269
-static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
270
- uint32_t desc, int size, uintptr_t ra,
271
- sve_ldst1_tlb_fn *tlb_fn)
272
-{
273
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
274
- intptr_t i, oprsz = simd_oprsz(desc);
275
- ARMVectorReg scratch[4] = { };
276
-
277
- for (i = 0; i < oprsz; ) {
278
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
279
- do {
280
- if (pg & 1) {
281
- tlb_fn(env, &scratch[0], i, addr, ra);
282
- tlb_fn(env, &scratch[1], i, addr + size, ra);
283
- tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
284
- tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
285
- }
286
- i += size, pg >>= size;
287
- addr += 4 * size;
288
- } while (i & 15);
289
- }
290
-
291
- /* Wait until all exceptions have been raised to write back. */
292
- memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
293
- memcpy(&env->vfp.zregs[(rd + 1) & 31], &scratch[1], oprsz);
294
- memcpy(&env->vfp.zregs[(rd + 2) & 31], &scratch[2], oprsz);
295
- memcpy(&env->vfp.zregs[(rd + 3) & 31], &scratch[3], oprsz);
296
-}
297
-
298
#define DO_LDN_1(N) \
299
-void QEMU_FLATTEN HELPER(sve_ld##N##bb_r) \
300
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
301
-{ \
302
- sve_ld##N##_r(env, vg, addr, desc, 1, GETPC(), sve_ld1bb_tlb); \
303
+void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \
304
+ target_ulong addr, uint32_t desc) \
305
+{ \
306
+ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, \
307
+ sve_ld1bb_host, sve_ld1bb_tlb); \
308
}
309
310
-#define DO_LDN_2(N, SUFF, SIZE) \
311
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_le_r) \
312
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
313
+#define DO_LDN_2(N, SUFF, ESZ) \
314
+void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \
315
+ target_ulong addr, uint32_t desc) \
316
{ \
317
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
318
- sve_ld1##SUFF##_le_tlb); \
319
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
320
+ sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \
321
} \
322
-void QEMU_FLATTEN HELPER(sve_ld##N##SUFF##_be_r) \
323
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
324
+void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \
325
+ target_ulong addr, uint32_t desc) \
326
{ \
327
- sve_ld##N##_r(env, vg, addr, desc, SIZE, GETPC(), \
328
- sve_ld1##SUFF##_be_tlb); \
329
+ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, \
330
+ sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \
331
}
332
333
DO_LDN_1(2)
334
DO_LDN_1(3)
335
DO_LDN_1(4)
336
337
-DO_LDN_2(2, hh, 2)
338
-DO_LDN_2(3, hh, 2)
339
-DO_LDN_2(4, hh, 2)
340
+DO_LDN_2(2, hh, MO_16)
341
+DO_LDN_2(3, hh, MO_16)
342
+DO_LDN_2(4, hh, MO_16)
343
344
-DO_LDN_2(2, ss, 4)
345
-DO_LDN_2(3, ss, 4)
346
-DO_LDN_2(4, ss, 4)
347
+DO_LDN_2(2, ss, MO_32)
348
+DO_LDN_2(3, ss, MO_32)
349
+DO_LDN_2(4, ss, MO_32)
350
351
-DO_LDN_2(2, dd, 8)
352
-DO_LDN_2(3, dd, 8)
353
-DO_LDN_2(4, dd, 8)
354
+DO_LDN_2(2, dd, MO_64)
355
+DO_LDN_2(3, dd, MO_64)
356
+DO_LDN_2(4, dd, MO_64)
357
358
#undef DO_LDN_1
359
#undef DO_LDN_2
116
--
360
--
117
2.20.1
361
2.20.1
118
362
119
363
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner H3 System on Chip has an System Control
3
With sve_cont_ldst_pages, the differences between first-fault and no-fault
4
module that provides system wide generic controls and
4
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
5
device information. This commit adds support for the
5
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
6
Allwinner H3 System Control module.
6
does not actually fire.
7
7
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20200508154359.7494-15-richard.henderson@linaro.org
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
hw/misc/Makefile.objs | 1 +
13
target/arm/sve_helper.c | 346 +++++++++++++++++++---------------------
16
include/hw/arm/allwinner-h3.h | 3 +
14
1 file changed, 162 insertions(+), 184 deletions(-)
17
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
18
hw/arm/allwinner-h3.c | 9 +-
19
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
20
5 files changed, 219 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
22
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
23
15
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
16
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
25
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
18
--- a/target/arm/sve_helper.c
27
+++ b/hw/misc/Makefile.objs
19
+++ b/target/arm/sve_helper.c
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
20
@@ -XXX,XX +XXX,XX @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off,
29
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
21
return reg_off;
30
22
}
31
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
23
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
24
-/*
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
25
- * Return the maximum offset <= @mem_max which is still within the page
34
common-obj-$(CONFIG_NSERIES) += cbus.o
26
- * referenced by @base + @mem_off.
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
27
- */
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
28
-static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
37
index XXXXXXX..XXXXXXX 100644
29
- intptr_t mem_max)
38
--- a/include/hw/arm/allwinner-h3.h
30
-{
39
+++ b/include/hw/arm/allwinner-h3.h
31
- target_ulong addr = base + mem_off;
40
@@ -XXX,XX +XXX,XX @@
32
- intptr_t split = -(intptr_t)(addr | TARGET_PAGE_MASK);
41
#include "hw/timer/allwinner-a10-pit.h"
33
- return MIN(split, mem_max - mem_off) + mem_off;
42
#include "hw/intc/arm_gic.h"
34
-}
43
#include "hw/misc/allwinner-h3-ccu.h"
35
-
44
+#include "hw/misc/allwinner-h3-sysctrl.h"
36
/*
45
#include "target/arm/cpu.h"
37
* Resolve the guest virtual address to info->host and info->flags.
46
38
* If @nofault, return false if the page is invalid, otherwise
47
/**
39
@@ -XXX,XX +XXX,XX @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env,
48
@@ -XXX,XX +XXX,XX @@ enum {
40
#endif
49
AW_H3_SRAM_A1,
41
}
50
AW_H3_SRAM_A2,
42
51
AW_H3_SRAM_C,
43
-/*
52
+ AW_H3_SYSCTRL,
44
- * The result of tlb_vaddr_to_host for user-only is just g2h(x),
53
AW_H3_EHCI0,
45
- * which is always non-null. Elide the useless test.
54
AW_H3_OHCI0,
46
- */
55
AW_H3_EHCI1,
47
-static inline bool test_host_page(void *host)
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
48
-{
57
const hwaddr *memmap;
49
-#ifdef CONFIG_USER_ONLY
58
AwA10PITState timer;
50
- return true;
59
AwH3ClockCtlState ccu;
51
-#else
60
+ AwH3SysCtrlState sysctrl;
52
- return likely(host != NULL);
61
GICState gic;
53
-#endif
62
MemoryRegion sram_a1;
54
-}
63
MemoryRegion sram_a2;
55
-
64
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h
56
/*
65
new file mode 100644
57
* Common helper for all contiguous 1,2,3,4-register predicated stores.
66
index XXXXXXX..XXXXXXX
58
*/
67
--- /dev/null
59
@@ -XXX,XX +XXX,XX @@ static void record_fault(CPUARMState *env, uintptr_t i, uintptr_t oprsz)
68
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
60
}
69
@@ -XXX,XX +XXX,XX @@
61
70
+/*
62
/*
71
+ * Allwinner H3 System Control emulation
63
- * Common helper for all contiguous first-fault loads.
72
+ *
64
+ * Common helper for all contiguous no-fault and first-fault loads.
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
65
*/
74
+ *
66
-static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
75
+ * This program is free software: you can redistribute it and/or modify
67
- uint32_t desc, const uintptr_t retaddr,
76
+ * it under the terms of the GNU General Public License as published by
68
- const int esz, const int msz,
77
+ * the Free Software Foundation, either version 2 of the License, or
69
- sve_ldst1_host_fn *host_fn,
78
+ * (at your option) any later version.
70
- sve_ldst1_tlb_fn *tlb_fn)
79
+ *
71
+static inline QEMU_ALWAYS_INLINE
80
+ * This program is distributed in the hope that it will be useful,
72
+void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
73
+ uint32_t desc, const uintptr_t retaddr,
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
74
+ const int esz, const int msz, const SVEContFault fault,
83
+ * GNU General Public License for more details.
75
+ sve_ldst1_host_fn *host_fn,
84
+ *
76
+ sve_ldst1_tlb_fn *tlb_fn)
85
+ * You should have received a copy of the GNU General Public License
77
{
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
78
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
87
+ */
79
- const int mmu_idx = get_mmuidx(oi);
88
+
80
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
89
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
81
void *vd = &env->vfp.zregs[rd];
90
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
82
- const int diffsz = esz - msz;
91
+
83
const intptr_t reg_max = simd_oprsz(desc);
92
+#include "qom/object.h"
84
- const intptr_t mem_max = reg_max >> diffsz;
93
+#include "hw/sysbus.h"
85
- intptr_t split, reg_off, mem_off, i;
94
+
86
+ intptr_t reg_off, mem_off, reg_last;
95
+/**
87
+ SVEContLdSt info;
96
+ * @name Constants
88
+ int flags;
97
+ * @{
89
void *host;
98
+ */
90
99
+
91
- /* Skip to the first active element. */
100
+/** Highest register address used by System Control device */
92
- reg_off = find_next_active(vg, 0, reg_max, esz);
101
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
93
- if (unlikely(reg_off == reg_max)) {
102
+
94
+ /* Find the active elements. */
103
+/** Total number of known registers */
95
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, 1 << msz)) {
104
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
96
/* The entire predicate was false; no load occurs. */
105
+ sizeof(uint32_t)) + 1)
97
memset(vd, 0, reg_max);
106
+
98
return;
107
+/** @} */
99
}
108
+
100
- mem_off = reg_off >> diffsz;
109
+/**
101
+ reg_off = info.reg_off_first[0];
110
+ * @name Object model
102
111
+ * @{
103
- /*
112
+ */
104
- * If the (remaining) load is entirely within a single page, then:
113
+
105
- * For softmmu, and the tlb hits, then no faults will occur;
114
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
106
- * For user-only, either the first load will fault or none will.
115
+#define AW_H3_SYSCTRL(obj) \
107
- * We can thus perform the load directly to the destination and
116
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
108
- * Vd will be unmodified on any exception path.
117
+
109
- */
118
+/** @} */
110
- split = max_for_page(addr, mem_off, mem_max);
119
+
111
- if (likely(split == mem_max)) {
120
+/**
112
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
121
+ * Allwinner H3 System Control object instance state
113
- if (test_host_page(host)) {
122
+ */
114
- i = reg_off;
123
+typedef struct AwH3SysCtrlState {
115
- host -= mem_off;
124
+ /*< private >*/
116
- do {
125
+ SysBusDevice parent_obj;
117
- host_fn(vd, i, host + (i >> diffsz));
126
+ /*< public >*/
118
- i = find_next_active(vg, i + (1 << esz), reg_max, esz);
127
+
119
- } while (i < reg_max);
128
+ /** Maps I/O registers in physical memory */
120
- /* After any fault, zero any leading inactive elements. */
129
+ MemoryRegion iomem;
121
+ /* Probe the page(s). */
130
+
122
+ if (!sve_cont_ldst_pages(&info, fault, env, addr, MMU_DATA_LOAD, retaddr)) {
131
+ /** Array of hardware registers */
123
+ /* Fault on first element. */
132
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
124
+ tcg_debug_assert(fault == FAULT_NO);
133
+
125
+ memset(vd, 0, reg_max);
134
+} AwH3SysCtrlState;
126
+ goto do_fault;
135
+
136
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
137
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/hw/arm/allwinner-h3.c
140
+++ b/hw/arm/allwinner-h3.c
141
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
142
[AW_H3_SRAM_A1] = 0x00000000,
143
[AW_H3_SRAM_A2] = 0x00044000,
144
[AW_H3_SRAM_C] = 0x00010000,
145
+ [AW_H3_SYSCTRL] = 0x01c00000,
146
[AW_H3_EHCI0] = 0x01c1a000,
147
[AW_H3_OHCI0] = 0x01c1a400,
148
[AW_H3_EHCI1] = 0x01c1b000,
149
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
150
} unimplemented[] = {
151
{ "d-engine", 0x01000000, 4 * MiB },
152
{ "d-inter", 0x01400000, 128 * KiB },
153
- { "syscon", 0x01c00000, 4 * KiB },
154
{ "dma", 0x01c02000, 4 * KiB },
155
{ "nfdc", 0x01c03000, 4 * KiB },
156
{ "ts", 0x01c06000, 4 * KiB },
157
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
158
159
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
160
TYPE_AW_H3_CCU);
161
+
162
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
163
+ TYPE_AW_H3_SYSCTRL);
164
}
165
166
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
168
qdev_init_nofail(DEVICE(&s->ccu));
169
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
170
171
+ /* System Control */
172
+ qdev_init_nofail(DEVICE(&s->sysctrl));
173
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
174
+
175
/* Universal Serial Bus */
176
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
177
qdev_get_gpio_in(DEVICE(&s->gic),
178
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
179
new file mode 100644
180
index XXXXXXX..XXXXXXX
181
--- /dev/null
182
+++ b/hw/misc/allwinner-h3-sysctrl.c
183
@@ -XXX,XX +XXX,XX @@
184
+/*
185
+ * Allwinner H3 System Control emulation
186
+ *
187
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
188
+ *
189
+ * This program is free software: you can redistribute it and/or modify
190
+ * it under the terms of the GNU General Public License as published by
191
+ * the Free Software Foundation, either version 2 of the License, or
192
+ * (at your option) any later version.
193
+ *
194
+ * This program is distributed in the hope that it will be useful,
195
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
196
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
197
+ * GNU General Public License for more details.
198
+ *
199
+ * You should have received a copy of the GNU General Public License
200
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
201
+ */
202
+
203
+#include "qemu/osdep.h"
204
+#include "qemu/units.h"
205
+#include "hw/sysbus.h"
206
+#include "migration/vmstate.h"
207
+#include "qemu/log.h"
208
+#include "qemu/module.h"
209
+#include "hw/misc/allwinner-h3-sysctrl.h"
210
+
211
+/* System Control register offsets */
212
+enum {
213
+ REG_VER = 0x24, /* Version */
214
+ REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
215
+};
216
+
217
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
218
+
219
+/* System Control register reset values */
220
+enum {
221
+ REG_VER_RST = 0x0,
222
+ REG_EMAC_PHY_CLK_RST = 0x58000,
223
+};
224
+
225
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
226
+ unsigned size)
227
+{
228
+ const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
229
+ const uint32_t idx = REG_INDEX(offset);
230
+
231
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
232
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
233
+ __func__, (uint32_t)offset);
234
+ return 0;
235
+ }
127
+ }
236
+
128
+
237
+ return s->regs[idx];
129
+ mem_off = info.mem_off_first[0];
238
+}
130
+ flags = info.page[0].flags;
239
+
131
+
240
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
132
+ if (fault == FAULT_FIRST) {
241
+ uint64_t val, unsigned size)
133
+ /*
242
+{
134
+ * Special handling of the first active element,
243
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
135
+ * if it crosses a page boundary or is MMIO.
244
+ const uint32_t idx = REG_INDEX(offset);
136
+ */
245
+
137
+ bool is_split = mem_off == info.mem_off_split;
246
+ if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
138
+ /* TODO: MTE check. */
247
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
139
+ if (unlikely(flags != 0) || unlikely(is_split)) {
248
+ __func__, (uint32_t)offset);
140
+ /*
141
+ * Use the slow path for cross-page handling.
142
+ * Might trap for MMIO or watchpoints.
143
+ */
144
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
145
+
146
+ /* After any fault, zero the other elements. */
147
swap_memzero(vd, reg_off);
148
- return;
149
+ reg_off += 1 << esz;
150
+ mem_off += 1 << msz;
151
+ swap_memzero(vd + reg_off, reg_max - reg_off);
152
+
153
+ if (is_split) {
154
+ goto second_page;
155
+ }
156
+ } else {
157
+ memset(vd, 0, reg_max);
158
+ }
159
+ } else {
160
+ memset(vd, 0, reg_max);
161
+ if (unlikely(mem_off == info.mem_off_split)) {
162
+ /* The first active element crosses a page boundary. */
163
+ flags |= info.page[1].flags;
164
+ if (unlikely(flags & TLB_MMIO)) {
165
+ /* Some page is MMIO, see below. */
166
+ goto do_fault;
167
+ }
168
+ if (unlikely(flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr + mem_off, 1 << msz)
171
+ & BP_MEM_READ)) {
172
+ /* Watchpoint hit, see below. */
173
+ goto do_fault;
174
+ }
175
+ /* TODO: MTE check. */
176
+ /*
177
+ * Use the slow path for cross-page handling.
178
+ * This is RAM, without a watchpoint, and will not trap.
179
+ */
180
+ tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
181
+ goto second_page;
182
}
183
}
184
185
/*
186
- * Perform one normal read, which will fault or not.
187
- * But it is likely to bring the page into the tlb.
188
+ * From this point on, all memory operations are MemSingleNF.
189
+ *
190
+ * Per the MemSingleNF pseudocode, a no-fault load from Device memory
191
+ * must not actually hit the bus -- it returns (UNKNOWN, FAULT) instead.
192
+ *
193
+ * Unfortuately we do not have access to the memory attributes from the
194
+ * PTE to tell Device memory from Normal memory. So we make a mostly
195
+ * correct check, and indicate (UNKNOWN, FAULT) for any MMIO.
196
+ * This gives the right answer for the common cases of "Normal memory,
197
+ * backed by host RAM" and "Device memory, backed by MMIO".
198
+ * The architecture allows us to suppress an NF load and return
199
+ * (UNKNOWN, FAULT) for any reason, so our behaviour for the corner
200
+ * case of "Normal memory, backed by MMIO" is permitted. The case we
201
+ * get wrong is "Device memory, backed by host RAM", for which we
202
+ * should return (UNKNOWN, FAULT) for but do not.
203
+ *
204
+ * Similarly, CPU_BP breakpoints would raise exceptions, and so
205
+ * return (UNKNOWN, FAULT). For simplicity, we consider gdb and
206
+ * architectural breakpoints the same.
207
*/
208
- tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
209
+ if (unlikely(flags & TLB_MMIO)) {
210
+ goto do_fault;
211
+ }
212
213
- /* After any fault, zero any leading predicated false elts. */
214
- swap_memzero(vd, reg_off);
215
- mem_off += 1 << msz;
216
- reg_off += 1 << esz;
217
+ reg_last = info.reg_off_last[0];
218
+ host = info.page[0].host;
219
220
- /* Try again to read the balance of the page. */
221
- split = max_for_page(addr, mem_off - 1, mem_max);
222
- if (split >= (1 << msz)) {
223
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
224
- if (host) {
225
- host -= mem_off;
226
- do {
227
+ do {
228
+ uint64_t pg = *(uint64_t *)(vg + (reg_off >> 3));
229
+ do {
230
+ if ((pg >> (reg_off & 63)) & 1) {
231
+ if (unlikely(flags & TLB_WATCHPOINT) &&
232
+ (cpu_watchpoint_address_matches
233
+ (env_cpu(env), addr + mem_off, 1 << msz)
234
+ & BP_MEM_READ)) {
235
+ goto do_fault;
236
+ }
237
+ /* TODO: MTE check. */
238
host_fn(vd, reg_off, host + mem_off);
239
- reg_off += 1 << esz;
240
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
241
- mem_off = reg_off >> diffsz;
242
- } while (split - mem_off >= (1 << msz));
243
- }
244
- }
245
-
246
- record_fault(env, reg_off, reg_max);
247
-}
248
-
249
-/*
250
- * Common helper for all contiguous no-fault loads.
251
- */
252
-static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
253
- uint32_t desc, const int esz, const int msz,
254
- sve_ldst1_host_fn *host_fn)
255
-{
256
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
257
- void *vd = &env->vfp.zregs[rd];
258
- const int diffsz = esz - msz;
259
- const intptr_t reg_max = simd_oprsz(desc);
260
- const intptr_t mem_max = reg_max >> diffsz;
261
- const int mmu_idx = cpu_mmu_index(env, false);
262
- intptr_t split, reg_off, mem_off;
263
- void *host;
264
-
265
-#ifdef CONFIG_USER_ONLY
266
- host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx);
267
- if (likely(page_check_range(addr, mem_max, PAGE_READ) == 0)) {
268
- /* The entire operation is valid and will not fault. */
269
- reg_off = 0;
270
- do {
271
- mem_off = reg_off >> diffsz;
272
- host_fn(vd, reg_off, host + mem_off);
273
+ }
274
reg_off += 1 << esz;
275
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
276
- } while (reg_off < reg_max);
277
- return;
278
- }
279
-#endif
280
+ mem_off += 1 << msz;
281
+ } while (reg_off <= reg_last && (reg_off & 63));
282
+ } while (reg_off <= reg_last);
283
284
- /* There will be no fault, so we may modify in advance. */
285
- memset(vd, 0, reg_max);
286
-
287
- /* Skip to the first active element. */
288
- reg_off = find_next_active(vg, 0, reg_max, esz);
289
- if (unlikely(reg_off == reg_max)) {
290
- /* The entire predicate was false; no load occurs. */
291
- return;
292
- }
293
- mem_off = reg_off >> diffsz;
294
-
295
-#ifdef CONFIG_USER_ONLY
296
- if (page_check_range(addr + mem_off, 1 << msz, PAGE_READ) == 0) {
297
- /* At least one load is valid; take the rest of the page. */
298
- split = max_for_page(addr, mem_off + (1 << msz) - 1, mem_max);
299
- do {
300
- host_fn(vd, reg_off, host + mem_off);
301
- reg_off += 1 << esz;
302
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
303
- mem_off = reg_off >> diffsz;
304
- } while (split - mem_off >= (1 << msz));
305
- }
306
-#else
307
/*
308
- * If the address is not in the TLB, we have no way to bring the
309
- * entry into the TLB without also risking a fault. Note that
310
- * the corollary is that we never load from an address not in RAM.
311
- *
312
- * This last is out of spec, in a weird corner case.
313
- * Per the MemNF/MemSingleNF pseudocode, a NF load from Device memory
314
- * must not actually hit the bus -- it returns UNKNOWN data instead.
315
- * But if you map non-RAM with Normal memory attributes and do a NF
316
- * load then it should access the bus. (Nobody ought actually do this
317
- * in the real world, obviously.)
318
- *
319
- * Then there are the annoying special cases with watchpoints...
320
- * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true).
321
+ * MemSingleNF is allowed to fail for any reason. We have special
322
+ * code above to handle the first element crossing a page boundary.
323
+ * As an implementation choice, decline to handle a cross-page element
324
+ * in any other position.
325
*/
326
- host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx);
327
- split = max_for_page(addr, mem_off, mem_max);
328
- if (host && split >= (1 << msz)) {
329
- host -= mem_off;
330
- do {
331
- host_fn(vd, reg_off, host + mem_off);
332
- reg_off += 1 << esz;
333
- reg_off = find_next_active(vg, reg_off, reg_max, esz);
334
- mem_off = reg_off >> diffsz;
335
- } while (split - mem_off >= (1 << msz));
336
+ reg_off = info.reg_off_split;
337
+ if (reg_off >= 0) {
338
+ goto do_fault;
339
}
340
-#endif
341
342
+ second_page:
343
+ reg_off = info.reg_off_first[1];
344
+ if (likely(reg_off < 0)) {
345
+ /* No active elements on the second page. All done. */
249
+ return;
346
+ return;
250
+ }
347
+ }
251
+
348
+
252
+ switch (offset) {
349
+ /*
253
+ case REG_VER: /* Version */
350
+ * MemSingleNF is allowed to fail for any reason. As an implementation
254
+ break;
351
+ * choice, decline to handle elements on the second page. This should
255
+ default:
352
+ * be low frequency as the guest walks through memory -- the next
256
+ s->regs[idx] = (uint32_t) val;
353
+ * iteration of the guest's loop should be aligned on the page boundary,
257
+ break;
354
+ * and then all following iterations will stay aligned.
258
+ }
355
+ */
259
+}
356
+
260
+
357
+ do_fault:
261
+static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
358
record_fault(env, reg_off, reg_max);
262
+ .read = allwinner_h3_sysctrl_read,
359
}
263
+ .write = allwinner_h3_sysctrl_write,
360
264
+ .endianness = DEVICE_NATIVE_ENDIAN,
361
@@ -XXX,XX +XXX,XX @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr,
265
+ .valid = {
362
void HELPER(sve_ldff1##PART##_r)(CPUARMState *env, void *vg, \
266
+ .min_access_size = 4,
363
target_ulong addr, uint32_t desc) \
267
+ .max_access_size = 4,
364
{ \
268
+ },
365
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, 0, \
269
+ .impl.min_access_size = 4,
366
- sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
270
+};
367
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_FIRST, \
271
+
368
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
272
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
369
} \
273
+{
370
void HELPER(sve_ldnf1##PART##_r)(CPUARMState *env, void *vg, \
274
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
371
target_ulong addr, uint32_t desc) \
275
+
372
{ \
276
+ /* Set default values for registers */
373
- sve_ldnf1_r(env, vg, addr, desc, ESZ, 0, sve_ld1##PART##_host); \
277
+ s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
374
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, FAULT_NO, \
278
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
375
+ sve_ld1##PART##_host, sve_ld1##PART##_tlb); \
279
+}
376
}
280
+
377
281
+static void allwinner_h3_sysctrl_init(Object *obj)
378
#define DO_LDFF1_LDNF1_2(PART, ESZ, MSZ) \
282
+{
379
void HELPER(sve_ldff1##PART##_le_r)(CPUARMState *env, void *vg, \
283
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
380
target_ulong addr, uint32_t desc) \
284
+ AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
381
{ \
285
+
382
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
286
+ /* Memory mapping */
383
- sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
287
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
384
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
288
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
385
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
289
+ sysbus_init_mmio(sbd, &s->iomem);
386
} \
290
+}
387
void HELPER(sve_ldnf1##PART##_le_r)(CPUARMState *env, void *vg, \
291
+
388
target_ulong addr, uint32_t desc) \
292
+static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
389
{ \
293
+ .name = "allwinner-h3-sysctrl",
390
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_le_host); \
294
+ .version_id = 1,
391
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
295
+ .minimum_version_id = 1,
392
+ sve_ld1##PART##_le_host, sve_ld1##PART##_le_tlb); \
296
+ .fields = (VMStateField[]) {
393
} \
297
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
394
void HELPER(sve_ldff1##PART##_be_r)(CPUARMState *env, void *vg, \
298
+ VMSTATE_END_OF_LIST()
395
target_ulong addr, uint32_t desc) \
299
+ }
396
{ \
300
+};
397
- sve_ldff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, \
301
+
398
- sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
302
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
399
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_FIRST, \
303
+{
400
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
401
} \
305
+
402
void HELPER(sve_ldnf1##PART##_be_r)(CPUARMState *env, void *vg, \
306
+ dc->reset = allwinner_h3_sysctrl_reset;
403
target_ulong addr, uint32_t desc) \
307
+ dc->vmsd = &allwinner_h3_sysctrl_vmstate;
404
{ \
308
+}
405
- sve_ldnf1_r(env, vg, addr, desc, ESZ, MSZ, sve_ld1##PART##_be_host); \
309
+
406
+ sve_ldnfff1_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, FAULT_NO, \
310
+static const TypeInfo allwinner_h3_sysctrl_info = {
407
+ sve_ld1##PART##_be_host, sve_ld1##PART##_be_tlb); \
311
+ .name = TYPE_AW_H3_SYSCTRL,
408
}
312
+ .parent = TYPE_SYS_BUS_DEVICE,
409
313
+ .instance_init = allwinner_h3_sysctrl_init,
410
-DO_LDFF1_LDNF1_1(bb, 0)
314
+ .instance_size = sizeof(AwH3SysCtrlState),
411
-DO_LDFF1_LDNF1_1(bhu, 1)
315
+ .class_init = allwinner_h3_sysctrl_class_init,
412
-DO_LDFF1_LDNF1_1(bhs, 1)
316
+};
413
-DO_LDFF1_LDNF1_1(bsu, 2)
317
+
414
-DO_LDFF1_LDNF1_1(bss, 2)
318
+static void allwinner_h3_sysctrl_register(void)
415
-DO_LDFF1_LDNF1_1(bdu, 3)
319
+{
416
-DO_LDFF1_LDNF1_1(bds, 3)
320
+ type_register_static(&allwinner_h3_sysctrl_info);
417
+DO_LDFF1_LDNF1_1(bb, MO_8)
321
+}
418
+DO_LDFF1_LDNF1_1(bhu, MO_16)
322
+
419
+DO_LDFF1_LDNF1_1(bhs, MO_16)
323
+type_init(allwinner_h3_sysctrl_register)
420
+DO_LDFF1_LDNF1_1(bsu, MO_32)
421
+DO_LDFF1_LDNF1_1(bss, MO_32)
422
+DO_LDFF1_LDNF1_1(bdu, MO_64)
423
+DO_LDFF1_LDNF1_1(bds, MO_64)
424
425
-DO_LDFF1_LDNF1_2(hh, 1, 1)
426
-DO_LDFF1_LDNF1_2(hsu, 2, 1)
427
-DO_LDFF1_LDNF1_2(hss, 2, 1)
428
-DO_LDFF1_LDNF1_2(hdu, 3, 1)
429
-DO_LDFF1_LDNF1_2(hds, 3, 1)
430
+DO_LDFF1_LDNF1_2(hh, MO_16, MO_16)
431
+DO_LDFF1_LDNF1_2(hsu, MO_32, MO_16)
432
+DO_LDFF1_LDNF1_2(hss, MO_32, MO_16)
433
+DO_LDFF1_LDNF1_2(hdu, MO_64, MO_16)
434
+DO_LDFF1_LDNF1_2(hds, MO_64, MO_16)
435
436
-DO_LDFF1_LDNF1_2(ss, 2, 2)
437
-DO_LDFF1_LDNF1_2(sdu, 3, 2)
438
-DO_LDFF1_LDNF1_2(sds, 3, 2)
439
+DO_LDFF1_LDNF1_2(ss, MO_32, MO_32)
440
+DO_LDFF1_LDNF1_2(sdu, MO_64, MO_32)
441
+DO_LDFF1_LDNF1_2(sds, MO_64, MO_32)
442
443
-DO_LDFF1_LDNF1_2(dd, 3, 3)
444
+DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
445
446
#undef DO_LDFF1_LDNF1_1
447
#undef DO_LDFF1_LDNF1_2
324
--
448
--
325
2.20.1
449
2.20.1
326
450
327
451
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
3
Follow the model set up for contiguous loads. This handles
4
which provides 10M/100M/1000M Ethernet connectivity. This commit
4
watchpoints correctly for contiguous stores, recognizing the
5
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
5
exception before any changes to memory.
6
including emulation for the following functionality:
6
7
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
* DMA transfers
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
* MII interface
9
Message-id: 20200508154359.7494-16-richard.henderson@linaro.org
10
* Transmit CRC calculation
11
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
11
---
17
hw/net/Makefile.objs | 1 +
12
target/arm/sve_helper.c | 285 ++++++++++++++++++++++------------------
18
include/hw/arm/allwinner-h3.h | 3 +
13
1 file changed, 159 insertions(+), 126 deletions(-)
19
include/hw/net/allwinner-sun8i-emac.h | 99 +++
14
20
hw/arm/allwinner-h3.c | 16 +-
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
21
hw/arm/orangepi.c | 3 +
22
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
23
hw/arm/Kconfig | 1 +
24
hw/net/Kconfig | 3 +
25
hw/net/trace-events | 10 +
26
9 files changed, 1006 insertions(+), 1 deletion(-)
27
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
28
create mode 100644 hw/net/allwinner-sun8i-emac.c
29
30
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
31
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/net/Makefile.objs
17
--- a/target/arm/sve_helper.c
33
+++ b/hw/net/Makefile.objs
18
+++ b/target/arm/sve_helper.c
34
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
19
@@ -XXX,XX +XXX,XX @@ static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
35
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
20
*(TYPEE *)(vd + H(reg_off)) = val; \
36
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
37
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
38
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o
39
common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
40
41
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
42
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/include/hw/arm/allwinner-h3.h
45
+++ b/include/hw/arm/allwinner-h3.h
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/misc/allwinner-h3-sysctrl.h"
48
#include "hw/misc/allwinner-sid.h"
49
#include "hw/sd/allwinner-sdhost.h"
50
+#include "hw/net/allwinner-sun8i-emac.h"
51
#include "target/arm/cpu.h"
52
53
/**
54
@@ -XXX,XX +XXX,XX @@ enum {
55
AW_H3_UART1,
56
AW_H3_UART2,
57
AW_H3_UART3,
58
+ AW_H3_EMAC,
59
AW_H3_GIC_DIST,
60
AW_H3_GIC_CPU,
61
AW_H3_GIC_HYP,
62
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
63
AwH3SysCtrlState sysctrl;
64
AwSidState sid;
65
AwSdHostState mmc0;
66
+ AwSun8iEmacState emac;
67
GICState gic;
68
MemoryRegion sram_a1;
69
MemoryRegion sram_a2;
70
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
71
new file mode 100644
72
index XXXXXXX..XXXXXXX
73
--- /dev/null
74
+++ b/include/hw/net/allwinner-sun8i-emac.h
75
@@ -XXX,XX +XXX,XX @@
76
+/*
77
+ * Allwinner Sun8i Ethernet MAC emulation
78
+ *
79
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
80
+ *
81
+ * This program is free software: you can redistribute it and/or modify
82
+ * it under the terms of the GNU General Public License as published by
83
+ * the Free Software Foundation, either version 2 of the License, or
84
+ * (at your option) any later version.
85
+ *
86
+ * This program is distributed in the hope that it will be useful,
87
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
88
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89
+ * GNU General Public License for more details.
90
+ *
91
+ * You should have received a copy of the GNU General Public License
92
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
93
+ */
94
+
95
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
96
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
97
+
98
+#include "qom/object.h"
99
+#include "net/net.h"
100
+#include "hw/sysbus.h"
101
+
102
+/**
103
+ * Object model
104
+ * @{
105
+ */
106
+
107
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
108
+#define AW_SUN8I_EMAC(obj) \
109
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
110
+
111
+/** @} */
112
+
113
+/**
114
+ * Allwinner Sun8i EMAC object instance state
115
+ */
116
+typedef struct AwSun8iEmacState {
117
+ /*< private >*/
118
+ SysBusDevice parent_obj;
119
+ /*< public >*/
120
+
121
+ /** Maps I/O registers in physical memory */
122
+ MemoryRegion iomem;
123
+
124
+ /** Interrupt output signal to notify CPU */
125
+ qemu_irq irq;
126
+
127
+ /** Generic Network Interface Controller (NIC) for networking API */
128
+ NICState *nic;
129
+
130
+ /** Generic Network Interface Controller (NIC) configuration */
131
+ NICConf conf;
132
+
133
+ /**
134
+ * @name Media Independent Interface (MII)
135
+ * @{
136
+ */
137
+
138
+ uint8_t mii_phy_addr; /**< PHY address */
139
+ uint32_t mii_cr; /**< Control */
140
+ uint32_t mii_st; /**< Status */
141
+ uint32_t mii_adv; /**< Advertised Abilities */
142
+
143
+ /** @} */
144
+
145
+ /**
146
+ * @name Hardware Registers
147
+ * @{
148
+ */
149
+
150
+ uint32_t basic_ctl0; /**< Basic Control 0 */
151
+ uint32_t basic_ctl1; /**< Basic Control 1 */
152
+ uint32_t int_en; /**< Interrupt Enable */
153
+ uint32_t int_sta; /**< Interrupt Status */
154
+ uint32_t frm_flt; /**< Receive Frame Filter */
155
+
156
+ uint32_t rx_ctl0; /**< Receive Control 0 */
157
+ uint32_t rx_ctl1; /**< Receive Control 1 */
158
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
159
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
160
+
161
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
162
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
163
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
164
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
165
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
166
+
167
+ uint32_t mii_cmd; /**< Management Interface Command */
168
+ uint32_t mii_data; /**< Management Interface Data */
169
+
170
+ /** @} */
171
+
172
+} AwSun8iEmacState;
173
+
174
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
175
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/arm/allwinner-h3.c
178
+++ b/hw/arm/allwinner-h3.c
179
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
180
[AW_H3_UART1] = 0x01c28400,
181
[AW_H3_UART2] = 0x01c28800,
182
[AW_H3_UART3] = 0x01c28c00,
183
+ [AW_H3_EMAC] = 0x01c30000,
184
[AW_H3_GIC_DIST] = 0x01c81000,
185
[AW_H3_GIC_CPU] = 0x01c82000,
186
[AW_H3_GIC_HYP] = 0x01c84000,
187
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
188
{ "twi1", 0x01c2b000, 1 * KiB },
189
{ "twi2", 0x01c2b400, 1 * KiB },
190
{ "scr", 0x01c2c400, 1 * KiB },
191
- { "emac", 0x01c30000, 64 * KiB },
192
{ "gpu", 0x01c40000, 64 * KiB },
193
{ "hstmr", 0x01c60000, 4 * KiB },
194
{ "dramcom", 0x01c62000, 4 * KiB },
195
@@ -XXX,XX +XXX,XX @@ enum {
196
AW_H3_GIC_SPI_OHCI2 = 77,
197
AW_H3_GIC_SPI_EHCI3 = 78,
198
AW_H3_GIC_SPI_OHCI3 = 79,
199
+ AW_H3_GIC_SPI_EMAC = 82
200
};
201
202
/* Allwinner H3 general constants */
203
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
204
205
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
206
TYPE_AW_SDHOST_SUN5I);
207
+
208
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
209
+ TYPE_AW_SUN8I_EMAC);
210
}
21
}
211
22
212
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
23
+#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
213
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
24
+static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
214
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
25
+{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); }
215
"sd-bus", &error_abort);
26
+
216
27
#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
217
+ /* EMAC */
28
static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
218
+ if (nd_table[0].used) {
29
target_ulong addr, uintptr_t ra) \
219
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
30
@@ -XXX,XX +XXX,XX @@ DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t)
220
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
31
DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t)
221
+ }
32
222
+ qdev_init_nofail(DEVICE(&s->emac));
33
#define DO_ST_PRIM_1(NAME, H, TE, TM) \
223
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
34
+ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
224
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
35
DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
225
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
36
226
+
37
DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
227
/* Universal Serial Bus */
38
@@ -XXX,XX +XXX,XX @@ DO_ST_PRIM_1(bd, , uint64_t, uint8_t)
228
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
39
DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
229
qdev_get_gpio_in(DEVICE(&s->gic),
40
230
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
41
#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
231
index XXXXXXX..XXXXXXX 100644
42
+ DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
232
--- a/hw/arm/orangepi.c
43
+ DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
233
+++ b/hw/arm/orangepi.c
44
DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
234
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
45
DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
235
warn_report("Security Identifier value does not include H3 prefix");
46
236
}
47
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_LDNF1_2(dd, MO_64, MO_64)
237
48
#undef DO_LDFF1_LDNF1_2
238
+ /* Setup EMAC properties */
49
239
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);
50
/*
240
+
51
- * Common helpers for all contiguous 1,2,3,4-register predicated stores.
241
/* Mark H3 object realized */
52
+ * Common helper for all contiguous 1,2,3,4-register predicated stores.
242
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
53
*/
243
54
-static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
244
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
55
- uint32_t desc, const uintptr_t ra,
245
new file mode 100644
56
- const int esize, const int msize,
246
index XXXXXXX..XXXXXXX
57
- sve_ldst1_tlb_fn *tlb_fn)
247
--- /dev/null
58
+
248
+++ b/hw/net/allwinner-sun8i-emac.c
59
+static inline QEMU_ALWAYS_INLINE
249
@@ -XXX,XX +XXX,XX @@
60
+void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
250
+/*
61
+ const uintptr_t retaddr, const int esz,
251
+ * Allwinner Sun8i Ethernet MAC emulation
62
+ const int msz, const int N,
252
+ *
63
+ sve_ldst1_host_fn *host_fn,
253
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
64
+ sve_ldst1_tlb_fn *tlb_fn)
254
+ *
65
{
255
+ * This program is free software: you can redistribute it and/or modify
66
const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
256
+ * it under the terms of the GNU General Public License as published by
67
- intptr_t i, oprsz = simd_oprsz(desc);
257
+ * the Free Software Foundation, either version 2 of the License, or
68
- void *vd = &env->vfp.zregs[rd];
258
+ * (at your option) any later version.
69
+ const intptr_t reg_max = simd_oprsz(desc);
259
+ *
70
+ intptr_t reg_off, reg_last, mem_off;
260
+ * This program is distributed in the hope that it will be useful,
71
+ SVEContLdSt info;
261
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
72
+ void *host;
262
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
73
+ int i, flags;
263
+ * GNU General Public License for more details.
74
264
+ *
75
- for (i = 0; i < oprsz; ) {
265
+ * You should have received a copy of the GNU General Public License
76
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
266
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
77
- do {
267
+ */
78
- if (pg & 1) {
268
+
79
- tlb_fn(env, vd, i, addr, ra);
269
+#include "qemu/osdep.h"
80
+ /* Find the active elements. */
270
+#include "qemu/units.h"
81
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, N << msz)) {
271
+#include "hw/sysbus.h"
82
+ /* The entire predicate was false; no store occurs. */
272
+#include "migration/vmstate.h"
273
+#include "net/net.h"
274
+#include "hw/irq.h"
275
+#include "hw/qdev-properties.h"
276
+#include "qemu/log.h"
277
+#include "trace.h"
278
+#include "net/checksum.h"
279
+#include "qemu/module.h"
280
+#include "exec/cpu-common.h"
281
+#include "hw/net/allwinner-sun8i-emac.h"
282
+
283
+/* EMAC register offsets */
284
+enum {
285
+ REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */
286
+ REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */
287
+ REG_INT_STA = 0x0008, /* Interrupt Status */
288
+ REG_INT_EN = 0x000C, /* Interrupt Enable */
289
+ REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
290
+ REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
291
+ REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
292
+ REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
293
+ REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
294
+ REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
295
+ REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
296
+ REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
297
+ REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
298
+ REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
299
+ REG_MII_CMD = 0x0048, /* Management Interface Command */
300
+ REG_MII_DATA = 0x004C, /* Management Interface Data */
301
+ REG_ADDR_HIGH = 0x0050, /* MAC Address High */
302
+ REG_ADDR_LOW = 0x0054, /* MAC Address Low */
303
+ REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
304
+ REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
305
+ REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
306
+ REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
307
+ REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
308
+ REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
309
+ REG_RGMII_STA = 0x00D0, /* RGMII Status */
310
+};
311
+
312
+/* EMAC register flags */
313
+enum {
314
+ BASIC_CTL0_100Mbps = (0b11 << 2),
315
+ BASIC_CTL0_FD = (1 << 0),
316
+ BASIC_CTL1_SOFTRST = (1 << 0),
317
+};
318
+
319
+enum {
320
+ INT_STA_RGMII_LINK = (1 << 16),
321
+ INT_STA_RX_EARLY = (1 << 13),
322
+ INT_STA_RX_OVERFLOW = (1 << 12),
323
+ INT_STA_RX_TIMEOUT = (1 << 11),
324
+ INT_STA_RX_DMA_STOP = (1 << 10),
325
+ INT_STA_RX_BUF_UA = (1 << 9),
326
+ INT_STA_RX = (1 << 8),
327
+ INT_STA_TX_EARLY = (1 << 5),
328
+ INT_STA_TX_UNDERFLOW = (1 << 4),
329
+ INT_STA_TX_TIMEOUT = (1 << 3),
330
+ INT_STA_TX_BUF_UA = (1 << 2),
331
+ INT_STA_TX_DMA_STOP = (1 << 1),
332
+ INT_STA_TX = (1 << 0),
333
+};
334
+
335
+enum {
336
+ INT_EN_RX_EARLY = (1 << 13),
337
+ INT_EN_RX_OVERFLOW = (1 << 12),
338
+ INT_EN_RX_TIMEOUT = (1 << 11),
339
+ INT_EN_RX_DMA_STOP = (1 << 10),
340
+ INT_EN_RX_BUF_UA = (1 << 9),
341
+ INT_EN_RX = (1 << 8),
342
+ INT_EN_TX_EARLY = (1 << 5),
343
+ INT_EN_TX_UNDERFLOW = (1 << 4),
344
+ INT_EN_TX_TIMEOUT = (1 << 3),
345
+ INT_EN_TX_BUF_UA = (1 << 2),
346
+ INT_EN_TX_DMA_STOP = (1 << 1),
347
+ INT_EN_TX = (1 << 0),
348
+};
349
+
350
+enum {
351
+ TX_CTL0_TX_EN = (1 << 31),
352
+ TX_CTL1_TX_DMA_START = (1 << 31),
353
+ TX_CTL1_TX_DMA_EN = (1 << 30),
354
+ TX_CTL1_TX_FLUSH = (1 << 0),
355
+};
356
+
357
+enum {
358
+ RX_CTL0_RX_EN = (1 << 31),
359
+ RX_CTL0_STRIP_FCS = (1 << 28),
360
+ RX_CTL0_CRC_IPV4 = (1 << 27),
361
+};
362
+
363
+enum {
364
+ RX_CTL1_RX_DMA_START = (1 << 31),
365
+ RX_CTL1_RX_DMA_EN = (1 << 30),
366
+ RX_CTL1_RX_MD = (1 << 1),
367
+};
368
+
369
+enum {
370
+ RX_FRM_FLT_DIS_ADDR = (1 << 31),
371
+};
372
+
373
+enum {
374
+ MII_CMD_PHY_ADDR_SHIFT = (12),
375
+ MII_CMD_PHY_ADDR_MASK = (0xf000),
376
+ MII_CMD_PHY_REG_SHIFT = (4),
377
+ MII_CMD_PHY_REG_MASK = (0xf0),
378
+ MII_CMD_PHY_RW = (1 << 1),
379
+ MII_CMD_PHY_BUSY = (1 << 0),
380
+};
381
+
382
+enum {
383
+ TX_DMA_STA_STOP = (0b000),
384
+ TX_DMA_STA_RUN_FETCH = (0b001),
385
+ TX_DMA_STA_WAIT_STA = (0b010),
386
+};
387
+
388
+enum {
389
+ RX_DMA_STA_STOP = (0b000),
390
+ RX_DMA_STA_RUN_FETCH = (0b001),
391
+ RX_DMA_STA_WAIT_FRM = (0b011),
392
+};
393
+
394
+/* EMAC register reset values */
395
+enum {
396
+ REG_BASIC_CTL_1_RST = 0x08000000,
397
+};
398
+
399
+/* EMAC constants */
400
+enum {
401
+ AW_SUN8I_EMAC_MIN_PKT_SZ = 64
402
+};
403
+
404
+/* Transmit/receive frame descriptor */
405
+typedef struct FrameDescriptor {
406
+ uint32_t status;
407
+ uint32_t status2;
408
+ uint32_t addr;
409
+ uint32_t next;
410
+} FrameDescriptor;
411
+
412
+/* Frame descriptor flags */
413
+enum {
414
+ DESC_STATUS_CTL = (1 << 31),
415
+ DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
416
+};
417
+
418
+/* Transmit frame descriptor flags */
419
+enum {
420
+ TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
421
+ TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
422
+ TX_DESC_STATUS2_LAST_DESC = (1 << 30),
423
+ TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
424
+};
425
+
426
+/* Receive frame descriptor flags */
427
+enum {
428
+ RX_DESC_STATUS_FIRST_DESC = (1 << 9),
429
+ RX_DESC_STATUS_LAST_DESC = (1 << 8),
430
+ RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
431
+ RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
432
+ RX_DESC_STATUS_NO_BUF = (1 << 14),
433
+ RX_DESC_STATUS_HEADER_ERR = (1 << 7),
434
+ RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
435
+ RX_DESC_STATUS_CRC_ERR = (1 << 1),
436
+ RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
437
+ RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
438
+};
439
+
440
+/* MII register offsets */
441
+enum {
442
+ MII_REG_CR = (0x0), /* Control */
443
+ MII_REG_ST = (0x1), /* Status */
444
+ MII_REG_ID_HIGH = (0x2), /* Identifier High */
445
+ MII_REG_ID_LOW = (0x3), /* Identifier Low */
446
+ MII_REG_ADV = (0x4), /* Advertised abilities */
447
+ MII_REG_LPA = (0x5), /* Link partner abilities */
448
+};
449
+
450
+/* MII register flags */
451
+enum {
452
+ MII_REG_CR_RESET = (1 << 15),
453
+ MII_REG_CR_POWERDOWN = (1 << 11),
454
+ MII_REG_CR_10Mbit = (0),
455
+ MII_REG_CR_100Mbit = (1 << 13),
456
+ MII_REG_CR_1000Mbit = (1 << 6),
457
+ MII_REG_CR_AUTO_NEG = (1 << 12),
458
+ MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
459
+ MII_REG_CR_FULLDUPLEX = (1 << 8),
460
+};
461
+
462
+enum {
463
+ MII_REG_ST_100BASE_T4 = (1 << 15),
464
+ MII_REG_ST_100BASE_X_FD = (1 << 14),
465
+ MII_REG_ST_100BASE_X_HD = (1 << 13),
466
+ MII_REG_ST_10_FD = (1 << 12),
467
+ MII_REG_ST_10_HD = (1 << 11),
468
+ MII_REG_ST_100BASE_T2_FD = (1 << 10),
469
+ MII_REG_ST_100BASE_T2_HD = (1 << 9),
470
+ MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
471
+ MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
472
+ MII_REG_ST_LINK_UP = (1 << 2),
473
+};
474
+
475
+enum {
476
+ MII_REG_LPA_10_HD = (1 << 5),
477
+ MII_REG_LPA_10_FD = (1 << 6),
478
+ MII_REG_LPA_100_HD = (1 << 7),
479
+ MII_REG_LPA_100_FD = (1 << 8),
480
+ MII_REG_LPA_PAUSE = (1 << 10),
481
+ MII_REG_LPA_ASYMPAUSE = (1 << 11),
482
+};
483
+
484
+/* MII constants */
485
+enum {
486
+ MII_PHY_ID_HIGH = 0x0044,
487
+ MII_PHY_ID_LOW = 0x1400,
488
+};
489
+
490
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
491
+ bool link_active)
492
+{
493
+ if (link_active) {
494
+ s->mii_st |= MII_REG_ST_LINK_UP;
495
+ } else {
496
+ s->mii_st &= ~MII_REG_ST_LINK_UP;
497
+ }
498
+}
499
+
500
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
501
+ bool link_active)
502
+{
503
+ s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
504
+ MII_REG_CR_FULLDUPLEX;
505
+ s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
506
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
507
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
508
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
509
+ s->mii_adv = 0;
510
+
511
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
512
+}
513
+
514
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
515
+{
516
+ uint8_t addr, reg;
517
+
518
+ addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
519
+ reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
520
+
521
+ if (addr != s->mii_phy_addr) {
522
+ return;
83
+ return;
523
+ }
84
+ }
524
+
85
+
525
+ /* Read or write a PHY register? */
86
+ /* Probe the page(s). Exit with exception for any invalid page. */
526
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
87
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, retaddr);
527
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
88
+
528
+
89
+ /* Handle watchpoints for all active elements. */
529
+ switch (reg) {
90
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, 1 << esz, N << msz,
530
+ case MII_REG_CR:
91
+ BP_MEM_WRITE, retaddr);
531
+ if (s->mii_data & MII_REG_CR_RESET) {
92
+
532
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
93
+ /* TODO: MTE check. */
533
+ MII_REG_ST_LINK_UP);
94
+
534
+ } else {
95
+ flags = info.page[0].flags | info.page[1].flags;
535
+ s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
96
+ if (unlikely(flags != 0)) {
536
+ MII_REG_CR_AUTO_NEG_RESTART);
97
+#ifdef CONFIG_USER_ONLY
98
+ g_assert_not_reached();
99
+#else
100
+ /*
101
+ * At least one page includes MMIO.
102
+ * Any bus operation can fail with cpu_transaction_failed,
103
+ * which for ARM will raise SyncExternal. We cannot avoid
104
+ * this fault and will leave with the store incomplete.
105
+ */
106
+ mem_off = info.mem_off_first[0];
107
+ reg_off = info.reg_off_first[0];
108
+ reg_last = info.reg_off_last[1];
109
+ if (reg_last < 0) {
110
+ reg_last = info.reg_off_split;
111
+ if (reg_last < 0) {
112
+ reg_last = info.reg_off_last[0];
113
}
114
- i += esize, pg >>= esize;
115
- addr += msize;
116
- } while (i & 15);
117
+ }
118
+
119
+ do {
120
+ uint64_t pg = vg[reg_off >> 6];
121
+ do {
122
+ if ((pg >> (reg_off & 63)) & 1) {
123
+ for (i = 0; i < N; ++i) {
124
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
125
+ addr + mem_off + (i << msz), retaddr);
126
+ }
127
+ }
128
+ reg_off += 1 << esz;
129
+ mem_off += N << msz;
130
+ } while (reg_off & 63);
131
+ } while (reg_off <= reg_last);
132
+ return;
133
+#endif
134
+ }
135
+
136
+ mem_off = info.mem_off_first[0];
137
+ reg_off = info.reg_off_first[0];
138
+ reg_last = info.reg_off_last[0];
139
+ host = info.page[0].host;
140
+
141
+ while (reg_off <= reg_last) {
142
+ uint64_t pg = vg[reg_off >> 6];
143
+ do {
144
+ if ((pg >> (reg_off & 63)) & 1) {
145
+ for (i = 0; i < N; ++i) {
146
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
147
+ host + mem_off + (i << msz));
148
+ }
537
+ }
149
+ }
538
+ break;
150
+ reg_off += 1 << esz;
539
+ case MII_REG_ADV:
151
+ mem_off += N << msz;
540
+ s->mii_adv = s->mii_data;
152
+ } while (reg_off <= reg_last && (reg_off & 63));
541
+ break;
542
+ case MII_REG_ID_HIGH:
543
+ case MII_REG_ID_LOW:
544
+ case MII_REG_LPA:
545
+ break;
546
+ default:
547
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
548
+ "unknown MII register 0x%x\n", reg);
549
+ break;
550
+ }
551
+ } else {
552
+ switch (reg) {
553
+ case MII_REG_CR:
554
+ s->mii_data = s->mii_cr;
555
+ break;
556
+ case MII_REG_ST:
557
+ s->mii_data = s->mii_st;
558
+ break;
559
+ case MII_REG_ID_HIGH:
560
+ s->mii_data = MII_PHY_ID_HIGH;
561
+ break;
562
+ case MII_REG_ID_LOW:
563
+ s->mii_data = MII_PHY_ID_LOW;
564
+ break;
565
+ case MII_REG_ADV:
566
+ s->mii_data = s->mii_adv;
567
+ break;
568
+ case MII_REG_LPA:
569
+ s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
570
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
571
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
572
+ break;
573
+ default:
574
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
575
+ "unknown MII register 0x%x\n", reg);
576
+ s->mii_data = 0;
577
+ break;
578
+ }
579
+
580
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
581
+ }
153
+ }
582
+}
154
+
583
+
155
+ /*
584
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
156
+ * Use the slow path to manage the cross-page misalignment.
585
+{
157
+ * But we know this is RAM and cannot trap.
586
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
158
+ */
587
+}
159
+ mem_off = info.mem_off_split;
588
+
160
+ if (unlikely(mem_off >= 0)) {
589
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
161
+ reg_off = info.reg_off_split;
590
+ size_t min_size)
162
+ for (i = 0; i < N; ++i) {
591
+{
163
+ tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off,
592
+ uint32_t paddr = desc->next;
164
+ addr + mem_off + (i << msz), retaddr);
593
+
594
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
595
+
596
+ if ((desc->status & DESC_STATUS_CTL) &&
597
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
598
+ return paddr;
599
+ } else {
600
+ return 0;
601
+ }
602
+}
603
+
604
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
605
+ uint32_t start_addr,
606
+ size_t min_size)
607
+{
608
+ uint32_t desc_addr = start_addr;
609
+
610
+ /* Note that the list is a cycle. Last entry points back to the head. */
611
+ while (desc_addr != 0) {
612
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
613
+
614
+ if ((desc->status & DESC_STATUS_CTL) &&
615
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
616
+ return desc_addr;
617
+ } else if (desc->next == start_addr) {
618
+ break;
619
+ } else {
620
+ desc_addr = desc->next;
621
+ }
165
+ }
622
+ }
166
+ }
623
+
167
+
624
+ return 0;
168
+ mem_off = info.mem_off_first[1];
625
+}
169
+ if (unlikely(mem_off >= 0)) {
626
+
170
+ reg_off = info.reg_off_first[1];
627
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
171
+ reg_last = info.reg_off_last[1];
628
+ FrameDescriptor *desc,
172
+ host = info.page[1].host;
629
+ size_t min_size)
173
+
630
+{
174
+ do {
631
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
175
+ uint64_t pg = vg[reg_off >> 6];
632
+}
176
+ do {
633
+
177
+ if ((pg >> (reg_off & 63)) & 1) {
634
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
178
+ for (i = 0; i < N; ++i) {
635
+ FrameDescriptor *desc,
179
+ host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off,
636
+ size_t min_size)
180
+ host + mem_off + (i << msz));
637
+{
181
+ }
638
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
182
+ }
639
+}
183
+ reg_off += 1 << esz;
640
+
184
+ mem_off += N << msz;
641
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
185
+ } while (reg_off & 63);
642
+ uint32_t phys_addr)
186
+ } while (reg_off <= reg_last);
643
+{
187
}
644
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
188
}
645
+}
189
646
+
190
-static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
647
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
191
- uint32_t desc, const uintptr_t ra,
648
+{
192
- const int esize, const int msize,
649
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
193
- sve_ldst1_tlb_fn *tlb_fn)
650
+ FrameDescriptor desc;
194
-{
651
+
195
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
652
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
196
- intptr_t i, oprsz = simd_oprsz(desc);
653
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
197
- void *d1 = &env->vfp.zregs[rd];
654
+}
198
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
655
+
199
-
656
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
200
- for (i = 0; i < oprsz; ) {
657
+ const uint8_t *buf,
201
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
658
+ size_t size)
202
- do {
659
+{
203
- if (pg & 1) {
660
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
204
- tlb_fn(env, d1, i, addr, ra);
661
+ FrameDescriptor desc;
205
- tlb_fn(env, d2, i, addr + msize, ra);
662
+ size_t bytes_left = size;
206
- }
663
+ size_t desc_bytes = 0;
207
- i += esize, pg >>= esize;
664
+ size_t pad_fcs_size = 4;
208
- addr += 2 * msize;
665
+ size_t padding = 0;
209
- } while (i & 15);
666
+
210
- }
667
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
211
-}
668
+ return -1;
212
-
669
+ }
213
-static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
670
+
214
- uint32_t desc, const uintptr_t ra,
671
+ s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
215
- const int esize, const int msize,
672
+ AW_SUN8I_EMAC_MIN_PKT_SZ);
216
- sve_ldst1_tlb_fn *tlb_fn)
673
+ if (!s->rx_desc_curr) {
217
-{
674
+ s->int_sta |= INT_STA_RX_BUF_UA;
218
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
675
+ }
219
- intptr_t i, oprsz = simd_oprsz(desc);
676
+
220
- void *d1 = &env->vfp.zregs[rd];
677
+ /* Keep filling RX descriptors until the whole frame is written */
221
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
678
+ while (s->rx_desc_curr && bytes_left > 0) {
222
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
679
+ desc.status &= ~DESC_STATUS_CTL;
223
-
680
+ desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
224
- for (i = 0; i < oprsz; ) {
681
+
225
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
682
+ if (bytes_left == size) {
226
- do {
683
+ desc.status |= RX_DESC_STATUS_FIRST_DESC;
227
- if (pg & 1) {
684
+ }
228
- tlb_fn(env, d1, i, addr, ra);
685
+
229
- tlb_fn(env, d2, i, addr + msize, ra);
686
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
230
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
687
+ (bytes_left + pad_fcs_size)) {
231
- }
688
+ desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
232
- i += esize, pg >>= esize;
689
+ desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
233
- addr += 3 * msize;
690
+ } else {
234
- } while (i & 15);
691
+ padding = pad_fcs_size;
235
- }
692
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
236
-}
693
+ padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
237
-
694
+ }
238
-static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
695
+
239
- uint32_t desc, const uintptr_t ra,
696
+ desc_bytes = (bytes_left);
240
- const int esize, const int msize,
697
+ desc.status |= RX_DESC_STATUS_LAST_DESC;
241
- sve_ldst1_tlb_fn *tlb_fn)
698
+ desc.status |= (bytes_left + padding)
242
-{
699
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
243
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
700
+ }
244
- intptr_t i, oprsz = simd_oprsz(desc);
701
+
245
- void *d1 = &env->vfp.zregs[rd];
702
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
246
- void *d2 = &env->vfp.zregs[(rd + 1) & 31];
703
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
247
- void *d3 = &env->vfp.zregs[(rd + 2) & 31];
704
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
248
- void *d4 = &env->vfp.zregs[(rd + 3) & 31];
705
+ desc_bytes);
249
-
706
+
250
- for (i = 0; i < oprsz; ) {
707
+ /* Check if frame needs to raise the receive interrupt */
251
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
708
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
252
- do {
709
+ s->int_sta |= INT_STA_RX;
253
- if (pg & 1) {
710
+ }
254
- tlb_fn(env, d1, i, addr, ra);
711
+
255
- tlb_fn(env, d2, i, addr + msize, ra);
712
+ /* Increment variables */
256
- tlb_fn(env, d3, i, addr + 2 * msize, ra);
713
+ buf += desc_bytes;
257
- tlb_fn(env, d4, i, addr + 3 * msize, ra);
714
+ bytes_left -= desc_bytes;
258
- }
715
+
259
- i += esize, pg >>= esize;
716
+ /* Move to the next descriptor */
260
- addr += 4 * msize;
717
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
261
- } while (i & 15);
718
+ if (!s->rx_desc_curr) {
262
- }
719
+ /* Not enough buffer space available */
263
-}
720
+ s->int_sta |= INT_STA_RX_BUF_UA;
264
-
721
+ s->rx_desc_curr = s->rx_desc_head;
265
-#define DO_STN_1(N, NAME, ESIZE) \
722
+ break;
266
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_r) \
723
+ }
267
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
724
+ }
268
+#define DO_STN_1(N, NAME, ESZ) \
725
+
269
+void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \
726
+ /* Report receive DMA is finished */
270
+ target_ulong addr, uint32_t desc) \
727
+ s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
271
{ \
728
+ allwinner_sun8i_emac_update_irq(s);
272
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, 1, \
729
+
273
- sve_st1##NAME##_tlb); \
730
+ return size;
274
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, \
731
+}
275
+ sve_st1##NAME##_host, sve_st1##NAME##_tlb); \
732
+
276
}
733
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
277
734
+{
278
-#define DO_STN_2(N, NAME, ESIZE, MSIZE) \
735
+ NetClientState *nc = qemu_get_queue(s->nic);
279
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_le_r) \
736
+ FrameDescriptor desc;
280
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
737
+ size_t bytes = 0;
281
+#define DO_STN_2(N, NAME, ESZ, MSZ) \
738
+ size_t packet_bytes = 0;
282
+void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \
739
+ size_t transmitted = 0;
283
+ target_ulong addr, uint32_t desc) \
740
+ static uint8_t packet_buf[2048];
284
{ \
741
+
285
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
742
+ s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
286
- sve_st1##NAME##_le_tlb); \
743
+
287
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
744
+ /* Read all transmit descriptors */
288
+ sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \
745
+ while (s->tx_desc_curr != 0) {
289
} \
746
+
290
-void QEMU_FLATTEN HELPER(sve_st##N##NAME##_be_r) \
747
+ /* Read from physical memory into packet buffer */
291
- (CPUARMState *env, void *vg, target_ulong addr, uint32_t desc) \
748
+ bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
292
+void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \
749
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
293
+ target_ulong addr, uint32_t desc) \
750
+ desc.status |= TX_DESC_STATUS_LENGTH_ERR;
294
{ \
751
+ break;
295
- sve_st##N##_r(env, vg, addr, desc, GETPC(), ESIZE, MSIZE, \
752
+ }
296
- sve_st1##NAME##_be_tlb); \
753
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
297
+ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, \
754
+ packet_bytes += bytes;
298
+ sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \
755
+ desc.status &= ~DESC_STATUS_CTL;
299
}
756
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
300
757
+
301
-DO_STN_1(1, bb, 1)
758
+ /* After the last descriptor, send the packet */
302
-DO_STN_1(1, bh, 2)
759
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
303
-DO_STN_1(1, bs, 4)
760
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
304
-DO_STN_1(1, bd, 8)
761
+ net_checksum_calculate(packet_buf, packet_bytes);
305
-DO_STN_1(2, bb, 1)
762
+ }
306
-DO_STN_1(3, bb, 1)
763
+
307
-DO_STN_1(4, bb, 1)
764
+ qemu_send_packet(nc, packet_buf, packet_bytes);
308
+DO_STN_1(1, bb, MO_8)
765
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
309
+DO_STN_1(1, bh, MO_16)
766
+ bytes);
310
+DO_STN_1(1, bs, MO_32)
767
+
311
+DO_STN_1(1, bd, MO_64)
768
+ packet_bytes = 0;
312
+DO_STN_1(2, bb, MO_8)
769
+ transmitted++;
313
+DO_STN_1(3, bb, MO_8)
770
+ }
314
+DO_STN_1(4, bb, MO_8)
771
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
315
772
+ }
316
-DO_STN_2(1, hh, 2, 2)
773
+
317
-DO_STN_2(1, hs, 4, 2)
774
+ /* Raise transmit completed interrupt */
318
-DO_STN_2(1, hd, 8, 2)
775
+ if (transmitted > 0) {
319
-DO_STN_2(2, hh, 2, 2)
776
+ s->int_sta |= INT_STA_TX;
320
-DO_STN_2(3, hh, 2, 2)
777
+ s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
321
-DO_STN_2(4, hh, 2, 2)
778
+ allwinner_sun8i_emac_update_irq(s);
322
+DO_STN_2(1, hh, MO_16, MO_16)
779
+ }
323
+DO_STN_2(1, hs, MO_32, MO_16)
780
+}
324
+DO_STN_2(1, hd, MO_64, MO_16)
781
+
325
+DO_STN_2(2, hh, MO_16, MO_16)
782
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
326
+DO_STN_2(3, hh, MO_16, MO_16)
783
+{
327
+DO_STN_2(4, hh, MO_16, MO_16)
784
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
328
785
+ NetClientState *nc = qemu_get_queue(s->nic);
329
-DO_STN_2(1, ss, 4, 4)
786
+
330
-DO_STN_2(1, sd, 8, 4)
787
+ trace_allwinner_sun8i_emac_reset();
331
-DO_STN_2(2, ss, 4, 4)
788
+
332
-DO_STN_2(3, ss, 4, 4)
789
+ s->mii_cmd = 0;
333
-DO_STN_2(4, ss, 4, 4)
790
+ s->mii_data = 0;
334
+DO_STN_2(1, ss, MO_32, MO_32)
791
+ s->basic_ctl0 = 0;
335
+DO_STN_2(1, sd, MO_64, MO_32)
792
+ s->basic_ctl1 = REG_BASIC_CTL_1_RST;
336
+DO_STN_2(2, ss, MO_32, MO_32)
793
+ s->int_en = 0;
337
+DO_STN_2(3, ss, MO_32, MO_32)
794
+ s->int_sta = 0;
338
+DO_STN_2(4, ss, MO_32, MO_32)
795
+ s->frm_flt = 0;
339
796
+ s->rx_ctl0 = 0;
340
-DO_STN_2(1, dd, 8, 8)
797
+ s->rx_ctl1 = RX_CTL1_RX_MD;
341
-DO_STN_2(2, dd, 8, 8)
798
+ s->rx_desc_head = 0;
342
-DO_STN_2(3, dd, 8, 8)
799
+ s->rx_desc_curr = 0;
343
-DO_STN_2(4, dd, 8, 8)
800
+ s->tx_ctl0 = 0;
344
+DO_STN_2(1, dd, MO_64, MO_64)
801
+ s->tx_ctl1 = 0;
345
+DO_STN_2(2, dd, MO_64, MO_64)
802
+ s->tx_desc_head = 0;
346
+DO_STN_2(3, dd, MO_64, MO_64)
803
+ s->tx_desc_curr = 0;
347
+DO_STN_2(4, dd, MO_64, MO_64)
804
+ s->tx_flowctl = 0;
348
805
+
349
#undef DO_STN_1
806
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
350
#undef DO_STN_2
807
+}
808
+
809
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
810
+ unsigned size)
811
+{
812
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
813
+ uint64_t value = 0;
814
+ FrameDescriptor desc;
815
+
816
+ switch (offset) {
817
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
818
+ value = s->basic_ctl0;
819
+ break;
820
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
821
+ value = s->basic_ctl1;
822
+ break;
823
+ case REG_INT_STA: /* Interrupt Status */
824
+ value = s->int_sta;
825
+ break;
826
+ case REG_INT_EN: /* Interupt Enable */
827
+ value = s->int_en;
828
+ break;
829
+ case REG_TX_CTL_0: /* Transmit Control 0 */
830
+ value = s->tx_ctl0;
831
+ break;
832
+ case REG_TX_CTL_1: /* Transmit Control 1 */
833
+ value = s->tx_ctl1;
834
+ break;
835
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
836
+ value = s->tx_flowctl;
837
+ break;
838
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
839
+ value = s->tx_desc_head;
840
+ break;
841
+ case REG_RX_CTL_0: /* Receive Control 0 */
842
+ value = s->rx_ctl0;
843
+ break;
844
+ case REG_RX_CTL_1: /* Receive Control 1 */
845
+ value = s->rx_ctl1;
846
+ break;
847
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
848
+ value = s->rx_desc_head;
849
+ break;
850
+ case REG_FRM_FLT: /* Receive Frame Filter */
851
+ value = s->frm_flt;
852
+ break;
853
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
854
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
855
+ break;
856
+ case REG_MII_CMD: /* Management Interface Command */
857
+ value = s->mii_cmd;
858
+ break;
859
+ case REG_MII_DATA: /* Management Interface Data */
860
+ value = s->mii_data;
861
+ break;
862
+ case REG_ADDR_HIGH: /* MAC Address High */
863
+ value = *(((uint32_t *) (s->conf.macaddr.a)) + 1);
864
+ break;
865
+ case REG_ADDR_LOW: /* MAC Address Low */
866
+ value = *(uint32_t *) (s->conf.macaddr.a);
867
+ break;
868
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
869
+ break;
870
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
871
+ value = s->tx_desc_curr;
872
+ break;
873
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
874
+ if (s->tx_desc_curr != 0) {
875
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
876
+ value = desc.addr;
877
+ } else {
878
+ value = 0;
879
+ }
880
+ break;
881
+ case REG_RX_DMA_STA: /* Receive DMA Status */
882
+ break;
883
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
884
+ value = s->rx_desc_curr;
885
+ break;
886
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
887
+ if (s->rx_desc_curr != 0) {
888
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
889
+ value = desc.addr;
890
+ } else {
891
+ value = 0;
892
+ }
893
+ break;
894
+ case REG_RGMII_STA: /* RGMII Status */
895
+ break;
896
+ default:
897
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
898
+ "EMAC register 0x" TARGET_FMT_plx "\n",
899
+ offset);
900
+ }
901
+
902
+ trace_allwinner_sun8i_emac_read(offset, value);
903
+ return value;
904
+}
905
+
906
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
907
+ uint64_t value, unsigned size)
908
+{
909
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
910
+ NetClientState *nc = qemu_get_queue(s->nic);
911
+
912
+ trace_allwinner_sun8i_emac_write(offset, value);
913
+
914
+ switch (offset) {
915
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
916
+ s->basic_ctl0 = value;
917
+ break;
918
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
919
+ if (value & BASIC_CTL1_SOFTRST) {
920
+ allwinner_sun8i_emac_reset(DEVICE(s));
921
+ value &= ~BASIC_CTL1_SOFTRST;
922
+ }
923
+ s->basic_ctl1 = value;
924
+ if (allwinner_sun8i_emac_can_receive(nc)) {
925
+ qemu_flush_queued_packets(nc);
926
+ }
927
+ break;
928
+ case REG_INT_STA: /* Interrupt Status */
929
+ s->int_sta &= ~value;
930
+ allwinner_sun8i_emac_update_irq(s);
931
+ break;
932
+ case REG_INT_EN: /* Interrupt Enable */
933
+ s->int_en = value;
934
+ allwinner_sun8i_emac_update_irq(s);
935
+ break;
936
+ case REG_TX_CTL_0: /* Transmit Control 0 */
937
+ s->tx_ctl0 = value;
938
+ break;
939
+ case REG_TX_CTL_1: /* Transmit Control 1 */
940
+ s->tx_ctl1 = value;
941
+ if (value & TX_CTL1_TX_DMA_EN) {
942
+ allwinner_sun8i_emac_transmit(s);
943
+ }
944
+ break;
945
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
946
+ s->tx_flowctl = value;
947
+ break;
948
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
949
+ s->tx_desc_head = value;
950
+ s->tx_desc_curr = value;
951
+ break;
952
+ case REG_RX_CTL_0: /* Receive Control 0 */
953
+ s->rx_ctl0 = value;
954
+ break;
955
+ case REG_RX_CTL_1: /* Receive Control 1 */
956
+ s->rx_ctl1 = value | RX_CTL1_RX_MD;
957
+ if ((value & RX_CTL1_RX_DMA_EN) &&
958
+ allwinner_sun8i_emac_can_receive(nc)) {
959
+ qemu_flush_queued_packets(nc);
960
+ }
961
+ break;
962
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
963
+ s->rx_desc_head = value;
964
+ s->rx_desc_curr = value;
965
+ break;
966
+ case REG_FRM_FLT: /* Receive Frame Filter */
967
+ s->frm_flt = value;
968
+ break;
969
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
970
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
971
+ break;
972
+ case REG_MII_CMD: /* Management Interface Command */
973
+ s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
974
+ allwinner_sun8i_emac_mii_cmd(s);
975
+ break;
976
+ case REG_MII_DATA: /* Management Interface Data */
977
+ s->mii_data = value;
978
+ break;
979
+ case REG_ADDR_HIGH: /* MAC Address High */
980
+ s->conf.macaddr.a[4] = (value & 0xff);
981
+ s->conf.macaddr.a[5] = (value & 0xff00) >> 8;
982
+ break;
983
+ case REG_ADDR_LOW: /* MAC Address Low */
984
+ s->conf.macaddr.a[0] = (value & 0xff);
985
+ s->conf.macaddr.a[1] = (value & 0xff00) >> 8;
986
+ s->conf.macaddr.a[2] = (value & 0xff0000) >> 16;
987
+ s->conf.macaddr.a[3] = (value & 0xff000000) >> 24;
988
+ break;
989
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
990
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
991
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
992
+ case REG_RX_DMA_STA: /* Receive DMA Status */
993
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
994
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
995
+ case REG_RGMII_STA: /* RGMII Status */
996
+ break;
997
+ default:
998
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
999
+ "EMAC register 0x" TARGET_FMT_plx "\n",
1000
+ offset);
1001
+ }
1002
+}
1003
+
1004
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
1005
+{
1006
+ AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
1007
+
1008
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
1009
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
1010
+}
1011
+
1012
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
1013
+ .read = allwinner_sun8i_emac_read,
1014
+ .write = allwinner_sun8i_emac_write,
1015
+ .endianness = DEVICE_NATIVE_ENDIAN,
1016
+ .valid = {
1017
+ .min_access_size = 4,
1018
+ .max_access_size = 4,
1019
+ },
1020
+ .impl.min_access_size = 4,
1021
+};
1022
+
1023
+static NetClientInfo net_allwinner_sun8i_emac_info = {
1024
+ .type = NET_CLIENT_DRIVER_NIC,
1025
+ .size = sizeof(NICState),
1026
+ .can_receive = allwinner_sun8i_emac_can_receive,
1027
+ .receive = allwinner_sun8i_emac_receive,
1028
+ .link_status_changed = allwinner_sun8i_emac_set_link,
1029
+};
1030
+
1031
+static void allwinner_sun8i_emac_init(Object *obj)
1032
+{
1033
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1034
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
1035
+
1036
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
1037
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
1038
+ sysbus_init_mmio(sbd, &s->iomem);
1039
+ sysbus_init_irq(sbd, &s->irq);
1040
+}
1041
+
1042
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
1043
+{
1044
+ AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
1045
+
1046
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
1047
+ s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
1048
+ object_get_typename(OBJECT(dev)), dev->id, s);
1049
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1050
+}
1051
+
1052
+static Property allwinner_sun8i_emac_properties[] = {
1053
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
1054
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
1055
+ DEFINE_PROP_END_OF_LIST(),
1056
+};
1057
+
1058
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
1059
+{
1060
+ AwSun8iEmacState *s = opaque;
1061
+
1062
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
1063
+
1064
+ return 0;
1065
+}
1066
+
1067
+static const VMStateDescription vmstate_aw_emac = {
1068
+ .name = "allwinner-sun8i-emac",
1069
+ .version_id = 1,
1070
+ .minimum_version_id = 1,
1071
+ .post_load = allwinner_sun8i_emac_post_load,
1072
+ .fields = (VMStateField[]) {
1073
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
1074
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
1075
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
1076
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
1077
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
1078
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
1079
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
1080
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
1081
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
1082
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
1083
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
1084
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
1085
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
1086
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
1087
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
1088
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
1089
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
1090
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
1091
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
1092
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
1093
+ VMSTATE_END_OF_LIST()
1094
+ }
1095
+};
1096
+
1097
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
1098
+{
1099
+ DeviceClass *dc = DEVICE_CLASS(klass);
1100
+
1101
+ dc->realize = allwinner_sun8i_emac_realize;
1102
+ dc->reset = allwinner_sun8i_emac_reset;
1103
+ dc->vmsd = &vmstate_aw_emac;
1104
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
1105
+}
1106
+
1107
+static const TypeInfo allwinner_sun8i_emac_info = {
1108
+ .name = TYPE_AW_SUN8I_EMAC,
1109
+ .parent = TYPE_SYS_BUS_DEVICE,
1110
+ .instance_size = sizeof(AwSun8iEmacState),
1111
+ .instance_init = allwinner_sun8i_emac_init,
1112
+ .class_init = allwinner_sun8i_emac_class_init,
1113
+};
1114
+
1115
+static void allwinner_sun8i_emac_register_types(void)
1116
+{
1117
+ type_register_static(&allwinner_sun8i_emac_info);
1118
+}
1119
+
1120
+type_init(allwinner_sun8i_emac_register_types)
1121
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
1122
index XXXXXXX..XXXXXXX 100644
1123
--- a/hw/arm/Kconfig
1124
+++ b/hw/arm/Kconfig
1125
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
1126
config ALLWINNER_H3
1127
bool
1128
select ALLWINNER_A10_PIT
1129
+ select ALLWINNER_SUN8I_EMAC
1130
select SERIAL
1131
select ARM_TIMER
1132
select ARM_GIC
1133
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/hw/net/Kconfig
1136
+++ b/hw/net/Kconfig
1137
@@ -XXX,XX +XXX,XX @@ config MIPSNET
1138
config ALLWINNER_EMAC
1139
bool
1140
1141
+config ALLWINNER_SUN8I_EMAC
1142
+ bool
1143
+
1144
config IMX_FEC
1145
bool
1146
1147
diff --git a/hw/net/trace-events b/hw/net/trace-events
1148
index XXXXXXX..XXXXXXX 100644
1149
--- a/hw/net/trace-events
1150
+++ b/hw/net/trace-events
1151
@@ -XXX,XX +XXX,XX @@
1152
# See docs/devel/tracing.txt for syntax documentation.
1153
1154
+# allwinner-sun8i-emac.c
1155
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32
1156
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32
1157
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1158
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32
1159
+allwinner_sun8i_emac_reset(void) "HW reset"
1160
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
1161
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
1162
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
1163
+
1164
# etraxfs_eth.c
1165
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
1166
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
1167
--
351
--
1168
2.20.1
352
2.20.1
1169
353
1170
354
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Let's move the code which freezes which gic-version to
3
This avoids the need for a separate set of helpers to implement
4
be applied in a dedicated function. We also now set by
4
no-fault semantics, and will enable MTE in the future.
5
default the VIRT_GIC_VERSION_NO_SET. This eventually
5
6
turns into the legacy v2 choice in the finalize() function.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20200508154359.7494-17-richard.henderson@linaro.org
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
11
Message-id: 20200311131618.7187-4-eric.auger@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
include/hw/arm/virt.h | 1 +
11
target/arm/sve_helper.c | 323 ++++++++++++++++------------------------
15
hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------
12
1 file changed, 127 insertions(+), 196 deletions(-)
16
2 files changed, 34 insertions(+), 21 deletions(-)
13
17
14
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/virt.h
16
--- a/target/arm/sve_helper.c
21
+++ b/include/hw/arm/virt.h
17
+++ b/target/arm/sve_helper.c
22
@@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType {
18
@@ -XXX,XX +XXX,XX @@ DO_LD1_ZPZ_D(dd_be, zd)
23
VIRT_GIC_VERSION_HOST,
19
24
VIRT_GIC_VERSION_2,
20
/* First fault loads with a vector index. */
25
VIRT_GIC_VERSION_3,
21
26
+ VIRT_GIC_VERSION_NOSEL,
22
-/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
27
} VirtGICType;
23
- * The controlling predicate is known to be true. Return true if the
28
24
- * load was successful.
29
typedef struct MemMapEntry {
25
- */
30
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
26
-typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
31
index XXXXXXX..XXXXXXX 100644
27
- target_ulong vaddr, int mmu_idx);
32
--- a/hw/arm/virt.c
28
-
33
+++ b/hw/arm/virt.c
29
-#ifdef CONFIG_SOFTMMU
34
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
30
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
31
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
32
- target_ulong addr, int mmu_idx) \
33
-{ \
34
- target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
35
- if (likely(next_page - addr >= sizeof(TYPEM))) { \
36
- void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
37
- if (likely(host)) { \
38
- TYPEM val = HOST(host); \
39
- *(TYPEE *)(vd + H(reg_off)) = val; \
40
- return true; \
41
- } \
42
- } \
43
- return false; \
44
-}
45
-#else
46
-#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
47
-static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
48
- target_ulong addr, int mmu_idx) \
49
-{ \
50
- if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
51
- TYPEM val = HOST(g2h(addr)); \
52
- *(TYPEE *)(vd + H(reg_off)) = val; \
53
- return true; \
54
- } \
55
- return false; \
56
-}
57
-#endif
58
-
59
-DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
60
-DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
61
-DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
62
-DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
63
-
64
-DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
65
-DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
66
-DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
67
-DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
68
-DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
69
-DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
70
-DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
71
-DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
72
-
73
-DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
74
-DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
75
-DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
76
-DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
77
-DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
78
-DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
79
-
80
-DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
81
-DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
82
-
83
/*
84
- * Common helper for all gather first-faulting loads.
85
+ * Common helpers for all gather first-faulting loads.
86
*/
87
-static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
88
- target_ulong base, uint32_t desc, uintptr_t ra,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
90
- sve_ld1_nf_fn *nonfault_fn)
91
+
92
+static inline QEMU_ALWAYS_INLINE
93
+void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
94
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
95
+ const int esz, const int msz, zreg_off_fn *off_fn,
96
+ sve_ldst1_host_fn *host_fn,
97
+ sve_ldst1_tlb_fn *tlb_fn)
98
{
99
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
100
- const int mmu_idx = get_mmuidx(oi);
101
+ const int mmu_idx = cpu_mmu_index(env, false);
102
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
103
- intptr_t reg_off, reg_max = simd_oprsz(desc);
104
- target_ulong addr;
105
+ const int esize = 1 << esz;
106
+ const int msize = 1 << msz;
107
+ const intptr_t reg_max = simd_oprsz(desc);
108
+ intptr_t reg_off;
109
+ SVEHostPage info;
110
+ target_ulong addr, in_page;
111
112
/* Skip to the first true predicate. */
113
- reg_off = find_next_active(vg, 0, reg_max, MO_32);
114
- if (likely(reg_off < reg_max)) {
115
- /* Perform one normal read, which will fault or not. */
116
- addr = off_fn(vm, reg_off);
117
- addr = base + (addr << scale);
118
- tlb_fn(env, vd, reg_off, addr, ra);
119
-
120
- /* The rest of the reads will be non-faulting. */
121
+ reg_off = find_next_active(vg, 0, reg_max, esz);
122
+ if (unlikely(reg_off >= reg_max)) {
123
+ /* The entire predicate was false; no load occurs. */
124
+ memset(vd, 0, reg_max);
125
+ return;
35
}
126
}
127
128
- /* After any fault, zero the leading predicated false elements. */
129
+ /*
130
+ * Probe the first element, allowing faults.
131
+ */
132
+ addr = base + (off_fn(vm, reg_off) << scale);
133
+ tlb_fn(env, vd, reg_off, addr, retaddr);
134
+
135
+ /* After any fault, zero the other elements. */
136
swap_memzero(vd, reg_off);
137
+ reg_off += esize;
138
+ swap_memzero(vd + reg_off, reg_max - reg_off);
139
140
- while (likely((reg_off += 4) < reg_max)) {
141
- uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
142
- if (likely((pg >> (reg_off & 63)) & 1)) {
143
- addr = off_fn(vm, reg_off);
144
- addr = base + (addr << scale);
145
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
146
- record_fault(env, reg_off, reg_max);
147
- break;
148
+ /*
149
+ * Probe the remaining elements, not allowing faults.
150
+ */
151
+ while (reg_off < reg_max) {
152
+ uint64_t pg = vg[reg_off >> 6];
153
+ do {
154
+ if (likely((pg >> (reg_off & 63)) & 1)) {
155
+ addr = base + (off_fn(vm, reg_off) << scale);
156
+ in_page = -(addr | TARGET_PAGE_MASK);
157
+
158
+ if (unlikely(in_page < msize)) {
159
+ /* Stop if the element crosses a page boundary. */
160
+ goto fault;
161
+ }
162
+
163
+ sve_probe_page(&info, true, env, addr, 0, MMU_DATA_LOAD,
164
+ mmu_idx, retaddr);
165
+ if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) {
166
+ goto fault;
167
+ }
168
+ if (unlikely(info.flags & TLB_WATCHPOINT) &&
169
+ (cpu_watchpoint_address_matches
170
+ (env_cpu(env), addr, msize) & BP_MEM_READ)) {
171
+ goto fault;
172
+ }
173
+ /* TODO: MTE check. */
174
+
175
+ host_fn(vd, reg_off, info.host);
176
}
177
- } else {
178
- *(uint32_t *)(vd + H1_4(reg_off)) = 0;
179
- }
180
+ reg_off += esize;
181
+ } while (reg_off & 63);
182
}
183
+ return;
184
+
185
+ fault:
186
+ record_fault(env, reg_off, reg_max);
36
}
187
}
37
188
38
+/*
189
-static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
39
+ * finalize_gic_version - Determines the final gic_version
190
- target_ulong base, uint32_t desc, uintptr_t ra,
40
+ * according to the gic-version property
191
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
41
+ *
192
- sve_ld1_nf_fn *nonfault_fn)
42
+ * Default GIC type is v2
193
-{
43
+ */
194
- const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
44
+static void finalize_gic_version(VirtMachineState *vms)
195
- const int mmu_idx = get_mmuidx(oi);
45
+{
196
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
46
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
197
- intptr_t reg_off, reg_max = simd_oprsz(desc);
47
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
198
- target_ulong addr;
48
+ if (!kvm_enabled()) {
199
-
49
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
200
- /* Skip to the first true predicate. */
50
+ error_report("gic-version=host requires KVM");
201
- reg_off = find_next_active(vg, 0, reg_max, MO_64);
51
+ exit(1);
202
- if (likely(reg_off < reg_max)) {
52
+ } else {
203
- /* Perform one normal read, which will fault or not. */
53
+ /* "max": currently means 3 for TCG */
204
- addr = off_fn(vm, reg_off);
54
+ vms->gic_version = VIRT_GIC_VERSION_3;
205
- addr = base + (addr << scale);
55
+ }
206
- tlb_fn(env, vd, reg_off, addr, ra);
56
+ } else {
207
-
57
+ vms->gic_version = kvm_arm_vgic_probe();
208
- /* The rest of the reads will be non-faulting. */
58
+ if (!vms->gic_version) {
209
- }
59
+ error_report(
210
-
60
+ "Unable to determine GIC version supported by host");
211
- /* After any fault, zero the leading predicated false elements. */
61
+ exit(1);
212
- swap_memzero(vd, reg_off);
62
+ }
213
-
63
+ }
214
- while (likely((reg_off += 8) < reg_max)) {
64
+ } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
215
- uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
65
+ vms->gic_version = VIRT_GIC_VERSION_2;
216
- if (likely(pg & 1)) {
66
+ }
217
- addr = off_fn(vm, reg_off);
67
+}
218
- addr = base + (addr << scale);
68
+
219
- if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
69
static void machvirt_init(MachineState *machine)
220
- record_fault(env, reg_off, reg_max);
70
{
221
- break;
71
VirtMachineState *vms = VIRT_MACHINE(machine);
72
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
73
/* We can probe only here because during property set
74
* KVM is not available yet
75
*/
76
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
77
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
78
- if (!kvm_enabled()) {
79
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
80
- error_report("gic-version=host requires KVM");
81
- exit(1);
82
- } else {
83
- /* "max": currently means 3 for TCG */
84
- vms->gic_version = VIRT_GIC_VERSION_3;
85
- }
222
- }
86
- } else {
223
- } else {
87
- vms->gic_version = kvm_arm_vgic_probe();
224
- *(uint64_t *)(vd + reg_off) = 0;
88
- if (!vms->gic_version) {
89
- error_report(
90
- "Unable to determine GIC version supported by host");
91
- exit(1);
92
- }
93
- }
225
- }
94
- }
226
- }
95
+ finalize_gic_version(vms);
227
+#define DO_LDFF1_ZPZ_S(MEM, OFS, MSZ) \
96
228
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
97
if (!cpu_type_valid(machine->cpu_type)) {
229
+ void *vm, target_ulong base, uint32_t desc) \
98
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
230
+{ \
99
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
231
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_32, MSZ, \
100
"Set on/off to enable/disable using "
232
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
101
"physical address space above 32 bits",
233
}
102
NULL);
234
103
- /* Default GIC type is v2 */
235
-#define DO_LDFF1_ZPZ_S(MEM, OFS) \
104
- vms->gic_version = VIRT_GIC_VERSION_2;
236
-void HELPER(sve_ldff##MEM##_##OFS) \
105
+ vms->gic_version = VIRT_GIC_VERSION_NOSEL;
237
- (CPUARMState *env, void *vd, void *vg, void *vm, \
106
object_property_add_str(obj, "gic-version", virt_get_gic_version,
238
- target_ulong base, uint32_t desc) \
107
virt_set_gic_version, NULL);
239
-{ \
108
object_property_set_description(obj, "gic-version",
240
- sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
241
- off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
242
+#define DO_LDFF1_ZPZ_D(MEM, OFS, MSZ) \
243
+void HELPER(sve_ldff##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
244
+ void *vm, target_ulong base, uint32_t desc) \
245
+{ \
246
+ sve_ldff1_z(env, vd, vg, vm, base, desc, GETPC(), MO_64, MSZ, \
247
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
248
}
249
250
-#define DO_LDFF1_ZPZ_D(MEM, OFS) \
251
-void HELPER(sve_ldff##MEM##_##OFS) \
252
- (CPUARMState *env, void *vd, void *vg, void *vm, \
253
- target_ulong base, uint32_t desc) \
254
-{ \
255
- sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
256
- off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
257
-}
258
+DO_LDFF1_ZPZ_S(bsu, zsu, MO_8)
259
+DO_LDFF1_ZPZ_S(bsu, zss, MO_8)
260
+DO_LDFF1_ZPZ_D(bdu, zsu, MO_8)
261
+DO_LDFF1_ZPZ_D(bdu, zss, MO_8)
262
+DO_LDFF1_ZPZ_D(bdu, zd, MO_8)
263
264
-DO_LDFF1_ZPZ_S(bsu, zsu)
265
-DO_LDFF1_ZPZ_S(bsu, zss)
266
-DO_LDFF1_ZPZ_D(bdu, zsu)
267
-DO_LDFF1_ZPZ_D(bdu, zss)
268
-DO_LDFF1_ZPZ_D(bdu, zd)
269
+DO_LDFF1_ZPZ_S(bss, zsu, MO_8)
270
+DO_LDFF1_ZPZ_S(bss, zss, MO_8)
271
+DO_LDFF1_ZPZ_D(bds, zsu, MO_8)
272
+DO_LDFF1_ZPZ_D(bds, zss, MO_8)
273
+DO_LDFF1_ZPZ_D(bds, zd, MO_8)
274
275
-DO_LDFF1_ZPZ_S(bss, zsu)
276
-DO_LDFF1_ZPZ_S(bss, zss)
277
-DO_LDFF1_ZPZ_D(bds, zsu)
278
-DO_LDFF1_ZPZ_D(bds, zss)
279
-DO_LDFF1_ZPZ_D(bds, zd)
280
+DO_LDFF1_ZPZ_S(hsu_le, zsu, MO_16)
281
+DO_LDFF1_ZPZ_S(hsu_le, zss, MO_16)
282
+DO_LDFF1_ZPZ_D(hdu_le, zsu, MO_16)
283
+DO_LDFF1_ZPZ_D(hdu_le, zss, MO_16)
284
+DO_LDFF1_ZPZ_D(hdu_le, zd, MO_16)
285
286
-DO_LDFF1_ZPZ_S(hsu_le, zsu)
287
-DO_LDFF1_ZPZ_S(hsu_le, zss)
288
-DO_LDFF1_ZPZ_D(hdu_le, zsu)
289
-DO_LDFF1_ZPZ_D(hdu_le, zss)
290
-DO_LDFF1_ZPZ_D(hdu_le, zd)
291
+DO_LDFF1_ZPZ_S(hsu_be, zsu, MO_16)
292
+DO_LDFF1_ZPZ_S(hsu_be, zss, MO_16)
293
+DO_LDFF1_ZPZ_D(hdu_be, zsu, MO_16)
294
+DO_LDFF1_ZPZ_D(hdu_be, zss, MO_16)
295
+DO_LDFF1_ZPZ_D(hdu_be, zd, MO_16)
296
297
-DO_LDFF1_ZPZ_S(hsu_be, zsu)
298
-DO_LDFF1_ZPZ_S(hsu_be, zss)
299
-DO_LDFF1_ZPZ_D(hdu_be, zsu)
300
-DO_LDFF1_ZPZ_D(hdu_be, zss)
301
-DO_LDFF1_ZPZ_D(hdu_be, zd)
302
+DO_LDFF1_ZPZ_S(hss_le, zsu, MO_16)
303
+DO_LDFF1_ZPZ_S(hss_le, zss, MO_16)
304
+DO_LDFF1_ZPZ_D(hds_le, zsu, MO_16)
305
+DO_LDFF1_ZPZ_D(hds_le, zss, MO_16)
306
+DO_LDFF1_ZPZ_D(hds_le, zd, MO_16)
307
308
-DO_LDFF1_ZPZ_S(hss_le, zsu)
309
-DO_LDFF1_ZPZ_S(hss_le, zss)
310
-DO_LDFF1_ZPZ_D(hds_le, zsu)
311
-DO_LDFF1_ZPZ_D(hds_le, zss)
312
-DO_LDFF1_ZPZ_D(hds_le, zd)
313
+DO_LDFF1_ZPZ_S(hss_be, zsu, MO_16)
314
+DO_LDFF1_ZPZ_S(hss_be, zss, MO_16)
315
+DO_LDFF1_ZPZ_D(hds_be, zsu, MO_16)
316
+DO_LDFF1_ZPZ_D(hds_be, zss, MO_16)
317
+DO_LDFF1_ZPZ_D(hds_be, zd, MO_16)
318
319
-DO_LDFF1_ZPZ_S(hss_be, zsu)
320
-DO_LDFF1_ZPZ_S(hss_be, zss)
321
-DO_LDFF1_ZPZ_D(hds_be, zsu)
322
-DO_LDFF1_ZPZ_D(hds_be, zss)
323
-DO_LDFF1_ZPZ_D(hds_be, zd)
324
+DO_LDFF1_ZPZ_S(ss_le, zsu, MO_32)
325
+DO_LDFF1_ZPZ_S(ss_le, zss, MO_32)
326
+DO_LDFF1_ZPZ_D(sdu_le, zsu, MO_32)
327
+DO_LDFF1_ZPZ_D(sdu_le, zss, MO_32)
328
+DO_LDFF1_ZPZ_D(sdu_le, zd, MO_32)
329
330
-DO_LDFF1_ZPZ_S(ss_le, zsu)
331
-DO_LDFF1_ZPZ_S(ss_le, zss)
332
-DO_LDFF1_ZPZ_D(sdu_le, zsu)
333
-DO_LDFF1_ZPZ_D(sdu_le, zss)
334
-DO_LDFF1_ZPZ_D(sdu_le, zd)
335
+DO_LDFF1_ZPZ_S(ss_be, zsu, MO_32)
336
+DO_LDFF1_ZPZ_S(ss_be, zss, MO_32)
337
+DO_LDFF1_ZPZ_D(sdu_be, zsu, MO_32)
338
+DO_LDFF1_ZPZ_D(sdu_be, zss, MO_32)
339
+DO_LDFF1_ZPZ_D(sdu_be, zd, MO_32)
340
341
-DO_LDFF1_ZPZ_S(ss_be, zsu)
342
-DO_LDFF1_ZPZ_S(ss_be, zss)
343
-DO_LDFF1_ZPZ_D(sdu_be, zsu)
344
-DO_LDFF1_ZPZ_D(sdu_be, zss)
345
-DO_LDFF1_ZPZ_D(sdu_be, zd)
346
+DO_LDFF1_ZPZ_D(sds_le, zsu, MO_32)
347
+DO_LDFF1_ZPZ_D(sds_le, zss, MO_32)
348
+DO_LDFF1_ZPZ_D(sds_le, zd, MO_32)
349
350
-DO_LDFF1_ZPZ_D(sds_le, zsu)
351
-DO_LDFF1_ZPZ_D(sds_le, zss)
352
-DO_LDFF1_ZPZ_D(sds_le, zd)
353
+DO_LDFF1_ZPZ_D(sds_be, zsu, MO_32)
354
+DO_LDFF1_ZPZ_D(sds_be, zss, MO_32)
355
+DO_LDFF1_ZPZ_D(sds_be, zd, MO_32)
356
357
-DO_LDFF1_ZPZ_D(sds_be, zsu)
358
-DO_LDFF1_ZPZ_D(sds_be, zss)
359
-DO_LDFF1_ZPZ_D(sds_be, zd)
360
+DO_LDFF1_ZPZ_D(dd_le, zsu, MO_64)
361
+DO_LDFF1_ZPZ_D(dd_le, zss, MO_64)
362
+DO_LDFF1_ZPZ_D(dd_le, zd, MO_64)
363
364
-DO_LDFF1_ZPZ_D(dd_le, zsu)
365
-DO_LDFF1_ZPZ_D(dd_le, zss)
366
-DO_LDFF1_ZPZ_D(dd_le, zd)
367
-
368
-DO_LDFF1_ZPZ_D(dd_be, zsu)
369
-DO_LDFF1_ZPZ_D(dd_be, zss)
370
-DO_LDFF1_ZPZ_D(dd_be, zd)
371
+DO_LDFF1_ZPZ_D(dd_be, zsu, MO_64)
372
+DO_LDFF1_ZPZ_D(dd_be, zss, MO_64)
373
+DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
374
375
/* Stores with a vector index. */
376
109
--
377
--
110
2.20.1
378
2.20.1
111
379
112
380
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
for non-volatile system date and time keeping. This commit adds a generic
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
5
Message-id: 20200508154359.7494-18-richard.henderson@linaro.org
6
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
7
The following RTC functionality and features are implemented:
8
9
* Year-Month-Day read/write
10
* Hour-Minute-Second read/write
11
* General Purpose storage
12
13
The following boards are extended with the RTC device:
14
15
* Cubieboard (hw/arm/cubieboard.c)
16
* Orange Pi PC (hw/arm/orangepi.c)
17
18
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
7
---
23
hw/rtc/Makefile.objs | 1 +
8
target/arm/sve_helper.c | 182 ++++++++++++++++++++++++----------------
24
include/hw/arm/allwinner-a10.h | 2 +
9
1 file changed, 111 insertions(+), 71 deletions(-)
25
include/hw/arm/allwinner-h3.h | 3 +
10
26
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
27
hw/arm/allwinner-a10.c | 8 +
28
hw/arm/allwinner-h3.c | 9 +-
29
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
30
hw/rtc/trace-events | 4 +
31
8 files changed, 571 insertions(+), 1 deletion(-)
32
create mode 100644 include/hw/rtc/allwinner-rtc.h
33
create mode 100644 hw/rtc/allwinner-rtc.c
34
35
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
36
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/rtc/Makefile.objs
13
--- a/target/arm/sve_helper.c
38
+++ b/hw/rtc/Makefile.objs
14
+++ b/target/arm/sve_helper.c
39
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
15
@@ -XXX,XX +XXX,XX @@ DO_LDFF1_ZPZ_D(dd_be, zd, MO_64)
40
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
16
41
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o
17
/* Stores with a vector index. */
42
common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o
18
43
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o
19
-static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
44
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
20
- target_ulong base, uint32_t desc, uintptr_t ra,
45
index XXXXXXX..XXXXXXX 100644
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
46
--- a/include/hw/arm/allwinner-a10.h
22
+static inline QEMU_ALWAYS_INLINE
47
+++ b/include/hw/arm/allwinner-a10.h
23
+void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
48
@@ -XXX,XX +XXX,XX @@
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
49
#include "hw/ide/ahci.h"
25
+ int esize, int msize, zreg_off_fn *off_fn,
50
#include "hw/usb/hcd-ohci.h"
26
+ sve_ldst1_host_fn *host_fn,
51
#include "hw/usb/hcd-ehci.h"
27
+ sve_ldst1_tlb_fn *tlb_fn)
52
+#include "hw/rtc/allwinner-rtc.h"
28
{
53
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
54
#include "target/arm/cpu.h"
30
- intptr_t i, oprsz = simd_oprsz(desc);
55
31
+ const int mmu_idx = cpu_mmu_index(env, false);
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
32
+ const intptr_t reg_max = simd_oprsz(desc);
57
AwEmacState emac;
33
+ void *host[ARM_MAX_VQ * 4];
58
AllwinnerAHCIState sata;
34
+ intptr_t reg_off, i;
59
AwSdHostState mmc0;
35
+ SVEHostPage info, info2;
60
+ AwRtcState rtc;
36
61
MemoryRegion sram_a;
37
- for (i = 0; i < oprsz; ) {
62
EHCISysBusState ehci[AW_A10_NUM_USB];
38
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
63
OHCISysBusState ohci[AW_A10_NUM_USB];
39
+ /*
64
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
40
+ * Probe all of the elements for host addresses and flags.
65
index XXXXXXX..XXXXXXX 100644
41
+ */
66
--- a/include/hw/arm/allwinner-h3.h
42
+ i = reg_off = 0;
67
+++ b/include/hw/arm/allwinner-h3.h
43
+ do {
68
@@ -XXX,XX +XXX,XX @@
44
+ uint64_t pg = vg[reg_off >> 6];
69
#include "hw/misc/allwinner-sid.h"
45
do {
70
#include "hw/sd/allwinner-sdhost.h"
46
- if (likely(pg & 1)) {
71
#include "hw/net/allwinner-sun8i-emac.h"
47
- target_ulong off = off_fn(vm, i);
72
+#include "hw/rtc/allwinner-rtc.h"
48
- tlb_fn(env, vd, i, base + (off << scale), ra);
73
#include "target/arm/cpu.h"
49
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
74
#include "sysemu/block-backend.h"
50
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
75
76
@@ -XXX,XX +XXX,XX @@ enum {
77
AW_H3_GIC_CPU,
78
AW_H3_GIC_HYP,
79
AW_H3_GIC_VCPU,
80
+ AW_H3_RTC,
81
AW_H3_CPUCFG,
82
AW_H3_SDRAM
83
};
84
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
85
AwSidState sid;
86
AwSdHostState mmc0;
87
AwSun8iEmacState emac;
88
+ AwRtcState rtc;
89
GICState gic;
90
MemoryRegion sram_a1;
91
MemoryRegion sram_a2;
92
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
93
new file mode 100644
94
index XXXXXXX..XXXXXXX
95
--- /dev/null
96
+++ b/include/hw/rtc/allwinner-rtc.h
97
@@ -XXX,XX +XXX,XX @@
98
+/*
99
+ * Allwinner Real Time Clock emulation
100
+ *
101
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
102
+ *
103
+ * This program is free software: you can redistribute it and/or modify
104
+ * it under the terms of the GNU General Public License as published by
105
+ * the Free Software Foundation, either version 2 of the License, or
106
+ * (at your option) any later version.
107
+ *
108
+ * This program is distributed in the hope that it will be useful,
109
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
110
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
111
+ * GNU General Public License for more details.
112
+ *
113
+ * You should have received a copy of the GNU General Public License
114
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
115
+ */
116
+
51
+
117
+#ifndef HW_MISC_ALLWINNER_RTC_H
52
+ host[i] = NULL;
118
+#define HW_MISC_ALLWINNER_RTC_H
53
+ if (likely((pg >> (reg_off & 63)) & 1)) {
54
+ if (likely(in_page >= msize)) {
55
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_STORE,
56
+ mmu_idx, retaddr);
57
+ host[i] = info.host;
58
+ } else {
59
+ /*
60
+ * Element crosses the page boundary.
61
+ * Probe both pages, but do not record the host address,
62
+ * so that we use the slow path.
63
+ */
64
+ sve_probe_page(&info, false, env, addr, 0,
65
+ MMU_DATA_STORE, mmu_idx, retaddr);
66
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
67
+ MMU_DATA_STORE, mmu_idx, retaddr);
68
+ info.flags |= info2.flags;
69
+ }
119
+
70
+
120
+#include "qom/object.h"
71
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
121
+#include "hw/sysbus.h"
72
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
122
+
73
+ info.attrs, BP_MEM_WRITE, retaddr);
123
+/**
74
+ }
124
+ * Constants
75
+ /* TODO: MTE check. */
125
+ * @{
76
}
126
+ */
77
- i += 4, pg >>= 4;
127
+
78
- } while (i & 15);
128
+/** Highest register address used by RTC device */
79
- }
129
+#define AW_RTC_REGS_MAXADDR (0x200)
80
-}
130
+
81
+ i += 1;
131
+/** Total number of known registers */
82
+ reg_off += esize;
132
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
83
+ } while (reg_off & 63);
133
+
84
+ } while (reg_off < reg_max);
134
+/** @} */
85
135
+
86
-static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
136
+/**
87
- target_ulong base, uint32_t desc, uintptr_t ra,
137
+ * Object model types
88
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
138
+ * @{
89
-{
139
+ */
90
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
140
+
91
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
141
+/** Generic Allwinner RTC device (abstract) */
92
-
142
+#define TYPE_AW_RTC "allwinner-rtc"
93
- for (i = 0; i < oprsz; i++) {
143
+
94
- uint8_t pg = *(uint8_t *)(vg + H1(i));
144
+/** Allwinner RTC sun4i family (A10, A12) */
95
- if (likely(pg & 1)) {
145
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
96
- target_ulong off = off_fn(vm, i * 8);
146
+
97
- tlb_fn(env, vd, i * 8, base + (off << scale), ra);
147
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
98
+ /*
148
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
99
+ * Now that we have recognized all exceptions except SyncExternal
149
+
100
+ * (from TLB_MMIO), which we cannot avoid, perform all of the stores.
150
+/** Allwinner RTC sun7i family (A20) */
151
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
152
+
153
+/** @} */
154
+
155
+/**
156
+ * Object model macros
157
+ * @{
158
+ */
159
+
160
+#define AW_RTC(obj) \
161
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
162
+#define AW_RTC_CLASS(klass) \
163
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
164
+#define AW_RTC_GET_CLASS(obj) \
165
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
166
+
167
+/** @} */
168
+
169
+/**
170
+ * Allwinner RTC per-object instance state.
171
+ */
172
+typedef struct AwRtcState {
173
+ /*< private >*/
174
+ SysBusDevice parent_obj;
175
+ /*< public >*/
176
+
177
+ /**
178
+ * Actual year represented by the device when year counter is zero
179
+ *
101
+ *
180
+ * Can be overridden by the user using the corresponding 'base-year'
102
+ * Note for the common case of an element in RAM, not crossing a page
181
+ * property. The base year used by the target OS driver can vary, for
103
+ * boundary, we have stored the host address in host[]. This doubles
182
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
104
+ * as a first-level check against the predicate, since only enabled
105
+ * elements have non-null host addresses.
183
+ */
106
+ */
184
+ int base_year;
107
+ i = reg_off = 0;
185
+
108
+ do {
186
+ /** Maps I/O registers in physical memory */
109
+ void *h = host[i];
187
+ MemoryRegion iomem;
110
+ if (likely(h != NULL)) {
188
+
111
+ host_fn(vd, reg_off, h);
189
+ /** Array of hardware registers */
112
+ } else if ((vg[reg_off >> 6] >> (reg_off & 63)) & 1) {
190
+ uint32_t regs[AW_RTC_REGS_NUM];
113
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
191
+
114
+ tlb_fn(env, vd, reg_off, addr, retaddr);
192
+} AwRtcState;
115
}
193
+
116
- }
194
+/**
117
+ i += 1;
195
+ * Allwinner RTC class-level struct.
118
+ reg_off += esize;
196
+ *
119
+ } while (reg_off < reg_max);
197
+ * This struct is filled by each sunxi device specific code
198
+ * such that the generic code can use this struct to support
199
+ * all devices.
200
+ */
201
+typedef struct AwRtcClass {
202
+ /*< private >*/
203
+ SysBusDeviceClass parent_class;
204
+ /*< public >*/
205
+
206
+ /** Defines device specific register map */
207
+ const uint8_t *regmap;
208
+
209
+ /** Size of the regmap in bytes */
210
+ size_t regmap_size;
211
+
212
+ /**
213
+ * Read device specific register
214
+ *
215
+ * @offset: register offset to read
216
+ * @return true if register read successful, false otherwise
217
+ */
218
+ bool (*read)(AwRtcState *s, uint32_t offset);
219
+
220
+ /**
221
+ * Write device specific register
222
+ *
223
+ * @offset: register offset to write
224
+ * @data: value to set in register
225
+ * @return true if register write successful, false otherwise
226
+ */
227
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
228
+
229
+} AwRtcClass;
230
+
231
+#endif /* HW_MISC_ALLWINNER_RTC_H */
232
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/arm/allwinner-a10.c
235
+++ b/hw/arm/allwinner-a10.c
236
@@ -XXX,XX +XXX,XX @@
237
#define AW_A10_EHCI_BASE 0x01c14000
238
#define AW_A10_OHCI_BASE 0x01c14400
239
#define AW_A10_SATA_BASE 0x01c18000
240
+#define AW_A10_RTC_BASE 0x01c20d00
241
242
static void aw_a10_init(Object *obj)
243
{
244
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
245
246
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
247
TYPE_AW_SDHOST_SUN4I);
248
+
249
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
250
+ TYPE_AW_RTC_SUN4I);
251
}
120
}
252
121
253
static void aw_a10_realize(DeviceState *dev, Error **errp)
122
-#define DO_ST1_ZPZ_S(MEM, OFS) \
254
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
123
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
255
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
124
- (CPUARMState *env, void *vd, void *vg, void *vm, \
256
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
125
- target_ulong base, uint32_t desc) \
257
"sd-bus", &error_abort);
126
-{ \
258
+
127
- sve_st1_zs(env, vd, vg, vm, base, desc, GETPC(), \
259
+ /* RTC */
128
- off_##OFS##_s, sve_st1##MEM##_tlb); \
260
+ qdev_init_nofail(DEVICE(&s->rtc));
129
+#define DO_ST1_ZPZ_S(MEM, OFS, MSZ) \
261
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
130
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
131
+ void *vm, target_ulong base, uint32_t desc) \
132
+{ \
133
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
134
+ off_##OFS##_s, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
262
}
135
}
263
136
264
static void aw_a10_class_init(ObjectClass *oc, void *data)
137
-#define DO_ST1_ZPZ_D(MEM, OFS) \
265
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
138
-void QEMU_FLATTEN HELPER(sve_st##MEM##_##OFS) \
266
index XXXXXXX..XXXXXXX 100644
139
- (CPUARMState *env, void *vd, void *vg, void *vm, \
267
--- a/hw/arm/allwinner-h3.c
140
- target_ulong base, uint32_t desc) \
268
+++ b/hw/arm/allwinner-h3.c
141
-{ \
269
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
142
- sve_st1_zd(env, vd, vg, vm, base, desc, GETPC(), \
270
[AW_H3_GIC_CPU] = 0x01c82000,
143
- off_##OFS##_d, sve_st1##MEM##_tlb); \
271
[AW_H3_GIC_HYP] = 0x01c84000,
144
+#define DO_ST1_ZPZ_D(MEM, OFS, MSZ) \
272
[AW_H3_GIC_VCPU] = 0x01c86000,
145
+void HELPER(sve_st##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
273
+ [AW_H3_RTC] = 0x01f00000,
146
+ void *vm, target_ulong base, uint32_t desc) \
274
[AW_H3_CPUCFG] = 0x01f01c00,
147
+{ \
275
[AW_H3_SDRAM] = 0x40000000
148
+ sve_st1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
276
};
149
+ off_##OFS##_d, sve_st1##MEM##_host, sve_st1##MEM##_tlb); \
277
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
278
{ "csi", 0x01cb0000, 320 * KiB },
279
{ "tve", 0x01e00000, 64 * KiB },
280
{ "hdmi", 0x01ee0000, 128 * KiB },
281
- { "rtc", 0x01f00000, 1 * KiB },
282
{ "r_timer", 0x01f00800, 1 * KiB },
283
{ "r_intc", 0x01f00c00, 1 * KiB },
284
{ "r_wdog", 0x01f01000, 1 * KiB },
285
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
286
"ram-addr", &error_abort);
287
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
288
"ram-size", &error_abort);
289
+
290
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
291
+ TYPE_AW_RTC_SUN6I);
292
}
150
}
293
151
294
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
152
-DO_ST1_ZPZ_S(bs, zsu)
295
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
153
-DO_ST1_ZPZ_S(hs_le, zsu)
296
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
154
-DO_ST1_ZPZ_S(hs_be, zsu)
297
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
155
-DO_ST1_ZPZ_S(ss_le, zsu)
298
156
-DO_ST1_ZPZ_S(ss_be, zsu)
299
+ /* RTC */
157
+DO_ST1_ZPZ_S(bs, zsu, MO_8)
300
+ qdev_init_nofail(DEVICE(&s->rtc));
158
+DO_ST1_ZPZ_S(hs_le, zsu, MO_16)
301
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
159
+DO_ST1_ZPZ_S(hs_be, zsu, MO_16)
302
+
160
+DO_ST1_ZPZ_S(ss_le, zsu, MO_32)
303
/* Unimplemented devices */
161
+DO_ST1_ZPZ_S(ss_be, zsu, MO_32)
304
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
162
305
create_unimplemented_device(unimplemented[i].device_name,
163
-DO_ST1_ZPZ_S(bs, zss)
306
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
164
-DO_ST1_ZPZ_S(hs_le, zss)
307
new file mode 100644
165
-DO_ST1_ZPZ_S(hs_be, zss)
308
index XXXXXXX..XXXXXXX
166
-DO_ST1_ZPZ_S(ss_le, zss)
309
--- /dev/null
167
-DO_ST1_ZPZ_S(ss_be, zss)
310
+++ b/hw/rtc/allwinner-rtc.c
168
+DO_ST1_ZPZ_S(bs, zss, MO_8)
311
@@ -XXX,XX +XXX,XX @@
169
+DO_ST1_ZPZ_S(hs_le, zss, MO_16)
312
+/*
170
+DO_ST1_ZPZ_S(hs_be, zss, MO_16)
313
+ * Allwinner Real Time Clock emulation
171
+DO_ST1_ZPZ_S(ss_le, zss, MO_32)
314
+ *
172
+DO_ST1_ZPZ_S(ss_be, zss, MO_32)
315
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
173
316
+ *
174
-DO_ST1_ZPZ_D(bd, zsu)
317
+ * This program is free software: you can redistribute it and/or modify
175
-DO_ST1_ZPZ_D(hd_le, zsu)
318
+ * it under the terms of the GNU General Public License as published by
176
-DO_ST1_ZPZ_D(hd_be, zsu)
319
+ * the Free Software Foundation, either version 2 of the License, or
177
-DO_ST1_ZPZ_D(sd_le, zsu)
320
+ * (at your option) any later version.
178
-DO_ST1_ZPZ_D(sd_be, zsu)
321
+ *
179
-DO_ST1_ZPZ_D(dd_le, zsu)
322
+ * This program is distributed in the hope that it will be useful,
180
-DO_ST1_ZPZ_D(dd_be, zsu)
323
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
181
+DO_ST1_ZPZ_D(bd, zsu, MO_8)
324
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
182
+DO_ST1_ZPZ_D(hd_le, zsu, MO_16)
325
+ * GNU General Public License for more details.
183
+DO_ST1_ZPZ_D(hd_be, zsu, MO_16)
326
+ *
184
+DO_ST1_ZPZ_D(sd_le, zsu, MO_32)
327
+ * You should have received a copy of the GNU General Public License
185
+DO_ST1_ZPZ_D(sd_be, zsu, MO_32)
328
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
186
+DO_ST1_ZPZ_D(dd_le, zsu, MO_64)
329
+ */
187
+DO_ST1_ZPZ_D(dd_be, zsu, MO_64)
330
+
188
331
+#include "qemu/osdep.h"
189
-DO_ST1_ZPZ_D(bd, zss)
332
+#include "qemu/units.h"
190
-DO_ST1_ZPZ_D(hd_le, zss)
333
+#include "hw/sysbus.h"
191
-DO_ST1_ZPZ_D(hd_be, zss)
334
+#include "migration/vmstate.h"
192
-DO_ST1_ZPZ_D(sd_le, zss)
335
+#include "qemu/log.h"
193
-DO_ST1_ZPZ_D(sd_be, zss)
336
+#include "qemu/module.h"
194
-DO_ST1_ZPZ_D(dd_le, zss)
337
+#include "qemu-common.h"
195
-DO_ST1_ZPZ_D(dd_be, zss)
338
+#include "hw/qdev-properties.h"
196
+DO_ST1_ZPZ_D(bd, zss, MO_8)
339
+#include "hw/rtc/allwinner-rtc.h"
197
+DO_ST1_ZPZ_D(hd_le, zss, MO_16)
340
+#include "trace.h"
198
+DO_ST1_ZPZ_D(hd_be, zss, MO_16)
341
+
199
+DO_ST1_ZPZ_D(sd_le, zss, MO_32)
342
+/* RTC registers */
200
+DO_ST1_ZPZ_D(sd_be, zss, MO_32)
343
+enum {
201
+DO_ST1_ZPZ_D(dd_le, zss, MO_64)
344
+ REG_LOSC = 1, /* Low Oscillator Control */
202
+DO_ST1_ZPZ_D(dd_be, zss, MO_64)
345
+ REG_YYMMDD, /* RTC Year-Month-Day */
203
346
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
204
-DO_ST1_ZPZ_D(bd, zd)
347
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
205
-DO_ST1_ZPZ_D(hd_le, zd)
348
+ REG_ALARM1_EN, /* Alarm1 Enable */
206
-DO_ST1_ZPZ_D(hd_be, zd)
349
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
207
-DO_ST1_ZPZ_D(sd_le, zd)
350
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
208
-DO_ST1_ZPZ_D(sd_be, zd)
351
+ REG_GP0, /* General Purpose Register 0 */
209
-DO_ST1_ZPZ_D(dd_le, zd)
352
+ REG_GP1, /* General Purpose Register 1 */
210
-DO_ST1_ZPZ_D(dd_be, zd)
353
+ REG_GP2, /* General Purpose Register 2 */
211
+DO_ST1_ZPZ_D(bd, zd, MO_8)
354
+ REG_GP3, /* General Purpose Register 3 */
212
+DO_ST1_ZPZ_D(hd_le, zd, MO_16)
355
+
213
+DO_ST1_ZPZ_D(hd_be, zd, MO_16)
356
+ /* sun4i registers */
214
+DO_ST1_ZPZ_D(sd_le, zd, MO_32)
357
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
215
+DO_ST1_ZPZ_D(sd_be, zd, MO_32)
358
+ REG_CPUCFG, /* CPU Configuration Register */
216
+DO_ST1_ZPZ_D(dd_le, zd, MO_64)
359
+
217
+DO_ST1_ZPZ_D(dd_be, zd, MO_64)
360
+ /* sun6i registers */
218
361
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
219
#undef DO_ST1_ZPZ_S
362
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
220
#undef DO_ST1_ZPZ_D
363
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
364
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
365
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
366
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
367
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
368
+ REG_ALARM_CONFIG, /* Alarm Config */
369
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
370
+ REG_GP4, /* General Purpose Register 4 */
371
+ REG_GP5, /* General Purpose Register 5 */
372
+ REG_GP6, /* General Purpose Register 6 */
373
+ REG_GP7, /* General Purpose Register 7 */
374
+ REG_RTC_DBG, /* RTC Debug Register */
375
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
376
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
377
+ REG_IC_CHARA, /* IC Characteristics Register */
378
+};
379
+
380
+/* RTC register flags */
381
+enum {
382
+ REG_LOSC_YMD = (1 << 7),
383
+ REG_LOSC_HMS = (1 << 8),
384
+};
385
+
386
+/* RTC sun4i register map (offset to name) */
387
+const uint8_t allwinner_rtc_sun4i_regmap[] = {
388
+ [0x0000] = REG_LOSC,
389
+ [0x0004] = REG_YYMMDD,
390
+ [0x0008] = REG_HHMMSS,
391
+ [0x000C] = REG_ALARM1_DDHHMMSS,
392
+ [0x0010] = REG_ALARM1_WKHHMMSS,
393
+ [0x0014] = REG_ALARM1_EN,
394
+ [0x0018] = REG_ALARM1_IRQ_EN,
395
+ [0x001C] = REG_ALARM1_IRQ_STA,
396
+ [0x0020] = REG_GP0,
397
+ [0x0024] = REG_GP1,
398
+ [0x0028] = REG_GP2,
399
+ [0x002C] = REG_GP3,
400
+ [0x003C] = REG_CPUCFG,
401
+};
402
+
403
+/* RTC sun6i register map (offset to name) */
404
+const uint8_t allwinner_rtc_sun6i_regmap[] = {
405
+ [0x0000] = REG_LOSC,
406
+ [0x0004] = REG_LOSC_AUTOSTA,
407
+ [0x0008] = REG_INT_OSC_PRE,
408
+ [0x0010] = REG_YYMMDD,
409
+ [0x0014] = REG_HHMMSS,
410
+ [0x0020] = REG_ALARM0_COUNTER,
411
+ [0x0024] = REG_ALARM0_CUR_VLU,
412
+ [0x0028] = REG_ALARM0_ENABLE,
413
+ [0x002C] = REG_ALARM0_IRQ_EN,
414
+ [0x0030] = REG_ALARM0_IRQ_STA,
415
+ [0x0040] = REG_ALARM1_WKHHMMSS,
416
+ [0x0044] = REG_ALARM1_EN,
417
+ [0x0048] = REG_ALARM1_IRQ_EN,
418
+ [0x004C] = REG_ALARM1_IRQ_STA,
419
+ [0x0050] = REG_ALARM_CONFIG,
420
+ [0x0060] = REG_LOSC_OUT_GATING,
421
+ [0x0100] = REG_GP0,
422
+ [0x0104] = REG_GP1,
423
+ [0x0108] = REG_GP2,
424
+ [0x010C] = REG_GP3,
425
+ [0x0110] = REG_GP4,
426
+ [0x0114] = REG_GP5,
427
+ [0x0118] = REG_GP6,
428
+ [0x011C] = REG_GP7,
429
+ [0x0170] = REG_RTC_DBG,
430
+ [0x0180] = REG_GPL_HOLD_OUT,
431
+ [0x0190] = REG_VDD_RTC,
432
+ [0x01F0] = REG_IC_CHARA,
433
+};
434
+
435
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
436
+{
437
+ /* no sun4i specific registers currently implemented */
438
+ return false;
439
+}
440
+
441
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
442
+ uint32_t data)
443
+{
444
+ /* no sun4i specific registers currently implemented */
445
+ return false;
446
+}
447
+
448
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
449
+{
450
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
451
+
452
+ switch (c->regmap[offset]) {
453
+ case REG_GP4: /* General Purpose Register 4 */
454
+ case REG_GP5: /* General Purpose Register 5 */
455
+ case REG_GP6: /* General Purpose Register 6 */
456
+ case REG_GP7: /* General Purpose Register 7 */
457
+ return true;
458
+ default:
459
+ break;
460
+ }
461
+ return false;
462
+}
463
+
464
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
465
+ uint32_t data)
466
+{
467
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
468
+
469
+ switch (c->regmap[offset]) {
470
+ case REG_GP4: /* General Purpose Register 4 */
471
+ case REG_GP5: /* General Purpose Register 5 */
472
+ case REG_GP6: /* General Purpose Register 6 */
473
+ case REG_GP7: /* General Purpose Register 7 */
474
+ return true;
475
+ default:
476
+ break;
477
+ }
478
+ return false;
479
+}
480
+
481
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
482
+ unsigned size)
483
+{
484
+ AwRtcState *s = AW_RTC(opaque);
485
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
486
+ uint64_t val = 0;
487
+
488
+ if (offset >= c->regmap_size) {
489
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
490
+ __func__, (uint32_t)offset);
491
+ return 0;
492
+ }
493
+
494
+ if (!c->regmap[offset]) {
495
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
496
+ __func__, (uint32_t)offset);
497
+ return 0;
498
+ }
499
+
500
+ switch (c->regmap[offset]) {
501
+ case REG_LOSC: /* Low Oscillator Control */
502
+ val = s->regs[REG_LOSC];
503
+ s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
504
+ break;
505
+ case REG_YYMMDD: /* RTC Year-Month-Day */
506
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
507
+ case REG_GP0: /* General Purpose Register 0 */
508
+ case REG_GP1: /* General Purpose Register 1 */
509
+ case REG_GP2: /* General Purpose Register 2 */
510
+ case REG_GP3: /* General Purpose Register 3 */
511
+ val = s->regs[c->regmap[offset]];
512
+ break;
513
+ default:
514
+ if (!c->read(s, offset)) {
515
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
516
+ __func__, (uint32_t)offset);
517
+ }
518
+ val = s->regs[c->regmap[offset]];
519
+ break;
520
+ }
521
+
522
+ trace_allwinner_rtc_read(offset, val);
523
+ return val;
524
+}
525
+
526
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
527
+ uint64_t val, unsigned size)
528
+{
529
+ AwRtcState *s = AW_RTC(opaque);
530
+ const AwRtcClass *c = AW_RTC_GET_CLASS(s);
531
+
532
+ if (offset >= c->regmap_size) {
533
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
534
+ __func__, (uint32_t)offset);
535
+ return;
536
+ }
537
+
538
+ if (!c->regmap[offset]) {
539
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
540
+ __func__, (uint32_t)offset);
541
+ return;
542
+ }
543
+
544
+ trace_allwinner_rtc_write(offset, val);
545
+
546
+ switch (c->regmap[offset]) {
547
+ case REG_YYMMDD: /* RTC Year-Month-Day */
548
+ s->regs[REG_YYMMDD] = val;
549
+ s->regs[REG_LOSC] |= REG_LOSC_YMD;
550
+ break;
551
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
552
+ s->regs[REG_HHMMSS] = val;
553
+ s->regs[REG_LOSC] |= REG_LOSC_HMS;
554
+ break;
555
+ case REG_GP0: /* General Purpose Register 0 */
556
+ case REG_GP1: /* General Purpose Register 1 */
557
+ case REG_GP2: /* General Purpose Register 2 */
558
+ case REG_GP3: /* General Purpose Register 3 */
559
+ s->regs[c->regmap[offset]] = val;
560
+ break;
561
+ default:
562
+ if (!c->write(s, offset, val)) {
563
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
564
+ __func__, (uint32_t)offset);
565
+ }
566
+ break;
567
+ }
568
+}
569
+
570
+static const MemoryRegionOps allwinner_rtc_ops = {
571
+ .read = allwinner_rtc_read,
572
+ .write = allwinner_rtc_write,
573
+ .endianness = DEVICE_NATIVE_ENDIAN,
574
+ .valid = {
575
+ .min_access_size = 4,
576
+ .max_access_size = 4,
577
+ },
578
+ .impl.min_access_size = 4,
579
+};
580
+
581
+static void allwinner_rtc_reset(DeviceState *dev)
582
+{
583
+ AwRtcState *s = AW_RTC(dev);
584
+ struct tm now;
585
+
586
+ /* Clear registers */
587
+ memset(s->regs, 0, sizeof(s->regs));
588
+
589
+ /* Get current datetime */
590
+ qemu_get_timedate(&now, 0);
591
+
592
+ /* Set RTC with current datetime */
593
+ if (s->base_year > 1900) {
594
+ s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
595
+ ((now.tm_mon + 1) << 8) |
596
+ now.tm_mday;
597
+ s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
598
+ (now.tm_hour << 16) |
599
+ (now.tm_min << 8) |
600
+ now.tm_sec;
601
+ }
602
+}
603
+
604
+static void allwinner_rtc_init(Object *obj)
605
+{
606
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
607
+ AwRtcState *s = AW_RTC(obj);
608
+
609
+ /* Memory mapping */
610
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
611
+ TYPE_AW_RTC, 1 * KiB);
612
+ sysbus_init_mmio(sbd, &s->iomem);
613
+}
614
+
615
+static const VMStateDescription allwinner_rtc_vmstate = {
616
+ .name = "allwinner-rtc",
617
+ .version_id = 1,
618
+ .minimum_version_id = 1,
619
+ .fields = (VMStateField[]) {
620
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
621
+ VMSTATE_END_OF_LIST()
622
+ }
623
+};
624
+
625
+static Property allwinner_rtc_properties[] = {
626
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
627
+ DEFINE_PROP_END_OF_LIST(),
628
+};
629
+
630
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
631
+{
632
+ DeviceClass *dc = DEVICE_CLASS(klass);
633
+
634
+ dc->reset = allwinner_rtc_reset;
635
+ dc->vmsd = &allwinner_rtc_vmstate;
636
+ device_class_set_props(dc, allwinner_rtc_properties);
637
+}
638
+
639
+static void allwinner_rtc_sun4i_init(Object *obj)
640
+{
641
+ AwRtcState *s = AW_RTC(obj);
642
+ s->base_year = 2010;
643
+}
644
+
645
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
646
+{
647
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
648
+
649
+ arc->regmap = allwinner_rtc_sun4i_regmap;
650
+ arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
651
+ arc->read = allwinner_rtc_sun4i_read;
652
+ arc->write = allwinner_rtc_sun4i_write;
653
+}
654
+
655
+static void allwinner_rtc_sun6i_init(Object *obj)
656
+{
657
+ AwRtcState *s = AW_RTC(obj);
658
+ s->base_year = 1970;
659
+}
660
+
661
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
662
+{
663
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
664
+
665
+ arc->regmap = allwinner_rtc_sun6i_regmap;
666
+ arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
667
+ arc->read = allwinner_rtc_sun6i_read;
668
+ arc->write = allwinner_rtc_sun6i_write;
669
+}
670
+
671
+static void allwinner_rtc_sun7i_init(Object *obj)
672
+{
673
+ AwRtcState *s = AW_RTC(obj);
674
+ s->base_year = 1970;
675
+}
676
+
677
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
678
+{
679
+ AwRtcClass *arc = AW_RTC_CLASS(klass);
680
+ allwinner_rtc_sun4i_class_init(klass, arc);
681
+}
682
+
683
+static const TypeInfo allwinner_rtc_info = {
684
+ .name = TYPE_AW_RTC,
685
+ .parent = TYPE_SYS_BUS_DEVICE,
686
+ .instance_init = allwinner_rtc_init,
687
+ .instance_size = sizeof(AwRtcState),
688
+ .class_init = allwinner_rtc_class_init,
689
+ .class_size = sizeof(AwRtcClass),
690
+ .abstract = true,
691
+};
692
+
693
+static const TypeInfo allwinner_rtc_sun4i_info = {
694
+ .name = TYPE_AW_RTC_SUN4I,
695
+ .parent = TYPE_AW_RTC,
696
+ .class_init = allwinner_rtc_sun4i_class_init,
697
+ .instance_init = allwinner_rtc_sun4i_init,
698
+};
699
+
700
+static const TypeInfo allwinner_rtc_sun6i_info = {
701
+ .name = TYPE_AW_RTC_SUN6I,
702
+ .parent = TYPE_AW_RTC,
703
+ .class_init = allwinner_rtc_sun6i_class_init,
704
+ .instance_init = allwinner_rtc_sun6i_init,
705
+};
706
+
707
+static const TypeInfo allwinner_rtc_sun7i_info = {
708
+ .name = TYPE_AW_RTC_SUN7I,
709
+ .parent = TYPE_AW_RTC,
710
+ .class_init = allwinner_rtc_sun7i_class_init,
711
+ .instance_init = allwinner_rtc_sun7i_init,
712
+};
713
+
714
+static void allwinner_rtc_register(void)
715
+{
716
+ type_register_static(&allwinner_rtc_info);
717
+ type_register_static(&allwinner_rtc_sun4i_info);
718
+ type_register_static(&allwinner_rtc_sun6i_info);
719
+ type_register_static(&allwinner_rtc_sun7i_info);
720
+}
721
+
722
+type_init(allwinner_rtc_register)
723
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
724
index XXXXXXX..XXXXXXX 100644
725
--- a/hw/rtc/trace-events
726
+++ b/hw/rtc/trace-events
727
@@ -XXX,XX +XXX,XX @@
728
# See docs/devel/tracing.txt for syntax documentation.
729
730
+# allwinner-rtc.c
731
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
732
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64
733
+
734
# sun4v-rtc.c
735
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64
736
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64
737
--
221
--
738
2.20.1
222
2.20.1
739
223
740
224
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert kvm_arm_vgic_probe() so that it returns a
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
bitmap of supported in-kernel emulation VGIC versions instead
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
of the max version: at the moment values can be v2 and v3.
5
Message-id: 20200508154359.7494-19-richard.henderson@linaro.org
6
This allows to expose the case where the host GICv3 also
7
supports GICv2 emulation. This will be useful to choose the
8
default version in KVM accelerated mode.
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20200311131618.7187-5-eric.auger@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
7
---
16
target/arm/kvm_arm.h | 3 +++
8
target/arm/sve_helper.c | 208 +++++++++++++++++++++-------------------
17
hw/arm/virt.c | 11 +++++++++--
9
1 file changed, 109 insertions(+), 99 deletions(-)
18
target/arm/kvm.c | 14 ++++++++------
10
19
3 files changed, 20 insertions(+), 8 deletions(-)
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
20
21
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
22
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/kvm_arm.h
13
--- a/target/arm/sve_helper.c
24
+++ b/target/arm/kvm_arm.h
14
+++ b/target/arm/sve_helper.c
25
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
26
#include "exec/memory.h"
16
return *(uint64_t *)(reg + reg_ofs);
27
#include "qemu/error-report.h"
17
}
28
18
29
+#define KVM_ARM_VGIC_V2 (1 << 0)
19
-static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
30
+#define KVM_ARM_VGIC_V3 (1 << 1)
20
- target_ulong base, uint32_t desc, uintptr_t ra,
21
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
22
+static inline QEMU_ALWAYS_INLINE
23
+void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
24
+ target_ulong base, uint32_t desc, uintptr_t retaddr,
25
+ int esize, int msize, zreg_off_fn *off_fn,
26
+ sve_ldst1_host_fn *host_fn,
27
+ sve_ldst1_tlb_fn *tlb_fn)
28
{
29
const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
30
- intptr_t i, oprsz = simd_oprsz(desc);
31
- ARMVectorReg scratch = { };
32
+ const int mmu_idx = cpu_mmu_index(env, false);
33
+ const intptr_t reg_max = simd_oprsz(desc);
34
+ ARMVectorReg scratch;
35
+ intptr_t reg_off;
36
+ SVEHostPage info, info2;
37
38
- for (i = 0; i < oprsz; ) {
39
- uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
40
+ memset(&scratch, 0, reg_max);
41
+ reg_off = 0;
42
+ do {
43
+ uint64_t pg = vg[reg_off >> 6];
44
do {
45
if (likely(pg & 1)) {
46
- target_ulong off = off_fn(vm, i);
47
- tlb_fn(env, &scratch, i, base + (off << scale), ra);
48
+ target_ulong addr = base + (off_fn(vm, reg_off) << scale);
49
+ target_ulong in_page = -(addr | TARGET_PAGE_MASK);
31
+
50
+
32
/**
51
+ sve_probe_page(&info, false, env, addr, 0, MMU_DATA_LOAD,
33
* kvm_arm_vcpu_init:
52
+ mmu_idx, retaddr);
34
* @cs: CPUState
35
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/virt.c
38
+++ b/hw/arm/virt.c
39
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
40
vms->gic_version = VIRT_GIC_VERSION_3;
41
}
42
} else {
43
- vms->gic_version = kvm_arm_vgic_probe();
44
- if (!vms->gic_version) {
45
+ int probe_bitmap = kvm_arm_vgic_probe();
46
+
53
+
47
+ if (!probe_bitmap) {
54
+ if (likely(in_page >= msize)) {
48
error_report(
55
+ if (unlikely(info.flags & TLB_WATCHPOINT)) {
49
"Unable to determine GIC version supported by host");
56
+ cpu_check_watchpoint(env_cpu(env), addr, msize,
50
exit(1);
57
+ info.attrs, BP_MEM_READ, retaddr);
51
+ } else {
58
+ }
52
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
59
+ /* TODO: MTE check */
53
+ vms->gic_version = VIRT_GIC_VERSION_3;
60
+ host_fn(&scratch, reg_off, info.host);
54
+ } else {
61
+ } else {
55
+ vms->gic_version = VIRT_GIC_VERSION_2;
62
+ /* Element crosses the page boundary. */
63
+ sve_probe_page(&info2, false, env, addr + in_page, 0,
64
+ MMU_DATA_LOAD, mmu_idx, retaddr);
65
+ if (unlikely((info.flags | info2.flags) & TLB_WATCHPOINT)) {
66
+ cpu_check_watchpoint(env_cpu(env), addr,
67
+ msize, info.attrs,
68
+ BP_MEM_READ, retaddr);
69
+ }
70
+ /* TODO: MTE check */
71
+ tlb_fn(env, &scratch, reg_off, addr, retaddr);
56
+ }
72
+ }
57
}
73
}
58
}
74
- i += 4, pg >>= 4;
59
} else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
75
- } while (i & 15);
60
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
76
- }
61
index XXXXXXX..XXXXXXX 100644
77
+ reg_off += esize;
62
--- a/target/arm/kvm.c
78
+ pg >>= esize;
63
+++ b/target/arm/kvm.c
79
+ } while (reg_off & 63);
64
@@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s)
80
+ } while (reg_off < reg_max);
65
81
66
int kvm_arm_vgic_probe(void)
82
/* Wait until all exceptions have been raised to write back. */
67
{
83
- memcpy(vd, &scratch, oprsz);
68
+ int val = 0;
84
+ memcpy(vd, &scratch, reg_max);
69
+
85
}
70
if (kvm_create_device(kvm_state,
86
71
KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
87
-static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
72
- return 3;
88
- target_ulong base, uint32_t desc, uintptr_t ra,
73
- } else if (kvm_create_device(kvm_state,
89
- zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
74
- KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
90
-{
75
- return 2;
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
76
- } else {
92
- intptr_t i, oprsz = simd_oprsz(desc) / 8;
77
- return 0;
93
- ARMVectorReg scratch = { };
78
+ val |= KVM_ARM_VGIC_V3;
94
-
79
}
95
- for (i = 0; i < oprsz; i++) {
80
+ if (kvm_create_device(kvm_state,
96
- uint8_t pg = *(uint8_t *)(vg + H1(i));
81
+ KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
97
- if (likely(pg & 1)) {
82
+ val |= KVM_ARM_VGIC_V2;
98
- target_ulong off = off_fn(vm, i * 8);
83
+ }
99
- tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
84
+ return val;
100
- }
85
}
101
- }
86
102
-
87
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level)
103
- /* Wait until all exceptions have been raised to write back. */
104
- memcpy(vd, &scratch, oprsz * 8);
105
+#define DO_LD1_ZPZ_S(MEM, OFS, MSZ) \
106
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
107
+ void *vm, target_ulong base, uint32_t desc) \
108
+{ \
109
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 4, 1 << MSZ, \
110
+ off_##OFS##_s, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
111
}
112
113
-#define DO_LD1_ZPZ_S(MEM, OFS) \
114
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
115
- (CPUARMState *env, void *vd, void *vg, void *vm, \
116
- target_ulong base, uint32_t desc) \
117
-{ \
118
- sve_ld1_zs(env, vd, vg, vm, base, desc, GETPC(), \
119
- off_##OFS##_s, sve_ld1##MEM##_tlb); \
120
+#define DO_LD1_ZPZ_D(MEM, OFS, MSZ) \
121
+void HELPER(sve_ld##MEM##_##OFS)(CPUARMState *env, void *vd, void *vg, \
122
+ void *vm, target_ulong base, uint32_t desc) \
123
+{ \
124
+ sve_ld1_z(env, vd, vg, vm, base, desc, GETPC(), 8, 1 << MSZ, \
125
+ off_##OFS##_d, sve_ld1##MEM##_host, sve_ld1##MEM##_tlb); \
126
}
127
128
-#define DO_LD1_ZPZ_D(MEM, OFS) \
129
-void QEMU_FLATTEN HELPER(sve_ld##MEM##_##OFS) \
130
- (CPUARMState *env, void *vd, void *vg, void *vm, \
131
- target_ulong base, uint32_t desc) \
132
-{ \
133
- sve_ld1_zd(env, vd, vg, vm, base, desc, GETPC(), \
134
- off_##OFS##_d, sve_ld1##MEM##_tlb); \
135
-}
136
+DO_LD1_ZPZ_S(bsu, zsu, MO_8)
137
+DO_LD1_ZPZ_S(bsu, zss, MO_8)
138
+DO_LD1_ZPZ_D(bdu, zsu, MO_8)
139
+DO_LD1_ZPZ_D(bdu, zss, MO_8)
140
+DO_LD1_ZPZ_D(bdu, zd, MO_8)
141
142
-DO_LD1_ZPZ_S(bsu, zsu)
143
-DO_LD1_ZPZ_S(bsu, zss)
144
-DO_LD1_ZPZ_D(bdu, zsu)
145
-DO_LD1_ZPZ_D(bdu, zss)
146
-DO_LD1_ZPZ_D(bdu, zd)
147
+DO_LD1_ZPZ_S(bss, zsu, MO_8)
148
+DO_LD1_ZPZ_S(bss, zss, MO_8)
149
+DO_LD1_ZPZ_D(bds, zsu, MO_8)
150
+DO_LD1_ZPZ_D(bds, zss, MO_8)
151
+DO_LD1_ZPZ_D(bds, zd, MO_8)
152
153
-DO_LD1_ZPZ_S(bss, zsu)
154
-DO_LD1_ZPZ_S(bss, zss)
155
-DO_LD1_ZPZ_D(bds, zsu)
156
-DO_LD1_ZPZ_D(bds, zss)
157
-DO_LD1_ZPZ_D(bds, zd)
158
+DO_LD1_ZPZ_S(hsu_le, zsu, MO_16)
159
+DO_LD1_ZPZ_S(hsu_le, zss, MO_16)
160
+DO_LD1_ZPZ_D(hdu_le, zsu, MO_16)
161
+DO_LD1_ZPZ_D(hdu_le, zss, MO_16)
162
+DO_LD1_ZPZ_D(hdu_le, zd, MO_16)
163
164
-DO_LD1_ZPZ_S(hsu_le, zsu)
165
-DO_LD1_ZPZ_S(hsu_le, zss)
166
-DO_LD1_ZPZ_D(hdu_le, zsu)
167
-DO_LD1_ZPZ_D(hdu_le, zss)
168
-DO_LD1_ZPZ_D(hdu_le, zd)
169
+DO_LD1_ZPZ_S(hsu_be, zsu, MO_16)
170
+DO_LD1_ZPZ_S(hsu_be, zss, MO_16)
171
+DO_LD1_ZPZ_D(hdu_be, zsu, MO_16)
172
+DO_LD1_ZPZ_D(hdu_be, zss, MO_16)
173
+DO_LD1_ZPZ_D(hdu_be, zd, MO_16)
174
175
-DO_LD1_ZPZ_S(hsu_be, zsu)
176
-DO_LD1_ZPZ_S(hsu_be, zss)
177
-DO_LD1_ZPZ_D(hdu_be, zsu)
178
-DO_LD1_ZPZ_D(hdu_be, zss)
179
-DO_LD1_ZPZ_D(hdu_be, zd)
180
+DO_LD1_ZPZ_S(hss_le, zsu, MO_16)
181
+DO_LD1_ZPZ_S(hss_le, zss, MO_16)
182
+DO_LD1_ZPZ_D(hds_le, zsu, MO_16)
183
+DO_LD1_ZPZ_D(hds_le, zss, MO_16)
184
+DO_LD1_ZPZ_D(hds_le, zd, MO_16)
185
186
-DO_LD1_ZPZ_S(hss_le, zsu)
187
-DO_LD1_ZPZ_S(hss_le, zss)
188
-DO_LD1_ZPZ_D(hds_le, zsu)
189
-DO_LD1_ZPZ_D(hds_le, zss)
190
-DO_LD1_ZPZ_D(hds_le, zd)
191
+DO_LD1_ZPZ_S(hss_be, zsu, MO_16)
192
+DO_LD1_ZPZ_S(hss_be, zss, MO_16)
193
+DO_LD1_ZPZ_D(hds_be, zsu, MO_16)
194
+DO_LD1_ZPZ_D(hds_be, zss, MO_16)
195
+DO_LD1_ZPZ_D(hds_be, zd, MO_16)
196
197
-DO_LD1_ZPZ_S(hss_be, zsu)
198
-DO_LD1_ZPZ_S(hss_be, zss)
199
-DO_LD1_ZPZ_D(hds_be, zsu)
200
-DO_LD1_ZPZ_D(hds_be, zss)
201
-DO_LD1_ZPZ_D(hds_be, zd)
202
+DO_LD1_ZPZ_S(ss_le, zsu, MO_32)
203
+DO_LD1_ZPZ_S(ss_le, zss, MO_32)
204
+DO_LD1_ZPZ_D(sdu_le, zsu, MO_32)
205
+DO_LD1_ZPZ_D(sdu_le, zss, MO_32)
206
+DO_LD1_ZPZ_D(sdu_le, zd, MO_32)
207
208
-DO_LD1_ZPZ_S(ss_le, zsu)
209
-DO_LD1_ZPZ_S(ss_le, zss)
210
-DO_LD1_ZPZ_D(sdu_le, zsu)
211
-DO_LD1_ZPZ_D(sdu_le, zss)
212
-DO_LD1_ZPZ_D(sdu_le, zd)
213
+DO_LD1_ZPZ_S(ss_be, zsu, MO_32)
214
+DO_LD1_ZPZ_S(ss_be, zss, MO_32)
215
+DO_LD1_ZPZ_D(sdu_be, zsu, MO_32)
216
+DO_LD1_ZPZ_D(sdu_be, zss, MO_32)
217
+DO_LD1_ZPZ_D(sdu_be, zd, MO_32)
218
219
-DO_LD1_ZPZ_S(ss_be, zsu)
220
-DO_LD1_ZPZ_S(ss_be, zss)
221
-DO_LD1_ZPZ_D(sdu_be, zsu)
222
-DO_LD1_ZPZ_D(sdu_be, zss)
223
-DO_LD1_ZPZ_D(sdu_be, zd)
224
+DO_LD1_ZPZ_D(sds_le, zsu, MO_32)
225
+DO_LD1_ZPZ_D(sds_le, zss, MO_32)
226
+DO_LD1_ZPZ_D(sds_le, zd, MO_32)
227
228
-DO_LD1_ZPZ_D(sds_le, zsu)
229
-DO_LD1_ZPZ_D(sds_le, zss)
230
-DO_LD1_ZPZ_D(sds_le, zd)
231
+DO_LD1_ZPZ_D(sds_be, zsu, MO_32)
232
+DO_LD1_ZPZ_D(sds_be, zss, MO_32)
233
+DO_LD1_ZPZ_D(sds_be, zd, MO_32)
234
235
-DO_LD1_ZPZ_D(sds_be, zsu)
236
-DO_LD1_ZPZ_D(sds_be, zss)
237
-DO_LD1_ZPZ_D(sds_be, zd)
238
+DO_LD1_ZPZ_D(dd_le, zsu, MO_64)
239
+DO_LD1_ZPZ_D(dd_le, zss, MO_64)
240
+DO_LD1_ZPZ_D(dd_le, zd, MO_64)
241
242
-DO_LD1_ZPZ_D(dd_le, zsu)
243
-DO_LD1_ZPZ_D(dd_le, zss)
244
-DO_LD1_ZPZ_D(dd_le, zd)
245
-
246
-DO_LD1_ZPZ_D(dd_be, zsu)
247
-DO_LD1_ZPZ_D(dd_be, zss)
248
-DO_LD1_ZPZ_D(dd_be, zd)
249
+DO_LD1_ZPZ_D(dd_be, zsu, MO_64)
250
+DO_LD1_ZPZ_D(dd_be, zss, MO_64)
251
+DO_LD1_ZPZ_D(dd_be, zd, MO_64)
252
253
#undef DO_LD1_ZPZ_S
254
#undef DO_LD1_ZPZ_D
88
--
255
--
89
2.20.1
256
2.20.1
90
257
91
258
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Aspeed SMC Controller can operate in different modes : Read, Fast
3
None of the sve helpers use TCGMemOpIdx any longer, so we can
4
Read, Write and User modes. When the User mode is configured, it
4
stop passing it.
5
selects automatically the SPI slave device until the CE_STOP_ACTIVE
6
bit is set to 1. When any other modes are configured the device is
7
unselected. The HW logic handles the chip select automatically when
8
the flash is accessed through its AHB window.
9
5
10
When configuring the CEx Control Register, the User mode logic to
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
select and unselect the slave is incorrect and data corruption can be
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
seen on machines using two chips, witherspoon and romulus.
8
Message-id: 20200508154359.7494-20-richard.henderson@linaro.org
13
14
Rework the handler setting the CEx Control Register to fix this issue.
15
16
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
18
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
19
Message-id: 20200206112645.21275-3-clg@kaod.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
10
---
22
hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++----------------
11
target/arm/internals.h | 5 -----
23
hw/ssi/trace-events | 1 +
12
target/arm/sve_helper.c | 14 +++++++-------
24
2 files changed, 24 insertions(+), 16 deletions(-)
13
target/arm/translate-sve.c | 17 +++--------------
14
3 files changed, 10 insertions(+), 26 deletions(-)
25
15
26
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
27
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/aspeed_smc.c
18
--- a/target/arm/internals.h
29
+++ b/hw/ssi/aspeed_smc.c
19
+++ b/target/arm/internals.h
30
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
20
@@ -XXX,XX +XXX,XX @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
31
}
21
}
32
}
22
}
33
23
34
-static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
24
-/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.
35
+static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
25
- * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.
26
- */
27
-#define MEMOPIDX_SHIFT 8
28
-
29
/**
30
* v7m_using_psp: Return true if using process stack pointer
31
* Return true if the CPU is currently using the process stack
32
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/sve_helper.c
35
+++ b/target/arm/sve_helper.c
36
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr,
37
sve_ldst1_host_fn *host_fn,
38
sve_ldst1_tlb_fn *tlb_fn)
36
{
39
{
37
- const AspeedSMCState *s = fl->controller;
40
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
38
+ AspeedSMCState *s = fl->controller;
41
+ const unsigned rd = simd_data(desc);
39
42
const intptr_t reg_max = simd_oprsz(desc);
40
- return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
43
intptr_t reg_off, reg_last, mem_off;
41
+ trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
44
SVEContLdSt info;
42
+
45
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
43
+ qemu_set_irq(s->cs_lines[fl->id], unselect);
46
sve_ldst1_host_fn *host_fn,
44
}
47
sve_ldst1_tlb_fn *tlb_fn)
45
46
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
47
{
48
{
48
- AspeedSMCState *s = fl->controller;
49
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
50
+ const unsigned rd = simd_data(desc);
51
void *vd = &env->vfp.zregs[rd];
52
const intptr_t reg_max = simd_oprsz(desc);
53
intptr_t reg_off, mem_off, reg_last;
54
@@ -XXX,XX +XXX,XX @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc,
55
sve_ldst1_host_fn *host_fn,
56
sve_ldst1_tlb_fn *tlb_fn)
57
{
58
- const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
59
+ const unsigned rd = simd_data(desc);
60
const intptr_t reg_max = simd_oprsz(desc);
61
intptr_t reg_off, reg_last, mem_off;
62
SVEContLdSt info;
63
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
64
sve_ldst1_host_fn *host_fn,
65
sve_ldst1_tlb_fn *tlb_fn)
66
{
67
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
68
const int mmu_idx = cpu_mmu_index(env, false);
69
const intptr_t reg_max = simd_oprsz(desc);
70
+ const int scale = simd_data(desc);
71
ARMVectorReg scratch;
72
intptr_t reg_off;
73
SVEHostPage info, info2;
74
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
75
sve_ldst1_tlb_fn *tlb_fn)
76
{
77
const int mmu_idx = cpu_mmu_index(env, false);
78
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
79
+ const intptr_t reg_max = simd_oprsz(desc);
80
+ const int scale = simd_data(desc);
81
const int esize = 1 << esz;
82
const int msize = 1 << msz;
83
- const intptr_t reg_max = simd_oprsz(desc);
84
intptr_t reg_off;
85
SVEHostPage info;
86
target_ulong addr, in_page;
87
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
88
sve_ldst1_host_fn *host_fn,
89
sve_ldst1_tlb_fn *tlb_fn)
90
{
91
- const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
92
const int mmu_idx = cpu_mmu_index(env, false);
93
const intptr_t reg_max = simd_oprsz(desc);
94
+ const int scale = simd_data(desc);
95
void *host[ARM_MAX_VQ * 4];
96
intptr_t reg_off, i;
97
SVEHostPage info, info2;
98
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate-sve.c
101
+++ b/target/arm/translate-sve.c
102
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
103
3, 2, 1, 3
104
};
105
106
-static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)
107
-{
108
- return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));
109
-}
49
-
110
-
50
- s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
111
static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
51
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
112
int dtype, gen_helper_gvec_mem *fn)
52
+ aspeed_smc_flash_do_select(fl, false);
53
}
54
55
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
56
{
113
{
57
- AspeedSMCState *s = fl->controller;
114
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
58
-
115
* registers as pointers, so encode the regno into the data field.
59
- s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
116
* For consistency, do this even for LD1.
60
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
117
*/
61
+ aspeed_smc_flash_do_select(fl, true);
118
- desc = sve_memopidx(s, dtype);
62
}
119
- desc |= zt << MEMOPIDX_SHIFT;
63
120
- desc = simd_desc(vsz, vsz, desc);
64
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
121
+ desc = simd_desc(vsz, vsz, zt);
65
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = {
122
t_desc = tcg_const_i32(desc);
66
},
123
t_pg = tcg_temp_new_ptr();
67
};
124
68
125
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
69
-static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
126
int desc, poff;
70
+static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
127
71
{
128
/* Load the first quadword using the normal predicated load helpers. */
72
AspeedSMCState *s = fl->controller;
129
- desc = sve_memopidx(s, msz_dtype(s, msz));
73
+ bool unselect;
130
- desc |= zt << MEMOPIDX_SHIFT;
74
131
- desc = simd_desc(16, 16, desc);
75
- s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START;
132
+ desc = simd_desc(16, 16, zt);
76
+ /* User mode selects the CS, other modes unselect */
133
t_desc = tcg_const_i32(desc);
77
+ unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
134
78
135
poff = pred_full_reg_offset(s, pg);
79
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
136
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
80
+ /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
137
TCGv_i32 t_desc;
81
+ if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
138
int desc;
82
+ value & CTRL_CE_STOP_ACTIVE) {
139
83
+ unselect = true;
140
- desc = sve_memopidx(s, msz_dtype(s, msz));
84
+ }
141
- desc |= scale << MEMOPIDX_SHIFT;
85
+
142
- desc = simd_desc(vsz, vsz, desc);
86
+ s->regs[s->r_ctrl0 + fl->id] = value;
143
+ desc = simd_desc(vsz, vsz, scale);
87
+
144
t_desc = tcg_const_i32(desc);
88
+ s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
145
89
+
146
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
90
+ aspeed_smc_flash_do_select(fl, unselect);
91
}
92
93
static void aspeed_smc_reset(DeviceState *d)
94
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
95
s->regs[addr] = value;
96
} else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
97
int cs = addr - s->r_ctrl0;
98
- s->regs[addr] = value;
99
- aspeed_smc_flash_update_cs(&s->flashes[cs]);
100
+ aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
101
} else if (addr >= R_SEG_ADDR0 &&
102
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
103
int cs = addr - R_SEG_ADDR0;
104
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/ssi/trace-events
107
+++ b/hw/ssi/trace-events
108
@@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int
109
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
110
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
111
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
112
+aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
113
--
147
--
114
2.20.1
148
2.20.1
115
149
116
150
diff view generated by jsdifflib
1
From: Beata Michalska <beata.michalska@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
3
We want to move the inlined declarations of set_feature()
4
As such this should be the last step of sync to avoid potential overwriting
4
from cpu*.c to cpu.h. To avoid clashing with the KVM
5
of whatever changes KVM might have done.
5
declarations, inline the few KVM calls.
6
6
7
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
7
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20200312003401.29017-2-beata.michalska@linaro.org
9
Message-id: 20200504172448.9402-2-philmd@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/kvm32.c | 15 ++++++++++-----
12
target/arm/kvm32.c | 13 ++++---------
13
target/arm/kvm64.c | 15 ++++++++++-----
13
target/arm/kvm64.c | 22 ++++++----------------
14
2 files changed, 20 insertions(+), 10 deletions(-)
14
2 files changed, 10 insertions(+), 25 deletions(-)
15
15
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
16
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm32.c
18
--- a/target/arm/kvm32.c
19
+++ b/target/arm/kvm32.c
19
+++ b/target/arm/kvm32.c
20
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
20
@@ -XXX,XX +XXX,XX @@
21
return ret;
21
#include "internals.h"
22
#include "qemu/log.h"
23
24
-static inline void set_feature(uint64_t *features, int feature)
25
-{
26
- *features |= 1ULL << feature;
27
-}
28
-
29
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
30
{
31
struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
* timers; this in turn implies most of the other feature
34
* bits, but a few must be tested.
35
*/
36
- set_feature(&features, ARM_FEATURE_V7VE);
37
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
38
+ features |= 1ULL << ARM_FEATURE_V7VE;
39
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
40
41
if (extract32(id_pfr0, 12, 4) == 1) {
42
- set_feature(&features, ARM_FEATURE_THUMB2EE);
43
+ features |= 1ULL << ARM_FEATURE_THUMB2EE;
22
}
44
}
23
45
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
24
- ret = kvm_put_vcpu_events(cpu);
46
- set_feature(&features, ARM_FEATURE_NEON);
25
- if (ret) {
47
+ features |= 1ULL << ARM_FEATURE_NEON;
26
- return ret;
27
- }
28
-
29
write_cpustate_to_list(cpu, true);
30
31
if (!write_list_to_kvmstate(cpu, level)) {
32
return EINVAL;
33
}
48
}
34
49
35
+ /*
50
ahcf->features = features;
36
+ * Setting VCPU events should be triggered after syncing the registers
37
+ * to avoid overwriting potential changes made by KVM upon calling
38
+ * KVM_SET_VCPU_EVENTS ioctl
39
+ */
40
+ ret = kvm_put_vcpu_events(cpu);
41
+ if (ret) {
42
+ return ret;
43
+ }
44
+
45
kvm_arm_sync_mpstate_to_kvm(cpu);
46
47
return ret;
48
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
51
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
49
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/kvm64.c
53
--- a/target/arm/kvm64.c
51
+++ b/target/arm/kvm64.c
54
+++ b/target/arm/kvm64.c
52
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
55
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
53
return ret;
54
}
56
}
55
57
}
56
- ret = kvm_put_vcpu_events(cpu);
58
57
- if (ret) {
59
-static inline void set_feature(uint64_t *features, int feature)
58
- return ret;
60
-{
59
- }
61
- *features |= 1ULL << feature;
62
-}
60
-
63
-
61
write_cpustate_to_list(cpu, true);
64
-static inline void unset_feature(uint64_t *features, int feature)
62
65
-{
63
if (!write_list_to_kvmstate(cpu, level)) {
66
- *features &= ~(1ULL << feature);
64
return -EINVAL;
67
-}
68
-
69
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
70
{
71
uint64_t ret;
72
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
73
* with VFPv4+Neon; this in turn implies most of the other
74
* feature bits.
75
*/
76
- set_feature(&features, ARM_FEATURE_V8);
77
- set_feature(&features, ARM_FEATURE_NEON);
78
- set_feature(&features, ARM_FEATURE_AARCH64);
79
- set_feature(&features, ARM_FEATURE_PMU);
80
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
81
+ features |= 1ULL << ARM_FEATURE_V8;
82
+ features |= 1ULL << ARM_FEATURE_NEON;
83
+ features |= 1ULL << ARM_FEATURE_AARCH64;
84
+ features |= 1ULL << ARM_FEATURE_PMU;
85
+ features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
86
87
ahcf->features = features;
88
89
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
90
if (cpu->has_pmu) {
91
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
92
} else {
93
- unset_feature(&env->features, ARM_FEATURE_PMU);
94
+ env->features &= ~(1ULL << ARM_FEATURE_PMU);
65
}
95
}
66
96
if (cpu_isar_feature(aa64_sve, cpu)) {
67
+ /*
97
assert(kvm_arm_sve_supported(cs));
68
+ * Setting VCPU events should be triggered after syncing the registers
69
+ * to avoid overwriting potential changes made by KVM upon calling
70
+ * KVM_SET_VCPU_EVENTS ioctl
71
+ */
72
+ ret = kvm_put_vcpu_events(cpu);
73
+ if (ret) {
74
+ return ret;
75
+ }
76
+
77
kvm_arm_sync_mpstate_to_kvm(cpu);
78
79
return ret;
80
--
98
--
81
2.20.1
99
2.20.1
82
100
83
101
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
The Clock Control Unit is responsible for clock signal generation,
3
Move the common set_feature() and unset_feature() functions
4
configuration and distribution in the Allwinner H3 System on Chip.
4
from cpu.c and cpu64.c to cpu.h.
5
This commit adds support for the Clock Control Unit which emulates
6
a simple read/write register interface.
7
5
8
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20200504172448.9402-3-philmd@redhat.com
12
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
13
[PMD: Split Thomas's patch in two: set_feature, cpu_register]
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
16
---
15
hw/misc/Makefile.objs | 1 +
17
target/arm/cpu.h | 10 ++++++++++
16
include/hw/arm/allwinner-h3.h | 3 +
18
target/arm/cpu.c | 10 ----------
17
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
19
target/arm/cpu64.c | 10 ----------
18
hw/arm/allwinner-h3.c | 9 +-
20
3 files changed, 10 insertions(+), 20 deletions(-)
19
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
20
5 files changed, 320 insertions(+), 1 deletion(-)
21
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
22
create mode 100644 hw/misc/allwinner-h3-ccu.c
23
21
24
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/misc/Makefile.objs
24
--- a/target/arm/cpu.h
27
+++ b/hw/misc/Makefile.objs
25
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/
26
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
29
27
void *gicv3state;
30
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
28
} CPUARMState;
31
29
32
+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
30
+static inline void set_feature(CPUARMState *env, int feature)
33
common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
34
common-obj-$(CONFIG_NSERIES) += cbus.o
35
common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
36
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/hw/arm/allwinner-h3.h
39
+++ b/include/hw/arm/allwinner-h3.h
40
@@ -XXX,XX +XXX,XX @@
41
#include "hw/arm/boot.h"
42
#include "hw/timer/allwinner-a10-pit.h"
43
#include "hw/intc/arm_gic.h"
44
+#include "hw/misc/allwinner-h3-ccu.h"
45
#include "target/arm/cpu.h"
46
47
/**
48
@@ -XXX,XX +XXX,XX @@ enum {
49
AW_H3_SRAM_A1,
50
AW_H3_SRAM_A2,
51
AW_H3_SRAM_C,
52
+ AW_H3_CCU,
53
AW_H3_PIT,
54
AW_H3_UART0,
55
AW_H3_UART1,
56
@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {
57
ARMCPU cpus[AW_H3_NUM_CPUS];
58
const hwaddr *memmap;
59
AwA10PITState timer;
60
+ AwH3ClockCtlState ccu;
61
GICState gic;
62
MemoryRegion sram_a1;
63
MemoryRegion sram_a2;
64
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/allwinner-h3-ccu.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Allwinner H3 Clock Control Unit emulation
72
+ *
73
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
74
+ *
75
+ * This program is free software: you can redistribute it and/or modify
76
+ * it under the terms of the GNU General Public License as published by
77
+ * the Free Software Foundation, either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful,
81
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
82
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83
+ * GNU General Public License for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License
86
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
89
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
90
+#define HW_MISC_ALLWINNER_H3_CCU_H
91
+
92
+#include "qom/object.h"
93
+#include "hw/sysbus.h"
94
+
95
+/**
96
+ * @name Constants
97
+ * @{
98
+ */
99
+
100
+/** Size of register I/O address space used by CCU device */
101
+#define AW_H3_CCU_IOSIZE (0x400)
102
+
103
+/** Total number of known registers */
104
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
105
+
106
+/** @} */
107
+
108
+/**
109
+ * @name Object model
110
+ * @{
111
+ */
112
+
113
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
114
+#define AW_H3_CCU(obj) \
115
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
116
+
117
+/** @} */
118
+
119
+/**
120
+ * Allwinner H3 CCU object instance state.
121
+ */
122
+typedef struct AwH3ClockCtlState {
123
+ /*< private >*/
124
+ SysBusDevice parent_obj;
125
+ /*< public >*/
126
+
127
+ /** Maps I/O registers in physical memory */
128
+ MemoryRegion iomem;
129
+
130
+ /** Array of hardware registers */
131
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
132
+
133
+} AwH3ClockCtlState;
134
+
135
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
136
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/arm/allwinner-h3.c
139
+++ b/hw/arm/allwinner-h3.c
140
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
141
[AW_H3_SRAM_A1] = 0x00000000,
142
[AW_H3_SRAM_A2] = 0x00044000,
143
[AW_H3_SRAM_C] = 0x00010000,
144
+ [AW_H3_CCU] = 0x01c20000,
145
[AW_H3_PIT] = 0x01c20c00,
146
[AW_H3_UART0] = 0x01c28000,
147
[AW_H3_UART1] = 0x01c28400,
148
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
149
{ "usb2-phy", 0x01c1c000, 4 * KiB },
150
{ "usb3-phy", 0x01c1d000, 4 * KiB },
151
{ "smc", 0x01c1e000, 4 * KiB },
152
- { "ccu", 0x01c20000, 1 * KiB },
153
{ "pio", 0x01c20800, 1 * KiB },
154
{ "owa", 0x01c21000, 1 * KiB },
155
{ "pwm", 0x01c21400, 1 * KiB },
156
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
157
"clk0-freq", &error_abort);
158
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
159
"clk1-freq", &error_abort);
160
+
161
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
162
+ TYPE_AW_H3_CCU);
163
}
164
165
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
166
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
167
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
168
&s->sram_c);
169
170
+ /* Clock Control Unit */
171
+ qdev_init_nofail(DEVICE(&s->ccu));
172
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
173
+
174
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
175
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
176
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
177
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
178
new file mode 100644
179
index XXXXXXX..XXXXXXX
180
--- /dev/null
181
+++ b/hw/misc/allwinner-h3-ccu.c
182
@@ -XXX,XX +XXX,XX @@
183
+/*
184
+ * Allwinner H3 Clock Control Unit emulation
185
+ *
186
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
187
+ *
188
+ * This program is free software: you can redistribute it and/or modify
189
+ * it under the terms of the GNU General Public License as published by
190
+ * the Free Software Foundation, either version 2 of the License, or
191
+ * (at your option) any later version.
192
+ *
193
+ * This program is distributed in the hope that it will be useful,
194
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
195
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196
+ * GNU General Public License for more details.
197
+ *
198
+ * You should have received a copy of the GNU General Public License
199
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
200
+ */
201
+
202
+#include "qemu/osdep.h"
203
+#include "qemu/units.h"
204
+#include "hw/sysbus.h"
205
+#include "migration/vmstate.h"
206
+#include "qemu/log.h"
207
+#include "qemu/module.h"
208
+#include "hw/misc/allwinner-h3-ccu.h"
209
+
210
+/* CCU register offsets */
211
+enum {
212
+ REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
213
+ REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
214
+ REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
215
+ REG_PLL_VE = 0x0018, /* PLL VE Control */
216
+ REG_PLL_DDR = 0x0020, /* PLL DDR Control */
217
+ REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
218
+ REG_PLL_GPU = 0x0038, /* PLL GPU Control */
219
+ REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
220
+ REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
221
+ REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
222
+ REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
223
+ REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
224
+ REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
225
+ REG_MBUS = 0x00FC, /* MBUS Reset */
226
+ REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
227
+ REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
228
+ REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
229
+ REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
230
+ REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
231
+ REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
232
+ REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
233
+ REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
234
+ REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
235
+ REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
236
+ REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
237
+ REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
238
+ REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
239
+};
240
+
241
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
242
+
243
+/* CCU register flags */
244
+enum {
245
+ REG_DRAM_CFG_UPDATE = (1 << 16),
246
+};
247
+
248
+enum {
249
+ REG_PLL_ENABLE = (1 << 31),
250
+ REG_PLL_LOCK = (1 << 28),
251
+};
252
+
253
+
254
+/* CCU register reset values */
255
+enum {
256
+ REG_PLL_CPUX_RST = 0x00001000,
257
+ REG_PLL_AUDIO_RST = 0x00035514,
258
+ REG_PLL_VIDEO_RST = 0x03006207,
259
+ REG_PLL_VE_RST = 0x03006207,
260
+ REG_PLL_DDR_RST = 0x00001000,
261
+ REG_PLL_PERIPH0_RST = 0x00041811,
262
+ REG_PLL_GPU_RST = 0x03006207,
263
+ REG_PLL_PERIPH1_RST = 0x00041811,
264
+ REG_PLL_DE_RST = 0x03006207,
265
+ REG_CPUX_AXI_RST = 0x00010000,
266
+ REG_APB1_RST = 0x00001010,
267
+ REG_APB2_RST = 0x01000000,
268
+ REG_DRAM_CFG_RST = 0x00000000,
269
+ REG_MBUS_RST = 0x80000000,
270
+ REG_PLL_TIME0_RST = 0x000000FF,
271
+ REG_PLL_TIME1_RST = 0x000000FF,
272
+ REG_PLL_CPUX_BIAS_RST = 0x08100200,
273
+ REG_PLL_AUDIO_BIAS_RST = 0x10100000,
274
+ REG_PLL_VIDEO_BIAS_RST = 0x10100000,
275
+ REG_PLL_VE_BIAS_RST = 0x10100000,
276
+ REG_PLL_DDR_BIAS_RST = 0x81104000,
277
+ REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
278
+ REG_PLL_GPU_BIAS_RST = 0x10100000,
279
+ REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
280
+ REG_PLL_DE_BIAS_RST = 0x10100000,
281
+ REG_PLL_CPUX_TUNING_RST = 0x0A101000,
282
+ REG_PLL_DDR_TUNING_RST = 0x14880000,
283
+};
284
+
285
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
286
+ unsigned size)
287
+{
31
+{
288
+ const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
32
+ env->features |= 1ULL << feature;
289
+ const uint32_t idx = REG_INDEX(offset);
290
+
291
+ switch (offset) {
292
+ case 0x308 ... AW_H3_CCU_IOSIZE:
293
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
294
+ __func__, (uint32_t)offset);
295
+ return 0;
296
+ }
297
+
298
+ return s->regs[idx];
299
+}
33
+}
300
+
34
+
301
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
35
+static inline void unset_feature(CPUARMState *env, int feature)
302
+ uint64_t val, unsigned size)
303
+{
36
+{
304
+ AwH3ClockCtlState *s = AW_H3_CCU(opaque);
37
+ env->features &= ~(1ULL << feature);
305
+ const uint32_t idx = REG_INDEX(offset);
306
+
307
+ switch (offset) {
308
+ case REG_DRAM_CFG: /* DRAM Configuration */
309
+ val &= ~REG_DRAM_CFG_UPDATE;
310
+ break;
311
+ case REG_PLL_CPUX: /* PLL CPUX Control */
312
+ case REG_PLL_AUDIO: /* PLL Audio Control */
313
+ case REG_PLL_VIDEO: /* PLL Video Control */
314
+ case REG_PLL_VE: /* PLL VE Control */
315
+ case REG_PLL_DDR: /* PLL DDR Control */
316
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
317
+ case REG_PLL_GPU: /* PLL GPU Control */
318
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
319
+ case REG_PLL_DE: /* PLL Display Engine Control */
320
+ if (val & REG_PLL_ENABLE) {
321
+ val |= REG_PLL_LOCK;
322
+ }
323
+ break;
324
+ case 0x308 ... AW_H3_CCU_IOSIZE:
325
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
326
+ __func__, (uint32_t)offset);
327
+ break;
328
+ default:
329
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
330
+ __func__, (uint32_t)offset);
331
+ break;
332
+ }
333
+
334
+ s->regs[idx] = (uint32_t) val;
335
+}
38
+}
336
+
39
+
337
+static const MemoryRegionOps allwinner_h3_ccu_ops = {
40
/**
338
+ .read = allwinner_h3_ccu_read,
41
* ARMELChangeHookFn:
339
+ .write = allwinner_h3_ccu_write,
42
* type of a function which can be registered via arm_register_el_change_hook()
340
+ .endianness = DEVICE_NATIVE_ENDIAN,
43
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
341
+ .valid = {
44
index XXXXXXX..XXXXXXX 100644
342
+ .min_access_size = 4,
45
--- a/target/arm/cpu.c
343
+ .max_access_size = 4,
46
+++ b/target/arm/cpu.c
344
+ },
47
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
345
+ .impl.min_access_size = 4,
48
346
+};
49
#endif
347
+
50
348
+static void allwinner_h3_ccu_reset(DeviceState *dev)
51
-static inline void set_feature(CPUARMState *env, int feature)
349
+{
52
-{
350
+ AwH3ClockCtlState *s = AW_H3_CCU(dev);
53
- env->features |= 1ULL << feature;
351
+
54
-}
352
+ /* Set default values for registers */
55
-
353
+ s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
56
-static inline void unset_feature(CPUARMState *env, int feature)
354
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
57
-{
355
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
58
- env->features &= ~(1ULL << feature);
356
+ s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
59
-}
357
+ s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
60
-
358
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
61
static int
359
+ s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
62
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
360
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
63
{
361
+ s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
64
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
362
+ s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
65
index XXXXXXX..XXXXXXX 100644
363
+ s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
66
--- a/target/arm/cpu64.c
364
+ s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
67
+++ b/target/arm/cpu64.c
365
+ s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
68
@@ -XXX,XX +XXX,XX @@
366
+ s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
69
#include "kvm_arm.h"
367
+ s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
70
#include "qapi/visitor.h"
368
+ s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
71
369
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
72
-static inline void set_feature(CPUARMState *env, int feature)
370
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
73
-{
371
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
74
- env->features |= 1ULL << feature;
372
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
75
-}
373
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
76
-
374
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
77
-static inline void unset_feature(CPUARMState *env, int feature)
375
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
78
-{
376
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
79
- env->features &= ~(1ULL << feature);
377
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
80
-}
378
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
81
-
379
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
82
#ifndef CONFIG_USER_ONLY
380
+}
83
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
381
+
84
{
382
+static void allwinner_h3_ccu_init(Object *obj)
383
+{
384
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
385
+ AwH3ClockCtlState *s = AW_H3_CCU(obj);
386
+
387
+ /* Memory mapping */
388
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
389
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
390
+ sysbus_init_mmio(sbd, &s->iomem);
391
+}
392
+
393
+static const VMStateDescription allwinner_h3_ccu_vmstate = {
394
+ .name = "allwinner-h3-ccu",
395
+ .version_id = 1,
396
+ .minimum_version_id = 1,
397
+ .fields = (VMStateField[]) {
398
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
399
+ VMSTATE_END_OF_LIST()
400
+ }
401
+};
402
+
403
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
404
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
407
+ dc->reset = allwinner_h3_ccu_reset;
408
+ dc->vmsd = &allwinner_h3_ccu_vmstate;
409
+}
410
+
411
+static const TypeInfo allwinner_h3_ccu_info = {
412
+ .name = TYPE_AW_H3_CCU,
413
+ .parent = TYPE_SYS_BUS_DEVICE,
414
+ .instance_init = allwinner_h3_ccu_init,
415
+ .instance_size = sizeof(AwH3ClockCtlState),
416
+ .class_init = allwinner_h3_ccu_class_init,
417
+};
418
+
419
+static void allwinner_h3_ccu_register(void)
420
+{
421
+ type_register_static(&allwinner_h3_ccu_info);
422
+}
423
+
424
+type_init(allwinner_h3_ccu_register)
425
--
85
--
426
2.20.1
86
2.20.1
427
87
428
88
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Restructure the finalize_gic_version with switch cases and
3
Use ARRAY_SIZE() to iterate over ARMCPUInfo[].
4
clearly separate the following cases:
5
4
6
- KVM mode / in-kernel irqchip
5
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
7
- KVM mode / userspace irqchip
6
the cpu_count variable and only iterate when it is non-zero.
8
- TCG mode
9
7
10
In KVM mode / in-kernel irqchip , we explictly check whether
8
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
11
the chosen version is supported by the host. If the end-user
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
explicitly sets v2/v3 and this is not supported by the host,
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
then the user gets an explicit error message. Note that for
11
Message-id: 20200504172448.9402-4-philmd@redhat.com
14
old kernels where the CREATE_DEVICE ioctl doesn't exist then
15
we will now fail if the user specifically asked for gicv2,
16
where previously we (probably) would have succeeded.
17
18
In KVM mode / userspace irqchip we immediatly output an error
19
in case the end-user explicitly selected v3. Also we warn the
20
end-user about the unexpected usage of gic-version=host in
21
that case as only userspace GICv2 is supported.
22
23
Signed-off-by: Eric Auger <eric.auger@redhat.com>
24
Reviewed-by: Andrew Jones <drjones@redhat.com>
25
Message-id: 20200311131618.7187-6-eric.auger@redhat.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
13
---
28
hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------
14
target/arm/cpu.c | 16 +++++++++-------
29
1 file changed, 67 insertions(+), 21 deletions(-)
15
target/arm/cpu64.c | 8 +++-----
16
2 files changed, 12 insertions(+), 12 deletions(-)
30
17
31
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
32
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/virt.c
20
--- a/target/arm/cpu.c
34
+++ b/hw/arm/virt.c
21
+++ b/target/arm/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
22
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
36
*/
23
{ .name = "any", .initfn = arm_max_initfn },
37
static void finalize_gic_version(VirtMachineState *vms)
24
#endif
25
#endif
26
- { .name = NULL }
27
};
28
29
static Property arm_cpu_properties[] = {
30
@@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = {
31
32
static void arm_cpu_register_types(void)
38
{
33
{
39
- if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
34
- const ARMCPUInfo *info = arm_cpus;
40
- vms->gic_version == VIRT_GIC_VERSION_MAX) {
35
+ const size_t cpu_count = ARRAY_SIZE(arm_cpus);
41
- if (!kvm_enabled()) {
36
42
- if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
37
type_register_static(&arm_cpu_type_info);
43
- error_report("gic-version=host requires KVM");
38
type_register_static(&idau_interface_type_info);
44
- exit(1);
39
45
- } else {
40
- while (info->name) {
46
- /* "max": currently means 3 for TCG */
41
- arm_cpu_register(info);
47
- vms->gic_version = VIRT_GIC_VERSION_3;
42
- info++;
48
- }
43
- }
49
- } else {
44
-
50
- int probe_bitmap = kvm_arm_vgic_probe();
45
#ifdef CONFIG_KVM
51
+ if (kvm_enabled()) {
46
type_register_static(&host_arm_cpu_type_info);
52
+ int probe_bitmap;
47
#endif
53
54
- if (!probe_bitmap) {
55
+ if (!kvm_irqchip_in_kernel()) {
56
+ switch (vms->gic_version) {
57
+ case VIRT_GIC_VERSION_HOST:
58
+ warn_report(
59
+ "gic-version=host not relevant with kernel-irqchip=off "
60
+ "as only userspace GICv2 is supported. Using v2 ...");
61
+ return;
62
+ case VIRT_GIC_VERSION_MAX:
63
+ case VIRT_GIC_VERSION_NOSEL:
64
+ vms->gic_version = VIRT_GIC_VERSION_2;
65
+ return;
66
+ case VIRT_GIC_VERSION_2:
67
+ return;
68
+ case VIRT_GIC_VERSION_3:
69
error_report(
70
- "Unable to determine GIC version supported by host");
71
+ "gic-version=3 is not supported with kernel-irqchip=off");
72
exit(1);
73
- } else {
74
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
75
- vms->gic_version = VIRT_GIC_VERSION_3;
76
- } else {
77
- vms->gic_version = VIRT_GIC_VERSION_2;
78
- }
79
}
80
}
81
- } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) {
82
+
48
+
83
+ probe_bitmap = kvm_arm_vgic_probe();
49
+ if (cpu_count) {
84
+ if (!probe_bitmap) {
50
+ size_t i;
85
+ error_report("Unable to determine GIC version supported by host");
51
+
86
+ exit(1);
52
+ for (i = 0; i < cpu_count; ++i) {
53
+ arm_cpu_register(&arm_cpus[i]);
87
+ }
54
+ }
88
+
89
+ switch (vms->gic_version) {
90
+ case VIRT_GIC_VERSION_HOST:
91
+ case VIRT_GIC_VERSION_MAX:
92
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
93
+ vms->gic_version = VIRT_GIC_VERSION_3;
94
+ } else {
95
+ vms->gic_version = VIRT_GIC_VERSION_2;
96
+ }
97
+ return;
98
+ case VIRT_GIC_VERSION_NOSEL:
99
+ vms->gic_version = VIRT_GIC_VERSION_2;
100
+ break;
101
+ case VIRT_GIC_VERSION_2:
102
+ case VIRT_GIC_VERSION_3:
103
+ break;
104
+ }
105
+
106
+ /* Check chosen version is effectively supported by the host */
107
+ if (vms->gic_version == VIRT_GIC_VERSION_2 &&
108
+ !(probe_bitmap & KVM_ARM_VGIC_V2)) {
109
+ error_report("host does not support in-kernel GICv2 emulation");
110
+ exit(1);
111
+ } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
112
+ !(probe_bitmap & KVM_ARM_VGIC_V3)) {
113
+ error_report("host does not support in-kernel GICv3 emulation");
114
+ exit(1);
115
+ }
116
+ return;
117
+ }
55
+ }
118
+
56
}
119
+ /* TCG mode */
57
120
+ switch (vms->gic_version) {
58
type_init(arm_cpu_register_types)
121
+ case VIRT_GIC_VERSION_NOSEL:
59
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
122
vms->gic_version = VIRT_GIC_VERSION_2;
60
index XXXXXXX..XXXXXXX 100644
123
+ break;
61
--- a/target/arm/cpu64.c
124
+ case VIRT_GIC_VERSION_MAX:
62
+++ b/target/arm/cpu64.c
125
+ vms->gic_version = VIRT_GIC_VERSION_3;
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
126
+ break;
64
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
127
+ case VIRT_GIC_VERSION_HOST:
65
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
128
+ error_report("gic-version=host requires KVM");
66
{ .name = "max", .initfn = aarch64_max_initfn },
129
+ exit(1);
67
- { .name = NULL }
130
+ case VIRT_GIC_VERSION_2:
68
};
131
+ case VIRT_GIC_VERSION_3:
69
132
+ break;
70
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
71
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = {
72
73
static void aarch64_cpu_register_types(void)
74
{
75
- const ARMCPUInfo *info = aarch64_cpus;
76
+ size_t i;
77
78
type_register_static(&aarch64_cpu_type_info);
79
80
- while (info->name) {
81
- aarch64_cpu_register(info);
82
- info++;
83
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
84
+ aarch64_cpu_register(&aarch64_cpus[i]);
133
}
85
}
134
}
86
}
135
87
136
--
88
--
137
2.20.1
89
2.20.1
138
90
139
91
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs.
4
the serial output is working.
5
6
The kernel image and DeviceTree blob are built by the Armbian
7
project (based on Debian):
8
https://www.armbian.com/orange-pi-pc/
9
10
The cpio image used comes from the linux-build-test project:
11
https://github.com/groeck/linux-build-test
12
13
If ARM is a target being built, "make check-acceptance" will
14
automatically include this test by the use of the "arch:arm" tags.
15
16
Alternatively, this test can be run using:
17
18
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
19
console: Uncompressing Linux... done, booting the kernel.
20
console: Booting Linux on physical CPU 0x0
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
23
console: CPU: div instructions available: patching division code
24
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
25
console: OF: fdt: Machine model: Xunlong Orange Pi PC
26
[...]
27
console: Trying to unpack rootfs image as initramfs...
28
console: Freeing initrd memory: 3256K
29
console: Freeing unused kernel memory: 1024K
30
console: Run /init as init process
31
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
32
console: Starting logging: OK
33
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
34
console: done.
35
console: Starting network: OK
36
console: Found console ttyS0
37
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
38
console: Boot successful.
39
console: cat /proc/cpuinfo
40
console: / # cat /proc/cpuinfo
41
console: processor : 0
42
console: model name : ARMv7 Processor rev 5 (v7l)
43
console: BogoMIPS : 125.00
44
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
45
console: CPU implementer : 0x41
46
console: CPU architecture: 7
47
console: CPU variant : 0x0
48
console: CPU part : 0xc07
49
console: CPU revision : 5
50
[...]
51
console: processor : 3
52
console: model name : ARMv7 Processor rev 5 (v7l)
53
console: BogoMIPS : 125.00
54
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
55
console: CPU implementer : 0x41
56
console: CPU architecture: 7
57
console: CPU variant : 0x0
58
console: CPU part : 0xc07
59
console: CPU revision : 5
60
console: Hardware : Allwinner sun8i Family
61
console: Revision : 0000
62
console: Serial : 0000000000000000
63
console: cat /proc/iomem
64
console: / # cat /proc/iomem
65
console: 01000000-010fffff : clock@1000000
66
console: 01c00000-01c00fff : system-control@1c00000
67
console: 01c02000-01c02fff : dma-controller@1c02000
68
[...]
69
console: reboot
70
console: / # reboot
71
console: / # Found console ttyS0
72
console: Stopping network: OK
73
console: hrtimer: interrupt took 21852064 ns
74
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
75
console: done.
76
console: Stopping logging: OK
77
console: umount: devtmpfs busy - remounted read-only
78
console: umount: can't unmount /: Invalid argument
79
console: The system is going down NOW!
80
console: Sent SIGTERM to all processes
81
console: Sent SIGKILL to all processes
82
console: Requesting system reboot
83
console: reboot: Restarting system
84
PASS (48.32 s)
85
JOB TIME : 49.16 s
86
4
87
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
88
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
89
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200504172448.9402-5-philmd@redhat.com
90
Tested-by: Alex Bennée <alex.bennee@linaro.org>
91
Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com
92
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
93
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94
---
9
---
95
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
10
target/arm/cpu.c | 2 +-
96
1 file changed, 40 insertions(+)
11
1 file changed, 1 insertion(+), 1 deletion(-)
97
12
98
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
99
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
100
--- a/tests/acceptance/boot_linux_console.py
15
--- a/target/arm/cpu.c
101
+++ b/tests/acceptance/boot_linux_console.py
16
+++ b/target/arm/cpu.c
102
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
17
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
103
console_pattern = 'Kernel command line: %s' % kernel_command_line
18
const size_t cpu_count = ARRAY_SIZE(arm_cpus);
104
self.wait_for_console_pattern(console_pattern)
19
105
20
type_register_static(&arm_cpu_type_info);
106
+ def test_arm_orangepi_initrd(self):
21
- type_register_static(&idau_interface_type_info);
107
+ """
22
108
+ :avocado: tags=arch:arm
23
#ifdef CONFIG_KVM
109
+ :avocado: tags=machine:orangepi-pc
24
type_register_static(&host_arm_cpu_type_info);
110
+ """
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
111
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
26
if (cpu_count) {
112
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
27
size_t i;
113
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
28
114
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
29
+ type_register_static(&idau_interface_type_info);
115
+ kernel_path = self.extract_from_deb(deb_path,
30
for (i = 0; i < cpu_count; ++i) {
116
+ '/boot/vmlinuz-4.20.7-sunxi')
31
arm_cpu_register(&arm_cpus[i]);
117
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
32
}
118
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
119
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
120
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
121
+ 'arm/rootfs-armv7a.cpio.gz')
122
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
123
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
124
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
125
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
126
+
127
+ self.vm.set_console()
128
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
129
+ 'console=ttyS0,115200 '
130
+ 'panic=-1 noreboot')
131
+ self.vm.add_args('-kernel', kernel_path,
132
+ '-dtb', dtb_path,
133
+ '-initrd', initrd_path,
134
+ '-append', kernel_command_line,
135
+ '-no-reboot')
136
+ self.vm.launch()
137
+ self.wait_for_console_pattern('Boot successful.')
138
+
139
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
140
+ 'Allwinner sun8i Family')
141
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
142
+ 'system-control@1c00000')
143
+ exec_command_and_wait_for_pattern(self, 'reboot',
144
+ 'reboot: Restarting system')
145
+
146
def test_s390x_s390_ccw_virtio(self):
147
"""
148
:avocado: tags=arch:s390x
149
--
33
--
150
2.20.1
34
2.20.1
151
35
152
36
diff view generated by jsdifflib
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
3
A KVM-only build won't be able to run TCG cpus.
4
processor cores. Features and specifications include DDR2/DDR3 memory,
5
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
6
various I/O modules. This commit adds support for the Allwinner H3
7
System on Chip.
8
4
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200504172448.9402-6-philmd@redhat.com
12
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
9
---
16
hw/arm/Makefile.objs | 1 +
10
target/arm/cpu.c | 634 -------------------------------------
17
include/hw/arm/allwinner-h3.h | 106 +++++++++++
11
target/arm/cpu_tcg.c | 664 +++++++++++++++++++++++++++++++++++++++
18
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
12
target/arm/Makefile.objs | 1 +
19
MAINTAINERS | 7 +
13
3 files changed, 665 insertions(+), 634 deletions(-)
20
default-configs/arm-softmmu.mak | 1 +
14
create mode 100644 target/arm/cpu_tcg.c
21
hw/arm/Kconfig | 8 +
22
6 files changed, 450 insertions(+)
23
create mode 100644 include/hw/arm/allwinner-h3.h
24
create mode 100644 hw/arm/allwinner-h3.c
25
15
26
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
27
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/Makefile.objs
18
--- a/target/arm/cpu.c
29
+++ b/hw/arm/Makefile.objs
19
+++ b/target/arm/cpu.c
30
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o
20
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
31
obj-$(CONFIG_OMAP) += omap1.o omap2.o
21
return true;
32
obj-$(CONFIG_STRONGARM) += strongarm.o
22
}
33
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
23
34
+obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o
24
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
35
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
25
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
36
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
26
-{
37
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
27
- CPUClass *cc = CPU_GET_CLASS(cs);
38
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
28
- ARMCPU *cpu = ARM_CPU(cs);
29
- CPUARMState *env = &cpu->env;
30
- bool ret = false;
31
-
32
- /*
33
- * ARMv7-M interrupt masking works differently than -A or -R.
34
- * There is no FIQ/IRQ distinction. Instead of I and F bits
35
- * masking FIQ and IRQ interrupts, an exception is taken only
36
- * if it is higher priority than the current execution priority
37
- * (which depends on state like BASEPRI, FAULTMASK and the
38
- * currently active exception).
39
- */
40
- if (interrupt_request & CPU_INTERRUPT_HARD
41
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
42
- cs->exception_index = EXCP_IRQ;
43
- cc->do_interrupt(cs);
44
- ret = true;
45
- }
46
- return ret;
47
-}
48
-#endif
49
-
50
void arm_cpu_update_virq(ARMCPU *cpu)
51
{
52
/*
53
@@ -XXX,XX +XXX,XX @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
54
/* CPU models. These are not needed for the AArch64 linux-user build. */
55
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
56
57
-static void arm926_initfn(Object *obj)
58
-{
59
- ARMCPU *cpu = ARM_CPU(obj);
60
-
61
- cpu->dtb_compatible = "arm,arm926";
62
- set_feature(&cpu->env, ARM_FEATURE_V5);
63
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
64
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
65
- cpu->midr = 0x41069265;
66
- cpu->reset_fpsid = 0x41011090;
67
- cpu->ctr = 0x1dd20d2;
68
- cpu->reset_sctlr = 0x00090078;
69
-
70
- /*
71
- * ARMv5 does not have the ID_ISAR registers, but we can still
72
- * set the field to indicate Jazelle support within QEMU.
73
- */
74
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
75
- /*
76
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
77
- * support even though ARMv5 doesn't have this register.
78
- */
79
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
80
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
81
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
82
-}
83
-
84
-static void arm946_initfn(Object *obj)
85
-{
86
- ARMCPU *cpu = ARM_CPU(obj);
87
-
88
- cpu->dtb_compatible = "arm,arm946";
89
- set_feature(&cpu->env, ARM_FEATURE_V5);
90
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
91
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
92
- cpu->midr = 0x41059461;
93
- cpu->ctr = 0x0f004006;
94
- cpu->reset_sctlr = 0x00000078;
95
-}
96
-
97
-static void arm1026_initfn(Object *obj)
98
-{
99
- ARMCPU *cpu = ARM_CPU(obj);
100
-
101
- cpu->dtb_compatible = "arm,arm1026";
102
- set_feature(&cpu->env, ARM_FEATURE_V5);
103
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
104
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
106
- cpu->midr = 0x4106a262;
107
- cpu->reset_fpsid = 0x410110a0;
108
- cpu->ctr = 0x1dd20d2;
109
- cpu->reset_sctlr = 0x00090078;
110
- cpu->reset_auxcr = 1;
111
-
112
- /*
113
- * ARMv5 does not have the ID_ISAR registers, but we can still
114
- * set the field to indicate Jazelle support within QEMU.
115
- */
116
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
117
- /*
118
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
119
- * support even though ARMv5 doesn't have this register.
120
- */
121
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
122
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
123
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
124
-
125
- {
126
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
127
- ARMCPRegInfo ifar = {
128
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
129
- .access = PL1_RW,
130
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
131
- .resetvalue = 0
132
- };
133
- define_one_arm_cp_reg(cpu, &ifar);
134
- }
135
-}
136
-
137
-static void arm1136_r2_initfn(Object *obj)
138
-{
139
- ARMCPU *cpu = ARM_CPU(obj);
140
- /*
141
- * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
142
- * older core than plain "arm1136". In particular this does not
143
- * have the v6K features.
144
- * These ID register values are correct for 1136 but may be wrong
145
- * for 1136_r2 (in particular r0p2 does not actually implement most
146
- * of the ID registers).
147
- */
148
-
149
- cpu->dtb_compatible = "arm,arm1136";
150
- set_feature(&cpu->env, ARM_FEATURE_V6);
151
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
152
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
153
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
154
- cpu->midr = 0x4107b362;
155
- cpu->reset_fpsid = 0x410120b4;
156
- cpu->isar.mvfr0 = 0x11111111;
157
- cpu->isar.mvfr1 = 0x00000000;
158
- cpu->ctr = 0x1dd20d2;
159
- cpu->reset_sctlr = 0x00050078;
160
- cpu->id_pfr0 = 0x111;
161
- cpu->id_pfr1 = 0x1;
162
- cpu->isar.id_dfr0 = 0x2;
163
- cpu->id_afr0 = 0x3;
164
- cpu->isar.id_mmfr0 = 0x01130003;
165
- cpu->isar.id_mmfr1 = 0x10030302;
166
- cpu->isar.id_mmfr2 = 0x01222110;
167
- cpu->isar.id_isar0 = 0x00140011;
168
- cpu->isar.id_isar1 = 0x12002111;
169
- cpu->isar.id_isar2 = 0x11231111;
170
- cpu->isar.id_isar3 = 0x01102131;
171
- cpu->isar.id_isar4 = 0x141;
172
- cpu->reset_auxcr = 7;
173
-}
174
-
175
-static void arm1136_initfn(Object *obj)
176
-{
177
- ARMCPU *cpu = ARM_CPU(obj);
178
-
179
- cpu->dtb_compatible = "arm,arm1136";
180
- set_feature(&cpu->env, ARM_FEATURE_V6K);
181
- set_feature(&cpu->env, ARM_FEATURE_V6);
182
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
183
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
184
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
185
- cpu->midr = 0x4117b363;
186
- cpu->reset_fpsid = 0x410120b4;
187
- cpu->isar.mvfr0 = 0x11111111;
188
- cpu->isar.mvfr1 = 0x00000000;
189
- cpu->ctr = 0x1dd20d2;
190
- cpu->reset_sctlr = 0x00050078;
191
- cpu->id_pfr0 = 0x111;
192
- cpu->id_pfr1 = 0x1;
193
- cpu->isar.id_dfr0 = 0x2;
194
- cpu->id_afr0 = 0x3;
195
- cpu->isar.id_mmfr0 = 0x01130003;
196
- cpu->isar.id_mmfr1 = 0x10030302;
197
- cpu->isar.id_mmfr2 = 0x01222110;
198
- cpu->isar.id_isar0 = 0x00140011;
199
- cpu->isar.id_isar1 = 0x12002111;
200
- cpu->isar.id_isar2 = 0x11231111;
201
- cpu->isar.id_isar3 = 0x01102131;
202
- cpu->isar.id_isar4 = 0x141;
203
- cpu->reset_auxcr = 7;
204
-}
205
-
206
-static void arm1176_initfn(Object *obj)
207
-{
208
- ARMCPU *cpu = ARM_CPU(obj);
209
-
210
- cpu->dtb_compatible = "arm,arm1176";
211
- set_feature(&cpu->env, ARM_FEATURE_V6K);
212
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
213
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
214
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
215
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
216
- set_feature(&cpu->env, ARM_FEATURE_EL3);
217
- cpu->midr = 0x410fb767;
218
- cpu->reset_fpsid = 0x410120b5;
219
- cpu->isar.mvfr0 = 0x11111111;
220
- cpu->isar.mvfr1 = 0x00000000;
221
- cpu->ctr = 0x1dd20d2;
222
- cpu->reset_sctlr = 0x00050078;
223
- cpu->id_pfr0 = 0x111;
224
- cpu->id_pfr1 = 0x11;
225
- cpu->isar.id_dfr0 = 0x33;
226
- cpu->id_afr0 = 0;
227
- cpu->isar.id_mmfr0 = 0x01130003;
228
- cpu->isar.id_mmfr1 = 0x10030302;
229
- cpu->isar.id_mmfr2 = 0x01222100;
230
- cpu->isar.id_isar0 = 0x0140011;
231
- cpu->isar.id_isar1 = 0x12002111;
232
- cpu->isar.id_isar2 = 0x11231121;
233
- cpu->isar.id_isar3 = 0x01102131;
234
- cpu->isar.id_isar4 = 0x01141;
235
- cpu->reset_auxcr = 7;
236
-}
237
-
238
-static void arm11mpcore_initfn(Object *obj)
239
-{
240
- ARMCPU *cpu = ARM_CPU(obj);
241
-
242
- cpu->dtb_compatible = "arm,arm11mpcore";
243
- set_feature(&cpu->env, ARM_FEATURE_V6K);
244
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
245
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
246
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
247
- cpu->midr = 0x410fb022;
248
- cpu->reset_fpsid = 0x410120b4;
249
- cpu->isar.mvfr0 = 0x11111111;
250
- cpu->isar.mvfr1 = 0x00000000;
251
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
252
- cpu->id_pfr0 = 0x111;
253
- cpu->id_pfr1 = 0x1;
254
- cpu->isar.id_dfr0 = 0;
255
- cpu->id_afr0 = 0x2;
256
- cpu->isar.id_mmfr0 = 0x01100103;
257
- cpu->isar.id_mmfr1 = 0x10020302;
258
- cpu->isar.id_mmfr2 = 0x01222000;
259
- cpu->isar.id_isar0 = 0x00100011;
260
- cpu->isar.id_isar1 = 0x12002111;
261
- cpu->isar.id_isar2 = 0x11221011;
262
- cpu->isar.id_isar3 = 0x01102131;
263
- cpu->isar.id_isar4 = 0x141;
264
- cpu->reset_auxcr = 1;
265
-}
266
-
267
-static void cortex_m0_initfn(Object *obj)
268
-{
269
- ARMCPU *cpu = ARM_CPU(obj);
270
- set_feature(&cpu->env, ARM_FEATURE_V6);
271
- set_feature(&cpu->env, ARM_FEATURE_M);
272
-
273
- cpu->midr = 0x410cc200;
274
-}
275
-
276
-static void cortex_m3_initfn(Object *obj)
277
-{
278
- ARMCPU *cpu = ARM_CPU(obj);
279
- set_feature(&cpu->env, ARM_FEATURE_V7);
280
- set_feature(&cpu->env, ARM_FEATURE_M);
281
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
282
- cpu->midr = 0x410fc231;
283
- cpu->pmsav7_dregion = 8;
284
- cpu->id_pfr0 = 0x00000030;
285
- cpu->id_pfr1 = 0x00000200;
286
- cpu->isar.id_dfr0 = 0x00100000;
287
- cpu->id_afr0 = 0x00000000;
288
- cpu->isar.id_mmfr0 = 0x00000030;
289
- cpu->isar.id_mmfr1 = 0x00000000;
290
- cpu->isar.id_mmfr2 = 0x00000000;
291
- cpu->isar.id_mmfr3 = 0x00000000;
292
- cpu->isar.id_isar0 = 0x01141110;
293
- cpu->isar.id_isar1 = 0x02111000;
294
- cpu->isar.id_isar2 = 0x21112231;
295
- cpu->isar.id_isar3 = 0x01111110;
296
- cpu->isar.id_isar4 = 0x01310102;
297
- cpu->isar.id_isar5 = 0x00000000;
298
- cpu->isar.id_isar6 = 0x00000000;
299
-}
300
-
301
-static void cortex_m4_initfn(Object *obj)
302
-{
303
- ARMCPU *cpu = ARM_CPU(obj);
304
-
305
- set_feature(&cpu->env, ARM_FEATURE_V7);
306
- set_feature(&cpu->env, ARM_FEATURE_M);
307
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
308
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
309
- cpu->midr = 0x410fc240; /* r0p0 */
310
- cpu->pmsav7_dregion = 8;
311
- cpu->isar.mvfr0 = 0x10110021;
312
- cpu->isar.mvfr1 = 0x11000011;
313
- cpu->isar.mvfr2 = 0x00000000;
314
- cpu->id_pfr0 = 0x00000030;
315
- cpu->id_pfr1 = 0x00000200;
316
- cpu->isar.id_dfr0 = 0x00100000;
317
- cpu->id_afr0 = 0x00000000;
318
- cpu->isar.id_mmfr0 = 0x00000030;
319
- cpu->isar.id_mmfr1 = 0x00000000;
320
- cpu->isar.id_mmfr2 = 0x00000000;
321
- cpu->isar.id_mmfr3 = 0x00000000;
322
- cpu->isar.id_isar0 = 0x01141110;
323
- cpu->isar.id_isar1 = 0x02111000;
324
- cpu->isar.id_isar2 = 0x21112231;
325
- cpu->isar.id_isar3 = 0x01111110;
326
- cpu->isar.id_isar4 = 0x01310102;
327
- cpu->isar.id_isar5 = 0x00000000;
328
- cpu->isar.id_isar6 = 0x00000000;
329
-}
330
-
331
-static void cortex_m7_initfn(Object *obj)
332
-{
333
- ARMCPU *cpu = ARM_CPU(obj);
334
-
335
- set_feature(&cpu->env, ARM_FEATURE_V7);
336
- set_feature(&cpu->env, ARM_FEATURE_M);
337
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
338
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
339
- cpu->midr = 0x411fc272; /* r1p2 */
340
- cpu->pmsav7_dregion = 8;
341
- cpu->isar.mvfr0 = 0x10110221;
342
- cpu->isar.mvfr1 = 0x12000011;
343
- cpu->isar.mvfr2 = 0x00000040;
344
- cpu->id_pfr0 = 0x00000030;
345
- cpu->id_pfr1 = 0x00000200;
346
- cpu->isar.id_dfr0 = 0x00100000;
347
- cpu->id_afr0 = 0x00000000;
348
- cpu->isar.id_mmfr0 = 0x00100030;
349
- cpu->isar.id_mmfr1 = 0x00000000;
350
- cpu->isar.id_mmfr2 = 0x01000000;
351
- cpu->isar.id_mmfr3 = 0x00000000;
352
- cpu->isar.id_isar0 = 0x01101110;
353
- cpu->isar.id_isar1 = 0x02112000;
354
- cpu->isar.id_isar2 = 0x20232231;
355
- cpu->isar.id_isar3 = 0x01111131;
356
- cpu->isar.id_isar4 = 0x01310132;
357
- cpu->isar.id_isar5 = 0x00000000;
358
- cpu->isar.id_isar6 = 0x00000000;
359
-}
360
-
361
-static void cortex_m33_initfn(Object *obj)
362
-{
363
- ARMCPU *cpu = ARM_CPU(obj);
364
-
365
- set_feature(&cpu->env, ARM_FEATURE_V8);
366
- set_feature(&cpu->env, ARM_FEATURE_M);
367
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
368
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
369
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
370
- cpu->midr = 0x410fd213; /* r0p3 */
371
- cpu->pmsav7_dregion = 16;
372
- cpu->sau_sregion = 8;
373
- cpu->isar.mvfr0 = 0x10110021;
374
- cpu->isar.mvfr1 = 0x11000011;
375
- cpu->isar.mvfr2 = 0x00000040;
376
- cpu->id_pfr0 = 0x00000030;
377
- cpu->id_pfr1 = 0x00000210;
378
- cpu->isar.id_dfr0 = 0x00200000;
379
- cpu->id_afr0 = 0x00000000;
380
- cpu->isar.id_mmfr0 = 0x00101F40;
381
- cpu->isar.id_mmfr1 = 0x00000000;
382
- cpu->isar.id_mmfr2 = 0x01000000;
383
- cpu->isar.id_mmfr3 = 0x00000000;
384
- cpu->isar.id_isar0 = 0x01101110;
385
- cpu->isar.id_isar1 = 0x02212000;
386
- cpu->isar.id_isar2 = 0x20232232;
387
- cpu->isar.id_isar3 = 0x01111131;
388
- cpu->isar.id_isar4 = 0x01310132;
389
- cpu->isar.id_isar5 = 0x00000000;
390
- cpu->isar.id_isar6 = 0x00000000;
391
- cpu->clidr = 0x00000000;
392
- cpu->ctr = 0x8000c000;
393
-}
394
-
395
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
396
-{
397
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
398
- CPUClass *cc = CPU_CLASS(oc);
399
-
400
- acc->info = data;
401
-#ifndef CONFIG_USER_ONLY
402
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
403
-#endif
404
-
405
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
406
-}
407
-
408
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
409
- /* Dummy the TCM region regs for the moment */
410
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
411
- .access = PL1_RW, .type = ARM_CP_CONST },
412
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
413
- .access = PL1_RW, .type = ARM_CP_CONST },
414
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
415
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
416
- REGINFO_SENTINEL
417
-};
418
-
419
-static void cortex_r5_initfn(Object *obj)
420
-{
421
- ARMCPU *cpu = ARM_CPU(obj);
422
-
423
- set_feature(&cpu->env, ARM_FEATURE_V7);
424
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
425
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
426
- set_feature(&cpu->env, ARM_FEATURE_PMU);
427
- cpu->midr = 0x411fc153; /* r1p3 */
428
- cpu->id_pfr0 = 0x0131;
429
- cpu->id_pfr1 = 0x001;
430
- cpu->isar.id_dfr0 = 0x010400;
431
- cpu->id_afr0 = 0x0;
432
- cpu->isar.id_mmfr0 = 0x0210030;
433
- cpu->isar.id_mmfr1 = 0x00000000;
434
- cpu->isar.id_mmfr2 = 0x01200000;
435
- cpu->isar.id_mmfr3 = 0x0211;
436
- cpu->isar.id_isar0 = 0x02101111;
437
- cpu->isar.id_isar1 = 0x13112111;
438
- cpu->isar.id_isar2 = 0x21232141;
439
- cpu->isar.id_isar3 = 0x01112131;
440
- cpu->isar.id_isar4 = 0x0010142;
441
- cpu->isar.id_isar5 = 0x0;
442
- cpu->isar.id_isar6 = 0x0;
443
- cpu->mp_is_up = true;
444
- cpu->pmsav7_dregion = 16;
445
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
446
-}
447
-
448
-static void cortex_r5f_initfn(Object *obj)
449
-{
450
- ARMCPU *cpu = ARM_CPU(obj);
451
-
452
- cortex_r5_initfn(obj);
453
- cpu->isar.mvfr0 = 0x10110221;
454
- cpu->isar.mvfr1 = 0x00000011;
455
-}
456
-
457
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
458
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
459
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
460
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
461
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
462
}
463
464
-static void ti925t_initfn(Object *obj)
465
-{
466
- ARMCPU *cpu = ARM_CPU(obj);
467
- set_feature(&cpu->env, ARM_FEATURE_V4T);
468
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
469
- cpu->midr = ARM_CPUID_TI925T;
470
- cpu->ctr = 0x5109149;
471
- cpu->reset_sctlr = 0x00000070;
472
-}
473
-
474
-static void sa1100_initfn(Object *obj)
475
-{
476
- ARMCPU *cpu = ARM_CPU(obj);
477
-
478
- cpu->dtb_compatible = "intel,sa1100";
479
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
480
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
481
- cpu->midr = 0x4401A11B;
482
- cpu->reset_sctlr = 0x00000070;
483
-}
484
-
485
-static void sa1110_initfn(Object *obj)
486
-{
487
- ARMCPU *cpu = ARM_CPU(obj);
488
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
489
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
490
- cpu->midr = 0x6901B119;
491
- cpu->reset_sctlr = 0x00000070;
492
-}
493
-
494
-static void pxa250_initfn(Object *obj)
495
-{
496
- ARMCPU *cpu = ARM_CPU(obj);
497
-
498
- cpu->dtb_compatible = "marvell,xscale";
499
- set_feature(&cpu->env, ARM_FEATURE_V5);
500
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
501
- cpu->midr = 0x69052100;
502
- cpu->ctr = 0xd172172;
503
- cpu->reset_sctlr = 0x00000078;
504
-}
505
-
506
-static void pxa255_initfn(Object *obj)
507
-{
508
- ARMCPU *cpu = ARM_CPU(obj);
509
-
510
- cpu->dtb_compatible = "marvell,xscale";
511
- set_feature(&cpu->env, ARM_FEATURE_V5);
512
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
513
- cpu->midr = 0x69052d00;
514
- cpu->ctr = 0xd172172;
515
- cpu->reset_sctlr = 0x00000078;
516
-}
517
-
518
-static void pxa260_initfn(Object *obj)
519
-{
520
- ARMCPU *cpu = ARM_CPU(obj);
521
-
522
- cpu->dtb_compatible = "marvell,xscale";
523
- set_feature(&cpu->env, ARM_FEATURE_V5);
524
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
525
- cpu->midr = 0x69052903;
526
- cpu->ctr = 0xd172172;
527
- cpu->reset_sctlr = 0x00000078;
528
-}
529
-
530
-static void pxa261_initfn(Object *obj)
531
-{
532
- ARMCPU *cpu = ARM_CPU(obj);
533
-
534
- cpu->dtb_compatible = "marvell,xscale";
535
- set_feature(&cpu->env, ARM_FEATURE_V5);
536
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
537
- cpu->midr = 0x69052d05;
538
- cpu->ctr = 0xd172172;
539
- cpu->reset_sctlr = 0x00000078;
540
-}
541
-
542
-static void pxa262_initfn(Object *obj)
543
-{
544
- ARMCPU *cpu = ARM_CPU(obj);
545
-
546
- cpu->dtb_compatible = "marvell,xscale";
547
- set_feature(&cpu->env, ARM_FEATURE_V5);
548
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
549
- cpu->midr = 0x69052d06;
550
- cpu->ctr = 0xd172172;
551
- cpu->reset_sctlr = 0x00000078;
552
-}
553
-
554
-static void pxa270a0_initfn(Object *obj)
555
-{
556
- ARMCPU *cpu = ARM_CPU(obj);
557
-
558
- cpu->dtb_compatible = "marvell,xscale";
559
- set_feature(&cpu->env, ARM_FEATURE_V5);
560
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
561
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
562
- cpu->midr = 0x69054110;
563
- cpu->ctr = 0xd172172;
564
- cpu->reset_sctlr = 0x00000078;
565
-}
566
-
567
-static void pxa270a1_initfn(Object *obj)
568
-{
569
- ARMCPU *cpu = ARM_CPU(obj);
570
-
571
- cpu->dtb_compatible = "marvell,xscale";
572
- set_feature(&cpu->env, ARM_FEATURE_V5);
573
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
574
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
575
- cpu->midr = 0x69054111;
576
- cpu->ctr = 0xd172172;
577
- cpu->reset_sctlr = 0x00000078;
578
-}
579
-
580
-static void pxa270b0_initfn(Object *obj)
581
-{
582
- ARMCPU *cpu = ARM_CPU(obj);
583
-
584
- cpu->dtb_compatible = "marvell,xscale";
585
- set_feature(&cpu->env, ARM_FEATURE_V5);
586
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
587
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
588
- cpu->midr = 0x69054112;
589
- cpu->ctr = 0xd172172;
590
- cpu->reset_sctlr = 0x00000078;
591
-}
592
-
593
-static void pxa270b1_initfn(Object *obj)
594
-{
595
- ARMCPU *cpu = ARM_CPU(obj);
596
-
597
- cpu->dtb_compatible = "marvell,xscale";
598
- set_feature(&cpu->env, ARM_FEATURE_V5);
599
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
600
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
601
- cpu->midr = 0x69054113;
602
- cpu->ctr = 0xd172172;
603
- cpu->reset_sctlr = 0x00000078;
604
-}
605
-
606
-static void pxa270c0_initfn(Object *obj)
607
-{
608
- ARMCPU *cpu = ARM_CPU(obj);
609
-
610
- cpu->dtb_compatible = "marvell,xscale";
611
- set_feature(&cpu->env, ARM_FEATURE_V5);
612
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
613
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
614
- cpu->midr = 0x69054114;
615
- cpu->ctr = 0xd172172;
616
- cpu->reset_sctlr = 0x00000078;
617
-}
618
-
619
-static void pxa270c5_initfn(Object *obj)
620
-{
621
- ARMCPU *cpu = ARM_CPU(obj);
622
-
623
- cpu->dtb_compatible = "marvell,xscale";
624
- set_feature(&cpu->env, ARM_FEATURE_V5);
625
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
626
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
627
- cpu->midr = 0x69054117;
628
- cpu->ctr = 0xd172172;
629
- cpu->reset_sctlr = 0x00000078;
630
-}
631
-
632
#ifndef TARGET_AARCH64
633
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
634
* otherwise, a CPU with as many features enabled as our emulation supports.
635
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
636
637
static const ARMCPUInfo arm_cpus[] = {
638
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
639
- { .name = "arm926", .initfn = arm926_initfn },
640
- { .name = "arm946", .initfn = arm946_initfn },
641
- { .name = "arm1026", .initfn = arm1026_initfn },
642
- /*
643
- * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
644
- * older core than plain "arm1136". In particular this does not
645
- * have the v6K features.
646
- */
647
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
648
- { .name = "arm1136", .initfn = arm1136_initfn },
649
- { .name = "arm1176", .initfn = arm1176_initfn },
650
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
651
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
652
- .class_init = arm_v7m_class_init },
653
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
654
- .class_init = arm_v7m_class_init },
655
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
656
- .class_init = arm_v7m_class_init },
657
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
658
- .class_init = arm_v7m_class_init },
659
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
660
- .class_init = arm_v7m_class_init },
661
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
662
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
663
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
664
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
665
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
666
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
667
- { .name = "ti925t", .initfn = ti925t_initfn },
668
- { .name = "sa1100", .initfn = sa1100_initfn },
669
- { .name = "sa1110", .initfn = sa1110_initfn },
670
- { .name = "pxa250", .initfn = pxa250_initfn },
671
- { .name = "pxa255", .initfn = pxa255_initfn },
672
- { .name = "pxa260", .initfn = pxa260_initfn },
673
- { .name = "pxa261", .initfn = pxa261_initfn },
674
- { .name = "pxa262", .initfn = pxa262_initfn },
675
- /* "pxa270" is an alias for "pxa270-a0" */
676
- { .name = "pxa270", .initfn = pxa270a0_initfn },
677
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
678
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
679
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
680
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
681
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
682
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
683
#ifndef TARGET_AARCH64
684
{ .name = "max", .initfn = arm_max_initfn },
685
#endif
686
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
39
new file mode 100644
687
new file mode 100644
40
index XXXXXXX..XXXXXXX
688
index XXXXXXX..XXXXXXX
41
--- /dev/null
689
--- /dev/null
42
+++ b/include/hw/arm/allwinner-h3.h
690
+++ b/target/arm/cpu_tcg.c
43
@@ -XXX,XX +XXX,XX @@
691
@@ -XXX,XX +XXX,XX @@
44
+/*
692
+/*
45
+ * Allwinner H3 System on Chip emulation
693
+ * QEMU ARM TCG CPUs.
46
+ *
694
+ *
47
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
695
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
48
+ *
696
+ *
49
+ * This program is free software: you can redistribute it and/or modify
697
+ * This code is licensed under the GNU GPL v2 or later.
50
+ * it under the terms of the GNU General Public License as published by
51
+ * the Free Software Foundation, either version 2 of the License, or
52
+ * (at your option) any later version.
53
+ *
698
+ *
54
+ * This program is distributed in the hope that it will be useful,
699
+ * SPDX-License-Identifier: GPL-2.0-or-later
55
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
56
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57
+ * GNU General Public License for more details.
58
+ *
59
+ * You should have received a copy of the GNU General Public License
60
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
61
+ */
700
+ */
62
+
701
+
63
+/*
702
+#include "qemu/osdep.h"
64
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
703
+#include "cpu.h"
65
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
704
+#include "internals.h"
66
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
705
+
67
+ * various I/O modules.
706
+/* CPU models. These are not needed for the AArch64 linux-user build. */
68
+ *
707
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
69
+ * This implementation is based on the following datasheet:
708
+
70
+ *
709
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
71
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
710
+{
72
+ *
711
+ CPUClass *cc = CPU_GET_CLASS(cs);
73
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
712
+ ARMCPU *cpu = ARM_CPU(cs);
74
+ *
713
+ CPUARMState *env = &cpu->env;
75
+ * https://linux-sunxi.org/H3
714
+ bool ret = false;
76
+ */
715
+
77
+
716
+ /*
78
+#ifndef HW_ARM_ALLWINNER_H3_H
717
+ * ARMv7-M interrupt masking works differently than -A or -R.
79
+#define HW_ARM_ALLWINNER_H3_H
718
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
80
+
719
+ * masking FIQ and IRQ interrupts, an exception is taken only
81
+#include "qom/object.h"
720
+ * if it is higher priority than the current execution priority
82
+#include "hw/arm/boot.h"
721
+ * (which depends on state like BASEPRI, FAULTMASK and the
83
+#include "hw/timer/allwinner-a10-pit.h"
722
+ * currently active exception).
84
+#include "hw/intc/arm_gic.h"
723
+ */
85
+#include "target/arm/cpu.h"
724
+ if (interrupt_request & CPU_INTERRUPT_HARD
86
+
725
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
87
+/**
726
+ cs->exception_index = EXCP_IRQ;
88
+ * Allwinner H3 device list
727
+ cc->do_interrupt(cs);
89
+ *
728
+ ret = true;
90
+ * This enumeration is can be used refer to a particular device in the
729
+ }
91
+ * Allwinner H3 SoC. For example, the physical memory base address for
730
+ return ret;
92
+ * each device can be found in the AwH3State object in the memmap member
731
+}
93
+ * using the device enum value as index.
732
+
94
+ *
733
+static void arm926_initfn(Object *obj)
95
+ * @see AwH3State
734
+{
96
+ */
735
+ ARMCPU *cpu = ARM_CPU(obj);
97
+enum {
736
+
98
+ AW_H3_SRAM_A1,
737
+ cpu->dtb_compatible = "arm,arm926";
99
+ AW_H3_SRAM_A2,
738
+ set_feature(&cpu->env, ARM_FEATURE_V5);
100
+ AW_H3_SRAM_C,
739
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
101
+ AW_H3_PIT,
740
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
102
+ AW_H3_UART0,
741
+ cpu->midr = 0x41069265;
103
+ AW_H3_UART1,
742
+ cpu->reset_fpsid = 0x41011090;
104
+ AW_H3_UART2,
743
+ cpu->ctr = 0x1dd20d2;
105
+ AW_H3_UART3,
744
+ cpu->reset_sctlr = 0x00090078;
106
+ AW_H3_GIC_DIST,
745
+
107
+ AW_H3_GIC_CPU,
746
+ /*
108
+ AW_H3_GIC_HYP,
747
+ * ARMv5 does not have the ID_ISAR registers, but we can still
109
+ AW_H3_GIC_VCPU,
748
+ * set the field to indicate Jazelle support within QEMU.
110
+ AW_H3_SDRAM
749
+ */
750
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
751
+ /*
752
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
753
+ * support even though ARMv5 doesn't have this register.
754
+ */
755
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
756
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
757
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
758
+}
759
+
760
+static void arm946_initfn(Object *obj)
761
+{
762
+ ARMCPU *cpu = ARM_CPU(obj);
763
+
764
+ cpu->dtb_compatible = "arm,arm946";
765
+ set_feature(&cpu->env, ARM_FEATURE_V5);
766
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
767
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
768
+ cpu->midr = 0x41059461;
769
+ cpu->ctr = 0x0f004006;
770
+ cpu->reset_sctlr = 0x00000078;
771
+}
772
+
773
+static void arm1026_initfn(Object *obj)
774
+{
775
+ ARMCPU *cpu = ARM_CPU(obj);
776
+
777
+ cpu->dtb_compatible = "arm,arm1026";
778
+ set_feature(&cpu->env, ARM_FEATURE_V5);
779
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
780
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
781
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
782
+ cpu->midr = 0x4106a262;
783
+ cpu->reset_fpsid = 0x410110a0;
784
+ cpu->ctr = 0x1dd20d2;
785
+ cpu->reset_sctlr = 0x00090078;
786
+ cpu->reset_auxcr = 1;
787
+
788
+ /*
789
+ * ARMv5 does not have the ID_ISAR registers, but we can still
790
+ * set the field to indicate Jazelle support within QEMU.
791
+ */
792
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
793
+ /*
794
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
795
+ * support even though ARMv5 doesn't have this register.
796
+ */
797
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
798
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
799
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
800
+
801
+ {
802
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
803
+ ARMCPRegInfo ifar = {
804
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
805
+ .access = PL1_RW,
806
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
807
+ .resetvalue = 0
808
+ };
809
+ define_one_arm_cp_reg(cpu, &ifar);
810
+ }
811
+}
812
+
813
+static void arm1136_r2_initfn(Object *obj)
814
+{
815
+ ARMCPU *cpu = ARM_CPU(obj);
816
+ /*
817
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
818
+ * older core than plain "arm1136". In particular this does not
819
+ * have the v6K features.
820
+ * These ID register values are correct for 1136 but may be wrong
821
+ * for 1136_r2 (in particular r0p2 does not actually implement most
822
+ * of the ID registers).
823
+ */
824
+
825
+ cpu->dtb_compatible = "arm,arm1136";
826
+ set_feature(&cpu->env, ARM_FEATURE_V6);
827
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
828
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
829
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
830
+ cpu->midr = 0x4107b362;
831
+ cpu->reset_fpsid = 0x410120b4;
832
+ cpu->isar.mvfr0 = 0x11111111;
833
+ cpu->isar.mvfr1 = 0x00000000;
834
+ cpu->ctr = 0x1dd20d2;
835
+ cpu->reset_sctlr = 0x00050078;
836
+ cpu->id_pfr0 = 0x111;
837
+ cpu->id_pfr1 = 0x1;
838
+ cpu->isar.id_dfr0 = 0x2;
839
+ cpu->id_afr0 = 0x3;
840
+ cpu->isar.id_mmfr0 = 0x01130003;
841
+ cpu->isar.id_mmfr1 = 0x10030302;
842
+ cpu->isar.id_mmfr2 = 0x01222110;
843
+ cpu->isar.id_isar0 = 0x00140011;
844
+ cpu->isar.id_isar1 = 0x12002111;
845
+ cpu->isar.id_isar2 = 0x11231111;
846
+ cpu->isar.id_isar3 = 0x01102131;
847
+ cpu->isar.id_isar4 = 0x141;
848
+ cpu->reset_auxcr = 7;
849
+}
850
+
851
+static void arm1136_initfn(Object *obj)
852
+{
853
+ ARMCPU *cpu = ARM_CPU(obj);
854
+
855
+ cpu->dtb_compatible = "arm,arm1136";
856
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
857
+ set_feature(&cpu->env, ARM_FEATURE_V6);
858
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
859
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
860
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
861
+ cpu->midr = 0x4117b363;
862
+ cpu->reset_fpsid = 0x410120b4;
863
+ cpu->isar.mvfr0 = 0x11111111;
864
+ cpu->isar.mvfr1 = 0x00000000;
865
+ cpu->ctr = 0x1dd20d2;
866
+ cpu->reset_sctlr = 0x00050078;
867
+ cpu->id_pfr0 = 0x111;
868
+ cpu->id_pfr1 = 0x1;
869
+ cpu->isar.id_dfr0 = 0x2;
870
+ cpu->id_afr0 = 0x3;
871
+ cpu->isar.id_mmfr0 = 0x01130003;
872
+ cpu->isar.id_mmfr1 = 0x10030302;
873
+ cpu->isar.id_mmfr2 = 0x01222110;
874
+ cpu->isar.id_isar0 = 0x00140011;
875
+ cpu->isar.id_isar1 = 0x12002111;
876
+ cpu->isar.id_isar2 = 0x11231111;
877
+ cpu->isar.id_isar3 = 0x01102131;
878
+ cpu->isar.id_isar4 = 0x141;
879
+ cpu->reset_auxcr = 7;
880
+}
881
+
882
+static void arm1176_initfn(Object *obj)
883
+{
884
+ ARMCPU *cpu = ARM_CPU(obj);
885
+
886
+ cpu->dtb_compatible = "arm,arm1176";
887
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
888
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
889
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
890
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
891
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
892
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
893
+ cpu->midr = 0x410fb767;
894
+ cpu->reset_fpsid = 0x410120b5;
895
+ cpu->isar.mvfr0 = 0x11111111;
896
+ cpu->isar.mvfr1 = 0x00000000;
897
+ cpu->ctr = 0x1dd20d2;
898
+ cpu->reset_sctlr = 0x00050078;
899
+ cpu->id_pfr0 = 0x111;
900
+ cpu->id_pfr1 = 0x11;
901
+ cpu->isar.id_dfr0 = 0x33;
902
+ cpu->id_afr0 = 0;
903
+ cpu->isar.id_mmfr0 = 0x01130003;
904
+ cpu->isar.id_mmfr1 = 0x10030302;
905
+ cpu->isar.id_mmfr2 = 0x01222100;
906
+ cpu->isar.id_isar0 = 0x0140011;
907
+ cpu->isar.id_isar1 = 0x12002111;
908
+ cpu->isar.id_isar2 = 0x11231121;
909
+ cpu->isar.id_isar3 = 0x01102131;
910
+ cpu->isar.id_isar4 = 0x01141;
911
+ cpu->reset_auxcr = 7;
912
+}
913
+
914
+static void arm11mpcore_initfn(Object *obj)
915
+{
916
+ ARMCPU *cpu = ARM_CPU(obj);
917
+
918
+ cpu->dtb_compatible = "arm,arm11mpcore";
919
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
920
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
921
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
922
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
923
+ cpu->midr = 0x410fb022;
924
+ cpu->reset_fpsid = 0x410120b4;
925
+ cpu->isar.mvfr0 = 0x11111111;
926
+ cpu->isar.mvfr1 = 0x00000000;
927
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
928
+ cpu->id_pfr0 = 0x111;
929
+ cpu->id_pfr1 = 0x1;
930
+ cpu->isar.id_dfr0 = 0;
931
+ cpu->id_afr0 = 0x2;
932
+ cpu->isar.id_mmfr0 = 0x01100103;
933
+ cpu->isar.id_mmfr1 = 0x10020302;
934
+ cpu->isar.id_mmfr2 = 0x01222000;
935
+ cpu->isar.id_isar0 = 0x00100011;
936
+ cpu->isar.id_isar1 = 0x12002111;
937
+ cpu->isar.id_isar2 = 0x11221011;
938
+ cpu->isar.id_isar3 = 0x01102131;
939
+ cpu->isar.id_isar4 = 0x141;
940
+ cpu->reset_auxcr = 1;
941
+}
942
+
943
+static void cortex_m0_initfn(Object *obj)
944
+{
945
+ ARMCPU *cpu = ARM_CPU(obj);
946
+ set_feature(&cpu->env, ARM_FEATURE_V6);
947
+ set_feature(&cpu->env, ARM_FEATURE_M);
948
+
949
+ cpu->midr = 0x410cc200;
950
+}
951
+
952
+static void cortex_m3_initfn(Object *obj)
953
+{
954
+ ARMCPU *cpu = ARM_CPU(obj);
955
+ set_feature(&cpu->env, ARM_FEATURE_V7);
956
+ set_feature(&cpu->env, ARM_FEATURE_M);
957
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
958
+ cpu->midr = 0x410fc231;
959
+ cpu->pmsav7_dregion = 8;
960
+ cpu->id_pfr0 = 0x00000030;
961
+ cpu->id_pfr1 = 0x00000200;
962
+ cpu->isar.id_dfr0 = 0x00100000;
963
+ cpu->id_afr0 = 0x00000000;
964
+ cpu->isar.id_mmfr0 = 0x00000030;
965
+ cpu->isar.id_mmfr1 = 0x00000000;
966
+ cpu->isar.id_mmfr2 = 0x00000000;
967
+ cpu->isar.id_mmfr3 = 0x00000000;
968
+ cpu->isar.id_isar0 = 0x01141110;
969
+ cpu->isar.id_isar1 = 0x02111000;
970
+ cpu->isar.id_isar2 = 0x21112231;
971
+ cpu->isar.id_isar3 = 0x01111110;
972
+ cpu->isar.id_isar4 = 0x01310102;
973
+ cpu->isar.id_isar5 = 0x00000000;
974
+ cpu->isar.id_isar6 = 0x00000000;
975
+}
976
+
977
+static void cortex_m4_initfn(Object *obj)
978
+{
979
+ ARMCPU *cpu = ARM_CPU(obj);
980
+
981
+ set_feature(&cpu->env, ARM_FEATURE_V7);
982
+ set_feature(&cpu->env, ARM_FEATURE_M);
983
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
984
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
985
+ cpu->midr = 0x410fc240; /* r0p0 */
986
+ cpu->pmsav7_dregion = 8;
987
+ cpu->isar.mvfr0 = 0x10110021;
988
+ cpu->isar.mvfr1 = 0x11000011;
989
+ cpu->isar.mvfr2 = 0x00000000;
990
+ cpu->id_pfr0 = 0x00000030;
991
+ cpu->id_pfr1 = 0x00000200;
992
+ cpu->isar.id_dfr0 = 0x00100000;
993
+ cpu->id_afr0 = 0x00000000;
994
+ cpu->isar.id_mmfr0 = 0x00000030;
995
+ cpu->isar.id_mmfr1 = 0x00000000;
996
+ cpu->isar.id_mmfr2 = 0x00000000;
997
+ cpu->isar.id_mmfr3 = 0x00000000;
998
+ cpu->isar.id_isar0 = 0x01141110;
999
+ cpu->isar.id_isar1 = 0x02111000;
1000
+ cpu->isar.id_isar2 = 0x21112231;
1001
+ cpu->isar.id_isar3 = 0x01111110;
1002
+ cpu->isar.id_isar4 = 0x01310102;
1003
+ cpu->isar.id_isar5 = 0x00000000;
1004
+ cpu->isar.id_isar6 = 0x00000000;
1005
+}
1006
+
1007
+static void cortex_m7_initfn(Object *obj)
1008
+{
1009
+ ARMCPU *cpu = ARM_CPU(obj);
1010
+
1011
+ set_feature(&cpu->env, ARM_FEATURE_V7);
1012
+ set_feature(&cpu->env, ARM_FEATURE_M);
1013
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1014
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1015
+ cpu->midr = 0x411fc272; /* r1p2 */
1016
+ cpu->pmsav7_dregion = 8;
1017
+ cpu->isar.mvfr0 = 0x10110221;
1018
+ cpu->isar.mvfr1 = 0x12000011;
1019
+ cpu->isar.mvfr2 = 0x00000040;
1020
+ cpu->id_pfr0 = 0x00000030;
1021
+ cpu->id_pfr1 = 0x00000200;
1022
+ cpu->isar.id_dfr0 = 0x00100000;
1023
+ cpu->id_afr0 = 0x00000000;
1024
+ cpu->isar.id_mmfr0 = 0x00100030;
1025
+ cpu->isar.id_mmfr1 = 0x00000000;
1026
+ cpu->isar.id_mmfr2 = 0x01000000;
1027
+ cpu->isar.id_mmfr3 = 0x00000000;
1028
+ cpu->isar.id_isar0 = 0x01101110;
1029
+ cpu->isar.id_isar1 = 0x02112000;
1030
+ cpu->isar.id_isar2 = 0x20232231;
1031
+ cpu->isar.id_isar3 = 0x01111131;
1032
+ cpu->isar.id_isar4 = 0x01310132;
1033
+ cpu->isar.id_isar5 = 0x00000000;
1034
+ cpu->isar.id_isar6 = 0x00000000;
1035
+}
1036
+
1037
+static void cortex_m33_initfn(Object *obj)
1038
+{
1039
+ ARMCPU *cpu = ARM_CPU(obj);
1040
+
1041
+ set_feature(&cpu->env, ARM_FEATURE_V8);
1042
+ set_feature(&cpu->env, ARM_FEATURE_M);
1043
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1044
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1045
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1046
+ cpu->midr = 0x410fd213; /* r0p3 */
1047
+ cpu->pmsav7_dregion = 16;
1048
+ cpu->sau_sregion = 8;
1049
+ cpu->isar.mvfr0 = 0x10110021;
1050
+ cpu->isar.mvfr1 = 0x11000011;
1051
+ cpu->isar.mvfr2 = 0x00000040;
1052
+ cpu->id_pfr0 = 0x00000030;
1053
+ cpu->id_pfr1 = 0x00000210;
1054
+ cpu->isar.id_dfr0 = 0x00200000;
1055
+ cpu->id_afr0 = 0x00000000;
1056
+ cpu->isar.id_mmfr0 = 0x00101F40;
1057
+ cpu->isar.id_mmfr1 = 0x00000000;
1058
+ cpu->isar.id_mmfr2 = 0x01000000;
1059
+ cpu->isar.id_mmfr3 = 0x00000000;
1060
+ cpu->isar.id_isar0 = 0x01101110;
1061
+ cpu->isar.id_isar1 = 0x02212000;
1062
+ cpu->isar.id_isar2 = 0x20232232;
1063
+ cpu->isar.id_isar3 = 0x01111131;
1064
+ cpu->isar.id_isar4 = 0x01310132;
1065
+ cpu->isar.id_isar5 = 0x00000000;
1066
+ cpu->isar.id_isar6 = 0x00000000;
1067
+ cpu->clidr = 0x00000000;
1068
+ cpu->ctr = 0x8000c000;
1069
+}
1070
+
1071
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1072
+ /* Dummy the TCM region regs for the moment */
1073
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1074
+ .access = PL1_RW, .type = ARM_CP_CONST },
1075
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1076
+ .access = PL1_RW, .type = ARM_CP_CONST },
1077
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1078
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1079
+ REGINFO_SENTINEL
111
+};
1080
+};
112
+
1081
+
113
+/** Total number of CPU cores in the H3 SoC */
1082
+static void cortex_r5_initfn(Object *obj)
114
+#define AW_H3_NUM_CPUS (4)
1083
+{
115
+
1084
+ ARMCPU *cpu = ARM_CPU(obj);
116
+/**
1085
+
117
+ * Allwinner H3 object model
1086
+ set_feature(&cpu->env, ARM_FEATURE_V7);
118
+ * @{
1087
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
119
+ */
1088
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
120
+
1089
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
121
+/** Object type for the Allwinner H3 SoC */
1090
+ cpu->midr = 0x411fc153; /* r1p3 */
122
+#define TYPE_AW_H3 "allwinner-h3"
1091
+ cpu->id_pfr0 = 0x0131;
123
+
1092
+ cpu->id_pfr1 = 0x001;
124
+/** Convert input object to Allwinner H3 state object */
1093
+ cpu->isar.id_dfr0 = 0x010400;
125
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
1094
+ cpu->id_afr0 = 0x0;
126
+
1095
+ cpu->isar.id_mmfr0 = 0x0210030;
127
+/** @} */
1096
+ cpu->isar.id_mmfr1 = 0x00000000;
128
+
1097
+ cpu->isar.id_mmfr2 = 0x01200000;
129
+/**
1098
+ cpu->isar.id_mmfr3 = 0x0211;
130
+ * Allwinner H3 object
1099
+ cpu->isar.id_isar0 = 0x02101111;
131
+ *
1100
+ cpu->isar.id_isar1 = 0x13112111;
132
+ * This struct contains the state of all the devices
1101
+ cpu->isar.id_isar2 = 0x21232141;
133
+ * which are currently emulated by the H3 SoC code.
1102
+ cpu->isar.id_isar3 = 0x01112131;
134
+ */
1103
+ cpu->isar.id_isar4 = 0x0010142;
135
+typedef struct AwH3State {
1104
+ cpu->isar.id_isar5 = 0x0;
136
+ /*< private >*/
1105
+ cpu->isar.id_isar6 = 0x0;
137
+ DeviceState parent_obj;
1106
+ cpu->mp_is_up = true;
138
+ /*< public >*/
1107
+ cpu->pmsav7_dregion = 16;
139
+
1108
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
140
+ ARMCPU cpus[AW_H3_NUM_CPUS];
1109
+}
141
+ const hwaddr *memmap;
1110
+
142
+ AwA10PITState timer;
1111
+static void cortex_r5f_initfn(Object *obj)
143
+ GICState gic;
1112
+{
144
+ MemoryRegion sram_a1;
1113
+ ARMCPU *cpu = ARM_CPU(obj);
145
+ MemoryRegion sram_a2;
1114
+
146
+ MemoryRegion sram_c;
1115
+ cortex_r5_initfn(obj);
147
+} AwH3State;
1116
+ cpu->isar.mvfr0 = 0x10110221;
148
+
1117
+ cpu->isar.mvfr1 = 0x00000011;
149
+#endif /* HW_ARM_ALLWINNER_H3_H */
1118
+}
150
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
1119
+
151
new file mode 100644
1120
+static void ti925t_initfn(Object *obj)
152
index XXXXXXX..XXXXXXX
1121
+{
153
--- /dev/null
1122
+ ARMCPU *cpu = ARM_CPU(obj);
154
+++ b/hw/arm/allwinner-h3.c
1123
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
155
@@ -XXX,XX +XXX,XX @@
1124
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
156
+/*
1125
+ cpu->midr = ARM_CPUID_TI925T;
157
+ * Allwinner H3 System on Chip emulation
1126
+ cpu->ctr = 0x5109149;
158
+ *
1127
+ cpu->reset_sctlr = 0x00000070;
159
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
1128
+}
160
+ *
1129
+
161
+ * This program is free software: you can redistribute it and/or modify
1130
+static void sa1100_initfn(Object *obj)
162
+ * it under the terms of the GNU General Public License as published by
1131
+{
163
+ * the Free Software Foundation, either version 2 of the License, or
1132
+ ARMCPU *cpu = ARM_CPU(obj);
164
+ * (at your option) any later version.
1133
+
165
+ *
1134
+ cpu->dtb_compatible = "intel,sa1100";
166
+ * This program is distributed in the hope that it will be useful,
1135
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
167
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1136
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
168
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1137
+ cpu->midr = 0x4401A11B;
169
+ * GNU General Public License for more details.
1138
+ cpu->reset_sctlr = 0x00000070;
170
+ *
1139
+}
171
+ * You should have received a copy of the GNU General Public License
1140
+
172
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
1141
+static void sa1110_initfn(Object *obj)
173
+ */
1142
+{
174
+
1143
+ ARMCPU *cpu = ARM_CPU(obj);
175
+#include "qemu/osdep.h"
1144
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
176
+#include "exec/address-spaces.h"
1145
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
177
+#include "qapi/error.h"
1146
+ cpu->midr = 0x6901B119;
178
+#include "qemu/error-report.h"
1147
+ cpu->reset_sctlr = 0x00000070;
179
+#include "qemu/module.h"
1148
+}
180
+#include "qemu/units.h"
1149
+
181
+#include "hw/qdev-core.h"
1150
+static void pxa250_initfn(Object *obj)
182
+#include "cpu.h"
1151
+{
183
+#include "hw/sysbus.h"
1152
+ ARMCPU *cpu = ARM_CPU(obj);
184
+#include "hw/char/serial.h"
1153
+
185
+#include "hw/misc/unimp.h"
1154
+ cpu->dtb_compatible = "marvell,xscale";
186
+#include "sysemu/sysemu.h"
1155
+ set_feature(&cpu->env, ARM_FEATURE_V5);
187
+#include "hw/arm/allwinner-h3.h"
1156
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
188
+
1157
+ cpu->midr = 0x69052100;
189
+/* Memory map */
1158
+ cpu->ctr = 0xd172172;
190
+const hwaddr allwinner_h3_memmap[] = {
1159
+ cpu->reset_sctlr = 0x00000078;
191
+ [AW_H3_SRAM_A1] = 0x00000000,
1160
+}
192
+ [AW_H3_SRAM_A2] = 0x00044000,
1161
+
193
+ [AW_H3_SRAM_C] = 0x00010000,
1162
+static void pxa255_initfn(Object *obj)
194
+ [AW_H3_PIT] = 0x01c20c00,
1163
+{
195
+ [AW_H3_UART0] = 0x01c28000,
1164
+ ARMCPU *cpu = ARM_CPU(obj);
196
+ [AW_H3_UART1] = 0x01c28400,
1165
+
197
+ [AW_H3_UART2] = 0x01c28800,
1166
+ cpu->dtb_compatible = "marvell,xscale";
198
+ [AW_H3_UART3] = 0x01c28c00,
1167
+ set_feature(&cpu->env, ARM_FEATURE_V5);
199
+ [AW_H3_GIC_DIST] = 0x01c81000,
1168
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
200
+ [AW_H3_GIC_CPU] = 0x01c82000,
1169
+ cpu->midr = 0x69052d00;
201
+ [AW_H3_GIC_HYP] = 0x01c84000,
1170
+ cpu->ctr = 0xd172172;
202
+ [AW_H3_GIC_VCPU] = 0x01c86000,
1171
+ cpu->reset_sctlr = 0x00000078;
203
+ [AW_H3_SDRAM] = 0x40000000
1172
+}
1173
+
1174
+static void pxa260_initfn(Object *obj)
1175
+{
1176
+ ARMCPU *cpu = ARM_CPU(obj);
1177
+
1178
+ cpu->dtb_compatible = "marvell,xscale";
1179
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1180
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1181
+ cpu->midr = 0x69052903;
1182
+ cpu->ctr = 0xd172172;
1183
+ cpu->reset_sctlr = 0x00000078;
1184
+}
1185
+
1186
+static void pxa261_initfn(Object *obj)
1187
+{
1188
+ ARMCPU *cpu = ARM_CPU(obj);
1189
+
1190
+ cpu->dtb_compatible = "marvell,xscale";
1191
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1192
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1193
+ cpu->midr = 0x69052d05;
1194
+ cpu->ctr = 0xd172172;
1195
+ cpu->reset_sctlr = 0x00000078;
1196
+}
1197
+
1198
+static void pxa262_initfn(Object *obj)
1199
+{
1200
+ ARMCPU *cpu = ARM_CPU(obj);
1201
+
1202
+ cpu->dtb_compatible = "marvell,xscale";
1203
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1204
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1205
+ cpu->midr = 0x69052d06;
1206
+ cpu->ctr = 0xd172172;
1207
+ cpu->reset_sctlr = 0x00000078;
1208
+}
1209
+
1210
+static void pxa270a0_initfn(Object *obj)
1211
+{
1212
+ ARMCPU *cpu = ARM_CPU(obj);
1213
+
1214
+ cpu->dtb_compatible = "marvell,xscale";
1215
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1216
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1217
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1218
+ cpu->midr = 0x69054110;
1219
+ cpu->ctr = 0xd172172;
1220
+ cpu->reset_sctlr = 0x00000078;
1221
+}
1222
+
1223
+static void pxa270a1_initfn(Object *obj)
1224
+{
1225
+ ARMCPU *cpu = ARM_CPU(obj);
1226
+
1227
+ cpu->dtb_compatible = "marvell,xscale";
1228
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1229
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1230
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1231
+ cpu->midr = 0x69054111;
1232
+ cpu->ctr = 0xd172172;
1233
+ cpu->reset_sctlr = 0x00000078;
1234
+}
1235
+
1236
+static void pxa270b0_initfn(Object *obj)
1237
+{
1238
+ ARMCPU *cpu = ARM_CPU(obj);
1239
+
1240
+ cpu->dtb_compatible = "marvell,xscale";
1241
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1242
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1243
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1244
+ cpu->midr = 0x69054112;
1245
+ cpu->ctr = 0xd172172;
1246
+ cpu->reset_sctlr = 0x00000078;
1247
+}
1248
+
1249
+static void pxa270b1_initfn(Object *obj)
1250
+{
1251
+ ARMCPU *cpu = ARM_CPU(obj);
1252
+
1253
+ cpu->dtb_compatible = "marvell,xscale";
1254
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1255
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1256
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1257
+ cpu->midr = 0x69054113;
1258
+ cpu->ctr = 0xd172172;
1259
+ cpu->reset_sctlr = 0x00000078;
1260
+}
1261
+
1262
+static void pxa270c0_initfn(Object *obj)
1263
+{
1264
+ ARMCPU *cpu = ARM_CPU(obj);
1265
+
1266
+ cpu->dtb_compatible = "marvell,xscale";
1267
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1268
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1269
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1270
+ cpu->midr = 0x69054114;
1271
+ cpu->ctr = 0xd172172;
1272
+ cpu->reset_sctlr = 0x00000078;
1273
+}
1274
+
1275
+static void pxa270c5_initfn(Object *obj)
1276
+{
1277
+ ARMCPU *cpu = ARM_CPU(obj);
1278
+
1279
+ cpu->dtb_compatible = "marvell,xscale";
1280
+ set_feature(&cpu->env, ARM_FEATURE_V5);
1281
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1282
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1283
+ cpu->midr = 0x69054117;
1284
+ cpu->ctr = 0xd172172;
1285
+ cpu->reset_sctlr = 0x00000078;
1286
+}
1287
+
1288
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
1289
+{
1290
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1291
+ CPUClass *cc = CPU_CLASS(oc);
1292
+
1293
+ acc->info = data;
1294
+#ifndef CONFIG_USER_ONLY
1295
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1296
+#endif
1297
+
1298
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1299
+}
1300
+
1301
+static const ARMCPUInfo arm_tcg_cpus[] = {
1302
+ { .name = "arm926", .initfn = arm926_initfn },
1303
+ { .name = "arm946", .initfn = arm946_initfn },
1304
+ { .name = "arm1026", .initfn = arm1026_initfn },
1305
+ /*
1306
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1307
+ * older core than plain "arm1136". In particular this does not
1308
+ * have the v6K features.
1309
+ */
1310
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1311
+ { .name = "arm1136", .initfn = arm1136_initfn },
1312
+ { .name = "arm1176", .initfn = arm1176_initfn },
1313
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1314
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1315
+ .class_init = arm_v7m_class_init },
1316
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1317
+ .class_init = arm_v7m_class_init },
1318
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1319
+ .class_init = arm_v7m_class_init },
1320
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1321
+ .class_init = arm_v7m_class_init },
1322
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1323
+ .class_init = arm_v7m_class_init },
1324
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1325
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1326
+ { .name = "ti925t", .initfn = ti925t_initfn },
1327
+ { .name = "sa1100", .initfn = sa1100_initfn },
1328
+ { .name = "sa1110", .initfn = sa1110_initfn },
1329
+ { .name = "pxa250", .initfn = pxa250_initfn },
1330
+ { .name = "pxa255", .initfn = pxa255_initfn },
1331
+ { .name = "pxa260", .initfn = pxa260_initfn },
1332
+ { .name = "pxa261", .initfn = pxa261_initfn },
1333
+ { .name = "pxa262", .initfn = pxa262_initfn },
1334
+ /* "pxa270" is an alias for "pxa270-a0" */
1335
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
1336
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1337
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1338
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1339
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1340
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1341
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
204
+};
1342
+};
205
+
1343
+
206
+/* List of unimplemented devices */
1344
+static void arm_tcg_cpu_register_types(void)
207
+struct AwH3Unimplemented {
1345
+{
208
+ const char *device_name;
1346
+ size_t i;
209
+ hwaddr base;
1347
+
210
+ hwaddr size;
1348
+ for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
211
+} unimplemented[] = {
1349
+ arm_cpu_register(&arm_tcg_cpus[i]);
212
+ { "d-engine", 0x01000000, 4 * MiB },
213
+ { "d-inter", 0x01400000, 128 * KiB },
214
+ { "syscon", 0x01c00000, 4 * KiB },
215
+ { "dma", 0x01c02000, 4 * KiB },
216
+ { "nfdc", 0x01c03000, 4 * KiB },
217
+ { "ts", 0x01c06000, 4 * KiB },
218
+ { "keymem", 0x01c0b000, 4 * KiB },
219
+ { "lcd0", 0x01c0c000, 4 * KiB },
220
+ { "lcd1", 0x01c0d000, 4 * KiB },
221
+ { "ve", 0x01c0e000, 4 * KiB },
222
+ { "mmc0", 0x01c0f000, 4 * KiB },
223
+ { "mmc1", 0x01c10000, 4 * KiB },
224
+ { "mmc2", 0x01c11000, 4 * KiB },
225
+ { "sid", 0x01c14000, 1 * KiB },
226
+ { "crypto", 0x01c15000, 4 * KiB },
227
+ { "msgbox", 0x01c17000, 4 * KiB },
228
+ { "spinlock", 0x01c18000, 4 * KiB },
229
+ { "usb0-otg", 0x01c19000, 4 * KiB },
230
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
231
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
232
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
233
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
234
+ { "smc", 0x01c1e000, 4 * KiB },
235
+ { "ccu", 0x01c20000, 1 * KiB },
236
+ { "pio", 0x01c20800, 1 * KiB },
237
+ { "owa", 0x01c21000, 1 * KiB },
238
+ { "pwm", 0x01c21400, 1 * KiB },
239
+ { "keyadc", 0x01c21800, 1 * KiB },
240
+ { "pcm0", 0x01c22000, 1 * KiB },
241
+ { "pcm1", 0x01c22400, 1 * KiB },
242
+ { "pcm2", 0x01c22800, 1 * KiB },
243
+ { "audio", 0x01c22c00, 2 * KiB },
244
+ { "smta", 0x01c23400, 1 * KiB },
245
+ { "ths", 0x01c25000, 1 * KiB },
246
+ { "uart0", 0x01c28000, 1 * KiB },
247
+ { "uart1", 0x01c28400, 1 * KiB },
248
+ { "uart2", 0x01c28800, 1 * KiB },
249
+ { "uart3", 0x01c28c00, 1 * KiB },
250
+ { "twi0", 0x01c2ac00, 1 * KiB },
251
+ { "twi1", 0x01c2b000, 1 * KiB },
252
+ { "twi2", 0x01c2b400, 1 * KiB },
253
+ { "scr", 0x01c2c400, 1 * KiB },
254
+ { "emac", 0x01c30000, 64 * KiB },
255
+ { "gpu", 0x01c40000, 64 * KiB },
256
+ { "hstmr", 0x01c60000, 4 * KiB },
257
+ { "dramcom", 0x01c62000, 4 * KiB },
258
+ { "dramctl0", 0x01c63000, 4 * KiB },
259
+ { "dramphy0", 0x01c65000, 4 * KiB },
260
+ { "spi0", 0x01c68000, 4 * KiB },
261
+ { "spi1", 0x01c69000, 4 * KiB },
262
+ { "csi", 0x01cb0000, 320 * KiB },
263
+ { "tve", 0x01e00000, 64 * KiB },
264
+ { "hdmi", 0x01ee0000, 128 * KiB },
265
+ { "rtc", 0x01f00000, 1 * KiB },
266
+ { "r_timer", 0x01f00800, 1 * KiB },
267
+ { "r_intc", 0x01f00c00, 1 * KiB },
268
+ { "r_wdog", 0x01f01000, 1 * KiB },
269
+ { "r_prcm", 0x01f01400, 1 * KiB },
270
+ { "r_twd", 0x01f01800, 1 * KiB },
271
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
272
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
273
+ { "r_twi", 0x01f02400, 1 * KiB },
274
+ { "r_uart", 0x01f02800, 1 * KiB },
275
+ { "r_pio", 0x01f02c00, 1 * KiB },
276
+ { "r_pwm", 0x01f03800, 1 * KiB },
277
+ { "core-dbg", 0x3f500000, 128 * KiB },
278
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
279
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
280
+ { "ddr-mem", 0x40000000, 2 * GiB },
281
+ { "n-brom", 0xffff0000, 32 * KiB },
282
+ { "s-brom", 0xffff0000, 64 * KiB }
283
+};
284
+
285
+/* Per Processor Interrupts */
286
+enum {
287
+ AW_H3_GIC_PPI_MAINT = 9,
288
+ AW_H3_GIC_PPI_HYPTIMER = 10,
289
+ AW_H3_GIC_PPI_VIRTTIMER = 11,
290
+ AW_H3_GIC_PPI_SECTIMER = 13,
291
+ AW_H3_GIC_PPI_PHYSTIMER = 14
292
+};
293
+
294
+/* Shared Processor Interrupts */
295
+enum {
296
+ AW_H3_GIC_SPI_UART0 = 0,
297
+ AW_H3_GIC_SPI_UART1 = 1,
298
+ AW_H3_GIC_SPI_UART2 = 2,
299
+ AW_H3_GIC_SPI_UART3 = 3,
300
+ AW_H3_GIC_SPI_TIMER0 = 18,
301
+ AW_H3_GIC_SPI_TIMER1 = 19,
302
+};
303
+
304
+/* Allwinner H3 general constants */
305
+enum {
306
+ AW_H3_GIC_NUM_SPI = 128
307
+};
308
+
309
+static void allwinner_h3_init(Object *obj)
310
+{
311
+ AwH3State *s = AW_H3(obj);
312
+
313
+ s->memmap = allwinner_h3_memmap;
314
+
315
+ for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
316
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
317
+ ARM_CPU_TYPE_NAME("cortex-a7"),
318
+ &error_abort, NULL);
319
+ }
1350
+ }
320
+
1351
+}
321
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
1352
+
322
+ TYPE_ARM_GIC);
1353
+type_init(arm_tcg_cpu_register_types)
323
+
1354
+
324
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
1355
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
325
+ TYPE_AW_A10_PIT);
1356
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
326
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
327
+ "clk0-freq", &error_abort);
328
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
329
+ "clk1-freq", &error_abort);
330
+}
331
+
332
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
333
+{
334
+ AwH3State *s = AW_H3(dev);
335
+ unsigned i;
336
+
337
+ /* CPUs */
338
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
339
+
340
+ /* Provide Power State Coordination Interface */
341
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
342
+ QEMU_PSCI_CONDUIT_HVC);
343
+
344
+ /* Disable secondary CPUs */
345
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
346
+ i > 0);
347
+
348
+ /* All exception levels required */
349
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
350
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
351
+
352
+ /* Mark realized */
353
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
354
+ }
355
+
356
+ /* Generic Interrupt Controller */
357
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
358
+ GIC_INTERNAL);
359
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
360
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
361
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
362
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
363
+ qdev_init_nofail(DEVICE(&s->gic));
364
+
365
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
366
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
367
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
368
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
369
+
370
+ /*
371
+ * Wire the outputs from each CPU's generic timer and the GICv3
372
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
373
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
374
+ */
375
+ for (i = 0; i < AW_H3_NUM_CPUS; i++) {
376
+ DeviceState *cpudev = DEVICE(&s->cpus[i]);
377
+ int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
378
+ int irq;
379
+ /*
380
+ * Mapping from the output timer irq lines from the CPU to the
381
+ * GIC PPI inputs used for this board.
382
+ */
383
+ const int timer_irq[] = {
384
+ [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
385
+ [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
386
+ [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
387
+ [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
388
+ };
389
+
390
+ /* Connect CPU timer outputs to GIC PPI inputs */
391
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
392
+ qdev_connect_gpio_out(cpudev, irq,
393
+ qdev_get_gpio_in(DEVICE(&s->gic),
394
+ ppibase + timer_irq[irq]));
395
+ }
396
+
397
+ /* Connect GIC outputs to CPU interrupt inputs */
398
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
399
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
400
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
401
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
402
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
403
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
404
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
405
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
406
+
407
+ /* GIC maintenance signal */
408
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
409
+ qdev_get_gpio_in(DEVICE(&s->gic),
410
+ ppibase + AW_H3_GIC_PPI_MAINT));
411
+ }
412
+
413
+ /* Timer */
414
+ qdev_init_nofail(DEVICE(&s->timer));
415
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
416
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
417
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
418
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
419
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
420
+
421
+ /* SRAM */
422
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
423
+ 64 * KiB, &error_abort);
424
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
425
+ 32 * KiB, &error_abort);
426
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
427
+ 44 * KiB, &error_abort);
428
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
429
+ &s->sram_a1);
430
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
431
+ &s->sram_a2);
432
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
433
+ &s->sram_c);
434
+
435
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
436
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
437
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
438
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
439
+ /* UART1 */
440
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
441
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
442
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
443
+ /* UART2 */
444
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
445
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
446
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
447
+ /* UART3 */
448
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
449
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
450
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
451
+
452
+ /* Unimplemented devices */
453
+ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
454
+ create_unimplemented_device(unimplemented[i].device_name,
455
+ unimplemented[i].base,
456
+ unimplemented[i].size);
457
+ }
458
+}
459
+
460
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
461
+{
462
+ DeviceClass *dc = DEVICE_CLASS(oc);
463
+
464
+ dc->realize = allwinner_h3_realize;
465
+ /* Reason: uses serial_hd() in realize function */
466
+ dc->user_creatable = false;
467
+}
468
+
469
+static const TypeInfo allwinner_h3_type_info = {
470
+ .name = TYPE_AW_H3,
471
+ .parent = TYPE_DEVICE,
472
+ .instance_size = sizeof(AwH3State),
473
+ .instance_init = allwinner_h3_init,
474
+ .class_init = allwinner_h3_class_init,
475
+};
476
+
477
+static void allwinner_h3_register_types(void)
478
+{
479
+ type_register_static(&allwinner_h3_type_info);
480
+}
481
+
482
+type_init(allwinner_h3_register_types)
483
diff --git a/MAINTAINERS b/MAINTAINERS
484
index XXXXXXX..XXXXXXX 100644
1357
index XXXXXXX..XXXXXXX 100644
485
--- a/MAINTAINERS
1358
--- a/target/arm/Makefile.objs
486
+++ b/MAINTAINERS
1359
+++ b/target/arm/Makefile.objs
487
@@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner*
1360
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o
488
F: include/hw/*/allwinner*
1361
obj-y += crypto_helper.o
489
F: hw/arm/cubieboard.c
1362
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
490
1363
obj-y += m_helper.o
491
+Allwinner-h3
1364
+obj-y += cpu_tcg.o
492
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
1365
493
+L: qemu-arm@nongnu.org
1366
obj-$(CONFIG_SOFTMMU) += psci.o
494
+S: Maintained
1367
495
+F: hw/*/allwinner-h3*
496
+F: include/hw/*/allwinner-h3*
497
+
498
ARM PrimeCell and CMSDK devices
499
M: Peter Maydell <peter.maydell@linaro.org>
500
L: qemu-arm@nongnu.org
501
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
502
index XXXXXXX..XXXXXXX 100644
503
--- a/default-configs/arm-softmmu.mak
504
+++ b/default-configs/arm-softmmu.mak
505
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y
506
CONFIG_FSL_IMX7=y
507
CONFIG_FSL_IMX6UL=y
508
CONFIG_SEMIHOSTING=y
509
+CONFIG_ALLWINNER_H3=y
510
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
511
index XXXXXXX..XXXXXXX 100644
512
--- a/hw/arm/Kconfig
513
+++ b/hw/arm/Kconfig
514
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
515
select SERIAL
516
select UNIMP
517
518
+config ALLWINNER_H3
519
+ bool
520
+ select ALLWINNER_A10_PIT
521
+ select SERIAL
522
+ select ARM_TIMER
523
+ select ARM_GIC
524
+ select UNIMP
525
+
526
config RASPI
527
bool
528
select FRAMEBUFFER
529
--
1368
--
530
2.20.1
1369
2.20.1
531
1370
532
1371
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a OrangePi PC board and verify
3
I can't find proper documentation or datasheet, but it is likely
4
the serial output is working.
4
a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff
5
5
range belongs to the SoC address space, thus is always mapped in
6
The kernel image and DeviceTree blob are built by the Armbian
6
the memory bus.
7
project (based on Debian):
7
Map the devices on the bus regardless a chardev is attached to it.
8
https://www.armbian.com/orange-pi-pc/
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ make check-venv
16
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
17
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
18
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
19
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
20
console: Uncompressing Linux... done, booting the kernel.
21
console: Booting Linux on physical CPU 0x0
22
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
23
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
24
console: CPU: div instructions available: patching division code
25
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
26
console: OF: fdt: Machine model: Xunlong Orange Pi PC
27
console: Memory policy: Data cache writealloc
28
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
29
console: cma: Failed to reserve 128 MiB
30
console: psci: probing for conduit method from DT.
31
console: psci: PSCIv0.2 detected in firmware.
32
console: psci: Using standard PSCI v0.2 function IDs
33
console: psci: Trusted OS migration not required
34
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
35
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
36
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
37
console: Kernel command line: printk.time=0 console=ttyS0,115200
38
PASS (8.59 s)
39
JOB TIME : 8.81 s
40
8
41
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
42
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Reviewed-by: Jan Kiszka <jan.kiszka@web.de>
43
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20200505095945.23146-1-f4bug@amsat.org
44
Tested-by: Alex Bennée <alex.bennee@linaro.org>
45
Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com
46
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
13
---
49
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
14
hw/arm/musicpal.c | 12 ++++--------
50
1 file changed, 25 insertions(+)
15
1 file changed, 4 insertions(+), 8 deletions(-)
51
16
52
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
53
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
54
--- a/tests/acceptance/boot_linux_console.py
19
--- a/hw/arm/musicpal.c
55
+++ b/tests/acceptance/boot_linux_console.py
20
+++ b/hw/arm/musicpal.c
56
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
21
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
57
exec_command_and_wait_for_pattern(self, 'reboot',
22
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
58
'reboot: Restarting system')
23
pic[MP_TIMER4_IRQ], NULL);
59
24
60
+ def test_arm_orangepi(self):
25
- if (serial_hd(0)) {
61
+ """
26
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
62
+ :avocado: tags=arch:arm
27
- 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
63
+ :avocado: tags=machine:orangepi-pc
28
- }
64
+ """
29
- if (serial_hd(1)) {
65
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
30
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
66
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
31
- 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
67
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
32
- }
68
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
33
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
69
+ kernel_path = self.extract_from_deb(deb_path,
34
+ 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
70
+ '/boot/vmlinuz-4.20.7-sunxi')
35
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
71
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb'
36
+ 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
72
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
37
73
+
38
/* Register flash */
74
+ self.vm.set_console()
39
dinfo = drive_get(IF_PFLASH, 0, 0);
75
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
76
+ 'console=ttyS0,115200n8 '
77
+ 'earlycon=uart,mmio32,0x1c28000')
78
+ self.vm.add_args('-kernel', kernel_path,
79
+ '-dtb', dtb_path,
80
+ '-append', kernel_command_line)
81
+ self.vm.launch()
82
+ console_pattern = 'Kernel command line: %s' % kernel_command_line
83
+ self.wait_for_console_pattern(console_pattern)
84
+
85
def test_s390x_s390_ccw_virtio(self):
86
"""
87
:avocado: tags=arch:s390x
88
--
40
--
89
2.20.1
41
2.20.1
90
42
91
43
diff view generated by jsdifflib
1
A write to the CONTROL register can change our current EL (by
1
From: Richard Henderson <richard.henderson@linaro.org>
2
writing to the nPRIV bit). That means that we can't assume
3
that s->current_el is still valid in trans_MSR_v7m() when
4
we try to rebuild the hflags.
5
2
6
Add a new helper rebuild_hflags_m32_newel() which, like the
3
Now that we can pass 7 parameters, do not encode register
7
existing rebuild_hflags_a32_newel(), recalculates the current
4
operands within simd_data.
8
EL from scratch, and use it in trans_MSR_v7m().
9
5
10
This fixes an assertion about an hflags mismatch when the
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
guest changes privilege by writing to CONTROL.
7
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200507172352.15418-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper-sve.h | 45 +++++++----
13
target/arm/sve_helper.c | 157 ++++++++++++++-----------------------
14
target/arm/translate-sve.c | 70 ++++++-----------
15
3 files changed, 114 insertions(+), 158 deletions(-)
12
16
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200303174950.3298-4-peter.maydell@linaro.org
16
---
17
target/arm/helper.h | 1 +
18
target/arm/helper.c | 12 ++++++++++++
19
target/arm/translate.c | 7 +++----
20
3 files changed, 16 insertions(+), 4 deletions(-)
21
22
diff --git a/target/arm/helper.h b/target/arm/helper.h
23
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.h
19
--- a/target/arm/helper-sve.h
25
+++ b/target/arm/helper.h
20
+++ b/target/arm/helper-sve.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
27
DEF_HELPER_2(get_user_reg, i32, env, i32)
22
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
28
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
23
void, ptr, ptr, ptr, ptr, ptr, i32)
29
24
30
+DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env)
25
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
31
DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
26
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
32
DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
27
-DEF_HELPER_FLAGS_3(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
33
DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
28
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
31
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
33
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
34
35
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
36
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
37
-DEF_HELPER_FLAGS_3(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
38
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
39
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
41
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
43
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
44
45
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
46
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
47
-DEF_HELPER_FLAGS_3(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
48
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
49
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
50
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
51
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
53
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
54
55
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
56
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
57
-DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
58
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
59
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
60
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
61
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
62
+DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
63
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
64
65
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32)
66
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
67
-DEF_HELPER_FLAGS_3(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
68
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
69
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
70
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
71
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
72
+DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
73
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
74
75
DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
76
DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
77
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
35
index XXXXXXX..XXXXXXX 100644
78
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
79
--- a/target/arm/sve_helper.c
37
+++ b/target/arm/helper.c
80
+++ b/target/arm/sve_helper.c
38
@@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env)
81
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64)
39
env->hflags = rebuild_hflags_internal(env);
82
40
}
83
#undef DO_ZPZ_FP
41
84
42
+/*
85
-/* 4-operand predicated multiply-add. This requires 7 operands to pass
43
+ * If we have triggered a EL state change we can't rely on the
86
- * "properly", so we need to encode some of the registers into DESC.
44
+ * translator having passed it to us, we need to recompute.
87
- */
45
+ */
88
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 20 > 32);
46
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
89
-
47
+{
90
-static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
48
+ int el = arm_current_el(env);
91
+static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
49
+ int fp_el = fp_exception_el(env, el);
92
+ float_status *status, uint32_t desc,
50
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
93
uint16_t neg1, uint16_t neg3)
51
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
94
{
52
+}
95
intptr_t i = simd_oprsz(desc);
53
+
96
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
54
void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
97
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
55
{
98
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
56
int fp_el = fp_exception_el(env, el);
99
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
57
diff --git a/target/arm/translate.c b/target/arm/translate.c
100
- void *vd = &env->vfp.zregs[rd];
101
- void *vn = &env->vfp.zregs[rn];
102
- void *vm = &env->vfp.zregs[rm];
103
- void *va = &env->vfp.zregs[ra];
104
uint64_t *g = vg;
105
106
do {
107
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
108
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
109
e2 = *(uint16_t *)(vm + H1_2(i));
110
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
111
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
112
+ r = float16_muladd(e1, e2, e3, 0, status);
113
*(uint16_t *)(vd + H1_2(i)) = r;
114
}
115
} while (i & 63);
116
} while (i != 0);
117
}
118
119
-void HELPER(sve_fmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
120
+void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
121
+ void *vg, void *status, uint32_t desc)
122
{
123
- do_fmla_zpzzz_h(env, vg, desc, 0, 0);
124
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
125
}
126
127
-void HELPER(sve_fmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
128
+void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
129
+ void *vg, void *status, uint32_t desc)
130
{
131
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0);
132
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
133
}
134
135
-void HELPER(sve_fnmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
136
+void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
137
+ void *vg, void *status, uint32_t desc)
138
{
139
- do_fmla_zpzzz_h(env, vg, desc, 0x8000, 0x8000);
140
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
141
}
142
143
-void HELPER(sve_fnmls_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
144
+void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
145
+ void *vg, void *status, uint32_t desc)
146
{
147
- do_fmla_zpzzz_h(env, vg, desc, 0, 0x8000);
148
+ do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
149
}
150
151
-static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
152
+static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
153
+ float_status *status, uint32_t desc,
154
uint32_t neg1, uint32_t neg3)
155
{
156
intptr_t i = simd_oprsz(desc);
157
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
158
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
159
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
160
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
161
- void *vd = &env->vfp.zregs[rd];
162
- void *vn = &env->vfp.zregs[rn];
163
- void *vm = &env->vfp.zregs[rm];
164
- void *va = &env->vfp.zregs[ra];
165
uint64_t *g = vg;
166
167
do {
168
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(CPUARMState *env, void *vg, uint32_t desc,
169
e1 = *(uint32_t *)(vn + H1_4(i)) ^ neg1;
170
e2 = *(uint32_t *)(vm + H1_4(i));
171
e3 = *(uint32_t *)(va + H1_4(i)) ^ neg3;
172
- r = float32_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
173
+ r = float32_muladd(e1, e2, e3, 0, status);
174
*(uint32_t *)(vd + H1_4(i)) = r;
175
}
176
} while (i & 63);
177
} while (i != 0);
178
}
179
180
-void HELPER(sve_fmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
181
+void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
182
+ void *vg, void *status, uint32_t desc)
183
{
184
- do_fmla_zpzzz_s(env, vg, desc, 0, 0);
185
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
186
}
187
188
-void HELPER(sve_fmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
189
+void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
190
+ void *vg, void *status, uint32_t desc)
191
{
192
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0);
193
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
194
}
195
196
-void HELPER(sve_fnmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
197
+void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
198
+ void *vg, void *status, uint32_t desc)
199
{
200
- do_fmla_zpzzz_s(env, vg, desc, 0x80000000, 0x80000000);
201
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
202
}
203
204
-void HELPER(sve_fnmls_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
205
+void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
206
+ void *vg, void *status, uint32_t desc)
207
{
208
- do_fmla_zpzzz_s(env, vg, desc, 0, 0x80000000);
209
+ do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
210
}
211
212
-static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
213
+static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
214
+ float_status *status, uint32_t desc,
215
uint64_t neg1, uint64_t neg3)
216
{
217
intptr_t i = simd_oprsz(desc);
218
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
219
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
220
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
221
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
222
- void *vd = &env->vfp.zregs[rd];
223
- void *vn = &env->vfp.zregs[rn];
224
- void *vm = &env->vfp.zregs[rm];
225
- void *va = &env->vfp.zregs[ra];
226
uint64_t *g = vg;
227
228
do {
229
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(CPUARMState *env, void *vg, uint32_t desc,
230
e1 = *(uint64_t *)(vn + i) ^ neg1;
231
e2 = *(uint64_t *)(vm + i);
232
e3 = *(uint64_t *)(va + i) ^ neg3;
233
- r = float64_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
234
+ r = float64_muladd(e1, e2, e3, 0, status);
235
*(uint64_t *)(vd + i) = r;
236
}
237
} while (i & 63);
238
} while (i != 0);
239
}
240
241
-void HELPER(sve_fmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
242
+void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
243
+ void *vg, void *status, uint32_t desc)
244
{
245
- do_fmla_zpzzz_d(env, vg, desc, 0, 0);
246
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
247
}
248
249
-void HELPER(sve_fmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
250
+void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
251
+ void *vg, void *status, uint32_t desc)
252
{
253
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, 0);
254
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
255
}
256
257
-void HELPER(sve_fnmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
258
+void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
259
+ void *vg, void *status, uint32_t desc)
260
{
261
- do_fmla_zpzzz_d(env, vg, desc, INT64_MIN, INT64_MIN);
262
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
263
}
264
265
-void HELPER(sve_fnmls_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
266
+void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
267
+ void *vg, void *status, uint32_t desc)
268
{
269
- do_fmla_zpzzz_d(env, vg, desc, 0, INT64_MIN);
270
+ do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
271
}
272
273
/* Two operand floating-point comparison controlled by a predicate.
274
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
275
* FP Complex Multiply
276
*/
277
278
-QEMU_BUILD_BUG_ON(SIMD_DATA_SHIFT + 22 > 32);
279
-
280
-void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
281
+void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
282
+ void *vg, void *status, uint32_t desc)
283
{
284
intptr_t j, i = simd_oprsz(desc);
285
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
286
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
287
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
288
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
289
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
290
+ unsigned rot = simd_data(desc);
291
bool flip = rot & 1;
292
float16 neg_imag, neg_real;
293
- void *vd = &env->vfp.zregs[rd];
294
- void *vn = &env->vfp.zregs[rn];
295
- void *vm = &env->vfp.zregs[rm];
296
- void *va = &env->vfp.zregs[ra];
297
uint64_t *g = vg;
298
299
neg_imag = float16_set_sign(0, (rot & 2) != 0);
300
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(CPUARMState *env, void *vg, uint32_t desc)
301
302
if (likely((pg >> (i & 63)) & 1)) {
303
d = *(float16 *)(va + H1_2(i));
304
- d = float16_muladd(e2, e1, d, 0, &env->vfp.fp_status_f16);
305
+ d = float16_muladd(e2, e1, d, 0, status);
306
*(float16 *)(vd + H1_2(i)) = d;
307
}
308
if (likely((pg >> (j & 63)) & 1)) {
309
d = *(float16 *)(va + H1_2(j));
310
- d = float16_muladd(e4, e3, d, 0, &env->vfp.fp_status_f16);
311
+ d = float16_muladd(e4, e3, d, 0, status);
312
*(float16 *)(vd + H1_2(j)) = d;
313
}
314
} while (i & 63);
315
} while (i != 0);
316
}
317
318
-void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
319
+void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
320
+ void *vg, void *status, uint32_t desc)
321
{
322
intptr_t j, i = simd_oprsz(desc);
323
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
324
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
325
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
326
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
327
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
328
+ unsigned rot = simd_data(desc);
329
bool flip = rot & 1;
330
float32 neg_imag, neg_real;
331
- void *vd = &env->vfp.zregs[rd];
332
- void *vn = &env->vfp.zregs[rn];
333
- void *vm = &env->vfp.zregs[rm];
334
- void *va = &env->vfp.zregs[ra];
335
uint64_t *g = vg;
336
337
neg_imag = float32_set_sign(0, (rot & 2) != 0);
338
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(CPUARMState *env, void *vg, uint32_t desc)
339
340
if (likely((pg >> (i & 63)) & 1)) {
341
d = *(float32 *)(va + H1_2(i));
342
- d = float32_muladd(e2, e1, d, 0, &env->vfp.fp_status);
343
+ d = float32_muladd(e2, e1, d, 0, status);
344
*(float32 *)(vd + H1_2(i)) = d;
345
}
346
if (likely((pg >> (j & 63)) & 1)) {
347
d = *(float32 *)(va + H1_2(j));
348
- d = float32_muladd(e4, e3, d, 0, &env->vfp.fp_status);
349
+ d = float32_muladd(e4, e3, d, 0, status);
350
*(float32 *)(vd + H1_2(j)) = d;
351
}
352
} while (i & 63);
353
} while (i != 0);
354
}
355
356
-void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
357
+void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
358
+ void *vg, void *status, uint32_t desc)
359
{
360
intptr_t j, i = simd_oprsz(desc);
361
- unsigned rd = extract32(desc, SIMD_DATA_SHIFT, 5);
362
- unsigned rn = extract32(desc, SIMD_DATA_SHIFT + 5, 5);
363
- unsigned rm = extract32(desc, SIMD_DATA_SHIFT + 10, 5);
364
- unsigned ra = extract32(desc, SIMD_DATA_SHIFT + 15, 5);
365
- unsigned rot = extract32(desc, SIMD_DATA_SHIFT + 20, 2);
366
+ unsigned rot = simd_data(desc);
367
bool flip = rot & 1;
368
float64 neg_imag, neg_real;
369
- void *vd = &env->vfp.zregs[rd];
370
- void *vn = &env->vfp.zregs[rn];
371
- void *vm = &env->vfp.zregs[rm];
372
- void *va = &env->vfp.zregs[ra];
373
uint64_t *g = vg;
374
375
neg_imag = float64_set_sign(0, (rot & 2) != 0);
376
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, void *vg, uint32_t desc)
377
378
if (likely((pg >> (i & 63)) & 1)) {
379
d = *(float64 *)(va + H1_2(i));
380
- d = float64_muladd(e2, e1, d, 0, &env->vfp.fp_status);
381
+ d = float64_muladd(e2, e1, d, 0, status);
382
*(float64 *)(vd + H1_2(i)) = d;
383
}
384
if (likely((pg >> (j & 63)) & 1)) {
385
d = *(float64 *)(va + H1_2(j));
386
- d = float64_muladd(e4, e3, d, 0, &env->vfp.fp_status);
387
+ d = float64_muladd(e4, e3, d, 0, status);
388
*(float64 *)(vd + H1_2(j)) = d;
389
}
390
} while (i & 63);
391
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
58
index XXXXXXX..XXXXXXX 100644
392
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/translate.c
393
--- a/target/arm/translate-sve.c
60
+++ b/target/arm/translate.c
394
+++ b/target/arm/translate-sve.c
61
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
395
@@ -XXX,XX +XXX,XX @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a)
62
396
return true;
63
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
397
}
64
{
398
65
- TCGv_i32 addr, reg, el;
399
-typedef void gen_helper_sve_fmla(TCGv_env, TCGv_ptr, TCGv_i32);
66
+ TCGv_i32 addr, reg;
400
-
67
401
-static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, gen_helper_sve_fmla *fn)
68
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
402
+static bool do_fmla(DisasContext *s, arg_rprrr_esz *a,
403
+ gen_helper_gvec_5_ptr *fn)
404
{
405
- if (fn == NULL) {
406
+ if (a->esz == 0) {
69
return false;
407
return false;
70
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
408
}
71
gen_helper_v7m_msr(cpu_env, addr, reg);
409
- if (!sve_access_check(s)) {
72
tcg_temp_free_i32(addr);
410
- return true;
73
tcg_temp_free_i32(reg);
411
+ if (sve_access_check(s)) {
74
- el = tcg_const_i32(s->current_el);
412
+ unsigned vsz = vec_full_reg_size(s);
75
- gen_helper_rebuild_hflags_m32(cpu_env, el);
413
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
76
- tcg_temp_free_i32(el);
414
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
77
+ /* If we wrote to CONTROL, the EL might have changed */
415
+ vec_full_reg_offset(s, a->rn),
78
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
416
+ vec_full_reg_offset(s, a->rm),
79
gen_lookup_tb(s);
417
+ vec_full_reg_offset(s, a->ra),
418
+ pred_full_reg_offset(s, a->pg),
419
+ status, vsz, vsz, 0, fn);
420
+ tcg_temp_free_ptr(status);
421
}
422
-
423
- unsigned vsz = vec_full_reg_size(s);
424
- unsigned desc;
425
- TCGv_i32 t_desc;
426
- TCGv_ptr pg = tcg_temp_new_ptr();
427
-
428
- /* We would need 7 operands to pass these arguments "properly".
429
- * So we encode all the register numbers into the descriptor.
430
- */
431
- desc = deposit32(a->rd, 5, 5, a->rn);
432
- desc = deposit32(desc, 10, 5, a->rm);
433
- desc = deposit32(desc, 15, 5, a->ra);
434
- desc = simd_desc(vsz, vsz, desc);
435
-
436
- t_desc = tcg_const_i32(desc);
437
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
438
- fn(cpu_env, pg, t_desc);
439
- tcg_temp_free_i32(t_desc);
440
- tcg_temp_free_ptr(pg);
441
return true;
442
}
443
444
#define DO_FMLA(NAME, name) \
445
static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
446
{ \
447
- static gen_helper_sve_fmla * const fns[4] = { \
448
+ static gen_helper_gvec_5_ptr * const fns[4] = { \
449
NULL, gen_helper_sve_##name##_h, \
450
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \
451
}; \
452
@@ -XXX,XX +XXX,XX @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz)
453
454
static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
455
{
456
- static gen_helper_sve_fmla * const fns[3] = {
457
+ static gen_helper_gvec_5_ptr * const fns[4] = {
458
+ NULL,
459
gen_helper_sve_fcmla_zpzzz_h,
460
gen_helper_sve_fcmla_zpzzz_s,
461
gen_helper_sve_fcmla_zpzzz_d,
462
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
463
}
464
if (sve_access_check(s)) {
465
unsigned vsz = vec_full_reg_size(s);
466
- unsigned desc;
467
- TCGv_i32 t_desc;
468
- TCGv_ptr pg = tcg_temp_new_ptr();
469
-
470
- /* We would need 7 operands to pass these arguments "properly".
471
- * So we encode all the register numbers into the descriptor.
472
- */
473
- desc = deposit32(a->rd, 5, 5, a->rn);
474
- desc = deposit32(desc, 10, 5, a->rm);
475
- desc = deposit32(desc, 15, 5, a->ra);
476
- desc = deposit32(desc, 20, 2, a->rot);
477
- desc = sextract32(desc, 0, 22);
478
- desc = simd_desc(vsz, vsz, desc);
479
-
480
- t_desc = tcg_const_i32(desc);
481
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
482
- fns[a->esz - 1](cpu_env, pg, t_desc);
483
- tcg_temp_free_i32(t_desc);
484
- tcg_temp_free_ptr(pg);
485
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
486
+ tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd),
487
+ vec_full_reg_offset(s, a->rn),
488
+ vec_full_reg_offset(s, a->rm),
489
+ vec_full_reg_offset(s, a->ra),
490
+ pred_full_reg_offset(s, a->pg),
491
+ status, vsz, vsz, a->rot, fns[a->esz]);
492
+ tcg_temp_free_ptr(status);
493
}
80
return true;
494
return true;
81
}
495
}
82
--
496
--
83
2.20.1
497
2.20.1
84
498
85
499
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We plan to introduce yet another value for the gic version (nosel).
3
DUP (indexed) can duplicate 128-bit elements, so using esz
4
As we already use exotic values such as 0 and -1, let's introduce
4
unconditionally can assert in tcg_gen_gvec_dup_imm.
5
a dedicated enum type and let vms->gic_version take this
6
type.
7
5
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Fixes: 8711e71f9cbb
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Message-id: 20200311131618.7187-3-eric.auger@redhat.com
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20200507172352.15418-5-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
include/hw/arm/virt.h | 11 +++++++++--
14
target/arm/translate-sve.c | 6 +++++-
16
hw/arm/virt.c | 30 +++++++++++++++---------------
15
1 file changed, 5 insertions(+), 1 deletion(-)
17
2 files changed, 24 insertions(+), 17 deletions(-)
18
16
19
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/virt.h
19
--- a/target/arm/translate-sve.c
22
+++ b/include/hw/arm/virt.h
20
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
21
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
24
VIRT_IOMMU_VIRTIO,
22
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
25
} VirtIOMMUType;
23
tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
26
24
} else {
27
+typedef enum VirtGICType {
25
- tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
28
+ VIRT_GIC_VERSION_MAX,
26
+ /*
29
+ VIRT_GIC_VERSION_HOST,
27
+ * While dup_mem handles 128-bit elements, dup_imm does not.
30
+ VIRT_GIC_VERSION_2,
28
+ * Thankfully element size doesn't matter for splatting zero.
31
+ VIRT_GIC_VERSION_3,
29
+ */
32
+} VirtGICType;
30
+ tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
33
+
34
typedef struct MemMapEntry {
35
hwaddr base;
36
hwaddr size;
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
bool highmem_ecam;
39
bool its;
40
bool virt;
41
- int32_t gic_version;
42
+ VirtGICType gic_version;
43
VirtIOMMUType iommu;
44
uint16_t virtio_iommu_bdf;
45
struct arm_boot_info bootinfo;
46
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
47
uint32_t redist0_capacity =
48
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
49
50
- assert(vms->gic_version == 3);
51
+ assert(vms->gic_version == VIRT_GIC_VERSION_3);
52
53
return vms->smp_cpus > redist0_capacity ? 2 : 1;
54
}
55
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/virt.c
58
+++ b/hw/arm/virt.c
59
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
60
irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
61
}
62
63
- if (vms->gic_version == 2) {
64
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
65
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
66
GIC_FDT_IRQ_PPI_CPU_WIDTH,
67
(1 << vms->smp_cpus) - 1);
68
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
70
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
71
qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
72
- if (vms->gic_version == 3) {
73
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
74
int nb_redist_regions = virt_gicv3_redist_region_count(vms);
75
76
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
77
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
78
}
31
}
79
}
32
}
80
33
return true;
81
- if (vms->gic_version == 2) {
82
+ if (vms->gic_version == VIRT_GIC_VERSION_2) {
83
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
84
GIC_FDT_IRQ_PPI_CPU_WIDTH,
85
(1 << vms->smp_cpus) - 1);
86
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
87
* purposes are to make TCG consistent (with 64-bit KVM hosts)
88
* and to improve SGI efficiency.
89
*/
90
- if (vms->gic_version == 3) {
91
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
92
clustersz = GICV3_TARGETLIST_BITS;
93
} else {
94
clustersz = GIC_TARGETLIST_BITS;
95
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
96
/* We can probe only here because during property set
97
* KVM is not available yet
98
*/
99
- if (vms->gic_version <= 0) {
100
- /* "host" or "max" */
101
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST ||
102
+ vms->gic_version == VIRT_GIC_VERSION_MAX) {
103
if (!kvm_enabled()) {
104
- if (vms->gic_version == 0) {
105
+ if (vms->gic_version == VIRT_GIC_VERSION_HOST) {
106
error_report("gic-version=host requires KVM");
107
exit(1);
108
} else {
109
/* "max": currently means 3 for TCG */
110
- vms->gic_version = 3;
111
+ vms->gic_version = VIRT_GIC_VERSION_3;
112
}
113
} else {
114
vms->gic_version = kvm_arm_vgic_probe();
115
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
116
/* The maximum number of CPUs depends on the GIC version, or on how
117
* many redistributors we can fit into the memory map.
118
*/
119
- if (vms->gic_version == 3) {
120
+ if (vms->gic_version == VIRT_GIC_VERSION_3) {
121
virt_max_cpus =
122
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
123
virt_max_cpus +=
124
@@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp)
125
static char *virt_get_gic_version(Object *obj, Error **errp)
126
{
127
VirtMachineState *vms = VIRT_MACHINE(obj);
128
- const char *val = vms->gic_version == 3 ? "3" : "2";
129
+ const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
130
131
return g_strdup(val);
132
}
133
@@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
134
VirtMachineState *vms = VIRT_MACHINE(obj);
135
136
if (!strcmp(value, "3")) {
137
- vms->gic_version = 3;
138
+ vms->gic_version = VIRT_GIC_VERSION_3;
139
} else if (!strcmp(value, "2")) {
140
- vms->gic_version = 2;
141
+ vms->gic_version = VIRT_GIC_VERSION_2;
142
} else if (!strcmp(value, "host")) {
143
- vms->gic_version = 0; /* Will probe later */
144
+ vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
145
} else if (!strcmp(value, "max")) {
146
- vms->gic_version = -1; /* Will probe later */
147
+ vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
148
} else {
149
error_setg(errp, "Invalid gic-version value");
150
error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
151
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
152
"physical address space above 32 bits",
153
NULL);
154
/* Default GIC type is v2 */
155
- vms->gic_version = 2;
156
+ vms->gic_version = VIRT_GIC_VERSION_2;
157
object_property_add_str(obj, "gic-version", virt_get_gic_version,
158
virt_set_gic_version, NULL);
159
object_property_set_description(obj, "gic-version",
160
--
34
--
161
2.20.1
35
2.20.1
162
36
163
37
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