arm queue; dunno if this will be the last before softfreeze

or not, but anyway probably the last large one. New orangepi-pc

board model is the big item here.

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312

for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:

target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)

* Fix various bugs that might result in an assert() due to

incorrect hflags for M-profile CPUs

* Fix Aspeed SMC Controller user-mode select handling

* Report correct (with-tag) address in fault address register

when TBI is enabled

* cubieboard: make sure SOC object isn't leaked

* fsl-imx25: Wire up eSDHC controllers

* fsl-imx25: Wire up USB controllers

* New board model: orangepi-pc (OrangePi PC)

* ARM/KVM: if user doesn't select GIC version and the

host kernel can only provide GICv3, use that, rather

than defaulting to "fail because GICv2 isn't possible"

* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync

Beata Michalska (1):

target/arm: kvm: Inject events at the last stage of sync

Cédric Le Goater (2):

aspeed/smc: Add some tracing

aspeed/smc: Fix User mode select/unselect scheme

Eric Auger (6):

hw/arm/virt: Document 'max' value in gic-version property description

hw/arm/virt: Introduce VirtGICType enum type

hw/arm/virt: Introduce finalize_gic_version()

target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap

hw/arm/virt: kvm: Restructure finalize_gic_version()

hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work

hw/arm/fsl-imx25: Wire up eSDHC controllers

hw/arm/fsl-imx25: Wire up USB controllers

Igor Mammedov (1):

hw/arm/cubieboard: make sure SOC object isn't leaked

Niek Linnenbank (13):

hw/arm: add Allwinner H3 System-on-Chip

hw/arm: add Xunlong Orange Pi PC machine

hw/arm/allwinner-h3: add Clock Control Unit

hw/arm/allwinner-h3: add USB host controller

hw/arm/allwinner-h3: add System Control module

hw/arm/allwinner: add CPU Configuration module

hw/arm/allwinner: add Security Identifier device

hw/arm/allwinner: add SD/MMC host controller

hw/arm/allwinner-h3: add EMAC ethernet device

hw/arm/allwinner-h3: add Boot ROM support

hw/arm/allwinner-h3: add SDRAM controller device

hw/arm/allwinner: add RTC device support

docs: add Orange Pi PC document

Peter Maydell (4):

hw/intc/armv7m_nvic: Rebuild hflags on reset

target/arm: Update hflags in trans_CPS_v7m()

target/arm: Recalculate hflags correctly after writes to CONTROL

target/arm: Fix some comment typos

Philippe Mathieu-Daudé (5):

tests/boot_linux_console: Add a quick test for the OrangePi PC board

tests/boot_linux_console: Add initrd test for the Orange Pi PC board

tests/boot_linux_console: Add a SD card test for the OrangePi PC board

tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC

tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC

Richard Henderson (2):

target/arm: Check addresses for disabled regimes

target/arm: Disable clean_data_tbi for system mode

Makefile.objs | 1 +

hw/arm/Makefile.objs | 1 +

hw/misc/Makefile.objs | 5 +

hw/net/Makefile.objs | 1 +

hw/rtc/Makefile.objs | 1 +

hw/sd/Makefile.objs | 1 +

hw/usb/hcd-ehci.h | 1 +

include/hw/arm/allwinner-a10.h | 4 +

include/hw/arm/allwinner-h3.h | 161 ++++++

include/hw/arm/fsl-imx25.h | 18 +

include/hw/arm/virt.h | 12 +-

include/hw/misc/allwinner-cpucfg.h | 52 ++

include/hw/misc/allwinner-h3-ccu.h | 66 +++

include/hw/misc/allwinner-h3-dramc.h | 106 ++++

include/hw/misc/allwinner-h3-sysctrl.h | 67 +++

include/hw/misc/allwinner-sid.h | 60 +++

include/hw/net/allwinner-sun8i-emac.h | 99 ++++

include/hw/rtc/allwinner-rtc.h | 134 +++++

include/hw/sd/allwinner-sdhost.h | 135 +++++

target/arm/helper.h | 1 +

target/arm/kvm_arm.h | 3 +

hw/arm/allwinner-a10.c | 19 +

hw/arm/allwinner-h3.c | 465 ++++++++++++++++++

hw/arm/cubieboard.c | 18 +

hw/arm/fsl-imx25.c | 56 +++

hw/arm/imx25_pdk.c | 16 +

hw/arm/orangepi.c | 130 +++++

hw/arm/virt.c | 145 ++++--

hw/intc/armv7m_nvic.c | 6 +

hw/misc/allwinner-cpucfg.c | 282 +++++++++++

hw/misc/allwinner-h3-ccu.c | 242 +++++++++

hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++

hw/misc/allwinner-h3-sysctrl.c | 140 ++++++

hw/misc/allwinner-sid.c | 168 +++++++

hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++

hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++

hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++

hw/ssi/aspeed_smc.c | 56 ++-

hw/usb/hcd-ehci-sysbus.c | 17 +

target/arm/helper.c | 49 +-

target/arm/kvm.c | 14 +-

target/arm/kvm32.c | 15 +-

target/arm/kvm64.c | 15 +-

target/arm/translate-a64.c | 11 +

target/arm/translate.c | 14 +-

MAINTAINERS | 9 +

default-configs/arm-softmmu.mak | 1 +

docs/system/arm/orangepi.rst | 253 ++++++++++

docs/system/target-arm.rst | 2 +

hw/arm/Kconfig | 12 +

hw/misc/trace-events | 19 +

hw/net/Kconfig | 3 +

hw/net/trace-events | 10 +

hw/rtc/trace-events | 4 +

hw/sd/trace-events | 7 +

hw/ssi/trace-events | 10 +

tests/acceptance/boot_linux_console.py | 230 +++++++++

57 files changed, 5787 insertions(+), 74 deletions(-)

create mode 100644 include/hw/arm/allwinner-h3.h

create mode 100644 include/hw/misc/allwinner-cpucfg.h

create mode 100644 include/hw/misc/allwinner-h3-ccu.h

create mode 100644 include/hw/misc/allwinner-h3-dramc.h

create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h

create mode 100644 include/hw/misc/allwinner-sid.h

create mode 100644 include/hw/net/allwinner-sun8i-emac.h

create mode 100644 include/hw/rtc/allwinner-rtc.h

create mode 100644 include/hw/sd/allwinner-sdhost.h

create mode 100644 hw/arm/allwinner-h3.c

create mode 100644 hw/arm/orangepi.c

create mode 100644 hw/misc/allwinner-cpucfg.c

create mode 100644 hw/misc/allwinner-h3-ccu.c

create mode 100644 hw/misc/allwinner-h3-dramc.c

create mode 100644 hw/misc/allwinner-h3-sysctrl.c

create mode 100644 hw/misc/allwinner-sid.c

create mode 100644 hw/net/allwinner-sun8i-emac.c

create mode 100644 hw/rtc/allwinner-rtc.c

create mode 100644 hw/sd/allwinner-sdhost.c

create mode 100644 docs/system/arm/orangepi.rst

create mode 100644 hw/ssi/trace-events

From: Eric Auger <eric.auger@redhat.com>

At the moment if the end-user does not specify the gic-version along

with KVM acceleration, v2 is set by default. However most of the

systems now have GICv3 and sometimes they do not support GICv2

compatibility.

This patch keeps the default v2 selection in all cases except

in the KVM accelerated mode when either

- the host does not support GICv2 in-kernel emulation or

- number of VCPUS exceeds 8.

Those cases did not work anyway so we do not break any compatibility.

Now we get v3 selected in such a case.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Message-id: 20200311131618.7187-7-eric.auger@redhat.com

hw/arm/virt.c | 17 ++++++++++++++++-

1 file changed, 16 insertions(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)

*/

static void finalize_gic_version(VirtMachineState *vms)

{

+ unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;

+

if (kvm_enabled()) {

int probe_bitmap;

@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)

}

return;

case VIRT_GIC_VERSION_NOSEL:

- vms->gic_version = VIRT_GIC_VERSION_2;

+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {

+ vms->gic_version = VIRT_GIC_VERSION_2;

+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {

+ /*

+ * in case the host does not support v2 in-kernel emulation or

+ * the end-user requested more than 8 VCPUs we now default

+ * to v3. In any case defaulting to v2 would be broken.

+ */

+ vms->gic_version = VIRT_GIC_VERSION_3;

+ } else if (max_cpus > GIC_NCPU) {

+ error_report("host only supports in-kernel GICv2 emulation "

+ "but more than 8 vcpus are requested");

+ exit(1);

+ }

break;

case VIRT_GIC_VERSION_2:

case VIRT_GIC_VERSION_3:

We must include the tag in the FAR_ELx register when raising

an addressing exception. Which means that we should not clear

out the tag during translation.

Message-id: 20200308012946.16303-3-richard.henderson@linaro.org

target/arm/translate-a64.c | 11 +++++++++++

1 file changed, 11 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)

static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)

{

TCGv_i64 clean = new_tmp_a64(s);

+ /*

+ * In order to get the correct value in the FAR_ELx register,

+ * we must present the memory subsystem with the "dirty" address

+ * including the TBI. In system mode we can make this work via

+ * the TLB, dropping the TBI during translation. But for user-only

+ * mode we don't have that option, and must remove the top byte now.

+ */

+#ifdef CONFIG_USER_ONLY

gen_top_byte_ignore(s, clean, addr, s->tbid);

+#else

+ tcg_gen_mov_i64(clean, addr);

+#endif

return clean;

}

This test boots Ubuntu Bionic on a OrangePi PC board.

As it requires 1GB of storage, and is slow, this test is disabled

on automatic CI testing.

It is useful for workstation testing. Currently Avocado timeouts too

quickly, so we can't run userland commands.

The kernel image and DeviceTree blob are built by the Armbian

project (based on Debian):

https://www.armbian.com/orange-pi-pc/

The Ubuntu image is downloaded from:

https://dl.armbian.com/orangepipc/Bionic_current

This test can be run using:

$ AVOCADO_ALLOW_LARGE_STORAGE=yes \

avocado --show=app,console run -t machine:orangepi-pc \

tests/acceptance/boot_linux_console.py

console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)

console: DRAM: 1024 MiB

console: Failed to set core voltage! Can't set CPU frequency

console: Trying to boot from MMC1

console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology

console: CPU: Allwinner H3 (SUN8I 0000)

console: Model: Xunlong Orange Pi PC

console: DRAM: 1 GiB

console: MMC: mmc@1c0f000: 0

[...]

console: Uncompressing Linux... done, booting the kernel.

console: Booting Linux on physical CPU 0x0

console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019

console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d

console: CPU: div instructions available: patching division code

console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

console: OF: fdt: Machine model: Xunlong Orange Pi PC

[...]

console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)

console: done.

console: Begin: Running /scripts/local-bottom ... done.

console: Begin: Running /scripts/init-bottom ... done.

console: systemd[1]: systemd 237 running in system mode. (...)

console: systemd[1]: Detected architecture arm.

console: Welcome to Ubuntu 18.04.3 LTS!

console: systemd[1]: Set hostname to <orangepipc>.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com

[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]

[NL: changed test to boot from SD card via BootROM, added check for 7z]

tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++

1 file changed, 48 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py

--- a/tests/acceptance/boot_linux_console.py

+++ b/tests/acceptance/boot_linux_console.py

@@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern

from avocado_qemu import wait_for_console_pattern

from avocado.utils import process

from avocado.utils import archive

+from avocado.utils.path import find_command, CmdNotFoundError

+P7ZIP_AVAILABLE = True

+try:

+ find_command('7z')

+except CmdNotFoundError:

+ P7ZIP_AVAILABLE = False

class BootLinuxConsole(Test):

"""

@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):

exec_command_and_wait_for_pattern(self, 'reboot',

'reboot: Restarting system')

+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')

+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')

+ def test_arm_orangepi_bionic(self):

+ """

+ :avocado: tags=arch:arm

+ :avocado: tags=machine:orangepi-pc

+ """

+

+ # This test download a 196MB compressed image and expand it to 932MB...

+ image_url = ('https://dl.armbian.com/orangepipc/archive/'

+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')

+ image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e'

+ image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash)

+ image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img'

+ image_path = os.path.join(self.workdir, image_name)

+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))

+

+ self.vm.set_console()

+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',

+ '-nic', 'user',

+ '-no-reboot')

+ self.vm.launch()

+

+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +

+ 'console=ttyS0,115200 '

+ 'loglevel=7 '

+ 'nosmp '

+ 'systemd.default_timeout_start_sec=9000 '

+ 'systemd.mask=armbian-zram-config.service '

+ 'systemd.mask=armbian-ramlog.service')

+

+ self.wait_for_console_pattern('U-Boot SPL')

+ self.wait_for_console_pattern('Autoboot in ')

+ exec_command_and_wait_for_pattern(self, ' ', '=>')

+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +

+ kernel_command_line + "'", '=>')

+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');

+

+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +

+ 'to <orangepipc>')

+ self.wait_for_console_pattern('Starting Load Kernel Modules...')

+

def test_s390x_s390_ccw_virtio(self):

"""

:avocado: tags=arch:s390x

From: Niek Linnenbank <nieklinnenbank@gmail.com>

In the Allwinner H3 SoC the SDRAM controller is responsible

for interfacing with the external Synchronous Dynamic Random

Access Memory (SDRAM). Types of memory that the SDRAM controller

supports are DDR2/DDR3 and capacities of up to 2GiB. This commit

adds emulation support of the Allwinner H3 SDRAM controller.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com

hw/misc/Makefile.objs | 1 +

include/hw/arm/allwinner-h3.h | 5 +

include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++

hw/arm/allwinner-h3.c | 19 +-

hw/arm/orangepi.c | 6 +

hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++

hw/misc/trace-events | 10 +

7 files changed, 502 insertions(+), 3 deletions(-)

create mode 100644 include/hw/misc/allwinner-h3-dramc.h

create mode 100644 hw/misc/allwinner-h3-dramc.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o

common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o

obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o

+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o

common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o

common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o

common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h

--- a/include/hw/arm/allwinner-h3.h

+++ b/include/hw/arm/allwinner-h3.h

@@ -XXX,XX +XXX,XX @@

#include "hw/intc/arm_gic.h"

#include "hw/misc/allwinner-h3-ccu.h"

#include "hw/misc/allwinner-cpucfg.h"

+#include "hw/misc/allwinner-h3-dramc.h"

#include "hw/misc/allwinner-h3-sysctrl.h"

#include "hw/misc/allwinner-sid.h"

#include "hw/sd/allwinner-sdhost.h"

@@ -XXX,XX +XXX,XX @@ enum {

AW_H3_UART2,

AW_H3_UART3,

AW_H3_EMAC,

+ AW_H3_DRAMCOM,

+ AW_H3_DRAMCTL,

+ AW_H3_DRAMPHY,

AW_H3_GIC_DIST,

AW_H3_GIC_CPU,

AW_H3_GIC_HYP,

@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {

AwA10PITState timer;

AwH3ClockCtlState ccu;

AwCpuCfgState cpucfg;

+ AwH3DramCtlState dramc;

AwH3SysCtrlState sysctrl;

AwSidState sid;

AwSdHostState mmc0;

diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/allwinner-h3-dramc.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Allwinner H3 SDRAM Controller emulation

+ *

+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>

+ *

+ * This program is free software: you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation, either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program. If not, see <http://www.gnu.org/licenses/>.

+ */

+

+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H

+#define HW_MISC_ALLWINNER_H3_DRAMC_H

+

+#include "qom/object.h"

+#include "hw/sysbus.h"

+#include "exec/hwaddr.h"

+

+/**

+ * Constants

+ * @{

+ */

+

+/** Highest register address used by DRAMCOM module */

+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)

+

+/** Total number of known DRAMCOM registers */

+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \

+ sizeof(uint32_t))

+

+/** Highest register address used by DRAMCTL module */

+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)

+

+/** Total number of known DRAMCTL registers */

+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \

+ sizeof(uint32_t))

+

+/** Highest register address used by DRAMPHY module */

+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)

+

+/** Total number of known DRAMPHY registers */

+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \

+ sizeof(uint32_t))

+

+/** @} */

+

+/**

+ * Object model

+ * @{

+ */

+

+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"

+#define AW_H3_DRAMC(obj) \

+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)

+

+/** @} */

+

+/**

+ * Allwinner H3 SDRAM Controller object instance state.

+ */

+typedef struct AwH3DramCtlState {

+ /*< private >*/

+ SysBusDevice parent_obj;

+ /*< public >*/

+

+ /** Physical base address for start of RAM */

+ hwaddr ram_addr;

+

+ /** Total RAM size in megabytes */

+ uint32_t ram_size;

+

+ /**

+ * @name Memory Regions

+ * @{

+ */

+

+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */

+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */

+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */

+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */

+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */

+

+ /** @} */

+

+ /**

+ * @name Hardware Registers

+ * @{

+ */

+

+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */

+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */

+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */

+

+ /** @} */

+

+} AwH3DramCtlState;

+

+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */

diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c

--- a/hw/arm/allwinner-h3.c

+++ b/hw/arm/allwinner-h3.c

@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {

[AW_H3_UART2] = 0x01c28800,

[AW_H3_UART3] = 0x01c28c00,

[AW_H3_EMAC] = 0x01c30000,

+ [AW_H3_DRAMCOM] = 0x01c62000,

+ [AW_H3_DRAMCTL] = 0x01c63000,

+ [AW_H3_DRAMPHY] = 0x01c65000,

[AW_H3_GIC_DIST] = 0x01c81000,

[AW_H3_GIC_CPU] = 0x01c82000,

[AW_H3_GIC_HYP] = 0x01c84000,

@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {

{ "scr", 0x01c2c400, 1 * KiB },

{ "gpu", 0x01c40000, 64 * KiB },

{ "hstmr", 0x01c60000, 4 * KiB },

- { "dramcom", 0x01c62000, 4 * KiB },

- { "dramctl0", 0x01c63000, 4 * KiB },

- { "dramphy0", 0x01c65000, 4 * KiB },

{ "spi0", 0x01c68000, 4 * KiB },

{ "spi1", 0x01c69000, 4 * KiB },

{ "csi", 0x01cb0000, 320 * KiB },

@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)

sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),

TYPE_AW_SUN8I_EMAC);

+

+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),

+ TYPE_AW_H3_DRAMC);

+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),

+ "ram-addr", &error_abort);

+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),

+ "ram-size", &error_abort);

static void allwinner_h3_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)

qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),

115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);

+ /* DRAMC */

+ qdev_init_nofail(DEVICE(&s->dramc));

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);

+

/* Unimplemented devices */

for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {

create_unimplemented_device(unimplemented[i].device_name,

diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/orangepi.c

+++ b/hw/arm/orangepi.c

@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)

/* Setup EMAC properties */

object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort);

+ /* DRAMC */

+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],

+ "ram-addr", &error_abort);

+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size",

+ &error_abort);

+

/* Mark H3 object realized */

object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);

diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/allwinner-h3-dramc.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Allwinner H3 SDRAM Controller emulation

+ *

+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>

+ *

+ * This program is free software: you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation, either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program. If not, see <http://www.gnu.org/licenses/>.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/units.h"

+#include "qemu/error-report.h"

+#include "hw/sysbus.h"

+#include "migration/vmstate.h"

+#include "qemu/log.h"

+#include "qemu/module.h"

+#include "exec/address-spaces.h"

+#include "hw/qdev-properties.h"

+#include "qapi/error.h"

+#include "hw/misc/allwinner-h3-dramc.h"

+#include "trace.h"

+

+#define REG_INDEX(offset) (offset / sizeof(uint32_t))

+

+/* DRAMCOM register offsets */

+enum {

+ REG_DRAMCOM_CR = 0x0000, /* Control Register */

+};

+

+/* DRAMCTL register offsets */

+enum {

+ REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */

+ REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */

+ REG_DRAMCTL_STATR = 0x0018, /* Status Register */

+};

+

+/* DRAMCTL register flags */

+enum {

+ REG_DRAMCTL_PGSR_INITDONE = (1 << 0),

+};

+

+enum {

+ REG_DRAMCTL_STATR_ACTIVE = (1 << 0),

+};

+

+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,

+ uint8_t bank_bits, uint16_t page_size)

+ * This function simulates row addressing behavior when bootloader

+ * software attempts to detect the amount of available SDRAM. In U-Boot

+ * the controller is configured with the widest row addressing available.

+ * Then a pattern is written to RAM at an offset on the row boundary size.

+ * If the value read back equals the value read back from the

+ * start of RAM, the bootloader knows the amount of row bits.

+ *

+ * This function inserts a mirrored memory region when the configured row

+ * bits are not matching the actual emulated memory, to simulate the

+ * same behavior on hardware as expected by the bootloader.

+ uint8_t row_bits_actual = 0;

+ /* Calculate the actual row bits using the ram_size property */

+ for (uint8_t i = 8; i < 12; i++) {

+ if (1 << i == s->ram_size) {

+ row_bits_actual = i + 3;

+ break;

+ }

+

+ if (s->ram_size == (1 << (row_bits - 3))) {

+ /* When row bits is the expected value, remove the mirror */

+ memory_region_set_enabled(&s->row_mirror_alias, false);

+ trace_allwinner_h3_dramc_rowmirror_disable();

+

+ } else if (row_bits_actual) {

+ /* Row bits not matching ram_size, install the rows mirror */

+ hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +

+ bank_bits)) * page_size);

+

+ memory_region_set_enabled(&s->row_mirror_alias, true);

+ memory_region_set_address(&s->row_mirror_alias, row_mirror);

+

+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);

+ }

+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+

+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);

+

+ return s->dramcom[idx];

+}

+

+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,

+ uint64_t val, unsigned size)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ trace_allwinner_h3_dramcom_write(offset, val, size);

+

+ if (idx >= AW_H3_DRAMCOM_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ switch (offset) {

+ case REG_DRAMCOM_CR: /* Control Register */

+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,

+ ((val >> 2) & 0x1) + 2,

+ 1 << (((val >> 8) & 0xf) + 3));

+ break;

+ default:

+ break;

+ };

+

+ s->dramcom[idx] = (uint32_t) val;

+}

+

+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+

+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);

+

+ return s->dramctl[idx];

+}

+

+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,

+ uint64_t val, unsigned size)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ trace_allwinner_h3_dramctl_write(offset, val, size);

+

+ if (idx >= AW_H3_DRAMCTL_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return;

+ }

+

+ switch (offset) {

+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */

+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;

+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;

+ break;

+ default:

+ break;

+ }

+

+ s->dramctl[idx] = (uint32_t) val;

+}

+

+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return 0;

+ }

+

+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);

+

+ return s->dramphy[idx];

+}

+

+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,

+ uint64_t val, unsigned size)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(opaque);

+ const uint32_t idx = REG_INDEX(offset);

+

+ trace_allwinner_h3_dramphy_write(offset, val, size);

+

+ if (idx >= AW_H3_DRAMPHY_REGS_NUM) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",

+ __func__, (uint32_t)offset);

+ return;

+ }

+

+ s->dramphy[idx] = (uint32_t) val;

+}

+

+static const MemoryRegionOps allwinner_h3_dramcom_ops = {

+ .read = allwinner_h3_dramcom_read,

+ .write = allwinner_h3_dramcom_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .valid = {

+ .min_access_size = 4,

+ .max_access_size = 4,

+ },

+ .impl.min_access_size = 4,

+};

+

+static const MemoryRegionOps allwinner_h3_dramctl_ops = {

+ .read = allwinner_h3_dramctl_read,

+ .write = allwinner_h3_dramctl_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .valid = {

+ .min_access_size = 4,

+ .max_access_size = 4,

+ },

+ .impl.min_access_size = 4,

+};

+

+static const MemoryRegionOps allwinner_h3_dramphy_ops = {

+ .read = allwinner_h3_dramphy_read,

+ .write = allwinner_h3_dramphy_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .valid = {

+ .min_access_size = 4,

+ .max_access_size = 4,

+ },

+ .impl.min_access_size = 4,

+};

+

+static void allwinner_h3_dramc_reset(DeviceState *dev)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);

+

+ /* Set default values for registers */

+ memset(&s->dramcom, 0, sizeof(s->dramcom));

+ memset(&s->dramctl, 0, sizeof(s->dramctl));

+ memset(&s->dramphy, 0, sizeof(s->dramphy));

+}

+

+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)

+{

+ AwH3DramCtlState *s = AW_H3_DRAMC(dev);

+

+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */

+ for (uint8_t i = 8; i < 13; i++) {

+ if (1 << i == s->ram_size) {

+ break;

+ } else if (i == 12) {

+ error_report("%s: ram-size %u MiB is not supported",

+ __func__, s->ram_size);

+ exit(1);

+ }

+ }

+

+ /* Setup row mirror mappings */

+ memory_region_init_ram(&s->row_mirror, OBJECT(s),

+ "allwinner-h3-dramc.row-mirror",

+ 4 * KiB, &error_abort);

+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,

+ &s->row_mirror, 10);

+

+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),

+ "allwinner-h3-dramc.row-mirror-alias",

+ &s->row_mirror, 0, 4 * KiB);

+ memory_region_add_subregion_overlap(get_system_memory(),

+ s->ram_addr + 1 * MiB,

+ &s->row_mirror_alias, 10);

+ memory_region_set_enabled(&s->row_mirror_alias, false);

+}

+

+static void allwinner_h3_dramc_init(Object *obj)

+{

+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

+ AwH3DramCtlState *s = AW_H3_DRAMC(obj);

+

+ /* DRAMCOM registers */

+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),

+ &allwinner_h3_dramcom_ops, s,

+ TYPE_AW_H3_DRAMC, 4 * KiB);

+ sysbus_init_mmio(sbd, &s->dramcom_iomem);

+

+ /* DRAMCTL registers */

+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),

+ &allwinner_h3_dramctl_ops, s,

+ TYPE_AW_H3_DRAMC, 4 * KiB);

+ sysbus_init_mmio(sbd, &s->dramctl_iomem);

+

+ /* DRAMPHY registers */

+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),

+ &allwinner_h3_dramphy_ops, s,

+ TYPE_AW_H3_DRAMC, 4 * KiB);

+ sysbus_init_mmio(sbd, &s->dramphy_iomem);

+}

+

+static Property allwinner_h3_dramc_properties[] = {

+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),

+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),

+ DEFINE_PROP_END_OF_LIST()

+};

+

+static const VMStateDescription allwinner_h3_dramc_vmstate = {

+ .name = "allwinner-h3-dramc",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),

+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),

+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = allwinner_h3_dramc_reset;

+ dc->vmsd = &allwinner_h3_dramc_vmstate;

+ dc->realize = allwinner_h3_dramc_realize;

+ device_class_set_props(dc, allwinner_h3_dramc_properties);

+}

+

+static const TypeInfo allwinner_h3_dramc_info = {

+ .name = TYPE_AW_H3_DRAMC,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_init = allwinner_h3_dramc_init,

+ .instance_size = sizeof(AwH3DramCtlState),

+ .class_init = allwinner_h3_dramc_class_init,

+};

+

+static void allwinner_h3_dramc_register(void)

+{

+ type_register_static(&allwinner_h3_dramc_info);

+}

+

+type_init(allwinner_h3_dramc_register)

diff --git a/hw/misc/trace-events b/hw/misc/trace-events

--- a/hw/misc/trace-events

+++ b/hw/misc/trace-events

@@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad

allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+# allwinner-h3-dramc.c

+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"

+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64

+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

+

# allwinner-sid.c

allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32

From: Igor Mammedov <imammedo@redhat.com>

SOC object returned by object_new() is leaked in current code.

Set SOC parent explicitly to board and then unref to SOC object

to make sure that refererence returned by object_new() is taken

care of.

The SOC object will be kept alive by its parent (machine) and

will be automatically freed when MachineState is destroyed.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>

Reported-by: Andrew Jones <drjones@redhat.com>

Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Message-id: 20200303091254.22373-1-imammedo@redhat.com

hw/arm/cubieboard.c | 3 +++

1 file changed, 3 insertions(+)

diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c

--- a/hw/arm/cubieboard.c

+++ b/hw/arm/cubieboard.c

@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)

}

a10 = AW_A10(object_new(TYPE_AW_A10));

+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),

+ &error_abort);

+ object_unref(OBJECT(a10));

object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);

if (err != NULL) {

From: Niek Linnenbank <nieklinnenbank@gmail.com>

The Clock Control Unit is responsible for clock signal generation,

configuration and distribution in the Allwinner H3 System on Chip.

This commit adds support for the Clock Control Unit which emulates

a simple read/write register interface.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com

hw/misc/Makefile.objs | 1 +

include/hw/arm/allwinner-h3.h | 3 +

include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++

hw/arm/allwinner-h3.c | 9 +-

hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++

5 files changed, 320 insertions(+), 1 deletion(-)

create mode 100644 include/hw/misc/allwinner-h3-ccu.h

create mode 100644 hw/misc/allwinner-h3-ccu.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/

common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o

+common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o

common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o

common-obj-$(CONFIG_NSERIES) += cbus.o

common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/allwinner-h3.h

+++ b/include/hw/arm/allwinner-h3.h

#include "hw/arm/boot.h"

#include "hw/timer/allwinner-a10-pit.h"

#include "hw/intc/arm_gic.h"

+#include "hw/misc/allwinner-h3-ccu.h"

#include "target/arm/cpu.h"

/**

@@ -XXX,XX +XXX,XX @@ enum {

AW_H3_SRAM_A1,

AW_H3_SRAM_A2,

AW_H3_SRAM_C,

+ AW_H3_CCU,

AW_H3_PIT,

AW_H3_UART0,

AW_H3_UART1,

@@ -XXX,XX +XXX,XX @@ typedef struct AwH3State {

ARMCPU cpus[AW_H3_NUM_CPUS];

const hwaddr *memmap;

AwA10PITState timer;

+ AwH3ClockCtlState ccu;

GICState gic;

MemoryRegion sram_a1;

MemoryRegion sram_a2;

diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/allwinner-h3-ccu.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Allwinner H3 Clock Control Unit emulation

+ *

+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>

+ *

+ * This program is free software: you can redistribute it and/or modify