[PATCH v5 00/60] target/riscv: support vector extension v0.7.1

LIU Zhiwei posted 60 patches 4 years, 2 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200312145900.2054-1-zhiwei_liu@c-sky.com
Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
There is a newer version of this series
target/riscv/Makefile.objs              |    2 +-
target/riscv/cpu.c                      |   49 +
target/riscv/cpu.h                      |   89 +-
target/riscv/cpu_bits.h                 |   15 +
target/riscv/csr.c                      |   75 +-
target/riscv/helper.h                   | 1075 +++++
target/riscv/insn32-64.decode           |   11 +
target/riscv/insn32.decode              |  366 ++
target/riscv/insn_trans/trans_rvv.inc.c | 2386 ++++++++++++
target/riscv/translate.c                |   24 +-
target/riscv/vector_helper.c            | 4745 +++++++++++++++++++++++
11 files changed, 8824 insertions(+), 13 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
[PATCH v5 00/60] target/riscv: support vector extension v0.7.1
Posted by LIU Zhiwei 4 years, 2 months ago
This patchset implements the vector extension for RISC-V on QEMU.

You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.

You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.

Features:
  * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
  * support basic vector extension.
  * support Zvlsseg.
  * support Zvamo.
  * not support Zvediv as it is changing.
  * SLEN always equals VLEN.
  * element width support 8bit, 16bit, 32bit, 64bit.

Changelog:
v5
  * fixup a bug in tb flags.
v4
  * no change
v3
  * move check code from execution-time to translation-time
  * use a continous memory block for vector register description.
  * vector registers as direct fields in RISCVCPUState.
  * support VLEN configure from qemu command line.
  * support ELEN configure from qemu command line.
  * support vector specification version configure from qemu command line.
  * probe pages before real load or store access.
  * use probe_page_check for no-fault operations in linux user mode.
  * generation atomic exit exception when in parallel environment.
  * fixup a lot of concrete bugs.

V2
  * use float16_compare{_quiet}
  * only use GETPC() in outer most helper
  * add ctx.ext_v Property


LIU Zhiwei (60):
  target/riscv: add vector extension field in CPURISCVState
  target/riscv: implementation-defined constant parameters
  target/riscv: support vector extension csr
  target/riscv: add vector configure instruction
  target/riscv: add vector stride load and store instructions
  target/riscv: add vector index load and store instructions
  target/riscv: add fault-only-first unit stride load
  target/riscv: add vector amo operations
  target/riscv: vector single-width integer add and subtract
  target/riscv: vector widening integer add and subtract
  target/riscv: vector integer add-with-carry / subtract-with-borrow
    instructions
  target/riscv: vector bitwise logical instructions
  target/riscv: vector single-width bit shift instructions
  target/riscv: vector narrowing integer right shift instructions
  target/riscv: vector integer comparison instructions
  target/riscv: vector integer min/max instructions
  target/riscv: vector single-width integer multiply instructions
  target/riscv: vector integer divide instructions
  target/riscv: vector widening integer multiply instructions
  target/riscv: vector single-width integer multiply-add instructions
  target/riscv: vector widening integer multiply-add instructions
  target/riscv: vector integer merge and move instructions
  target/riscv: vector single-width saturating add and subtract
  target/riscv: vector single-width averaging add and subtract
  target/riscv: vector single-width fractional multiply with rounding
    and saturation
  target/riscv: vector widening saturating scaled multiply-add
  target/riscv: vector single-width scaling shift instructions
  target/riscv: vector narrowing fixed-point clip instructions
  target/riscv: vector single-width floating-point add/subtract
    instructions
  target/riscv: vector widening floating-point add/subtract instructions
  target/riscv: vector single-width floating-point multiply/divide
    instructions
  target/riscv: vector widening floating-point multiply
  target/riscv: vector single-width floating-point fused multiply-add
    instructions
  target/riscv: vector widening floating-point fused multiply-add
    instructions
  target/riscv: vector floating-point square-root instruction
  target/riscv: vector floating-point min/max instructions
  target/riscv: vector floating-point sign-injection instructions
  target/riscv: vector floating-point compare instructions
  target/riscv: vector floating-point classify instructions
  target/riscv: vector floating-point merge instructions
  target/riscv: vector floating-point/integer type-convert instructions
  target/riscv: widening floating-point/integer type-convert
    instructions
  target/riscv: narrowing floating-point/integer type-convert
    instructions
  target/riscv: vector single-width integer reduction instructions
  target/riscv: vector wideing integer reduction instructions
  target/riscv: vector single-width floating-point reduction
    instructions
  target/riscv: vector widening floating-point reduction instructions
  target/riscv: vector mask-register logical instructions
  target/riscv: vector mask population count vmpopc
  target/riscv: vmfirst find-first-set mask bit
  target/riscv: set-X-first mask bit
  target/riscv: vector iota instruction
  target/riscv: vector element index instruction
  target/riscv: integer extract instruction
  target/riscv: integer scalar move instruction
  target/riscv: floating-point scalar move instructions
  target/riscv: vector slide instructions
  target/riscv: vector register gather instruction
  target/riscv: vector compress instruction
  target/riscv: configure and turn on vector extension from command line

 target/riscv/Makefile.objs              |    2 +-
 target/riscv/cpu.c                      |   49 +
 target/riscv/cpu.h                      |   89 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/csr.c                      |   75 +-
 target/riscv/helper.h                   | 1075 +++++
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  366 ++
 target/riscv/insn_trans/trans_rvv.inc.c | 2386 ++++++++++++
 target/riscv/translate.c                |   24 +-
 target/riscv/vector_helper.c            | 4745 +++++++++++++++++++++++
 11 files changed, 8824 insertions(+), 13 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/vector_helper.c

-- 
2.23.0


Re: [PATCH v5 00/60] target/riscv: support vector extension v0.7.1
Posted by no-reply@patchew.org 4 years, 2 months ago
Patchew URL: https://patchew.org/QEMU/20200312145900.2054-1-zhiwei_liu@c-sky.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v5 00/60] target/riscv: support vector extension v0.7.1
Message-id: 20200312145900.2054-1-zhiwei_liu@c-sky.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
375b545 target/riscv: configure and turn on vector extension from command line
1b21cbe target/riscv: vector compress instruction
f991525 target/riscv: vector register gather instruction
1e14e32 target/riscv: vector slide instructions
39f1497 target/riscv: floating-point scalar move instructions
2e66424 target/riscv: integer scalar move instruction
72404d7 target/riscv: integer extract instruction
3e441a9 target/riscv: vector element index instruction
0e8d18f target/riscv: vector iota instruction
5941891 target/riscv: set-X-first mask bit
1403c7e target/riscv: vmfirst find-first-set mask bit
3eba22e target/riscv: vector mask population count vmpopc
10809a8 target/riscv: vector mask-register logical instructions
b279b81 target/riscv: vector widening floating-point reduction instructions
6b1e85b target/riscv: vector single-width floating-point reduction instructions
ae44adc target/riscv: vector wideing integer reduction instructions
2f73f58 target/riscv: vector single-width integer reduction instructions
4ddb4e3 target/riscv: narrowing floating-point/integer type-convert instructions
ec3b1de target/riscv: widening floating-point/integer type-convert instructions
fc9abf9 target/riscv: vector floating-point/integer type-convert instructions
b3ae6d1 target/riscv: vector floating-point merge instructions
cb59558 target/riscv: vector floating-point classify instructions
1aa8c5b target/riscv: vector floating-point compare instructions
4b71902 target/riscv: vector floating-point sign-injection instructions
9a4bcd8 target/riscv: vector floating-point min/max instructions
8cefa5a target/riscv: vector floating-point square-root instruction
1dca724 target/riscv: vector widening floating-point fused multiply-add instructions
d730445 target/riscv: vector single-width floating-point fused multiply-add instructions
59e9d00 target/riscv: vector widening floating-point multiply
7728ab1 target/riscv: vector single-width floating-point multiply/divide instructions
db7a3eb target/riscv: vector widening floating-point add/subtract instructions
b74ee11 target/riscv: vector single-width floating-point add/subtract instructions
a6aed98 target/riscv: vector narrowing fixed-point clip instructions
41bff4f target/riscv: vector single-width scaling shift instructions
4e0735b target/riscv: vector widening saturating scaled multiply-add
7175350 target/riscv: vector single-width fractional multiply with rounding and saturation
866ade9 target/riscv: vector single-width averaging add and subtract
a10f893 target/riscv: vector single-width saturating add and subtract
b1968d2 target/riscv: vector integer merge and move instructions
b9a7f44 target/riscv: vector widening integer multiply-add instructions
9a490e5 target/riscv: vector single-width integer multiply-add instructions
24d1513 target/riscv: vector widening integer multiply instructions
4080b57 target/riscv: vector integer divide instructions
aafca3f target/riscv: vector single-width integer multiply instructions
386c472 target/riscv: vector integer min/max instructions
9586428 target/riscv: vector integer comparison instructions
615ad80 target/riscv: vector narrowing integer right shift instructions
2eb1e18 target/riscv: vector single-width bit shift instructions
047a1fa target/riscv: vector bitwise logical instructions
b403895 target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
8f2bc0b target/riscv: vector widening integer add and subtract
8f204ca target/riscv: vector single-width integer add and subtract
d5f58d7 target/riscv: add vector amo operations
29a0e0d target/riscv: add fault-only-first unit stride load
8166bfc target/riscv: add vector index load and store instructions
72f9f39 target/riscv: add vector stride load and store instructions
392ca2c target/riscv: add vector configure instruction
472b5e6 target/riscv: support vector extension csr
d172c56 target/riscv: implementation-defined constant parameters
73ee7eb target/riscv: add vector extension field in CPURISCVState

=== OUTPUT BEGIN ===
1/60 Checking commit 73ee7eb553fc (target/riscv: add vector extension field in CPURISCVState)
2/60 Checking commit d172c5624ac8 (target/riscv: implementation-defined constant parameters)
3/60 Checking commit 472b5e62cd77 (target/riscv: support vector extension csr)
4/60 Checking commit 392ca2c42910 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#158: 
new file mode 100644

total: 0 errors, 1 warnings, 284 lines checked

Patch 4/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/60 Checking commit 72f9f398f938 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#283: FILE: target/riscv/insn_trans/trans_rvv.inc.c:127:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

total: 1 errors, 0 warnings, 966 lines checked

Patch 5/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/60 Checking commit 8166bfc954b6 (target/riscv: add vector index load and store instructions)
7/60 Checking commit 29a0e0d6fbc3 (target/riscv: add fault-only-first unit stride load)
8/60 Checking commit d5f58d7a2231 (target/riscv: add vector amo operations)
9/60 Checking commit 8f204cad4cdc (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#87: FILE: target/riscv/insn_trans/trans_rvv.inc.c:739:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#98: FILE: target/riscv/insn_trans/trans_rvv.inc.c:750:
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
                                                    ^

total: 2 errors, 0 warnings, 399 lines checked

Patch 9/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/60 Checking commit 8f2bc0b5ecdc (target/riscv: vector widening integer add and subtract)
11/60 Checking commit b403895b2425 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#83: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1110:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#105: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1132:
+static bool opivv_vadc_check(DisasContext *s, arg_r *a)
                                                     ^

ERROR: spaces required around that '*' (ctx:WxV)
#120: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1147:
+static bool opivv_vmadc_check(DisasContext *s, arg_r *a)
                                                      ^

ERROR: spaces required around that '*' (ctx:WxV)
#133: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1160:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                      \
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#149: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1176:
+static bool opivx_vadc_check(DisasContext *s, arg_r *a)
                                                     ^

ERROR: spaces required around that '*' (ctx:WxV)
#159: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1186:
+static bool opivx_vmadc_check(DisasContext *s, arg_r *a)
                                                      ^

ERROR: spaces required around that '*' (ctx:WxV)
#170: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1197:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                      \
                                                 ^

total: 7 errors, 0 warnings, 312 lines checked

Patch 11/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

12/60 Checking commit 047a1fa32f47 (target/riscv: vector bitwise logical instructions)
13/60 Checking commit 2eb1e18e754d (target/riscv: vector single-width bit shift instructions)
14/60 Checking commit 615ad80f3f71 (target/riscv: vector narrowing integer right shift instructions)
15/60 Checking commit 9586428c962a (target/riscv: vector integer comparison instructions)
16/60 Checking commit 386c472368f0 (target/riscv: vector integer min/max instructions)
17/60 Checking commit aafca3f152fa (target/riscv: vector single-width integer multiply instructions)
18/60 Checking commit 4080b573cb2c (target/riscv: vector integer divide instructions)
19/60 Checking commit 24d15131325b (target/riscv: vector widening integer multiply instructions)
20/60 Checking commit 9a490e5f02a8 (target/riscv: vector single-width integer multiply-add instructions)
21/60 Checking commit b9a7f44e4b10 (target/riscv: vector widening integer multiply-add instructions)
22/60 Checking commit b1968d225be8 (target/riscv: vector integer merge and move instructions)
23/60 Checking commit a10f89334975 (target/riscv: vector single-width saturating add and subtract)
24/60 Checking commit 866ade991718 (target/riscv: vector single-width averaging add and subtract)
25/60 Checking commit 71753503b7bd (target/riscv: vector single-width fractional multiply with rounding and saturation)
26/60 Checking commit 4e0735b24caa (target/riscv: vector widening saturating scaled multiply-add)
27/60 Checking commit 41bff4f7fb9c (target/riscv: vector single-width scaling shift instructions)
28/60 Checking commit a6aed98d4490 (target/riscv: vector narrowing fixed-point clip instructions)
29/60 Checking commit b74ee1196c93 (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#249: FILE: target/riscv/vector_helper.c:3012:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 238 lines checked

Patch 29/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

30/60 Checking commit db7a3eb8d90a (target/riscv: vector widening floating-point add/subtract instructions)
31/60 Checking commit 7728ab1858dc (target/riscv: vector single-width floating-point multiply/divide instructions)
32/60 Checking commit 59e9d00e6557 (target/riscv: vector widening floating-point multiply)
33/60 Checking commit d7304457e529 (target/riscv: vector single-width floating-point fused multiply-add instructions)
34/60 Checking commit 1dca7240a1c4 (target/riscv: vector widening floating-point fused multiply-add instructions)
35/60 Checking commit 8cefa5a85791 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#65: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1844:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#75: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1854:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 111 lines checked

Patch 35/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

36/60 Checking commit 9a4bcd893d2b (target/riscv: vector floating-point min/max instructions)
37/60 Checking commit 4b7190263384 (target/riscv: vector floating-point sign-injection instructions)
38/60 Checking commit 1aa8c5ba7f17 (target/riscv: vector floating-point compare instructions)
39/60 Checking commit cb595588a5aa (target/riscv: vector floating-point classify instructions)
40/60 Checking commit b3ae6d1de7d2 (target/riscv: vector floating-point merge instructions)
41/60 Checking commit fc9abf966c74 (target/riscv: vector floating-point/integer type-convert instructions)
42/60 Checking commit ec3b1dee93bb (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#60: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1949:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1961:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 118 lines checked

Patch 42/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

43/60 Checking commit 4ddb4e380116 (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#60: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1991:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2003:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 115 lines checked

Patch 43/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

44/60 Checking commit 2f73f581cd8f (target/riscv: vector single-width integer reduction instructions)
45/60 Checking commit ae44adc808a4 (target/riscv: vector wideing integer reduction instructions)
46/60 Checking commit 6b1e85bd5bf9 (target/riscv: vector single-width floating-point reduction instructions)
47/60 Checking commit b279b81d260f (target/riscv: vector widening floating-point reduction instructions)
48/60 Checking commit 10809a8f183e (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#60: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2061:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

ERROR: "foo * bar" should be "foo *bar"
#64: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2065:
+        gen_helper_gvec_4_ptr * fn = gen_helper_##NAME;            \

total: 2 errors, 0 warnings, 100 lines checked

Patch 48/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

49/60 Checking commit 3eba22ed5b2f (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#42: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2085:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 49/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

50/60 Checking commit 1403c7eebe82 (target/riscv: vmfirst find-first-set mask bit)
ERROR: suspect code indent for conditional statements (12, 15)
#92: FILE: target/riscv/vector_helper.c:4313:
+            if (vext_elem_mask(vs2, mlen, i)) {
+               return i;

total: 1 errors, 0 warnings, 69 lines checked

Patch 50/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

51/60 Checking commit 5941891e02bf (target/riscv: set-X-first mask bit)
ERROR: "foo * bar" should be "foo *bar"
#53: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2156:
+        gen_helper_gvec_3_ptr * fn = gen_helper_##NAME;            \

total: 1 errors, 0 warnings, 111 lines checked

Patch 51/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

52/60 Checking commit 0e8d18f00c74 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#45: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2172:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 74 lines checked

Patch 52/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

53/60 Checking commit 3e441a993c10 (target/riscv: vector element index instruction)
54/60 Checking commit 72404d73d06a (target/riscv: integer extract instruction)
ERROR: space prohibited after that '*' (ctx:BxW)
#48: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2218:
+typedef void (* gen_helper_vext_x_v)(TCGv, TCGv_ptr, TCGv, TCGv_env);
               ^

total: 1 errors, 0 warnings, 74 lines checked

Patch 54/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

55/60 Checking commit 2e66424902bf (target/riscv: integer scalar move instruction)
ERROR: space prohibited after that '*' (ctx:BxW)
#45: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2248:
+typedef void (* gen_helper_vmv_s_x)(TCGv_ptr, TCGv, TCGv_env);
               ^

total: 1 errors, 0 warnings, 62 lines checked

Patch 55/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

56/60 Checking commit 39f1497df9c9 (target/riscv: floating-point scalar move instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#50: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2274:
+typedef void (* gen_helper_vfmv_f_s)(TCGv_i64, TCGv_ptr, TCGv_env);
               ^

ERROR: space prohibited after that '*' (ctx:BxW)
#71: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2295:
+typedef void (* gen_helper_vfmv_s_f)(TCGv_ptr, TCGv_i64, TCGv_env);
               ^

total: 2 errors, 0 warnings, 109 lines checked

Patch 56/60 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

57/60 Checking commit 1e14e32ecd73 (target/riscv: vector slide instructions)
58/60 Checking commit f991525dafb5 (target/riscv: vector register gather instruction)
59/60 Checking commit 1b21cbeba68f (target/riscv: vector compress instruction)
60/60 Checking commit 375b5454f423 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200312145900.2054-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
Re: [PATCH v5 35/60] target/riscv: vector floating-point square-root instruction
Posted by Richard Henderson 4 years, 2 months ago
[ Patch didn't make it to the list, so reviewing

https://github.com/romanheros/qemu/commit/c77bef489c5517951077679ec9228438d05f1e1a
]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v5 51/60] target/riscv: set-X-first mask bit
Posted by Richard Henderson 4 years, 2 months ago
[ Patch didn't make it to the list, so reviewing

https://github.com/romanheros/qemu/commit/60668e86d94ffa48adb2f9c346753cf77f582686
]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

It should be possible to rewrite the helpers in units of uint64_t.  The
unmasked path is easy; the masked path is more complicated.


r~

Re: [PATCH v5 59/60] target/riscv: vector compress instruction
Posted by Richard Henderson 4 years, 2 months ago
[ The patch didn't make it to the list, so reviewing

https://github.com/romanheros/qemu/commit/f46b8c8bbbf0acd78746a49fe712306d7c05c7e6
]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~