1 | Nothing much exciting here, but it's 37 patches worth... | 1 | A largish pullreq but it's almost all docs fixes. |
---|---|---|---|
2 | 2 | ||
3 | thanks | ||
4 | -- PMM | 3 | -- PMM |
5 | 4 | ||
6 | The following changes since commit e64a62df378a746c0b257105959613c9f8122e59: | 5 | The following changes since commit 10a3c4a4b3e14208cfed274514d1911e5230935f: |
7 | 6 | ||
8 | Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-040320-1' into staging (2020-03-05 12:13:51 +0000) | 7 | Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-08-02 09:47:07 +0100) |
9 | 8 | ||
10 | are available in the Git repository at: | 9 | are available in the Git repository at: |
11 | 10 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200305 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210802 |
13 | 12 | ||
14 | for you to fetch changes up to 597d61a3b1f94c53a3aaa77671697c0c5f797dbf: | 13 | for you to fetch changes up to 4a64939db76b10d8d41d2af3c6aad8142da55450: |
15 | 14 | ||
16 | target/arm: Clean address for DC ZVA (2020-03-05 16:09:21 +0000) | 15 | docs: Move user-facing barrier docs into system manual (2021-08-02 12:55:51 +0100) |
17 | 16 | ||
18 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
19 | * versal: Implement ADMA | 18 | target-arm queue: |
20 | * Implement (trivially) ARMv8.2-TTCNP | 19 | * Add documentation of Arm 'mainstone', 'kzm', 'imx25-pdk' boards |
21 | * hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus | 20 | * MAINTAINERS: Don't list Andrzej Zaborowski for various components |
22 | * Remove unnecessary endianness-handling on some boards | 21 | * docs: Remove stale TODO comments about license and version |
23 | * Avoid minor memory leaks from timer_new in some devices | 22 | * docs: Move licence/copyright from HTML output to rST comments |
24 | * Honour more of the HCR_EL2 trap bits | 23 | * docs: Format literal text correctly |
25 | * Complain rather than ignoring bad command line options for cubieboard | 24 | * hw/arm/boot: Report error if there is no fw_cfg device in the machine |
26 | * Honour TBI for DC ZVA and exception return | 25 | * docs: rSTify barrier.txt and bootindex.txt |
27 | 26 | ||
28 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
29 | Edgar E. Iglesias (2): | 28 | Peter Maydell (21): |
30 | hw/arm: versal: Add support for the LPD ADMAs | 29 | docs: Add documentation of Arm 'mainstone' board |
31 | hw/arm: versal: Generate xlnx-versal-virt zdma FDT nodes | 30 | docs: Add documentation of Arm 'kzm' board |
31 | docs: Add documentation of Arm 'imx25-pdk' board | ||
32 | MAINTAINERS: Don't list Andrzej Zaborowski for various components | ||
33 | docs: Remove stale TODO comments about license and version | ||
34 | docs: Move licence/copyright from HTML output to rST comments | ||
35 | docs/devel/build-system.rst: Format literals correctly | ||
36 | docs/devel/build-system.rst: Correct typo in example code | ||
37 | docs/devel/ebpf_rss.rst: Format literals correctly | ||
38 | docs/devel/migration.rst: Format literals correctly | ||
39 | docs/devel: Format literals correctly | ||
40 | docs/system/s390x/protvirt.rst: Format literals correctly | ||
41 | docs/system/arm/cpu-features.rst: Format literals correctly | ||
42 | docs: Format literals correctly | ||
43 | docs/about/removed-features: Fix markup error | ||
44 | docs/tools/virtiofsd.rst: Delete stray backtick | ||
45 | hw/arm/boot: Report error if there is no fw_cfg device in the machine | ||
46 | docs: Move bootindex.txt into system section and rstify | ||
47 | docs: Move the protocol part of barrier.txt into interop | ||
48 | ui/input-barrier: Move TODOs from barrier.txt to a comment | ||
49 | docs: Move user-facing barrier docs into system manual | ||
32 | 50 | ||
33 | Eric Auger (1): | 51 | docs/about/index.rst | 2 +- |
34 | hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus | 52 | docs/about/removed-features.rst | 2 +- |
53 | docs/barrier.txt | 370 ----------------------- | ||
54 | docs/bootindex.txt | 52 ---- | ||
55 | docs/devel/build-system.rst | 160 +++++----- | ||
56 | docs/devel/ebpf_rss.rst | 18 +- | ||
57 | docs/devel/migration.rst | 36 +-- | ||
58 | docs/devel/qgraph.rst | 8 +- | ||
59 | docs/devel/tcg-plugins.rst | 14 +- | ||
60 | docs/devel/testing.rst | 8 +- | ||
61 | docs/interop/barrier.rst | 426 +++++++++++++++++++++++++++ | ||
62 | docs/interop/index.rst | 1 + | ||
63 | docs/interop/live-block-operations.rst | 2 +- | ||
64 | docs/interop/qemu-ga-ref.rst | 9 - | ||
65 | docs/interop/qemu-qmp-ref.rst | 9 - | ||
66 | docs/interop/qemu-storage-daemon-qmp-ref.rst | 9 - | ||
67 | docs/interop/vhost-user-gpu.rst | 7 +- | ||
68 | docs/interop/vhost-user.rst | 12 +- | ||
69 | docs/system/arm/cpu-features.rst | 116 ++++---- | ||
70 | docs/system/arm/imx25-pdk.rst | 19 ++ | ||
71 | docs/system/arm/kzm.rst | 18 ++ | ||
72 | docs/system/arm/mainstone.rst | 25 ++ | ||
73 | docs/system/arm/nuvoton.rst | 2 +- | ||
74 | docs/system/arm/sbsa.rst | 4 +- | ||
75 | docs/system/arm/virt.rst | 2 +- | ||
76 | docs/system/barrier.rst | 44 +++ | ||
77 | docs/system/bootindex.rst | 76 +++++ | ||
78 | docs/system/cpu-hotplug.rst | 2 +- | ||
79 | docs/system/generic-loader.rst | 4 +- | ||
80 | docs/system/guest-loader.rst | 6 +- | ||
81 | docs/system/index.rst | 2 + | ||
82 | docs/system/ppc/powernv.rst | 8 +- | ||
83 | docs/system/riscv/microchip-icicle-kit.rst | 2 +- | ||
84 | docs/system/riscv/virt.rst | 2 +- | ||
85 | docs/system/s390x/protvirt.rst | 12 +- | ||
86 | docs/system/target-arm.rst | 3 + | ||
87 | docs/tools/virtiofsd.rst | 2 +- | ||
88 | hw/arm/boot.c | 9 + | ||
89 | hw/arm/sbsa-ref.c | 7 - | ||
90 | ui/input-barrier.c | 5 + | ||
91 | MAINTAINERS | 8 +- | ||
92 | 41 files changed, 849 insertions(+), 674 deletions(-) | ||
93 | delete mode 100644 docs/barrier.txt | ||
94 | delete mode 100644 docs/bootindex.txt | ||
95 | create mode 100644 docs/interop/barrier.rst | ||
96 | create mode 100644 docs/system/arm/imx25-pdk.rst | ||
97 | create mode 100644 docs/system/arm/kzm.rst | ||
98 | create mode 100644 docs/system/arm/mainstone.rst | ||
99 | create mode 100644 docs/system/barrier.rst | ||
100 | create mode 100644 docs/system/bootindex.rst | ||
35 | 101 | ||
36 | Niek Linnenbank (4): | ||
37 | hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition | ||
38 | hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8 | ||
39 | hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB | ||
40 | hw/arm/cubieboard: report error when using unsupported -bios argument | ||
41 | |||
42 | Pan Nengyuan (4): | ||
43 | hw/arm/pxa2xx: move timer_new from init() into realize() to avoid memleaks | ||
44 | hw/arm/spitz: move timer_new from init() into realize() to avoid memleaks | ||
45 | hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks | ||
46 | hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks | ||
47 | |||
48 | Peter Maydell (1): | ||
49 | target/arm: Implement (trivially) ARMv8.2-TTCNP | ||
50 | |||
51 | Philippe Mathieu-Daudé (6): | ||
52 | hw/arm/smmu-common: Simplify smmu_find_smmu_pcibus() logic | ||
53 | hw/arm/gumstix: Simplify since the machines are little-endian only | ||
54 | hw/arm/mainstone: Simplify since the machines are little-endian only | ||
55 | hw/arm/omap_sx1: Simplify since the machines are little-endian only | ||
56 | hw/arm/z2: Simplify since the machines are little-endian only | ||
57 | hw/arm/musicpal: Simplify since the machines are little-endian only | ||
58 | |||
59 | Richard Henderson (19): | ||
60 | target/arm: Improve masking of HCR/HCR2 RES0 bits | ||
61 | target/arm: Add HCR_EL2 bit definitions from ARMv8.6 | ||
62 | target/arm: Disable has_el2 and has_el3 for user-only | ||
63 | target/arm: Remove EL2 and EL3 setup from user-only | ||
64 | target/arm: Improve masking in arm_hcr_el2_eff | ||
65 | target/arm: Honor the HCR_EL2.{TVM,TRVM} bits | ||
66 | target/arm: Honor the HCR_EL2.TSW bit | ||
67 | target/arm: Honor the HCR_EL2.TACR bit | ||
68 | target/arm: Honor the HCR_EL2.TPCP bit | ||
69 | target/arm: Honor the HCR_EL2.TPU bit | ||
70 | target/arm: Honor the HCR_EL2.TTLB bit | ||
71 | tests/tcg/aarch64: Add newline in pauth-1 printf | ||
72 | target/arm: Replicate TBI/TBID bits for single range regimes | ||
73 | target/arm: Optimize cpu_mmu_index | ||
74 | target/arm: Introduce core_to_aa64_mmu_idx | ||
75 | target/arm: Apply TBI to ESR_ELx in helper_exception_return | ||
76 | target/arm: Move helper_dc_zva to helper-a64.c | ||
77 | target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva | ||
78 | target/arm: Clean address for DC ZVA | ||
79 | |||
80 | include/hw/arm/xlnx-versal.h | 6 + | ||
81 | target/arm/cpu.h | 30 ++-- | ||
82 | target/arm/helper-a64.h | 1 + | ||
83 | target/arm/helper.h | 1 - | ||
84 | target/arm/internals.h | 6 + | ||
85 | hw/arm/cubieboard.c | 29 +++- | ||
86 | hw/arm/gumstix.c | 16 +- | ||
87 | hw/arm/mainstone.c | 8 +- | ||
88 | hw/arm/musicpal.c | 10 -- | ||
89 | hw/arm/omap_sx1.c | 11 +- | ||
90 | hw/arm/pxa2xx.c | 17 +- | ||
91 | hw/arm/smmu-common.c | 20 +-- | ||
92 | hw/arm/spitz.c | 8 +- | ||
93 | hw/arm/strongarm.c | 18 ++- | ||
94 | hw/arm/xlnx-versal-virt.c | 28 ++++ | ||
95 | hw/arm/xlnx-versal.c | 24 +++ | ||
96 | hw/arm/z2.c | 8 +- | ||
97 | hw/timer/cadence_ttc.c | 18 ++- | ||
98 | target/arm/cpu.c | 13 +- | ||
99 | target/arm/cpu64.c | 2 + | ||
100 | target/arm/helper-a64.c | 114 ++++++++++++- | ||
101 | target/arm/helper.c | 373 ++++++++++++++++++++++++++++++------------- | ||
102 | target/arm/op_helper.c | 93 ----------- | ||
103 | target/arm/translate-a64.c | 4 +- | ||
104 | tests/tcg/aarch64/pauth-1.c | 2 +- | ||
105 | 25 files changed, 551 insertions(+), 309 deletions(-) | ||
106 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Add brief documentation of the Arm 'mainstone' board. |
---|---|---|---|
2 | 2 | ||
3 | This data access was forgotten when we added support for cleaning | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | addresses of TBI information. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20210722175229.29065-2-peter.maydell@linaro.org | ||
6 | --- | ||
7 | docs/system/arm/mainstone.rst | 25 +++++++++++++++++++++++++ | ||
8 | docs/system/target-arm.rst | 1 + | ||
9 | MAINTAINERS | 1 + | ||
10 | 3 files changed, 27 insertions(+) | ||
11 | create mode 100644 docs/system/arm/mainstone.rst | ||
5 | 12 | ||
6 | Fixes: 3a471103ac1823ba | 13 | diff --git a/docs/system/arm/mainstone.rst b/docs/system/arm/mainstone.rst |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | new file mode 100644 |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 15 | index XXXXXXX..XXXXXXX |
9 | Message-id: 20200302175829.2183-8-richard.henderson@linaro.org | 16 | --- /dev/null |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | +++ b/docs/system/arm/mainstone.rst |
11 | --- | 18 | @@ -XXX,XX +XXX,XX @@ |
12 | target/arm/translate-a64.c | 2 +- | 19 | +Intel Mainstone II board (``mainstone``) |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 20 | +======================================== |
14 | 21 | + | |
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 22 | +The ``mainstone`` board emulates the Intel Mainstone II development |
23 | +board, which uses a PXA270 CPU. | ||
24 | + | ||
25 | +Emulated devices: | ||
26 | + | ||
27 | +- Flash memory | ||
28 | +- Keypad | ||
29 | +- MMC controller | ||
30 | +- 91C111 ethernet | ||
31 | +- PIC | ||
32 | +- Timer | ||
33 | +- DMA | ||
34 | +- GPIO | ||
35 | +- FIR | ||
36 | +- Serial | ||
37 | +- LCD controller | ||
38 | +- SSP | ||
39 | +- USB controller | ||
40 | +- RTC | ||
41 | +- PCMCIA | ||
42 | +- I2C | ||
43 | +- I2S | ||
44 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
16 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 46 | --- a/docs/system/target-arm.rst |
18 | +++ b/target/arm/translate-a64.c | 47 | +++ b/docs/system/target-arm.rst |
19 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | 48 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
20 | return; | 49 | arm/highbank |
21 | case ARM_CP_DC_ZVA: | 50 | arm/musicpal |
22 | /* Writes clear the aligned block of memory which rt points into. */ | 51 | arm/gumstix |
23 | - tcg_rt = cpu_reg(s, rt); | 52 | + arm/mainstone |
24 | + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); | 53 | arm/nrf |
25 | gen_helper_dc_zva(cpu_env, tcg_rt); | 54 | arm/nseries |
26 | return; | 55 | arm/nuvoton |
27 | default: | 56 | diff --git a/MAINTAINERS b/MAINTAINERS |
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/MAINTAINERS | ||
59 | +++ b/MAINTAINERS | ||
60 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/pxa.h | ||
61 | F: include/hw/arm/sharpsl.h | ||
62 | F: include/hw/display/tc6393xb.h | ||
63 | F: docs/system/arm/xscale.rst | ||
64 | +F: docs/system/arm/mainstone.rst | ||
65 | |||
66 | SABRELITE / i.MX6 | ||
67 | M: Peter Maydell <peter.maydell@linaro.org> | ||
28 | -- | 68 | -- |
29 | 2.20.1 | 69 | 2.20.1 |
30 | 70 | ||
31 | 71 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Add brief documentation of the Arm 'kzm' board. |
---|---|---|---|
2 | 2 | ||
3 | The function does not write registers, and only reads them by | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | implication via the exception path. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20210722175229.29065-3-peter.maydell@linaro.org | ||
6 | --- | ||
7 | docs/system/arm/kzm.rst | 18 ++++++++++++++++++ | ||
8 | docs/system/target-arm.rst | 1 + | ||
9 | MAINTAINERS | 1 + | ||
10 | 3 files changed, 20 insertions(+) | ||
11 | create mode 100644 docs/system/arm/kzm.rst | ||
5 | 12 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | diff --git a/docs/system/arm/kzm.rst b/docs/system/arm/kzm.rst |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | new file mode 100644 |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 15 | index XXXXXXX..XXXXXXX |
9 | Message-id: 20200302175829.2183-7-richard.henderson@linaro.org | 16 | --- /dev/null |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | +++ b/docs/system/arm/kzm.rst |
11 | --- | 18 | @@ -XXX,XX +XXX,XX @@ |
12 | target/arm/helper-a64.h | 2 +- | 19 | +Kyoto Microcomputer KZM-ARM11-01 (``kzm``) |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 20 | +========================================== |
14 | 21 | + | |
15 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | 22 | +The ``kzm`` board emulates the Kyoto Microcomputer KZM-ARM11-01 |
23 | +evaluation board, which is based on an NXP i.MX32 SoC | ||
24 | +which uses an ARM1136 CPU. | ||
25 | + | ||
26 | +Emulated devices: | ||
27 | + | ||
28 | +- UARTs | ||
29 | +- LAN9118 ethernet | ||
30 | +- AVIC | ||
31 | +- CCM | ||
32 | +- GPT | ||
33 | +- EPIT timers | ||
34 | +- I2C | ||
35 | +- GPIO controllers | ||
36 | +- Watchdog timer | ||
37 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
16 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-a64.h | 39 | --- a/docs/system/target-arm.rst |
18 | +++ b/target/arm/helper-a64.h | 40 | +++ b/docs/system/target-arm.rst |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) | 41 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
20 | DEF_HELPER_2(sqrt_f16, f16, f16, ptr) | 42 | arm/musicpal |
21 | 43 | arm/gumstix | |
22 | DEF_HELPER_2(exception_return, void, env, i64) | 44 | arm/mainstone |
23 | -DEF_HELPER_2(dc_zva, void, env, i64) | 45 | + arm/kzm |
24 | +DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64) | 46 | arm/nrf |
25 | 47 | arm/nseries | |
26 | DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) | 48 | arm/nuvoton |
27 | DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) | 49 | diff --git a/MAINTAINERS b/MAINTAINERS |
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/MAINTAINERS | ||
52 | +++ b/MAINTAINERS | ||
53 | @@ -XXX,XX +XXX,XX @@ F: hw/*/imx_* | ||
54 | F: hw/*/*imx31* | ||
55 | F: include/hw/*/imx_* | ||
56 | F: include/hw/*/*imx31* | ||
57 | +F: docs/system/arm/kzm.rst | ||
58 | |||
59 | Integrator CP | ||
60 | M: Peter Maydell <peter.maydell@linaro.org> | ||
28 | -- | 61 | -- |
29 | 2.20.1 | 62 | 2.20.1 |
30 | 63 | ||
31 | 64 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Add brief documentation of the Arm 'imx25-pdk' board. |
---|---|---|---|
2 | 2 | ||
3 | We missed this case within AArch64.ExceptionReturn. | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210722175229.29065-4-peter.maydell@linaro.org | ||
6 | --- | ||
7 | docs/system/arm/imx25-pdk.rst | 19 +++++++++++++++++++ | ||
8 | docs/system/target-arm.rst | 1 + | ||
9 | MAINTAINERS | 1 + | ||
10 | 3 files changed, 21 insertions(+) | ||
11 | create mode 100644 docs/system/arm/imx25-pdk.rst | ||
4 | 12 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | diff --git a/docs/system/arm/imx25-pdk.rst b/docs/system/arm/imx25-pdk.rst |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | new file mode 100644 |
7 | Message-id: 20200302175829.2183-5-richard.henderson@linaro.org | 15 | index XXXXXXX..XXXXXXX |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | --- /dev/null |
9 | --- | 17 | +++ b/docs/system/arm/imx25-pdk.rst |
10 | target/arm/helper-a64.c | 23 ++++++++++++++++++++++- | 18 | @@ -XXX,XX +XXX,XX @@ |
11 | 1 file changed, 22 insertions(+), 1 deletion(-) | 19 | +NXP i.MX25 PDK board (``imx25-pdk``) |
12 | 20 | +==================================== | |
13 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | 21 | + |
22 | +The ``imx25-pdk`` board emulates the NXP i.MX25 Product Development Kit | ||
23 | +board, which is based on an i.MX25 SoC which uses an ARM926 CPU. | ||
24 | + | ||
25 | +Emulated devices: | ||
26 | + | ||
27 | +- SD controller | ||
28 | +- AVIC | ||
29 | +- CCM | ||
30 | +- GPT | ||
31 | +- EPIT timers | ||
32 | +- FEC | ||
33 | +- RNGC | ||
34 | +- I2C | ||
35 | +- GPIO controllers | ||
36 | +- Watchdog timer | ||
37 | +- USB controllers | ||
38 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
14 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper-a64.c | 40 | --- a/docs/system/target-arm.rst |
16 | +++ b/target/arm/helper-a64.c | 41 | +++ b/docs/system/target-arm.rst |
17 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) | 42 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
18 | "AArch32 EL%d PC 0x%" PRIx32 "\n", | 43 | arm/nrf |
19 | cur_el, new_el, env->regs[15]); | 44 | arm/nseries |
20 | } else { | 45 | arm/nuvoton |
21 | + int tbii; | 46 | + arm/imx25-pdk |
22 | + | 47 | arm/orangepi |
23 | env->aarch64 = 1; | 48 | arm/palm |
24 | spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); | 49 | arm/raspi |
25 | pstate_write(env, spsr); | 50 | diff --git a/MAINTAINERS b/MAINTAINERS |
26 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) | 51 | index XXXXXXX..XXXXXXX 100644 |
27 | env->pstate &= ~PSTATE_SS; | 52 | --- a/MAINTAINERS |
28 | } | 53 | +++ b/MAINTAINERS |
29 | aarch64_restore_sp(env, new_el); | 54 | @@ -XXX,XX +XXX,XX @@ F: hw/watchdog/wdt_imx2.c |
30 | - env->pc = new_pc; | 55 | F: include/hw/arm/fsl-imx25.h |
31 | helper_rebuild_hflags_a64(env, new_el); | 56 | F: include/hw/misc/imx25_ccm.h |
32 | + | 57 | F: include/hw/watchdog/wdt_imx2.h |
33 | + /* | 58 | +F: docs/system/arm/imx25-pdk.rst |
34 | + * Apply TBI to the exception return address. We had to delay this | 59 | |
35 | + * until after we selected the new EL, so that we could select the | 60 | i.MX31 (kzm) |
36 | + * correct TBI+TBID bits. This is made easier by waiting until after | 61 | M: Peter Maydell <peter.maydell@linaro.org> |
37 | + * the hflags rebuild, since we can pull the composite TBII field | ||
38 | + * from there. | ||
39 | + */ | ||
40 | + tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII); | ||
41 | + if ((tbii >> extract64(new_pc, 55, 1)) & 1) { | ||
42 | + /* TBI is enabled. */ | ||
43 | + int core_mmu_idx = cpu_mmu_index(env, false); | ||
44 | + if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { | ||
45 | + new_pc = sextract64(new_pc, 0, 56); | ||
46 | + } else { | ||
47 | + new_pc = extract64(new_pc, 0, 56); | ||
48 | + } | ||
49 | + } | ||
50 | + env->pc = new_pc; | ||
51 | + | ||
52 | qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " | ||
53 | "AArch64 EL%d PC 0x%" PRIx64 "\n", | ||
54 | cur_el, new_el, env->pc); | ||
55 | -- | 62 | -- |
56 | 2.20.1 | 63 | 2.20.1 |
57 | 64 | ||
58 | 65 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Andrzej Zaborowski is listed as an "Odd Fixes" maintainer for the |
---|---|---|---|
2 | nSeries, Palm and PXA2XX boards, as well as the "Maintained" status | ||
3 | Arm 32-bit TCG backend. | ||
2 | 4 | ||
3 | If by context we know that we're in AArch64 mode, we need not | 5 | Andrzej's last email to qemu-devel was back in 2017, and the email |
4 | test for M-profile when reconstructing the full ARMMMUIdx. | 6 | before that was all the way back in 2013. We don't really need to |
7 | fill his email up with CCs on QEMU patches any more... | ||
5 | 8 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Remove Andrzej from the various boards sections (leaving them still |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Odd Fixes with me as the backup patch reviewer). Add Richard |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Henderson as the maintainer for the Arm TCG backend, since removing |
9 | Message-id: 20200302175829.2183-4-richard.henderson@linaro.org | 12 | Andrzej would otherwise leave that section with no M: line at all. |
13 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 20210722180951.29802-1-peter.maydell@linaro.org | ||
11 | --- | 17 | --- |
12 | target/arm/internals.h | 6 ++++++ | 18 | MAINTAINERS | 5 +---- |
13 | target/arm/translate-a64.c | 2 +- | 19 | 1 file changed, 1 insertion(+), 4 deletions(-) |
14 | 2 files changed, 7 insertions(+), 1 deletion(-) | ||
15 | 20 | ||
16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 21 | diff --git a/MAINTAINERS b/MAINTAINERS |
17 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/internals.h | 23 | --- a/MAINTAINERS |
19 | +++ b/target/arm/internals.h | 24 | +++ b/MAINTAINERS |
20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) | 25 | @@ -XXX,XX +XXX,XX @@ F: roms/vbootrom |
21 | } | 26 | F: docs/system/arm/nuvoton.rst |
22 | } | 27 | |
23 | 28 | nSeries | |
24 | +static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) | 29 | -M: Andrzej Zaborowski <balrogg@gmail.com> |
25 | +{ | 30 | M: Peter Maydell <peter.maydell@linaro.org> |
26 | + /* AArch64 is always a-profile. */ | 31 | L: qemu-arm@nongnu.org |
27 | + return mmu_idx | ARM_MMU_IDX_A; | 32 | S: Odd Fixes |
28 | +} | 33 | @@ -XXX,XX +XXX,XX @@ F: tests/acceptance/machine_arm_n8x0.py |
29 | + | 34 | F: docs/system/arm/nseries.rst |
30 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); | 35 | |
31 | 36 | Palm | |
32 | /* | 37 | -M: Andrzej Zaborowski <balrogg@gmail.com> |
33 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 38 | M: Peter Maydell <peter.maydell@linaro.org> |
34 | index XXXXXXX..XXXXXXX 100644 | 39 | L: qemu-arm@nongnu.org |
35 | --- a/target/arm/translate-a64.c | 40 | S: Odd Fixes |
36 | +++ b/target/arm/translate-a64.c | 41 | @@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h |
37 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | 42 | F: docs/system/arm/realview.rst |
38 | dc->condexec_mask = 0; | 43 | |
39 | dc->condexec_cond = 0; | 44 | PXA2XX |
40 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); | 45 | -M: Andrzej Zaborowski <balrogg@gmail.com> |
41 | - dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); | 46 | M: Peter Maydell <peter.maydell@linaro.org> |
42 | + dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); | 47 | L: qemu-arm@nongnu.org |
43 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); | 48 | S: Odd Fixes |
44 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); | 49 | @@ -XXX,XX +XXX,XX @@ F: disas/arm-a64.cc |
45 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); | 50 | F: disas/libvixl/ |
51 | |||
52 | ARM TCG target | ||
53 | -M: Andrzej Zaborowski <balrogg@gmail.com> | ||
54 | +M: Richard Henderson <richard.henderson@linaro.org> | ||
55 | S: Maintained | ||
56 | L: qemu-arm@nongnu.org | ||
57 | F: tcg/arm/ | ||
46 | -- | 58 | -- |
47 | 2.20.1 | 59 | 2.20.1 |
48 | 60 | ||
49 | 61 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Since commits 13f934e79fa and 3a50c8f3067aaf, our HTML docs include a |
---|---|---|---|
2 | footer to all pages stating the license and version. We can | ||
3 | therefore delete the TODO comments suggesting we should do that from | ||
4 | our .rst files. | ||
2 | 5 | ||
3 | Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | we can unconditionally use pointer bit 55 to index into our | 7 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
5 | composite TBI1:TBI0 field. | 8 | Reviewed-by: Cleber Rosa <crosa@redhat.com> |
9 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
10 | Message-id: 20210722192016.24915-2-peter.maydell@linaro.org | ||
11 | --- | ||
12 | docs/interop/qemu-ga-ref.rst | 9 --------- | ||
13 | docs/interop/qemu-qmp-ref.rst | 9 --------- | ||
14 | docs/interop/qemu-storage-daemon-qmp-ref.rst | 9 --------- | ||
15 | 3 files changed, 27 deletions(-) | ||
6 | 16 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | diff --git a/docs/interop/qemu-ga-ref.rst b/docs/interop/qemu-ga-ref.rst |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Message-id: 20200302175829.2183-2-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/helper.c | 6 ++++-- | ||
14 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper.c | 19 | --- a/docs/interop/qemu-ga-ref.rst |
19 | +++ b/target/arm/helper.c | 20 | +++ b/docs/interop/qemu-ga-ref.rst |
20 | @@ -XXX,XX +XXX,XX @@ static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) | 21 | @@ -XXX,XX +XXX,XX @@ |
21 | } else if (mmu_idx == ARMMMUIdx_Stage2) { | 22 | QEMU Guest Agent Protocol Reference |
22 | return 0; /* VTCR_EL2 */ | 23 | =================================== |
23 | } else { | 24 | |
24 | - return extract32(tcr, 20, 1); | 25 | -.. |
25 | + /* Replicate the single TBI bit so we always have 2 bits. */ | 26 | - TODO: the old Texinfo manual used to note that this manual |
26 | + return extract32(tcr, 20, 1) * 3; | 27 | - is GPL-v2-or-later. We should make that reader-visible |
27 | } | 28 | - both here and in our Sphinx manuals more generally. |
28 | } | 29 | - |
29 | 30 | -.. | |
30 | @@ -XXX,XX +XXX,XX @@ static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) | 31 | - TODO: display the QEMU version, both here and in our Sphinx manuals |
31 | } else if (mmu_idx == ARMMMUIdx_Stage2) { | 32 | - more generally. |
32 | return 0; /* VTCR_EL2 */ | 33 | - |
33 | } else { | 34 | .. contents:: |
34 | - return extract32(tcr, 29, 1); | 35 | :depth: 3 |
35 | + /* Replicate the single TBID bit so we always have 2 bits. */ | 36 | |
36 | + return extract32(tcr, 29, 1) * 3; | 37 | diff --git a/docs/interop/qemu-qmp-ref.rst b/docs/interop/qemu-qmp-ref.rst |
37 | } | 38 | index XXXXXXX..XXXXXXX 100644 |
38 | } | 39 | --- a/docs/interop/qemu-qmp-ref.rst |
40 | +++ b/docs/interop/qemu-qmp-ref.rst | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | QEMU QMP Reference Manual | ||
43 | ========================= | ||
44 | |||
45 | -.. | ||
46 | - TODO: the old Texinfo manual used to note that this manual | ||
47 | - is GPL-v2-or-later. We should make that reader-visible | ||
48 | - both here and in our Sphinx manuals more generally. | ||
49 | - | ||
50 | -.. | ||
51 | - TODO: display the QEMU version, both here and in our Sphinx manuals | ||
52 | - more generally. | ||
53 | - | ||
54 | .. contents:: | ||
55 | :depth: 3 | ||
56 | |||
57 | diff --git a/docs/interop/qemu-storage-daemon-qmp-ref.rst b/docs/interop/qemu-storage-daemon-qmp-ref.rst | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/docs/interop/qemu-storage-daemon-qmp-ref.rst | ||
60 | +++ b/docs/interop/qemu-storage-daemon-qmp-ref.rst | ||
61 | @@ -XXX,XX +XXX,XX @@ | ||
62 | QEMU Storage Daemon QMP Reference Manual | ||
63 | ======================================== | ||
64 | |||
65 | -.. | ||
66 | - TODO: the old Texinfo manual used to note that this manual | ||
67 | - is GPL-v2-or-later. We should make that reader-visible | ||
68 | - both here and in our Sphinx manuals more generally. | ||
69 | - | ||
70 | -.. | ||
71 | - TODO: display the QEMU version, both here and in our Sphinx manuals | ||
72 | - more generally. | ||
73 | - | ||
74 | .. contents:: | ||
75 | :depth: 3 | ||
39 | 76 | ||
40 | -- | 77 | -- |
41 | 2.20.1 | 78 | 2.20.1 |
42 | 79 | ||
43 | 80 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Our built HTML documentation now has a standard footer which |
---|---|---|---|
2 | gives the license for QEMU (and its documentation as a whole). | ||
3 | In almost all pages, we either don't bother to state the | ||
4 | copyright/license for the individual rST sources, or we put | ||
5 | it in an rST comment. There are just three pages which render | ||
6 | copyright or license information into the user-visible HTML. | ||
2 | 7 | ||
3 | We now cache the core mmu_idx in env->hflags. Rather than recompute | 8 | Quoting a specific (different) license for an individual HTML |
4 | from scratch, extract the field. All of the uses of cpu_mmu_index | 9 | page within the manual is confusing. Downgrade the license |
5 | within target/arm are within helpers, and env->hflags is always stable | 10 | and copyright info to a comment within the rST source, bringing |
6 | within a translation block from whence helpers are called. | 11 | these pages in line with the rest of our documents. |
7 | 12 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Suggested-by: Markus Armbruster <armbru@redhat.com> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20200302175829.2183-3-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> | ||
16 | Reviewed-by: Cleber Rosa <crosa@redhat.com> | ||
17 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
18 | Acked-by: Michael S. Tsirkin <mst@redhat.com> | ||
19 | Message-id: 20210722192016.24915-3-peter.maydell@linaro.org | ||
12 | --- | 20 | --- |
13 | target/arm/cpu.h | 23 +++++++++++++---------- | 21 | docs/interop/vhost-user-gpu.rst | 7 ++++--- |
14 | target/arm/helper.c | 5 ----- | 22 | docs/interop/vhost-user.rst | 12 +++++++----- |
15 | 2 files changed, 13 insertions(+), 15 deletions(-) | 23 | docs/system/generic-loader.rst | 4 ++-- |
24 | 3 files changed, 13 insertions(+), 10 deletions(-) | ||
16 | 25 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 26 | diff --git a/docs/interop/vhost-user-gpu.rst b/docs/interop/vhost-user-gpu.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 28 | --- a/docs/interop/vhost-user-gpu.rst |
20 | +++ b/target/arm/cpu.h | 29 | +++ b/docs/interop/vhost-user-gpu.rst |
21 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit { | 30 | @@ -XXX,XX +XXX,XX @@ |
22 | 31 | Vhost-user-gpu Protocol | |
23 | #define MMU_USER_IDX 0 | 32 | ======================= |
24 | 33 | ||
25 | -/** | 34 | -:Licence: This work is licensed under the terms of the GNU GPL, |
26 | - * cpu_mmu_index: | 35 | - version 2 or later. See the COPYING file in the top-level |
27 | - * @env: The cpu environment | 36 | - directory. |
28 | - * @ifetch: True for code access, false for data access. | 37 | +.. |
29 | - * | 38 | + Licence: This work is licensed under the terms of the GNU GPL, |
30 | - * Return the core mmu index for the current translation regime. | 39 | + version 2 or later. See the COPYING file in the top-level |
31 | - * This function is used by generic TCG code paths. | 40 | + directory. |
32 | - */ | 41 | |
33 | -int cpu_mmu_index(CPUARMState *env, bool ifetch); | 42 | .. contents:: Table of Contents |
34 | - | 43 | |
35 | /* Indexes used when registering address spaces with cpu_address_space_init */ | 44 | diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst |
36 | typedef enum ARMASIdx { | 45 | index XXXXXXX..XXXXXXX 100644 |
37 | ARMASIdx_NS = 0, | 46 | --- a/docs/interop/vhost-user.rst |
38 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ | 47 | +++ b/docs/interop/vhost-user.rst |
39 | FIELD(TBFLAG_A64, TBID, 12, 2) | 48 | @@ -XXX,XX +XXX,XX @@ |
40 | FIELD(TBFLAG_A64, UNPRIV, 14, 1) | 49 | =================== |
41 | 50 | Vhost-user Protocol | |
42 | +/** | 51 | =================== |
43 | + * cpu_mmu_index: | 52 | -:Copyright: 2014 Virtual Open Systems Sarl. |
44 | + * @env: The cpu environment | 53 | -:Copyright: 2019 Intel Corporation |
45 | + * @ifetch: True for code access, false for data access. | 54 | -:Licence: This work is licensed under the terms of the GNU GPL, |
46 | + * | 55 | - version 2 or later. See the COPYING file in the top-level |
47 | + * Return the core mmu index for the current translation regime. | 56 | - directory. |
48 | + * This function is used by generic TCG code paths. | ||
49 | + */ | ||
50 | +static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) | ||
51 | +{ | ||
52 | + return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); | ||
53 | +} | ||
54 | + | 57 | + |
55 | static inline bool bswap_code(bool sctlr_b) | 58 | +.. |
56 | { | 59 | + Copyright 2014 Virtual Open Systems Sarl. |
57 | #ifdef CONFIG_USER_ONLY | 60 | + Copyright 2019 Intel Corporation |
58 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 61 | + Licence: This work is licensed under the terms of the GNU GPL, |
62 | + version 2 or later. See the COPYING file in the top-level | ||
63 | + directory. | ||
64 | |||
65 | .. contents:: Table of Contents | ||
66 | |||
67 | diff --git a/docs/system/generic-loader.rst b/docs/system/generic-loader.rst | ||
59 | index XXXXXXX..XXXXXXX 100644 | 68 | index XXXXXXX..XXXXXXX 100644 |
60 | --- a/target/arm/helper.c | 69 | --- a/docs/system/generic-loader.rst |
61 | +++ b/target/arm/helper.c | 70 | +++ b/docs/system/generic-loader.rst |
62 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) | 71 | @@ -XXX,XX +XXX,XX @@ |
63 | return arm_mmu_idx_el(env, arm_current_el(env)); | 72 | .. |
64 | } | 73 | Copyright (c) 2016, Xilinx Inc. |
65 | 74 | ||
66 | -int cpu_mmu_index(CPUARMState *env, bool ifetch) | 75 | -This work is licensed under the terms of the GNU GPL, version 2 or later. See |
67 | -{ | 76 | -the COPYING file in the top-level directory. |
68 | - return arm_to_core_mmu_idx(arm_mmu_idx(env)); | 77 | + This work is licensed under the terms of the GNU GPL, version 2 or later. See |
69 | -} | 78 | + the COPYING file in the top-level directory. |
70 | - | 79 | |
71 | #ifndef CONFIG_USER_ONLY | 80 | Generic Loader |
72 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | 81 | -------------- |
73 | { | ||
74 | -- | 82 | -- |
75 | 2.20.1 | 83 | 2.20.1 |
76 | 84 | ||
77 | 85 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | 2 | text", which can be handled as a bunch of different things if tagged | |
3 | The Cubieboard machine does not support the -bios argument. | 3 | with a specific "role": |
4 | Report an error when -bios is used and exit immediately. | 4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text |
5 | 5 | (the most common one for us is "reference to a URL, which gets | |
6 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 6 | hyperlinked"). |
7 | Message-id: 20200227220149.6845-5-nieklinnenbank@gmail.com | 7 | |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | The default "role" if none is specified is "title_reference", |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | intended for references to book or article titles, and it renders |
10 | into the HTML as <cite>...</cite> (usually comes out as italics). | ||
11 | |||
12 | build-system.rst seems to have been written under the mistaken | ||
13 | assumption that single-backticks mark up literal text (function | ||
14 | names, etc) which should be rendered in a fixed-width font. | ||
15 | The rST markup for this is ``double backticks``. | ||
16 | |||
17 | Update all the markup. | ||
18 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20210726142338.31872-2-peter.maydell@linaro.org | ||
11 | --- | 22 | --- |
12 | hw/arm/cubieboard.c | 7 +++++++ | 23 | docs/devel/build-system.rst | 156 ++++++++++++++++++------------------ |
13 | 1 file changed, 7 insertions(+) | 24 | 1 file changed, 78 insertions(+), 78 deletions(-) |
14 | 25 | ||
15 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 26 | diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/cubieboard.c | 28 | --- a/docs/devel/build-system.rst |
18 | +++ b/hw/arm/cubieboard.c | 29 | +++ b/docs/devel/build-system.rst |
19 | @@ -XXX,XX +XXX,XX @@ | 30 | @@ -XXX,XX +XXX,XX @@ following tasks: |
20 | #include "exec/address-spaces.h" | 31 | - Add a Meson build option to meson_options.txt. |
21 | #include "qapi/error.h" | 32 | |
22 | #include "cpu.h" | 33 | - Add support to the command line arg parser to handle any new |
23 | +#include "sysemu/sysemu.h" | 34 | - `--enable-XXX`/`--disable-XXX` flags required by the feature. |
24 | #include "hw/sysbus.h" | 35 | + ``--enable-XXX``/``--disable-XXX`` flags required by the feature. |
25 | #include "hw/boards.h" | 36 | |
26 | #include "hw/arm/allwinner-a10.h" | 37 | - Add information to the help output message to report on the new |
27 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | 38 | feature flag. |
28 | AwA10State *a10; | 39 | |
29 | Error *err = NULL; | 40 | - Add code to perform the actual feature check. |
30 | 41 | ||
31 | + /* BIOS is not supported by this board */ | 42 | - - Add code to include the feature status in `config-host.h` |
32 | + if (bios_name) { | 43 | + - Add code to include the feature status in ``config-host.h`` |
33 | + error_report("BIOS not supported for this machine"); | 44 | |
34 | + exit(1); | 45 | - Add code to print out the feature status in the configure summary |
35 | + } | 46 | upon completion. |
36 | + | 47 | @@ -XXX,XX +XXX,XX @@ Helper functions |
37 | /* This board has fixed size RAM (512MiB or 1GiB) */ | 48 | The configure script provides a variety of helper functions to assist |
38 | if (machine->ram_size != 512 * MiB && | 49 | developers in checking for system features: |
39 | machine->ram_size != 1 * GiB) { | 50 | |
51 | -`do_cc $ARGS...` | ||
52 | +``do_cc $ARGS...`` | ||
53 | Attempt to run the system C compiler passing it $ARGS... | ||
54 | |||
55 | -`do_cxx $ARGS...` | ||
56 | +``do_cxx $ARGS...`` | ||
57 | Attempt to run the system C++ compiler passing it $ARGS... | ||
58 | |||
59 | -`compile_object $CFLAGS` | ||
60 | +``compile_object $CFLAGS`` | ||
61 | Attempt to compile a test program with the system C compiler using | ||
62 | $CFLAGS. The test program must have been previously written to a file | ||
63 | - called $TMPC. The replacement in Meson is the compiler object `cc`, | ||
64 | - which has methods such as `cc.compiles()`, | ||
65 | - `cc.check_header()`, `cc.has_function()`. | ||
66 | + called $TMPC. The replacement in Meson is the compiler object ``cc``, | ||
67 | + which has methods such as ``cc.compiles()``, | ||
68 | + ``cc.check_header()``, ``cc.has_function()``. | ||
69 | |||
70 | -`compile_prog $CFLAGS $LDFLAGS` | ||
71 | +``compile_prog $CFLAGS $LDFLAGS`` | ||
72 | Attempt to compile a test program with the system C compiler using | ||
73 | $CFLAGS and link it with the system linker using $LDFLAGS. The test | ||
74 | program must have been previously written to a file called $TMPC. | ||
75 | - The replacement in Meson is `cc.find_library()` and `cc.links()`. | ||
76 | + The replacement in Meson is ``cc.find_library()`` and ``cc.links()``. | ||
77 | |||
78 | -`has $COMMAND` | ||
79 | +``has $COMMAND`` | ||
80 | Determine if $COMMAND exists in the current environment, either as a | ||
81 | shell builtin, or executable binary, returning 0 on success. The | ||
82 | - replacement in Meson is `find_program()`. | ||
83 | + replacement in Meson is ``find_program()``. | ||
84 | |||
85 | -`check_define $NAME` | ||
86 | +``check_define $NAME`` | ||
87 | Determine if the macro $NAME is defined by the system C compiler | ||
88 | |||
89 | -`check_include $NAME` | ||
90 | +``check_include $NAME`` | ||
91 | Determine if the include $NAME file is available to the system C | ||
92 | - compiler. The replacement in Meson is `cc.has_header()`. | ||
93 | + compiler. The replacement in Meson is ``cc.has_header()``. | ||
94 | |||
95 | -`write_c_skeleton` | ||
96 | +``write_c_skeleton`` | ||
97 | Write a minimal C program main() function to the temporary file | ||
98 | indicated by $TMPC | ||
99 | |||
100 | -`feature_not_found $NAME $REMEDY` | ||
101 | +``feature_not_found $NAME $REMEDY`` | ||
102 | Print a message to stderr that the feature $NAME was not available | ||
103 | on the system, suggesting the user try $REMEDY to address the | ||
104 | problem. | ||
105 | |||
106 | -`error_exit $MESSAGE $MORE...` | ||
107 | +``error_exit $MESSAGE $MORE...`` | ||
108 | Print $MESSAGE to stderr, followed by $MORE... and then exit from the | ||
109 | configure script with non-zero status | ||
110 | |||
111 | -`query_pkg_config $ARGS...` | ||
112 | +``query_pkg_config $ARGS...`` | ||
113 | Run pkg-config passing it $ARGS. If QEMU is doing a static build, | ||
114 | then --static will be automatically added to $ARGS | ||
115 | |||
116 | @@ -XXX,XX +XXX,XX @@ process for: | ||
117 | |||
118 | 4) other data files, such as icons or desktop files | ||
119 | |||
120 | -All executables are built by default, except for some `contrib/` | ||
121 | +All executables are built by default, except for some ``contrib/`` | ||
122 | binaries that are known to fail to build on some platforms (for example | ||
123 | 32-bit or big-endian platforms). Tests are also built by default, | ||
124 | though that might change in the future. | ||
125 | @@ -XXX,XX +XXX,XX @@ though that might change in the future. | ||
126 | The source code is highly modularized, split across many files to | ||
127 | facilitate building of all of these components with as little duplicated | ||
128 | compilation as possible. Using the Meson "sourceset" functionality, | ||
129 | -`meson.build` files group the source files in rules that are | ||
130 | +``meson.build`` files group the source files in rules that are | ||
131 | enabled according to the available system libraries and to various | ||
132 | configuration symbols. Sourcesets belong to one of four groups: | ||
133 | |||
134 | Subsystem sourcesets: | ||
135 | Various subsystems that are common to both tools and emulators have | ||
136 | - their own sourceset, for example `block_ss` for the block device subsystem, | ||
137 | - `chardev_ss` for the character device subsystem, etc. These sourcesets | ||
138 | + their own sourceset, for example ``block_ss`` for the block device subsystem, | ||
139 | + ``chardev_ss`` for the character device subsystem, etc. These sourcesets | ||
140 | are then turned into static libraries as follows:: | ||
141 | |||
142 | libchardev = static_library('chardev', chardev_ss.sources(), | ||
143 | @@ -XXX,XX +XXX,XX @@ Subsystem sourcesets: | ||
144 | |||
145 | chardev = declare_dependency(link_whole: libchardev) | ||
146 | |||
147 | - As of Meson 0.55.1, the special `.fa` suffix should be used for everything | ||
148 | - that is used with `link_whole`, to ensure that the link flags are placed | ||
149 | + As of Meson 0.55.1, the special ``.fa`` suffix should be used for everything | ||
150 | + that is used with ``link_whole``, to ensure that the link flags are placed | ||
151 | correctly in the command line. | ||
152 | |||
153 | Target-independent emulator sourcesets: | ||
154 | @@ -XXX,XX +XXX,XX @@ Target-independent emulator sourcesets: | ||
155 | This includes error handling infrastructure, standard data structures, | ||
156 | platform portability wrapper functions, etc. | ||
157 | |||
158 | - Target-independent code lives in the `common_ss`, `softmmu_ss` and | ||
159 | - `user_ss` sourcesets. `common_ss` is linked into all emulators, | ||
160 | - `softmmu_ss` only in system emulators, `user_ss` only in user-mode | ||
161 | + Target-independent code lives in the ``common_ss``, ``softmmu_ss`` and | ||
162 | + ``user_ss`` sourcesets. ``common_ss`` is linked into all emulators, | ||
163 | + ``softmmu_ss`` only in system emulators, ``user_ss`` only in user-mode | ||
164 | emulators. | ||
165 | |||
166 | Target-independent sourcesets must exercise particular care when using | ||
167 | - `if_false` rules. The `if_false` rule will be used correctly when linking | ||
168 | + ``if_false`` rules. The ``if_false`` rule will be used correctly when linking | ||
169 | emulator binaries; however, when *compiling* target-independent files | ||
170 | - into .o files, Meson may need to pick *both* the `if_true` and | ||
171 | - `if_false` sides to cater for targets that want either side. To | ||
172 | + into .o files, Meson may need to pick *both* the ``if_true`` and | ||
173 | + ``if_false`` sides to cater for targets that want either side. To | ||
174 | achieve that, you can add a special rule using the ``CONFIG_ALL`` | ||
175 | symbol:: | ||
176 | |||
177 | @@ -XXX,XX +XXX,XX @@ Target-dependent emulator sourcesets: | ||
178 | In the target-dependent set lives CPU emulation, some device emulation and | ||
179 | much glue code. This sometimes also has to be compiled multiple times, | ||
180 | once for each target being built. Target-dependent files are included | ||
181 | - in the `specific_ss` sourceset. | ||
182 | + in the ``specific_ss`` sourceset. | ||
183 | |||
184 | - Each emulator also includes sources for files in the `hw/` and `target/` | ||
185 | + Each emulator also includes sources for files in the ``hw/`` and ``target/`` | ||
186 | subdirectories. The subdirectory used for each emulator comes | ||
187 | from the target's definition of ``TARGET_BASE_ARCH`` or (if missing) | ||
188 | - ``TARGET_ARCH``, as found in `default-configs/targets/*.mak`. | ||
189 | + ``TARGET_ARCH``, as found in ``default-configs/targets/*.mak``. | ||
190 | |||
191 | - Each subdirectory in `hw/` adds one sourceset to the `hw_arch` dictionary, | ||
192 | + Each subdirectory in ``hw/`` adds one sourceset to the ``hw_arch`` dictionary, | ||
193 | for example:: | ||
194 | |||
195 | arm_ss = ss.source_set() | ||
196 | @@ -XXX,XX +XXX,XX @@ Target-dependent emulator sourcesets: | ||
197 | |||
198 | The sourceset is only used for system emulators. | ||
199 | |||
200 | - Each subdirectory in `target/` instead should add one sourceset to each | ||
201 | - of the `target_arch` and `target_softmmu_arch`, which are used respectively | ||
202 | + Each subdirectory in ``target/`` instead should add one sourceset to each | ||
203 | + of the ``target_arch`` and ``target_softmmu_arch``, which are used respectively | ||
204 | for all emulators and for system emulators only. For example:: | ||
205 | |||
206 | arm_ss = ss.source_set() | ||
207 | @@ -XXX,XX +XXX,XX @@ Target-dependent emulator sourcesets: | ||
208 | target_softmmu_arch += {'arm': arm_softmmu_ss} | ||
209 | |||
210 | Module sourcesets: | ||
211 | - There are two dictionaries for modules: `modules` is used for | ||
212 | - target-independent modules and `target_modules` is used for | ||
213 | - target-dependent modules. When modules are disabled the `module` | ||
214 | - source sets are added to `softmmu_ss` and the `target_modules` | ||
215 | - source sets are added to `specific_ss`. | ||
216 | + There are two dictionaries for modules: ``modules`` is used for | ||
217 | + target-independent modules and ``target_modules`` is used for | ||
218 | + target-dependent modules. When modules are disabled the ``module`` | ||
219 | + source sets are added to ``softmmu_ss`` and the ``target_modules`` | ||
220 | + source sets are added to ``specific_ss``. | ||
221 | |||
222 | Both dictionaries are nested. One dictionary is created per | ||
223 | subdirectory, and these per-subdirectory dictionaries are added to | ||
224 | @@ -XXX,XX +XXX,XX @@ Module sourcesets: | ||
225 | modules += { 'hw-display': hw_display_modules } | ||
226 | |||
227 | Utility sourcesets: | ||
228 | - All binaries link with a static library `libqemuutil.a`. This library | ||
229 | + All binaries link with a static library ``libqemuutil.a``. This library | ||
230 | is built from several sourcesets; most of them however host generated | ||
231 | - code, and the only two of general interest are `util_ss` and `stub_ss`. | ||
232 | + code, and the only two of general interest are ``util_ss`` and ``stub_ss``. | ||
233 | |||
234 | The separation between these two is purely for documentation purposes. | ||
235 | - `util_ss` contains generic utility files. Even though this code is only | ||
236 | + ``util_ss`` contains generic utility files. Even though this code is only | ||
237 | linked in some binaries, sometimes it requires hooks only in some of | ||
238 | these and depend on other functions that are not fully implemented by | ||
239 | - all QEMU binaries. `stub_ss` links dummy stubs that will only be linked | ||
240 | + all QEMU binaries. ``stub_ss`` links dummy stubs that will only be linked | ||
241 | into the binary if the real implementation is not present. In a way, | ||
242 | the stubs can be thought of as a portable implementation of the weak | ||
243 | symbols concept. | ||
244 | @@ -XXX,XX +XXX,XX @@ Utility sourcesets: | ||
245 | The following files concur in the definition of which files are linked | ||
246 | into each emulator: | ||
247 | |||
248 | -`default-configs/devices/*.mak` | ||
249 | - The files under `default-configs/devices/` control the boards and devices | ||
250 | +``default-configs/devices/*.mak`` | ||
251 | + The files under ``default-configs/devices/`` control the boards and devices | ||
252 | that are built into each QEMU system emulation targets. They merely contain | ||
253 | a list of config variable definitions such as:: | ||
254 | |||
255 | @@ -XXX,XX +XXX,XX @@ into each emulator: | ||
256 | CONFIG_XLNX_ZYNQMP_ARM=y | ||
257 | CONFIG_XLNX_VERSAL=y | ||
258 | |||
259 | -`*/Kconfig` | ||
260 | - These files are processed together with `default-configs/devices/*.mak` and | ||
261 | +``*/Kconfig`` | ||
262 | + These files are processed together with ``default-configs/devices/*.mak`` and | ||
263 | describe the dependencies between various features, subsystems and | ||
264 | device models. They are described in :ref:`kconfig` | ||
265 | |||
266 | -`default-configs/targets/*.mak` | ||
267 | - These files mostly define symbols that appear in the `*-config-target.h` | ||
268 | +``default-configs/targets/*.mak`` | ||
269 | + These files mostly define symbols that appear in the ``*-config-target.h`` | ||
270 | file for each emulator [#cfgtarget]_. However, the ``TARGET_ARCH`` | ||
271 | - and ``TARGET_BASE_ARCH`` will also be used to select the `hw/` and | ||
272 | - `target/` subdirectories that are compiled into each target. | ||
273 | + and ``TARGET_BASE_ARCH`` will also be used to select the ``hw/`` and | ||
274 | + ``target/`` subdirectories that are compiled into each target. | ||
275 | |||
276 | -.. [#cfgtarget] This header is included by `qemu/osdep.h` when | ||
277 | +.. [#cfgtarget] This header is included by ``qemu/osdep.h`` when | ||
278 | compiling files from the target-specific sourcesets. | ||
279 | |||
280 | These files rarely need changing unless you are adding a completely | ||
281 | @@ -XXX,XX +XXX,XX @@ Support scripts | ||
282 | --------------- | ||
283 | |||
284 | Meson has a special convention for invoking Python scripts: if their | ||
285 | -first line is `#! /usr/bin/env python3` and the file is *not* executable, | ||
286 | +first line is ``#! /usr/bin/env python3`` and the file is *not* executable, | ||
287 | find_program() arranges to invoke the script under the same Python | ||
288 | interpreter that was used to invoke Meson. This is the most common | ||
289 | and preferred way to invoke support scripts from Meson build files, | ||
290 | because it automatically uses the value of configure's --python= option. | ||
291 | |||
292 | -In case the script is not written in Python, use a `#! /usr/bin/env ...` | ||
293 | +In case the script is not written in Python, use a ``#! /usr/bin/env ...`` | ||
294 | line and make the script executable. | ||
295 | |||
296 | Scripts written in Python, where it is desirable to make the script | ||
297 | executable (for example for test scripts that developers may want to | ||
298 | invoke from the command line, such as tests/qapi-schema/test-qapi.py), | ||
299 | -should be invoked through the `python` variable in meson.build. For | ||
300 | +should be invoked through the ``python`` variable in meson.build. For | ||
301 | example:: | ||
302 | |||
303 | test('QAPI schema regression tests', python, | ||
304 | @@ -XXX,XX +XXX,XX @@ rules and wraps them so that e.g. submodules are built before QEMU. | ||
305 | The resulting build system is largely non-recursive in nature, in | ||
306 | contrast to common practices seen with automake. | ||
307 | |||
308 | -Tests are also ran by the Makefile with the traditional `make check` | ||
309 | -phony target, while benchmarks are run with `make bench`. Meson test | ||
310 | -suites such as `unit` can be ran with `make check-unit` too. It is also | ||
311 | -possible to run tests defined in meson.build with `meson test`. | ||
312 | +Tests are also ran by the Makefile with the traditional ``make check`` | ||
313 | +phony target, while benchmarks are run with ``make bench``. Meson test | ||
314 | +suites such as ``unit`` can be ran with ``make check-unit`` too. It is also | ||
315 | +possible to run tests defined in meson.build with ``meson test``. | ||
316 | |||
317 | Important files for the build system | ||
318 | ==================================== | ||
319 | @@ -XXX,XX +XXX,XX @@ The following key files are statically defined in the source tree, with | ||
320 | the rules needed to build QEMU. Their behaviour is influenced by a | ||
321 | number of dynamically created files listed later. | ||
322 | |||
323 | -`Makefile` | ||
324 | +``Makefile`` | ||
325 | The main entry point used when invoking make to build all the components | ||
326 | of QEMU. The default 'all' target will naturally result in the build of | ||
327 | every component. Makefile takes care of recursively building submodules | ||
328 | directly via a non-recursive set of rules. | ||
329 | |||
330 | -`*/meson.build` | ||
331 | +``*/meson.build`` | ||
332 | The meson.build file in the root directory is the main entry point for the | ||
333 | Meson build system, and it coordinates the configuration and build of all | ||
334 | executables. Build rules for various subdirectories are included in | ||
335 | other meson.build files spread throughout the QEMU source tree. | ||
336 | |||
337 | -`tests/Makefile.include` | ||
338 | +``tests/Makefile.include`` | ||
339 | Rules for external test harnesses. These include the TCG tests, | ||
340 | - `qemu-iotests` and the Avocado-based acceptance tests. | ||
341 | + ``qemu-iotests`` and the Avocado-based acceptance tests. | ||
342 | |||
343 | -`tests/docker/Makefile.include` | ||
344 | +``tests/docker/Makefile.include`` | ||
345 | Rules for Docker tests. Like tests/Makefile, this file is included | ||
346 | directly by the top level Makefile, anything defined in this file will | ||
347 | influence the entire build system. | ||
348 | |||
349 | -`tests/vm/Makefile.include` | ||
350 | +``tests/vm/Makefile.include`` | ||
351 | Rules for VM-based tests. Like tests/Makefile, this file is included | ||
352 | directly by the top level Makefile, anything defined in this file will | ||
353 | influence the entire build system. | ||
354 | @@ -XXX,XX +XXX,XX @@ Makefile. | ||
355 | |||
356 | Built by configure: | ||
357 | |||
358 | -`config-host.mak` | ||
359 | +``config-host.mak`` | ||
360 | When configure has determined the characteristics of the build host it | ||
361 | will write a long list of variables to config-host.mak file. This | ||
362 | provides the various install directories, compiler / linker flags and a | ||
363 | - variety of `CONFIG_*` variables related to optionally enabled features. | ||
364 | + variety of ``CONFIG_*`` variables related to optionally enabled features. | ||
365 | This is imported by the top level Makefile and meson.build in order to | ||
366 | tailor the build output. | ||
367 | |||
368 | @@ -XXX,XX +XXX,XX @@ Built by configure: | ||
369 | |||
370 | Built by Meson: | ||
371 | |||
372 | -`${TARGET-NAME}-config-devices.mak` | ||
373 | +``${TARGET-NAME}-config-devices.mak`` | ||
374 | TARGET-NAME is again the name of a system or userspace emulator. The | ||
375 | config-devices.mak file is automatically generated by make using the | ||
376 | scripts/make_device_config.sh program, feeding it the | ||
377 | default-configs/$TARGET-NAME file as input. | ||
378 | |||
379 | -`config-host.h`, `$TARGET-NAME/config-target.h`, `$TARGET-NAME/config-devices.h` | ||
380 | +``config-host.h``, ``$TARGET-NAME/config-target.h``, ``$TARGET-NAME/config-devices.h`` | ||
381 | These files are used by source code to determine what features | ||
382 | are enabled. They are generated from the contents of the corresponding | ||
383 | - `*.h` files using the scripts/create_config program. This extracts | ||
384 | + ``*.h`` files using the scripts/create_config program. This extracts | ||
385 | relevant variables and formats them as C preprocessor macros. | ||
386 | |||
387 | -`build.ninja` | ||
388 | +``build.ninja`` | ||
389 | The build rules. | ||
390 | |||
391 | |||
392 | Built by Makefile: | ||
393 | |||
394 | -`Makefile.ninja` | ||
395 | +``Makefile.ninja`` | ||
396 | A Makefile include that bridges to ninja for the actual build. The | ||
397 | Makefile is mostly a list of targets that Meson included in build.ninja. | ||
398 | |||
399 | -`Makefile.mtest` | ||
400 | +``Makefile.mtest`` | ||
401 | The Makefile definitions that let "make check" run tests defined in | ||
402 | meson.build. The rules are produced from Meson's JSON description of | ||
403 | tests (obtained with "meson introspect --tests") through the script | ||
404 | @@ -XXX,XX +XXX,XX @@ Built by Makefile: | ||
405 | Useful make targets | ||
406 | ------------------- | ||
407 | |||
408 | -`help` | ||
409 | +``help`` | ||
410 | Print a help message for the most common build targets. | ||
411 | |||
412 | -`print-VAR` | ||
413 | +``print-VAR`` | ||
414 | Print the value of the variable VAR. Useful for debugging the build | ||
415 | system. | ||
40 | -- | 416 | -- |
41 | 2.20.1 | 417 | 2.20.1 |
42 | 418 | ||
43 | 419 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | One of the example meson.build fragments incorrectly quotes some |
---|---|---|---|
2 | symbols as 'CONFIG_FOO`; the correct syntax here is 'CONFIG_FOO'. | ||
3 | (This isn't a rST formatting mistake because the example is displayed | ||
4 | literally; it's just the wrong kind of quote.) | ||
2 | 5 | ||
3 | The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip [1]. | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Cortex-A8 processor. Currently the Cubieboard machine definition specifies the | ||
6 | ARM Cortex-A9 in its description and as the default CPU. | ||
7 | |||
8 | This patch corrects the Cubieboard machine definition to use the ARM Cortex-A8. | ||
9 | |||
10 | The only user-visible effect is that our textual description of the | ||
11 | machine was wrong, because hw/arm/allwinner-a10.c always creates a | ||
12 | Cortex-A8 CPU regardless of the default value in the MachineClass struct. | ||
13 | |||
14 | [1] http://docs.cubieboard.org/products/start#cubieboard1 | ||
15 | [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf | ||
16 | |||
17 | Fixes: 8a863c8120994981a099 | ||
18 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
19 | Message-id: 20200227220149.6845-2-nieklinnenbank@gmail.com | ||
20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: 20210726142338.31872-3-peter.maydell@linaro.org |
22 | [note in commit message that the bug didn't have much visible effect] | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | --- | 10 | --- |
25 | hw/arm/cubieboard.c | 4 ++-- | 11 | docs/devel/build-system.rst | 4 ++-- |
26 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 2 insertions(+), 2 deletions(-) |
27 | 13 | ||
28 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 14 | diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst |
29 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/arm/cubieboard.c | 16 | --- a/docs/devel/build-system.rst |
31 | +++ b/hw/arm/cubieboard.c | 17 | +++ b/docs/devel/build-system.rst |
32 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | 18 | @@ -XXX,XX +XXX,XX @@ Target-independent emulator sourcesets: |
33 | 19 | symbol:: | |
34 | static void cubieboard_machine_init(MachineClass *mc) | 20 | |
35 | { | 21 | # Some targets have CONFIG_ACPI, some don't, so this is not enough |
36 | - mc->desc = "cubietech cubieboard (Cortex-A9)"; | 22 | - softmmu_ss.add(when: 'CONFIG_ACPI`, if_true: files('acpi.c'), |
37 | - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); | 23 | + softmmu_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi.c'), |
38 | + mc->desc = "cubietech cubieboard (Cortex-A8)"; | 24 | if_false: files('acpi-stub.c')) |
39 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); | 25 | |
40 | mc->init = cubieboard_init; | 26 | # This is required as well: |
41 | mc->block_default_type = IF_IDE; | 27 | - softmmu_ss.add(when: 'CONFIG_ALL`, if_true: files('acpi-stub.c')) |
42 | mc->units_per_default_bus = 1; | 28 | + softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c')) |
29 | |||
30 | Target-dependent emulator sourcesets: | ||
31 | In the target-dependent set lives CPU emulation, some device emulation and | ||
43 | -- | 32 | -- |
44 | 2.20.1 | 33 | 2.20.1 |
45 | 34 | ||
46 | 35 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | text", which can be handled as a bunch of different things if tagged | ||
3 | with a specific "role": | ||
4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text | ||
5 | (the most common one for us is "reference to a URL, which gets | ||
6 | hyperlinked"). | ||
2 | 7 | ||
3 | The Cubieboard contains either 512MiB or 1GiB of onboard RAM [1]. | 8 | The default "role" if none is specified is "title_reference", |
4 | Prevent changing RAM to a different size which could break user programs. | 9 | intended for references to book or article titles, and it renders |
10 | into the HTML as <cite>...</cite> (usually comes out as italics). | ||
5 | 11 | ||
6 | [1] http://linux-sunxi.org/Cubieboard | 12 | To format a literal (generally rendered as fixed-width font), |
13 | double-backticks are required. | ||
7 | 14 | ||
8 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 15 | ebpf_rss.rst gets this wrong in a few places; correct them. |
9 | Message-id: 20200227220149.6845-4-nieklinnenbank@gmail.com | 16 | |
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 19 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Message-id: 20210726142338.31872-4-peter.maydell@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | 21 | --- |
14 | hw/arm/cubieboard.c | 8 ++++++++ | 22 | docs/devel/ebpf_rss.rst | 18 +++++++++--------- |
15 | 1 file changed, 8 insertions(+) | 23 | 1 file changed, 9 insertions(+), 9 deletions(-) |
16 | 24 | ||
17 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 25 | diff --git a/docs/devel/ebpf_rss.rst b/docs/devel/ebpf_rss.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/cubieboard.c | 27 | --- a/docs/devel/ebpf_rss.rst |
20 | +++ b/hw/arm/cubieboard.c | 28 | +++ b/docs/devel/ebpf_rss.rst |
21 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | 29 | @@ -XXX,XX +XXX,XX @@ eBPF RSS implementation |
22 | AwA10State *a10; | 30 | |
23 | Error *err = NULL; | 31 | eBPF RSS loading functionality located in ebpf/ebpf_rss.c and ebpf/ebpf_rss.h. |
24 | 32 | ||
25 | + /* This board has fixed size RAM (512MiB or 1GiB) */ | 33 | -The `struct EBPFRSSContext` structure that holds 4 file descriptors: |
26 | + if (machine->ram_size != 512 * MiB && | 34 | +The ``struct EBPFRSSContext`` structure that holds 4 file descriptors: |
27 | + machine->ram_size != 1 * GiB) { | 35 | |
28 | + error_report("This machine can only be used with 512MiB or 1GiB RAM"); | 36 | - ctx - pointer of the libbpf context. |
29 | + exit(1); | 37 | - program_fd - file descriptor of the eBPF RSS program. |
30 | + } | 38 | @@ -XXX,XX +XXX,XX @@ The `struct EBPFRSSContext` structure that holds 4 file descriptors: |
31 | + | 39 | - map_toeplitz_key - file descriptor of the 'Toeplitz key' map. One element of the 40byte key prepared for the hashing algorithm. |
32 | /* Only allow Cortex-A8 for this board */ | 40 | - map_indirections_table - 128 elements of queue indexes. |
33 | if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a8")) != 0) { | 41 | |
34 | error_report("This board can only be used with cortex-a8 CPU"); | 42 | -`struct EBPFRSSConfig` fields: |
35 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_machine_init(MachineClass *mc) | 43 | +``struct EBPFRSSConfig`` fields: |
36 | { | 44 | |
37 | mc->desc = "cubietech cubieboard (Cortex-A8)"; | 45 | -- redirect - "boolean" value, should the hash be calculated, on false - `default_queue` would be used as the final decision. |
38 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); | 46 | +- redirect - "boolean" value, should the hash be calculated, on false - ``default_queue`` would be used as the final decision. |
39 | + mc->default_ram_size = 1 * GiB; | 47 | - populate_hash - for now, not used. eBPF RSS doesn't support hash reporting. |
40 | mc->init = cubieboard_init; | 48 | -- hash_types - binary mask of different hash types. See `VIRTIO_NET_RSS_HASH_TYPE_*` defines. If for packet hash should not be calculated - `default_queue` would be used. |
41 | mc->block_default_type = IF_IDE; | 49 | +- hash_types - binary mask of different hash types. See ``VIRTIO_NET_RSS_HASH_TYPE_*`` defines. If for packet hash should not be calculated - ``default_queue`` would be used. |
42 | mc->units_per_default_bus = 1; | 50 | - indirections_len - length of the indirections table, maximum 128. |
51 | - default_queue - the queue index that used for packet that shouldn't be hashed. For some packets, the hash can't be calculated(g.e ARP). | ||
52 | |||
53 | Functions: | ||
54 | |||
55 | -- `ebpf_rss_init()` - sets ctx to NULL, which indicates that EBPFRSSContext is not loaded. | ||
56 | -- `ebpf_rss_load()` - creates 3 maps and loads eBPF program from the rss.bpf.skeleton.h. Returns 'true' on success. After that, program_fd can be used to set steering for TAP. | ||
57 | -- `ebpf_rss_set_all()` - sets values for eBPF maps. `indirections_table` length is in EBPFRSSConfig. `toeplitz_key` is VIRTIO_NET_RSS_MAX_KEY_SIZE aka 40 bytes array. | ||
58 | -- `ebpf_rss_unload()` - close all file descriptors and set ctx to NULL. | ||
59 | +- ``ebpf_rss_init()`` - sets ctx to NULL, which indicates that EBPFRSSContext is not loaded. | ||
60 | +- ``ebpf_rss_load()`` - creates 3 maps and loads eBPF program from the rss.bpf.skeleton.h. Returns 'true' on success. After that, program_fd can be used to set steering for TAP. | ||
61 | +- ``ebpf_rss_set_all()`` - sets values for eBPF maps. ``indirections_table`` length is in EBPFRSSConfig. ``toeplitz_key`` is VIRTIO_NET_RSS_MAX_KEY_SIZE aka 40 bytes array. | ||
62 | +- ``ebpf_rss_unload()`` - close all file descriptors and set ctx to NULL. | ||
63 | |||
64 | Simplified eBPF RSS workflow: | ||
65 | |||
66 | @@ -XXX,XX +XXX,XX @@ Simplified eBPF RSS workflow: | ||
67 | NetClientState SetSteeringEBPF() | ||
68 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
69 | |||
70 | -For now, `set_steering_ebpf()` method supported by Linux TAP NetClientState. The method requires an eBPF program file descriptor as an argument. | ||
71 | +For now, ``set_steering_ebpf()`` method supported by Linux TAP NetClientState. The method requires an eBPF program file descriptor as an argument. | ||
43 | -- | 72 | -- |
44 | 2.20.1 | 73 | 2.20.1 |
45 | 74 | ||
46 | 75 | diff view generated by jsdifflib |
1 | From: Niek Linnenbank <nieklinnenbank@gmail.com> | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | text", which can be handled as a bunch of different things if tagged | ||
3 | with a specific "role": | ||
4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text | ||
5 | (the most common one for us is "reference to a URL, which gets | ||
6 | hyperlinked"). | ||
2 | 7 | ||
3 | The Cubieboard has an ARM Cortex-A8. Instead of simply ignoring a | 8 | The default "role" if none is specified is "title_reference", |
4 | bogus -cpu option provided by the user, give them an error message so | 9 | intended for references to book or article titles, and it renders |
5 | they know their command line is wrong. | 10 | into the HTML as <cite>...</cite> (usually comes out as italics). |
6 | 11 | ||
7 | Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 12 | To format a literal (generally rendered as fixed-width font), |
8 | Message-id: 20200227220149.6845-3-nieklinnenbank@gmail.com | 13 | double-backticks are required. |
14 | |||
15 | Mostly migration.rst gets this right, but some places incorrectly use | ||
16 | single backticks where double backticks were intended; correct them. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> |
11 | [PMM: tweaked commit message] | 22 | Message-id: 20210726142338.31872-5-peter.maydell@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | 23 | --- |
14 | hw/arm/cubieboard.c | 10 +++++++++- | 24 | docs/devel/migration.rst | 36 ++++++++++++++++++------------------ |
15 | 1 file changed, 9 insertions(+), 1 deletion(-) | 25 | 1 file changed, 18 insertions(+), 18 deletions(-) |
16 | 26 | ||
17 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 27 | diff --git a/docs/devel/migration.rst b/docs/devel/migration.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/cubieboard.c | 29 | --- a/docs/devel/migration.rst |
20 | +++ b/hw/arm/cubieboard.c | 30 | +++ b/docs/devel/migration.rst |
21 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info cubieboard_binfo = { | 31 | @@ -XXX,XX +XXX,XX @@ savevm/loadvm functionality. |
22 | 32 | Debugging | |
23 | static void cubieboard_init(MachineState *machine) | 33 | ========= |
24 | { | 34 | |
25 | - AwA10State *a10 = AW_A10(object_new(TYPE_AW_A10)); | 35 | -The migration stream can be analyzed thanks to `scripts/analyze-migration.py`. |
26 | + AwA10State *a10; | 36 | +The migration stream can be analyzed thanks to ``scripts/analyze-migration.py``. |
27 | Error *err = NULL; | 37 | |
28 | 38 | Example usage: | |
29 | + /* Only allow Cortex-A8 for this board */ | 39 | |
30 | + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a8")) != 0) { | 40 | @@ -XXX,XX +XXX,XX @@ Common infrastructure |
31 | + error_report("This board can only be used with cortex-a8 CPU"); | 41 | ===================== |
32 | + exit(1); | 42 | |
33 | + } | 43 | The files, sockets or fd's that carry the migration stream are abstracted by |
34 | + | 44 | -the ``QEMUFile`` type (see `migration/qemu-file.h`). In most cases this |
35 | + a10 = AW_A10(object_new(TYPE_AW_A10)); | 45 | -is connected to a subtype of ``QIOChannel`` (see `io/`). |
36 | + | 46 | +the ``QEMUFile`` type (see ``migration/qemu-file.h``). In most cases this |
37 | object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err); | 47 | +is connected to a subtype of ``QIOChannel`` (see ``io/``). |
38 | if (err != NULL) { | 48 | |
39 | error_reportf_err(err, "Couldn't set phy address: "); | 49 | |
50 | Saving the state of one device | ||
51 | @@ -XXX,XX +XXX,XX @@ An example (from hw/input/pckbd.c) | ||
52 | }; | ||
53 | |||
54 | We are declaring the state with name "pckbd". | ||
55 | -The `version_id` is 3, and the fields are 4 uint8_t in a KBDState structure. | ||
56 | +The ``version_id`` is 3, and the fields are 4 uint8_t in a KBDState structure. | ||
57 | We registered this with: | ||
58 | |||
59 | .. code:: c | ||
60 | |||
61 | vmstate_register(NULL, 0, &vmstate_kbd, s); | ||
62 | |||
63 | -For devices that are `qdev` based, we can register the device in the class | ||
64 | +For devices that are ``qdev`` based, we can register the device in the class | ||
65 | init function: | ||
66 | |||
67 | .. code:: c | ||
68 | @@ -XXX,XX +XXX,XX @@ another to load the state back. | ||
69 | SaveVMHandlers *ops, | ||
70 | void *opaque); | ||
71 | |||
72 | -Two functions in the ``ops`` structure are the `save_state` | ||
73 | -and `load_state` functions. Notice that `load_state` receives a version_id | ||
74 | -parameter to know what state format is receiving. `save_state` doesn't | ||
75 | +Two functions in the ``ops`` structure are the ``save_state`` | ||
76 | +and ``load_state`` functions. Notice that ``load_state`` receives a version_id | ||
77 | +parameter to know what state format is receiving. ``save_state`` doesn't | ||
78 | have a version_id parameter because it always uses the latest version. | ||
79 | |||
80 | Note that because the VMState macros still save the data in a raw | ||
81 | @@ -XXX,XX +XXX,XX @@ migration of a device, and using them breaks backward-migration | ||
82 | compatibility; in general most changes can be made by adding Subsections | ||
83 | (see above) or _TEST macros (see above) which won't break compatibility. | ||
84 | |||
85 | -Each version is associated with a series of fields saved. The `save_state` always saves | ||
86 | -the state as the newer version. But `load_state` sometimes is able to | ||
87 | +Each version is associated with a series of fields saved. The ``save_state`` always saves | ||
88 | +the state as the newer version. But ``load_state`` sometimes is able to | ||
89 | load state from an older version. | ||
90 | |||
91 | You can see that there are several version fields: | ||
92 | |||
93 | -- `version_id`: the maximum version_id supported by VMState for that device. | ||
94 | -- `minimum_version_id`: the minimum version_id that VMState is able to understand | ||
95 | +- ``version_id``: the maximum version_id supported by VMState for that device. | ||
96 | +- ``minimum_version_id``: the minimum version_id that VMState is able to understand | ||
97 | for that device. | ||
98 | -- `minimum_version_id_old`: For devices that were not able to port to vmstate, we can | ||
99 | +- ``minimum_version_id_old``: For devices that were not able to port to vmstate, we can | ||
100 | assign a function that knows how to read this old state. This field is | ||
101 | - ignored if there is no `load_state_old` handler. | ||
102 | + ignored if there is no ``load_state_old`` handler. | ||
103 | |||
104 | VMState is able to read versions from minimum_version_id to | ||
105 | version_id. And the function ``load_state_old()`` (if present) is able to | ||
106 | @@ -XXX,XX +XXX,XX @@ data and then transferred to the main structure. | ||
107 | |||
108 | If you use memory API functions that update memory layout outside | ||
109 | initialization (i.e., in response to a guest action), this is a strong | ||
110 | -indication that you need to call these functions in a `post_load` callback. | ||
111 | +indication that you need to call these functions in a ``post_load`` callback. | ||
112 | Examples of such memory API functions are: | ||
113 | |||
114 | - memory_region_add_subregion() | ||
115 | @@ -XXX,XX +XXX,XX @@ Postcopy migration with shared memory needs explicit support from the other | ||
116 | processes that share memory and from QEMU. There are restrictions on the type of | ||
117 | memory that userfault can support shared. | ||
118 | |||
119 | -The Linux kernel userfault support works on `/dev/shm` memory and on `hugetlbfs` | ||
120 | -(although the kernel doesn't provide an equivalent to `madvise(MADV_DONTNEED)` | ||
121 | +The Linux kernel userfault support works on ``/dev/shm`` memory and on ``hugetlbfs`` | ||
122 | +(although the kernel doesn't provide an equivalent to ``madvise(MADV_DONTNEED)`` | ||
123 | for hugetlbfs which may be a problem in some configurations). | ||
124 | |||
125 | The vhost-user code in QEMU supports clients that have Postcopy support, | ||
126 | -and the `vhost-user-bridge` (in `tests/`) and the DPDK package have changes | ||
127 | +and the ``vhost-user-bridge`` (in ``tests/``) and the DPDK package have changes | ||
128 | to support postcopy. | ||
129 | |||
130 | The client needs to open a userfaultfd and register the areas | ||
40 | -- | 131 | -- |
41 | 2.20.1 | 132 | 2.20.1 |
42 | 133 | ||
43 | 134 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | text", which can be handled as a bunch of different things if tagged | ||
3 | with a specific "role": | ||
4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text | ||
5 | (the most common one for us is "reference to a URL, which gets | ||
6 | hyperlinked"). | ||
2 | 7 | ||
3 | This bit traps EL1 access to tlb maintenance insns. | 8 | The default "role" if none is specified is "title_reference", |
9 | intended for references to book or article titles, and it renders | ||
10 | into the HTML as <cite>...</cite> (usually comes out as italics). | ||
4 | 11 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Fix various places in the devel section of the manual which were |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | using single backticks when double backticks (for literal text) |
7 | Message-id: 20200229012811.24129-12-richard.henderson@linaro.org | 14 | were intended. |
15 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
19 | Message-id: 20210726142338.31872-6-peter.maydell@linaro.org | ||
9 | --- | 20 | --- |
10 | target/arm/helper.c | 85 +++++++++++++++++++++++++++++---------------- | 21 | docs/devel/qgraph.rst | 8 ++++---- |
11 | 1 file changed, 55 insertions(+), 30 deletions(-) | 22 | docs/devel/tcg-plugins.rst | 14 +++++++------- |
23 | docs/devel/testing.rst | 8 ++++---- | ||
24 | 3 files changed, 15 insertions(+), 15 deletions(-) | ||
12 | 25 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 26 | diff --git a/docs/devel/qgraph.rst b/docs/devel/qgraph.rst |
14 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 28 | --- a/docs/devel/qgraph.rst |
16 | +++ b/target/arm/helper.c | 29 | +++ b/docs/devel/qgraph.rst |
17 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | 30 | @@ -XXX,XX +XXX,XX @@ Notes for the nodes: |
18 | return CP_ACCESS_OK; | 31 | Edges |
19 | } | 32 | ^^^^^^ |
20 | 33 | ||
21 | +/* Check for traps from EL1 due to HCR_EL2.TTLB. */ | 34 | -An edge relation between two nodes (drivers or machines) `X` and `Y` can be: |
22 | +static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | 35 | +An edge relation between two nodes (drivers or machines) ``X`` and ``Y`` can be: |
23 | + bool isread) | 36 | |
24 | +{ | 37 | -- ``X CONSUMES Y``: `Y` can be plugged into `X` |
25 | + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | 38 | -- ``X PRODUCES Y``: `X` provides the interface `Y` |
26 | + return CP_ACCESS_TRAP_EL2; | 39 | -- ``X CONTAINS Y``: `Y` is part of `X` component |
27 | + } | 40 | +- ``X CONSUMES Y``: ``Y`` can be plugged into ``X`` |
28 | + return CP_ACCESS_OK; | 41 | +- ``X PRODUCES Y``: ``X`` provides the interface ``Y`` |
29 | +} | 42 | +- ``X CONTAINS Y``: ``Y`` is part of ``X`` component |
30 | + | 43 | |
31 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 44 | Execution steps |
32 | { | 45 | ^^^^^^^^^^^^^^^ |
33 | ARMCPU *cpu = env_archcpu(env); | 46 | diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst |
34 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | 47 | index XXXXXXX..XXXXXXX 100644 |
35 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, | 48 | --- a/docs/devel/tcg-plugins.rst |
36 | /* 32 bit ITLB invalidates */ | 49 | +++ b/docs/devel/tcg-plugins.rst |
37 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | 50 | @@ -XXX,XX +XXX,XX @@ version they were built against. This can be done simply by:: |
38 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, | 51 | QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION; |
39 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 52 | |
40 | + .writefn = tlbiall_write }, | 53 | The core code will refuse to load a plugin that doesn't export a |
41 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | 54 | -`qemu_plugin_version` symbol or if plugin version is outside of QEMU's |
42 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, | 55 | +``qemu_plugin_version`` symbol or if plugin version is outside of QEMU's |
43 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 56 | supported range of API versions. |
44 | + .writefn = tlbimva_write }, | 57 | |
45 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, | 58 | -Additionally the `qemu_info_t` structure which is passed to the |
46 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, | 59 | -`qemu_plugin_install` method of a plugin will detail the minimum and |
47 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 60 | +Additionally the ``qemu_info_t`` structure which is passed to the |
48 | + .writefn = tlbiasid_write }, | 61 | +``qemu_plugin_install`` method of a plugin will detail the minimum and |
49 | /* 32 bit DTLB invalidates */ | 62 | current API versions supported by QEMU. The API version will be |
50 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | 63 | incremented if new APIs are added. The minimum API version will be |
51 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, | 64 | incremented if existing APIs are changed or removed. |
52 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 65 | @@ -XXX,XX +XXX,XX @@ Example Plugins |
53 | + .writefn = tlbiall_write }, | 66 | |
54 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | 67 | There are a number of plugins included with QEMU and you are |
55 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, | 68 | encouraged to contribute your own plugins plugins upstream. There is a |
56 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 69 | -`contrib/plugins` directory where they can go. |
57 | + .writefn = tlbimva_write }, | 70 | +``contrib/plugins`` directory where they can go. |
58 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, | 71 | |
59 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, | 72 | - tests/plugins |
60 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 73 | |
61 | + .writefn = tlbiasid_write }, | 74 | These are some basic plugins that are used to test and exercise the |
62 | /* 32 bit TLB invalidates */ | 75 | -API during the `make check-tcg` target. |
63 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | 76 | +API during the ``make check-tcg`` target. |
64 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, | 77 | |
65 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 78 | - contrib/plugins/hotblocks.c |
66 | + .writefn = tlbiall_write }, | 79 | |
67 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | 80 | @@ -XXX,XX +XXX,XX @@ with linux-user execution as system emulation tends to generate |
68 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, | 81 | re-translations as blocks from different programs get swapped in and |
69 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 82 | out of system memory. |
70 | + .writefn = tlbimva_write }, | 83 | |
71 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | 84 | -If your program is single-threaded you can use the `inline` option for |
72 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, | 85 | +If your program is single-threaded you can use the ``inline`` option for |
73 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 86 | slightly faster (but not thread safe) counters. |
74 | + .writefn = tlbiasid_write }, | 87 | |
75 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | 88 | Example:: |
76 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, | 89 | @@ -XXX,XX +XXX,XX @@ which will lead to a sorted list after the class breakdown:: |
77 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 90 | ... |
78 | + .writefn = tlbimvaa_write }, | 91 | |
79 | REGINFO_SENTINEL | 92 | To find the argument shorthand for the class you need to examine the |
80 | }; | 93 | -source code of the plugin at the moment, specifically the `*opt` |
81 | 94 | +source code of the plugin at the moment, specifically the ``*opt`` | |
82 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | 95 | argument in the InsnClassExecCount tables. |
83 | /* 32 bit TLB invalidates, Inner Shareable */ | 96 | |
84 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | 97 | - contrib/plugins/lockstep.c |
85 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, | 98 | diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst |
86 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 99 | index XXXXXXX..XXXXXXX 100644 |
87 | + .writefn = tlbiall_is_write }, | 100 | --- a/docs/devel/testing.rst |
88 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | 101 | +++ b/docs/devel/testing.rst |
89 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, | 102 | @@ -XXX,XX +XXX,XX @@ The base test class has also support for tests with more than one |
90 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 103 | QEMUMachine. The way to get machines is through the ``self.get_vm()`` |
91 | + .writefn = tlbimva_is_write }, | 104 | method which will return a QEMUMachine instance. The ``self.get_vm()`` |
92 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | 105 | method accepts arguments that will be passed to the QEMUMachine creation |
93 | - .type = ARM_CP_NO_RAW, .access = PL1_W, | 106 | -and also an optional `name` attribute so you can identify a specific |
94 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 107 | +and also an optional ``name`` attribute so you can identify a specific |
95 | .writefn = tlbiasid_is_write }, | 108 | machine and get it more than once through the tests methods. A simple |
96 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | 109 | and hypothetical example follows: |
97 | - .type = ARM_CP_NO_RAW, .access = PL1_W, | 110 | |
98 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 111 | @@ -XXX,XX +XXX,XX @@ Here is a list of the most used variables: |
99 | .writefn = tlbimvaa_is_write }, | 112 | AVOCADO_ALLOW_LARGE_STORAGE |
100 | REGINFO_SENTINEL | 113 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
101 | }; | 114 | Tests which are going to fetch or produce assets considered *large* are not |
102 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 115 | -going to run unless that `AVOCADO_ALLOW_LARGE_STORAGE=1` is exported on |
103 | /* TLBI operations */ | 116 | +going to run unless that ``AVOCADO_ALLOW_LARGE_STORAGE=1`` is exported on |
104 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | 117 | the environment. |
105 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | 118 | |
106 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | 119 | The definition of *large* is a bit arbitrary here, but it usually means an |
107 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 120 | @@ -XXX,XX +XXX,XX @@ skipped by default. The definition of *not safe* is also arbitrary but |
108 | .writefn = tlbi_aa64_vmalle1is_write }, | 121 | usually it means a blob which either its source or build process aren't |
109 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, | 122 | public available. |
110 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | 123 | |
111 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | 124 | -You should export `AVOCADO_ALLOW_UNTRUSTED_CODE=1` on the environment in |
112 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 125 | +You should export ``AVOCADO_ALLOW_UNTRUSTED_CODE=1`` on the environment in |
113 | .writefn = tlbi_aa64_vae1is_write }, | 126 | order to allow tests which make use of those kind of assets. |
114 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, | 127 | |
115 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | 128 | AVOCADO_TIMEOUT_EXPECTED |
116 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | 129 | @@ -XXX,XX +XXX,XX @@ property defined in the test class, for further details:: |
117 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 130 | Even though the timeout can be set by the test developer, there are some tests |
118 | .writefn = tlbi_aa64_vmalle1is_write }, | 131 | that may not have a well-defined limit of time to finish under certain |
119 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, | 132 | conditions. For example, tests that take longer to execute when QEMU is |
120 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | 133 | -compiled with debug flags. Therefore, the `AVOCADO_TIMEOUT_EXPECTED` variable |
121 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | 134 | +compiled with debug flags. Therefore, the ``AVOCADO_TIMEOUT_EXPECTED`` variable |
122 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 135 | has been used to determine whether those tests should run or not. |
123 | .writefn = tlbi_aa64_vae1is_write }, | 136 | |
124 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, | 137 | GITLAB_CI |
125 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | ||
126 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
127 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
128 | .writefn = tlbi_aa64_vae1is_write }, | ||
129 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, | ||
130 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | ||
131 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
132 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
133 | .writefn = tlbi_aa64_vae1is_write }, | ||
134 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, | ||
135 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | ||
136 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
137 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
138 | .writefn = tlbi_aa64_vmalle1_write }, | ||
139 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | ||
140 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | ||
141 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
142 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
143 | .writefn = tlbi_aa64_vae1_write }, | ||
144 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | ||
145 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | ||
146 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
147 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
148 | .writefn = tlbi_aa64_vmalle1_write }, | ||
149 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | ||
150 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | ||
151 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
152 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
153 | .writefn = tlbi_aa64_vae1_write }, | ||
154 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | ||
155 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, | ||
156 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
157 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
158 | .writefn = tlbi_aa64_vae1_write }, | ||
159 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | ||
160 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | ||
161 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
162 | + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
163 | .writefn = tlbi_aa64_vae1_write }, | ||
164 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, | ||
165 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | ||
166 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
167 | #endif | ||
168 | /* TLB invalidate last level of translation table walk */ | ||
169 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | ||
170 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, | ||
171 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
172 | + .writefn = tlbimva_is_write }, | ||
173 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | ||
174 | - .type = ARM_CP_NO_RAW, .access = PL1_W, | ||
175 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
176 | .writefn = tlbimvaa_is_write }, | ||
177 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, | ||
178 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, | ||
179 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
180 | + .writefn = tlbimva_write }, | ||
181 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | ||
182 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, | ||
183 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | ||
184 | + .writefn = tlbimvaa_write }, | ||
185 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | ||
186 | .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
187 | .writefn = tlbimva_hyp_write }, | ||
188 | -- | 138 | -- |
189 | 2.20.1 | 139 | 2.20.1 |
190 | 140 | ||
191 | 141 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | text", which can be handled as a bunch of different things if tagged | ||
3 | with a specific "role": | ||
4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text | ||
5 | (the most common one for us is "reference to a URL, which gets | ||
6 | hyperlinked"). | ||
2 | 7 | ||
3 | This bit traps EL1 access to cache maintenance insns that operate | 8 | The default "role" if none is specified is "title_reference", |
4 | to the point of unification. There are no longer any references to | 9 | intended for references to book or article titles, and it renders |
5 | plain aa64_cacheop_access, so remove it. | 10 | into the HTML as <cite>...</cite> (usually comes out as italics). |
6 | 11 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | To format a literal (generally rendered as fixed-width font), |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | double-backticks are required. |
9 | Message-id: 20200229012811.24129-11-richard.henderson@linaro.org | 14 | |
15 | protvirt.rst consistently uses single backticks when double backticks | ||
16 | are required; correct it. | ||
17 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
21 | Acked-by: Cornelia Huck <cohuck@redhat.com> | ||
22 | Message-id: 20210726142338.31872-7-peter.maydell@linaro.org | ||
11 | --- | 23 | --- |
12 | target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------ | 24 | docs/system/s390x/protvirt.rst | 12 ++++++------ |
13 | 1 file changed, 32 insertions(+), 21 deletions(-) | 25 | 1 file changed, 6 insertions(+), 6 deletions(-) |
14 | 26 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 27 | diff --git a/docs/system/s390x/protvirt.rst b/docs/system/s390x/protvirt.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 29 | --- a/docs/system/s390x/protvirt.rst |
18 | +++ b/target/arm/helper.c | 30 | +++ b/docs/system/s390x/protvirt.rst |
19 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo uao_reginfo = { | 31 | @@ -XXX,XX +XXX,XX @@ Prerequisites |
20 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | 32 | To run PVMs, a machine with the Protected Virtualization feature, as |
21 | }; | 33 | indicated by the Ultravisor Call facility (stfle bit 158), is |
22 | 34 | required. The Ultravisor needs to be initialized at boot by setting | |
23 | -static CPAccessResult aa64_cacheop_access(CPUARMState *env, | 35 | -`prot_virt=1` on the host's kernel command line. |
24 | - const ARMCPRegInfo *ri, | 36 | +``prot_virt=1`` on the host's kernel command line. |
25 | - bool isread) | 37 | |
26 | -{ | 38 | Running PVMs requires using the KVM hypervisor. |
27 | - /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | 39 | |
28 | - * SCTLR_EL1.UCI is set. | 40 | -If those requirements are met, the capability `KVM_CAP_S390_PROTECTED` |
29 | - */ | 41 | +If those requirements are met, the capability ``KVM_CAP_S390_PROTECTED`` |
30 | - if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { | 42 | will indicate that KVM can support PVMs on that LPAR. |
31 | - return CP_ACCESS_TRAP; | 43 | |
32 | - } | 44 | |
33 | - return CP_ACCESS_OK; | 45 | @@ -XXX,XX +XXX,XX @@ Running a Protected Virtual Machine |
34 | -} | 46 | ----------------------------------- |
35 | - | 47 | |
36 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, | 48 | To run a PVM you will need to select a CPU model which includes the |
37 | const ARMCPRegInfo *ri, | 49 | -`Unpack facility` (stfle bit 161 represented by the feature |
38 | bool isread) | 50 | -`unpack`/`S390_FEAT_UNPACK`), and add these options to the command line:: |
39 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, | 51 | +``Unpack facility`` (stfle bit 161 represented by the feature |
40 | return CP_ACCESS_OK; | 52 | +``unpack``/``S390_FEAT_UNPACK``), and add these options to the command line:: |
41 | } | 53 | |
42 | 54 | -object s390-pv-guest,id=pv0 \ | |
43 | +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, | 55 | -machine confidential-guest-support=pv0 |
44 | + const ARMCPRegInfo *ri, | 56 | |
45 | + bool isread) | 57 | Adding these options will: |
46 | +{ | 58 | |
47 | + /* Cache invalidate/clean to Point of Unification... */ | 59 | -* Ensure the `unpack` facility is available |
48 | + switch (arm_current_el(env)) { | 60 | +* Ensure the ``unpack`` facility is available |
49 | + case 0: | 61 | * Enable the IOMMU by default for all I/O devices |
50 | + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | 62 | * Initialize the PV mechanism |
51 | + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | 63 | |
52 | + return CP_ACCESS_TRAP; | 64 | @@ -XXX,XX +XXX,XX @@ from the disk boot. This memory layout includes the encrypted |
53 | + } | 65 | components (kernel, initrd, cmdline), the stage3a loader and |
54 | + /* fall through */ | 66 | metadata. In case this boot method is used, the command line |
55 | + case 1: | 67 | options -initrd and -cmdline are ineffective. The preparation of a PVM |
56 | + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ | 68 | -image is done via the `genprotimg` tool from the s390-tools |
57 | + if (arm_hcr_el2_eff(env) & HCR_TPU) { | 69 | +image is done via the ``genprotimg`` tool from the s390-tools |
58 | + return CP_ACCESS_TRAP_EL2; | 70 | collection. |
59 | + } | ||
60 | + break; | ||
61 | + } | ||
62 | + return CP_ACCESS_OK; | ||
63 | +} | ||
64 | + | ||
65 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions | ||
66 | * Page D4-1736 (DDI0487A.b) | ||
67 | */ | ||
68 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
69 | /* Cache ops: all NOPs since we don't emulate caches */ | ||
70 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | ||
71 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | ||
72 | - .access = PL1_W, .type = ARM_CP_NOP }, | ||
73 | + .access = PL1_W, .type = ARM_CP_NOP, | ||
74 | + .accessfn = aa64_cacheop_pou_access }, | ||
75 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | ||
76 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | ||
77 | - .access = PL1_W, .type = ARM_CP_NOP }, | ||
78 | + .access = PL1_W, .type = ARM_CP_NOP, | ||
79 | + .accessfn = aa64_cacheop_pou_access }, | ||
80 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | ||
81 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | ||
82 | .access = PL0_W, .type = ARM_CP_NOP, | ||
83 | - .accessfn = aa64_cacheop_access }, | ||
84 | + .accessfn = aa64_cacheop_pou_access }, | ||
85 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | ||
86 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | ||
87 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, | ||
88 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
89 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | ||
90 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | ||
91 | .access = PL0_W, .type = ARM_CP_NOP, | ||
92 | - .accessfn = aa64_cacheop_access }, | ||
93 | + .accessfn = aa64_cacheop_pou_access }, | ||
94 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | ||
95 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | ||
96 | .access = PL0_W, .type = ARM_CP_NOP, | ||
97 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
98 | .writefn = tlbiipas2_is_write }, | ||
99 | /* 32 bit cache operations */ | ||
100 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | ||
101 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
102 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
103 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | ||
104 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
105 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | ||
106 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
107 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
108 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | ||
109 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
110 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
111 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | ||
112 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
113 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | ||
114 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
115 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | ||
116 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
117 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | ||
118 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
119 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
120 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | ||
121 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, | ||
122 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | ||
123 | -- | 71 | -- |
124 | 2.20.1 | 72 | 2.20.1 |
125 | 73 | ||
126 | 74 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | 2 | text", which can be handled as a bunch of different things if tagged | |
3 | We only build the little-endian softmmu configurations. Checking | 3 | with a specific "role": |
4 | for big endian is pointless, remove the unused code. | 4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text |
5 | 5 | (the most common one for us is "reference to a URL, which gets | |
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 6 | hyperlinked"). |
7 | |||
8 | The default "role" if none is specified is "title_reference", | ||
9 | intended for references to book or article titles, and it renders | ||
10 | into the HTML as <cite>...</cite> (usually comes out as italics). | ||
11 | |||
12 | To format a literal (generally rendered as fixed-width font), | ||
13 | double-backticks are required. | ||
14 | |||
15 | cpu-features.rst consistently uses single backticks when double backticks | ||
16 | are required; correct it. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
21 | Message-id: 20210726142338.31872-8-peter.maydell@linaro.org | ||
9 | --- | 22 | --- |
10 | hw/arm/musicpal.c | 10 ---------- | 23 | docs/system/arm/cpu-features.rst | 116 +++++++++++++++---------------- |
11 | 1 file changed, 10 deletions(-) | 24 | 1 file changed, 58 insertions(+), 58 deletions(-) |
12 | 25 | ||
13 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | 26 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst |
14 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/musicpal.c | 28 | --- a/docs/system/arm/cpu-features.rst |
16 | +++ b/hw/arm/musicpal.c | 29 | +++ b/docs/system/arm/cpu-features.rst |
17 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | 30 | @@ -XXX,XX +XXX,XX @@ is the Performance Monitoring Unit (PMU). CPU types such as the |
18 | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the | 31 | Cortex-A15 and the Cortex-A57, which respectively implement Arm |
19 | * image is smaller than 32 MB. | 32 | architecture reference manuals ARMv7-A and ARMv8-A, may both optionally |
20 | */ | 33 | implement PMUs. For example, if a user wants to use a Cortex-A15 without |
21 | -#ifdef TARGET_WORDS_BIGENDIAN | 34 | -a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU |
22 | - pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, | 35 | -command line, i.e. `-cpu cortex-a15,pmu=off`. |
23 | - "musicpal.flash", flash_size, | 36 | +a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU |
24 | - blk, 0x10000, | 37 | +command line, i.e. ``-cpu cortex-a15,pmu=off``. |
25 | - MP_FLASH_SIZE_MAX / flash_size, | 38 | |
26 | - 2, 0x00BF, 0x236D, 0x0000, 0x0000, | 39 | As not all CPU types support all optional CPU features, then whether or |
27 | - 0x5555, 0x2AAA, 1); | 40 | not a CPU property exists depends on the CPU type. For example, CPUs |
28 | -#else | 41 | that implement the ARMv8-A architecture reference manual may optionally |
29 | pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, | 42 | support the AArch32 CPU feature, which may be enabled by disabling the |
30 | "musicpal.flash", flash_size, | 43 | -`aarch64` CPU property. A CPU type such as the Cortex-A15, which does |
31 | blk, 0x10000, | 44 | -not implement ARMv8-A, will not have the `aarch64` CPU property. |
32 | MP_FLASH_SIZE_MAX / flash_size, | 45 | +``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does |
33 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | 46 | +not implement ARMv8-A, will not have the ``aarch64`` CPU property. |
34 | 0x5555, 0x2AAA, 0); | 47 | |
35 | -#endif | 48 | QEMU's support may be limited for some CPU features, only partially |
36 | - | 49 | supporting the feature or only supporting the feature under certain |
37 | } | 50 | -configurations. For example, the `aarch64` CPU feature, which, when |
38 | sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); | 51 | +configurations. For example, the ``aarch64`` CPU feature, which, when |
52 | disabled, enables the optional AArch32 CPU feature, is only supported | ||
53 | when using the KVM accelerator and when running on a host CPU type that | ||
54 | -supports the feature. While `aarch64` currently only works with KVM, | ||
55 | +supports the feature. While ``aarch64`` currently only works with KVM, | ||
56 | it could work with TCG. CPU features that are specific to KVM are | ||
57 | prefixed with "kvm-" and are described in "KVM VCPU Features". | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ CPU Feature Probing | ||
60 | =================== | ||
61 | |||
62 | Determining which CPU features are available and functional for a given | ||
63 | -CPU type is possible with the `query-cpu-model-expansion` QMP command. | ||
64 | -Below are some examples where `scripts/qmp/qmp-shell` (see the top comment | ||
65 | +CPU type is possible with the ``query-cpu-model-expansion`` QMP command. | ||
66 | +Below are some examples where ``scripts/qmp/qmp-shell`` (see the top comment | ||
67 | block in the script for usage) is used to issue the QMP commands. | ||
68 | |||
69 | -1. Determine which CPU features are available for the `max` CPU type | ||
70 | - (Note, we started QEMU with qemu-system-aarch64, so `max` is | ||
71 | +1. Determine which CPU features are available for the ``max`` CPU type | ||
72 | + (Note, we started QEMU with qemu-system-aarch64, so ``max`` is | ||
73 | implementing the ARMv8-A reference manual in this case):: | ||
74 | |||
75 | (QEMU) query-cpu-model-expansion type=full model={"name":"max"} | ||
76 | @@ -XXX,XX +XXX,XX @@ block in the script for usage) is used to issue the QMP commands. | ||
77 | "sve896": true, "sve1280": true, "sve2048": true | ||
78 | }}}} | ||
79 | |||
80 | -We see that the `max` CPU type has the `pmu`, `aarch64`, `sve`, and many | ||
81 | -`sve<N>` CPU features. We also see that all the CPU features are | ||
82 | -enabled, as they are all `true`. (The `sve<N>` CPU features are all | ||
83 | +We see that the ``max`` CPU type has the ``pmu``, ``aarch64``, ``sve``, and many | ||
84 | +``sve<N>`` CPU features. We also see that all the CPU features are | ||
85 | +enabled, as they are all ``true``. (The ``sve<N>`` CPU features are all | ||
86 | optional SVE vector lengths (see "SVE CPU Properties"). While with TCG | ||
87 | all SVE vector lengths can be supported, when KVM is in use it's more | ||
88 | likely that only a few lengths will be supported, if SVE is supported at | ||
89 | @@ -XXX,XX +XXX,XX @@ all.) | ||
90 | "sve896": true, "sve1280": true, "sve2048": true | ||
91 | }}}} | ||
92 | |||
93 | -We see it worked, as `pmu` is now `false`. | ||
94 | +We see it worked, as ``pmu`` is now ``false``. | ||
95 | |||
96 | -(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature:: | ||
97 | +(3) Let's try to disable ``aarch64``, which enables the AArch32 CPU feature:: | ||
98 | |||
99 | (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}} | ||
100 | {"error": { | ||
101 | @@ -XXX,XX +XXX,XX @@ We see it worked, as `pmu` is now `false`. | ||
102 | It looks like this feature is limited to a configuration we do not | ||
103 | currently have. | ||
104 | |||
105 | -(4) Let's disable `sve` and see what happens to all the optional SVE | ||
106 | +(4) Let's disable ``sve`` and see what happens to all the optional SVE | ||
107 | vector lengths:: | ||
108 | |||
109 | (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}} | ||
110 | @@ -XXX,XX +XXX,XX @@ currently have. | ||
111 | "sve896": false, "sve1280": false, "sve2048": false | ||
112 | }}}} | ||
113 | |||
114 | -As expected they are now all `false`. | ||
115 | +As expected they are now all ``false``. | ||
116 | |||
117 | (5) Let's try probing CPU features for the Cortex-A15 CPU type:: | ||
118 | |||
119 | (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"} | ||
120 | {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}} | ||
121 | |||
122 | -Only the `pmu` CPU feature is available. | ||
123 | +Only the ``pmu`` CPU feature is available. | ||
124 | |||
125 | A note about CPU feature dependencies | ||
126 | ------------------------------------- | ||
127 | @@ -XXX,XX +XXX,XX @@ A note about CPU models and KVM | ||
128 | ------------------------------- | ||
129 | |||
130 | Named CPU models generally do not work with KVM. There are a few cases | ||
131 | -that do work, e.g. using the named CPU model `cortex-a57` with KVM on a | ||
132 | -seattle host, but mostly if KVM is enabled the `host` CPU type must be | ||
133 | +that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a | ||
134 | +seattle host, but mostly if KVM is enabled the ``host`` CPU type must be | ||
135 | used. This means the guest is provided all the same CPU features as the | ||
136 | -host CPU type has. And, for this reason, the `host` CPU type should | ||
137 | +host CPU type has. And, for this reason, the ``host`` CPU type should | ||
138 | enable all CPU features that the host has by default. Indeed it's even | ||
139 | a bit strange to allow disabling CPU features that the host has when using | ||
140 | -the `host` CPU type, but in the absence of CPU models it's the best we can | ||
141 | +the ``host`` CPU type, but in the absence of CPU models it's the best we can | ||
142 | do if we want to launch guests without all the host's CPU features enabled. | ||
143 | |||
144 | -Enabling KVM also affects the `query-cpu-model-expansion` QMP command. The | ||
145 | +Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. The | ||
146 | affect is not only limited to specific features, as pointed out in example | ||
147 | (3) of "CPU Feature Probing", but also to which CPU types may be expanded. | ||
148 | -When KVM is enabled, only the `max`, `host`, and current CPU type may be | ||
149 | +When KVM is enabled, only the ``max``, ``host``, and current CPU type may be | ||
150 | expanded. This restriction is necessary as it's not possible to know all | ||
151 | CPU types that may work with KVM, but it does impose a small risk of users | ||
152 | experiencing unexpected errors. For example on a seattle, as mentioned | ||
153 | -above, the `cortex-a57` CPU type is also valid when KVM is enabled. | ||
154 | -Therefore a user could use the `host` CPU type for the current type, but | ||
155 | -then attempt to query `cortex-a57`, however that query will fail with our | ||
156 | +above, the ``cortex-a57`` CPU type is also valid when KVM is enabled. | ||
157 | +Therefore a user could use the ``host`` CPU type for the current type, but | ||
158 | +then attempt to query ``cortex-a57``, however that query will fail with our | ||
159 | restrictions. This shouldn't be an issue though as management layers and | ||
160 | -users have been preferring the `host` CPU type for use with KVM for quite | ||
161 | +users have been preferring the ``host`` CPU type for use with KVM for quite | ||
162 | some time. Additionally, if the KVM-enabled QEMU instance running on a | ||
163 | -seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57` | ||
164 | +seattle host is using the ``cortex-a57`` CPU type, then querying ``cortex-a57`` | ||
165 | will work. | ||
166 | |||
167 | Using CPU Features | ||
168 | @@ -XXX,XX +XXX,XX @@ QEMU command line with that CPU type:: | ||
169 | $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on | ||
170 | |||
171 | The example above disables the PMU and enables the first two SVE vector | ||
172 | -lengths for the `max` CPU type. Note, the `sve=on` isn't actually | ||
173 | -necessary, because, as we observed above with our probe of the `max` CPU | ||
174 | -type, `sve` is already on by default. Also, based on our probe of | ||
175 | +lengths for the ``max`` CPU type. Note, the ``sve=on`` isn't actually | ||
176 | +necessary, because, as we observed above with our probe of the ``max`` CPU | ||
177 | +type, ``sve`` is already on by default. Also, based on our probe of | ||
178 | defaults, it would seem we need to disable many SVE vector lengths, rather | ||
179 | than only enabling the two we want. This isn't the case, because, as | ||
180 | -disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU | ||
181 | +disabling many SVE vector lengths would be quite verbose, the ``sve<N>`` CPU | ||
182 | properties have special semantics (see "SVE CPU Property Parsing | ||
183 | Semantics"). | ||
184 | |||
185 | @@ -XXX,XX +XXX,XX @@ TCG VCPU Features | ||
186 | TCG VCPU features are CPU features that are specific to TCG. | ||
187 | Below is the list of TCG VCPU features and their descriptions. | ||
188 | |||
189 | - pauth Enable or disable `FEAT_Pauth`, pointer | ||
190 | + pauth Enable or disable ``FEAT_Pauth``, pointer | ||
191 | authentication. By default, the feature is | ||
192 | - enabled with `-cpu max`. | ||
193 | + enabled with ``-cpu max``. | ||
194 | |||
195 | - pauth-impdef When `FEAT_Pauth` is enabled, either the | ||
196 | + pauth-impdef When ``FEAT_Pauth`` is enabled, either the | ||
197 | *impdef* (Implementation Defined) algorithm | ||
198 | is enabled or the *architected* QARMA algorithm | ||
199 | is enabled. By default the impdef algorithm | ||
200 | @@ -XXX,XX +XXX,XX @@ Below is the list of TCG VCPU features and their descriptions. | ||
201 | SVE CPU Properties | ||
202 | ================== | ||
203 | |||
204 | -There are two types of SVE CPU properties: `sve` and `sve<N>`. The first | ||
205 | -is used to enable or disable the entire SVE feature, just as the `pmu` | ||
206 | +There are two types of SVE CPU properties: ``sve`` and ``sve<N>``. The first | ||
207 | +is used to enable or disable the entire SVE feature, just as the ``pmu`` | ||
208 | CPU property completely enables or disables the PMU. The second type | ||
209 | -is used to enable or disable specific vector lengths, where `N` is the | ||
210 | -number of bits of the length. The `sve<N>` CPU properties have special | ||
211 | +is used to enable or disable specific vector lengths, where ``N`` is the | ||
212 | +number of bits of the length. The ``sve<N>`` CPU properties have special | ||
213 | dependencies and constraints, see "SVE CPU Property Dependencies and | ||
214 | Constraints" below. Additionally, as we want all supported vector lengths | ||
215 | to be enabled by default, then, in order to avoid overly verbose command | ||
216 | -lines (command lines full of `sve<N>=off`, for all `N` not wanted), we | ||
217 | +lines (command lines full of ``sve<N>=off``, for all ``N`` not wanted), we | ||
218 | provide the parsing semantics listed in "SVE CPU Property Parsing | ||
219 | Semantics". | ||
220 | |||
221 | SVE CPU Property Dependencies and Constraints | ||
222 | --------------------------------------------- | ||
223 | |||
224 | - 1) At least one vector length must be enabled when `sve` is enabled. | ||
225 | + 1) At least one vector length must be enabled when ``sve`` is enabled. | ||
226 | |||
227 | - 2) If a vector length `N` is enabled, then, when KVM is enabled, all | ||
228 | + 2) If a vector length ``N`` is enabled, then, when KVM is enabled, all | ||
229 | smaller, host supported vector lengths must also be enabled. If | ||
230 | KVM is not enabled, then only all the smaller, power-of-two vector | ||
231 | lengths must be enabled. E.g. with KVM if the host supports all | ||
232 | - vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512` | ||
233 | + vector lengths up to 512-bits (128, 256, 384, 512), then if ``sve512`` | ||
234 | is enabled, the 128-bit vector length, 256-bit vector length, and | ||
235 | 384-bit vector length must also be enabled. Without KVM, the 384-bit | ||
236 | vector length would not be required. | ||
237 | |||
238 | 3) If KVM is enabled then only vector lengths that the host CPU type | ||
239 | support may be enabled. If SVE is not supported by the host, then | ||
240 | - no `sve*` properties may be enabled. | ||
241 | + no ``sve*`` properties may be enabled. | ||
242 | |||
243 | SVE CPU Property Parsing Semantics | ||
244 | ---------------------------------- | ||
245 | |||
246 | - 1) If SVE is disabled (`sve=off`), then which SVE vector lengths | ||
247 | + 1) If SVE is disabled (``sve=off``), then which SVE vector lengths | ||
248 | are enabled or disabled is irrelevant to the guest, as the entire | ||
249 | SVE feature is disabled and that disables all vector lengths for | ||
250 | - the guest. However QEMU will still track any `sve<N>` CPU | ||
251 | - properties provided by the user. If later an `sve=on` is provided, | ||
252 | - then the guest will get only the enabled lengths. If no `sve=on` | ||
253 | + the guest. However QEMU will still track any ``sve<N>`` CPU | ||
254 | + properties provided by the user. If later an ``sve=on`` is provided, | ||
255 | + then the guest will get only the enabled lengths. If no ``sve=on`` | ||
256 | is provided and there are explicitly enabled vector lengths, then | ||
257 | an error is generated. | ||
258 | |||
259 | - 2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are | ||
260 | + 2) If SVE is enabled (``sve=on``), but no ``sve<N>`` CPU properties are | ||
261 | provided, then all supported vector lengths are enabled, which when | ||
262 | KVM is not in use means including the non-power-of-two lengths, and, | ||
263 | when KVM is in use, it means all vector lengths supported by the host | ||
264 | @@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics | ||
265 | constraint (2) of "SVE CPU Property Dependencies and Constraints"). | ||
266 | |||
267 | 5) When KVM is enabled, if the host does not support SVE, then an error | ||
268 | - is generated when attempting to enable any `sve*` properties (see | ||
269 | + is generated when attempting to enable any ``sve*`` properties (see | ||
270 | constraint (3) of "SVE CPU Property Dependencies and Constraints"). | ||
271 | |||
272 | 6) When KVM is enabled, if the host does support SVE, then an error is | ||
273 | @@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics | ||
274 | by the host (see constraint (3) of "SVE CPU Property Dependencies and | ||
275 | Constraints"). | ||
276 | |||
277 | - 7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`, | ||
278 | - CPU properties are set `on`, then the specified vector lengths are | ||
279 | + 7) If one or more ``sve<N>`` CPU properties are set ``off``, but no ``sve<N>``, | ||
280 | + CPU properties are set ``on``, then the specified vector lengths are | ||
281 | disabled but the default for any unspecified lengths remains enabled. | ||
282 | When KVM is not enabled, disabling a power-of-two vector length also | ||
283 | disables all vector lengths larger than the power-of-two length. | ||
284 | @@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics | ||
285 | disables all larger vector lengths (see constraint (2) of "SVE CPU | ||
286 | Property Dependencies and Constraints"). | ||
287 | |||
288 | - 8) If one or more `sve<N>` CPU properties are set to `on`, then they | ||
289 | + 8) If one or more ``sve<N>`` CPU properties are set to ``on``, then they | ||
290 | are enabled and all unspecified lengths default to disabled, except | ||
291 | for the required lengths per constraint (2) of "SVE CPU Property | ||
292 | Dependencies and Constraints", which will even be auto-enabled if | ||
293 | they were not explicitly enabled. | ||
294 | |||
295 | - 9) If SVE was disabled (`sve=off`), allowing all vector lengths to be | ||
296 | + 9) If SVE was disabled (``sve=off``), allowing all vector lengths to be | ||
297 | explicitly disabled (i.e. avoiding the error specified in (3) of | ||
298 | - "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is | ||
299 | + "SVE CPU Property Parsing Semantics"), then if later an ``sve=on`` is | ||
300 | provided an error will be generated. To avoid this error, one must | ||
301 | enable at least one vector length prior to enabling SVE. | ||
302 | |||
303 | @@ -XXX,XX +XXX,XX @@ SVE CPU Property Examples | ||
304 | |||
305 | $ qemu-system-aarch64 -M virt -cpu max,sve=off | ||
306 | |||
307 | - 2) Implicitly enable all vector lengths for the `max` CPU type:: | ||
308 | + 2) Implicitly enable all vector lengths for the ``max`` CPU type:: | ||
309 | |||
310 | $ qemu-system-aarch64 -M virt -cpu max | ||
311 | |||
312 | 3) When KVM is enabled, implicitly enable all host CPU supported vector | ||
313 | - lengths with the `host` CPU type:: | ||
314 | + lengths with the ``host`` CPU type:: | ||
315 | |||
316 | $ qemu-system-aarch64 -M virt,accel=kvm -cpu host | ||
39 | 317 | ||
40 | -- | 318 | -- |
41 | 2.20.1 | 319 | 2.20.1 |
42 | 320 | ||
43 | 321 | diff view generated by jsdifflib |
1 | The ARMv8.2-TTCNP extension allows an implementation to optimize by | 1 | In rST markup, single backticks `like this` represent "interpreted |
---|---|---|---|
2 | sharing TLB entries between multiple cores, provided that software | 2 | text", which can be handled as a bunch of different things if tagged |
3 | declares that it's ready to deal with this by setting a CnP bit in | 3 | with a specific "role": |
4 | the TTBRn_ELx. It is mandatory from ARMv8.2 onward. | 4 | https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text |
5 | (the most common one for us is "reference to a URL, which gets | ||
6 | hyperlinked"). | ||
5 | 7 | ||
6 | For QEMU's TLB implementation, sharing TLB entries between different | 8 | The default "role" if none is specified is "title_reference", |
7 | cores would not really benefit us and would be a lot of work to | 9 | intended for references to book or article titles, and it renders |
8 | implement. So we implement this extension in the "trivial" manner: | 10 | into the HTML as <cite>...</cite> (usually comes out as italics). |
9 | we allow the guest to set and read back the CnP bit, but don't change | ||
10 | our behaviour (this is an architecturally valid implementation | ||
11 | choice). | ||
12 | 11 | ||
13 | The only code path which looks at the TTBRn_ELx values for the | 12 | This commit fixes various places in the manual which were |
14 | long-descriptor format where the CnP bit is defined is already doing | 13 | using single backticks when double backticks (for literal text) |
15 | enough masking to not get confused when the CnP bit at the bottom of | 14 | were intended, and covers those files where only one or two |
16 | the register is set, so we can simply add a comment noting why we're | 15 | instances of these errors were made. |
17 | relying on that mask. | ||
18 | 16 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
21 | Message-id: 20200225193822.18874-1-peter.maydell@linaro.org | ||
22 | --- | 19 | --- |
23 | target/arm/cpu.c | 1 + | 20 | docs/about/index.rst | 2 +- |
24 | target/arm/cpu64.c | 2 ++ | 21 | docs/interop/live-block-operations.rst | 2 +- |
25 | target/arm/helper.c | 4 ++++ | 22 | docs/system/arm/nuvoton.rst | 2 +- |
26 | 3 files changed, 7 insertions(+) | 23 | docs/system/arm/sbsa.rst | 4 ++-- |
24 | docs/system/arm/virt.rst | 2 +- | ||
25 | docs/system/cpu-hotplug.rst | 2 +- | ||
26 | docs/system/guest-loader.rst | 6 +++--- | ||
27 | docs/system/ppc/powernv.rst | 8 ++++---- | ||
28 | docs/system/riscv/microchip-icicle-kit.rst | 2 +- | ||
29 | docs/system/riscv/virt.rst | 2 +- | ||
30 | 10 files changed, 16 insertions(+), 16 deletions(-) | ||
27 | 31 | ||
28 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 32 | diff --git a/docs/about/index.rst b/docs/about/index.rst |
29 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/cpu.c | 34 | --- a/docs/about/index.rst |
31 | +++ b/target/arm/cpu.c | 35 | +++ b/docs/about/index.rst |
32 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 36 | @@ -XXX,XX +XXX,XX @@ where QEMU can launch processes compiled for one CPU on another CPU. |
33 | t = cpu->isar.id_mmfr4; | 37 | In this mode the CPU is always emulated. |
34 | t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | 38 | |
35 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | 39 | QEMU also provides a number of standalone commandline utilities, |
36 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | 40 | -such as the `qemu-img` disk image utility that allows you to create, |
37 | cpu->isar.id_mmfr4 = t; | 41 | +such as the ``qemu-img`` disk image utility that allows you to create, |
42 | convert and modify disk images. | ||
43 | |||
44 | .. toctree:: | ||
45 | diff --git a/docs/interop/live-block-operations.rst b/docs/interop/live-block-operations.rst | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/docs/interop/live-block-operations.rst | ||
48 | +++ b/docs/interop/live-block-operations.rst | ||
49 | @@ -XXX,XX +XXX,XX @@ the content of image [D]. | ||
38 | } | 50 | } |
39 | #endif | 51 | |
40 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 52 | (6) [On *destination* QEMU] Finally, resume the guest vCPUs by issuing the |
53 | - QMP command `cont`:: | ||
54 | + QMP command ``cont``:: | ||
55 | |||
56 | (QEMU) cont | ||
57 | { | ||
58 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | ||
41 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/target/arm/cpu64.c | 60 | --- a/docs/system/arm/nuvoton.rst |
43 | +++ b/target/arm/cpu64.c | 61 | +++ b/docs/system/arm/nuvoton.rst |
44 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 62 | @@ -XXX,XX +XXX,XX @@ Boot options |
45 | 63 | ------------ | |
46 | t = cpu->isar.id_aa64mmfr2; | 64 | |
47 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | 65 | The Nuvoton machines can boot from an OpenBMC firmware image, or directly into |
48 | + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | 66 | -a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and |
49 | cpu->isar.id_aa64mmfr2 = t; | 67 | +a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and |
50 | 68 | possibly others can be downloaded from the OpenPOWER jenkins : | |
51 | /* Replicate the same data to the 32-bit id registers. */ | 69 | |
52 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 70 | https://openpower.xyz/ |
53 | u = cpu->isar.id_mmfr4; | 71 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst |
54 | u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
55 | u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
56 | + u = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
57 | cpu->isar.id_mmfr4 = u; | ||
58 | |||
59 | u = cpu->isar.id_aa64dfr0; | ||
60 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | 72 | index XXXXXXX..XXXXXXX 100644 |
62 | --- a/target/arm/helper.c | 73 | --- a/docs/system/arm/sbsa.rst |
63 | +++ b/target/arm/helper.c | 74 | +++ b/docs/system/arm/sbsa.rst |
64 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | 75 | @@ -XXX,XX +XXX,XX @@ |
65 | 76 | Arm Server Base System Architecture Reference board (``sbsa-ref``) | |
66 | /* Now we can extract the actual base address from the TTBR */ | 77 | ================================================================== |
67 | descaddr = extract64(ttbr, 0, 48); | 78 | |
68 | + /* | 79 | -While the `virt` board is a generic board platform that doesn't match |
69 | + * We rely on this masking to clear the RES0 bits at the bottom of the TTBR | 80 | -any real hardware the `sbsa-ref` board intends to look like real |
70 | + * and also to mask out CnP (bit 0) which could validly be non-zero. | 81 | +While the ``virt`` board is a generic board platform that doesn't match |
71 | + */ | 82 | +any real hardware the ``sbsa-ref`` board intends to look like real |
72 | descaddr &= ~indexmask; | 83 | hardware. The `Server Base System Architecture |
73 | 84 | <https://developer.arm.com/documentation/den0029/latest>`_ defines a | |
74 | /* The address field in the descriptor goes up to bit 39 for ARMv7 | 85 | minimum base line of hardware support and importantly how the firmware |
86 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/docs/system/arm/virt.rst | ||
89 | +++ b/docs/system/arm/virt.rst | ||
90 | @@ -XXX,XX +XXX,XX @@ | ||
91 | 'virt' generic virtual platform (``virt``) | ||
92 | ========================================== | ||
93 | |||
94 | -The `virt` board is a platform which does not correspond to any | ||
95 | +The ``virt`` board is a platform which does not correspond to any | ||
96 | real hardware; it is designed for use in virtual machines. | ||
97 | It is the recommended board type if you simply want to run | ||
98 | a guest such as Linux and do not care about reproducing the | ||
99 | diff --git a/docs/system/cpu-hotplug.rst b/docs/system/cpu-hotplug.rst | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/docs/system/cpu-hotplug.rst | ||
102 | +++ b/docs/system/cpu-hotplug.rst | ||
103 | @@ -XXX,XX +XXX,XX @@ vCPU hotplug | ||
104 | } | ||
105 | (QEMU) | ||
106 | |||
107 | -(5) Optionally, run QMP `query-cpus-fast` for some details about the | ||
108 | +(5) Optionally, run QMP ``query-cpus-fast`` for some details about the | ||
109 | vCPUs:: | ||
110 | |||
111 | (QEMU) query-cpus-fast | ||
112 | diff --git a/docs/system/guest-loader.rst b/docs/system/guest-loader.rst | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/docs/system/guest-loader.rst | ||
115 | +++ b/docs/system/guest-loader.rst | ||
116 | @@ -XXX,XX +XXX,XX @@ | ||
117 | Guest Loader | ||
118 | ------------ | ||
119 | |||
120 | -The guest loader is similar to the `generic-loader` although it is | ||
121 | +The guest loader is similar to the ``generic-loader`` although it is | ||
122 | aimed at a particular use case of loading hypervisor guests. This is | ||
123 | useful for debugging hypervisors without having to jump through the | ||
124 | hoops of firmware and boot-loaders. | ||
125 | @@ -XXX,XX +XXX,XX @@ multi-boot capability. A typical example would look like: | ||
126 | In the above example the Xen hypervisor is loaded by the -kernel | ||
127 | parameter and passed it's boot arguments via -append. The Dom0 guest | ||
128 | is loaded into the areas of memory. Each blob will get | ||
129 | -`/chosen/module@<addr>` entry in the FDT to indicate it's location and | ||
130 | +``/chosen/module@<addr>`` entry in the FDT to indicate it's location and | ||
131 | size. Additional information can be passed with by using additional | ||
132 | arguments. | ||
133 | |||
134 | Currently the only supported machines which use FDT data to boot are | ||
135 | -the ARM and RiscV `virt` machines. | ||
136 | +the ARM and RiscV ``virt`` machines. | ||
137 | |||
138 | Arguments | ||
139 | ^^^^^^^^^ | ||
140 | diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst | ||
141 | index XXXXXXX..XXXXXXX 100644 | ||
142 | --- a/docs/system/ppc/powernv.rst | ||
143 | +++ b/docs/system/ppc/powernv.rst | ||
144 | @@ -XXX,XX +XXX,XX @@ Firmware | ||
145 | -------- | ||
146 | |||
147 | The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems | ||
148 | -includes the runtime services `skiboot` and the bootloader kernel and | ||
149 | -initramfs `skiroot`. Source code can be found on GitHub: | ||
150 | +includes the runtime services ``skiboot`` and the bootloader kernel and | ||
151 | +initramfs ``skiroot``. Source code can be found on GitHub: | ||
152 | |||
153 | https://github.com/open-power. | ||
154 | |||
155 | -Prebuilt images of `skiboot` and `skiboot` are made available on the `OpenPOWER <https://openpower.xyz/job/openpower/job/openpower-op-build/>`__ site. To boot a POWER9 machine, use the `witherspoon <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=witherspoon/lastSuccessfulBuild/>`__ images. For POWER8, use | ||
156 | +Prebuilt images of ``skiboot`` and ``skiboot`` are made available on the `OpenPOWER <https://openpower.xyz/job/openpower/job/openpower-op-build/>`__ site. To boot a POWER9 machine, use the `witherspoon <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=witherspoon/lastSuccessfulBuild/>`__ images. For POWER8, use | ||
157 | the `palmetto <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=palmetto/lastSuccessfulBuild/>`__ images. | ||
158 | |||
159 | -QEMU includes a prebuilt image of `skiboot` which is updated when a | ||
160 | +QEMU includes a prebuilt image of ``skiboot`` which is updated when a | ||
161 | more recent version is required by the models. | ||
162 | |||
163 | Boot options | ||
164 | diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst | ||
165 | index XXXXXXX..XXXXXXX 100644 | ||
166 | --- a/docs/system/riscv/microchip-icicle-kit.rst | ||
167 | +++ b/docs/system/riscv/microchip-icicle-kit.rst | ||
168 | @@ -XXX,XX +XXX,XX @@ Then we can boot the machine by: | ||
169 | -serial chardev:serial1 | ||
170 | |||
171 | With above command line, current terminal session will be used for the first | ||
172 | -serial port. Open another terminal window, and use `minicom` to connect the | ||
173 | +serial port. Open another terminal window, and use ``minicom`` to connect the | ||
174 | second serial port. | ||
175 | |||
176 | .. code-block:: bash | ||
177 | diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst | ||
178 | index XXXXXXX..XXXXXXX 100644 | ||
179 | --- a/docs/system/riscv/virt.rst | ||
180 | +++ b/docs/system/riscv/virt.rst | ||
181 | @@ -XXX,XX +XXX,XX @@ | ||
182 | 'virt' Generic Virtual Platform (``virt``) | ||
183 | ========================================== | ||
184 | |||
185 | -The `virt` board is a platform which does not correspond to any real hardware; | ||
186 | +The ``virt`` board is a platform which does not correspond to any real hardware; | ||
187 | it is designed for use in virtual machines. It is the recommended board type | ||
188 | if you simply want to run a guest such as Linux and do not care about | ||
189 | reproducing the idiosyncrasies and limitations of a particular bit of | ||
75 | -- | 190 | -- |
76 | 2.20.1 | 191 | 2.20.1 |
77 | 192 | ||
78 | 193 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The section describing the removed feature "-usbdevice ccid" had a |
---|---|---|---|
2 | typo so the markup started with single backtick and ended with double | ||
3 | backtick; fix it. | ||
2 | 4 | ||
3 | Make the output just a bit prettier when running by hand. | ||
4 | |||
5 | Cc: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200229012811.24129-13-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Message-id: 20210726142338.31872-10-peter.maydell@linaro.org | ||
10 | --- | 9 | --- |
11 | tests/tcg/aarch64/pauth-1.c | 2 +- | 10 | docs/about/removed-features.rst | 2 +- |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
13 | 12 | ||
14 | diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c | 13 | diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/tests/tcg/aarch64/pauth-1.c | 15 | --- a/docs/about/removed-features.rst |
17 | +++ b/tests/tcg/aarch64/pauth-1.c | 16 | +++ b/docs/about/removed-features.rst |
18 | @@ -XXX,XX +XXX,XX @@ int main() | 17 | @@ -XXX,XX +XXX,XX @@ devices. Drives the board doesn't pick up can no longer be used with |
19 | } | 18 | ''''''''''''''''''''''''''''''''''''' |
20 | 19 | ||
21 | perc = (float) count / (float) (TESTS * 2); | 20 | This option was undocumented and not used in the field. |
22 | - printf("Ptr Check: %0.2f%%", perc * 100.0); | 21 | -Use `-device usb-ccid`` instead. |
23 | + printf("Ptr Check: %0.2f%%\n", perc * 100.0); | 22 | +Use ``-device usb-ccid`` instead. |
24 | assert(perc > 0.95); | 23 | |
25 | return 0; | 24 | RISC-V firmware not booted by default (removed in 5.1) |
26 | } | 25 | '''''''''''''''''''''''''''''''''''''''''''''''''''''' |
27 | -- | 26 | -- |
28 | 2.20.1 | 27 | 2.20.1 |
29 | 28 | ||
30 | 29 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | The documentation of the posix_acl option has a stray backtick |
---|---|---|---|
2 | at the end of the text (which is rendered literally into the HTML). | ||
3 | Delete it. | ||
2 | 4 | ||
3 | Add support for the Versal LPD ADMAs. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> | ||
9 | Message-id: 20210726142338.31872-11-peter.maydell@linaro.org | ||
10 | --- | ||
11 | docs/tools/virtiofsd.rst | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
4 | 13 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 14 | diff --git a/docs/tools/virtiofsd.rst b/docs/tools/virtiofsd.rst |
6 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
7 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/arm/xlnx-versal.h | 6 ++++++ | ||
12 | hw/arm/xlnx-versal.c | 24 ++++++++++++++++++++++++ | ||
13 | 2 files changed, 30 insertions(+) | ||
14 | |||
15 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/xlnx-versal.h | 16 | --- a/docs/tools/virtiofsd.rst |
18 | +++ b/include/hw/arm/xlnx-versal.h | 17 | +++ b/docs/tools/virtiofsd.rst |
19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ Options |
20 | #define XLNX_VERSAL_NR_ACPUS 2 | 19 | default is ``no_xattr``. |
21 | #define XLNX_VERSAL_NR_UARTS 2 | 20 | |
22 | #define XLNX_VERSAL_NR_GEMS 2 | 21 | * posix_acl|no_posix_acl - |
23 | +#define XLNX_VERSAL_NR_ADMAS 8 | 22 | - Enable/disable posix acl support. Posix ACLs are disabled by default`. |
24 | #define XLNX_VERSAL_NR_IRQS 192 | 23 | + Enable/disable posix acl support. Posix ACLs are disabled by default. |
25 | 24 | ||
26 | typedef struct Versal { | 25 | .. option:: --socket-path=PATH |
27 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
28 | struct { | ||
29 | SysBusDevice *uart[XLNX_VERSAL_NR_UARTS]; | ||
30 | SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; | ||
31 | + SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; | ||
32 | } iou; | ||
33 | } lpd; | ||
34 | |||
35 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
36 | #define VERSAL_GEM0_WAKE_IRQ_0 57 | ||
37 | #define VERSAL_GEM1_IRQ_0 58 | ||
38 | #define VERSAL_GEM1_WAKE_IRQ_0 59 | ||
39 | +#define VERSAL_ADMA_IRQ_0 60 | ||
40 | |||
41 | /* Architecturally reserved IRQs suitable for virtualization. */ | ||
42 | #define VERSAL_RSVD_IRQ_FIRST 111 | ||
43 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
44 | #define MM_GEM1 0xff0d0000U | ||
45 | #define MM_GEM1_SIZE 0x10000 | ||
46 | |||
47 | +#define MM_ADMA_CH0 0xffa80000U | ||
48 | +#define MM_ADMA_CH0_SIZE 0x10000 | ||
49 | + | ||
50 | #define MM_OCM 0xfffc0000U | ||
51 | #define MM_OCM_SIZE 0x40000 | ||
52 | |||
53 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/arm/xlnx-versal.c | ||
56 | +++ b/hw/arm/xlnx-versal.c | ||
57 | @@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic) | ||
58 | } | ||
59 | } | ||
60 | |||
61 | +static void versal_create_admas(Versal *s, qemu_irq *pic) | ||
62 | +{ | ||
63 | + int i; | ||
64 | + | ||
65 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | ||
66 | + char *name = g_strdup_printf("adma%d", i); | ||
67 | + DeviceState *dev; | ||
68 | + MemoryRegion *mr; | ||
69 | + | ||
70 | + dev = qdev_create(NULL, "xlnx.zdma"); | ||
71 | + s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev); | ||
72 | + object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); | ||
73 | + qdev_init_nofail(dev); | ||
74 | + | ||
75 | + mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0); | ||
76 | + memory_region_add_subregion(&s->mr_ps, | ||
77 | + MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); | ||
78 | + | ||
79 | + sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]); | ||
80 | + g_free(name); | ||
81 | + } | ||
82 | +} | ||
83 | + | ||
84 | /* This takes the board allocated linear DDR memory and creates aliases | ||
85 | * for each split DDR range/aperture on the Versal address map. | ||
86 | */ | ||
87 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
88 | versal_create_apu_gic(s, pic); | ||
89 | versal_create_uarts(s, pic); | ||
90 | versal_create_gems(s, pic); | ||
91 | + versal_create_admas(s, pic); | ||
92 | versal_map_ddr(s); | ||
93 | versal_unimp(s); | ||
94 | 26 | ||
95 | -- | 27 | -- |
96 | 2.20.1 | 28 | 2.20.1 |
97 | 29 | ||
98 | 30 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
2 | 1 | ||
3 | Generate xlnx-versal-virt zdma FDT nodes. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
6 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
7 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/xlnx-versal-virt.c | 28 ++++++++++++++++++++++++++++ | ||
12 | 1 file changed, 28 insertions(+) | ||
13 | |||
14 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/xlnx-versal-virt.c | ||
17 | +++ b/hw/arm/xlnx-versal-virt.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_gem_nodes(VersalVirt *s) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | +static void fdt_add_zdma_nodes(VersalVirt *s) | ||
23 | +{ | ||
24 | + const char clocknames[] = "clk_main\0clk_apb"; | ||
25 | + const char compat[] = "xlnx,zynqmp-dma-1.0"; | ||
26 | + int i; | ||
27 | + | ||
28 | + for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { | ||
29 | + uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; | ||
30 | + char *name = g_strdup_printf("/dma@%" PRIx64, addr); | ||
31 | + | ||
32 | + qemu_fdt_add_subnode(s->fdt, name); | ||
33 | + | ||
34 | + qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); | ||
35 | + qemu_fdt_setprop_cells(s->fdt, name, "clocks", | ||
36 | + s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); | ||
37 | + qemu_fdt_setprop(s->fdt, name, "clock-names", | ||
38 | + clocknames, sizeof(clocknames)); | ||
39 | + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", | ||
40 | + GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, | ||
41 | + GIC_FDT_IRQ_FLAGS_LEVEL_HI); | ||
42 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", | ||
43 | + 2, addr, 2, 0x1000); | ||
44 | + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); | ||
45 | + g_free(name); | ||
46 | + } | ||
47 | +} | ||
48 | + | ||
49 | static void fdt_nop_memory_nodes(void *fdt, Error **errp) | ||
50 | { | ||
51 | Error *err = NULL; | ||
52 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | ||
53 | fdt_add_uart_nodes(s); | ||
54 | fdt_add_gic_nodes(s); | ||
55 | fdt_add_timer_nodes(s); | ||
56 | + fdt_add_zdma_nodes(s); | ||
57 | fdt_add_cpu_nodes(s, psci_conduit); | ||
58 | fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); | ||
59 | fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); | ||
60 | -- | ||
61 | 2.20.1 | ||
62 | |||
63 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Eric Auger <eric.auger@redhat.com> | ||
2 | 1 | ||
3 | Make sure a null SMMUPciBus is returned in case we were | ||
4 | not able to identify a pci bus matching the @bus_num. | ||
5 | |||
6 | This matches the fix done on intel iommu in commit: | ||
7 | a2e1cd41ccfe796529abfd1b6aeb1dd4393762a2 | ||
8 | |||
9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
10 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
11 | Message-Id: <20200226172628.17449-1-eric.auger@redhat.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/arm/smmu-common.c | 1 + | ||
17 | 1 file changed, 1 insertion(+) | ||
18 | |||
19 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/arm/smmu-common.c | ||
22 | +++ b/hw/arm/smmu-common.c | ||
23 | @@ -XXX,XX +XXX,XX @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num) | ||
24 | return smmu_pci_bus; | ||
25 | } | ||
26 | } | ||
27 | + smmu_pci_bus = NULL; | ||
28 | } | ||
29 | return smmu_pci_bus; | ||
30 | } | ||
31 | -- | ||
32 | 2.20.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | The smmu_find_smmu_pcibus() function was introduced (in commit | ||
4 | cac994ef43b) in a code format that could return an incorrect | ||
5 | pointer, which was then fixed by the previous commit. | ||
6 | We could have avoided this by writing the if() statement | ||
7 | differently. Do it now, in case this function is re-used. | ||
8 | The code is easier to review (harder to miss bugs). | ||
9 | |||
10 | Acked-by: Eric Auger <eric.auger@redhat.com> | ||
11 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
12 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/arm/smmu-common.c | 25 +++++++++++++------------ | ||
16 | 1 file changed, 13 insertions(+), 12 deletions(-) | ||
17 | |||
18 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/arm/smmu-common.c | ||
21 | +++ b/hw/arm/smmu-common.c | ||
22 | @@ -XXX,XX +XXX,XX @@ inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, | ||
23 | SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num) | ||
24 | { | ||
25 | SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num]; | ||
26 | + GHashTableIter iter; | ||
27 | |||
28 | - if (!smmu_pci_bus) { | ||
29 | - GHashTableIter iter; | ||
30 | - | ||
31 | - g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr); | ||
32 | - while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) { | ||
33 | - if (pci_bus_num(smmu_pci_bus->bus) == bus_num) { | ||
34 | - s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus; | ||
35 | - return smmu_pci_bus; | ||
36 | - } | ||
37 | - } | ||
38 | - smmu_pci_bus = NULL; | ||
39 | + if (smmu_pci_bus) { | ||
40 | + return smmu_pci_bus; | ||
41 | } | ||
42 | - return smmu_pci_bus; | ||
43 | + | ||
44 | + g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr); | ||
45 | + while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) { | ||
46 | + if (pci_bus_num(smmu_pci_bus->bus) == bus_num) { | ||
47 | + s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus; | ||
48 | + return smmu_pci_bus; | ||
49 | + } | ||
50 | + } | ||
51 | + | ||
52 | + return NULL; | ||
53 | } | ||
54 | |||
55 | static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | As the Connex and Verdex machines only boot in little-endian, | ||
4 | we can simplify the code. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/gumstix.c | 16 ++-------------- | ||
12 | 1 file changed, 2 insertions(+), 14 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/gumstix.c | ||
17 | +++ b/hw/arm/gumstix.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine) | ||
19 | { | ||
20 | PXA2xxState *cpu; | ||
21 | DriveInfo *dinfo; | ||
22 | - int be; | ||
23 | MemoryRegion *address_space_mem = get_system_memory(); | ||
24 | |||
25 | uint32_t connex_rom = 0x01000000; | ||
26 | @@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine) | ||
27 | exit(1); | ||
28 | } | ||
29 | |||
30 | -#ifdef TARGET_WORDS_BIGENDIAN | ||
31 | - be = 1; | ||
32 | -#else | ||
33 | - be = 0; | ||
34 | -#endif | ||
35 | if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, | ||
36 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
37 | - sector_len, 2, 0, 0, 0, 0, be)) { | ||
38 | + sector_len, 2, 0, 0, 0, 0, 0)) { | ||
39 | error_report("Error registering flash memory"); | ||
40 | exit(1); | ||
41 | } | ||
42 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | ||
43 | { | ||
44 | PXA2xxState *cpu; | ||
45 | DriveInfo *dinfo; | ||
46 | - int be; | ||
47 | MemoryRegion *address_space_mem = get_system_memory(); | ||
48 | |||
49 | uint32_t verdex_rom = 0x02000000; | ||
50 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | ||
51 | exit(1); | ||
52 | } | ||
53 | |||
54 | -#ifdef TARGET_WORDS_BIGENDIAN | ||
55 | - be = 1; | ||
56 | -#else | ||
57 | - be = 0; | ||
58 | -#endif | ||
59 | if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, | ||
60 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
61 | - sector_len, 2, 0, 0, 0, 0, be)) { | ||
62 | + sector_len, 2, 0, 0, 0, 0, 0)) { | ||
63 | error_report("Error registering flash memory"); | ||
64 | exit(1); | ||
65 | } | ||
66 | -- | ||
67 | 2.20.1 | ||
68 | |||
69 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | We only build the little-endian softmmu configurations. Checking | ||
4 | for big endian is pointless, remove the unused code. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/mainstone.c | 8 +------- | ||
11 | 1 file changed, 1 insertion(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/mainstone.c | ||
16 | +++ b/hw/arm/mainstone.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem, | ||
18 | DeviceState *mst_irq; | ||
19 | DriveInfo *dinfo; | ||
20 | int i; | ||
21 | - int be; | ||
22 | MemoryRegion *rom = g_new(MemoryRegion, 1); | ||
23 | |||
24 | /* Setup CPU & memory */ | ||
25 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem, | ||
26 | memory_region_set_readonly(rom, true); | ||
27 | memory_region_add_subregion(address_space_mem, 0, rom); | ||
28 | |||
29 | -#ifdef TARGET_WORDS_BIGENDIAN | ||
30 | - be = 1; | ||
31 | -#else | ||
32 | - be = 0; | ||
33 | -#endif | ||
34 | /* There are two 32MiB flash devices on the board */ | ||
35 | for (i = 0; i < 2; i ++) { | ||
36 | dinfo = drive_get(IF_PFLASH, 0, i); | ||
37 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem, | ||
38 | i ? "mainstone.flash1" : "mainstone.flash0", | ||
39 | MAINSTONE_FLASH, | ||
40 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
41 | - sector_len, 4, 0, 0, 0, 0, be)) { | ||
42 | + sector_len, 4, 0, 0, 0, 0, 0)) { | ||
43 | error_report("Error registering flash memory"); | ||
44 | exit(1); | ||
45 | } | ||
46 | -- | ||
47 | 2.20.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | We only build the little-endian softmmu configurations. Checking | ||
4 | for big endian is pointless, remove the unused code. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/omap_sx1.c | 11 ++--------- | ||
11 | 1 file changed, 2 insertions(+), 9 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/omap_sx1.c | ||
16 | +++ b/hw/arm/omap_sx1.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
18 | DriveInfo *dinfo; | ||
19 | int fl_idx; | ||
20 | uint32_t flash_size = flash0_size; | ||
21 | - int be; | ||
22 | |||
23 | if (machine->ram_size != mc->default_ram_size) { | ||
24 | char *sz = size_to_str(mc->default_ram_size); | ||
25 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
26 | OMAP_CS2_BASE, &cs[3]); | ||
27 | |||
28 | fl_idx = 0; | ||
29 | -#ifdef TARGET_WORDS_BIGENDIAN | ||
30 | - be = 1; | ||
31 | -#else | ||
32 | - be = 0; | ||
33 | -#endif | ||
34 | - | ||
35 | if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { | ||
36 | if (!pflash_cfi01_register(OMAP_CS0_BASE, | ||
37 | "omap_sx1.flash0-1", flash_size, | ||
38 | blk_by_legacy_dinfo(dinfo), | ||
39 | - sector_size, 4, 0, 0, 0, 0, be)) { | ||
40 | + sector_size, 4, 0, 0, 0, 0, 0)) { | ||
41 | fprintf(stderr, "qemu: Error registering flash memory %d.\n", | ||
42 | fl_idx); | ||
43 | } | ||
44 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
45 | if (!pflash_cfi01_register(OMAP_CS1_BASE, | ||
46 | "omap_sx1.flash1-1", flash1_size, | ||
47 | blk_by_legacy_dinfo(dinfo), | ||
48 | - sector_size, 4, 0, 0, 0, 0, be)) { | ||
49 | + sector_size, 4, 0, 0, 0, 0, 0)) { | ||
50 | fprintf(stderr, "qemu: Error registering flash memory %d.\n", | ||
51 | fl_idx); | ||
52 | } | ||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
2 | 1 | ||
3 | We only build the little-endian softmmu configurations. Checking | ||
4 | for big endian is pointless, remove the unused code. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/z2.c | 8 +------- | ||
11 | 1 file changed, 1 insertion(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/z2.c | ||
16 | +++ b/hw/arm/z2.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine) | ||
18 | uint32_t sector_len = 0x10000; | ||
19 | PXA2xxState *mpu; | ||
20 | DriveInfo *dinfo; | ||
21 | - int be; | ||
22 | void *z2_lcd; | ||
23 | I2CBus *bus; | ||
24 | DeviceState *wm; | ||
25 | @@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine) | ||
26 | /* Setup CPU & memory */ | ||
27 | mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); | ||
28 | |||
29 | -#ifdef TARGET_WORDS_BIGENDIAN | ||
30 | - be = 1; | ||
31 | -#else | ||
32 | - be = 0; | ||
33 | -#endif | ||
34 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
35 | if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, | ||
36 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
37 | - sector_len, 4, 0, 0, 0, 0, be)) { | ||
38 | + sector_len, 4, 0, 0, 0, 0, 0)) { | ||
39 | error_report("Error registering flash memory"); | ||
40 | exit(1); | ||
41 | } | ||
42 | -- | ||
43 | 2.20.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Pan Nengyuan <pannengyuan@huawei.com> | ||
2 | 1 | ||
3 | There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. | ||
4 | |||
5 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
6 | Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> | ||
7 | Message-id: 20200227025055.14341-3-pannengyuan@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/pxa2xx.c | 17 +++++++++++------ | ||
12 | 1 file changed, 11 insertions(+), 6 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/pxa2xx.c | ||
17 | +++ b/hw/arm/pxa2xx.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_init(Object *obj) | ||
19 | s->last_rtcpicr = 0; | ||
20 | s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); | ||
21 | |||
22 | + sysbus_init_irq(dev, &s->rtc_irq); | ||
23 | + | ||
24 | + memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, | ||
25 | + "pxa2xx-rtc", 0x10000); | ||
26 | + sysbus_init_mmio(dev, &s->iomem); | ||
27 | +} | ||
28 | + | ||
29 | +static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) | ||
30 | +{ | ||
31 | + PXA2xxRTCState *s = PXA2XX_RTC(dev); | ||
32 | s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); | ||
33 | s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); | ||
34 | s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); | ||
35 | s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); | ||
36 | s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); | ||
37 | s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); | ||
38 | - | ||
39 | - sysbus_init_irq(dev, &s->rtc_irq); | ||
40 | - | ||
41 | - memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, | ||
42 | - "pxa2xx-rtc", 0x10000); | ||
43 | - sysbus_init_mmio(dev, &s->iomem); | ||
44 | } | ||
45 | |||
46 | static int pxa2xx_rtc_pre_save(void *opaque) | ||
47 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) | ||
48 | |||
49 | dc->desc = "PXA2xx RTC Controller"; | ||
50 | dc->vmsd = &vmstate_pxa2xx_rtc_regs; | ||
51 | + dc->realize = pxa2xx_rtc_realize; | ||
52 | } | ||
53 | |||
54 | static const TypeInfo pxa2xx_rtc_sysbus_info = { | ||
55 | -- | ||
56 | 2.20.1 | ||
57 | |||
58 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Pan Nengyuan <pannengyuan@huawei.com> | ||
2 | 1 | ||
3 | There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. | ||
4 | |||
5 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
6 | Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> | ||
7 | Message-id: 20200227025055.14341-4-pannengyuan@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/spitz.c | 8 +++++++- | ||
12 | 1 file changed, 7 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/spitz.c | ||
17 | +++ b/hw/arm/spitz.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_init(Object *obj) | ||
19 | |||
20 | spitz_keyboard_pre_map(s); | ||
21 | |||
22 | - s->kbdtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, spitz_keyboard_tick, s); | ||
23 | qdev_init_gpio_in(dev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM); | ||
24 | qdev_init_gpio_out(dev, s->sense, SPITZ_KEY_SENSE_NUM); | ||
25 | } | ||
26 | |||
27 | +static void spitz_keyboard_realize(DeviceState *dev, Error **errp) | ||
28 | +{ | ||
29 | + SpitzKeyboardState *s = SPITZ_KEYBOARD(dev); | ||
30 | + s->kbdtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, spitz_keyboard_tick, s); | ||
31 | +} | ||
32 | + | ||
33 | /* LCD backlight controller */ | ||
34 | |||
35 | #define LCDTG_RESCTL 0x00 | ||
36 | @@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_class_init(ObjectClass *klass, void *data) | ||
37 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
38 | |||
39 | dc->vmsd = &vmstate_spitz_kbd; | ||
40 | + dc->realize = spitz_keyboard_realize; | ||
41 | } | ||
42 | |||
43 | static const TypeInfo spitz_keyboard_info = { | ||
44 | -- | ||
45 | 2.20.1 | ||
46 | |||
47 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Pan Nengyuan <pannengyuan@huawei.com> | ||
2 | 1 | ||
3 | There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. | ||
4 | |||
5 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
6 | Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> | ||
7 | Message-id: 20200227025055.14341-5-pannengyuan@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/strongarm.c | 18 ++++++++++++------ | ||
12 | 1 file changed, 12 insertions(+), 6 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/strongarm.c | ||
17 | +++ b/hw/arm/strongarm.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void strongarm_rtc_init(Object *obj) | ||
19 | s->last_rcnr = (uint32_t) mktimegm(&tm); | ||
20 | s->last_hz = qemu_clock_get_ms(rtc_clock); | ||
21 | |||
22 | - s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); | ||
23 | - s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); | ||
24 | - | ||
25 | sysbus_init_irq(dev, &s->rtc_irq); | ||
26 | sysbus_init_irq(dev, &s->rtc_hz_irq); | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ static void strongarm_rtc_init(Object *obj) | ||
29 | sysbus_init_mmio(dev, &s->iomem); | ||
30 | } | ||
31 | |||
32 | +static void strongarm_rtc_realize(DeviceState *dev, Error **errp) | ||
33 | +{ | ||
34 | + StrongARMRTCState *s = STRONGARM_RTC(dev); | ||
35 | + s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); | ||
36 | + s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); | ||
37 | +} | ||
38 | + | ||
39 | static int strongarm_rtc_pre_save(void *opaque) | ||
40 | { | ||
41 | StrongARMRTCState *s = opaque; | ||
42 | @@ -XXX,XX +XXX,XX @@ static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) | ||
43 | |||
44 | dc->desc = "StrongARM RTC Controller"; | ||
45 | dc->vmsd = &vmstate_strongarm_rtc_regs; | ||
46 | + dc->realize = strongarm_rtc_realize; | ||
47 | } | ||
48 | |||
49 | static const TypeInfo strongarm_rtc_sysbus_info = { | ||
50 | @@ -XXX,XX +XXX,XX @@ static void strongarm_uart_init(Object *obj) | ||
51 | "uart", 0x10000); | ||
52 | sysbus_init_mmio(dev, &s->iomem); | ||
53 | sysbus_init_irq(dev, &s->irq); | ||
54 | - | ||
55 | - s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); | ||
56 | - s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); | ||
57 | } | ||
58 | |||
59 | static void strongarm_uart_realize(DeviceState *dev, Error **errp) | ||
60 | { | ||
61 | StrongARMUARTState *s = STRONGARM_UART(dev); | ||
62 | |||
63 | + s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | ||
64 | + strongarm_uart_rx_to, | ||
65 | + s); | ||
66 | + s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); | ||
67 | qemu_chr_fe_set_handlers(&s->chr, | ||
68 | strongarm_uart_can_receive, | ||
69 | strongarm_uart_receive, | ||
70 | -- | ||
71 | 2.20.1 | ||
72 | |||
73 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Pan Nengyuan <pannengyuan@huawei.com> | ||
2 | 1 | ||
3 | There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. | ||
4 | |||
5 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
6 | Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-id: 20200227025055.14341-7-pannengyuan@huawei.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/timer/cadence_ttc.c | 18 ++++++++++++------ | ||
13 | 1 file changed, 12 insertions(+), 6 deletions(-) | ||
14 | |||
15 | diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/timer/cadence_ttc.c | ||
18 | +++ b/hw/timer/cadence_ttc.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void cadence_timer_init(uint32_t freq, CadenceTimerState *s) | ||
20 | static void cadence_ttc_init(Object *obj) | ||
21 | { | ||
22 | CadenceTTCState *s = CADENCE_TTC(obj); | ||
23 | - int i; | ||
24 | - | ||
25 | - for (i = 0; i < 3; ++i) { | ||
26 | - cadence_timer_init(133000000, &s->timer[i]); | ||
27 | - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq); | ||
28 | - } | ||
29 | |||
30 | memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s, | ||
31 | "timer", 0x1000); | ||
32 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | ||
33 | } | ||
34 | |||
35 | +static void cadence_ttc_realize(DeviceState *dev, Error **errp) | ||
36 | +{ | ||
37 | + CadenceTTCState *s = CADENCE_TTC(dev); | ||
38 | + int i; | ||
39 | + | ||
40 | + for (i = 0; i < 3; ++i) { | ||
41 | + cadence_timer_init(133000000, &s->timer[i]); | ||
42 | + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->timer[i].irq); | ||
43 | + } | ||
44 | +} | ||
45 | + | ||
46 | static int cadence_timer_pre_save(void *opaque) | ||
47 | { | ||
48 | cadence_timer_sync((CadenceTimerState *)opaque); | ||
49 | @@ -XXX,XX +XXX,XX @@ static void cadence_ttc_class_init(ObjectClass *klass, void *data) | ||
50 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
51 | |||
52 | dc->vmsd = &vmstate_cadence_ttc; | ||
53 | + dc->realize = cadence_ttc_realize; | ||
54 | } | ||
55 | |||
56 | static const TypeInfo cadence_ttc_info = { | ||
57 | -- | ||
58 | 2.20.1 | ||
59 | |||
60 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Don't merely start with v8.0, handle v7VE as well. Ensure that writes | ||
4 | from aarch32 mode do not change bits in the other half of the register. | ||
5 | Protect reads of aa64 id registers with ARM_FEATURE_AARCH64. | ||
6 | |||
7 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200229012811.24129-2-richard.henderson@linaro.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/helper.c | 38 +++++++++++++++++++++++++------------- | ||
14 | 1 file changed, 25 insertions(+), 13 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/helper.c | ||
19 | +++ b/target/arm/helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
21 | REGINFO_SENTINEL | ||
22 | }; | ||
23 | |||
24 | -static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
25 | +static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
26 | { | ||
27 | ARMCPU *cpu = env_archcpu(env); | ||
28 | - /* Begin with bits defined in base ARMv8.0. */ | ||
29 | - uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); | ||
30 | + | ||
31 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
32 | + valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | ||
33 | + } else { | ||
34 | + valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | ||
35 | + } | ||
36 | |||
37 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
38 | valid_mask &= ~HCR_HCD; | ||
39 | @@ -XXX,XX +XXX,XX @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
40 | */ | ||
41 | valid_mask &= ~HCR_TSC; | ||
42 | } | ||
43 | - if (cpu_isar_feature(aa64_vh, cpu)) { | ||
44 | - valid_mask |= HCR_E2H; | ||
45 | - } | ||
46 | - if (cpu_isar_feature(aa64_lor, cpu)) { | ||
47 | - valid_mask |= HCR_TLOR; | ||
48 | - } | ||
49 | - if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
50 | - valid_mask |= HCR_API | HCR_APK; | ||
51 | + | ||
52 | + if (arm_feature(env, ARM_FEATURE_AARCH64)) { | ||
53 | + if (cpu_isar_feature(aa64_vh, cpu)) { | ||
54 | + valid_mask |= HCR_E2H; | ||
55 | + } | ||
56 | + if (cpu_isar_feature(aa64_lor, cpu)) { | ||
57 | + valid_mask |= HCR_TLOR; | ||
58 | + } | ||
59 | + if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
60 | + valid_mask |= HCR_API | HCR_APK; | ||
61 | + } | ||
62 | } | ||
63 | |||
64 | /* Clear RES0 bits. */ | ||
65 | @@ -XXX,XX +XXX,XX @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
66 | arm_cpu_update_vfiq(cpu); | ||
67 | } | ||
68 | |||
69 | +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
70 | +{ | ||
71 | + do_hcr_write(env, value, 0); | ||
72 | +} | ||
73 | + | ||
74 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, | ||
75 | uint64_t value) | ||
76 | { | ||
77 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | ||
78 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | ||
79 | - hcr_write(env, NULL, value); | ||
80 | + do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); | ||
81 | } | ||
82 | |||
83 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | ||
84 | @@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | ||
85 | { | ||
86 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | ||
87 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | ||
88 | - hcr_write(env, NULL, value); | ||
89 | + do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); | ||
90 | } | ||
91 | |||
92 | /* | ||
93 | -- | ||
94 | 2.20.1 | ||
95 | |||
96 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20200229012811.24129-3-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 7 +++++++ | ||
9 | 1 file changed, 7 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | ||
16 | #define HCR_TERR (1ULL << 36) | ||
17 | #define HCR_TEA (1ULL << 37) | ||
18 | #define HCR_MIOCNCE (1ULL << 38) | ||
19 | +/* RES0 bit 39 */ | ||
20 | #define HCR_APK (1ULL << 40) | ||
21 | #define HCR_API (1ULL << 41) | ||
22 | #define HCR_NV (1ULL << 42) | ||
23 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | ||
24 | #define HCR_NV2 (1ULL << 45) | ||
25 | #define HCR_FWB (1ULL << 46) | ||
26 | #define HCR_FIEN (1ULL << 47) | ||
27 | +/* RES0 bit 48 */ | ||
28 | #define HCR_TID4 (1ULL << 49) | ||
29 | #define HCR_TICAB (1ULL << 50) | ||
30 | +#define HCR_AMVOFFEN (1ULL << 51) | ||
31 | #define HCR_TOCU (1ULL << 52) | ||
32 | +#define HCR_ENSCXT (1ULL << 53) | ||
33 | #define HCR_TTLBIS (1ULL << 54) | ||
34 | #define HCR_TTLBOS (1ULL << 55) | ||
35 | #define HCR_ATA (1ULL << 56) | ||
36 | #define HCR_DCT (1ULL << 57) | ||
37 | +#define HCR_TID5 (1ULL << 58) | ||
38 | +#define HCR_TWEDEN (1ULL << 59) | ||
39 | +#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) | ||
40 | |||
41 | #define SCR_NS (1U << 0) | ||
42 | #define SCR_IRQ (1U << 1) | ||
43 | -- | ||
44 | 2.20.1 | ||
45 | |||
46 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | In arm_cpu_reset, we configure many system registers so that user-only | ||
4 | behaves as it should with a minimum of ifdefs. However, we do not set | ||
5 | all of the system registers as required for a cpu with EL2 and EL3. | ||
6 | |||
7 | Disabling EL2 and EL3 mean that we will not look at those registers, | ||
8 | which means that we don't have to worry about configuring them. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20200229012811.24129-4-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/cpu.c | 6 ++++-- | ||
16 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpu.c | ||
21 | +++ b/target/arm/cpu.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_reset_hivecs_property = | ||
23 | static Property arm_cpu_rvbar_property = | ||
24 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | ||
25 | |||
26 | +#ifndef CONFIG_USER_ONLY | ||
27 | static Property arm_cpu_has_el2_property = | ||
28 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | ||
29 | |||
30 | static Property arm_cpu_has_el3_property = | ||
31 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | ||
32 | +#endif | ||
33 | |||
34 | static Property arm_cpu_cfgend_property = | ||
35 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | ||
36 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | ||
37 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); | ||
38 | } | ||
39 | |||
40 | +#ifndef CONFIG_USER_ONLY | ||
41 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | ||
42 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | ||
43 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | ||
44 | */ | ||
45 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); | ||
46 | |||
47 | -#ifndef CONFIG_USER_ONLY | ||
48 | object_property_add_link(obj, "secure-memory", | ||
49 | TYPE_MEMORY_REGION, | ||
50 | (Object **)&cpu->secure_memory, | ||
51 | qdev_prop_allow_set_link_before_realize, | ||
52 | OBJ_PROP_LINK_STRONG, | ||
53 | &error_abort); | ||
54 | -#endif | ||
55 | } | ||
56 | |||
57 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { | ||
58 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); | ||
59 | } | ||
60 | +#endif | ||
61 | |||
62 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { | ||
63 | cpu->has_pmu = true; | ||
64 | -- | ||
65 | 2.20.1 | ||
66 | |||
67 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | We have disabled EL2 and EL3 for user-only, which means that these | ||
4 | registers "don't exist" and should not be set. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200229012811.24129-5-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.c | 6 ------ | ||
12 | 1 file changed, 6 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
19 | /* Enable all PAC keys. */ | ||
20 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | ||
21 | SCTLR_EnDA | SCTLR_EnDB); | ||
22 | - /* Enable all PAC instructions */ | ||
23 | - env->cp15.hcr_el2 |= HCR_API; | ||
24 | - env->cp15.scr_el3 |= SCR_API; | ||
25 | /* and to the FP/Neon instructions */ | ||
26 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); | ||
27 | /* and to the SVE instructions */ | ||
28 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | ||
29 | - env->cp15.cptr_el[3] |= CPTR_EZ; | ||
30 | /* with maximum vector length */ | ||
31 | env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? | ||
32 | cpu->sve_max_vq - 1 : 0; | ||
33 | - env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; | ||
34 | - env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; | ||
35 | /* | ||
36 | * Enable TBI0 and TBI1. While the real kernel only enables TBI0, | ||
37 | * turning on both here will produce smaller code and otherwise | ||
38 | -- | ||
39 | 2.20.1 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Update the {TGE,E2H} == '11' masking to ARMv8.6. | ||
4 | If EL2 is configured for aarch32, disable all of | ||
5 | the bits that are RES0 in aarch32 mode. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200229012811.24129-6-richard.henderson@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper.c | 31 +++++++++++++++++++++++++++---- | ||
13 | 1 file changed, 27 insertions(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.c | ||
18 | +++ b/target/arm/helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) | ||
20 | * Since the v8.4 language applies to the entire register, and | ||
21 | * appears to be backward compatible, use that. | ||
22 | */ | ||
23 | - ret = 0; | ||
24 | - } else if (ret & HCR_TGE) { | ||
25 | - /* These bits are up-to-date as of ARMv8.4. */ | ||
26 | + return 0; | ||
27 | + } | ||
28 | + | ||
29 | + /* | ||
30 | + * For a cpu that supports both aarch64 and aarch32, we can set bits | ||
31 | + * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | ||
32 | + * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | ||
33 | + */ | ||
34 | + if (!arm_el_is_aa64(env, 2)) { | ||
35 | + uint64_t aa32_valid; | ||
36 | + | ||
37 | + /* | ||
38 | + * These bits are up-to-date as of ARMv8.6. | ||
39 | + * For HCR, it's easiest to list just the 2 bits that are invalid. | ||
40 | + * For HCR2, list those that are valid. | ||
41 | + */ | ||
42 | + aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | ||
43 | + aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | ||
44 | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | ||
45 | + ret &= aa32_valid; | ||
46 | + } | ||
47 | + | ||
48 | + if (ret & HCR_TGE) { | ||
49 | + /* These bits are up-to-date as of ARMv8.6. */ | ||
50 | if (ret & HCR_E2H) { | ||
51 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | ||
52 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | ||
53 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | ||
54 | - HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); | ||
55 | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | | ||
56 | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | ||
57 | + HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | ||
58 | } else { | ||
59 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | ||
60 | } | ||
61 | -- | ||
62 | 2.20.1 | ||
63 | |||
64 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | If the user provides both a BIOS/firmware image and also a guest |
---|---|---|---|
2 | kernel filename, arm_setup_firmware_boot() will pass the | ||
3 | kernel image to the firmware via the fw_cfg device. However we | ||
4 | weren't checking whether there really was a fw_cfg device present, | ||
5 | and if there wasn't we would crash. | ||
2 | 6 | ||
3 | This bit traps EL1 access to cache maintenance insns that operate | 7 | This crash can be provoked with a command line such as |
4 | to the point of coherency or persistence. | 8 | qemu-system-aarch64 -M raspi3 -kernel /dev/null -bios /dev/null -display none |
5 | 9 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | It is currently only possible on the raspi3 machine, because unless |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | the machine sets info->firmware_loaded we won't call |
8 | Message-id: 20200229012811.24129-10-richard.henderson@linaro.org | 12 | arm_setup_firmware_boot(), and the only machines which set that are: |
13 | * virt (has a fw-cfg device) | ||
14 | * sbsa-ref (checks itself for kernel_filename && firmware_loaded) | ||
15 | * raspi3 (crashes) | ||
16 | |||
17 | But this is an unfortunate beartrap to leave for future machine | ||
18 | model implementors, so we should handle this situation in boot.c. | ||
19 | |||
20 | Check in arm_setup_firmware_boot() whether the fw-cfg device exists | ||
21 | before trying to load files into it, and if it doesn't exist then | ||
22 | exit with a hopefully helpful error message. | ||
23 | |||
24 | Because we now handle this check in a machine-agnostic way, we | ||
25 | can remove the check from sbsa-ref. | ||
26 | |||
27 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/503 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
29 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
31 | Message-id: 20210726163351.32086-1-peter.maydell@linaro.org | ||
10 | --- | 32 | --- |
11 | target/arm/helper.c | 39 +++++++++++++++++++++++++++++++-------- | 33 | hw/arm/boot.c | 9 +++++++++ |
12 | 1 file changed, 31 insertions(+), 8 deletions(-) | 34 | hw/arm/sbsa-ref.c | 7 ------- |
35 | 2 files changed, 9 insertions(+), 7 deletions(-) | ||
13 | 36 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 37 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
15 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 39 | --- a/hw/arm/boot.c |
17 | +++ b/target/arm/helper.c | 40 | +++ b/hw/arm/boot.c |
18 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, | 41 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) |
19 | return CP_ACCESS_OK; | 42 | bool try_decompressing_kernel; |
20 | } | 43 | |
21 | 44 | fw_cfg = fw_cfg_find(); | |
22 | +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, | 45 | + |
23 | + const ARMCPRegInfo *ri, | 46 | + if (!fw_cfg) { |
24 | + bool isread) | 47 | + error_report("This machine type does not support loading both " |
25 | +{ | 48 | + "a guest firmware/BIOS image and a guest kernel at " |
26 | + /* Cache invalidate/clean to Point of Coherency or Persistence... */ | 49 | + "the same time. You should change your QEMU command " |
27 | + switch (arm_current_el(env)) { | 50 | + "line to specify one or the other, but not both."); |
28 | + case 0: | 51 | + exit(1); |
29 | + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | ||
30 | + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | ||
31 | + return CP_ACCESS_TRAP; | ||
32 | + } | 52 | + } |
33 | + /* fall through */ | ||
34 | + case 1: | ||
35 | + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | ||
36 | + if (arm_hcr_el2_eff(env) & HCR_TPCP) { | ||
37 | + return CP_ACCESS_TRAP_EL2; | ||
38 | + } | ||
39 | + break; | ||
40 | + } | ||
41 | + return CP_ACCESS_OK; | ||
42 | +} | ||
43 | + | 53 | + |
44 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions | 54 | try_decompressing_kernel = arm_feature(&cpu->env, |
45 | * Page D4-1736 (DDI0487A.b) | 55 | ARM_FEATURE_AARCH64); |
46 | */ | 56 | |
47 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 57 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
48 | .accessfn = aa64_cacheop_access }, | 58 | index XXXXXXX..XXXXXXX 100644 |
49 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | 59 | --- a/hw/arm/sbsa-ref.c |
50 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | 60 | +++ b/hw/arm/sbsa-ref.c |
51 | - .access = PL1_W, .type = ARM_CP_NOP }, | 61 | @@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine) |
52 | + .access = PL1_W, .accessfn = aa64_cacheop_poc_access, | 62 | |
53 | + .type = ARM_CP_NOP }, | 63 | firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); |
54 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | 64 | |
55 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | 65 | - if (machine->kernel_filename && firmware_loaded) { |
56 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | 66 | - error_report("sbsa-ref: No fw_cfg device on this machine, " |
57 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | 67 | - "so -kernel option is not supported when firmware loaded, " |
58 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | 68 | - "please load OS from hard disk instead"); |
59 | .access = PL0_W, .type = ARM_CP_NOP, | 69 | - exit(1); |
60 | - .accessfn = aa64_cacheop_access }, | 70 | - } |
61 | + .accessfn = aa64_cacheop_poc_access }, | 71 | - |
62 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | 72 | /* |
63 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | 73 | * This machine has EL3 enabled, external firmware should supply PSCI |
64 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | 74 | * implementation, so the QEMU's internal PSCI is disabled. |
65 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
66 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | ||
67 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | ||
68 | .access = PL0_W, .type = ARM_CP_NOP, | ||
69 | - .accessfn = aa64_cacheop_access }, | ||
70 | + .accessfn = aa64_cacheop_poc_access }, | ||
71 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | ||
72 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | ||
73 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | ||
74 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
75 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | ||
76 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
77 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | ||
78 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
79 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, | ||
80 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | ||
81 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
82 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | ||
83 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
84 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, | ||
85 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | ||
86 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
87 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | ||
88 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
89 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | ||
90 | - .type = ARM_CP_NOP, .access = PL1_W }, | ||
91 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, | ||
92 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | ||
93 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
94 | /* MMU Domain access control / MPU write buffer control */ | ||
95 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = { | ||
96 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | ||
97 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | ||
98 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | ||
99 | - .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn }, | ||
100 | + .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
101 | REGINFO_SENTINEL | ||
102 | }; | ||
103 | |||
104 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = { | ||
105 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | ||
106 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | ||
107 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | ||
108 | - .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn }, | ||
109 | + .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
110 | REGINFO_SENTINEL | ||
111 | }; | ||
112 | #endif /*CONFIG_USER_ONLY*/ | ||
113 | -- | 75 | -- |
114 | 2.20.1 | 76 | 2.20.1 |
115 | 77 | ||
116 | 78 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Move bootindex.txt into the system section of the manual and turn it |
---|---|---|---|
2 | into rST format. To make the document make more sense in the context | ||
3 | of the system manual, expand the title and introductory paragraphs to | ||
4 | give more context. | ||
2 | 5 | ||
3 | This bit traps EL1 access to the auxiliary control registers. | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
8 | Message-id: 20210727194955.7764-1-peter.maydell@linaro.org | ||
9 | --- | ||
10 | docs/bootindex.txt | 52 --------------------------- | ||
11 | docs/system/bootindex.rst | 76 +++++++++++++++++++++++++++++++++++++++ | ||
12 | docs/system/index.rst | 1 + | ||
13 | 3 files changed, 77 insertions(+), 52 deletions(-) | ||
14 | delete mode 100644 docs/bootindex.txt | ||
15 | create mode 100644 docs/system/bootindex.rst | ||
4 | 16 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | diff --git a/docs/bootindex.txt b/docs/bootindex.txt |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 18 | deleted file mode 100644 |
7 | Message-id: 20200229012811.24129-9-richard.henderson@linaro.org | 19 | index XXXXXXX..XXXXXXX |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | --- a/docs/bootindex.txt |
9 | --- | 21 | +++ /dev/null |
10 | target/arm/helper.c | 18 ++++++++++++++---- | 22 | @@ -XXX,XX +XXX,XX @@ |
11 | 1 file changed, 14 insertions(+), 4 deletions(-) | 23 | -= Bootindex property = |
12 | 24 | - | |
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 25 | -Block and net devices have bootindex property. This property is used to |
26 | -determine the order in which firmware will consider devices for booting | ||
27 | -the guest OS. If the bootindex property is not set for a device, it gets | ||
28 | -lowest boot priority. There is no particular order in which devices with | ||
29 | -unset bootindex property will be considered for booting, but they will | ||
30 | -still be bootable. | ||
31 | - | ||
32 | -== Example == | ||
33 | - | ||
34 | -Let's assume we have a QEMU machine with two NICs (virtio, e1000) and two | ||
35 | -disks (IDE, virtio): | ||
36 | - | ||
37 | -qemu -drive file=disk1.img,if=none,id=disk1 | ||
38 | - -device ide-hd,drive=disk1,bootindex=4 | ||
39 | - -drive file=disk2.img,if=none,id=disk2 | ||
40 | - -device virtio-blk-pci,drive=disk2,bootindex=3 | ||
41 | - -netdev type=user,id=net0 -device virtio-net-pci,netdev=net0,bootindex=2 | ||
42 | - -netdev type=user,id=net1 -device e1000,netdev=net1,bootindex=1 | ||
43 | - | ||
44 | -Given the command above, firmware should try to boot from the e1000 NIC | ||
45 | -first. If this fails, it should try the virtio NIC next; if this fails | ||
46 | -too, it should try the virtio disk, and then the IDE disk. | ||
47 | - | ||
48 | -== Limitations == | ||
49 | - | ||
50 | -1. Some firmware has limitations on which devices can be considered for | ||
51 | -booting. For instance, the PC BIOS boot specification allows only one | ||
52 | -disk to be bootable. If boot from disk fails for some reason, the BIOS | ||
53 | -won't retry booting from other disk. It can still try to boot from | ||
54 | -floppy or net, though. | ||
55 | - | ||
56 | -2. Sometimes, firmware cannot map the device path QEMU wants firmware to | ||
57 | -boot from to a boot method. It doesn't happen for devices the firmware | ||
58 | -can natively boot from, but if firmware relies on an option ROM for | ||
59 | -booting, and the same option ROM is used for booting from more then one | ||
60 | -device, the firmware may not be able to ask the option ROM to boot from | ||
61 | -a particular device reliably. For instance with the PC BIOS, if a SCSI HBA | ||
62 | -has three bootable devices target1, target3, target5 connected to it, | ||
63 | -the option ROM will have a boot method for each of them, but it is not | ||
64 | -possible to map from boot method back to a specific target. This is a | ||
65 | -shortcoming of the PC BIOS boot specification. | ||
66 | - | ||
67 | -== Mixing bootindex and boot order parameters == | ||
68 | - | ||
69 | -Note that it does not make sense to use the bootindex property together | ||
70 | -with the "-boot order=..." (or "-boot once=...") parameter. The guest | ||
71 | -firmware implementations normally either support the one or the other, | ||
72 | -but not both parameters at the same time. Mixing them will result in | ||
73 | -undefined behavior, and thus the guest firmware will likely not boot | ||
74 | -from the expected devices. | ||
75 | diff --git a/docs/system/bootindex.rst b/docs/system/bootindex.rst | ||
76 | new file mode 100644 | ||
77 | index XXXXXXX..XXXXXXX | ||
78 | --- /dev/null | ||
79 | +++ b/docs/system/bootindex.rst | ||
80 | @@ -XXX,XX +XXX,XX @@ | ||
81 | +Managing device boot order with bootindex properties | ||
82 | +==================================================== | ||
83 | + | ||
84 | +QEMU can tell QEMU-aware guest firmware (like the x86 PC BIOS) | ||
85 | +which order it should look for a bootable OS on which devices. | ||
86 | +A simple way to set this order is to use the ``-boot order=`` option, | ||
87 | +but you can also do this more flexibly, by setting a ``bootindex`` | ||
88 | +property on the individual block or net devices you specify | ||
89 | +on the QEMU command line. | ||
90 | + | ||
91 | +The ``bootindex`` properties are used to determine the order in which | ||
92 | +firmware will consider devices for booting the guest OS. If the | ||
93 | +``bootindex`` property is not set for a device, it gets the lowest | ||
94 | +boot priority. There is no particular order in which devices with no | ||
95 | +``bootindex`` property set will be considered for booting, but they | ||
96 | +will still be bootable. | ||
97 | + | ||
98 | +Some guest machine types (for instance the s390x machines) do | ||
99 | +not support ``-boot order=``; on those machines you must always | ||
100 | +use ``bootindex`` properties. | ||
101 | + | ||
102 | +There is no way to set a ``bootindex`` property if you are using | ||
103 | +a short-form option like ``-hda`` or ``-cdrom``, so to use | ||
104 | +``bootindex`` properties you will need to expand out those options | ||
105 | +into long-form ``-drive`` and ``-device`` option pairs. | ||
106 | + | ||
107 | +Example | ||
108 | +------- | ||
109 | + | ||
110 | +Let's assume we have a QEMU machine with two NICs (virtio, e1000) and two | ||
111 | +disks (IDE, virtio): | ||
112 | + | ||
113 | +.. parsed-literal:: | ||
114 | + | ||
115 | + |qemu_system| -drive file=disk1.img,if=none,id=disk1 \\ | ||
116 | + -device ide-hd,drive=disk1,bootindex=4 \\ | ||
117 | + -drive file=disk2.img,if=none,id=disk2 \\ | ||
118 | + -device virtio-blk-pci,drive=disk2,bootindex=3 \\ | ||
119 | + -netdev type=user,id=net0 \\ | ||
120 | + -device virtio-net-pci,netdev=net0,bootindex=2 \\ | ||
121 | + -netdev type=user,id=net1 \\ | ||
122 | + -device e1000,netdev=net1,bootindex=1 | ||
123 | + | ||
124 | +Given the command above, firmware should try to boot from the e1000 NIC | ||
125 | +first. If this fails, it should try the virtio NIC next; if this fails | ||
126 | +too, it should try the virtio disk, and then the IDE disk. | ||
127 | + | ||
128 | +Limitations | ||
129 | +----------- | ||
130 | + | ||
131 | +Some firmware has limitations on which devices can be considered for | ||
132 | +booting. For instance, the PC BIOS boot specification allows only one | ||
133 | +disk to be bootable. If boot from disk fails for some reason, the BIOS | ||
134 | +won't retry booting from other disk. It can still try to boot from | ||
135 | +floppy or net, though. | ||
136 | + | ||
137 | +Sometimes, firmware cannot map the device path QEMU wants firmware to | ||
138 | +boot from to a boot method. It doesn't happen for devices the firmware | ||
139 | +can natively boot from, but if firmware relies on an option ROM for | ||
140 | +booting, and the same option ROM is used for booting from more then one | ||
141 | +device, the firmware may not be able to ask the option ROM to boot from | ||
142 | +a particular device reliably. For instance with the PC BIOS, if a SCSI HBA | ||
143 | +has three bootable devices target1, target3, target5 connected to it, | ||
144 | +the option ROM will have a boot method for each of them, but it is not | ||
145 | +possible to map from boot method back to a specific target. This is a | ||
146 | +shortcoming of the PC BIOS boot specification. | ||
147 | + | ||
148 | +Mixing bootindex and boot order parameters | ||
149 | +------------------------------------------ | ||
150 | + | ||
151 | +Note that it does not make sense to use the bootindex property together | ||
152 | +with the ``-boot order=...`` (or ``-boot once=...``) parameter. The guest | ||
153 | +firmware implementations normally either support the one or the other, | ||
154 | +but not both parameters at the same time. Mixing them will result in | ||
155 | +undefined behavior, and thus the guest firmware will likely not boot | ||
156 | +from the expected devices. | ||
157 | diff --git a/docs/system/index.rst b/docs/system/index.rst | ||
14 | index XXXXXXX..XXXXXXX 100644 | 158 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 159 | --- a/docs/system/index.rst |
16 | +++ b/target/arm/helper.c | 160 | +++ b/docs/system/index.rst |
17 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | 161 | @@ -XXX,XX +XXX,XX @@ or Hypervisor.Framework. |
18 | return CP_ACCESS_OK; | 162 | authz |
19 | } | 163 | gdb |
20 | 164 | managed-startup | |
21 | +/* Check for traps from EL1 due to HCR_EL2.TACR. */ | 165 | + bootindex |
22 | +static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | 166 | cpu-hotplug |
23 | + bool isread) | 167 | pr-manager |
24 | +{ | 168 | targets |
25 | + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | ||
26 | + return CP_ACCESS_TRAP_EL2; | ||
27 | + } | ||
28 | + return CP_ACCESS_OK; | ||
29 | +} | ||
30 | + | ||
31 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
32 | { | ||
33 | ARMCPU *cpu = env_archcpu(env); | ||
34 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1cp_reginfo[] = { | ||
35 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | ||
36 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | ||
37 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | ||
38 | - .access = PL1_RW, .type = ARM_CP_CONST, | ||
39 | - .resetvalue = 0 }, | ||
40 | + .access = PL1_RW, .accessfn = access_tacr, | ||
41 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
42 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, | ||
43 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | ||
44 | .access = PL2_RW, .type = ARM_CP_CONST, | ||
45 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
46 | ARMCPRegInfo auxcr_reginfo[] = { | ||
47 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | ||
48 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | ||
49 | - .access = PL1_RW, .type = ARM_CP_CONST, | ||
50 | - .resetvalue = cpu->reset_auxcr }, | ||
51 | + .access = PL1_RW, .accessfn = access_tacr, | ||
52 | + .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | ||
53 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | ||
54 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | ||
55 | .access = PL2_RW, .type = ARM_CP_CONST, | ||
56 | -- | 169 | -- |
57 | 2.20.1 | 170 | 2.20.1 |
58 | 171 | ||
59 | 172 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Most of docs/barrier.txt is describing the protocol implemented |
---|---|---|---|
2 | by the input-barrier device. Move this into the interop | ||
3 | section of the manual, and rstify it. | ||
2 | 4 | ||
3 | These bits trap EL1 access to set/way cache maintenance insns. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
7 | Reviewed-by: Laurent Vivier <laurent@vivier.eu> | ||
8 | Message-id: 20210727204112.12579-2-peter.maydell@linaro.org | ||
9 | --- | ||
10 | docs/barrier.txt | 318 ----------------------------- | ||
11 | docs/interop/barrier.rst | 426 +++++++++++++++++++++++++++++++++++++++ | ||
12 | docs/interop/index.rst | 1 + | ||
13 | 3 files changed, 427 insertions(+), 318 deletions(-) | ||
14 | create mode 100644 docs/interop/barrier.rst | ||
4 | 15 | ||
5 | Buglink: https://bugs.launchpad.net/bugs/1863685 | 16 | diff --git a/docs/barrier.txt b/docs/barrier.txt |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200229012811.24129-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/helper.c | 22 ++++++++++++++++------ | ||
12 | 1 file changed, 16 insertions(+), 6 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 18 | --- a/docs/barrier.txt |
17 | +++ b/target/arm/helper.c | 19 | +++ b/docs/barrier.txt |
18 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | 20 | @@ -XXX,XX +XXX,XX @@ |
19 | return CP_ACCESS_OK; | 21 | |
20 | } | 22 | (qemu) object_del barrier0 |
21 | 23 | (qemu) object_add input-barrier,id=barrier0,name=VM-1 | |
22 | +/* Check for traps from EL1 due to HCR_EL2.TSW. */ | 24 | - |
23 | +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | 25 | -* Message format |
24 | + bool isread) | 26 | - |
25 | +{ | 27 | - Message format between the server and client is in two parts: |
26 | + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | 28 | - |
27 | + return CP_ACCESS_TRAP_EL2; | 29 | - 1- the payload length is a 32bit integer in network endianness, |
28 | + } | 30 | - 2- the payload |
29 | + return CP_ACCESS_OK; | 31 | - |
30 | +} | 32 | - The payload starts with a 4byte string (without NUL) which is the |
31 | + | 33 | - command. The first command between the server and the client |
32 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 34 | - is the only command not encoded on 4 bytes ("Barrier"). |
33 | { | 35 | - The remaining part of the payload is decoded according to the command. |
34 | ARMCPU *cpu = env_archcpu(env); | 36 | - |
35 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 37 | -* Protocol Description (from barrier/src/lib/barrier/protocol_types.h) |
36 | .access = PL1_W, .type = ARM_CP_NOP }, | 38 | - |
37 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | 39 | - - barrierCmdHello "Barrier" |
38 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | 40 | - |
39 | - .access = PL1_W, .type = ARM_CP_NOP }, | 41 | - Direction: server -> client |
40 | + .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | 42 | - Parameters: { int16_t minor, int16_t major } |
41 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | 43 | - Description: |
42 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | 44 | - |
43 | .access = PL0_W, .type = ARM_CP_NOP, | 45 | - Say hello to client |
44 | .accessfn = aa64_cacheop_access }, | 46 | - minor = protocol major version number supported by server |
45 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | 47 | - major = protocol minor version number supported by server |
46 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | 48 | - |
47 | - .access = PL1_W, .type = ARM_CP_NOP }, | 49 | - - barrierCmdHelloBack "Barrier" |
48 | + .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | 50 | - |
49 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | 51 | - Direction: client ->server |
50 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | 52 | - Parameters: { int16_t minor, int16_t major, char *name} |
51 | .access = PL0_W, .type = ARM_CP_NOP, | 53 | - Description: |
52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 54 | - |
53 | .accessfn = aa64_cacheop_access }, | 55 | - Respond to hello from server |
54 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | 56 | - minor = protocol major version number supported by client |
55 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | 57 | - major = protocol minor version number supported by client |
56 | - .access = PL1_W, .type = ARM_CP_NOP }, | 58 | - name = client name |
57 | + .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | 59 | - |
58 | /* TLBI operations */ | 60 | - - barrierCmdDInfo "DINF" |
59 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | 61 | - |
60 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | 62 | - Direction: client ->server |
61 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 63 | - Parameters: { int16_t x_origin, int16_t y_origin, int16_t width, int16_t height, int16_t x, int16_t y} |
62 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | 64 | - Description: |
63 | .type = ARM_CP_NOP, .access = PL1_W }, | 65 | - |
64 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | 66 | - The client screen must send this message in response to the |
65 | - .type = ARM_CP_NOP, .access = PL1_W }, | 67 | - barrierCmdQInfo message. It must also send this message when the |
66 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 68 | - screen's resolution changes. In this case, the client screen should |
67 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | 69 | - ignore any barrierCmdDMouseMove messages until it receives a |
68 | .type = ARM_CP_NOP, .access = PL1_W }, | 70 | - barrierCmdCInfoAck in order to prevent attempts to move the mouse off |
69 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | 71 | - the new screen area. |
70 | - .type = ARM_CP_NOP, .access = PL1_W }, | 72 | - |
71 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 73 | - - barrierCmdCNoop "CNOP" |
72 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | 74 | - |
73 | .type = ARM_CP_NOP, .access = PL1_W }, | 75 | - Direction: client -> server |
74 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | 76 | - Parameters: None |
75 | .type = ARM_CP_NOP, .access = PL1_W }, | 77 | - Description: |
76 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | 78 | - |
77 | - .type = ARM_CP_NOP, .access = PL1_W }, | 79 | - No operation |
78 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | 80 | - |
79 | /* MMU Domain access control / MPU write buffer control */ | 81 | - - barrierCmdCClose "CBYE" |
80 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, | 82 | - |
81 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, | 83 | - Direction: server -> client |
84 | - Parameters: None | ||
85 | - Description: | ||
86 | - | ||
87 | - Close connection | ||
88 | - | ||
89 | - - barrierCmdCEnter "CINN" | ||
90 | - | ||
91 | - Direction: server -> client | ||
92 | - Parameters: { int16_t x, int16_t y, int32_t seq, int16_t modifier } | ||
93 | - Description: | ||
94 | - | ||
95 | - Enter screen. | ||
96 | - x,y = entering screen absolute coordinates | ||
97 | - seq = sequence number, which is used to order messages between | ||
98 | - screens. the secondary screen must return this number | ||
99 | - with some messages | ||
100 | - modifier = modifier key mask. this will have bits set for each | ||
101 | - toggle modifier key that is activated on entry to the | ||
102 | - screen. the secondary screen should adjust its toggle | ||
103 | - modifiers to reflect that state. | ||
104 | - | ||
105 | - - barrierCmdCLeave "COUT" | ||
106 | - | ||
107 | - Direction: server -> client | ||
108 | - Parameters: None | ||
109 | - Description: | ||
110 | - | ||
111 | - Leaving screen. the secondary screen should send clipboard data in | ||
112 | - response to this message for those clipboards that it has grabbed | ||
113 | - (i.e. has sent a barrierCmdCClipboard for and has not received a | ||
114 | - barrierCmdCClipboard for with a greater sequence number) and that | ||
115 | - were grabbed or have changed since the last leave. | ||
116 | - | ||
117 | - - barrierCmdCClipboard "CCLP" | ||
118 | - | ||
119 | - Direction: server -> client | ||
120 | - Parameters: { int8_t id, int32_t seq } | ||
121 | - Description: | ||
122 | - | ||
123 | - Grab clipboard. Sent by screen when some other app on that screen | ||
124 | - grabs a clipboard. | ||
125 | - id = the clipboard identifier | ||
126 | - seq = sequence number. Client must use the sequence number passed in | ||
127 | - the most recent barrierCmdCEnter. the server always sends 0. | ||
128 | - | ||
129 | - - barrierCmdCScreenSaver "CSEC" | ||
130 | - | ||
131 | - Direction: server -> client | ||
132 | - Parameters: { int8_t started } | ||
133 | - Description: | ||
134 | - | ||
135 | - Screensaver change. | ||
136 | - started = Screensaver on primary has started (1) or closed (0) | ||
137 | - | ||
138 | - - barrierCmdCResetOptions "CROP" | ||
139 | - | ||
140 | - Direction: server -> client | ||
141 | - Parameters: None | ||
142 | - Description: | ||
143 | - | ||
144 | - Reset options. Client should reset all of its options to their | ||
145 | - defaults. | ||
146 | - | ||
147 | - - barrierCmdCInfoAck "CIAK" | ||
148 | - | ||
149 | - Direction: server -> client | ||
150 | - Parameters: None | ||
151 | - Description: | ||
152 | - | ||
153 | - Resolution change acknowledgment. Sent by server in response to a | ||
154 | - client screen's barrierCmdDInfo. This is sent for every | ||
155 | - barrierCmdDInfo, whether or not the server had sent a barrierCmdQInfo. | ||
156 | - | ||
157 | - - barrierCmdCKeepAlive "CALV" | ||
158 | - | ||
159 | - Direction: server -> client | ||
160 | - Parameters: None | ||
161 | - Description: | ||
162 | - | ||
163 | - Keep connection alive. Sent by the server periodically to verify | ||
164 | - that connections are still up and running. clients must reply in | ||
165 | - kind on receipt. if the server gets an error sending the message or | ||
166 | - does not receive a reply within a reasonable time then the server | ||
167 | - disconnects the client. if the client doesn't receive these (or any | ||
168 | - message) periodically then it should disconnect from the server. the | ||
169 | - appropriate interval is defined by an option. | ||
170 | - | ||
171 | - - barrierCmdDKeyDown "DKDN" | ||
172 | - | ||
173 | - Direction: server -> client | ||
174 | - Parameters: { int16_t keyid, int16_t modifier [,int16_t button] } | ||
175 | - Description: | ||
176 | - | ||
177 | - Key pressed. | ||
178 | - keyid = X11 key id | ||
179 | - modified = modified mask | ||
180 | - button = X11 Xkb keycode (optional) | ||
181 | - | ||
182 | - - barrierCmdDKeyRepeat "DKRP" | ||
183 | - | ||
184 | - Direction: server -> client | ||
185 | - Parameters: { int16_t keyid, int16_t modifier, int16_t repeat [,int16_t button] } | ||
186 | - Description: | ||
187 | - | ||
188 | - Key auto-repeat. | ||
189 | - keyid = X11 key id | ||
190 | - modified = modified mask | ||
191 | - repeat = number of repeats | ||
192 | - button = X11 Xkb keycode (optional) | ||
193 | - | ||
194 | - - barrierCmdDKeyUp "DKUP" | ||
195 | - | ||
196 | - Direction: server -> client | ||
197 | - Parameters: { int16_t keyid, int16_t modifier [,int16_t button] } | ||
198 | - Description: | ||
199 | - | ||
200 | - Key released. | ||
201 | - keyid = X11 key id | ||
202 | - modified = modified mask | ||
203 | - button = X11 Xkb keycode (optional) | ||
204 | - | ||
205 | - - barrierCmdDMouseDown "DMDN" | ||
206 | - | ||
207 | - Direction: server -> client | ||
208 | - Parameters: { int8_t button } | ||
209 | - Description: | ||
210 | - | ||
211 | - Mouse button pressed. | ||
212 | - button = button id | ||
213 | - | ||
214 | - - barrierCmdDMouseUp "DMUP" | ||
215 | - | ||
216 | - Direction: server -> client | ||
217 | - Parameters: { int8_t button } | ||
218 | - Description: | ||
219 | - | ||
220 | - Mouse button release. | ||
221 | - button = button id | ||
222 | - | ||
223 | - - barrierCmdDMouseMove "DMMV" | ||
224 | - | ||
225 | - Direction: server -> client | ||
226 | - Parameters: { int16_t x, int16_t y } | ||
227 | - Description: | ||
228 | - | ||
229 | - Absolute mouse moved. | ||
230 | - x,y = absolute screen coordinates | ||
231 | - | ||
232 | - - barrierCmdDMouseRelMove "DMRM" | ||
233 | - | ||
234 | - Direction: server -> client | ||
235 | - Parameters: { int16_t x, int16_t y } | ||
236 | - Description: | ||
237 | - | ||
238 | - Relative mouse moved. | ||
239 | - x,y = r relative screen coordinates | ||
240 | - | ||
241 | - - barrierCmdDMouseWheel "DMWM" | ||
242 | - | ||
243 | - Direction: server -> client | ||
244 | - Parameters: { int16_t x , int16_t y } or { int16_t y } | ||
245 | - Description: | ||
246 | - | ||
247 | - Mouse scroll. The delta should be +120 for one tick forward (away | ||
248 | - from the user) or right and -120 for one tick backward (toward the | ||
249 | - user) or left. | ||
250 | - x = x delta | ||
251 | - y = y delta | ||
252 | - | ||
253 | - - barrierCmdDClipboard "DCLP" | ||
254 | - | ||
255 | - Direction: server -> client | ||
256 | - Parameters: { int8_t id, int32_t seq, int8_t mark, char *data } | ||
257 | - Description: | ||
258 | - | ||
259 | - Clipboard data. | ||
260 | - id = clipboard id | ||
261 | - seq = sequence number. The sequence number is 0 when sent by the | ||
262 | - server. Client screens should use the/ sequence number from | ||
263 | - the most recent barrierCmdCEnter. | ||
264 | - | ||
265 | - - barrierCmdDSetOptions "DSOP" | ||
266 | - | ||
267 | - Direction: server -> client | ||
268 | - Parameters: { int32 t nb, { int32_t id, int32_t val }[] } | ||
269 | - Description: | ||
270 | - | ||
271 | - Set options. Client should set the given option/value pairs. | ||
272 | - nb = numbers of { id, val } entries | ||
273 | - id = option id | ||
274 | - val = option new value | ||
275 | - | ||
276 | - - barrierCmdDFileTransfer "DFTR" | ||
277 | - | ||
278 | - Direction: server -> client | ||
279 | - Parameters: { int8_t mark, char *content } | ||
280 | - Description: | ||
281 | - | ||
282 | - Transfer file data. | ||
283 | - mark = 0 means the content followed is the file size | ||
284 | - 1 means the content followed is the chunk data | ||
285 | - 2 means the file transfer is finished | ||
286 | - | ||
287 | - - barrierCmdDDragInfo "DDRG" int16_t char * | ||
288 | - | ||
289 | - Direction: server -> client | ||
290 | - Parameters: { int16_t nb, char *content } | ||
291 | - Description: | ||
292 | - | ||
293 | - Drag information. | ||
294 | - nb = number of dragging objects | ||
295 | - content = object's directory | ||
296 | - | ||
297 | - - barrierCmdQInfo "QINF" | ||
298 | - | ||
299 | - Direction: server -> client | ||
300 | - Parameters: None | ||
301 | - Description: | ||
302 | - | ||
303 | - Query screen info | ||
304 | - Client should reply with a barrierCmdDInfo | ||
305 | - | ||
306 | - - barrierCmdEIncompatible "EICV" | ||
307 | - | ||
308 | - Direction: server -> client | ||
309 | - Parameters: { int16_t nb, major *minor } | ||
310 | - Description: | ||
311 | - | ||
312 | - Incompatible version. | ||
313 | - major = major version | ||
314 | - minor = minor version | ||
315 | - | ||
316 | - - barrierCmdEBusy "EBSY" | ||
317 | - | ||
318 | - Direction: server -> client | ||
319 | - Parameters: None | ||
320 | - Description: | ||
321 | - | ||
322 | - Name provided when connecting is already in use. | ||
323 | - | ||
324 | - - barrierCmdEUnknown "EUNK" | ||
325 | - | ||
326 | - Direction: server -> client | ||
327 | - Parameters: None | ||
328 | - Description: | ||
329 | - | ||
330 | - Unknown client. Name provided when connecting is not in primary's | ||
331 | - screen configuration map. | ||
332 | - | ||
333 | - - barrierCmdEBad "EBAD" | ||
334 | - | ||
335 | - Direction: server -> client | ||
336 | - Parameters: None | ||
337 | - Description: | ||
338 | - | ||
339 | - Protocol violation. Server should disconnect after sending this | ||
340 | - message. | ||
341 | - | ||
342 | * TO DO | ||
343 | |||
344 | - Enable SSL | ||
345 | diff --git a/docs/interop/barrier.rst b/docs/interop/barrier.rst | ||
346 | new file mode 100644 | ||
347 | index XXXXXXX..XXXXXXX | ||
348 | --- /dev/null | ||
349 | +++ b/docs/interop/barrier.rst | ||
350 | @@ -XXX,XX +XXX,XX @@ | ||
351 | +Barrier client protocol | ||
352 | +======================= | ||
353 | + | ||
354 | +QEMU's ``input-barrier`` device implements the client end of | ||
355 | +the KVM (Keyboard-Video-Mouse) software | ||
356 | +`Barrier <https://github.com/debauchee/barrier>`__. | ||
357 | + | ||
358 | +This document briefly describes the protocol as we implement it. | ||
359 | + | ||
360 | +Message format | ||
361 | +-------------- | ||
362 | + | ||
363 | +Message format between the server and client is in two parts: | ||
364 | + | ||
365 | +#. the payload length, a 32bit integer in network endianness | ||
366 | +#. the payload | ||
367 | + | ||
368 | +The payload starts with a 4byte string (without NUL) which is the | ||
369 | +command. The first command between the server and the client | ||
370 | +is the only command not encoded on 4 bytes ("Barrier"). | ||
371 | +The remaining part of the payload is decoded according to the command. | ||
372 | + | ||
373 | +Protocol Description | ||
374 | +-------------------- | ||
375 | + | ||
376 | +This comes from ``barrier/src/lib/barrier/protocol_types.h``. | ||
377 | + | ||
378 | +barrierCmdHello "Barrier" | ||
379 | +^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
380 | + | ||
381 | +Direction: | ||
382 | + server -> client | ||
383 | +Parameters: | ||
384 | + ``{ int16_t minor, int16_t major }`` | ||
385 | +Description: | ||
386 | + Say hello to client | ||
387 | + | ||
388 | + ``minor`` = protocol major version number supported by server | ||
389 | + | ||
390 | + ``major`` = protocol minor version number supported by server | ||
391 | + | ||
392 | +barrierCmdHelloBack "Barrier" | ||
393 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
394 | + | ||
395 | +Direction: | ||
396 | + client ->server | ||
397 | +Parameters: | ||
398 | + ``{ int16_t minor, int16_t major, char *name}`` | ||
399 | +Description: | ||
400 | + Respond to hello from server | ||
401 | + | ||
402 | + ``minor`` = protocol major version number supported by client | ||
403 | + | ||
404 | + ``major`` = protocol minor version number supported by client | ||
405 | + | ||
406 | + ``name`` = client name | ||
407 | + | ||
408 | +barrierCmdDInfo "DINF" | ||
409 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
410 | + | ||
411 | +Direction: | ||
412 | + client ->server | ||
413 | +Parameters: | ||
414 | + ``{ int16_t x_origin, int16_t y_origin, int16_t width, int16_t height, int16_t x, int16_t y}`` | ||
415 | +Description: | ||
416 | + The client screen must send this message in response to the | ||
417 | + barrierCmdQInfo message. It must also send this message when the | ||
418 | + screen's resolution changes. In this case, the client screen should | ||
419 | + ignore any barrierCmdDMouseMove messages until it receives a | ||
420 | + barrierCmdCInfoAck in order to prevent attempts to move the mouse off | ||
421 | + the new screen area. | ||
422 | + | ||
423 | +barrierCmdCNoop "CNOP" | ||
424 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
425 | + | ||
426 | +Direction: | ||
427 | + client -> server | ||
428 | +Parameters: | ||
429 | + None | ||
430 | +Description: | ||
431 | + No operation | ||
432 | + | ||
433 | +barrierCmdCClose "CBYE" | ||
434 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
435 | + | ||
436 | +Direction: | ||
437 | + server -> client | ||
438 | +Parameters: | ||
439 | + None | ||
440 | +Description: | ||
441 | + Close connection | ||
442 | + | ||
443 | +barrierCmdCEnter "CINN" | ||
444 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
445 | + | ||
446 | +Direction: | ||
447 | + server -> client | ||
448 | +Parameters: | ||
449 | + ``{ int16_t x, int16_t y, int32_t seq, int16_t modifier }`` | ||
450 | +Description: | ||
451 | + Enter screen. | ||
452 | + | ||
453 | + ``x``, ``y`` = entering screen absolute coordinates | ||
454 | + | ||
455 | + ``seq`` = sequence number, which is used to order messages between | ||
456 | + screens. the secondary screen must return this number | ||
457 | + with some messages | ||
458 | + | ||
459 | + ``modifier`` = modifier key mask. this will have bits set for each | ||
460 | + toggle modifier key that is activated on entry to the | ||
461 | + screen. the secondary screen should adjust its toggle | ||
462 | + modifiers to reflect that state. | ||
463 | + | ||
464 | +barrierCmdCLeave "COUT" | ||
465 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
466 | + | ||
467 | +Direction: | ||
468 | + server -> client | ||
469 | +Parameters: | ||
470 | + None | ||
471 | +Description: | ||
472 | + Leaving screen. the secondary screen should send clipboard data in | ||
473 | + response to this message for those clipboards that it has grabbed | ||
474 | + (i.e. has sent a barrierCmdCClipboard for and has not received a | ||
475 | + barrierCmdCClipboard for with a greater sequence number) and that | ||
476 | + were grabbed or have changed since the last leave. | ||
477 | + | ||
478 | +barrierCmdCClipboard "CCLP" | ||
479 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
480 | + | ||
481 | +Direction: | ||
482 | + server -> client | ||
483 | +Parameters: | ||
484 | + ``{ int8_t id, int32_t seq }`` | ||
485 | +Description: | ||
486 | + Grab clipboard. Sent by screen when some other app on that screen | ||
487 | + grabs a clipboard. | ||
488 | + | ||
489 | + ``id`` = the clipboard identifier | ||
490 | + | ||
491 | + ``seq`` = sequence number. Client must use the sequence number passed in | ||
492 | + the most recent barrierCmdCEnter. the server always sends 0. | ||
493 | + | ||
494 | +barrierCmdCScreenSaver "CSEC" | ||
495 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
496 | + | ||
497 | +Direction: | ||
498 | + server -> client | ||
499 | +Parameters: | ||
500 | + ``{ int8_t started }`` | ||
501 | +Description: | ||
502 | + Screensaver change. | ||
503 | + | ||
504 | + ``started`` = Screensaver on primary has started (1) or closed (0) | ||
505 | + | ||
506 | +barrierCmdCResetOptions "CROP" | ||
507 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
508 | + | ||
509 | +Direction: | ||
510 | + server -> client | ||
511 | +Parameters: | ||
512 | + None | ||
513 | +Description: | ||
514 | + Reset options. Client should reset all of its options to their | ||
515 | + defaults. | ||
516 | + | ||
517 | +barrierCmdCInfoAck "CIAK" | ||
518 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
519 | + | ||
520 | +Direction: | ||
521 | + server -> client | ||
522 | +Parameters: | ||
523 | + None | ||
524 | +Description: | ||
525 | + Resolution change acknowledgment. Sent by server in response to a | ||
526 | + client screen's barrierCmdDInfo. This is sent for every | ||
527 | + barrierCmdDInfo, whether or not the server had sent a barrierCmdQInfo. | ||
528 | + | ||
529 | +barrierCmdCKeepAlive "CALV" | ||
530 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
531 | + | ||
532 | +Direction: | ||
533 | + server -> client | ||
534 | +Parameters: | ||
535 | + None | ||
536 | +Description: | ||
537 | + Keep connection alive. Sent by the server periodically to verify | ||
538 | + that connections are still up and running. clients must reply in | ||
539 | + kind on receipt. if the server gets an error sending the message or | ||
540 | + does not receive a reply within a reasonable time then the server | ||
541 | + disconnects the client. if the client doesn't receive these (or any | ||
542 | + message) periodically then it should disconnect from the server. the | ||
543 | + appropriate interval is defined by an option. | ||
544 | + | ||
545 | +barrierCmdDKeyDown "DKDN" | ||
546 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
547 | + | ||
548 | +Direction: | ||
549 | + server -> client | ||
550 | +Parameters: | ||
551 | + ``{ int16_t keyid, int16_t modifier [,int16_t button] }`` | ||
552 | +Description: | ||
553 | + Key pressed. | ||
554 | + | ||
555 | + ``keyid`` = X11 key id | ||
556 | + | ||
557 | + ``modified`` = modified mask | ||
558 | + | ||
559 | + ``button`` = X11 Xkb keycode (optional) | ||
560 | + | ||
561 | +barrierCmdDKeyRepeat "DKRP" | ||
562 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
563 | + | ||
564 | +Direction: | ||
565 | + server -> client | ||
566 | +Parameters: | ||
567 | + ``{ int16_t keyid, int16_t modifier, int16_t repeat [,int16_t button] }`` | ||
568 | +Description: | ||
569 | + Key auto-repeat. | ||
570 | + | ||
571 | + ``keyid`` = X11 key id | ||
572 | + | ||
573 | + ``modified`` = modified mask | ||
574 | + | ||
575 | + ``repeat`` = number of repeats | ||
576 | + | ||
577 | + ``button`` = X11 Xkb keycode (optional) | ||
578 | + | ||
579 | +barrierCmdDKeyUp "DKUP" | ||
580 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
581 | + | ||
582 | +Direction: | ||
583 | + server -> client | ||
584 | +Parameters: | ||
585 | + ``{ int16_t keyid, int16_t modifier [,int16_t button] }`` | ||
586 | +Description: | ||
587 | + Key released. | ||
588 | + | ||
589 | + ``keyid`` = X11 key id | ||
590 | + | ||
591 | + ``modified`` = modified mask | ||
592 | + | ||
593 | + ``button`` = X11 Xkb keycode (optional) | ||
594 | + | ||
595 | +barrierCmdDMouseDown "DMDN" | ||
596 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
597 | + | ||
598 | +Direction: | ||
599 | + server -> client | ||
600 | +Parameters: | ||
601 | + ``{ int8_t button }`` | ||
602 | +Description: | ||
603 | + Mouse button pressed. | ||
604 | + | ||
605 | + ``button`` = button id | ||
606 | + | ||
607 | +barrierCmdDMouseUp "DMUP" | ||
608 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
609 | + | ||
610 | +Direction: | ||
611 | + server -> client | ||
612 | +Parameters: | ||
613 | + ``{ int8_t button }`` | ||
614 | +Description: | ||
615 | + Mouse button release. | ||
616 | + | ||
617 | + ``button`` = button id | ||
618 | + | ||
619 | +barrierCmdDMouseMove "DMMV" | ||
620 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
621 | + | ||
622 | +Direction: | ||
623 | + server -> client | ||
624 | +Parameters: | ||
625 | + ``{ int16_t x, int16_t y }`` | ||
626 | +Description: | ||
627 | + Absolute mouse moved. | ||
628 | + | ||
629 | + ``x``, ``y`` = absolute screen coordinates | ||
630 | + | ||
631 | +barrierCmdDMouseRelMove "DMRM" | ||
632 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
633 | + | ||
634 | +Direction: | ||
635 | + server -> client | ||
636 | +Parameters: | ||
637 | + ``{ int16_t x, int16_t y }`` | ||
638 | +Description: | ||
639 | + Relative mouse moved. | ||
640 | + | ||
641 | + ``x``, ``y`` = r relative screen coordinates | ||
642 | + | ||
643 | +barrierCmdDMouseWheel "DMWM" | ||
644 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
645 | + | ||
646 | +Direction: | ||
647 | + server -> client | ||
648 | +Parameters: | ||
649 | + ``{ int16_t x , int16_t y }`` or ``{ int16_t y }`` | ||
650 | +Description: | ||
651 | + Mouse scroll. The delta should be +120 for one tick forward (away | ||
652 | + from the user) or right and -120 for one tick backward (toward the | ||
653 | + user) or left. | ||
654 | + | ||
655 | + ``x`` = x delta | ||
656 | + | ||
657 | + ``y`` = y delta | ||
658 | + | ||
659 | +barrierCmdDClipboard "DCLP" | ||
660 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
661 | + | ||
662 | +Direction: | ||
663 | + server -> client | ||
664 | +Parameters: | ||
665 | + ``{ int8_t id, int32_t seq, int8_t mark, char *data }`` | ||
666 | +Description: | ||
667 | + Clipboard data. | ||
668 | + | ||
669 | + ``id`` = clipboard id | ||
670 | + | ||
671 | + ``seq`` = sequence number. The sequence number is 0 when sent by the | ||
672 | + server. Client screens should use the/ sequence number from | ||
673 | + the most recent barrierCmdCEnter. | ||
674 | + | ||
675 | +barrierCmdDSetOptions "DSOP" | ||
676 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
677 | + | ||
678 | +Direction: | ||
679 | + server -> client | ||
680 | +Parameters: | ||
681 | + ``{ int32 t nb, { int32_t id, int32_t val }[] }`` | ||
682 | +Description: | ||
683 | + Set options. Client should set the given option/value pairs. | ||
684 | + | ||
685 | + ``nb`` = numbers of ``{ id, val }`` entries | ||
686 | + | ||
687 | + ``id`` = option id | ||
688 | + | ||
689 | + ``val`` = option new value | ||
690 | + | ||
691 | +barrierCmdDFileTransfer "DFTR" | ||
692 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
693 | + | ||
694 | +Direction: | ||
695 | + server -> client | ||
696 | +Parameters: | ||
697 | + ``{ int8_t mark, char *content }`` | ||
698 | +Description: | ||
699 | + Transfer file data. | ||
700 | + | ||
701 | + * ``mark`` = 0 means the content followed is the file size | ||
702 | + * 1 means the content followed is the chunk data | ||
703 | + * 2 means the file transfer is finished | ||
704 | + | ||
705 | +barrierCmdDDragInfo "DDRG" | ||
706 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
707 | + | ||
708 | +Direction: | ||
709 | + server -> client | ||
710 | +Parameters: | ||
711 | + ``{ int16_t nb, char *content }`` | ||
712 | +Description: | ||
713 | + Drag information. | ||
714 | + | ||
715 | + ``nb`` = number of dragging objects | ||
716 | + | ||
717 | + ``content`` = object's directory | ||
718 | + | ||
719 | +barrierCmdQInfo "QINF" | ||
720 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
721 | + | ||
722 | +Direction: | ||
723 | + server -> client | ||
724 | +Parameters: | ||
725 | + None | ||
726 | +Description: | ||
727 | + Query screen info | ||
728 | + | ||
729 | + Client should reply with a barrierCmdDInfo | ||
730 | + | ||
731 | +barrierCmdEIncompatible "EICV" | ||
732 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
733 | + | ||
734 | +Direction: | ||
735 | + server -> client | ||
736 | +Parameters: | ||
737 | + ``{ int16_t nb, major *minor }`` | ||
738 | +Description: | ||
739 | + Incompatible version. | ||
740 | + | ||
741 | + ``major`` = major version | ||
742 | + | ||
743 | + ``minor`` = minor version | ||
744 | + | ||
745 | +barrierCmdEBusy "EBSY" | ||
746 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
747 | + | ||
748 | +Direction: | ||
749 | + server -> client | ||
750 | +Parameters: | ||
751 | + None | ||
752 | +Description: | ||
753 | + Name provided when connecting is already in use. | ||
754 | + | ||
755 | +barrierCmdEUnknown "EUNK" | ||
756 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
757 | + | ||
758 | +Direction: | ||
759 | + server -> client | ||
760 | +Parameters: | ||
761 | + None | ||
762 | +Description: | ||
763 | + Unknown client. Name provided when connecting is not in primary's | ||
764 | + screen configuration map. | ||
765 | + | ||
766 | +barrierCmdEBad "EBAD" | ||
767 | +^^^^^^^^^^^^^^^^^^^^^^^ | ||
768 | + | ||
769 | +Direction: | ||
770 | + server -> client | ||
771 | +Parameters: | ||
772 | + None | ||
773 | +Description: | ||
774 | + Protocol violation. Server should disconnect after sending this | ||
775 | + message. | ||
776 | + | ||
777 | diff --git a/docs/interop/index.rst b/docs/interop/index.rst | ||
778 | index XXXXXXX..XXXXXXX 100644 | ||
779 | --- a/docs/interop/index.rst | ||
780 | +++ b/docs/interop/index.rst | ||
781 | @@ -XXX,XX +XXX,XX @@ are useful for making QEMU interoperate with other software. | ||
782 | .. toctree:: | ||
783 | :maxdepth: 2 | ||
784 | |||
785 | + barrier | ||
786 | bitmaps | ||
787 | dbus | ||
788 | dbus-vmstate | ||
82 | -- | 789 | -- |
83 | 2.20.1 | 790 | 2.20.1 |
84 | 791 | ||
85 | 792 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | docs/barrier.txt has a couple of TODO notes about things to be |
---|---|---|---|
2 | implemented in this device; move them into a comment in the | ||
3 | source code. | ||
2 | 4 | ||
3 | This is an aarch64-only function. Move it out of the shared file. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | This patch is code movement only. | 6 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> |
7 | Reviewed-by: Laurent Vivier <laurent@vivier.eu> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20210727204112.12579-3-peter.maydell@linaro.org | ||
10 | --- | ||
11 | docs/barrier.txt | 4 ---- | ||
12 | ui/input-barrier.c | 5 +++++ | ||
13 | 2 files changed, 5 insertions(+), 4 deletions(-) | ||
5 | 14 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | diff --git a/docs/barrier.txt b/docs/barrier.txt |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20200302175829.2183-6-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper-a64.h | 1 + | ||
13 | target/arm/helper.h | 1 - | ||
14 | target/arm/helper-a64.c | 91 ++++++++++++++++++++++++++++++++++++++++ | ||
15 | target/arm/op_helper.c | 93 ----------------------------------------- | ||
16 | 4 files changed, 92 insertions(+), 94 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper-a64.h | 17 | --- a/docs/barrier.txt |
21 | +++ b/target/arm/helper-a64.h | 18 | +++ b/docs/barrier.txt |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) | 19 | @@ -XXX,XX +XXX,XX @@ |
23 | DEF_HELPER_2(sqrt_f16, f16, f16, ptr) | 20 | |
24 | 21 | (qemu) object_del barrier0 | |
25 | DEF_HELPER_2(exception_return, void, env, i64) | 22 | (qemu) object_add input-barrier,id=barrier0,name=VM-1 |
26 | +DEF_HELPER_2(dc_zva, void, env, i64) | 23 | -* TO DO |
27 | 24 | - | |
28 | DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) | 25 | - - Enable SSL |
29 | DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) | 26 | - - Manage SetOptions/ResetOptions commands |
30 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 27 | |
28 | diff --git a/ui/input-barrier.c b/ui/input-barrier.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/helper.h | 30 | --- a/ui/input-barrier.c |
33 | +++ b/target/arm/helper.h | 31 | +++ b/ui/input-barrier.c |
34 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
35 | |||
36 | DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) | ||
37 | DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) | ||
38 | -DEF_HELPER_2(dc_zva, void, env, i64) | ||
39 | |||
40 | DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, | ||
41 | void, ptr, ptr, ptr, ptr, i32) | ||
42 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/helper-a64.c | ||
45 | +++ b/target/arm/helper-a64.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | 32 | @@ -XXX,XX +XXX,XX @@ |
33 | * | ||
34 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
35 | * See the COPYING file in the top-level directory. | ||
36 | + * | ||
37 | + * TODO: | ||
38 | + * | ||
39 | + * - Enable SSL | ||
40 | + * - Manage SetOptions/ResetOptions commands | ||
47 | */ | 41 | */ |
48 | 42 | ||
49 | #include "qemu/osdep.h" | 43 | #include "qemu/osdep.h" |
50 | +#include "qemu/units.h" | ||
51 | #include "cpu.h" | ||
52 | #include "exec/gdbstub.h" | ||
53 | #include "exec/helper-proto.h" | ||
54 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) | ||
55 | return float16_sqrt(a, s); | ||
56 | } | ||
57 | |||
58 | +void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) | ||
59 | +{ | ||
60 | + /* | ||
61 | + * Implement DC ZVA, which zeroes a fixed-length block of memory. | ||
62 | + * Note that we do not implement the (architecturally mandated) | ||
63 | + * alignment fault for attempts to use this on Device memory | ||
64 | + * (which matches the usual QEMU behaviour of not implementing either | ||
65 | + * alignment faults or any memory attribute handling). | ||
66 | + */ | ||
67 | |||
68 | + ARMCPU *cpu = env_archcpu(env); | ||
69 | + uint64_t blocklen = 4 << cpu->dcz_blocksize; | ||
70 | + uint64_t vaddr = vaddr_in & ~(blocklen - 1); | ||
71 | + | ||
72 | +#ifndef CONFIG_USER_ONLY | ||
73 | + { | ||
74 | + /* | ||
75 | + * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | ||
76 | + * the block size so we might have to do more than one TLB lookup. | ||
77 | + * We know that in fact for any v8 CPU the page size is at least 4K | ||
78 | + * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | ||
79 | + * 1K as an artefact of legacy v5 subpage support being present in the | ||
80 | + * same QEMU executable. So in practice the hostaddr[] array has | ||
81 | + * two entries, given the current setting of TARGET_PAGE_BITS_MIN. | ||
82 | + */ | ||
83 | + int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | ||
84 | + void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; | ||
85 | + int try, i; | ||
86 | + unsigned mmu_idx = cpu_mmu_index(env, false); | ||
87 | + TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); | ||
88 | + | ||
89 | + assert(maxidx <= ARRAY_SIZE(hostaddr)); | ||
90 | + | ||
91 | + for (try = 0; try < 2; try++) { | ||
92 | + | ||
93 | + for (i = 0; i < maxidx; i++) { | ||
94 | + hostaddr[i] = tlb_vaddr_to_host(env, | ||
95 | + vaddr + TARGET_PAGE_SIZE * i, | ||
96 | + 1, mmu_idx); | ||
97 | + if (!hostaddr[i]) { | ||
98 | + break; | ||
99 | + } | ||
100 | + } | ||
101 | + if (i == maxidx) { | ||
102 | + /* | ||
103 | + * If it's all in the TLB it's fair game for just writing to; | ||
104 | + * we know we don't need to update dirty status, etc. | ||
105 | + */ | ||
106 | + for (i = 0; i < maxidx - 1; i++) { | ||
107 | + memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | ||
108 | + } | ||
109 | + memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | ||
110 | + return; | ||
111 | + } | ||
112 | + /* | ||
113 | + * OK, try a store and see if we can populate the tlb. This | ||
114 | + * might cause an exception if the memory isn't writable, | ||
115 | + * in which case we will longjmp out of here. We must for | ||
116 | + * this purpose use the actual register value passed to us | ||
117 | + * so that we get the fault address right. | ||
118 | + */ | ||
119 | + helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); | ||
120 | + /* Now we can populate the other TLB entries, if any */ | ||
121 | + for (i = 0; i < maxidx; i++) { | ||
122 | + uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | ||
123 | + if (va != (vaddr_in & TARGET_PAGE_MASK)) { | ||
124 | + helper_ret_stb_mmu(env, va, 0, oi, GETPC()); | ||
125 | + } | ||
126 | + } | ||
127 | + } | ||
128 | + | ||
129 | + /* | ||
130 | + * Slow path (probably attempt to do this to an I/O device or | ||
131 | + * similar, or clearing of a block of code we have translations | ||
132 | + * cached for). Just do a series of byte writes as the architecture | ||
133 | + * demands. It's not worth trying to use a cpu_physical_memory_map(), | ||
134 | + * memset(), unmap() sequence here because: | ||
135 | + * + we'd need to account for the blocksize being larger than a page | ||
136 | + * + the direct-RAM access case is almost always going to be dealt | ||
137 | + * with in the fastpath code above, so there's no speed benefit | ||
138 | + * + we would have to deal with the map returning NULL because the | ||
139 | + * bounce buffer was in use | ||
140 | + */ | ||
141 | + for (i = 0; i < blocklen; i++) { | ||
142 | + helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); | ||
143 | + } | ||
144 | + } | ||
145 | +#else | ||
146 | + memset(g2h(vaddr), 0, blocklen); | ||
147 | +#endif | ||
148 | +} | ||
149 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/target/arm/op_helper.c | ||
152 | +++ b/target/arm/op_helper.c | ||
153 | @@ -XXX,XX +XXX,XX @@ | ||
154 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
155 | */ | ||
156 | #include "qemu/osdep.h" | ||
157 | -#include "qemu/units.h" | ||
158 | #include "qemu/log.h" | ||
159 | #include "qemu/main-loop.h" | ||
160 | #include "cpu.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) | ||
162 | return ((uint32_t)x >> shift) | (x << (32 - shift)); | ||
163 | } | ||
164 | } | ||
165 | - | ||
166 | -void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) | ||
167 | -{ | ||
168 | - /* | ||
169 | - * Implement DC ZVA, which zeroes a fixed-length block of memory. | ||
170 | - * Note that we do not implement the (architecturally mandated) | ||
171 | - * alignment fault for attempts to use this on Device memory | ||
172 | - * (which matches the usual QEMU behaviour of not implementing either | ||
173 | - * alignment faults or any memory attribute handling). | ||
174 | - */ | ||
175 | - | ||
176 | - ARMCPU *cpu = env_archcpu(env); | ||
177 | - uint64_t blocklen = 4 << cpu->dcz_blocksize; | ||
178 | - uint64_t vaddr = vaddr_in & ~(blocklen - 1); | ||
179 | - | ||
180 | -#ifndef CONFIG_USER_ONLY | ||
181 | - { | ||
182 | - /* | ||
183 | - * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | ||
184 | - * the block size so we might have to do more than one TLB lookup. | ||
185 | - * We know that in fact for any v8 CPU the page size is at least 4K | ||
186 | - * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | ||
187 | - * 1K as an artefact of legacy v5 subpage support being present in the | ||
188 | - * same QEMU executable. So in practice the hostaddr[] array has | ||
189 | - * two entries, given the current setting of TARGET_PAGE_BITS_MIN. | ||
190 | - */ | ||
191 | - int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | ||
192 | - void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)]; | ||
193 | - int try, i; | ||
194 | - unsigned mmu_idx = cpu_mmu_index(env, false); | ||
195 | - TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); | ||
196 | - | ||
197 | - assert(maxidx <= ARRAY_SIZE(hostaddr)); | ||
198 | - | ||
199 | - for (try = 0; try < 2; try++) { | ||
200 | - | ||
201 | - for (i = 0; i < maxidx; i++) { | ||
202 | - hostaddr[i] = tlb_vaddr_to_host(env, | ||
203 | - vaddr + TARGET_PAGE_SIZE * i, | ||
204 | - 1, mmu_idx); | ||
205 | - if (!hostaddr[i]) { | ||
206 | - break; | ||
207 | - } | ||
208 | - } | ||
209 | - if (i == maxidx) { | ||
210 | - /* | ||
211 | - * If it's all in the TLB it's fair game for just writing to; | ||
212 | - * we know we don't need to update dirty status, etc. | ||
213 | - */ | ||
214 | - for (i = 0; i < maxidx - 1; i++) { | ||
215 | - memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | ||
216 | - } | ||
217 | - memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | ||
218 | - return; | ||
219 | - } | ||
220 | - /* | ||
221 | - * OK, try a store and see if we can populate the tlb. This | ||
222 | - * might cause an exception if the memory isn't writable, | ||
223 | - * in which case we will longjmp out of here. We must for | ||
224 | - * this purpose use the actual register value passed to us | ||
225 | - * so that we get the fault address right. | ||
226 | - */ | ||
227 | - helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); | ||
228 | - /* Now we can populate the other TLB entries, if any */ | ||
229 | - for (i = 0; i < maxidx; i++) { | ||
230 | - uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | ||
231 | - if (va != (vaddr_in & TARGET_PAGE_MASK)) { | ||
232 | - helper_ret_stb_mmu(env, va, 0, oi, GETPC()); | ||
233 | - } | ||
234 | - } | ||
235 | - } | ||
236 | - | ||
237 | - /* | ||
238 | - * Slow path (probably attempt to do this to an I/O device or | ||
239 | - * similar, or clearing of a block of code we have translations | ||
240 | - * cached for). Just do a series of byte writes as the architecture | ||
241 | - * demands. It's not worth trying to use a cpu_physical_memory_map(), | ||
242 | - * memset(), unmap() sequence here because: | ||
243 | - * + we'd need to account for the blocksize being larger than a page | ||
244 | - * + the direct-RAM access case is almost always going to be dealt | ||
245 | - * with in the fastpath code above, so there's no speed benefit | ||
246 | - * + we would have to deal with the map returning NULL because the | ||
247 | - * bounce buffer was in use | ||
248 | - */ | ||
249 | - for (i = 0; i < blocklen; i++) { | ||
250 | - helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); | ||
251 | - } | ||
252 | - } | ||
253 | -#else | ||
254 | - memset(g2h(vaddr), 0, blocklen); | ||
255 | -#endif | ||
256 | -} | ||
257 | -- | 44 | -- |
258 | 2.20.1 | 45 | 2.20.1 |
259 | 46 | ||
260 | 47 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The remaining text in docs/barrier.txt is user-facing description |
---|---|---|---|
2 | of what the device is and how to use it. Move this into the | ||
3 | system manual and rstify it. | ||
2 | 4 | ||
3 | These bits trap EL1 access to various virtual memory controls. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
7 | Reviewed-by: Laurent Vivier <laurent@vivier.eu> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20210727204112.12579-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | docs/barrier.txt | 48 ----------------------------------------- | ||
12 | docs/system/barrier.rst | 44 +++++++++++++++++++++++++++++++++++++ | ||
13 | docs/system/index.rst | 1 + | ||
14 | 3 files changed, 45 insertions(+), 48 deletions(-) | ||
15 | delete mode 100644 docs/barrier.txt | ||
16 | create mode 100644 docs/system/barrier.rst | ||
4 | 17 | ||
5 | Buglink: https://bugs.launchpad.net/bugs/1855072 | 18 | diff --git a/docs/barrier.txt b/docs/barrier.txt |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | deleted file mode 100644 |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 20 | index XXXXXXX..XXXXXXX |
8 | Message-id: 20200229012811.24129-7-richard.henderson@linaro.org | 21 | --- a/docs/barrier.txt |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | +++ /dev/null |
10 | --- | 23 | @@ -XXX,XX +XXX,XX @@ |
11 | target/arm/helper.c | 82 ++++++++++++++++++++++++++++++--------------- | 24 | - QEMU Barrier Client |
12 | 1 file changed, 55 insertions(+), 27 deletions(-) | 25 | - |
13 | 26 | - | |
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 27 | -* About |
28 | - | ||
29 | - Barrier is a KVM (Keyboard-Video-Mouse) software forked from Symless's | ||
30 | - synergy 1.9 codebase. | ||
31 | - | ||
32 | - See https://github.com/debauchee/barrier | ||
33 | - | ||
34 | -* QEMU usage | ||
35 | - | ||
36 | - Generally, mouse and keyboard are grabbed through the QEMU video | ||
37 | - interface emulation. | ||
38 | - | ||
39 | - But when we want to use a video graphic adapter via a PCI passthrough | ||
40 | - there is no way to provide the keyboard and mouse inputs to the VM | ||
41 | - except by plugging a second set of mouse and keyboard to the host | ||
42 | - or by installing a KVM software in the guest OS. | ||
43 | - | ||
44 | - The QEMU Barrier client avoids this by implementing directly the Barrier | ||
45 | - protocol into QEMU. | ||
46 | - | ||
47 | - This protocol is enabled by adding an input-barrier object to QEMU. | ||
48 | - | ||
49 | - Syntax: input-barrier,id=<object-id>,name=<guest display name> | ||
50 | - [,server=<barrier server address>][,port=<barrier server port>] | ||
51 | - [,x-origin=<x-origin>][,y-origin=<y-origin>] | ||
52 | - [,width=<width>][,height=<height>] | ||
53 | - | ||
54 | - The object can be added on the QEMU command line, for instance with: | ||
55 | - | ||
56 | - ... -object input-barrier,id=barrier0,name=VM-1 ... | ||
57 | - | ||
58 | - where VM-1 is the name the display configured int the Barrier server | ||
59 | - on the host providing the mouse and the keyboard events. | ||
60 | - | ||
61 | - by default <barrier server address> is "localhost", port is 24800, | ||
62 | - <x-origin> and <y-origin> are set to 0, <width> and <height> to | ||
63 | - 1920 and 1080. | ||
64 | - | ||
65 | - If Barrier server is stopped QEMU needs to be reconnected manually, | ||
66 | - by removing and re-adding the input-barrier object, for instance | ||
67 | - with the help of the HMP monitor: | ||
68 | - | ||
69 | - (qemu) object_del barrier0 | ||
70 | - (qemu) object_add input-barrier,id=barrier0,name=VM-1 | ||
71 | - | ||
72 | diff --git a/docs/system/barrier.rst b/docs/system/barrier.rst | ||
73 | new file mode 100644 | ||
74 | index XXXXXXX..XXXXXXX | ||
75 | --- /dev/null | ||
76 | +++ b/docs/system/barrier.rst | ||
77 | @@ -XXX,XX +XXX,XX @@ | ||
78 | +QEMU Barrier Client | ||
79 | +=================== | ||
80 | + | ||
81 | +Generally, mouse and keyboard are grabbed through the QEMU video | ||
82 | +interface emulation. | ||
83 | + | ||
84 | +But when we want to use a video graphic adapter via a PCI passthrough | ||
85 | +there is no way to provide the keyboard and mouse inputs to the VM | ||
86 | +except by plugging a second set of mouse and keyboard to the host | ||
87 | +or by installing a KVM software in the guest OS. | ||
88 | + | ||
89 | +The QEMU Barrier client avoids this by implementing directly the Barrier | ||
90 | +protocol into QEMU. | ||
91 | + | ||
92 | +`Barrier <https://github.com/debauchee/barrier>`__ | ||
93 | +is a KVM (Keyboard-Video-Mouse) software forked from Symless's | ||
94 | +synergy 1.9 codebase. | ||
95 | + | ||
96 | +This protocol is enabled by adding an input-barrier object to QEMU. | ||
97 | + | ||
98 | +Syntax:: | ||
99 | + | ||
100 | + input-barrier,id=<object-id>,name=<guest display name> | ||
101 | + [,server=<barrier server address>][,port=<barrier server port>] | ||
102 | + [,x-origin=<x-origin>][,y-origin=<y-origin>] | ||
103 | + [,width=<width>][,height=<height>] | ||
104 | + | ||
105 | +The object can be added on the QEMU command line, for instance with:: | ||
106 | + | ||
107 | + -object input-barrier,id=barrier0,name=VM-1 | ||
108 | + | ||
109 | +where VM-1 is the name the display configured in the Barrier server | ||
110 | +on the host providing the mouse and the keyboard events. | ||
111 | + | ||
112 | +by default ``<barrier server address>`` is ``localhost``, | ||
113 | +``<port>`` is ``24800``, ``<x-origin>`` and ``<y-origin>`` are set to ``0``, | ||
114 | +``<width>`` and ``<height>`` to ``1920`` and ``1080``. | ||
115 | + | ||
116 | +If the Barrier server is stopped QEMU needs to be reconnected manually, | ||
117 | +by removing and re-adding the input-barrier object, for instance | ||
118 | +with the help of the HMP monitor:: | ||
119 | + | ||
120 | + (qemu) object_del barrier0 | ||
121 | + (qemu) object_add input-barrier,id=barrier0,name=VM-1 | ||
122 | diff --git a/docs/system/index.rst b/docs/system/index.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | 123 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 124 | --- a/docs/system/index.rst |
17 | +++ b/target/arm/helper.c | 125 | +++ b/docs/system/index.rst |
18 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | 126 | @@ -XXX,XX +XXX,XX @@ or Hypervisor.Framework. |
19 | return CP_ACCESS_OK; | 127 | linuxboot |
20 | } | 128 | generic-loader |
21 | 129 | guest-loader | |
22 | +/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ | 130 | + barrier |
23 | +static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | 131 | vnc-security |
24 | + bool isread) | 132 | tls |
25 | +{ | 133 | secrets |
26 | + if (arm_current_el(env) == 1) { | ||
27 | + uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | ||
28 | + if (arm_hcr_el2_eff(env) & trap) { | ||
29 | + return CP_ACCESS_TRAP_EL2; | ||
30 | + } | ||
31 | + } | ||
32 | + return CP_ACCESS_OK; | ||
33 | +} | ||
34 | + | ||
35 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
36 | { | ||
37 | ARMCPU *cpu = env_archcpu(env); | ||
38 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = { | ||
39 | */ | ||
40 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
41 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | ||
42 | - .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | ||
43 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
44 | + .secure = ARM_CP_SECSTATE_NS, | ||
45 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | ||
46 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | ||
47 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, | ||
48 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | ||
49 | - .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | ||
50 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
51 | + .secure = ARM_CP_SECSTATE_S, | ||
52 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | ||
53 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | ||
54 | REGINFO_SENTINEL | ||
55 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = { | ||
56 | /* MMU Domain access control / MPU write buffer control */ | ||
57 | { .name = "DACR", | ||
58 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | ||
59 | - .access = PL1_RW, .resetvalue = 0, | ||
60 | + .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, | ||
61 | .writefn = dacr_write, .raw_writefn = raw_write, | ||
62 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | ||
63 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | ||
64 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { | ||
65 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, | ||
66 | .access = PL0_W, .type = ARM_CP_NOP }, | ||
67 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, | ||
68 | - .access = PL1_RW, | ||
69 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
70 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), | ||
71 | offsetof(CPUARMState, cp15.ifar_ns) }, | ||
72 | .resetvalue = 0, }, | ||
73 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
74 | */ | ||
75 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | ||
76 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | ||
77 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
78 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
79 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
80 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | ||
81 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | ||
82 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
83 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
84 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
85 | /* MAIR can just read-as-written because we don't implement caches | ||
86 | * and so don't need to care about memory attributes. | ||
87 | */ | ||
88 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | ||
89 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | ||
90 | - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | ||
91 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
92 | + .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | ||
93 | .resetvalue = 0 }, | ||
94 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, | ||
95 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | ||
96 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
97 | * handled in the field definitions. | ||
98 | */ | ||
99 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, | ||
100 | - .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, | ||
101 | + .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | ||
102 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
103 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), | ||
104 | offsetof(CPUARMState, cp15.mair0_ns) }, | ||
105 | .resetfn = arm_cp_reset_ignore }, | ||
106 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, | ||
107 | - .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, | ||
108 | + .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, | ||
109 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
110 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), | ||
111 | offsetof(CPUARMState, cp15.mair1_ns) }, | ||
112 | .resetfn = arm_cp_reset_ignore }, | ||
113 | @@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
114 | |||
115 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { | ||
116 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
117 | - .access = PL1_RW, .type = ARM_CP_ALIAS, | ||
118 | + .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, | ||
119 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), | ||
120 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, | ||
121 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | ||
122 | - .access = PL1_RW, .resetvalue = 0, | ||
123 | + .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, | ||
124 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | ||
125 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | ||
126 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, | ||
127 | - .access = PL1_RW, .resetvalue = 0, | ||
128 | + .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, | ||
129 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | ||
130 | offsetof(CPUARMState, cp15.dfar_ns) } }, | ||
131 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | ||
132 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
133 | - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | ||
134 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
135 | + .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | ||
136 | .resetvalue = 0, }, | ||
137 | REGINFO_SENTINEL | ||
138 | }; | ||
139 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { | ||
140 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
141 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, | ||
142 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | ||
143 | - .access = PL1_RW, | ||
144 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
145 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, | ||
146 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, | ||
147 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, | ||
148 | - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | ||
149 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
150 | + .writefn = vmsa_ttbr_write, .resetvalue = 0, | ||
151 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | ||
152 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | ||
153 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, | ||
154 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, | ||
155 | - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | ||
156 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
157 | + .writefn = vmsa_ttbr_write, .resetvalue = 0, | ||
158 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | ||
159 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | ||
160 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, | ||
161 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | ||
162 | - .access = PL1_RW, .writefn = vmsa_tcr_el12_write, | ||
163 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
164 | + .writefn = vmsa_tcr_el12_write, | ||
165 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | ||
166 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, | ||
167 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | ||
168 | - .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | ||
169 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
170 | + .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | ||
171 | .raw_writefn = vmsa_ttbcr_raw_write, | ||
172 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), | ||
173 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | ||
174 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
175 | */ | ||
176 | static const ARMCPRegInfo ttbcr2_reginfo = { | ||
177 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | ||
178 | - .access = PL1_RW, .type = ARM_CP_ALIAS, | ||
179 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
180 | + .type = ARM_CP_ALIAS, | ||
181 | .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), | ||
182 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, | ||
183 | }; | ||
184 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { | ||
185 | /* NOP AMAIR0/1 */ | ||
186 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, | ||
187 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | ||
188 | - .access = PL1_RW, .type = ARM_CP_CONST, | ||
189 | - .resetvalue = 0 }, | ||
190 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
191 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
192 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ | ||
193 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, | ||
194 | - .access = PL1_RW, .type = ARM_CP_CONST, | ||
195 | - .resetvalue = 0 }, | ||
196 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
197 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
198 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, | ||
199 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, | ||
200 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | ||
201 | offsetof(CPUARMState, cp15.par_ns)} }, | ||
202 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, | ||
203 | - .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | ||
204 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
205 | + .type = ARM_CP_64BIT | ARM_CP_ALIAS, | ||
206 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | ||
207 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | ||
208 | .writefn = vmsa_ttbr_write, }, | ||
209 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, | ||
210 | - .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | ||
211 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
212 | + .type = ARM_CP_64BIT | ARM_CP_ALIAS, | ||
213 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | ||
214 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | ||
215 | .writefn = vmsa_ttbr_write, }, | ||
216 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
217 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
218 | /* MMU Domain access control / MPU write buffer control */ | ||
219 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, | ||
220 | - .access = PL1_RW, .resetvalue = 0, | ||
221 | + .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, | ||
222 | .writefn = dacr_write, .raw_writefn = raw_write, | ||
223 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | ||
224 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | ||
225 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
226 | ARMCPRegInfo sctlr = { | ||
227 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, | ||
228 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | ||
229 | - .access = PL1_RW, | ||
230 | + .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
231 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | ||
232 | offsetof(CPUARMState, cp15.sctlr_ns) }, | ||
233 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, | ||
234 | -- | 134 | -- |
235 | 2.20.1 | 135 | 2.20.1 |
236 | 136 | ||
237 | 137 | diff view generated by jsdifflib |