[PULL 00/33] target-arm queue
[PULL 00/72] target-arm queue
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Another arm pullreq; nothing particularly exciting here.
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
handling series. (Lots more in my to-review queue, but I don't
3
like pullreqs growing too close to a hundred patches at a time :-))
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4
5
thanks
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-- PMM
6
-- PMM
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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The following changes since commit e27d5b488ef08408691bfed61f34ee2858136287:
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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8
Merge remote-tracking branch 'remotes/juanquintela/tags/pull-migration-pull-request' into staging (2020-02-28 14:02:31 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200228
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 1904f9b5f1d94fe12fe021db6b504c87d684f6db:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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16
hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 (2020-02-28 16:14:57 +0000)
18
MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
target-arm queue:
20
* hw/arm: Use TYPE_PL011 to create serial port
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
21
* target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
22
* hw/arm/integratorcp: Map the audio codec controller
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
23
* GICv2: Correctly implement the limited number of priority bits
25
* fpu: Minor NaN-related cleanups
24
* target/arm: refactoring of VFP related feature checks and decode
26
* MAINTAINERS: email address updates
25
* xilinx_zynq: Fix USB port instantiation
26
* acceptance tests for n800, n810, integratorcp
27
* Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX
28
* arm_gic_kvm: Don't assume kernel can provide a GICv2
29
(provide better error message for user error)
30
27
31
----------------------------------------------------------------
28
----------------------------------------------------------------
32
Gavin Shan (1):
29
Bernhard Beschow (5):
33
hw/arm: Use TYPE_PL011 to create serial port
30
hw/net/lan9118: Extract lan9118_phy
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
34
35
35
Guenter Roeck (2):
36
Leif Lindholm (1):
36
hw/arm/xilinx_zynq: Fix USB port instantiation
37
MAINTAINERS: update email address for Leif Lindholm
37
hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class
38
38
39
Peter Maydell (5):
39
Peter Maydell (54):
40
target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
target/arm: Implement v8.3-RCPC
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
target/arm: Implement v8.4-RCPC
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
target/arm: Implement ARMv8.3-CCIDX
43
tests/fp: Explicitly set inf-zero-nan rule
44
hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
45
94
46
Philippe Mathieu-Daudé (3):
95
Richard Henderson (11):
47
hw/arm/integratorcp: Map the audio codec controller
96
target/arm: Copy entire float_status in is_ebf
48
tests/acceptance: Extract boot_integratorcp() from test_integratorcp()
97
softfloat: Inline pickNaNMulAdd
49
tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
50
107
51
Richard Henderson (17):
108
Vikram Garhwal (1):
52
target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
109
MAINTAINERS: Add correct email address for Vikram Garhwal
53
target/arm: Add isar_feature_aa32_vfp_simd
54
target/arm: Rename isar_feature_aa32_fpdp_v2
55
target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
56
target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
57
target/arm: Perform fpdp_v2 check first
58
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
59
target/arm: Add missing checks for fpsp_v2
60
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
61
target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
62
target/arm: Move VLLDM and VLSTM to vfp.decode
63
target/arm: Move the vfp decodetree calls next to the base isa
64
linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
65
target/arm: Remove ARM_FEATURE_VFP*
66
target/arm: Add formats for some vfp 2 and 3-register insns
67
target/arm: Split VFM decode
68
target/arm: Split VMINMAXNM decode
69
110
70
Sai Pavan Boddu (3):
111
MAINTAINERS | 4 +-
71
arm_gic: Mask the un-supported priority bits
112
include/fpu/softfloat-helpers.h | 38 +++-
72
cpu/a9mpcore: Set number of GIC priority bits to 5
113
include/fpu/softfloat-types.h | 89 +++++++-
73
cpu/arm11mpcore: Set number of GIC priority bits to 4
114
include/hw/net/imx_fec.h | 9 +-
74
115
include/hw/net/lan9118_phy.h | 37 ++++
75
Thomas Huth (2):
116
include/hw/net/mii.h | 6 +
76
tests/acceptance: Add a test for the N800 and N810 arm machines
117
target/mips/fpu_helper.h | 20 ++
77
tests/acceptance: Add a test for the integratorcp arm machine
118
target/sparc/helper.h | 4 +-
78
119
fpu/softfloat.c | 19 ++
79
include/hw/intc/arm_gic.h | 2 +
120
hw/net/imx_fec.c | 146 ++------------
80
include/hw/intc/arm_gic_common.h | 1 +
121
hw/net/lan9118.c | 137 ++-----------
81
target/arm/cpu.h | 88 +++++-
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
82
hw/arm/integratorcp.c | 1 +
123
linux-user/arm/nwfpe/fpa11.c | 5 +
83
hw/arm/sbsa-ref.c | 3 +-
124
target/alpha/cpu.c | 2 +
84
hw/arm/virt.c | 3 +-
125
target/arm/cpu.c | 10 +
85
hw/arm/xilinx_zynq.c | 5 +-
126
target/arm/tcg/vec_helper.c | 20 +-
86
hw/arm/xlnx-versal.c | 3 +-
127
target/hexagon/cpu.c | 2 +
87
hw/cpu/a9mpcore.c | 4 +
128
target/hppa/fpu_helper.c | 12 ++
88
hw/cpu/arm11mpcore.c | 5 +
129
target/i386/tcg/fpu_helper.c | 12 ++
89
hw/intc/arm_gic.c | 33 +-
130
target/loongarch/tcg/fpu_helper.c | 14 +-
90
hw/intc/arm_gic_common.c | 1 +
131
target/m68k/cpu.c | 14 +-
91
hw/intc/arm_gic_kvm.c | 9 +
132
target/m68k/fpu_helper.c | 6 +-
92
hw/intc/armv7m_nvic.c | 20 +-
133
target/m68k/helper.c | 6 +-
93
hw/usb/hcd-ehci-sysbus.c | 17 -
134
target/microblaze/cpu.c | 2 +
94
linux-user/arm/signal.c | 4 +-
135
target/mips/msa.c | 10 +
95
linux-user/elfload.c | 25 +-
136
target/openrisc/cpu.c | 2 +
96
target/arm/arch_dump.c | 11 +-
137
target/ppc/cpu_init.c | 19 ++
97
target/arm/cpu.c | 44 +--
138
target/ppc/fpu_helper.c | 3 +-
98
target/arm/cpu64.c | 5 +-
139
target/riscv/cpu.c | 2 +
99
target/arm/helper.c | 23 +-
140
target/rx/cpu.c | 2 +
100
target/arm/kvm32.c | 5 -
141
target/s390x/cpu.c | 5 +
101
target/arm/kvm64.c | 1 -
142
target/sh4/cpu.c | 2 +
102
target/arm/m_helper.c | 11 +-
143
target/sparc/cpu.c | 6 +
103
target/arm/machine.c | 5 +-
144
target/sparc/fop_helper.c | 8 +-
104
target/arm/translate-a64.c | 114 +++++++
145
target/sparc/translate.c | 4 +-
105
target/arm/translate-vfp.inc.c | 448 +++++++++++++++++----------
146
target/tricore/helper.c | 2 +
106
target/arm/translate.c | 122 ++------
147
target/xtensa/cpu.c | 4 +
107
MAINTAINERS | 2 +
148
target/xtensa/fpu_helper.c | 3 +-
108
hw/arm/Kconfig | 1 +
149
tests/fp/fp-bench.c | 7 +
109
target/arm/vfp-uncond.decode | 12 +-
150
tests/fp/fp-test-log2.c | 1 +
110
target/arm/vfp.decode | 153 ++++-----
151
tests/fp/fp-test.c | 7 +
111
tests/acceptance/machine_arm_integratorcp.py | 99 ++++++
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
112
tests/acceptance/machine_arm_n8x0.py | 49 +++
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
113
34 files changed, 865 insertions(+), 464 deletions(-)
154
.mailmap | 5 +-
114
create mode 100644 tests/acceptance/machine_arm_integratorcp.py
155
hw/net/Kconfig | 5 +
115
create mode 100644 tests/acceptance/machine_arm_n8x0.py
156
hw/net/meson.build | 1 +
116
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 31/33] target/arm: Implement v8.4-RCPC
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
The v8.4-RCPC extension implements some new instructions:
1
From: Bernhard Beschow <shentey@gmail.com>
2
* LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW
3
* STLUR, STLURB, STLURH
4
2
5
These are all in a new subgroup of encodings that sits below the
3
A very similar implementation of the same device exists in imx_fec. Prepare for
6
top-level "Loads and Stores" group in the Arm ARM.
4
a common implementation by extracting a device model into its own files.
7
5
8
The STLUR* instructions have standard store-release semantics; the
6
Some migration state has been moved into the new device model which breaks
9
LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose
7
migration compatibility for the following machines:
10
to implement them as the slightly stronger Load-Acquire.
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
11
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200224172846.13053-4-peter.maydell@linaro.org
15
---
22
---
16
target/arm/cpu.h | 5 +++
23
include/hw/net/lan9118_phy.h | 37 ++++++++
17
linux-user/elfload.c | 1 +
24
hw/net/lan9118.c | 137 +++++-----------------------
18
target/arm/cpu64.c | 2 +-
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
19
target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
20
4 files changed, 97 insertions(+), 1 deletion(-)
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
21
31
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
23
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
77
--- a/hw/net/lan9118.c
25
+++ b/target/arm/cpu.h
78
+++ b/hw/net/lan9118.c
26
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
79
@@ -XXX,XX +XXX,XX @@
27
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
28
}
141
}
29
142
30
+static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
143
-static void phy_update_irq(lan9118_state *s)
31
+{
144
+static void lan9118_update_irq(void *opaque, int n, int level)
32
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
145
{
33
+}
146
- if (s->phy_int & s->phy_int_mask) {
34
+
147
+ lan9118_state *s = opaque;
35
/*
148
+
36
* Feature tests for "does this exist in either 32-bit or 64-bit?"
149
+ if (level) {
37
*/
150
s->int_sts |= PHY_INT;
38
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
151
} else {
39
index XXXXXXX..XXXXXXX 100644
152
s->int_sts &= ~PHY_INT;
40
--- a/linux-user/elfload.c
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
41
+++ b/linux-user/elfload.c
154
lan9118_update(s);
42
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
43
GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
44
GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
45
GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
46
+ GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC);
47
48
return hwcaps;
49
}
155
}
50
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
156
51
index XXXXXXX..XXXXXXX 100644
157
-static void phy_update_link(lan9118_state *s)
52
--- a/target/arm/cpu64.c
158
-{
53
+++ b/target/arm/cpu64.c
159
- /* Autonegotiation status mirrors link status. */
54
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
160
- if (qemu_get_queue(s->nic)->link_down) {
55
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
161
- s->phy_status &= ~0x0024;
56
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
162
- s->phy_int |= PHY_INT_DOWN;
57
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
163
- } else {
58
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */
164
- s->phy_status |= 0x0024;
59
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
165
- s->phy_int |= PHY_INT_ENERGYON;
60
cpu->isar.id_aa64isar1 = t;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
61
167
- }
62
t = cpu->isar.id_aa64pfr0;
168
- phy_update_irq(s);
63
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
169
-}
64
index XXXXXXX..XXXXXXX 100644
170
-
65
--- a/target/arm/translate-a64.c
171
static void lan9118_set_link(NetClientState *nc)
66
+++ b/target/arm/translate-a64.c
172
{
67
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
186
}
187
188
static void lan9118_reset(DeviceState *d)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
68
}
208
}
69
}
209
}
70
210
71
+/*
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
72
+ * LDAPR/STLR (unscaled immediate)
212
-{
73
+ *
213
- uint32_t val;
74
+ * 31 30 24 22 21 12 10 5 0
214
-
75
+ * +------+-------------+-----+---+--------+-----+----+-----+
215
- switch (reg) {
76
+ * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
216
- case 0: /* Basic Control */
77
+ * +------+-------------+-----+---+--------+-----+----+-----+
217
- return s->phy_control;
78
+ *
218
- case 1: /* Basic Status */
79
+ * Rt: source or destination register
219
- return s->phy_status;
80
+ * Rn: base register
220
- case 2: /* ID1 */
81
+ * imm9: unscaled immediate offset
221
- return 0x0007;
82
+ * opc: 00: STLUR*, 01/10/11: various LDAPUR*
222
- case 3: /* ID2 */
83
+ * size: size of load/store
223
- return 0xc0d1;
84
+ */
224
- case 4: /* Auto-neg advertisement */
85
+static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
225
- return s->phy_advertise;
86
+{
226
- case 5: /* Auto-neg Link Partner Ability */
87
+ int rt = extract32(insn, 0, 5);
227
- return 0x0f71;
88
+ int rn = extract32(insn, 5, 5);
228
- case 6: /* Auto-neg Expansion */
89
+ int offset = sextract32(insn, 12, 9);
229
- return 1;
90
+ int opc = extract32(insn, 22, 2);
230
- /* TODO 17, 18, 27, 29, 30, 31 */
91
+ int size = extract32(insn, 30, 2);
231
- case 29: /* Interrupt source. */
92
+ TCGv_i64 clean_addr, dirty_addr;
232
- val = s->phy_int;
93
+ bool is_store = false;
233
- s->phy_int = 0;
94
+ bool is_signed = false;
234
- phy_update_irq(s);
95
+ bool extend = false;
235
- return val;
96
+ bool iss_sf;
236
- case 30: /* Interrupt mask */
97
+
237
- return s->phy_int_mask;
98
+ if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
238
- default:
99
+ unallocated_encoding(s);
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
100
+ return;
304
+ return;
101
+ }
305
+ }
102
+
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
103
+ switch (opc) {
307
+
104
+ case 0: /* STLURB */
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
105
+ is_store = true;
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
106
+ break;
396
+ break;
107
+ case 1: /* LDAPUR* */
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
108
+ break;
399
+ break;
109
+ case 2: /* LDAPURS* 64-bit variant */
400
+ /* TODO 17, 18, 27, 31 */
110
+ if (size == 3) {
401
+ case 30: /* Interrupt mask */
111
+ unallocated_encoding(s);
402
+ s->int_mask = val & 0xff;
112
+ return;
403
+ lan9118_phy_update_irq(s);
113
+ }
114
+ is_signed = true;
115
+ break;
116
+ case 3: /* LDAPURS* 32-bit variant */
117
+ if (size > 1) {
118
+ unallocated_encoding(s);
119
+ return;
120
+ }
121
+ is_signed = true;
122
+ extend = true; /* zero-extend 32->64 after signed load */
123
+ break;
404
+ break;
124
+ default:
405
+ default:
125
+ g_assert_not_reached();
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
126
+ }
408
+ }
127
+
409
+}
128
+ iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
410
+
129
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
130
+ if (rn == 31) {
412
+{
131
+ gen_check_sp_alignment(s);
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
132
+ }
423
+ }
133
+
424
+ lan9118_phy_update_irq(s);
134
+ dirty_addr = read_cpu_reg_sp(s, rn, 1);
425
+}
135
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
426
+
136
+ clean_addr = clean_data_tbi(s, dirty_addr);
427
+void lan9118_phy_reset(Lan9118PhyState *s)
137
+
428
+{
138
+ if (is_store) {
429
+ s->control = 0x3000;
139
+ /* Store-Release semantics */
430
+ s->status = 0x7809;
140
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
431
+ s->advertise = 0x01e1;
141
+ do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true);
432
+ s->int_mask = 0;
142
+ } else {
433
+ s->ints = 0;
143
+ /*
434
+ lan9118_phy_update_link(s, s->link_down);
144
+ * Load-AcquirePC semantics; we implement as the slightly more
435
+}
145
+ * restrictive Load-Acquire.
436
+
146
+ */
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
147
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend,
438
+{
148
+ true, rt, iss_sf, true);
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
149
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
150
+ }
463
+ }
151
+}
464
+};
152
+
465
+
153
/* Load/store register (all forms) */
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
154
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
467
+{
155
{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
156
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
157
case 0x0d: /* AdvSIMD load/store single structure */
470
+
158
disas_ldst_single_struct(s, insn);
471
+ rc->phases.hold = lan9118_phy_reset_hold;
159
break;
472
+ dc->vmsd = &vmstate_lan9118_phy;
160
+ case 0x19: /* LDAPR/STLR (unscaled immediate) */
473
+}
161
+ if (extract32(insn, 10, 2) != 0 ||
474
+
162
+ extract32(insn, 21, 1) != 0) {
475
+static const TypeInfo types[] = {
163
+ unallocated_encoding(s);
476
+ {
164
+ break;
477
+ .name = TYPE_LAN9118_PHY,
165
+ }
478
+ .parent = TYPE_SYS_BUS_DEVICE,
166
+ disas_ldst_ldapr_stlr(s, insn);
479
+ .instance_size = sizeof(Lan9118PhyState),
167
+ break;
480
+ .instance_init = lan9118_phy_init,
168
default:
481
+ .class_init = lan9118_phy_class_init,
169
unallocated_encoding(s);
482
+ }
170
break;
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
171
--
515
--
172
2.20.1
516
2.34.1
173
174
diff view generated by jsdifflib
[PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Xilinx USB devices are now instantiated through TYPE_CHIPIDEA,
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
and xlnx support in the EHCI code is no longer needed.
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
5
6
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
Some migration state how resides in the new device model which breaks migration
7
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
8
compatibility for the following machines:
8
Message-id: 20200215122354.13706-3-linux@roeck-us.net
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
19
---
11
hw/usb/hcd-ehci-sysbus.c | 17 -----------------
20
include/hw/net/imx_fec.h | 9 ++-
12
1 file changed, 17 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
13
26
14
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
15
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/usb/hcd-ehci-sysbus.c
29
--- a/include/hw/net/imx_fec.h
17
+++ b/hw/usb/hcd-ehci-sysbus.c
30
+++ b/include/hw/net/imx_fec.h
18
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_platform_type_info = {
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
19
.class_init = ehci_platform_class_init,
32
#define TYPE_IMX_ENET "imx.enet"
33
34
#include "hw/sysbus.h"
35
+#include "hw/net/lan9118_phy.h"
36
+#include "hw/irq.h"
37
#include "net/net.h"
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
20
};
80
};
21
81
22
-static void ehci_xlnx_class_init(ObjectClass *oc, void *data)
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
23
-{
104
-{
24
- SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
105
- /* Autonegotiation status mirrors link status. */
25
- DeviceClass *dc = DEVICE_CLASS(oc);
106
- if (qemu_get_queue(s->nic)->link_down) {
26
-
107
- trace_imx_phy_update_link("down");
27
- set_bit(DEVICE_CATEGORY_USB, dc->categories);
108
- s->phy_status &= ~0x0024;
28
- sec->capsbase = 0x100;
109
- s->phy_int |= PHY_INT_DOWN;
29
- sec->opregbase = 0x140;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
30
-}
123
-}
31
-
124
-
32
-static const TypeInfo ehci_xlnx_type_info = {
125
-static void imx_phy_reset(IMXFECState *s)
33
- .name = "xlnx,ps7-usb",
126
-{
34
- .parent = TYPE_SYS_BUS_EHCI,
127
- trace_imx_phy_reset();
35
- .class_init = ehci_xlnx_class_init,
128
-
36
-};
129
- s->phy_status = 0x7809;
37
-
130
- s->phy_control = 0x3000;
38
static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
39
{
140
{
40
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
141
- uint32_t val;
41
@@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void)
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
42
{
353
{
43
type_register_static(&ehci_type_info);
354
+ trace_lan9118_phy_write(val, reg);
44
type_register_static(&ehci_platform_type_info);
355
+
45
- type_register_static(&ehci_xlnx_type_info);
356
switch (reg) {
46
type_register_static(&ehci_exynos4210_type_info);
357
case 0: /* Basic Control */
47
type_register_static(&ehci_tegra2_type_info);
358
if (val & 0x8000) {
48
type_register_static(&ehci_ppc4xx_type_info);
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
49
--
471
--
50
2.20.1
472
2.34.1
51
52
diff view generated by jsdifflib
[PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Add a test that verifies the Tux logo is displayed on the framebuffer.
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
4
5
5
We simply follow the OpenCV "Template Matching with Multiple Objects"
6
Fixes: 2a424990170b "LAN9118 emulation"
6
tutorial, replacing Lionel Messi by Tux:
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
When OpenCV and NumPy are installed, this test can be run using:
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
10
11
$ AVOCADO_ALLOW_UNTRUSTED_CODE=hmmm \
12
avocado --show=app,framebuffer run -t device:framebuffer \
13
tests/acceptance/machine_arm_integratorcp.py
14
JOB ID : 8c46b0f8269242e87d738247883ea2a470df949e
15
JOB LOG : avocado/job-results/job-2020-01-31T21.38-8c46b0f/job.log
16
(1/1) tests/acceptance/machine_arm_integratorcp.py:IntegratorMachine.test_framebuffer_tux_logo:
17
framebuffer: found Tux at position [x, y] = (0, 0)
18
PASS (3.96 s)
19
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
20
JOB TIME : 4.23 s
21
22
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
24
Message-id: 20200225172501.29609-5-philmd@redhat.com
25
Message-Id: <20200131211102.29612-3-f4bug@amsat.org>
26
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
12
---
29
tests/acceptance/machine_arm_integratorcp.py | 52 ++++++++++++++++++++
13
hw/net/lan9118_phy.c | 2 +-
30
1 file changed, 52 insertions(+)
14
1 file changed, 1 insertion(+), 1 deletion(-)
31
15
32
diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/tests/acceptance/machine_arm_integratorcp.py
18
--- a/hw/net/lan9118_phy.c
35
+++ b/tests/acceptance/machine_arm_integratorcp.py
19
+++ b/hw/net/lan9118_phy.c
36
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
37
# later. See the COPYING file in the top-level directory.
21
val = s->advertise;
38
22
break;
39
import os
23
case 5: /* Auto-neg Link Partner Ability */
40
+import logging
24
- val = 0x0f71;
41
25
+ val = 0x0fe1;
42
from avocado import skipUnless
26
break;
43
from avocado_qemu import Test
27
case 6: /* Auto-neg Expansion */
44
from avocado_qemu import wait_for_console_pattern
28
val = 1;
45
46
+
47
+NUMPY_AVAILABLE = True
48
+try:
49
+ import numpy as np
50
+except ImportError:
51
+ NUMPY_AVAILABLE = False
52
+
53
+CV2_AVAILABLE = True
54
+try:
55
+ import cv2
56
+except ImportError:
57
+ CV2_AVAILABLE = False
58
+
59
+
60
class IntegratorMachine(Test):
61
62
timeout = 90
63
@@ -XXX,XX +XXX,XX @@ class IntegratorMachine(Test):
64
"""
65
self.boot_integratorcp()
66
wait_for_console_pattern(self, 'Log in as root')
67
+
68
+ @skipUnless(NUMPY_AVAILABLE, 'Python NumPy not installed')
69
+ @skipUnless(CV2_AVAILABLE, 'Python OpenCV not installed')
70
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
71
+ def test_framebuffer_tux_logo(self):
72
+ """
73
+ Boot Linux and verify the Tux logo is displayed on the framebuffer.
74
+ :avocado: tags=arch:arm
75
+ :avocado: tags=machine:integratorcp
76
+ :avocado: tags=device:pl110
77
+ :avocado: tags=device:framebuffer
78
+ """
79
+ screendump_path = os.path.join(self.workdir, "screendump.pbm")
80
+ tuxlogo_url = ('https://github.com/torvalds/linux/raw/v2.6.12/'
81
+ 'drivers/video/logo/logo_linux_vga16.ppm')
82
+ tuxlogo_hash = '3991c2ddbd1ddaecda7601f8aafbcf5b02dc86af'
83
+ tuxlogo_path = self.fetch_asset(tuxlogo_url, asset_hash=tuxlogo_hash)
84
+
85
+ self.boot_integratorcp()
86
+ framebuffer_ready = 'Console: switching to colour frame buffer device'
87
+ wait_for_console_pattern(self, framebuffer_ready)
88
+ self.vm.command('human-monitor-command', command_line='stop')
89
+ self.vm.command('human-monitor-command',
90
+ command_line='screendump %s' % screendump_path)
91
+ logger = logging.getLogger('framebuffer')
92
+
93
+ cpu_count = 1
94
+ match_threshold = 0.92
95
+ screendump_bgr = cv2.imread(screendump_path)
96
+ screendump_gray = cv2.cvtColor(screendump_bgr, cv2.COLOR_BGR2GRAY)
97
+ result = cv2.matchTemplate(screendump_gray, cv2.imread(tuxlogo_path, 0),
98
+ cv2.TM_CCOEFF_NORMED)
99
+ loc = np.where(result >= match_threshold)
100
+ tux_count = 0
101
+ for tux_count, pt in enumerate(zip(*loc[::-1]), start=1):
102
+ logger.debug('found Tux at position [x, y] = %s', pt)
103
+ self.assertGreaterEqual(tux_count, cpu_count)
104
--
29
--
105
2.20.1
30
2.34.1
106
107
diff view generated by jsdifflib
[PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp()
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
As we want to re-use this code, extract it as a new function.
3
Prefer named constants over magic values for better readability.
4
Since we are using the PL011 serial console, add a Avocado tag
5
to ease filtering of tests.
6
4
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20200225172501.29609-4-philmd@redhat.com
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
tests/acceptance/machine_arm_integratorcp.py | 18 +++++++++++-------
11
include/hw/net/mii.h | 6 +++++
14
1 file changed, 11 insertions(+), 7 deletions(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
15
14
16
diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/acceptance/machine_arm_integratorcp.py
17
--- a/include/hw/net/mii.h
19
+++ b/tests/acceptance/machine_arm_integratorcp.py
18
+++ b/include/hw/net/mii.h
20
@@ -XXX,XX +XXX,XX @@ class IntegratorMachine(Test):
19
@@ -XXX,XX +XXX,XX @@
21
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
22
timeout = 90
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
23
22
24
- @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
25
- def test_integratorcp_console(self):
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
26
- """
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
27
- Boots the Linux kernel and checks that the console is operational
26
#define MII_ANAR_TXFD (1 << 8)
28
- :avocado: tags=arch:arm
27
@@ -XXX,XX +XXX,XX @@
29
- :avocado: tags=machine:integratorcp
28
#define MII_ANAR_10FD (1 << 6)
30
- """
29
#define MII_ANAR_10 (1 << 5)
31
+ def boot_integratorcp(self):
30
#define MII_ANAR_CSMACD (1 << 0)
32
kernel_url = ('https://github.com/zayac/qemu-arm/raw/master/'
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
33
'arm-test/kernel/zImage.integrator')
32
34
kernel_hash = '0d7adba893c503267c946a3cbdc63b4b54f25468'
33
#define MII_ANLPAR_ACK (1 << 14)
35
@@ -XXX,XX +XXX,XX @@ class IntegratorMachine(Test):
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
36
'-initrd', initrd_path,
35
@@ -XXX,XX +XXX,XX @@
37
'-append', 'printk.time=0 console=ttyAMA0')
36
#define RTL8201CP_PHYID1 0x0000
38
self.vm.launch()
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
39
+
42
+
40
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
43
/* RealTek 8211E */
41
+ def test_integratorcp_console(self):
44
#define RTL8211E_PHYID1 0x001c
42
+ """
45
#define RTL8211E_PHYID2 0xc915
43
+ Boots the Linux kernel and checks that the console is operational
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
44
+ :avocado: tags=arch:arm
47
index XXXXXXX..XXXXXXX 100644
45
+ :avocado: tags=machine:integratorcp
48
--- a/hw/net/lan9118_phy.c
46
+ :avocado: tags=device:pl011
49
+++ b/hw/net/lan9118_phy.c
47
+ """
50
@@ -XXX,XX +XXX,XX @@
48
+ self.boot_integratorcp()
51
49
wait_for_console_pattern(self, 'Log in as root')
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
50
--
166
--
51
2.20.1
167
2.34.1
52
53
diff view generated by jsdifflib
[PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The GIC built into the ARM11MPCore is always implemented with 4
3
The real device advertises this mode and the device model already advertises
4
priority bits; set the GIC property accordingly.
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
5
6
6
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
11
[PMM: tweaked commit message]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
hw/cpu/arm11mpcore.c | 5 +++++
13
hw/net/lan9118_phy.c | 4 ++--
15
1 file changed, 5 insertions(+)
14
1 file changed, 2 insertions(+), 2 deletions(-)
16
15
17
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/cpu/arm11mpcore.c
18
--- a/hw/net/lan9118_phy.c
20
+++ b/hw/cpu/arm11mpcore.c
19
+++ b/hw/net/lan9118_phy.c
21
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
22
#include "hw/irq.h"
21
break;
23
#include "hw/qdev-properties.h"
22
case MII_ANAR:
24
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
25
+#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
26
25
- MII_ANAR_SELECT))
27
static void mpcore_priv_set_irq(void *opaque, int irq, int level)
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
28
{
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
29
@@ -XXX,XX +XXX,XX @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)
28
| MII_ANAR_TX;
30
29
break;
31
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
30
case 30: /* Interrupt mask */
32
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
33
+ qdev_prop_set_uint32(gicdev, "num-priority-bits",
34
+ ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
35
+
36
+
37
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
38
if (err != NULL) {
39
error_propagate(errp, err);
40
--
31
--
41
2.20.1
32
2.34.1
42
43
diff view generated by jsdifflib
[PULL 04/33] arm_gic: Mask the un-supported priority bits
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
The GICv2 allows the implementation to implement a variable number
7
For the cases where the infzero test in pickNaNMulAdd was
4
of priority bits; unimplemented bits in the priority registers
8
returning 2, we can delete the check entirely and allow the
5
are read as zeros, writes ignored. We were previously always
9
code to fall into the normal pick-a-NaN handling, because this
6
implementing a full 8 bits of priority, which is allowed but not
10
will return 2 anyway (input 'c' being the only NaN in this case).
7
what the real hardware typically does (which is usually to have
11
For the cases where infzero was returning 3 to indicate "return
8
4 or 5 bits of priority).
12
the default NaN", we must retain that "return 3".
9
13
10
Add a new device property to allow the number of implemented
14
For Arm, this looks like it might be a behaviour change because we
11
property bits to be specified.
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
12
20
13
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
21
For any target architecture using the "default implementation" at the
14
Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com
22
bottom of the ifdef, this is a behaviour change but will be fixing a
15
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
23
bug (where we failed to raise the Invalid exception for (0 * inf +
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
QNaN). The architectures using the default case are:
17
[PMM: improved commit message]
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
19
---
37
---
20
include/hw/intc/arm_gic.h | 2 ++
38
fpu/softfloat-parts.c.inc | 13 +++++++------
21
include/hw/intc/arm_gic_common.h | 1 +
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
22
hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++--
40
2 files changed, 8 insertions(+), 34 deletions(-)
23
hw/intc/arm_gic_common.c | 1 +
24
4 files changed, 35 insertions(+), 2 deletions(-)
25
41
26
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
27
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/intc/arm_gic.h
44
--- a/fpu/softfloat-parts.c.inc
29
+++ b/include/hw/intc/arm_gic.h
45
+++ b/fpu/softfloat-parts.c.inc
30
@@ -XXX,XX +XXX,XX @@
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
31
47
int ab_mask, int abc_mask)
32
/* Number of SGI target-list bits */
33
#define GIC_TARGETLIST_BITS 8
34
+#define GIC_MAX_PRIORITY_BITS 8
35
+#define GIC_MIN_PRIORITY_BITS 4
36
37
#define TYPE_ARM_GIC "arm_gic"
38
#define ARM_GIC(obj) \
39
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/hw/intc/arm_gic_common.h
42
+++ b/include/hw/intc/arm_gic_common.h
43
@@ -XXX,XX +XXX,XX @@ typedef struct GICState {
44
uint16_t priority_mask[GIC_NCPU_VCPU];
45
uint16_t running_priority[GIC_NCPU_VCPU];
46
uint16_t current_pending[GIC_NCPU_VCPU];
47
+ uint32_t n_prio_bits;
48
49
/* If we present the GICv2 without security extensions to a guest,
50
* the guest can configure the GICC_CTLR to configure group 1 binary point
51
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/intc/arm_gic.c
54
+++ b/hw/intc/arm_gic.c
55
@@ -XXX,XX +XXX,XX @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
56
return ret;
57
}
58
59
+static uint32_t gic_fullprio_mask(GICState *s, int cpu)
60
+{
61
+ /*
62
+ * Return a mask word which clears the unimplemented priority
63
+ * bits from a priority value for an interrupt. (Not to be
64
+ * confused with the group priority, whose mask depends on BPR.)
65
+ */
66
+ int priBits;
67
+
68
+ if (gic_is_vcpu(cpu)) {
69
+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;
70
+ } else {
71
+ priBits = s->n_prio_bits;
72
+ }
73
+ return ~0U << (8 - priBits);
74
+}
75
+
76
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
77
MemTxAttrs attrs)
78
{
48
{
79
@@ -XXX,XX +XXX,XX @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
49
int which;
80
val = 0x80 | (val >> 1); /* Non-secure view */
50
+ bool infzero = (ab_mask == float_cmask_infzero);
51
52
if (unlikely(abc_mask & float_cmask_snan)) {
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
81
}
54
}
82
55
83
+ val &= gic_fullprio_mask(s, cpu);
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
84
+
57
- ab_mask == float_cmask_infzero, s);
85
if (irq < GIC_INTERNAL) {
58
+ if (infzero) {
86
s->priority1[irq][cpu] = val;
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
87
} else {
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
88
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
89
}
90
prio = (prio << 1) & 0xff; /* Non-secure view */
91
}
92
- return prio;
93
+ return prio & gic_fullprio_mask(s, cpu);
94
}
95
96
static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
97
@@ -XXX,XX +XXX,XX @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
98
return;
99
}
100
}
101
- s->priority_mask[cpu] = pmask;
102
+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);
103
}
104
105
static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
106
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
107
return;
108
}
109
110
+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||
111
+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :
112
+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {
113
+ error_setg(errp, "num-priority-bits cannot be greater than %d"
114
+ " or less than %d", GIC_MAX_PRIORITY_BITS,
115
+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :
116
+ GIC_MIN_PRIORITY_BITS);
117
+ return;
118
+ }
61
+ }
119
+
62
+
120
/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
121
* enabled, virtualization extensions related interfaces (main virtual
64
122
* interface (s->vifaceiomem[0]) and virtual CPU interface).
65
if (s->default_nan_mode || which == 3) {
123
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
124
index XXXXXXX..XXXXXXX 100644
74
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/intc/arm_gic_common.c
75
--- a/fpu/softfloat-specialize.c.inc
126
+++ b/hw/intc/arm_gic_common.c
76
+++ b/fpu/softfloat-specialize.c.inc
127
@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
78
* the default NaN
129
/* True if the GIC should implement the virtualization extensions */
79
*/
130
DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
80
if (infzero && is_qnan(c_cls)) {
131
+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
132
DEFINE_PROP_END_OF_LIST(),
82
return 3;
133
};
83
}
134
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
135
--
165
--
136
2.20.1
166
2.34.1
137
138
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 30/33] target/arm: Implement v8.3-RCPC
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
The v8.3-RCPC extension implements three new load instructions
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
which provide slightly weaker consistency guarantees than the
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
existing load-acquire operations. For QEMU we choose to simply
3
architectures thus do different things:
4
implement them with a full LDAQ barrier.
4
* some return the default NaN
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
5
29
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200224172846.13053-3-peter.maydell@linaro.org
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
9
---
33
---
10
target/arm/cpu.h | 5 +++++
34
include/fpu/softfloat-helpers.h | 11 ++++
11
linux-user/elfload.c | 1 +
35
include/fpu/softfloat-types.h | 23 +++++++++
12
target/arm/cpu64.c | 1 +
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
13
target/arm/translate-a64.c | 24 ++++++++++++++++++++++++
37
3 files changed, 95 insertions(+), 30 deletions(-)
14
4 files changed, 31 insertions(+)
38
15
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
41
--- a/include/fpu/softfloat-helpers.h
19
+++ b/target/arm/cpu.h
42
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
21
FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
44
status->float_2nan_prop_rule = rule;
22
}
45
}
23
46
24
+static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
25
+{
49
+{
26
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
50
+ status->float_infzeronan_rule = rule;
27
+}
51
+}
28
+
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
29
/*
98
/*
30
* Feature tests for "does this exist in either 32-bit or 64-bit?"
99
* Floating Point Status. Individual architectures may maintain
31
*/
100
* several versions of float_status for different functions. The
32
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
33
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/elfload.c
111
--- a/fpu/softfloat-specialize.c.inc
35
+++ b/linux-user/elfload.c
112
+++ b/fpu/softfloat-specialize.c.inc
36
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
37
GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
38
GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
115
bool infzero, float_status *status)
39
GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
116
{
40
+ GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
41
118
+
42
return hwcaps;
119
/*
43
}
120
* We guarantee not to require the target to tell us how to
44
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
121
* pick a NaN if we're always returning the default NaN.
45
index XXXXXXX..XXXXXXX 100644
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
--- a/target/arm/cpu64.c
123
* specify.
47
+++ b/target/arm/cpu64.c
124
*/
48
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
125
assert(!status->default_nan_mode);
49
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
126
+
50
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
127
+ if (rule == float_infzeronan_none) {
51
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
128
+ /*
52
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */
129
+ * Temporarily fall back to ifdef ladder
53
cpu->isar.id_aa64isar1 = t;
130
+ */
54
131
#if defined(TARGET_ARM)
55
t = cpu->isar.id_aa64pfr0;
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
56
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
133
- * the default NaN
57
index XXXXXXX..XXXXXXX 100644
134
- */
58
--- a/target/arm/translate-a64.c
135
- if (infzero && is_qnan(c_cls)) {
59
+++ b/target/arm/translate-a64.c
136
- return 3;
60
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
137
+ /*
61
int rs = extract32(insn, 16, 5);
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
62
int rn = extract32(insn, 5, 5);
139
+ * but (inf,zero,snan) returns the input NaN.
63
int o3_opc = extract32(insn, 12, 4);
140
+ */
64
+ bool r = extract32(insn, 22, 1);
141
+ rule = float_infzeronan_dnan_if_qnan;
65
+ bool a = extract32(insn, 23, 1);
142
+#elif defined(TARGET_MIPS)
66
TCGv_i64 tcg_rs, clean_addr;
143
+ if (snan_bit_is_one(status)) {
67
AtomicThreeOpFn *fn;
144
+ /*
68
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
69
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
146
+ * case sets InvalidOp and returns the default NaN
70
case 010: /* SWP */
147
+ */
71
fn = tcg_gen_atomic_xchg_i64;
148
+ rule = float_infzeronan_dnan_always;
72
break;
149
+ } else {
73
+ case 014: /* LDAPR, LDAPRH, LDAPRB */
150
+ /*
74
+ if (!dc_isar_feature(aa64_rcpc_8_3, s) ||
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
75
+ rs != 31 || a != 1 || r != 0) {
152
+ * case sets InvalidOp and returns the input value 'c'
76
+ unallocated_encoding(s);
153
+ */
77
+ return;
154
+ rule = float_infzeronan_dnan_never;
78
+ }
155
+ }
79
+ break;
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
80
default:
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
81
unallocated_encoding(s);
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
82
return;
159
+ /*
83
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
84
gen_check_sp_alignment(s);
161
+ * case sets InvalidOp and returns the input value 'c'
85
}
162
+ */
86
clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
163
+ /*
87
+
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
88
+ if (o3_opc == 014) {
165
+ * to return an input NaN if we have one (ie c) rather than generating
89
+ /*
166
+ * a default NaN
90
+ * LDAPR* are a special case because they are a simple load, not a
167
+ */
91
+ * fetch-and-do-something op.
168
+ rule = float_infzeronan_dnan_never;
92
+ * The architectural consistency requirements here are weaker than
169
+#elif defined(TARGET_S390X)
93
+ * full load-acquire (we only need "load-acquire processor consistent"),
170
+ rule = float_infzeronan_dnan_always;
94
+ * but we choose to implement them as full LDAQ.
171
+#endif
95
+ */
172
}
96
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false,
173
97
+ true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
174
+ if (infzero) {
98
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
175
+ /*
99
+ return;
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
100
+ }
189
+ }
101
+
190
+
102
tcg_rs = read_cpu_reg(s, rs, true);
191
+#if defined(TARGET_ARM)
103
192
+
104
if (o3_opc == 1) { /* LDCLR */
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
105
--
256
--
106
2.20.1
257
2.34.1
107
108
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
[PULL 19/33] target/arm: Remove ARM_FEATURE_VFP*
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
We have converted all tests against these features
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to ISAR tests.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200224222232.13807-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 3 ---
12
target/arm/cpu.c | 25 -------------------------
13
target/arm/cpu64.c | 3 ---
14
target/arm/kvm32.c | 5 -----
15
target/arm/kvm64.c | 1 -
16
5 files changed, 37 deletions(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
23
* mapping in linux-user/elfload.c:get_elf_hwcap().
24
*/
25
enum arm_features {
26
- ARM_FEATURE_VFP,
27
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
28
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
29
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
30
@@ -XXX,XX +XXX,XX @@ enum arm_features {
31
ARM_FEATURE_V7,
32
ARM_FEATURE_THUMB2,
33
ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
34
- ARM_FEATURE_VFP3,
35
ARM_FEATURE_NEON,
36
ARM_FEATURE_M, /* Microcontroller profile. */
37
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
38
@@ -XXX,XX +XXX,XX @@ enum arm_features {
39
ARM_FEATURE_V5,
40
ARM_FEATURE_STRONGARM,
41
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
42
- ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
43
ARM_FEATURE_GENERIC_TIMER,
44
ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
45
ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
46
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
47
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
49
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
50
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
51
if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
17
* * tininess-before-rounding
52
set_feature(&cpu->env, ARM_FEATURE_PMSA);
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
53
}
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
54
- /* Similarly for the VFP feature bits */
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
55
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
21
+ * and the input NaN if it is signalling
56
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
22
*/
57
- }
23
static void arm_set_default_fp_behaviours(float_status *s)
58
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
24
{
59
- set_feature(&cpu->env, ARM_FEATURE_VFP);
25
set_float_detect_tininess(float_tininess_before_rounding, s);
60
- }
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
61
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
62
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
63
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
64
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
65
uint64_t t;
66
uint32_t u;
67
68
- unset_feature(env, ARM_FEATURE_VFP);
69
- unset_feature(env, ARM_FEATURE_VFP3);
70
- unset_feature(env, ARM_FEATURE_VFP4);
71
-
72
t = cpu->isar.id_aa64isar1;
73
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
74
cpu->isar.id_aa64isar1 = t;
75
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
76
77
cpu->dtb_compatible = "arm,arm926";
78
set_feature(&cpu->env, ARM_FEATURE_V5);
79
- set_feature(&cpu->env, ARM_FEATURE_VFP);
80
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
81
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
82
cpu->midr = 0x41069265;
83
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
84
85
cpu->dtb_compatible = "arm,arm1026";
86
set_feature(&cpu->env, ARM_FEATURE_V5);
87
- set_feature(&cpu->env, ARM_FEATURE_VFP);
88
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
89
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
90
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
91
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
92
93
cpu->dtb_compatible = "arm,arm1136";
94
set_feature(&cpu->env, ARM_FEATURE_V6);
95
- set_feature(&cpu->env, ARM_FEATURE_VFP);
96
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
97
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
98
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
99
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
100
cpu->dtb_compatible = "arm,arm1136";
101
set_feature(&cpu->env, ARM_FEATURE_V6K);
102
set_feature(&cpu->env, ARM_FEATURE_V6);
103
- set_feature(&cpu->env, ARM_FEATURE_VFP);
104
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
105
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
106
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
107
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
108
109
cpu->dtb_compatible = "arm,arm1176";
110
set_feature(&cpu->env, ARM_FEATURE_V6K);
111
- set_feature(&cpu->env, ARM_FEATURE_VFP);
112
set_feature(&cpu->env, ARM_FEATURE_VAPA);
113
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
114
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
115
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
116
117
cpu->dtb_compatible = "arm,arm11mpcore";
118
set_feature(&cpu->env, ARM_FEATURE_V6K);
119
- set_feature(&cpu->env, ARM_FEATURE_VFP);
120
set_feature(&cpu->env, ARM_FEATURE_VAPA);
121
set_feature(&cpu->env, ARM_FEATURE_MPIDR);
122
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
123
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
124
set_feature(&cpu->env, ARM_FEATURE_M);
125
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
126
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
127
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
128
cpu->midr = 0x410fc240; /* r0p0 */
129
cpu->pmsav7_dregion = 8;
130
cpu->isar.mvfr0 = 0x10110021;
131
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
132
set_feature(&cpu->env, ARM_FEATURE_M);
133
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
134
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
135
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
136
cpu->midr = 0x411fc272; /* r1p2 */
137
cpu->pmsav7_dregion = 8;
138
cpu->isar.mvfr0 = 0x10110221;
139
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
140
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
141
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
142
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
143
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
144
cpu->midr = 0x410fd213; /* r0p3 */
145
cpu->pmsav7_dregion = 16;
146
cpu->sau_sregion = 8;
147
@@ -XXX,XX +XXX,XX @@ static void cortex_r5f_initfn(Object *obj)
148
ARMCPU *cpu = ARM_CPU(obj);
149
150
cortex_r5_initfn(obj);
151
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
152
cpu->isar.mvfr0 = 0x10110221;
153
cpu->isar.mvfr1 = 0x00000011;
154
}
28
}
155
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
29
156
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
157
cpu->dtb_compatible = "arm,cortex-a8";
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
158
set_feature(&cpu->env, ARM_FEATURE_V7);
159
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
160
set_feature(&cpu->env, ARM_FEATURE_NEON);
161
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
162
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
163
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
164
165
cpu->dtb_compatible = "arm,cortex-a9";
166
set_feature(&cpu->env, ARM_FEATURE_V7);
167
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
168
set_feature(&cpu->env, ARM_FEATURE_NEON);
169
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
170
set_feature(&cpu->env, ARM_FEATURE_EL3);
171
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
172
173
cpu->dtb_compatible = "arm,cortex-a7";
174
set_feature(&cpu->env, ARM_FEATURE_V7VE);
175
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
176
set_feature(&cpu->env, ARM_FEATURE_NEON);
177
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
178
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
179
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
180
181
cpu->dtb_compatible = "arm,cortex-a15";
182
set_feature(&cpu->env, ARM_FEATURE_V7VE);
183
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
184
set_feature(&cpu->env, ARM_FEATURE_NEON);
185
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
186
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
187
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
188
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
189
--- a/target/arm/cpu64.c
33
--- a/fpu/softfloat-specialize.c.inc
190
+++ b/target/arm/cpu64.c
34
+++ b/fpu/softfloat-specialize.c.inc
191
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
192
36
/*
193
cpu->dtb_compatible = "arm,cortex-a57";
37
* Temporarily fall back to ifdef ladder
194
set_feature(&cpu->env, ARM_FEATURE_V8);
38
*/
195
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
39
-#if defined(TARGET_ARM)
196
set_feature(&cpu->env, ARM_FEATURE_NEON);
40
- /*
197
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
198
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
42
- * but (inf,zero,snan) returns the input NaN.
199
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
43
- */
200
44
- rule = float_infzeronan_dnan_if_qnan;
201
cpu->dtb_compatible = "arm,cortex-a53";
45
-#elif defined(TARGET_MIPS)
202
set_feature(&cpu->env, ARM_FEATURE_V8);
46
+#if defined(TARGET_MIPS)
203
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
47
if (snan_bit_is_one(status)) {
204
set_feature(&cpu->env, ARM_FEATURE_NEON);
48
/*
205
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
206
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
207
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
208
209
cpu->dtb_compatible = "arm,cortex-a72";
210
set_feature(&cpu->env, ARM_FEATURE_V8);
211
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
212
set_feature(&cpu->env, ARM_FEATURE_NEON);
213
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
214
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
215
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
216
index XXXXXXX..XXXXXXX 100644
217
--- a/target/arm/kvm32.c
218
+++ b/target/arm/kvm32.c
219
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
220
* bits, but a few must be tested.
221
*/
222
set_feature(&features, ARM_FEATURE_V7VE);
223
- set_feature(&features, ARM_FEATURE_VFP3);
224
set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
225
226
if (extract32(id_pfr0, 12, 4) == 1) {
227
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
228
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
229
set_feature(&features, ARM_FEATURE_NEON);
230
}
231
- if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
232
- /* FMAC support implies VFPv4 */
233
- set_feature(&features, ARM_FEATURE_VFP4);
234
- }
235
236
ahcf->features = features;
237
238
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
239
index XXXXXXX..XXXXXXX 100644
240
--- a/target/arm/kvm64.c
241
+++ b/target/arm/kvm64.c
242
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
243
* feature bits.
244
*/
245
set_feature(&features, ARM_FEATURE_V8);
246
- set_feature(&features, ARM_FEATURE_VFP4);
247
set_feature(&features, ARM_FEATURE_NEON);
248
set_feature(&features, ARM_FEATURE_AARCH64);
249
set_feature(&features, ARM_FEATURE_PMU);
250
--
50
--
251
2.20.1
51
2.34.1
252
253
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
We will shortly use these to test for VFPv2 and VFPv3
3
are NaNs. As a result different architectures have ended up with
4
in different situations.
4
different rules for propagating NaNs.
5
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
Message-id: 20200224222232.13807-4-richard.henderson@linaro.org
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
10
---
27
---
11
target/arm/cpu.h | 18 ++++++++++++++++++
28
include/fpu/softfloat-helpers.h | 11 +++
12
1 file changed, 18 insertions(+)
29
include/fpu/softfloat-types.h | 55 +++++++++++
13
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
15
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
35
--- a/include/fpu/softfloat-helpers.h
17
+++ b/target/arm/cpu.h
36
+++ b/include/fpu/softfloat-helpers.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
19
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
38
status->float_2nan_prop_rule = rule;
20
}
39
}
21
40
22
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
42
+ float_status *status)
23
+{
43
+{
24
+ /* Return true if CPU supports single precision floating point, VFPv2 */
44
+ status->float_3nan_prop_rule = rule;
25
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
26
+}
45
+}
27
+
46
+
28
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
float_status *status)
49
{
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
51
return status->float_2nan_prop_rule;
52
}
53
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
29
+{
55
+{
30
+ /* Return true if CPU supports single precision floating point, VFPv3 */
56
+ return status->float_3nan_prop_rule;
31
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
32
+}
57
+}
33
+
58
+
34
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
35
{
60
{
36
/* Return true if CPU supports double precision floating point, VFPv2 */
61
return status->float_infzeronan_rule;
37
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
159
}
160
161
+ if (rule == float_3nan_prop_none) {
162
#if defined(TARGET_ARM)
163
-
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
166
- */
167
- if (is_snan(c_cls)) {
168
- return 2;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
321
+ }
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
38
}
337
}
39
338
40
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
339
/*----------------------------------------------------------------------------
41
+{
42
+ /* Return true if CPU supports double precision floating point, VFPv3 */
43
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
44
+}
45
+
46
/*
47
* We always set the FP and SIMD FP16 fields to indicate identical
48
* levels of support (assuming SIMD is implemented at all), so
49
--
340
--
50
2.20.1
341
2.34.1
51
52
diff view generated by jsdifflib
[PULL 03/33] hw/arm/integratorcp: Map the audio codec controller
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
2
4
3
The Linux kernel displays errors why trying to detect the PL041
4
audio interface:
5
6
Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
7
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
8
CPU: VIVT data cache, VIVT instruction cache
9
OF: fdt: Machine model: ARM Integrator/CP
10
...
11
OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000
12
13
Since we have it already modelled, simply plug it.
14
15
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20200223233033.15371-2-f4bug@amsat.org
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
19
---
8
---
20
hw/arm/integratorcp.c | 1 +
9
tests/fp/fp-bench.c | 1 +
21
hw/arm/Kconfig | 1 +
10
tests/fp/fp-test.c | 1 +
22
2 files changed, 2 insertions(+)
11
2 files changed, 2 insertions(+)
23
12
24
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/integratorcp.c
15
--- a/tests/fp/fp-bench.c
27
+++ b/hw/arm/integratorcp.c
16
+++ b/tests/fp/fp-bench.c
28
@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
29
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
18
* doesn't specify match those used by the Arm architecture.
30
qdev_connect_gpio_out(dev, 1,
19
*/
31
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
32
+ sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
33
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
34
if (nd_table[0].used)
23
35
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
24
f = bench_funcs[operation][precision];
36
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/Kconfig
27
--- a/tests/fp/fp-test.c
39
+++ b/hw/arm/Kconfig
28
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ config INTEGRATOR
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
select INTEGRATOR_DEBUG
30
* doesn't specify match those used by the Arm architecture.
42
select PL011 # UART
31
*/
43
select PL031 # RTC
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ select PL041 # audio
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
45
select PL050 # keyboard/mouse
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
select PL110 # pl111 LCD controller
35
47
select PL181 # display
36
genCases_setLevel(test_level);
48
--
37
--
49
2.20.1
38
2.34.1
50
51
diff view generated by jsdifflib
[PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
All remaining tests for VFP4 are for fused multiply-add insns.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 5 +++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
4
11
5
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
6
from the !has_neon block to the (!has_vfp && !has_neon) block.
7
8
Test for vfp of the appropraite width alongside the test for simdfmac
9
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
10
already tested for ARM_FEATURE_NEON.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200224222232.13807-10-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu.h | 12 ++++++++++++
18
target/arm/cpu.c | 6 +++++-
19
target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++----
20
target/arm/translate.c | 2 +-
21
4 files changed, 36 insertions(+), 6 deletions(-)
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
28
return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
29
}
30
31
+/*
32
+ * Note that this ID register field covers both VFP and Neon FMAC,
33
+ * so should usually be tested in combination with some other
34
+ * check that confirms the presence of whichever of VFP or Neon is
35
+ * relevant, to avoid accidentally enabling a Neon feature on
36
+ * a VFP-no-Neon core or vice-versa.
37
+ */
38
+static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
39
+{
40
+ return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
41
+}
42
+
43
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
44
{
45
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
46
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
47
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
49
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
50
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
51
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
17
* * tininess-before-rounding
52
u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
53
u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
54
- u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
55
cpu->isar.mvfr1 = u;
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
56
22
+ * but note that for QEMU muladd is a * b + c, whereas for
57
u = cpu->isar.mvfr2;
23
+ * the pseudocode function the arguments are in the order c, a, b.
58
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
59
u = cpu->isar.mvfr0;
25
* and the input NaN if it is signalling
60
u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
26
*/
61
cpu->isar.mvfr0 = u;
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
62
+
28
{
63
+ /* Despite the name, this field covers both VFP and Neon */
29
set_float_detect_tininess(float_tininess_before_rounding, s);
64
+ u = cpu->isar.mvfr1;
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
65
+ u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
66
+ cpu->isar.mvfr1 = u;
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
67
}
40
}
68
41
69
if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
42
if (rule == float_3nan_prop_none) {
70
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
43
-#if defined(TARGET_ARM)
71
index XXXXXXX..XXXXXXX 100644
44
- /*
72
--- a/target/arm/translate-vfp.inc.c
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
73
+++ b/target/arm/translate-vfp.inc.c
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
47
- */
75
48
- rule = float_3nan_prop_s_cab;
76
/*
49
-#elif defined(TARGET_MIPS)
77
* Present in VFPv4 only.
50
+#if defined(TARGET_MIPS)
78
+ * Note that we can't rely on the SIMDFMAC check alone, because
51
if (snan_bit_is_one(status)) {
79
+ * in a Neon-no-VFP core that ID register field will be non-zero.
52
rule = float_3nan_prop_s_abc;
80
+ */
53
} else {
81
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
82
+ !dc_isar_feature(aa32_fpsp_v2, s)) {
83
+ return false;
84
+ }
85
+ /*
86
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
87
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
88
*/
89
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
90
- (s->vec_len != 0 || s->vec_stride != 0)) {
91
+ if (s->vec_len != 0 || s->vec_stride != 0) {
92
return false;
93
}
94
95
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
96
97
/*
98
* Present in VFPv4 only.
99
+ * Note that we can't rely on the SIMDFMAC check alone, because
100
+ * in a Neon-no-VFP core that ID register field will be non-zero.
101
+ */
102
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
103
+ !dc_isar_feature(aa32_fpdp_v2, s)) {
104
+ return false;
105
+ }
106
+ /*
107
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
108
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
109
*/
110
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
111
- (s->vec_len != 0 || s->vec_stride != 0)) {
112
+ if (s->vec_len != 0 || s->vec_stride != 0) {
113
return false;
114
}
115
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/translate.c
119
+++ b/target/arm/translate.c
120
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
121
}
122
break;
123
case NEON_3R_VFM_VQRDMLSH:
124
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
125
+ if (!dc_isar_feature(aa32_simdfmac, s)) {
126
return 1;
127
}
128
break;
129
--
54
--
130
2.20.1
55
2.34.1
131
132
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
The old name, isar_feature_aa32_fpdp, does not reflect
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
that the test includes VFPv2. We will introduce another
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
feature tests for VFPv3.
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
6
11
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200224222232.13807-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 4 ++--
13
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
14
2 files changed, 22 insertions(+), 22 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
14
--- a/target/xtensa/fpu_helper.c
19
+++ b/target/arm/cpu.h
15
+++ b/target/xtensa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
21
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
22
}
22
}
23
23
24
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
25
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
{
27
- /* Return true if CPU supports double precision floating point */
28
+ /* Return true if CPU supports double precision floating point, VFPv2 */
29
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
30
}
31
32
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
33
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-vfp.inc.c
27
--- a/fpu/softfloat-specialize.c.inc
35
+++ b/target/arm/translate-vfp.inc.c
28
+++ b/fpu/softfloat-specialize.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
37
return false;
38
}
30
}
39
31
40
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
32
if (rule == float_3nan_prop_none) {
41
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
33
-#if defined(TARGET_XTENSA)
42
return false;
34
- if (status->use_first_nan) {
35
- rule = float_3nan_prop_abc;
36
- } else {
37
- rule = float_3nan_prop_cba;
38
- }
39
-#else
40
rule = float_3nan_prop_abc;
41
-#endif
43
}
42
}
44
43
45
@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
44
assert(rule != float_3nan_prop_none);
46
return false;
47
}
48
49
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
50
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
51
return false;
52
}
53
54
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
55
return false;
56
}
57
58
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
59
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
60
return false;
61
}
62
63
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
64
return false;
65
}
66
67
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
68
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
69
return false;
70
}
71
72
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
73
return false;
74
}
75
76
- if (!dc_isar_feature(aa32_fpdp, s)) {
77
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
78
return false;
79
}
80
81
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
82
return false;
83
}
84
85
- if (!dc_isar_feature(aa32_fpdp, s)) {
86
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
87
return false;
88
}
89
90
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
91
return false;
92
}
93
94
- if (!dc_isar_feature(aa32_fpdp, s)) {
95
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
96
return false;
97
}
98
99
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
100
return false;
101
}
102
103
- if (!dc_isar_feature(aa32_fpdp, s)) {
104
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
105
return false;
106
}
107
108
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
109
return false;
110
}
111
112
- if (!dc_isar_feature(aa32_fpdp, s)) {
113
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
114
return false;
115
}
116
117
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
118
return false;
119
}
120
121
- if (!dc_isar_feature(aa32_fpdp, s)) {
122
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
123
return false;
124
}
125
126
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
127
return false;
128
}
129
130
- if (!dc_isar_feature(aa32_fpdp, s)) {
131
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
132
return false;
133
}
134
135
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
136
return false;
137
}
138
139
- if (!dc_isar_feature(aa32_fpdp, s)) {
140
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
141
return false;
142
}
143
144
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
145
return false;
146
}
147
148
- if (!dc_isar_feature(aa32_fpdp, s)) {
149
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
150
return false;
151
}
152
153
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
154
return false;
155
}
156
157
- if (!dc_isar_feature(aa32_fpdp, s)) {
158
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
159
return false;
160
}
161
162
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
163
return false;
164
}
165
166
- if (!dc_isar_feature(aa32_fpdp, s)) {
167
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
168
return false;
169
}
170
171
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
172
return false;
173
}
174
175
- if (!dc_isar_feature(aa32_fpdp, s)) {
176
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
177
return false;
178
}
179
180
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
181
return false;
182
}
183
184
- if (!dc_isar_feature(aa32_fpdp, s)) {
185
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
186
return false;
187
}
188
189
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
190
return false;
191
}
192
193
- if (!dc_isar_feature(aa32_fpdp, s)) {
194
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
195
return false;
196
}
197
198
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
199
return false;
200
}
201
202
- if (!dc_isar_feature(aa32_fpdp, s)) {
203
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
204
return false;
205
}
206
207
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
208
return false;
209
}
210
211
- if (!dc_isar_feature(aa32_fpdp, s)) {
212
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
213
return false;
214
}
215
216
--
45
--
217
2.20.1
46
2.34.1
218
219
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
[PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In our KVM GICv2 realize function, we try to cope with old kernels
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we
2
from float64 to floatx80 using a scratch float_status, because we
3
try to use the device control, and if that fails we fall back to
3
don't want the conversion to affect the CPU's floating point exception
4
assuming that the kernel has the old style KVM_CREATE_IRQCHIP and
4
status. Currently we use a zero-initialized float_status. This will
5
that it will provide a GICv2.
5
get steadily more awkward as we add config knobs to float_status
6
6
that the target must initialize. Avoid having to add any of that
7
This doesn't cater for the possibility of a kernel and hardware which
7
configuration here by instead initializing our local float_status
8
only provide a GICv3, which is very common now. On that setup we
8
from the env->fp_status.
9
will abort() later on in kvm_arm_pmu_set_irq() when we try to wire up
10
an interrupt to the GIC we failed to create:
11
12
qemu-system-aarch64: PMU: KVM_SET_DEVICE_ATTR: Invalid argument
13
qemu-system-aarch64: failed to set irq for PMU
14
Aborted
15
16
If the kernel advertises KVM_CAP_DEVICE_CTRL we should trust it if it
17
says it can't create a GICv2, rather than assuming it has one. We
18
can then produce a more helpful error message including a hint about
19
the most probable reason for the failure.
20
21
If the kernel doesn't advertise KVM_CAP_DEVICE_CTRL then it is truly
22
ancient by this point but we might as well still fall back to a
23
KVM_CREATE_IRQCHIP GICv2.
24
25
With this patch then the user misconfiguration which previously
26
caused an abort now prints:
27
qemu-system-aarch64: Initialization of device kvm-arm-gic failed: error creating in-kernel VGIC: No such device
28
Perhaps the host CPU does not support GICv2?
29
9
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
33
Tested-by: Andrew Jones <drjones@redhat.com>
34
Message-id: 20200225182435.1131-1-peter.maydell@linaro.org
35
---
13
---
36
hw/intc/arm_gic_kvm.c | 9 +++++++++
14
target/m68k/helper.c | 6 ++++--
37
1 file changed, 9 insertions(+)
15
1 file changed, 4 insertions(+), 2 deletions(-)
38
16
39
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
40
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/intc/arm_gic_kvm.c
19
--- a/target/m68k/helper.c
42
+++ b/hw/intc/arm_gic_kvm.c
20
+++ b/target/m68k/helper.c
43
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
44
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
22
CPUM68KState *env = &cpu->env;
45
&error_abort);
23
46
}
24
if (n < 8) {
47
+ } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) {
25
- float_status s = {};
48
+ error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
49
+ error_append_hint(errp,
27
+ float_status s = env->fp_status;
50
+ "Perhaps the host CPU does not support GICv2?\n");
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
51
} else if (ret != -ENODEV && ret != -ENOTSUP) {
29
}
52
+ /*
30
switch (n) {
53
+ * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
54
+ * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
32
CPUM68KState *env = &cpu->env;
55
+ * and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
33
56
+ */
34
if (n < 8) {
57
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
35
- float_status s = {};
58
return;
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
59
}
40
}
60
--
41
--
61
2.20.1
42
2.34.1
62
63
diff view generated by jsdifflib
[PULL 21/33] target/arm: Split VFM decode
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
Passing the raw o1 and o2 fields from the manual is less
8
To do this we need to pass the CPU env pointer in to the helper.
4
instructive than it might be. Do the full decode and let
5
the trans_* functions pass in booleans to a helper.
6
9
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200224222232.13807-17-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
11
---
13
---
12
target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++----
14
target/sparc/helper.h | 4 ++--
13
target/arm/vfp.decode | 17 +++++------
15
target/sparc/fop_helper.c | 8 ++++----
14
2 files changed, 55 insertions(+), 14 deletions(-)
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
15
18
16
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-vfp.inc.c
21
--- a/target/sparc/helper.h
19
+++ b/target/arm/translate-vfp.inc.c
22
+++ b/target/sparc/helper.h
20
@@ -XXX,XX +XXX,XX @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
21
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
32
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/sparc/fop_helper.c
37
+++ b/target/sparc/fop_helper.c
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
22
}
40
}
23
41
24
-static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
25
+static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
26
{
44
{
27
/*
45
/*
28
* VFNMA : fd = muladd(-fd, fn, fm)
46
* FLCMP never raises an exception nor modifies any FSR fields.
29
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
47
* Perform the comparison with a dummy fp environment.
30
48
*/
31
neon_load_reg32(vn, a->vn);
49
- float_status discard = { };
32
neon_load_reg32(vm, a->vm);
50
+ float_status discard = env->fp_status;
33
- if (a->o2) {
51
FloatRelation r;
34
+ if (neg_n) {
52
35
/* VFNMS, VFMS */
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
36
gen_helper_vfp_negs(vn, vn);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
37
}
55
g_assert_not_reached();
38
neon_load_reg32(vd, a->vd);
39
- if (a->o1 & 1) {
40
+ if (neg_d) {
41
/* VFNMA, VFNMS */
42
gen_helper_vfp_negs(vd, vd);
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
45
return true;
46
}
56
}
47
57
48
-static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
49
+static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a)
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
50
+{
51
+ return do_vfm_sp(s, a, false, false);
52
+}
53
+
54
+static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a)
55
+{
56
+ return do_vfm_sp(s, a, true, false);
57
+}
58
+
59
+static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a)
60
+{
61
+ return do_vfm_sp(s, a, false, true);
62
+}
63
+
64
+static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a)
65
+{
66
+ return do_vfm_sp(s, a, true, true);
67
+}
68
+
69
+static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
70
{
60
{
71
/*
61
- float_status discard = { };
72
* VFNMA : fd = muladd(-fd, fn, fm)
62
+ float_status discard = env->fp_status;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
63
FloatRelation r;
74
64
75
neon_load_reg64(vn, a->vn);
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
76
neon_load_reg64(vm, a->vm);
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
77
- if (a->o2) {
67
index XXXXXXX..XXXXXXX 100644
78
+ if (neg_n) {
68
--- a/target/sparc/translate.c
79
/* VFNMS, VFMS */
69
+++ b/target/sparc/translate.c
80
gen_helper_vfp_negd(vn, vn);
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
81
}
71
82
neon_load_reg64(vd, a->vd);
72
src1 = gen_load_fpr_F(dc, a->rs1);
83
- if (a->o1 & 1) {
73
src2 = gen_load_fpr_F(dc, a->rs2);
84
+ if (neg_d) {
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
85
/* VFNMA, VFNMS */
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
86
gen_helper_vfp_negd(vd, vd);
76
return advance_pc(dc);
87
}
88
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
89
return true;
90
}
77
}
91
78
92
+static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a)
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
93
+{
80
94
+ return do_vfm_dp(s, a, false, false);
81
src1 = gen_load_fpr_D(dc, a->rs1);
95
+}
82
src2 = gen_load_fpr_D(dc, a->rs2);
96
+
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
97
+static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a)
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
98
+{
85
return advance_pc(dc);
99
+ return do_vfm_dp(s, a, true, false);
86
}
100
+}
87
101
+
102
+static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a)
103
+{
104
+ return do_vfm_dp(s, a, false, true);
105
+}
106
+
107
+static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a)
108
+{
109
+ return do_vfm_dp(s, a, true, true);
110
+}
111
+
112
static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
113
{
114
uint32_t delta_d = 0;
115
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
116
index XXXXXXX..XXXXXXX 100644
117
--- a/target/arm/vfp.decode
118
+++ b/target/arm/vfp.decode
119
@@ -XXX,XX +XXX,XX @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
120
VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
121
VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
122
123
-VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
124
- vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
125
-VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \
126
- vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1
127
-VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \
128
- vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2
129
-VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
130
- vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
131
+VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s
132
+VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s
133
+VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s
134
+VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s
135
+
136
+VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d
137
+VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d
138
+VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d
139
+VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d
140
141
VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
142
vd=%vd_sp imm=%vmov_imm
143
--
88
--
144
2.20.1
89
2.34.1
145
146
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We had set this for aarch32-only in arm_max_initfn, but
3
Now that float_status has a bunch of fp parameters,
4
failed to set the same bit for aarch64.
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
5
8
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200218190958.745-2-richard.henderson@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
target/arm/cpu64.c | 1 +
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
12
1 file changed, 1 insertion(+)
16
1 file changed, 7 insertions(+), 13 deletions(-)
13
17
14
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu64.c
20
--- a/target/arm/tcg/vec_helper.c
17
+++ b/target/arm/cpu64.c
21
+++ b/target/arm/tcg/vec_helper.c
18
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
19
cpu->isar.id_mmfr3 = u;
23
* no effect on AArch32 instructions.
20
24
*/
21
u = cpu->isar.id_mmfr4;
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
22
+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
26
- *statusp = (float_status){
23
u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
27
- .tininess_before_rounding = float_tininess_before_rounding,
24
cpu->isar.id_mmfr4 = u;
28
- .float_rounding_mode = float_round_to_odd_inf,
29
- .flush_to_zero = true,
30
- .flush_inputs_to_zero = true,
31
- .default_nan_mode = true,
32
- };
33
+
34
+ *statusp = env->vfp.fp_status;
35
+ set_default_nan_mode(true, statusp);
36
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
50
}
51
-
52
return ebf;
53
}
25
54
26
--
55
--
27
2.20.1
56
2.34.1
28
57
29
58
diff view generated by jsdifflib
[PULL 32/33] target/arm: Implement ARMv8.3-CCIDX
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
have a format that uses the full 64 bit width of the register, and
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
adds a new CCSIDR2 register so AArch32 can get at the high 32 bits.
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
4
6
5
QEMU doesn't implement caches, so we just treat these ID registers as
7
Add a field to float_status to specify the default NaN value; fall
6
opaque values that are set to the correct constant values for each
8
back to the old ifdef behaviour if these are not set.
7
CPU. The only thing we need to do is allow 64-bit values in our
8
cssidr[] array and provide the CCSIDR2 accessors.
9
9
10
We don't set the CCIDX field in our 'max' CPU because the CCSIDR
10
The default NaN value is specified by setting a uint8_t to a
11
constant values we use are the same as the ones used by the
11
pattern corresponding to the sign and upper fraction parts of
12
Cortex-A57 and they are in the old 32-bit format. This means
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
that the extra regdef added here is unused currently, but it
13
the pattern.
14
means that whenever in the future we add a CPU that does need
15
the new 64-bit format it will just work when we set the cssidr
16
values and the ID registers for it.
17
14
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20200224182626.29252-1-peter.maydell@linaro.org
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
21
---
18
---
22
target/arm/cpu.h | 17 ++++++++++++++++-
19
include/fpu/softfloat-helpers.h | 11 +++++++
23
target/arm/helper.c | 19 +++++++++++++++++++
20
include/fpu/softfloat-types.h | 10 ++++++
24
2 files changed, 35 insertions(+), 1 deletion(-)
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
25
23
26
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
27
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/cpu.h
26
--- a/include/fpu/softfloat-helpers.h
29
+++ b/target/arm/cpu.h
27
+++ b/include/fpu/softfloat-helpers.h
30
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
31
/* The elements of this array are the CCSIDR values for each cache,
29
status->float_infzeronan_rule = rule;
32
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
33
*/
34
- uint32_t ccsidr[16];
35
+ uint64_t ccsidr[16];
36
uint64_t reset_cbar;
37
uint32_t reset_auxcr;
38
bool reset_hivecs;
39
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
40
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
41
}
30
}
42
31
43
+static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
33
+ float_status *status)
44
+{
34
+{
45
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
35
+ status->default_nan_pattern = dnan_pattern;
46
+}
36
+}
47
+
37
+
48
/*
38
static inline void set_flush_to_zero(bool val, float_status *status)
49
* 64-bit feature tests via id registers.
39
{
50
*/
40
status->flush_to_zero = val;
51
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
52
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
42
return status->float_infzeronan_rule;
53
}
43
}
54
44
55
+static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
56
+{
46
+{
57
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
47
+ return status->default_nan_pattern;
58
+}
48
+}
59
+
49
+
60
/*
50
static inline bool get_flush_to_zero(float_status *status)
61
* Feature tests for "does this exist in either 32-bit or 64-bit?"
51
{
62
*/
52
return status->flush_to_zero;
63
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
64
return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
54
index XXXXXXX..XXXXXXX 100644
65
}
55
--- a/include/fpu/softfloat-types.h
66
56
+++ b/include/fpu/softfloat-types.h
67
+static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
68
+{
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
69
+ return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
59
bool flush_inputs_to_zero;
70
+}
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
71
+
136
+
72
/*
137
+ sign = dnan_pattern >> 7;
73
* Forward to the above feature tests given an ARMCPU pointer.
138
+ /*
74
*/
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
140
+ * and replecate bit [0] down into [55:0]
76
index XXXXXXX..XXXXXXX 100644
141
+ */
77
--- a/target/arm/helper.c
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
78
+++ b/target/arm/helper.c
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
79
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
144
80
REGINFO_SENTINEL
145
*p = (FloatParts64) {
81
};
146
.cls = float_class_qnan,
82
83
+static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
84
+{
85
+ /* Read the high 32 bits of the current CCSIDR */
86
+ return extract64(ccsidr_read(env, ri), 32, 32);
87
+}
88
+
89
+static const ARMCPRegInfo ccsidr2_reginfo[] = {
90
+ { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
91
+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
92
+ .access = PL1_R,
93
+ .accessfn = access_aa64_tid2,
94
+ .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
95
+ REGINFO_SENTINEL
96
+};
97
+
98
static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
99
bool isread)
100
{
101
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
102
define_arm_cp_regs(cpu, predinv_reginfo);
103
}
104
105
+ if (cpu_isar_feature(any_ccidx, cpu)) {
106
+ define_arm_cp_regs(cpu, ccsidr2_reginfo);
107
+ }
108
+
109
#ifndef CONFIG_USER_ONLY
110
/*
111
* Register redirections and aliases must be done last,
112
--
147
--
113
2.20.1
148
2.34.1
114
115
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
We cannot easily create "any" functions for these, because the
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Which means that an aarch32-only cpu will return incorrect results
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
6
when testing the aarch64 registers.
9
---
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
7
13
8
To use these, we must either have context or additionally test
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
9
vs ARM_FEATURE_AARCH64.
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20200224222232.13807-5-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/cpu.h | 11 +++++++++++
17
target/arm/cpu.c | 9 ++++++---
18
target/arm/machine.c | 5 +++--
19
3 files changed, 20 insertions(+), 5 deletions(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
16
--- a/linux-user/arm/nwfpe/fpa11.c
24
+++ b/target/arm/cpu.h
17
+++ b/linux-user/arm/nwfpe/fpa11.c
25
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
26
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
19
* this late date.
20
*/
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
22
+ /*
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
25
+ */
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
27
}
27
}
28
28
29
+static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
29
void SetRoundingMode(const unsigned int opcode)
30
+{
31
+ return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
32
+}
33
+
34
/*
35
* We always set the FP and SIMD FP16 fields to indicate identical
36
* levels of support (assuming SIMD is implemented at all), so
37
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
38
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
39
}
40
41
+static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
42
+{
43
+ /* We always set the AdvSIMD and FP fields identically. */
44
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
45
+}
46
+
47
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
48
{
49
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
50
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
51
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/cpu.c
32
--- a/target/arm/cpu.c
53
+++ b/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
54
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
55
* KVM does not currently allow us to lie to the guest about its
35
* the pseudocode function the arguments are in the order c, a, b.
56
* ID/feature registers, so the guest always sees what the host has.
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
57
*/
37
* and the input NaN if it is signalling
58
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
38
+ * * Default NaN has sign bit clear, msb frac bit set
59
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
39
*/
60
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
40
static void arm_set_default_fp_behaviours(float_status *s)
61
+ : cpu_isar_feature(aa32_vfp, cpu)) {
62
cpu->has_vfp = true;
63
if (!kvm_enabled()) {
64
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
66
* We rely on no XScale CPU having VFP so we can use the same bits in the
67
* TB flags field for VECSTRIDE and XSCALE_CPAR.
68
*/
69
- assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
70
- arm_feature(env, ARM_FEATURE_XSCALE)));
71
+ assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
72
+ !cpu_isar_feature(aa32_vfp_simd, cpu) ||
73
+ !arm_feature(env, ARM_FEATURE_XSCALE));
74
75
if (arm_feature(env, ARM_FEATURE_V7) &&
76
!arm_feature(env, ARM_FEATURE_M) &&
77
diff --git a/target/arm/machine.c b/target/arm/machine.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/machine.c
80
+++ b/target/arm/machine.c
81
@@ -XXX,XX +XXX,XX @@
82
static bool vfp_needed(void *opaque)
83
{
41
{
84
ARMCPU *cpu = opaque;
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
85
- CPUARMState *env = &cpu->env;
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
86
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
87
- return arm_feature(env, ARM_FEATURE_VFP);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
88
+ return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
46
+ set_float_default_nan_pattern(0b01000000, s);
89
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
90
+ : cpu_isar_feature(aa32_vfp_simd, cpu));
91
}
47
}
92
48
93
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
94
--
50
--
95
2.20.1
51
2.34.1
96
97
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/mips/fpu_helper.h
17
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
+ /*
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
30
}
31
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/mips/msa.c
35
+++ b/target/mips/msa.c
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
37
/* Inf * 0 + NaN returns the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
39
&env->active_tc.msa_fp_status);
40
+ /* Default NaN: sign bit clear, frac msb set */
41
+ set_float_default_nan_pattern(0b01000000,
42
+ &env->active_tc.msa_fp_status);
43
}
44
--
45
2.34.1
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
Set the default NaN pattern explicitly for ppc.
2
2
3
All A9 CPUs have a GIC with 5 bits of priority.
4
5
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
11
---
6
---
12
hw/cpu/a9mpcore.c | 4 ++++
7
target/ppc/cpu_init.c | 4 ++++
13
1 file changed, 4 insertions(+)
8
1 file changed, 4 insertions(+)
14
9
15
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/cpu/a9mpcore.c
12
--- a/target/ppc/cpu_init.c
18
+++ b/hw/cpu/a9mpcore.c
13
+++ b/target/ppc/cpu_init.c
19
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
20
#include "hw/qdev-properties.h"
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
21
#include "hw/core/cpu.h"
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
22
17
23
+#define A9_GIC_NUM_PRIORITY_BITS 5
18
+ /* Default NaN: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
24
+
21
+
25
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
26
{
23
ppc_spr_t *spr = &env->spr_cb[i];
27
A9MPPrivState *s = (A9MPPrivState *)opaque;
24
28
@@ -XXX,XX +XXX,XX @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
29
gicdev = DEVICE(&s->gic);
30
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
31
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
32
+ qdev_prop_set_uint32(gicdev, "num-priority-bits",
33
+ A9_GIC_NUM_PRIORITY_BITS);
34
35
/* Make the GIC's TZ support match the CPUs. We assume that
36
* either all the CPUs have TZ, or none do.
37
--
25
--
38
2.20.1
26
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sh4/cpu.c
15
+++ b/target/sh4/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
22
}
23
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for rx.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/rx/cpu.c
13
+++ b/target/rx/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for xtensa.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
6
---
7
target/xtensa/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/xtensa/cpu.c
13
+++ b/target/xtensa/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
15
/* For inf * 0 + NaN, return the input NaN */
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_no_signaling_nans(!dfpu, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
xtensa_use_first_nan(env, !dfpu);
21
}
22
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
12
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/hexagon/cpu.c
16
+++ b/target/hexagon/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
18
19
set_default_nan_mode(1, &env->fp_status);
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
21
+ /* Default NaN value: sign bit set, all frac bits set */
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
23
}
24
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
27
index XXXXXXX..XXXXXXX 100644
28
--- a/fpu/softfloat-specialize.c.inc
29
+++ b/fpu/softfloat-specialize.c.inc
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
31
uint8_t dnan_pattern = status->default_nan_pattern;
32
33
if (dnan_pattern == 0) {
34
-#if defined(TARGET_HEXAGON)
35
- /* Sign bit set, all frac bits set. */
36
- dnan_pattern = 0b11111111;
37
-#else
38
/*
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
42
/* sign bit clear, set frac msb */
43
dnan_pattern = 0b01000000;
44
}
45
-#endif
46
}
47
assert(dnan_pattern != 0);
48
49
--
50
2.34.1
diff view generated by jsdifflib
[PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
From: Guenter Roeck <linux@roeck-us.net>
1
Set the default NaN pattern explicitly for riscv.
2
2
3
USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Linux expects and checks various chipidea registers, which do not exist
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
with the basic ehci emulation. This patch series fixes the problem.
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
6
9
7
Without this patch, USB ports fail to instantiate under Linux.
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
8
9
ci_hdrc ci_hdrc.0: doesn't support host
10
ci_hdrc ci_hdrc.0: no supported roles
11
12
With this patch, USB ports are instantiated, and it is possible
13
to boot from USB drive.
14
15
ci_hdrc ci_hdrc.0: EHCI Host Controller
16
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
17
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
18
usb 1-1: new full-speed USB device number 2 using ci_hdrc
19
usb 1-1: not running at top speed; connect to a high speed hub
20
usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpacket 512, setting to 64
21
usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 512, setting to 64
22
usb-storage 1-1:1.0: USB Mass Storage device detected
23
scsi host0: usb-storage 1-1:1.0
24
25
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
26
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
27
Message-id: 20200215122354.13706-2-linux@roeck-us.net
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
30
hw/arm/xilinx_zynq.c | 5 +++--
31
1 file changed, 3 insertions(+), 2 deletions(-)
32
33
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
34
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/xilinx_zynq.c
12
--- a/target/riscv/cpu.c
36
+++ b/hw/arm/xilinx_zynq.c
13
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
38
#include "hw/loader.h"
15
cs->exception_index = RISCV_EXCP_NONE;
39
#include "hw/misc/zynq-xadc.h"
16
env->load_res = -1;
40
#include "hw/ssi/ssi.h"
17
set_default_nan_mode(1, &env->fp_status);
41
+#include "hw/usb/chipidea.h"
18
+ /* Default NaN value: sign bit clear, frac msb set */
42
#include "qemu/error-report.h"
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
43
#include "hw/sd/sdhci.h"
20
env->vill = true;
44
#include "hw/char/cadence_uart.h"
21
45
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
22
#ifndef CONFIG_USER_ONLY
46
zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
47
zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
48
49
- sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
50
- sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
51
+ sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
52
+ sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
53
54
cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
55
cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
56
--
23
--
57
2.20.1
24
2.34.1
58
59
diff view generated by jsdifflib
[PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
We missed an instance of using FIELD_EX32 on a 64-bit ID
1
Set the default NaN pattern explicitly for tricore.
2
register, in isar_feature_aa64_pmu_8_4(). Fix it.
3
2
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200224172846.13053-2-peter.maydell@linaro.org
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
8
---
6
---
9
target/arm/cpu.h | 4 ++--
7
target/tricore/helper.c | 2 ++
10
1 file changed, 2 insertions(+), 2 deletions(-)
8
1 file changed, 2 insertions(+)
11
9
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
13
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.h
12
--- a/target/tricore/helper.c
15
+++ b/target/arm/cpu.h
13
+++ b/target/tricore/helper.c
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
17
15
set_flush_to_zero(1, &env->fp_status);
18
static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
19
{
17
set_default_nan_mode(1, &env->fp_status);
20
- return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
21
- FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
22
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
23
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
24
}
20
}
25
21
26
/*
22
uint32_t psw_read(CPUTriCoreState *env)
27
--
23
--
28
2.20.1
24
2.34.1
29
30
diff view generated by jsdifflib
[PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
From: Gavin Shan <gshan@redhat.com>
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
2
4
3
This uses TYPE_PL011 when creating the serial port so that the code
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
looks cleaner.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
5
11
6
Signed-off-by: Gavin Shan <gshan@redhat.com>
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20200224222223.4128-1-gshan@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/sbsa-ref.c | 3 ++-
13
hw/arm/virt.c | 3 ++-
14
hw/arm/xlnx-versal.c | 3 ++-
15
3 files changed, 6 insertions(+), 3 deletions(-)
16
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
14
--- a/fpu/softfloat-specialize.c.inc
20
+++ b/hw/arm/sbsa-ref.c
15
+++ b/fpu/softfloat-specialize.c.inc
21
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
22
#include "hw/pci-host/gpex.h"
17
uint64_t frac;
23
#include "hw/qdev-properties.h"
18
uint8_t dnan_pattern = status->default_nan_pattern;
24
#include "hw/usb.h"
19
25
+#include "hw/char/pl011.h"
20
- if (dnan_pattern == 0) {
26
#include "net/net.h"
21
- /*
27
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
28
#define RAMLIMIT_GB 8192
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
29
@@ -XXX,XX +XXX,XX @@ static void create_uart(const SBSAMachineState *sms, int uart,
24
- * do not have floating-point.
30
{
25
- */
31
hwaddr base = sbsa_ref_memmap[uart].base;
26
- if (snan_bit_is_one(status)) {
32
int irq = sbsa_ref_irqmap[uart];
27
- /* sign bit clear, set all frac bits other than msb */
33
- DeviceState *dev = qdev_create(NULL, "pl011");
28
- dnan_pattern = 0b00111111;
34
+ DeviceState *dev = qdev_create(NULL, TYPE_PL011);
29
- } else {
35
SysBusDevice *s = SYS_BUS_DEVICE(dev);
30
- /* sign bit clear, set frac msb */
36
31
- dnan_pattern = 0b01000000;
37
qdev_prop_set_chr(dev, "chardev", chr);
32
- }
38
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
33
- }
39
index XXXXXXX..XXXXXXX 100644
34
assert(dnan_pattern != 0);
40
--- a/hw/arm/virt.c
35
41
+++ b/hw/arm/virt.c
36
sign = dnan_pattern >> 7;
42
@@ -XXX,XX +XXX,XX @@
43
#include "hw/mem/nvdimm.h"
44
#include "hw/acpi/generic_event_device.h"
45
#include "hw/virtio/virtio-iommu.h"
46
+#include "hw/char/pl011.h"
47
48
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
49
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
50
@@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, int uart,
51
int irq = vms->irqmap[uart];
52
const char compat[] = "arm,pl011\0arm,primecell";
53
const char clocknames[] = "uartclk\0apb_pclk";
54
- DeviceState *dev = qdev_create(NULL, "pl011");
55
+ DeviceState *dev = qdev_create(NULL, TYPE_PL011);
56
SysBusDevice *s = SYS_BUS_DEVICE(dev);
57
58
qdev_prop_set_chr(dev, "chardev", chr);
59
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/xlnx-versal.c
62
+++ b/hw/arm/xlnx-versal.c
63
@@ -XXX,XX +XXX,XX @@
64
#include "hw/misc/unimp.h"
65
#include "hw/intc/arm_gicv3_common.h"
66
#include "hw/arm/xlnx-versal.h"
67
+#include "hw/char/pl011.h"
68
69
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
70
#define GEM_REVISION 0x40070106
71
@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
72
DeviceState *dev;
73
MemoryRegion *mr;
74
75
- dev = qdev_create(NULL, "pl011");
76
+ dev = qdev_create(NULL, TYPE_PL011);
77
s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
78
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
79
object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
80
--
37
--
81
2.20.1
38
2.34.1
82
83
diff view generated by jsdifflib
[PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Sort this check to the start of a trans_* function.
3
Inline pickNaNMulAdd into its only caller. This makes
4
Merge this with any existing test for fpdp_v2.
4
one assert redundant with the immediately preceding IF.
5
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200224222232.13807-8-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-vfp.inc.c | 24 ++++++++----------------
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
12
1 file changed, 8 insertions(+), 16 deletions(-)
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
13
15
14
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-vfp.inc.c
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-vfp.inc.c
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
20
* all ID registers to privileged access only.
21
*/
22
- if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
23
+ if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
24
return false;
25
}
26
ignore_vfp_enabled = true;
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
28
case ARM_VFP_FPINST:
29
case ARM_VFP_FPINST2:
30
/* Not present in VFPv3 */
31
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
32
+ if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
33
return false;
34
}
35
break;
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
37
38
vd = a->vd;
39
40
- if (!dc_isar_feature(aa32_fpshvec, s) &&
41
- (veclen != 0 || s->vec_stride != 0)) {
42
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
43
return false;
44
}
21
}
45
22
46
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
23
if (s->default_nan_mode) {
47
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
24
+ /*
48
+ (veclen != 0 || s->vec_stride != 0)) {
25
+ * We guarantee not to require the target to tell us how to
49
return false;
26
+ * pick a NaN if we're always returning the default NaN.
27
+ * But if we're not in default-NaN mode then the target must
28
+ * specify.
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
50
}
67
}
51
68
52
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
69
if (which == 3) {
53
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
vd = a->vd;
71
index XXXXXXX..XXXXXXX 100644
55
72
--- a/fpu/softfloat-specialize.c.inc
56
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
73
+++ b/fpu/softfloat-specialize.c.inc
57
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
58
return false;
59
}
75
}
60
76
}
61
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
77
62
return false;
78
-/*----------------------------------------------------------------------------
63
}
79
-| Select which NaN to propagate for a three-input operation.
64
80
-| For the moment we assume that no CPU needs the 'larger significand'
65
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
81
-| information.
66
- return false;
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
86
-{
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
67
- }
114
- }
68
-
115
-
69
if (!vfp_access_check(s)) {
116
- assert(rule != float_3nan_prop_none);
70
return true;
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
71
}
118
- /* We have at least one SNaN input and should prefer it */
72
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
119
- do {
73
TCGv_ptr fpst;
120
- which = rule & R_3NAN_1ST_MASK;
74
int frac_bits;
121
- rule >>= R_3NAN_1ST_LENGTH;
75
122
- } while (!is_snan(cls[which]));
76
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
123
- } else {
77
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
124
- do {
78
return false;
125
- which = rule & R_3NAN_1ST_MASK;
79
}
126
- rule >>= R_3NAN_1ST_LENGTH;
80
127
- } while (!is_nan(cls[which]));
81
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
82
TCGv_ptr fpst;
83
int frac_bits;
84
85
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
86
- return false;
87
- }
128
- }
129
- return which;
130
-}
88
-
131
-
89
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
132
/*----------------------------------------------------------------------------
90
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
91
return false;
134
| NaN; otherwise returns 0.
92
}
93
94
--
135
--
95
2.20.1
136
2.34.1
96
137
97
138
diff view generated by jsdifflib
[PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We now have proper ISA checks within each trans_* function.
3
Remove "3" as a special case for which and simply
4
branch to return the desired value.
4
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200224222232.13807-11-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/translate.c | 4 ----
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
11
1 file changed, 4 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
12
13
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
--- a/fpu/softfloat-parts.c.inc
16
+++ b/target/arm/translate.c
17
+++ b/fpu/softfloat-parts.c.inc
17
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
18
*/
19
* But if we're not in default-NaN mode then the target must
19
static int disas_vfp_insn(DisasContext *s, uint32_t insn)
20
* specify.
20
{
21
*/
21
- if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
22
- which = 3;
22
- return 1;
23
+ goto default_nan;
24
} else if (infzero) {
25
/*
26
* Inf * 0 + NaN -- some implementations return the
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
28
*/
29
switch (s->float_infzeronan_rule) {
30
case float_infzeronan_dnan_never:
31
- which = 2;
32
break;
33
case float_infzeronan_dnan_always:
34
- which = 3;
35
- break;
36
+ goto default_nan;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
51
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
23
- }
57
- }
24
-
58
-
25
/*
59
switch (which) {
26
* If the decodetree decoder handles this insn it will always
60
case 0:
27
* emit code to either execute the insn or generate an appropriate
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
70
}
71
72
/*
28
--
73
--
29
2.20.1
74
2.34.1
30
75
31
76
diff view generated by jsdifflib
[PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use this in the places that were checking ARM_FEATURE_VFP, and
3
Assign the pointer return value to 'a' directly,
4
are obviously testing for the existance of the register set
4
rather than going through an intermediary index.
5
as opposed to testing for some particular instruction extension.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20200224222232.13807-2-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/cpu.h | 9 +++++++++
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
13
hw/intc/armv7m_nvic.c | 20 ++++++++++----------
12
1 file changed, 10 insertions(+), 22 deletions(-)
14
linux-user/arm/signal.c | 4 ++--
15
target/arm/arch_dump.c | 11 ++++++-----
16
target/arm/cpu.c | 4 ++--
17
target/arm/helper.c | 4 ++--
18
target/arm/m_helper.c | 11 ++++++-----
19
7 files changed, 37 insertions(+), 26 deletions(-)
20
13
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
16
--- a/fpu/softfloat-parts.c.inc
24
+++ b/target/arm/cpu.h
17
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
19
FloatPartsN *c, float_status *s,
27
}
20
int ab_mask, int abc_mask)
28
29
+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
30
+{
31
+ /*
32
+ * Return true if either VFP or SIMD is implemented.
33
+ * In this case, a minimum of VFP w/ D0-D15.
34
+ */
35
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
36
+}
37
+
38
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
39
{
21
{
40
/* Return true if D16-D31 are implemented */
22
- int which;
41
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
23
bool infzero = (ab_mask == float_cmask_infzero);
42
index XXXXXXX..XXXXXXX 100644
24
bool have_snan = (abc_mask & float_cmask_snan);
43
--- a/hw/intc/armv7m_nvic.c
25
+ FloatPartsN *ret;
44
+++ b/hw/intc/armv7m_nvic.c
26
45
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
27
if (unlikely(have_snan)) {
46
case 0xd84: /* CSSELR */
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
47
return cpu->env.v7m.csselr[attrs.secure];
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
48
case 0xd88: /* CPACR */
30
default:
49
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
31
g_assert_not_reached();
50
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
51
return 0;
52
}
32
}
53
return cpu->env.v7m.cpacr[attrs.secure];
33
- which = 2;
54
case 0xd8c: /* NSACR */
34
+ ret = c;
55
- if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
56
+ if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {
57
return 0;
58
}
59
return cpu->env.v7m.nsacr;
60
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
61
}
62
return cpu->env.v7m.sfar;
63
case 0xf34: /* FPCCR */
64
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
65
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
66
return 0;
67
}
68
if (attrs.secure) {
69
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
70
return value;
71
}
72
case 0xf38: /* FPCAR */
73
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
74
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
75
return 0;
76
}
77
return cpu->env.v7m.fpcar[attrs.secure];
78
case 0xf3c: /* FPDSCR */
79
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
80
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
81
return 0;
82
}
83
return cpu->env.v7m.fpdscr[attrs.secure];
84
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
85
}
86
break;
87
case 0xd88: /* CPACR */
88
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
89
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
90
/* We implement only the Floating Point extension's CP10/CP11 */
91
cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
92
}
93
break;
94
case 0xd8c: /* NSACR */
95
- if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
96
+ if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {
97
/* We implement only the Floating Point extension's CP10/CP11 */
98
cpu->env.v7m.nsacr = value & (3 << 10);
99
}
100
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
101
break;
102
}
103
case 0xf34: /* FPCCR */
104
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
105
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
106
/* Not all bits here are banked. */
107
uint32_t fpccr_s;
108
109
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
110
}
111
break;
112
case 0xf38: /* FPCAR */
113
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
114
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
115
value &= ~7;
116
cpu->env.v7m.fpcar[attrs.secure] = value;
117
}
118
break;
119
case 0xf3c: /* FPDSCR */
120
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
121
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
122
value &= 0x07c00000;
123
cpu->env.v7m.fpdscr[attrs.secure] = value;
124
}
125
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/linux-user/arm/signal.c
128
+++ b/linux-user/arm/signal.c
129
@@ -XXX,XX +XXX,XX @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
130
setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);
131
/* Save coprocessor signal frame. */
132
regspace = uc->tuc_regspace;
133
- if (arm_feature(env, ARM_FEATURE_VFP)) {
134
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
135
regspace = setup_sigframe_v2_vfp(regspace, env);
136
}
137
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
138
@@ -XXX,XX +XXX,XX @@ static int do_sigframe_return_v2(CPUARMState *env,
139
140
/* Restore coprocessor signal frame */
141
regspace = uc->tuc_regspace;
142
- if (arm_feature(env, ARM_FEATURE_VFP)) {
143
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
144
regspace = restore_sigframe_v2_vfp(env, regspace);
145
if (!regspace) {
146
return 1;
147
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
148
index XXXXXXX..XXXXXXX 100644
149
--- a/target/arm/arch_dump.c
150
+++ b/target/arm/arch_dump.c
151
@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
152
int cpuid, void *opaque)
153
{
154
struct arm_note note;
155
- CPUARMState *env = &ARM_CPU(cs)->env;
156
+ ARMCPU *cpu = ARM_CPU(cs);
157
+ CPUARMState *env = &cpu->env;
158
DumpState *s = opaque;
159
- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);
160
+ int ret, i;
161
+ bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);
162
163
arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
164
165
@@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info,
166
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
167
{
168
ARMCPU *cpu = ARM_CPU(first_cpu);
169
- CPUARMState *env = &cpu->env;
170
size_t note_size;
171
172
if (class == ELFCLASS64) {
173
@@ -XXX,XX +XXX,XX @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
174
note_size += AARCH64_PRFPREG_NOTE_SIZE;
175
#ifdef TARGET_AARCH64
176
if (cpu_isar_feature(aa64_sve, cpu)) {
177
- note_size += AARCH64_SVE_NOTE_SIZE(env);
178
+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
179
}
180
#endif
181
} else {
35
} else {
182
note_size = ARM_PRSTATUS_NOTE_SIZE;
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
183
- if (arm_feature(env, ARM_FEATURE_VFP)) {
37
+ FloatPartsN *val[3] = { a, b, c };
184
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
185
note_size += ARM_VFP_NOTE_SIZE;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
186
}
56
}
187
}
57
}
188
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
58
189
index XXXXXXX..XXXXXXX 100644
59
- switch (which) {
190
--- a/target/arm/cpu.c
60
- case 0:
191
+++ b/target/arm/cpu.c
61
- break;
192
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
62
- case 1:
193
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
63
- a = b;
194
}
64
- break;
195
65
- case 2:
196
- if (arm_feature(env, ARM_FEATURE_VFP)) {
66
- a = c;
197
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
67
- break;
198
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
68
- default:
199
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
69
- g_assert_not_reached();
200
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
70
+ if (is_snan(ret->cls)) {
201
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
71
+ parts_silence_nan(ret, s);
202
int numvfpregs = 0;
203
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
204
numvfpregs = 32;
205
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
206
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
207
numvfpregs = 16;
208
}
209
for (i = 0; i < numvfpregs; i++) {
210
diff --git a/target/arm/helper.c b/target/arm/helper.c
211
index XXXXXXX..XXXXXXX 100644
212
--- a/target/arm/helper.c
213
+++ b/target/arm/helper.c
214
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
215
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
216
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
217
*/
218
- if (arm_feature(env, ARM_FEATURE_VFP)) {
219
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
220
/* VFP coprocessor: cp10 & cp11 [23:20] */
221
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
222
223
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
224
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
225
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
226
35, "arm-vfp3.xml", 0);
227
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
228
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
229
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
230
19, "arm-vfp.xml", 0);
231
}
72
}
232
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
73
- if (is_snan(a->cls)) {
233
index XXXXXXX..XXXXXXX 100644
74
- parts_silence_nan(a, s);
234
--- a/target/arm/m_helper.c
75
- }
235
+++ b/target/arm/m_helper.c
76
- return a;
236
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
77
+ return ret;
237
*/
78
238
uint32_t sig = 0xfefa125a;
79
default_nan:
239
80
parts_default_nan(a, s);
240
- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
241
+ if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
242
+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
243
sig |= 1;
244
}
245
return sig;
246
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
247
248
if (dotailchain) {
249
/* Sanitize LR FType and PREFIX bits */
250
- if (!arm_feature(env, ARM_FEATURE_VFP)) {
251
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
252
lr |= R_V7M_EXCRET_FTYPE_MASK;
253
}
254
lr = deposit32(lr, 24, 8, 0xff);
255
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
256
257
ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
258
259
- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {
260
+ if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
261
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
262
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
263
"if FPU not present\n",
264
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
265
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
266
* RES0 if the FPU is not present, and is stored in the S bank
267
*/
268
- if (arm_feature(env, ARM_FEATURE_VFP) &&
269
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&
270
extract32(env->v7m.nsacr, 10, 1)) {
271
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
272
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
273
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
274
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
275
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
276
}
277
- if (arm_feature(env, ARM_FEATURE_VFP)) {
278
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
279
/*
280
* SFPA is RAZ/WI from NS or if no FPU.
281
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
282
--
81
--
283
2.20.1
82
2.34.1
284
83
285
84
diff view generated by jsdifflib
[PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Those vfp instructions without extra opcode fields can
3
While all indices into val[] should be in [0-2], the mask
4
share a common @format for brevity.
4
applied is two bits. To help static analysis see there is
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
5
7
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200224222232.13807-16-richard.henderson@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/vfp.decode | 134 ++++++++++++++++--------------------------
13
fpu/softfloat-parts.c.inc | 2 +-
12
1 file changed, 52 insertions(+), 82 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
15
14
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/vfp.decode
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/vfp.decode
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
21
}
20
%vmov_imm 16:4 0:4
22
ret = c;
21
23
} else {
22
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
24
- FloatPartsN *val[3] = { a, b, c };
23
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
24
+
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
25
+@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp
27
26
+@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp
28
assert(rule != float_3nan_prop_none);
27
+@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp
28
+@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp
29
+
30
# VMOV scalar to general-purpose register; note that this does
31
# include some Neon cases.
32
VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
33
@@ -XXX,XX +XXX,XX @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
34
vn=%vn_dp
35
36
VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
37
-VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
38
- vn=%vn_sp
39
+VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
40
41
-VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
42
- vm=%vm_sp
43
-VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
44
- vm=%vm_dp
45
+VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
46
+VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
47
48
# Note that the half-precision variants of VLDR and VSTR are
49
# not part of this decodetree at all because they have bits [9:8] == 0b01
50
-VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
51
- vd=%vd_sp
52
-VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
53
- vd=%vd_dp
54
+VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
55
+VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
56
57
# We split the load/store multiple up into two patterns to avoid
58
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
59
@@ -XXX,XX +XXX,XX @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
60
vd=%vd_dp p=1 u=0 w=1
61
62
# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
63
-VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \
64
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
65
-VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \
66
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
67
+VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s
68
+VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d
69
70
-VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \
71
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
72
-VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \
73
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
74
+VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s
75
+VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d
76
77
-VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \
78
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
79
-VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \
80
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
81
+VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s
82
+VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d
83
84
-VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \
85
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
86
-VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \
87
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
88
+VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s
89
+VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d
90
91
-VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \
92
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
93
-VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \
94
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
95
+VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s
96
+VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d
97
98
-VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \
99
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
100
-VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \
101
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
102
+VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s
103
+VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d
104
105
-VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \
106
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
107
-VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \
108
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
109
+VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s
110
+VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d
111
112
-VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \
113
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
114
-VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \
115
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
116
+VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s
117
+VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
118
119
-VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \
120
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
121
-VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \
122
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
123
+VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
124
+VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
125
126
VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
127
vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
128
@@ -XXX,XX +XXX,XX @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
129
VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
130
vd=%vd_dp imm=%vmov_imm
131
132
-VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \
133
- vd=%vd_sp vm=%vm_sp
134
-VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \
135
- vd=%vd_dp vm=%vm_dp
136
+VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
137
+VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
138
139
-VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \
140
- vd=%vd_sp vm=%vm_sp
141
-VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \
142
- vd=%vd_dp vm=%vm_dp
143
+VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
144
+VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
145
146
-VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \
147
- vd=%vd_sp vm=%vm_sp
148
-VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \
149
- vd=%vd_dp vm=%vm_dp
150
+VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
151
+VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
152
153
-VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \
154
- vd=%vd_sp vm=%vm_sp
155
-VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \
156
- vd=%vd_dp vm=%vm_dp
157
+VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
158
+VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd
159
160
VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
161
vd=%vd_sp vm=%vm_sp
162
@@ -XXX,XX +XXX,XX @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
163
VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
164
vd=%vd_dp vm=%vm_sp
165
166
-# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit
167
+# VCVTB and VCVTT to f16: Vd format is always vd_sp;
168
+# Vm format depends on size bit
169
VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
170
vd=%vd_sp vm=%vm_sp
171
VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
172
vd=%vd_sp vm=%vm_dp
173
174
-VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \
175
- vd=%vd_sp vm=%vm_sp
176
-VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \
177
- vd=%vd_dp vm=%vm_dp
178
+VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss
179
+VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd
180
181
-VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \
182
- vd=%vd_sp vm=%vm_sp
183
-VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \
184
- vd=%vd_dp vm=%vm_dp
185
+VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss
186
+VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd
187
188
-VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
189
- vd=%vd_sp vm=%vm_sp
190
-VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
191
- vd=%vd_dp vm=%vm_dp
192
+VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss
193
+VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd
194
195
-# VCVT between single and double: Vm precision depends on size; Vd is its reverse
196
-VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
197
- vd=%vd_dp vm=%vm_sp
198
-VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
199
- vd=%vd_sp vm=%vm_dp
200
+# VCVT between single and double:
201
+# Vm precision depends on size; Vd is its reverse
202
+VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds
203
+VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd
204
205
# VCVT from integer to floating point: Vm always single; Vd depends on size
206
VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
207
@@ -XXX,XX +XXX,XX @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
208
vd=%vd_dp vm=%vm_sp
209
210
# VJCVT is always dp to sp
211
-VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \
212
- vd=%vd_sp vm=%vm_dp
213
+VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
214
215
# VCVT between floating-point and fixed-point. The immediate value
216
# is in the same format as a Vm single-precision register number.
217
--
29
--
218
2.20.1
30
2.34.1
219
31
220
32
diff view generated by jsdifflib
[PULL 22/33] target/arm: Split VMINMAXNM decode
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Passing the raw op field from the manual is less instructive
3
This function is part of the public interface and
4
than it might be. Do the full decode and use the existing
4
is not "specialized" to any target in any way.
5
helpers to perform the expansion.
6
5
7
Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
11
Message-id: 20200224222232.13807-18-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
target/arm/translate-vfp.inc.c | 109 +++++++++++----------------------
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
15
target/arm/vfp-uncond.decode | 12 ++--
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
16
2 files changed, 44 insertions(+), 77 deletions(-)
13
2 files changed, 52 insertions(+), 52 deletions(-)
17
14
18
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-vfp.inc.c
17
--- a/fpu/softfloat.c
21
+++ b/target/arm/translate-vfp.inc.c
18
+++ b/fpu/softfloat.c
22
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
23
return true;
20
*zExpPtr = 1 - shiftCount;
24
}
21
}
25
22
26
-static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
23
+/*----------------------------------------------------------------------------
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+*----------------------------------------------------------------------------*/
28
+
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
30
+{
31
+ bool aIsLargerSignificand;
32
+ FloatClass a_cls, b_cls;
33
+
34
+ /* This is not complete, but is good enough for pickNaN. */
35
+ a_cls = (!floatx80_is_any_nan(a)
36
+ ? float_class_normal
37
+ : floatx80_is_signaling_nan(a, status)
38
+ ? float_class_snan
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
45
+
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
47
+ float_raise(float_flag_invalid, status);
48
+ }
49
+
50
+ if (status->default_nan_mode) {
51
+ return floatx80_default_nan(status);
52
+ }
53
+
54
+ if (a.low < b.low) {
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
61
+
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
63
+ if (is_snan(b_cls)) {
64
+ return floatx80_silence_nan(b, status);
65
+ }
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
72
+ }
73
+}
74
+
75
/*----------------------------------------------------------------------------
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
79
index XXXXXXX..XXXXXXX 100644
80
--- a/fpu/softfloat-specialize.c.inc
81
+++ b/fpu/softfloat-specialize.c.inc
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
83
return a;
84
}
85
86
-/*----------------------------------------------------------------------------
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
27
-{
93
-{
28
- uint32_t rd, rn, rm;
94
- bool aIsLargerSignificand;
29
- bool dp = a->dp;
95
- FloatClass a_cls, b_cls;
30
- bool vmin = a->op;
31
- TCGv_ptr fpst;
32
-
96
-
33
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
97
- /* This is not complete, but is good enough for pickNaN. */
34
- return false;
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
35
- }
111
- }
36
-
112
-
37
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
113
- if (status->default_nan_mode) {
38
- return false;
114
- return floatx80_default_nan(status);
39
- }
115
- }
40
-
116
-
41
- /* UNDEF accesses to D16-D31 if they don't exist */
117
- if (a.low < b.low) {
42
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
118
- aIsLargerSignificand = 0;
43
- ((a->vm | a->vn | a->vd) & 0x10)) {
119
- } else if (b.low < a.low) {
44
- return false;
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
45
- }
123
- }
46
-
124
-
47
- rd = a->vd;
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
48
- rn = a->vn;
126
- if (is_snan(b_cls)) {
49
- rm = a->vm;
127
- return floatx80_silence_nan(b, status);
50
-
128
- }
51
- if (!vfp_access_check(s)) {
129
- return b;
52
- return true;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
53
- }
135
- }
54
-
55
- fpst = get_fpstatus_ptr(0);
56
-
57
- if (dp) {
58
- TCGv_i64 frn, frm, dest;
59
-
60
- frn = tcg_temp_new_i64();
61
- frm = tcg_temp_new_i64();
62
- dest = tcg_temp_new_i64();
63
-
64
- neon_load_reg64(frn, rn);
65
- neon_load_reg64(frm, rm);
66
- if (vmin) {
67
- gen_helper_vfp_minnumd(dest, frn, frm, fpst);
68
- } else {
69
- gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
70
- }
71
- neon_store_reg64(dest, rd);
72
- tcg_temp_free_i64(frn);
73
- tcg_temp_free_i64(frm);
74
- tcg_temp_free_i64(dest);
75
- } else {
76
- TCGv_i32 frn, frm, dest;
77
-
78
- frn = tcg_temp_new_i32();
79
- frm = tcg_temp_new_i32();
80
- dest = tcg_temp_new_i32();
81
-
82
- neon_load_reg32(frn, rn);
83
- neon_load_reg32(frm, rm);
84
- if (vmin) {
85
- gen_helper_vfp_minnums(dest, frn, frm, fpst);
86
- } else {
87
- gen_helper_vfp_maxnums(dest, frn, frm, fpst);
88
- }
89
- neon_store_reg32(dest, rd);
90
- tcg_temp_free_i32(frn);
91
- tcg_temp_free_i32(frm);
92
- tcg_temp_free_i32(dest);
93
- }
94
-
95
- tcg_temp_free_ptr(fpst);
96
- return true;
97
-}
136
-}
98
-
137
-
99
/*
138
/*----------------------------------------------------------------------------
100
* Table for converting the most common AArch32 encoding of
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
101
* rounding mode to arm_fprounding order (which matches the
140
| NaN; otherwise returns 0.
102
@@ -XXX,XX +XXX,XX @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
103
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
104
}
105
106
+static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
107
+{
108
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
109
+ return false;
110
+ }
111
+ return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
112
+ a->vd, a->vn, a->vm, false);
113
+}
114
+
115
+static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
116
+{
117
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
118
+ return false;
119
+ }
120
+ return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
121
+ a->vd, a->vn, a->vm, false);
122
+}
123
+
124
+static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
125
+{
126
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
127
+ return false;
128
+ }
129
+ return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
130
+ a->vd, a->vn, a->vm, false);
131
+}
132
+
133
+static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
134
+{
135
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
136
+ return false;
137
+ }
138
+ return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
139
+ a->vd, a->vn, a->vm, false);
140
+}
141
+
142
static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
143
{
144
/*
145
diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
146
index XXXXXXX..XXXXXXX 100644
147
--- a/target/arm/vfp-uncond.decode
148
+++ b/target/arm/vfp-uncond.decode
149
@@ -XXX,XX +XXX,XX @@
150
%vd_dp 22:1 12:4
151
%vd_sp 12:4 22:1
152
153
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
154
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
155
+
156
VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
157
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
158
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
159
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
160
161
-VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
162
- vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
163
-VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
164
- vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
165
+VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
166
+VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s
167
+
168
+VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
169
+VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d
170
171
VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
172
vm=%vm_sp vd=%vd_sp dp=0
173
--
141
--
174
2.20.1
142
2.34.1
175
176
diff view generated by jsdifflib
[PULL 13/33] target/arm: Add missing checks for fpsp_v2
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We will eventually remove the early ARM_FEATURE_VFP test,
3
Unpacking and repacking the parts may be slightly more work
4
so add a proper test for each trans_* that does not already
4
than we did before, but we get to reuse more code. For a
5
have another ISA test.
5
code path handling exceptional values, this is an improvement.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200224222232.13807-9-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++----
12
fpu/softfloat.c | 43 +++++--------------------------------------
13
1 file changed, 69 insertions(+), 9 deletions(-)
13
1 file changed, 5 insertions(+), 38 deletions(-)
14
14
15
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-vfp.inc.c
17
--- a/fpu/softfloat.c
18
+++ b/target/arm/translate-vfp.inc.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
int pass;
20
21
uint32_t offset;
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
22
22
{
23
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
23
- bool aIsLargerSignificand;
24
+ if (a->size == 2
24
- FloatClass a_cls, b_cls;
25
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
25
+ FloatParts128 pa, pb, *pr;
26
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
26
27
+ return false;
27
- /* This is not complete, but is good enough for pickNaN. */
28
+ }
28
- a_cls = (!floatx80_is_any_nan(a)
29
+
29
- ? float_class_normal
30
/* UNDEF accesses to D16-D31 if they don't exist */
30
- : floatx80_is_signaling_nan(a, status)
31
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
31
- ? float_class_snan
32
return false;
32
- : float_class_qnan);
33
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
33
- b_cls = (!floatx80_is_any_nan(b)
34
pass = extract32(offset, 2, 1);
34
- ? float_class_normal
35
offset = extract32(offset, 0, 2) * 8;
35
- : floatx80_is_signaling_nan(b, status)
36
36
- ? float_class_snan
37
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
37
- : float_class_qnan);
38
- return false;
38
-
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
40
- float_raise(float_flag_invalid, status);
39
- }
41
- }
40
-
42
-
41
if (!vfp_access_check(s)) {
43
- if (status->default_nan_mode) {
42
return true;
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
43
}
47
}
44
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
48
45
int pass;
49
- if (a.low < b.low) {
46
uint32_t offset;
50
- aIsLargerSignificand = 0;
47
51
- } else if (b.low < a.low) {
48
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
52
- aIsLargerSignificand = 1;
49
+ if (a->size == 2
53
- } else {
50
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
51
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
52
+ return false;
53
+ }
54
+
55
/* UNDEF accesses to D16-D31 if they don't exist */
56
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
57
return false;
58
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
59
pass = extract32(offset, 2, 1);
60
offset = extract32(offset, 0, 2) * 8;
61
62
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
63
- return false;
64
- }
55
- }
65
-
56
-
66
if (!vfp_access_check(s)) {
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
67
return true;
58
- if (is_snan(b_cls)) {
68
}
59
- return floatx80_silence_nan(b, status);
69
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
60
- }
70
TCGv_i32 tmp;
61
- return b;
71
bool ignore_vfp_enabled = false;
62
- } else {
72
63
- if (is_snan(a_cls)) {
73
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
64
- return floatx80_silence_nan(a, status);
74
+ return false;
65
- }
75
+ }
66
- return a;
76
+
67
- }
77
if (arm_dc_feature(s, ARM_FEATURE_M)) {
68
+ pr = parts_pick_nan(&pa, &pb, status);
78
/*
69
+ return floatx80_round_pack_canonical(pr, status);
79
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
70
}
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
71
81
{
72
/*----------------------------------------------------------------------------
82
TCGv_i32 tmp;
83
84
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
85
+ return false;
86
+ }
87
+
88
if (!vfp_access_check(s)) {
89
return true;
90
}
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
92
{
93
TCGv_i32 tmp;
94
95
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
96
+ return false;
97
+ }
98
+
99
/*
100
* VMOV between two general-purpose registers and two single precision
101
* floating point registers
102
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
103
104
/*
105
* VMOV between two general-purpose registers and one double precision
106
- * floating point register
107
+ * floating point register. Note that this does not require support
108
+ * for double precision arithmetic.
109
*/
110
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
111
+ return false;
112
+ }
113
114
/* UNDEF accesses to D16-D31 if they don't exist */
115
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
116
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
117
uint32_t offset;
118
TCGv_i32 addr, tmp;
119
120
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
121
+ return false;
122
+ }
123
+
124
if (!vfp_access_check(s)) {
125
return true;
126
}
127
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
128
TCGv_i32 addr;
129
TCGv_i64 tmp;
130
131
+ /* Note that this does not require support for double arithmetic. */
132
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
133
+ return false;
134
+ }
135
+
136
/* UNDEF accesses to D16-D31 if they don't exist */
137
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
138
return false;
139
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
140
TCGv_i32 addr, tmp;
141
int i, n;
142
143
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
144
+ return false;
145
+ }
146
+
147
n = a->imm;
148
149
if (n == 0 || (a->vd + n) > 32) {
150
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
151
TCGv_i64 tmp;
152
int i, n;
153
154
+ /* Note that this does not require support for double arithmetic. */
155
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
156
+ return false;
157
+ }
158
+
159
n = a->imm >> 1;
160
161
if (n == 0 || (a->vd + n) > 32 || n > 16) {
162
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
163
TCGv_i32 f0, f1, fd;
164
TCGv_ptr fpst;
165
166
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
167
+ return false;
168
+ }
169
+
170
if (!dc_isar_feature(aa32_fpshvec, s) &&
171
(veclen != 0 || s->vec_stride != 0)) {
172
return false;
173
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
174
int veclen = s->vec_len;
175
TCGv_i32 f0, fd;
176
177
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
178
+ return false;
179
+ }
180
+
181
if (!dc_isar_feature(aa32_fpshvec, s) &&
182
(veclen != 0 || s->vec_stride != 0)) {
183
return false;
184
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
185
{
186
TCGv_i32 vd, vm;
187
188
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
189
+ return false;
190
+ }
191
+
192
/* Vm/M bits must be zero for the Z variant */
193
if (a->z && a->vm != 0) {
194
return false;
195
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
196
TCGv_i32 vm;
197
TCGv_ptr fpst;
198
199
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
200
+ return false;
201
+ }
202
+
203
if (!vfp_access_check(s)) {
204
return true;
205
}
206
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
207
TCGv_i32 vm;
208
TCGv_ptr fpst;
209
210
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
211
+ return false;
212
+ }
213
+
214
if (!vfp_access_check(s)) {
215
return true;
216
}
217
--
73
--
218
2.20.1
74
2.34.1
219
220
diff view generated by jsdifflib
[PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Have the calls adjacent as an intermediate step toward
3
Inline pickNaN into its only caller. This makes one assert
4
actually merging the decodes.
4
redundant with the immediately preceding IF.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20200224222232.13807-13-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate.c | 83 +++++++++++++++---------------------------
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
12
1 file changed, 29 insertions(+), 54 deletions(-)
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
13
13
2 files changed, 73 insertions(+), 105 deletions(-)
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate.c
18
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
19
tcg_temp_free_i32(tmp);
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
float_status *s)
22
{
23
+ int cmp, which;
24
+
25
if (is_snan(a->cls) || is_snan(b->cls)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
if (s->default_nan_mode) {
30
parts_default_nan(a, s);
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
20
}
116
}
21
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
22
-/*
118
index XXXXXXX..XXXXXXX 100644
23
- * Disassemble a VFP instruction. Returns nonzero if an error occurred
119
--- a/fpu/softfloat-specialize.c.inc
24
- * (ie. an undefined instruction).
120
+++ b/fpu/softfloat-specialize.c.inc
25
- */
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
26
-static int disas_vfp_insn(DisasContext *s, uint32_t insn)
122
}
123
}
124
125
-/*----------------------------------------------------------------------------
126
-| Select which NaN to propagate for a two-input operation.
127
-| IEEE754 doesn't specify all the details of this, so the
128
-| algorithm is target-specific.
129
-| The routine is passed various bits of information about the
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
131
-| Note that signalling NaNs are always squashed to quiet NaNs
132
-| by the caller, by calling floatXX_silence_nan() before
133
-| returning them.
134
-|
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
141
-
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
27
-{
144
-{
28
- /*
145
- /*
29
- * If the decodetree decoder handles this insn it will always
146
- * We guarantee not to require the target to tell us how to
30
- * emit code to either execute the insn or generate an appropriate
147
- * pick a NaN if we're always returning the default NaN.
31
- * exception; so we don't need to ever return non-zero to tell
148
- * But if we're not in default-NaN mode then the target must
32
- * the calling code to emit an UNDEF exception.
149
- * specify via set_float_2nan_prop_rule().
33
- */
150
- */
34
- if (extract32(insn, 28, 4) == 0xf) {
151
- assert(!status->default_nan_mode);
35
- if (disas_vfp_uncond(s, insn)) {
152
-
36
- return 0;
153
- switch (status->float_2nan_prop_rule) {
37
- }
154
- case float_2nan_prop_s_ab:
38
- } else {
155
- if (is_snan(a_cls)) {
39
- if (disas_vfp(s, insn)) {
156
- return 0;
40
- return 0;
157
- } else if (is_snan(b_cls)) {
41
- }
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
42
- }
218
- }
43
- /* If the decodetree decoder didn't handle this insn, it must be UNDEF */
44
- return 1;
45
-}
219
-}
46
-
220
-
47
static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
221
/*----------------------------------------------------------------------------
48
{
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
49
#ifndef CONFIG_USER_ONLY
223
| NaN; otherwise returns 0.
50
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
51
ARCH(5);
52
53
/* Unconditional instructions. */
54
- if (disas_a32_uncond(s, insn)) {
55
+ /* TODO: Perhaps merge these into one decodetree output file. */
56
+ if (disas_a32_uncond(s, insn) ||
57
+ disas_vfp_uncond(s, insn)) {
58
return;
59
}
60
/* fall back to legacy decoder */
61
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
62
}
63
return;
64
}
65
- if ((insn & 0x0f000e10) == 0x0e000a00) {
66
- /* VFP. */
67
- if (disas_vfp_insn(s, insn)) {
68
- goto illegal_op;
69
- }
70
- return;
71
- }
72
if ((insn & 0x0e000f00) == 0x0c000100) {
73
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
74
/* iWMMXt register transfer. */
75
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
76
arm_skip_unless(s, cond);
77
}
78
79
- if (disas_a32(s, insn)) {
80
+ /* TODO: Perhaps merge these into one decodetree output file. */
81
+ if (disas_a32(s, insn) ||
82
+ disas_vfp(s, insn)) {
83
return;
84
}
85
/* fall back to legacy decoder */
86
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
87
case 0xd:
88
case 0xe:
89
if (((insn >> 8) & 0xe) == 10) {
90
- /* VFP. */
91
- if (disas_vfp_insn(s, insn)) {
92
- goto illegal_op;
93
- }
94
- } else if (disas_coproc_insn(s, insn)) {
95
+ /* VFP, but failed disas_vfp. */
96
+ goto illegal_op;
97
+ }
98
+ if (disas_coproc_insn(s, insn)) {
99
/* Coprocessor. */
100
goto illegal_op;
101
}
102
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
103
ARCH(6T2);
104
}
105
106
- if (disas_t32(s, insn)) {
107
+ /*
108
+ * TODO: Perhaps merge these into one decodetree output file.
109
+ * Note disas_vfp is written for a32 with cond field in the
110
+ * top nibble. The t32 encoding requires 0xe in the top nibble.
111
+ */
112
+ if (disas_t32(s, insn) ||
113
+ disas_vfp_uncond(s, insn) ||
114
+ ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
115
return;
116
}
117
/* fall back to legacy decoder */
118
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
119
goto illegal_op; /* op0 = 0b11 : unallocated */
120
}
121
122
- if (disas_vfp_insn(s, insn)) {
123
- if (((insn >> 8) & 0xe) == 10 &&
124
- dc_isar_feature(aa32_fpsp_v2, s)) {
125
- /* FP, and the CPU supports it */
126
- goto illegal_op;
127
- } else {
128
- /* All other insns: NOCP */
129
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
130
- syn_uncategorized(),
131
- default_exception_el(s));
132
- }
133
+ if (((insn >> 8) & 0xe) == 10 &&
134
+ dc_isar_feature(aa32_fpsp_v2, s)) {
135
+ /* FP, and the CPU supports it */
136
+ goto illegal_op;
137
+ } else {
138
+ /* All other insns: NOCP */
139
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
140
+ syn_uncategorized(),
141
+ default_exception_el(s));
142
}
143
break;
144
}
145
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
146
goto illegal_op;
147
}
148
} else if (((insn >> 8) & 0xe) == 10) {
149
- if (disas_vfp_insn(s, insn)) {
150
- goto illegal_op;
151
- }
152
+ /* VFP, but failed disas_vfp. */
153
+ goto illegal_op;
154
} else {
155
if (insn & (1 << 28))
156
goto illegal_op;
157
--
224
--
158
2.20.1
225
2.34.1
159
226
160
227
diff view generated by jsdifflib
[PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use isar feature tests instead of feature bit tests.
3
Remember if there was an SNaN, and use that to simplify
4
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Although none of QEMUs current cpus have VFPv3 without D32,
5
Then, fall through to the corresponding
6
replace the large comment explaining why with one line that
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions.
7
nans, which must be quiet.
8
Mirror the test sequence used in the linux kernel.
9
8
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20200224222232.13807-14-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
linux-user/elfload.c | 23 +++++++++++++----------
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
16
1 file changed, 13 insertions(+), 10 deletions(-)
15
1 file changed, 12 insertions(+), 20 deletions(-)
17
16
18
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/linux-user/elfload.c
19
--- a/fpu/softfloat-parts.c.inc
21
+++ b/linux-user/elfload.c
20
+++ b/fpu/softfloat-parts.c.inc
22
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
23
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
24
/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
23
float_status *s)
25
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
24
{
26
- GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
25
+ bool have_snan = false;
27
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
26
int cmp, which;
28
GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
27
29
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
28
if (is_snan(a->cls) || is_snan(b->cls)) {
30
- GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
31
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
30
+ have_snan = true;
32
- GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
31
}
33
+ GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
32
34
GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
33
if (s->default_nan_mode) {
35
GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
36
- /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
35
37
- * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
36
switch (s->float_2nan_prop_rule) {
38
- * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
37
case float_2nan_prop_s_ab:
39
- * to our VFP_FP16 feature bit.
38
- if (is_snan(a->cls)) {
40
- */
39
- which = 0;
41
- GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32);
40
- } else if (is_snan(b->cls)) {
42
- GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
41
- which = 1;
43
+ GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
42
- } else if (is_qnan(a->cls)) {
44
+
43
- which = 0;
45
+ if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
44
- } else {
46
+ cpu_isar_feature(aa32_fpdp_v3, cpu)) {
45
- which = 1;
47
+ hwcaps |= ARM_HWCAP_ARM_VFPv3;
46
+ if (have_snan) {
48
+ if (cpu_isar_feature(aa32_simd_r32, cpu)) {
47
+ which = is_snan(a->cls) ? 0 : 1;
49
+ hwcaps |= ARM_HWCAP_ARM_VFPD32;
48
+ break;
50
+ } else {
49
}
51
+ hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
50
- break;
51
- case float_2nan_prop_s_ba:
52
- if (is_snan(b->cls)) {
53
- which = 1;
54
- } else if (is_snan(a->cls)) {
55
- which = 0;
56
- } else if (is_qnan(b->cls)) {
57
- which = 1;
58
- } else {
59
- which = 0;
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
52
+ }
70
+ }
53
+ }
71
+ /* fall through */
54
+ GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
72
case float_2nan_prop_ba:
55
73
which = is_nan(b->cls) ? 1 : 0;
56
return hwcaps;
74
break;
57
}
58
--
75
--
59
2.20.1
76
2.34.1
60
61
diff view generated by jsdifflib
[PULL 11/33] target/arm: Perform fpdp_v2 check first
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Shuffle the order of the checks so that we test the ISA
3
Move the fractional comparison to the end of the
4
before we test anything else, such as the register arguments.
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
5
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
8
Message-id: 20200224222232.13807-7-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/translate-vfp.inc.c | 140 +++++++++++++++++----------------
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
12
1 file changed, 71 insertions(+), 69 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
13
16
14
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-vfp.inc.c
19
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-vfp.inc.c
20
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
19
return false;
22
return a;
20
}
23
}
21
24
22
- /* UNDEF accesses to D16-D31 if they don't exist */
25
- cmp = frac_cmp(a, b);
23
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
26
- if (cmp == 0) {
24
- ((a->vm | a->vn | a->vd) & 0x10)) {
27
- cmp = a->sign < b->sign;
25
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
26
return false;
27
}
28
29
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
30
+ /* UNDEF accesses to D16-D31 if they don't exist */
31
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
32
+ ((a->vm | a->vn | a->vd) & 0x10)) {
33
return false;
34
}
35
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
37
return false;
38
}
39
40
- /* UNDEF accesses to D16-D31 if they don't exist */
41
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
42
- ((a->vm | a->vn | a->vd) & 0x10)) {
43
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
44
return false;
45
}
46
47
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
48
+ /* UNDEF accesses to D16-D31 if they don't exist */
49
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
50
+ ((a->vm | a->vn | a->vd) & 0x10)) {
51
return false;
52
}
53
54
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
55
return false;
56
}
57
58
- /* UNDEF accesses to D16-D31 if they don't exist */
59
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
60
- ((a->vm | a->vd) & 0x10)) {
61
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
62
return false;
63
}
64
65
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
66
+ /* UNDEF accesses to D16-D31 if they don't exist */
67
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
68
+ ((a->vm | a->vd) & 0x10)) {
69
return false;
70
}
71
72
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
73
return false;
74
}
75
76
- /* UNDEF accesses to D16-D31 if they don't exist */
77
- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
78
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
79
return false;
80
}
81
82
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
83
+ /* UNDEF accesses to D16-D31 if they don't exist */
84
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
85
return false;
86
}
87
88
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
89
TCGv_i64 f0, f1, fd;
90
TCGv_ptr fpst;
91
92
- /* UNDEF accesses to D16-D31 if they don't exist */
93
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
94
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
95
return false;
96
}
97
98
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
99
+ /* UNDEF accesses to D16-D31 if they don't exist */
100
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
101
return false;
102
}
103
104
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
105
int veclen = s->vec_len;
106
TCGv_i64 f0, fd;
107
108
- /* UNDEF accesses to D16-D31 if they don't exist */
109
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
110
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
111
return false;
112
}
113
114
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
115
+ /* UNDEF accesses to D16-D31 if they don't exist */
116
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
117
return false;
118
}
119
120
@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
121
return false;
122
}
123
124
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
125
+ /* UNDEF accesses to D16-D31 if they don't exist. */
126
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
127
+ ((a->vd | a->vn | a->vm) & 0x10)) {
128
return false;
129
}
130
131
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
132
133
vd = a->vd;
134
135
- /* UNDEF accesses to D16-D31 if they don't exist. */
136
- if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
137
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
138
return false;
139
}
140
141
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
142
+ /* UNDEF accesses to D16-D31 if they don't exist. */
143
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
144
return false;
145
}
146
147
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
148
{
149
TCGv_i64 vd, vm;
150
151
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
152
+ return false;
153
+ }
154
+
155
/* Vm/M bits must be zero for the Z variant */
156
if (a->z && a->vm != 0) {
157
return false;
158
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
159
return false;
160
}
161
162
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
163
- return false;
164
- }
28
- }
165
-
29
-
166
if (!vfp_access_check(s)) {
30
switch (s->float_2nan_prop_rule) {
167
return true;
31
case float_2nan_prop_s_ab:
168
}
32
if (have_snan) {
169
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
170
TCGv_i32 tmp;
34
* return the NaN with the positive sign bit (if any).
171
TCGv_i64 vd;
35
*/
172
36
if (is_snan(a->cls)) {
173
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
37
- if (is_snan(b->cls)) {
174
+ return false;
38
- which = cmp > 0 ? 0 : 1;
175
+ }
39
- } else {
176
+
40
+ if (!is_snan(b->cls)) {
177
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
41
which = is_qnan(b->cls) ? 1 : 0;
178
return false;
42
+ break;
179
}
43
}
180
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
44
} else if (is_qnan(a->cls)) {
181
return false;
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
182
}
46
which = 0;
183
47
- } else {
184
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
48
- which = cmp > 0 ? 0 : 1;
185
- return false;
49
+ break;
186
- }
50
}
187
-
51
} else {
188
if (!vfp_access_check(s)) {
52
which = 1;
189
return true;
53
+ break;
190
}
54
}
191
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
55
+ cmp = frac_cmp(a, b);
192
TCGv_i32 tmp;
56
+ if (cmp == 0) {
193
TCGv_i64 vm;
57
+ cmp = a->sign < b->sign;
194
58
+ }
195
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
59
+ which = cmp > 0 ? 0 : 1;
196
+ return false;
60
break;
197
+ }
61
default:
198
+
62
g_assert_not_reached();
199
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
200
return false;
201
}
202
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
203
return false;
204
}
205
206
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
207
- return false;
208
- }
209
-
210
if (!vfp_access_check(s)) {
211
return true;
212
}
213
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
214
TCGv_ptr fpst;
215
TCGv_i64 tmp;
216
217
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
218
+ return false;
219
+ }
220
+
221
if (!dc_isar_feature(aa32_vrint, s)) {
222
return false;
223
}
224
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
225
return false;
226
}
227
228
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
229
- return false;
230
- }
231
-
232
if (!vfp_access_check(s)) {
233
return true;
234
}
235
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
236
TCGv_i64 tmp;
237
TCGv_i32 tcg_rmode;
238
239
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
240
+ return false;
241
+ }
242
+
243
if (!dc_isar_feature(aa32_vrint, s)) {
244
return false;
245
}
246
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
247
return false;
248
}
249
250
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
251
- return false;
252
- }
253
-
254
if (!vfp_access_check(s)) {
255
return true;
256
}
257
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
258
TCGv_ptr fpst;
259
TCGv_i64 tmp;
260
261
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
262
+ return false;
263
+ }
264
+
265
if (!dc_isar_feature(aa32_vrint, s)) {
266
return false;
267
}
268
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
269
return false;
270
}
271
272
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
273
- return false;
274
- }
275
-
276
if (!vfp_access_check(s)) {
277
return true;
278
}
279
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
280
TCGv_i64 vd;
281
TCGv_i32 vm;
282
283
- /* UNDEF accesses to D16-D31 if they don't exist. */
284
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
285
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
286
return false;
287
}
288
289
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
290
+ /* UNDEF accesses to D16-D31 if they don't exist. */
291
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
292
return false;
293
}
294
295
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
296
TCGv_i64 vm;
297
TCGv_i32 vd;
298
299
- /* UNDEF accesses to D16-D31 if they don't exist. */
300
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
301
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
302
return false;
303
}
304
305
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
306
+ /* UNDEF accesses to D16-D31 if they don't exist. */
307
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
308
return false;
309
}
310
311
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
312
TCGv_i64 vd;
313
TCGv_ptr fpst;
314
315
- /* UNDEF accesses to D16-D31 if they don't exist. */
316
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
317
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
318
return false;
319
}
320
321
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
322
+ /* UNDEF accesses to D16-D31 if they don't exist. */
323
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
324
return false;
325
}
326
327
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
328
TCGv_i32 vd;
329
TCGv_i64 vm;
330
331
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
332
+ return false;
333
+ }
334
+
335
if (!dc_isar_feature(aa32_jscvt, s)) {
336
return false;
337
}
338
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
339
return false;
340
}
341
342
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
343
- return false;
344
- }
345
-
346
if (!vfp_access_check(s)) {
347
return true;
348
}
349
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
350
TCGv_ptr fpst;
351
int frac_bits;
352
353
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
354
+ return false;
355
+ }
356
+
357
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
358
return false;
359
}
360
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
361
return false;
362
}
363
364
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
365
- return false;
366
- }
367
-
368
if (!vfp_access_check(s)) {
369
return true;
370
}
371
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
372
TCGv_i64 vm;
373
TCGv_ptr fpst;
374
375
- /* UNDEF accesses to D16-D31 if they don't exist. */
376
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
377
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
378
return false;
379
}
380
381
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
382
+ /* UNDEF accesses to D16-D31 if they don't exist. */
383
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
384
return false;
385
}
386
387
--
63
--
388
2.20.1
64
2.34.1
389
390
diff view generated by jsdifflib
[PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Now that we no longer have an early check for ARM_FEATURE_VFP,
3
Replace the "index" selecting between A and B with a result variable
4
we can use the proper ISA check in trans_VLLDM_VLSTM.
4
of the proper type. This improves clarity within the function.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20200224222232.13807-12-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
12
target/arm/translate.c | 53 ++++++----------------------------
12
1 file changed, 13 insertions(+), 15 deletions(-)
13
target/arm/vfp.decode | 2 ++
14
3 files changed, 50 insertions(+), 44 deletions(-)
15
13
16
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-vfp.inc.c
16
--- a/fpu/softfloat-parts.c.inc
19
+++ b/target/arm/translate-vfp.inc.c
17
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
tcg_temp_free_ptr(fpst);
19
float_status *s)
22
return true;
20
{
23
}
21
bool have_snan = false;
24
+
22
- int cmp, which;
25
+/*
23
+ FloatPartsN *ret;
26
+ * Decode VLLDM and VLSTM are nonstandard because:
24
+ int cmp;
27
+ * * if there is no FPU then these insns must NOP in
25
28
+ * Secure state and UNDEF in Nonsecure state
26
if (is_snan(a->cls) || is_snan(b->cls)) {
29
+ * * if there is an FPU then these insns do not have
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
30
+ * the usual behaviour that vfp_access_check() provides of
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
31
+ * being controlled by CPACR/NSACR enable bits or the
29
switch (s->float_2nan_prop_rule) {
32
+ * lazy-stacking logic.
30
case float_2nan_prop_s_ab:
33
+ */
31
if (have_snan) {
34
+static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
32
- which = is_snan(a->cls) ? 0 : 1;
35
+{
33
+ ret = is_snan(a->cls) ? a : b;
36
+ TCGv_i32 fptr;
37
+
38
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
39
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
40
+ return false;
41
+ }
42
+ /* If not secure, UNDEF. */
43
+ if (!s->v8m_secure) {
44
+ return false;
45
+ }
46
+ /* If no fpu, NOP. */
47
+ if (!dc_isar_feature(aa32_vfp, s)) {
48
+ return true;
49
+ }
50
+
51
+ fptr = load_reg(s, a->rn);
52
+ if (a->l) {
53
+ gen_helper_v7m_vlldm(cpu_env, fptr);
54
+ } else {
55
+ gen_helper_v7m_vlstm(cpu_env, fptr);
56
+ }
57
+ tcg_temp_free_i32(fptr);
58
+
59
+ /* End the TB, because we have updated FP control bits */
60
+ s->base.is_jmp = DISAS_UPDATE;
61
+ return true;
62
+}
63
diff --git a/target/arm/translate.c b/target/arm/translate.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/translate.c
66
+++ b/target/arm/translate.c
67
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
68
goto illegal_op; /* op0 = 0b11 : unallocated */
69
}
70
71
- /*
72
- * Decode VLLDM and VLSTM first: these are nonstandard because:
73
- * * if there is no FPU then these insns must NOP in
74
- * Secure state and UNDEF in Nonsecure state
75
- * * if there is an FPU then these insns do not have
76
- * the usual behaviour that disas_vfp_insn() provides of
77
- * being controlled by CPACR/NSACR enable bits or the
78
- * lazy-stacking logic.
79
- */
80
- if (arm_dc_feature(s, ARM_FEATURE_V8) &&
81
- (insn & 0xffa00f00) == 0xec200a00) {
82
- /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
83
- * - VLLDM, VLSTM
84
- * We choose to UNDEF if the RAZ bits are non-zero.
85
- */
86
- if (!s->v8m_secure || (insn & 0x0040f0ff)) {
87
+ if (disas_vfp_insn(s, insn)) {
88
+ if (((insn >> 8) & 0xe) == 10 &&
89
+ dc_isar_feature(aa32_fpsp_v2, s)) {
90
+ /* FP, and the CPU supports it */
91
goto illegal_op;
92
+ } else {
93
+ /* All other insns: NOCP */
94
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
95
+ syn_uncategorized(),
96
+ default_exception_el(s));
97
}
98
-
99
- if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
100
- uint32_t rn = (insn >> 16) & 0xf;
101
- TCGv_i32 fptr = load_reg(s, rn);
102
-
103
- if (extract32(insn, 20, 1)) {
104
- gen_helper_v7m_vlldm(cpu_env, fptr);
105
- } else {
106
- gen_helper_v7m_vlstm(cpu_env, fptr);
107
- }
108
- tcg_temp_free_i32(fptr);
109
-
110
- /* End the TB, because we have updated FP control bits */
111
- s->base.is_jmp = DISAS_UPDATE;
112
- }
113
- break;
114
}
115
- if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
116
- ((insn >> 8) & 0xe) == 10) {
117
- /* FP, and the CPU supports it */
118
- if (disas_vfp_insn(s, insn)) {
119
- goto illegal_op;
120
- }
121
- break;
122
- }
123
-
124
- /* All other insns: NOCP */
125
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
126
- default_exception_el(s));
127
break;
34
break;
128
}
35
}
129
if ((insn & 0xfe000a00) == 0xfc000800
36
/* fall through */
130
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
37
case float_2nan_prop_ab:
131
index XXXXXXX..XXXXXXX 100644
38
- which = is_nan(a->cls) ? 0 : 1;
132
--- a/target/arm/vfp.decode
39
+ ret = is_nan(a->cls) ? a : b;
133
+++ b/target/arm/vfp.decode
40
break;
134
@@ -XXX,XX +XXX,XX @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
41
case float_2nan_prop_s_ba:
135
vd=%vd_sp vm=%vm_sp
42
if (have_snan) {
136
VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
43
- which = is_snan(b->cls) ? 1 : 0;
137
vd=%vd_sp vm=%vm_dp
44
+ ret = is_snan(b->cls) ? b : a;
138
+
45
break;
139
+VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
82
}
83
84
- if (which) {
85
- a = b;
86
+ if (is_snan(ret->cls)) {
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
94
}
95
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
140
--
97
--
141
2.20.1
98
2.34.1
142
99
143
100
diff view generated by jsdifflib
[PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Thomas Huth <thuth@redhat.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
There is a kernel and initrd available on github which we can use
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
for testing this machine.
4
update my email address, and update the mailmap to match.
5
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20200225172501.29609-3-philmd@redhat.com
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
12
Message-Id: <20200131170233.14584-1-thuth@redhat.com>
13
[PMD: Renamed test method, moved description from class to method]
14
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
MAINTAINERS | 1 +
14
MAINTAINERS | 2 +-
18
tests/acceptance/machine_arm_integratorcp.py | 43 ++++++++++++++++++++
15
.mailmap | 5 +++--
19
2 files changed, 44 insertions(+)
16
2 files changed, 4 insertions(+), 3 deletions(-)
20
create mode 100644 tests/acceptance/machine_arm_integratorcp.py
21
17
22
diff --git a/MAINTAINERS b/MAINTAINERS
18
diff --git a/MAINTAINERS b/MAINTAINERS
23
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
24
--- a/MAINTAINERS
20
--- a/MAINTAINERS
25
+++ b/MAINTAINERS
21
+++ b/MAINTAINERS
26
@@ -XXX,XX +XXX,XX @@ S: Maintained
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
27
F: hw/arm/integratorcp.c
23
SBSA-REF
28
F: hw/misc/arm_integrator_debug.c
24
M: Radoslaw Biernacki <rad@semihalf.com>
29
F: include/hw/misc/arm_integrator_debug.h
30
+F: tests/acceptance/machine_arm_integratorcp.py
31
32
MCIMX6UL EVK / i.MX6ul
33
M: Peter Maydell <peter.maydell@linaro.org>
25
M: Peter Maydell <peter.maydell@linaro.org>
34
diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
35
new file mode 100644
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
36
index XXXXXXX..XXXXXXX
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
37
--- /dev/null
29
L: qemu-arm@nongnu.org
38
+++ b/tests/acceptance/machine_arm_integratorcp.py
30
S: Maintained
39
@@ -XXX,XX +XXX,XX @@
31
diff --git a/.mailmap b/.mailmap
40
+# Functional test that boots a Linux kernel and checks the console
32
index XXXXXXX..XXXXXXX 100644
41
+#
33
--- a/.mailmap
42
+# Copyright (c) 2020 Red Hat, Inc.
34
+++ b/.mailmap
43
+#
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
44
+# Author:
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
45
+# Thomas Huth <thuth@redhat.com>
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
46
+#
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
47
+# This work is licensed under the terms of the GNU GPL, version 2 or
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
48
+# later. See the COPYING file in the top-level directory.
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
49
+
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
50
+import os
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
51
+
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
52
+from avocado import skipUnless
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
53
+from avocado_qemu import Test
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
54
+from avocado_qemu import wait_for_console_pattern
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
55
+
56
+class IntegratorMachine(Test):
57
+
58
+ timeout = 90
59
+
60
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
61
+ def test_integratorcp_console(self):
62
+ """
63
+ Boots the Linux kernel and checks that the console is operational
64
+ :avocado: tags=arch:arm
65
+ :avocado: tags=machine:integratorcp
66
+ """
67
+ kernel_url = ('https://github.com/zayac/qemu-arm/raw/master/'
68
+ 'arm-test/kernel/zImage.integrator')
69
+ kernel_hash = '0d7adba893c503267c946a3cbdc63b4b54f25468'
70
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
71
+
72
+ initrd_url = ('https://github.com/zayac/qemu-arm/raw/master/'
73
+ 'arm-test/kernel/arm_root.img')
74
+ initrd_hash = 'b51e4154285bf784e017a37586428332d8c7bd8b'
75
+ initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
76
+
77
+ self.vm.set_console()
78
+ self.vm.add_args('-kernel', kernel_path,
79
+ '-initrd', initrd_path,
80
+ '-append', 'printk.time=0 console=ttyAMA0')
81
+ self.vm.launch()
82
+ wait_for_console_pattern(self, 'Log in as root')
83
--
47
--
84
2.20.1
48
2.34.1
85
49
86
50
diff view generated by jsdifflib
[PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Thomas Huth <thuth@redhat.com>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
Old kernels from the Meego project can be used to check that Linux
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
is at least starting on these machines.
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
7
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
9
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200225172501.29609-2-philmd@redhat.com
12
Message-Id: <20200129131920.22302-1-thuth@redhat.com>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
MAINTAINERS | 1 +
11
MAINTAINERS | 2 ++
17
tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++
12
1 file changed, 2 insertions(+)
18
2 files changed, 50 insertions(+)
19
create mode 100644 tests/acceptance/machine_arm_n8x0.py
20
13
21
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/MAINTAINERS b/MAINTAINERS
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/MAINTAINERS
16
--- a/MAINTAINERS
24
+++ b/MAINTAINERS
17
+++ b/MAINTAINERS
25
@@ -XXX,XX +XXX,XX @@ F: hw/rtc/twl92230.c
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
26
F: include/hw/display/blizzard.h
19
27
F: include/hw/input/tsc2xxx.h
20
Xilinx CAN
28
F: include/hw/misc/cbus.h
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
29
+F: tests/acceptance/machine_arm_n8x0.py
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
30
23
S: Maintained
31
Palm
24
F: hw/net/can/xlnx-*
32
M: Andrzej Zaborowski <balrogg@gmail.com>
25
F: include/hw/net/xlnx-*
33
diff --git a/tests/acceptance/machine_arm_n8x0.py b/tests/acceptance/machine_arm_n8x0.py
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
34
new file mode 100644
27
CAN bus subsystem and hardware
35
index XXXXXXX..XXXXXXX
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
36
--- /dev/null
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
37
+++ b/tests/acceptance/machine_arm_n8x0.py
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
38
@@ -XXX,XX +XXX,XX @@
31
S: Maintained
39
+# Functional test that boots a Linux kernel and checks the console
32
W: https://canbus.pages.fel.cvut.cz/
40
+#
33
F: net/can/*
41
+# Copyright (c) 2020 Red Hat, Inc.
42
+#
43
+# Author:
44
+# Thomas Huth <thuth@redhat.com>
45
+#
46
+# This work is licensed under the terms of the GNU GPL, version 2 or
47
+# later. See the COPYING file in the top-level directory.
48
+
49
+import os
50
+
51
+from avocado import skipUnless
52
+from avocado_qemu import Test
53
+from avocado_qemu import wait_for_console_pattern
54
+
55
+class N8x0Machine(Test):
56
+ """Boots the Linux kernel and checks that the console is operational"""
57
+
58
+ timeout = 90
59
+
60
+ def __do_test_n8x0(self):
61
+ kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
62
+ 'meego-arm-n8x0-1.0.80.20100712.1431-'
63
+ 'vmlinuz-2.6.35~rc4-129.1-n8x0')
64
+ kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
65
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
66
+
67
+ self.vm.set_console(console_index=1)
68
+ self.vm.add_args('-kernel', kernel_path,
69
+ '-append', 'printk.time=0 console=ttyS1')
70
+ self.vm.launch()
71
+ wait_for_console_pattern(self, 'TSC2005 driver initializing')
72
+
73
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
74
+ def test_n800(self):
75
+ """
76
+ :avocado: tags=arch:arm
77
+ :avocado: tags=machine:n800
78
+ """
79
+ self.__do_test_n8x0()
80
+
81
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
82
+ def test_n810(self):
83
+ """
84
+ :avocado: tags=arch:arm
85
+ :avocado: tags=machine:n810
86
+ """
87
+ self.__do_test_n8x0()
88
--
34
--
89
2.20.1
35
2.34.1
90
91
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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