From: Gavin Shan <gshan@redhat.com>

This uses TYPE_PL011 when creating the serial port so that the code

looks cleaner.

Signed-off-by: Gavin Shan <gshan@redhat.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20200224222223.4128-1-gshan@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/sbsa-ref.c | 3 ++-

hw/arm/virt.c | 3 ++-

hw/arm/xlnx-versal.c | 3 ++-

3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/sbsa-ref.c

+++ b/hw/arm/sbsa-ref.c

@@ -XXX,XX +XXX,XX @@

#include "hw/pci-host/gpex.h"

#include "hw/qdev-properties.h"

#include "hw/usb.h"

+#include "hw/char/pl011.h"

#include "net/net.h"

#define RAMLIMIT_GB 8192

@@ -XXX,XX +XXX,XX @@ static void create_uart(const SBSAMachineState *sms, int uart,

{

hwaddr base = sbsa_ref_memmap[uart].base;

int irq = sbsa_ref_irqmap[uart];

- DeviceState *dev = qdev_create(NULL, "pl011");

+ DeviceState *dev = qdev_create(NULL, TYPE_PL011);

SysBusDevice *s = SYS_BUS_DEVICE(dev);

qdev_prop_set_chr(dev, "chardev", chr);

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@

#include "hw/mem/nvdimm.h"

#include "hw/acpi/generic_event_device.h"

#include "hw/virtio/virtio-iommu.h"

+#include "hw/char/pl011.h"

#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \

static void virt_##major##_##minor##_class_init(ObjectClass *oc, \

@@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, int uart,

int irq = vms->irqmap[uart];

const char compat[] = "arm,pl011\0arm,primecell";

const char clocknames[] = "uartclk\0apb_pclk";

- DeviceState *dev = qdev_create(NULL, "pl011");

+ DeviceState *dev = qdev_create(NULL, TYPE_PL011);

SysBusDevice *s = SYS_BUS_DEVICE(dev);

qdev_prop_set_chr(dev, "chardev", chr);

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@

#include "hw/misc/unimp.h"

#include "hw/intc/arm_gicv3_common.h"

#include "hw/arm/xlnx-versal.h"

+#include "hw/char/pl011.h"

#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")

#define GEM_REVISION 0x40070106

@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)

DeviceState *dev;

MemoryRegion *mr;

- dev = qdev_create(NULL, "pl011");

+ dev = qdev_create(NULL, TYPE_PL011);

s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);

qdev_prop_set_chr(dev, "chardev", serial_hd(i));

object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

We had set this for aarch32-only in arm_max_initfn, but

failed to set the same bit for aarch64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200218190958.745-2-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu64.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

cpu->isar.id_mmfr3 = u;

u = cpu->isar.id_mmfr4;

+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */

u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

cpu->isar.id_mmfr4 = u;

--

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The Linux kernel displays errors why trying to detect the PL041

audio interface:

Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018

CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177

CPU: VIVT data cache, VIVT instruction cache

OF: fdt: Machine model: ARM Integrator/CP

...

OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000

Since we have it already modelled, simply plug it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200223233033.15371-2-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/integratorcp.c | 1 +

hw/arm/Kconfig | 1 +

2 files changed, 2 insertions(+)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/integratorcp.c

+++ b/hw/arm/integratorcp.c

@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)

qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));

qdev_connect_gpio_out(dev, 1,

qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));

+ sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);

if (nd_table[0].used)

smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config INTEGRATOR

select INTEGRATOR_DEBUG

select PL011 # UART

select PL031 # RTC

+ select PL041 # audio

select PL050 # keyboard/mouse

select PL110 # pl111 LCD controller

select PL181 # display

--

2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

The GICv2 allows the implementation to implement a variable number

of priority bits; unimplemented bits in the priority registers

are read as zeros, writes ignored. We were previously always

implementing a full 8 bits of priority, which is allowed but not

what the real hardware typically does (which is usually to have

4 or 5 bits of priority).

Add a new device property to allow the number of implemented

property bits to be specified.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

[PMM: improved commit message]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/intc/arm_gic.h | 2 ++

include/hw/intc/arm_gic_common.h | 1 +

hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++--

hw/intc/arm_gic_common.c | 1 +

4 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/intc/arm_gic.h

+++ b/include/hw/intc/arm_gic.h

@@ -XXX,XX +XXX,XX @@

/* Number of SGI target-list bits */

#define GIC_TARGETLIST_BITS 8

+#define GIC_MAX_PRIORITY_BITS 8

+#define GIC_MIN_PRIORITY_BITS 4

#define TYPE_ARM_GIC "arm_gic"

#define ARM_GIC(obj) \

diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/intc/arm_gic_common.h

+++ b/include/hw/intc/arm_gic_common.h

@@ -XXX,XX +XXX,XX @@ typedef struct GICState {

uint16_t priority_mask[GIC_NCPU_VCPU];

uint16_t running_priority[GIC_NCPU_VCPU];

uint16_t current_pending[GIC_NCPU_VCPU];

+ uint32_t n_prio_bits;

/* If we present the GICv2 without security extensions to a guest,

* the guest can configure the GICC_CTLR to configure group 1 binary point

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gic.c

+++ b/hw/intc/arm_gic.c

@@ -XXX,XX +XXX,XX @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)

return ret;

}

+static uint32_t gic_fullprio_mask(GICState *s, int cpu)

+{

+ /*

+ * Return a mask word which clears the unimplemented priority

+ * bits from a priority value for an interrupt. (Not to be

+ * confused with the group priority, whose mask depends on BPR.)

+ */

+ int priBits;

+

+ if (gic_is_vcpu(cpu)) {

+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;

+ } else {

+ priBits = s->n_prio_bits;

+ }

+ return ~0U << (8 - priBits);

+}

+

void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,

MemTxAttrs attrs)

{

@@ -XXX,XX +XXX,XX @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,

val = 0x80 | (val >> 1); /* Non-secure view */

}

+ val &= gic_fullprio_mask(s, cpu);

+

if (irq < GIC_INTERNAL) {

s->priority1[irq][cpu] = val;

} else {

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,

}

prio = (prio << 1) & 0xff; /* Non-secure view */

}

- return prio;

+ return prio & gic_fullprio_mask(s, cpu);

}

static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,

@@ -XXX,XX +XXX,XX @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,

return;

}

}

- s->priority_mask[cpu] = pmask;

+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);

}

static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)

@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)

return;

}

+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||

+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :

+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {

+ error_setg(errp, "num-priority-bits cannot be greater than %d"

+ " or less than %d", GIC_MAX_PRIORITY_BITS,

+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :

+ GIC_MIN_PRIORITY_BITS);

+ return;

+ }

+

/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if

* enabled, virtualization extensions related interfaces (main virtual

* interface (s->vifaceiomem[0]) and virtual CPU interface).

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gic_common.c

+++ b/hw/intc/arm_gic_common.c

@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {

DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),

/* True if the GIC should implement the virtualization extensions */

DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),

+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),

DEFINE_PROP_END_OF_LIST(),

};

--

2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

All A9 CPUs have a GIC with 5 bits of priority.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/cpu/a9mpcore.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/cpu/a9mpcore.c

+++ b/hw/cpu/a9mpcore.c

@@ -XXX,XX +XXX,XX @@

#include "hw/qdev-properties.h"

#include "hw/core/cpu.h"

+#define A9_GIC_NUM_PRIORITY_BITS 5

+

static void a9mp_priv_set_irq(void *opaque, int irq, int level)

{

A9MPPrivState *s = (A9MPPrivState *)opaque;

@@ -XXX,XX +XXX,XX @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)

gicdev = DEVICE(&s->gic);

qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);

qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);

+ qdev_prop_set_uint32(gicdev, "num-priority-bits",

+ A9_GIC_NUM_PRIORITY_BITS);

/* Make the GIC's TZ support match the CPUs. We assume that

* either all the CPUs have TZ, or none do.

--

2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

The GIC built into the ARM11MPCore is always implemented with 4

priority bits; set the GIC property accordingly.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

[PMM: tweaked commit message]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/cpu/arm11mpcore.c | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/cpu/arm11mpcore.c

+++ b/hw/cpu/arm11mpcore.c

@@ -XXX,XX +XXX,XX @@

#include "hw/irq.h"

#include "hw/qdev-properties.h"

+#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4

static void mpcore_priv_set_irq(void *opaque, int irq, int level)

{

@@ -XXX,XX +XXX,XX @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)

qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);

qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);

+ qdev_prop_set_uint32(gicdev, "num-priority-bits",

+ ARM11MPCORE_NUM_GIC_PRIORITY_BITS);

+

+

object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);

if (err != NULL) {

error_propagate(errp, err);

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Use this in the places that were checking ARM_FEATURE_VFP, and

are obviously testing for the existance of the register set

as opposed to testing for some particular instruction extension.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20200224222232.13807-2-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 9 +++++++++

hw/intc/armv7m_nvic.c | 20 ++++++++++----------

linux-user/arm/signal.c | 4 ++--

target/arm/arch_dump.c | 11 ++++++-----

target/arm/cpu.c | 4 ++--

target/arm/helper.c | 4 ++--

target/arm/m_helper.c | 11 ++++++-----

7 files changed, 37 insertions(+), 26 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;

}

+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)

+{

+ /*

+ * Return true if either VFP or SIMD is implemented.

+ * In this case, a minimum of VFP w/ D0-D15.

+ */

+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;

+}

+

static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)

{

/* Return true if D16-D31 are implemented */

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

case 0xd84: /* CSSELR */

return cpu->env.v7m.csselr[attrs.secure];

case 0xd88: /* CPACR */

- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {

return 0;

}

return cpu->env.v7m.cpacr[attrs.secure];

case 0xd8c: /* NSACR */

- if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {

return 0;

}

return cpu->env.v7m.nsacr;

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

}

return cpu->env.v7m.sfar;

case 0xf34: /* FPCCR */

- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {

return 0;

}

if (attrs.secure) {

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

return value;

}

case 0xf38: /* FPCAR */

- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {

return 0;

}

return cpu->env.v7m.fpcar[attrs.secure];

case 0xf3c: /* FPDSCR */

- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {

return 0;

}

return cpu->env.v7m.fpdscr[attrs.secure];

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

}

break;

case 0xd88: /* CPACR */

- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

/* We implement only the Floating Point extension's CP10/CP11 */

cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);

}

break;

case 0xd8c: /* NSACR */

- if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {

/* We implement only the Floating Point extension's CP10/CP11 */

cpu->env.v7m.nsacr = value & (3 << 10);

}

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

break;

}

case 0xf34: /* FPCCR */

- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

/* Not all bits here are banked. */

uint32_t fpccr_s;

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

}

break;

case 0xf38: /* FPCAR */

- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

value &= ~7;

cpu->env.v7m.fpcar[attrs.secure] = value;

}

break;

case 0xf3c: /* FPDSCR */

- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

value &= 0x07c00000;

cpu->env.v7m.fpdscr[attrs.secure] = value;

}

diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/arm/signal.c

+++ b/linux-user/arm/signal.c

@@ -XXX,XX +XXX,XX @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,

setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);

/* Save coprocessor signal frame. */

regspace = uc->tuc_regspace;

- if (arm_feature(env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {

regspace = setup_sigframe_v2_vfp(regspace, env);

}

if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

@@ -XXX,XX +XXX,XX @@ static int do_sigframe_return_v2(CPUARMState *env,

/* Restore coprocessor signal frame */

regspace = uc->tuc_regspace;

- if (arm_feature(env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {

regspace = restore_sigframe_v2_vfp(env, regspace);

if (!regspace) {

return 1;

diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/arch_dump.c

+++ b/target/arm/arch_dump.c

@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,

int cpuid, void *opaque)

{

struct arm_note note;

- CPUARMState *env = &ARM_CPU(cs)->env;

+ ARMCPU *cpu = ARM_CPU(cs);

+ CPUARMState *env = &cpu->env;

DumpState *s = opaque;

- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);

+ int ret, i;

+ bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);

arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));

@@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info,

ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)

{

ARMCPU *cpu = ARM_CPU(first_cpu);

- CPUARMState *env = &cpu->env;

size_t note_size;

if (class == ELFCLASS64) {

@@ -XXX,XX +XXX,XX @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)

note_size += AARCH64_PRFPREG_NOTE_SIZE;

#ifdef TARGET_AARCH64

if (cpu_isar_feature(aa64_sve, cpu)) {

- note_size += AARCH64_SVE_NOTE_SIZE(env);

+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);

}

#endif

} else {

note_size = ARM_PRSTATUS_NOTE_SIZE;

- if (arm_feature(env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

note_size += ARM_VFP_NOTE_SIZE;

}

}

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;

}

- if (arm_feature(env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;

env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |

R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)

int numvfpregs = 0;

if (cpu_isar_feature(aa32_simd_r32, cpu)) {

numvfpregs = 32;

- } else if (arm_feature(env, ARM_FEATURE_VFP)) {

+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

numvfpregs = 16;

}

for (i = 0; i < numvfpregs; i++) {

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,

* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.

* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.

*/

- if (arm_feature(env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {

/* VFP coprocessor: cp10 & cp11 [23:20] */

mask |= (1 << 31) | (1 << 30) | (0xf << 20);

@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)

} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {

gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

35, "arm-vfp3.xml", 0);

- } else if (arm_feature(env, ARM_FEATURE_VFP)) {

+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

19, "arm-vfp.xml", 0);

}

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/m_helper.c

+++ b/target/arm/m_helper.c

@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)

*/

uint32_t sig = 0xfefa125a;

- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {

+ if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))

+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {

sig |= 1;

}

return sig;

@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,

if (dotailchain) {

/* Sanitize LR FType and PREFIX bits */

- if (!arm_feature(env, ARM_FEATURE_VFP)) {

+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {

lr |= R_V7M_EXCRET_FTYPE_MASK;

}

lr = deposit32(lr, 24, 8, 0xff);

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

ftype = excret & R_V7M_EXCRET_FTYPE_MASK;

- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {

+ if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {

qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "

"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "

"if FPU not present\n",

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)

* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,

* RES0 if the FPU is not present, and is stored in the S bank

*/

- if (arm_feature(env, ARM_FEATURE_VFP) &&

+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&

extract32(env->v7m.nsacr, 10, 1)) {

env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;

env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)

env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;

env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;

}

- if (arm_feature(env, ARM_FEATURE_VFP)) {

+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {

/*

* SFPA is RAZ/WI from NS or if no FPU.

* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The old name, isar_feature_aa32_fpdp, does not reflect

that the test includes VFPv2. We will introduce another

feature tests for VFPv3.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200224222232.13807-3-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 4 ++--

target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------

2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)

return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;

}

-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)

+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)

{

- /* Return true if CPU supports double precision floating point */

+ /* Return true if CPU supports double precision floating point, VFPv2 */

return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;

}

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-vfp.inc.c

+++ b/target/arm/translate-vfp.inc.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp, s)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp, s)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp, s)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp, s)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp, s)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

We will shortly use these to test for VFPv2 and VFPv3

in different situations.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200224222232.13807-4-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 18 ++++++++++++++++++

1 file changed, 18 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)

return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;

}

+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)

+{

+ /* Return true if CPU supports single precision floating point, VFPv2 */

+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;

+}

+

+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)

+{

+ /* Return true if CPU supports single precision floating point, VFPv3 */

+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;

+}

+

static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)

{

/* Return true if CPU supports double precision floating point, VFPv2 */

return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;

}

+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)

+{

+ /* Return true if CPU supports double precision floating point, VFPv3 */

+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;

+}

+

/*

* We always set the FP and SIMD FP16 fields to indicate identical

* levels of support (assuming SIMD is implemented at all), so

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

We cannot easily create "any" functions for these, because the

ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.

Which means that an aarch32-only cpu will return incorrect results

when testing the aarch64 registers.

To use these, we must either have context or additionally test

vs ARM_FEATURE_AARCH64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20200224222232.13807-5-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 11 +++++++++++

target/arm/cpu.c | 9 ++++++---

target/arm/machine.c | 5 +++--

3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)

return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;

}

+static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)

+{

+ return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);

+}

+

/*

* We always set the FP and SIMD FP16 fields to indicate identical

* levels of support (assuming SIMD is implemented at all), so

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;

}

+static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)

+{

+ /* We always set the AdvSIMD and FP fields identically. */

+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;

+}

+

static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)

{

/* We always set the AdvSIMD and FP fields identically wrt FP16. */

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)

* KVM does not currently allow us to lie to the guest about its

* ID/feature registers, so the guest always sees what the host has.

*/

- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {

+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)

+ ? cpu_isar_feature(aa64_fp_simd, cpu)

+ : cpu_isar_feature(aa32_vfp, cpu)) {

cpu->has_vfp = true;

if (!kvm_enabled()) {

qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

* We rely on no XScale CPU having VFP so we can use the same bits in the

* TB flags field for VECSTRIDE and XSCALE_CPAR.

*/

- assert(!(arm_feature(env, ARM_FEATURE_VFP) &&

- arm_feature(env, ARM_FEATURE_XSCALE)));

+ assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||

+ !cpu_isar_feature(aa32_vfp_simd, cpu) ||

+ !arm_feature(env, ARM_FEATURE_XSCALE));

if (arm_feature(env, ARM_FEATURE_V7) &&

!arm_feature(env, ARM_FEATURE_M) &&

diff --git a/target/arm/machine.c b/target/arm/machine.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/machine.c

+++ b/target/arm/machine.c

@@ -XXX,XX +XXX,XX @@

static bool vfp_needed(void *opaque)

{

ARMCPU *cpu = opaque;

- CPUARMState *env = &cpu->env;

- return arm_feature(env, ARM_FEATURE_VFP);

+ return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)

+ ? cpu_isar_feature(aa64_fp_simd, cpu)

+ : cpu_isar_feature(aa32_vfp_simd, cpu));

}

static int get_fpscr(QEMUFile *f, void *opaque, size_t size,

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Shuffle the order of the checks so that we test the ISA

before we test anything else, such as the register arguments.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200224222232.13807-7-richard.henderson@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/translate-vfp.inc.c | 140 +++++++++++++++++----------------

1 file changed, 71 insertions(+), 69 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-vfp.inc.c

+++ b/target/arm/translate-vfp.inc.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)

return false;

}

- /* UNDEF accesses to D16-D31 if they don't exist */

- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&

- ((a->vm | a->vn | a->vd) & 0x10)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist */

+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&

+ ((a->vm | a->vn | a->vd) & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)

return false;

}

- /* UNDEF accesses to D16-D31 if they don't exist */

- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&

- ((a->vm | a->vn | a->vd) & 0x10)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist */

+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&

+ ((a->vm | a->vn | a->vd) & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)

return false;

}

- /* UNDEF accesses to D16-D31 if they don't exist */

- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&

- ((a->vm | a->vd) & 0x10)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist */

+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&

+ ((a->vm | a->vd) & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)

return false;

}

- /* UNDEF accesses to D16-D31 if they don't exist */

- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {

+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist */

+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,

TCGv_i64 f0, f1, fd;

TCGv_ptr fpst;

- /* UNDEF accesses to D16-D31 if they don't exist */

- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

- if (!dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist */

+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)

int veclen = s->vec_len;

TCGv_i64 f0, fd;

- /* UNDEF accesses to D16-D31 if they don't exist */

- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {

+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {

return false;

}

- if (!dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist */

+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)

return false;

}

- if (!dc_isar_feature(aa32_fpdp_v2, s)) {

+ /* UNDEF accesses to D16-D31 if they don't exist. */

+ if (!dc_isar_feature(aa32_simd_r32, s) &&

+ ((a->vd | a->vn | a->vm) & 0x10)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)