[PULL 0/3] tcg patch queue
[PULL v2 00/74] tcg patch queue
1
The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
1
v2: Drop a few patches, which showed regressions in CI
2
for jobs that are not run for forks. :-/
2
3
3
Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
4
5
r~
6
7
8
The following changes since commit f9d58e0ca53b3f470b84725a7b5e47fcf446a2ea:
9
10
Merge tag 'pull-9p-20230516' of https://github.com/cschoenebeck/qemu into staging (2023-05-16 10:21:44 -0700)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230516-2
8
15
9
for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
16
for you to fetch changes up to 44fe8f47fce3bdc8dcf49e3f001519a375ecc88a:
10
17
11
tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
18
tcg: Split out exec/user/guest-base.h (2023-05-16 16:31:05 -0700)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
Fix breakpoint invalidation.
21
tcg/i386: Fix tcg_out_addi_ptr for win64
15
Add support for tcg helpers with 7 arguments.
22
tcg: Implement atomicity for TCGv_i128
16
Add support for gvec helpers with 5 arguments.
23
tcg: First quarter of cleanups for building tcg once
17
24
18
----------------------------------------------------------------
25
----------------------------------------------------------------
19
Max Filippov (1):
26
Richard Henderson (74):
20
exec: flush CPU TB cache in breakpoint_invalidate
27
tcg/i386: Set P_REXW in tcg_out_addi_ptr
28
include/exec/memop: Add MO_ATOM_*
29
accel/tcg: Honor atomicity of loads
30
accel/tcg: Honor atomicity of stores
31
tcg: Unify helper_{be,le}_{ld,st}*
32
accel/tcg: Implement helper_{ld,st}*_mmu for user-only
33
tcg/tci: Use helper_{ld,st}*_mmu for user-only
34
tcg: Add 128-bit guest memory primitives
35
meson: Detect atomic128 support with optimization
36
tcg/i386: Add have_atomic16
37
tcg/aarch64: Detect have_lse, have_lse2 for linux
38
tcg/aarch64: Detect have_lse, have_lse2 for darwin
39
tcg/i386: Use full load/store helpers in user-only mode
40
tcg/aarch64: Use full load/store helpers in user-only mode
41
tcg/ppc: Use full load/store helpers in user-only mode
42
tcg/loongarch64: Use full load/store helpers in user-only mode
43
tcg/riscv: Use full load/store helpers in user-only mode
44
tcg/arm: Adjust constraints on qemu_ld/st
45
tcg/arm: Use full load/store helpers in user-only mode
46
tcg/mips: Use full load/store helpers in user-only mode
47
tcg/s390x: Use full load/store helpers in user-only mode
48
tcg/sparc64: Allocate %g2 as a third temporary
49
tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13
50
target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32
51
tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32
52
tcg/sparc64: Split out tcg_out_movi_s32
53
tcg/sparc64: Use standard slow path for softmmu
54
accel/tcg: Remove helper_unaligned_{ld,st}
55
tcg/loongarch64: Check the host supports unaligned accesses
56
tcg/loongarch64: Support softmmu unaligned accesses
57
tcg/riscv: Support softmmu unaligned accesses
58
tcg: Introduce tcg_target_has_memory_bswap
59
tcg: Add INDEX_op_qemu_{ld,st}_i128
60
tcg: Introduce tcg_out_movext3
61
tcg: Merge tcg_out_helper_load_regs into caller
62
tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}
63
tcg: Introduce atom_and_align_for_opc
64
tcg/i386: Use atom_and_align_for_opc
65
tcg/aarch64: Use atom_and_align_for_opc
66
tcg/arm: Use atom_and_align_for_opc
67
tcg/loongarch64: Use atom_and_align_for_opc
68
tcg/mips: Use atom_and_align_for_opc
69
tcg/ppc: Use atom_and_align_for_opc
70
tcg/riscv: Use atom_and_align_for_opc
71
tcg/s390x: Use atom_and_align_for_opc
72
tcg/sparc64: Use atom_and_align_for_opc
73
tcg: Split out memory ops to tcg-op-ldst.c
74
tcg: Widen gen_insn_data to uint64_t
75
accel/tcg: Widen tcg-ldst.h addresses to uint64_t
76
tcg: Widen helper_{ld,st}_i128 addresses to uint64_t
77
tcg: Widen helper_atomic_* addresses to uint64_t
78
tcg: Widen tcg_gen_code pc_start argument to uint64_t
79
accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback
80
accel/tcg: Merge do_gen_mem_cb into caller
81
tcg: Reduce copies for plugin_gen_mem_callbacks
82
accel/tcg: Widen plugin_gen_empty_mem_callback to i64
83
tcg: Add addr_type to TCGContext
84
tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
85
tcg: Remove TCGv from tcg_gen_atomic_*
86
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
87
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
88
tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
89
tcg/i386: Conditionalize tcg_out_extu_i32_i64
90
tcg/i386: Adjust type of tlb_mask
91
tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
92
tcg/arm: Remove TARGET_LONG_BITS
93
tcg/aarch64: Remove USE_GUEST_BASE
94
tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
95
tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
96
tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
97
tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
98
tcg: Add page_bits and page_mask to TCGContext
99
tcg: Add tlb_dyn_max_bits to TCGContext
100
tcg: Split out exec/user/guest-base.h
21
101
22
Richard Henderson (1):
102
docs/devel/loads-stores.rst | 36 +-
23
tcg: Add tcg_gen_gvec_5_ptr
103
docs/devel/tcg-ops.rst | 11 +-
24
104
meson.build | 52 +-
25
Taylor Simpson (1):
105
accel/tcg/tcg-runtime.h | 49 +-
26
tcg: Add support for a helper with 7 arguments
106
include/exec/cpu-all.h | 5 +-
27
107
include/exec/memop.h | 37 ++
28
include/exec/helper-gen.h | 13 +++++++++++++
108
include/exec/plugin-gen.h | 4 +-
29
include/exec/helper-head.h | 2 ++
109
include/exec/user/guest-base.h | 12 +
30
include/exec/helper-proto.h | 6 ++++++
110
include/qemu/cpuid.h | 18 +
31
include/exec/helper-tcg.h | 7 +++++++
111
include/tcg/tcg-ldst.h | 72 +--
32
include/tcg/tcg-op-gvec.h | 7 +++++++
112
include/tcg/tcg-op.h | 273 ++++++---
33
exec.c | 15 +++++++--------
113
include/tcg/tcg-opc.h | 41 +-
34
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
114
include/tcg/tcg.h | 39 +-
35
7 files changed, 74 insertions(+), 8 deletions(-)
115
tcg/aarch64/tcg-target.h | 6 +-
36
116
tcg/arm/tcg-target-con-set.h | 16 +-
117
tcg/arm/tcg-target-con-str.h | 5 +-
118
tcg/arm/tcg-target.h | 3 +-
119
tcg/i386/tcg-target.h | 12 +-
120
tcg/loongarch64/tcg-target.h | 3 +-
121
tcg/mips/tcg-target.h | 4 +-
122
tcg/ppc/tcg-target.h | 3 +-
123
tcg/riscv/tcg-target.h | 4 +-
124
tcg/s390x/tcg-target.h | 4 +-
125
tcg/sparc64/tcg-target-con-set.h | 2 -
126
tcg/sparc64/tcg-target-con-str.h | 1 -
127
tcg/sparc64/tcg-target.h | 4 +-
128
tcg/tcg-internal.h | 2 +
129
tcg/tci/tcg-target.h | 4 +-
130
accel/tcg/cputlb.c | 839 ++++++++++++++++---------
131
accel/tcg/plugin-gen.c | 68 +-
132
accel/tcg/translate-all.c | 35 +-
133
accel/tcg/user-exec.c | 488 ++++++++++-----
134
tcg/optimize.c | 19 +-
135
tcg/tcg-op-ldst.c | 1234 +++++++++++++++++++++++++++++++++++++
136
tcg/tcg-op.c | 864 --------------------------
137
tcg/tcg.c | 631 +++++++++++++++----
138
tcg/tci.c | 243 +++-----
139
accel/tcg/atomic_common.c.inc | 14 +-
140
accel/tcg/ldst_atomicity.c.inc | 1262 ++++++++++++++++++++++++++++++++++++++
141
tcg/aarch64/tcg-target.c.inc | 207 +++----
142
tcg/arm/tcg-target.c.inc | 246 +++-----
143
tcg/i386/tcg-target.c.inc | 240 ++++----
144
tcg/loongarch64/tcg-target.c.inc | 123 ++--
145
tcg/mips/tcg-target.c.inc | 216 +++----
146
tcg/ppc/tcg-target.c.inc | 189 +++---
147
tcg/riscv/tcg-target.c.inc | 161 ++---
148
tcg/s390x/tcg-target.c.inc | 104 +---
149
tcg/sparc64/tcg-target.c.inc | 731 ++++++++--------------
150
tcg/tci/tcg-target.c.inc | 58 +-
151
tcg/meson.build | 1 +
152
50 files changed, 5345 insertions(+), 3350 deletions(-)
153
create mode 100644 include/exec/user/guest-base.h
154
create mode 100644 tcg/tcg-op-ldst.c
155
create mode 100644 accel/tcg/ldst_atomicity.c.inc
diff view generated by jsdifflib
[PULL 1/3] exec: flush CPU TB cache in breakpoint_invalidate
Deleted patch
1
From: Max Filippov <jcmvbkbc@gmail.com>
2
1
3
When a breakpoint is inserted at location for which there's currently no
4
virtual to physical translation no action is taken on CPU TB cache. If a
5
TB for that virtual address already exists but is not visible ATM the
6
breakpoint won't be hit next time an instruction at that address will be
7
executed.
8
9
Flush entire CPU TB cache in breakpoint_invalidate to force
10
re-translation of all TBs for the breakpoint address.
11
12
This change fixes the following scenario:
13
- linux user application is running
14
- a breakpoint is inserted from QEMU gdbstub for a user address that is
15
not currently present in the target CPU TLB
16
- an instruction at that address is executed, but the external debugger
17
doesn't get control.
18
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
21
Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
24
exec.c | 15 +++++++--------
25
1 file changed, 7 insertions(+), 8 deletions(-)
26
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
32
33
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
34
{
35
- MemTxAttrs attrs;
36
- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
37
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
38
- if (phys != -1) {
39
- /* Locks grabbed by tb_invalidate_phys_addr */
40
- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
41
- phys | (pc & ~TARGET_PAGE_MASK), attrs);
42
- }
43
+ /*
44
+ * There may not be a virtual to physical translation for the pc
45
+ * right now, but there may exist cached TB for this pc.
46
+ * Flush the whole TB cache to force re-translation of such TBs.
47
+ * This is heavyweight, but we're debugging anyway.
48
+ */
49
+ tb_flush(cpu);
50
}
51
#endif
52
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
[PULL 2/3] tcg: Add support for a helper with 7 arguments
Deleted patch
1
From: Taylor Simpson <tsimpson@quicinc.com>
2
1
3
Currently, helpers can only take up to 6 arguments. This patch adds the
4
capability for up to 7 arguments. I have tested it with the Hexagon port
5
that I am preparing for submission.
6
7
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
8
Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/helper-gen.h | 13 +++++++++++++
12
include/exec/helper-head.h | 2 ++
13
include/exec/helper-proto.h | 6 ++++++
14
include/exec/helper-tcg.h | 7 +++++++
15
4 files changed, 28 insertions(+)
16
17
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/helper-gen.h
20
+++ b/include/exec/helper-gen.h
21
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
22
tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
23
}
24
25
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
26
+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
27
+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
28
+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
29
+ dh_arg_decl(t7, 7)) \
30
+{ \
31
+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
32
+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
33
+ dh_arg(t7, 7) }; \
34
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
35
+}
36
+
37
#include "helper.h"
38
#include "trace/generated-helpers.h"
39
#include "trace/generated-helpers-wrappers.h"
40
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
41
#undef DEF_HELPER_FLAGS_4
42
#undef DEF_HELPER_FLAGS_5
43
#undef DEF_HELPER_FLAGS_6
44
+#undef DEF_HELPER_FLAGS_7
45
#undef GEN_HELPER
46
47
#endif /* HELPER_GEN_H */
48
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/helper-head.h
51
+++ b/include/exec/helper-head.h
52
@@ -XXX,XX +XXX,XX @@
53
DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
54
#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
55
DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
56
+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
57
+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
58
59
/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
60
61
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/exec/helper-proto.h
64
+++ b/include/exec/helper-proto.h
65
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
66
dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
68
69
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
70
+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
71
+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
72
+ dh_ctype(t7));
73
+
74
#include "helper.h"
75
#include "trace/generated-helpers.h"
76
#include "tcg-runtime.h"
77
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
78
#undef DEF_HELPER_FLAGS_4
79
#undef DEF_HELPER_FLAGS_5
80
#undef DEF_HELPER_FLAGS_6
81
+#undef DEF_HELPER_FLAGS_7
82
83
#endif /* HELPER_PROTO_H */
84
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/exec/helper-tcg.h
87
+++ b/include/exec/helper-tcg.h
88
@@ -XXX,XX +XXX,XX @@
89
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
90
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
91
92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
93
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
94
+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
95
+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
96
+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
97
+
98
#include "helper.h"
99
#include "trace/generated-helpers.h"
100
#include "tcg-runtime.h"
101
@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
104
#undef DEF_HELPER_FLAGS_6
105
+#undef DEF_HELPER_FLAGS_7
106
107
#endif /* HELPER_TCG_H */
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_gvec_5_ptr
Deleted patch
1
Extend the vector generator infrastructure to handle
2
5 vector arguments.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/tcg/tcg-op-gvec.h | 7 +++++++
10
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
11
2 files changed, 39 insertions(+)
12
13
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/tcg/tcg-op-gvec.h
16
+++ b/include/tcg/tcg-op-gvec.h
17
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
18
uint32_t maxsz, int32_t data,
19
gen_helper_gvec_4_ptr *fn);
20
21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
22
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
23
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
24
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
25
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
26
+ gen_helper_gvec_5_ptr *fn);
27
+
28
/* Expand a gvec operation. Either inline or out-of-line depending on
29
the actual vector size and the operations supported by the host. */
30
typedef struct {
31
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg-op-gvec.c
34
+++ b/tcg/tcg-op-gvec.c
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
36
tcg_temp_free_i32(desc);
37
}
38
39
+/* Generate a call to a gvec-style helper with five vector operands
40
+ and an extra pointer operand. */
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
44
+ gen_helper_gvec_5_ptr *fn)
45
+{
46
+ TCGv_ptr a0, a1, a2, a3, a4;
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
48
+
49
+ a0 = tcg_temp_new_ptr();
50
+ a1 = tcg_temp_new_ptr();
51
+ a2 = tcg_temp_new_ptr();
52
+ a3 = tcg_temp_new_ptr();
53
+ a4 = tcg_temp_new_ptr();
54
+
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
56
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
57
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
58
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
59
+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
60
+
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
62
+
63
+ tcg_temp_free_ptr(a0);
64
+ tcg_temp_free_ptr(a1);
65
+ tcg_temp_free_ptr(a2);
66
+ tcg_temp_free_ptr(a3);
67
+ tcg_temp_free_ptr(a4);
68
+ tcg_temp_free_i32(desc);
69
+}
70
+
71
/* Return true if we want to implement something of OPRSZ bytes
72
in units of LNSZ. This limits the expansion of inline code. */
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
74
--
75
2.20.1
76
77
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.