[PULL 0/3] tcg patch queue
[PULL v2 00/53] tcg patch queue
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The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
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v2: Remove poisoned symbol CONFIG_RISCV_DIS from disas.c.
2
Wasn't visible from x86 with gcc or clang;
3
was visible from macos clang;
4
was visible from native riscv clang.
2
5
3
Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
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7
r~
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9
10
The following changes since commit fff86d48a2cdcdfa75f845cac3e0d3cdd848d9e4:
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12
Merge tag 'migration-20230509-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-05-11 05:55:12 +0100)
4
13
5
are available in the Git repository at:
14
are available in the Git repository at:
6
15
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
16
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230511-2
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17
9
for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
18
for you to fetch changes up to 335dfd253fc242b009a1b9b5d4fffbf4ea52928d:
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19
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tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
20
target/loongarch: Do not include tcg-ldst.h (2023-05-11 09:53:41 +0100)
12
21
13
----------------------------------------------------------------
22
----------------------------------------------------------------
14
Fix breakpoint invalidation.
23
target/m68k: Fix gen_load_fp regression
15
Add support for tcg helpers with 7 arguments.
24
accel/tcg: Ensure fairness with icount
16
Add support for gvec helpers with 5 arguments.
25
disas: Move disas.c into the target-independent source sets
26
tcg: Use common routines for calling slow path helpers
27
tcg/*: Cleanups to qemu_ld/st constraints
28
tcg: Remove TARGET_ALIGNED_ONLY
29
accel/tcg: Reorg system mode load/store helpers
17
30
18
----------------------------------------------------------------
31
----------------------------------------------------------------
19
Max Filippov (1):
32
Jamie Iles (2):
20
exec: flush CPU TB cache in breakpoint_invalidate
33
cpu: expose qemu_cpu_list_lock for lock-guard use
34
accel/tcg/tcg-accel-ops-rr: ensure fairness with icount
21
35
22
Richard Henderson (1):
36
Richard Henderson (49):
23
tcg: Add tcg_gen_gvec_5_ptr
37
target/m68k: Fix gen_load_fp for OS_LONG
38
accel/tcg: Fix atomic_mmu_lookup for reads
39
disas: Fix tabs and braces in disas.c
40
disas: Move disas.c to disas/
41
disas: Remove target_ulong from the interface
42
disas: Remove target-specific headers
43
tcg/i386: Introduce prepare_host_addr
44
tcg/i386: Use indexed addressing for softmmu fast path
45
tcg/aarch64: Introduce prepare_host_addr
46
tcg/arm: Introduce prepare_host_addr
47
tcg/loongarch64: Introduce prepare_host_addr
48
tcg/mips: Introduce prepare_host_addr
49
tcg/ppc: Introduce prepare_host_addr
50
tcg/riscv: Introduce prepare_host_addr
51
tcg/s390x: Introduce prepare_host_addr
52
tcg: Add routines for calling slow-path helpers
53
tcg/i386: Convert tcg_out_qemu_ld_slow_path
54
tcg/i386: Convert tcg_out_qemu_st_slow_path
55
tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path
56
tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path
57
tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path
58
tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path
59
tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path
60
tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path
61
tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path
62
tcg/loongarch64: Simplify constraints on qemu_ld/st
63
tcg/mips: Remove MO_BSWAP handling
64
tcg/mips: Reorg tlb load within prepare_host_addr
65
tcg/mips: Simplify constraints on qemu_ld/st
66
tcg/ppc: Reorg tcg_out_tlb_read
67
tcg/ppc: Adjust constraints on qemu_ld/st
68
tcg/ppc: Remove unused constraints A, B, C, D
69
tcg/ppc: Remove unused constraint J
70
tcg/riscv: Simplify constraints on qemu_ld/st
71
tcg/s390x: Use ALGFR in constructing softmmu host address
72
tcg/s390x: Simplify constraints on qemu_ld/st
73
target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
74
target/mips: Add missing default_tcg_memop_mask
75
target/mips: Use MO_ALIGN instead of 0
76
target/mips: Remove TARGET_ALIGNED_ONLY
77
target/nios2: Remove TARGET_ALIGNED_ONLY
78
target/sh4: Use MO_ALIGN where required
79
target/sh4: Remove TARGET_ALIGNED_ONLY
80
tcg: Remove TARGET_ALIGNED_ONLY
81
accel/tcg: Add cpu_in_serial_context
82
accel/tcg: Introduce tlb_read_idx
83
accel/tcg: Reorg system mode load helpers
84
accel/tcg: Reorg system mode store helpers
85
target/loongarch: Do not include tcg-ldst.h
24
86
25
Taylor Simpson (1):
87
Thomas Huth (2):
26
tcg: Add support for a helper with 7 arguments
88
disas: Move softmmu specific code to separate file
89
disas: Move disas.c into the target-independent source set
27
90
28
include/exec/helper-gen.h | 13 +++++++++++++
91
configs/targets/mips-linux-user.mak | 1 -
29
include/exec/helper-head.h | 2 ++
92
configs/targets/mips-softmmu.mak | 1 -
30
include/exec/helper-proto.h | 6 ++++++
93
configs/targets/mips64-linux-user.mak | 1 -
31
include/exec/helper-tcg.h | 7 +++++++
94
configs/targets/mips64-softmmu.mak | 1 -
32
include/tcg/tcg-op-gvec.h | 7 +++++++
95
configs/targets/mips64el-linux-user.mak | 1 -
33
exec.c | 15 +++++++--------
96
configs/targets/mips64el-softmmu.mak | 1 -
34
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
97
configs/targets/mipsel-linux-user.mak | 1 -
35
7 files changed, 74 insertions(+), 8 deletions(-)
98
configs/targets/mipsel-softmmu.mak | 1 -
36
99
configs/targets/mipsn32-linux-user.mak | 1 -
100
configs/targets/mipsn32el-linux-user.mak | 1 -
101
configs/targets/nios2-softmmu.mak | 1 -
102
configs/targets/sh4-linux-user.mak | 1 -
103
configs/targets/sh4-softmmu.mak | 1 -
104
configs/targets/sh4eb-linux-user.mak | 1 -
105
configs/targets/sh4eb-softmmu.mak | 1 -
106
meson.build | 3 -
107
accel/tcg/internal.h | 9 +
108
accel/tcg/tcg-accel-ops-icount.h | 3 +-
109
disas/disas-internal.h | 21 +
110
include/disas/disas.h | 23 +-
111
include/exec/cpu-common.h | 1 +
112
include/exec/cpu-defs.h | 7 +-
113
include/exec/cpu_ldst.h | 26 +-
114
include/exec/memop.h | 13 +-
115
include/exec/poison.h | 1 -
116
tcg/loongarch64/tcg-target-con-set.h | 2 -
117
tcg/loongarch64/tcg-target-con-str.h | 1 -
118
tcg/mips/tcg-target-con-set.h | 13 +-
119
tcg/mips/tcg-target-con-str.h | 2 -
120
tcg/mips/tcg-target.h | 4 +-
121
tcg/ppc/tcg-target-con-set.h | 11 +-
122
tcg/ppc/tcg-target-con-str.h | 7 -
123
tcg/riscv/tcg-target-con-set.h | 2 -
124
tcg/riscv/tcg-target-con-str.h | 1 -
125
tcg/s390x/tcg-target-con-set.h | 2 -
126
tcg/s390x/tcg-target-con-str.h | 1 -
127
accel/tcg/cpu-exec-common.c | 3 +
128
accel/tcg/cputlb.c | 1113 ++++++++++++++++-------------
129
accel/tcg/tb-maint.c | 2 +-
130
accel/tcg/tcg-accel-ops-icount.c | 21 +-
131
accel/tcg/tcg-accel-ops-rr.c | 37 +-
132
bsd-user/elfload.c | 5 +-
133
cpus-common.c | 2 +-
134
disas/disas-mon.c | 65 ++
135
disas.c => disas/disas.c | 111 +--
136
linux-user/elfload.c | 18 +-
137
migration/dirtyrate.c | 26 +-
138
replay/replay.c | 3 +-
139
target/loongarch/csr_helper.c | 1 -
140
target/loongarch/iocsr_helper.c | 1 -
141
target/m68k/translate.c | 1 +
142
target/mips/tcg/mxu_translate.c | 3 +-
143
target/nios2/translate.c | 10 +
144
target/sh4/translate.c | 102 ++-
145
tcg/tcg.c | 480 ++++++++++++-
146
trace/control-target.c | 9 +-
147
target/mips/tcg/micromips_translate.c.inc | 24 +-
148
target/mips/tcg/mips16e_translate.c.inc | 18 +-
149
target/mips/tcg/nanomips_translate.c.inc | 32 +-
150
tcg/aarch64/tcg-target.c.inc | 347 ++++-----
151
tcg/arm/tcg-target.c.inc | 455 +++++-------
152
tcg/i386/tcg-target.c.inc | 453 +++++-------
153
tcg/loongarch64/tcg-target.c.inc | 313 +++-----
154
tcg/mips/tcg-target.c.inc | 870 +++++++---------------
155
tcg/ppc/tcg-target.c.inc | 512 ++++++-------
156
tcg/riscv/tcg-target.c.inc | 304 ++++----
157
tcg/s390x/tcg-target.c.inc | 314 ++++----
158
disas/meson.build | 6 +-
159
68 files changed, 2789 insertions(+), 3040 deletions(-)
160
create mode 100644 disas/disas-internal.h
161
create mode 100644 disas/disas-mon.c
162
rename disas.c => disas/disas.c (78%)
diff view generated by jsdifflib
[PULL 1/3] exec: flush CPU TB cache in breakpoint_invalidate
Deleted patch
1
From: Max Filippov <jcmvbkbc@gmail.com>
2
1
3
When a breakpoint is inserted at location for which there's currently no
4
virtual to physical translation no action is taken on CPU TB cache. If a
5
TB for that virtual address already exists but is not visible ATM the
6
breakpoint won't be hit next time an instruction at that address will be
7
executed.
8
9
Flush entire CPU TB cache in breakpoint_invalidate to force
10
re-translation of all TBs for the breakpoint address.
11
12
This change fixes the following scenario:
13
- linux user application is running
14
- a breakpoint is inserted from QEMU gdbstub for a user address that is
15
not currently present in the target CPU TLB
16
- an instruction at that address is executed, but the external debugger
17
doesn't get control.
18
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
21
Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
24
exec.c | 15 +++++++--------
25
1 file changed, 7 insertions(+), 8 deletions(-)
26
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
32
33
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
34
{
35
- MemTxAttrs attrs;
36
- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
37
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
38
- if (phys != -1) {
39
- /* Locks grabbed by tb_invalidate_phys_addr */
40
- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
41
- phys | (pc & ~TARGET_PAGE_MASK), attrs);
42
- }
43
+ /*
44
+ * There may not be a virtual to physical translation for the pc
45
+ * right now, but there may exist cached TB for this pc.
46
+ * Flush the whole TB cache to force re-translation of such TBs.
47
+ * This is heavyweight, but we're debugging anyway.
48
+ */
49
+ tb_flush(cpu);
50
}
51
#endif
52
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
[PULL 2/3] tcg: Add support for a helper with 7 arguments
Deleted patch
1
From: Taylor Simpson <tsimpson@quicinc.com>
2
1
3
Currently, helpers can only take up to 6 arguments. This patch adds the
4
capability for up to 7 arguments. I have tested it with the Hexagon port
5
that I am preparing for submission.
6
7
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
8
Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/helper-gen.h | 13 +++++++++++++
12
include/exec/helper-head.h | 2 ++
13
include/exec/helper-proto.h | 6 ++++++
14
include/exec/helper-tcg.h | 7 +++++++
15
4 files changed, 28 insertions(+)
16
17
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/helper-gen.h
20
+++ b/include/exec/helper-gen.h
21
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
22
tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
23
}
24
25
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
26
+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
27
+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
28
+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
29
+ dh_arg_decl(t7, 7)) \
30
+{ \
31
+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
32
+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
33
+ dh_arg(t7, 7) }; \
34
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
35
+}
36
+
37
#include "helper.h"
38
#include "trace/generated-helpers.h"
39
#include "trace/generated-helpers-wrappers.h"
40
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
41
#undef DEF_HELPER_FLAGS_4
42
#undef DEF_HELPER_FLAGS_5
43
#undef DEF_HELPER_FLAGS_6
44
+#undef DEF_HELPER_FLAGS_7
45
#undef GEN_HELPER
46
47
#endif /* HELPER_GEN_H */
48
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/helper-head.h
51
+++ b/include/exec/helper-head.h
52
@@ -XXX,XX +XXX,XX @@
53
DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
54
#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
55
DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
56
+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
57
+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
58
59
/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
60
61
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/exec/helper-proto.h
64
+++ b/include/exec/helper-proto.h
65
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
66
dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
68
69
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
70
+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
71
+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
72
+ dh_ctype(t7));
73
+
74
#include "helper.h"
75
#include "trace/generated-helpers.h"
76
#include "tcg-runtime.h"
77
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
78
#undef DEF_HELPER_FLAGS_4
79
#undef DEF_HELPER_FLAGS_5
80
#undef DEF_HELPER_FLAGS_6
81
+#undef DEF_HELPER_FLAGS_7
82
83
#endif /* HELPER_PROTO_H */
84
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/exec/helper-tcg.h
87
+++ b/include/exec/helper-tcg.h
88
@@ -XXX,XX +XXX,XX @@
89
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
90
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
91
92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
93
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
94
+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
95
+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
96
+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
97
+
98
#include "helper.h"
99
#include "trace/generated-helpers.h"
100
#include "tcg-runtime.h"
101
@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
104
#undef DEF_HELPER_FLAGS_6
105
+#undef DEF_HELPER_FLAGS_7
106
107
#endif /* HELPER_TCG_H */
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_gvec_5_ptr
[PULL v2 08/53] disas: Move disas.c into the target-independent source set
1
Extend the vector generator infrastructure to handle
1
From: Thomas Huth <thuth@redhat.com>
2
5 vector arguments.
3
2
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Use target_words_bigendian() instead of an ifdef.
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
6
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
5
Remove CONFIG_RISCV_DIS from the check for riscv as a host; this is
6
a poisoned identifier, and anyway will always be set by meson.build
7
when building on a riscv host.
8
9
Signed-off-by: Thomas Huth <thuth@redhat.com>
10
Message-Id: <20230508133745.109463-3-thuth@redhat.com>
11
[rth: Type change done in a separate patch]
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
13
---
9
include/tcg/tcg-op-gvec.h | 7 +++++++
14
disas/disas.c | 12 ++++++------
10
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
15
disas/meson.build | 3 ++-
11
2 files changed, 39 insertions(+)
16
2 files changed, 8 insertions(+), 7 deletions(-)
12
17
13
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
18
diff --git a/disas/disas.c b/disas/disas.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/include/tcg/tcg-op-gvec.h
20
--- a/disas/disas.c
16
+++ b/include/tcg/tcg-op-gvec.h
21
+++ b/disas/disas.c
17
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
22
@@ -XXX,XX +XXX,XX @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
18
uint32_t maxsz, int32_t data,
23
s->cpu = cpu;
19
gen_helper_gvec_4_ptr *fn);
24
s->info.read_memory_func = target_read_memory;
20
25
s->info.print_address_func = print_address;
21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
26
-#if TARGET_BIG_ENDIAN
22
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
27
- s->info.endian = BFD_ENDIAN_BIG;
23
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
28
-#else
24
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
29
- s->info.endian = BFD_ENDIAN_LITTLE;
25
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
30
-#endif
26
+ gen_helper_gvec_5_ptr *fn);
31
+ if (target_words_bigendian()) {
27
+
32
+ s->info.endian = BFD_ENDIAN_BIG;
28
/* Expand a gvec operation. Either inline or out-of-line depending on
33
+ } else {
29
the actual vector size and the operations supported by the host. */
34
+ s->info.endian = BFD_ENDIAN_LITTLE;
30
typedef struct {
35
+ }
31
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
36
37
CPUClass *cc = CPU_GET_CLASS(cpu);
38
if (cc->disas_set_info) {
39
@@ -XXX,XX +XXX,XX @@ static void initialize_debug_host(CPUDebug *s)
40
# ifdef _ARCH_PPC64
41
s->info.cap_mode = CS_MODE_64;
42
# endif
43
-#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
44
+#elif defined(__riscv)
45
#if defined(_ILP32) || (__riscv_xlen == 32)
46
s->info.print_insn = print_insn_riscv32;
47
#elif defined(_LP64)
48
diff --git a/disas/meson.build b/disas/meson.build
32
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg-op-gvec.c
50
--- a/disas/meson.build
34
+++ b/tcg/tcg-op-gvec.c
51
+++ b/disas/meson.build
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
52
@@ -XXX,XX +XXX,XX @@ common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
36
tcg_temp_free_i32(desc);
53
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
37
}
54
common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
38
55
common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
39
+/* Generate a call to a gvec-style helper with five vector operands
56
+common_ss.add(files('disas.c'))
40
+ and an extra pointer operand. */
57
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
58
softmmu_ss.add(files('disas-mon.c'))
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
59
-specific_ss.add(files('disas.c'), capstone)
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
60
+specific_ss.add(capstone)
44
+ gen_helper_gvec_5_ptr *fn)
45
+{
46
+ TCGv_ptr a0, a1, a2, a3, a4;
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
48
+
49
+ a0 = tcg_temp_new_ptr();
50
+ a1 = tcg_temp_new_ptr();
51
+ a2 = tcg_temp_new_ptr();
52
+ a3 = tcg_temp_new_ptr();
53
+ a4 = tcg_temp_new_ptr();
54
+
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
56
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
57
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
58
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
59
+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
60
+
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
62
+
63
+ tcg_temp_free_ptr(a0);
64
+ tcg_temp_free_ptr(a1);
65
+ tcg_temp_free_ptr(a2);
66
+ tcg_temp_free_ptr(a3);
67
+ tcg_temp_free_ptr(a4);
68
+ tcg_temp_free_i32(desc);
69
+}
70
+
71
/* Return true if we want to implement something of OPRSZ bytes
72
in units of LNSZ. This limits the expansion of inline code. */
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
74
--
61
--
75
2.20.1
62
2.34.1
76
77
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Patchew 2.1-devel-b67e4c2

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