[PULL 0/3] tcg patch queue
[PULL v3 00/91] tcg patch queue
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The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
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Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
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Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
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r~
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The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
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Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
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14
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for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
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for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
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tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
17
tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
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13
----------------------------------------------------------------
19
----------------------------------------------------------------
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Fix breakpoint invalidation.
20
accel/tcg: Fix NB_MMU_MODES to 16
15
Add support for tcg helpers with 7 arguments.
21
Balance of the target/ patchset which eliminates tcg_temp_free
16
Add support for gvec helpers with 5 arguments.
22
Balance of the target/ patchset which eliminates tcg_const
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----------------------------------------------------------------
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----------------------------------------------------------------
19
Max Filippov (1):
25
Anton Johansson (23):
20
exec: flush CPU TB cache in breakpoint_invalidate
26
include/exec: Set default `NB_MMU_MODES` to 16
27
target/alpha: Remove `NB_MMU_MODES` define
28
target/arm: Remove `NB_MMU_MODES` define
29
target/avr: Remove `NB_MMU_MODES` define
30
target/cris: Remove `NB_MMU_MODES` define
31
target/hexagon: Remove `NB_MMU_MODES` define
32
target/hppa: Remove `NB_MMU_MODES` define
33
target/i386: Remove `NB_MMU_MODES` define
34
target/loongarch: Remove `NB_MMU_MODES` define
35
target/m68k: Remove `NB_MMU_MODES` define
36
target/microblaze: Remove `NB_MMU_MODES` define
37
target/mips: Remove `NB_MMU_MODES` define
38
target/nios2: Remove `NB_MMU_MODES` define
39
target/openrisc: Remove `NB_MMU_MODES` define
40
target/ppc: Remove `NB_MMU_MODES` define
41
target/riscv: Remove `NB_MMU_MODES` define
42
target/rx: Remove `NB_MMU_MODES` define
43
target/s390x: Remove `NB_MMU_MODES` define
44
target/sh4: Remove `NB_MMU_MODES` define
45
target/sparc: Remove `NB_MMU_MODES` define
46
target/tricore: Remove `NB_MMU_MODES` define
47
target/xtensa: Remove `NB_MMU_MODES` define
48
include/exec: Remove guards around `NB_MMU_MODES`
21
49
22
Richard Henderson (1):
50
Richard Henderson (68):
23
tcg: Add tcg_gen_gvec_5_ptr
51
target/mips: Drop tcg_temp_free from micromips_translate.c.inc
52
target/mips: Drop tcg_temp_free from msa_translate.c
53
target/mips: Drop tcg_temp_free from mxu_translate.c
54
target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
55
target/mips: Drop tcg_temp_free from octeon_translate.c
56
target/mips: Drop tcg_temp_free from translate_addr_const.c
57
target/mips: Drop tcg_temp_free from tx79_translate.c
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target/mips: Drop tcg_temp_free from vr54xx_translate.c
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target/mips: Drop tcg_temp_free from translate.c
60
target/s390x: Drop free_compare
61
target/s390x: Drop tcg_temp_free from translate_vx.c.inc
62
target/s390x: Drop tcg_temp_free from translate.c
63
target/s390x: Remove assert vs g_in2
64
target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
65
tcg: Create tcg/tcg-temp-internal.h
66
target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
67
target/avr: Avoid use of tcg_const_i32 throughout
68
target/cris: Avoid use of tcg_const_i32 throughout
69
target/hppa: Avoid tcg_const_i64 in trans_fid_f
70
target/hppa: Avoid use of tcg_const_i32 throughout
71
target/i386: Avoid use of tcg_const_* throughout
72
target/m68k: Avoid tcg_const_i32 when modified
73
target/m68k: Avoid tcg_const_i32 in bfop_reg
74
target/m68k: Avoid tcg_const_* throughout
75
target/mips: Split out gen_lxl
76
target/mips: Split out gen_lxr
77
target/mips: Avoid tcg_const_tl in gen_r6_ld
78
target/mips: Avoid tcg_const_* throughout
79
target/ppc: Split out gen_vx_vmul10
80
target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
81
target/rx: Use tcg_gen_abs_i32
82
target/rx: Use cpu_psw_z as temp in flags computation
83
target/rx: Avoid tcg_const_i32 when new temp needed
84
target/rx: Avoid tcg_const_i32
85
target/s390x: Avoid tcg_const_i64
86
target/sh4: Avoid tcg_const_i32 for TAS.B
87
target/sh4: Avoid tcg_const_i32
88
tcg/sparc: Avoid tcg_const_tl in gen_edge
89
target/tricore: Split t_n as constant from temp as variable
90
target/tricore: Rename t_off10 and use tcg_constant_i32
91
target/tricore: Use setcondi instead of explicit allocation
92
target/tricore: Drop some temp initialization
93
target/tricore: Avoid tcg_const_i32
94
tcg: Replace tcg_const_i64 in tcg-op.c
95
target/arm: Use rmode >= 0 for need_rmode
96
target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
97
target/arm: Improve arm_rmode_to_sf
98
target/arm: Consistently use ARMFPRounding during translation
99
target/arm: Create gen_set_rmode, gen_restore_rmode
100
target/arm: Improve trans_BFCI
101
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
102
target/arm: Avoid tcg_const_* in translate-mve.c
103
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
104
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
105
target/arm: Avoid tcg_const_ptr in handle_rev
106
target/m68k: Use tcg_constant_i32 in gen_ea_mode
107
target/ppc: Avoid tcg_const_i64 in do_vcntmb
108
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
109
target/ppc: Avoid tcg_const_* in xxeval
110
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
111
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
112
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
113
target/ppc: Rewrite trans_ADDG6S
114
target/ppc: Fix gen_tlbsx_booke206
115
target/ppc: Avoid tcg_const_* in translate.c
116
target/tricore: Use min/max for saturate
117
tcg: Drop tcg_const_*_vec
118
tcg: Drop tcg_const_*
24
119
25
Taylor Simpson (1):
120
include/exec/cpu-defs.h | 9 +-
26
tcg: Add support for a helper with 7 arguments
121
include/tcg/tcg-op.h | 4 -
27
122
include/tcg/tcg-temp-internal.h | 83 +++
28
include/exec/helper-gen.h | 13 +++++++++++++
123
include/tcg/tcg.h | 64 ---
29
include/exec/helper-head.h | 2 ++
124
target/alpha/cpu-param.h | 2 -
30
include/exec/helper-proto.h | 6 ++++++
125
target/arm/cpu-param.h | 2 -
31
include/exec/helper-tcg.h | 7 +++++++
126
target/arm/internals.h | 12 +-
32
include/tcg/tcg-op-gvec.h | 7 +++++++
127
target/arm/tcg/translate.h | 17 +
33
exec.c | 15 +++++++--------
128
target/avr/cpu-param.h | 1 -
34
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
129
target/cris/cpu-param.h | 1 -
35
7 files changed, 74 insertions(+), 8 deletions(-)
130
target/hexagon/cpu-param.h | 2 -
36
131
target/hppa/cpu-param.h | 1 -
132
target/i386/cpu-param.h | 1 -
133
target/loongarch/cpu-param.h | 1 -
134
target/m68k/cpu-param.h | 1 -
135
target/microblaze/cpu-param.h | 1 -
136
target/microblaze/cpu.h | 2 +-
137
target/mips/cpu-param.h | 1 -
138
target/nios2/cpu-param.h | 1 -
139
target/openrisc/cpu-param.h | 1 -
140
target/ppc/cpu-param.h | 1 -
141
target/riscv/cpu-param.h | 1 -
142
target/rx/cpu-param.h | 2 -
143
target/s390x/cpu-param.h | 1 -
144
target/sh4/cpu-param.h | 1 -
145
target/sparc/cpu-param.h | 2 -
146
target/tricore/cpu-param.h | 1 -
147
target/xtensa/cpu-param.h | 1 -
148
accel/tcg/plugin-gen.c | 1 +
149
target/arm/tcg/translate-a64.c | 168 +++---
150
target/arm/tcg/translate-mve.c | 56 +-
151
target/arm/tcg/translate-sve.c | 28 +-
152
target/arm/tcg/translate-vfp.c | 26 +-
153
target/arm/tcg/translate.c | 14 +-
154
target/arm/vfp_helper.c | 35 +-
155
target/avr/translate.c | 48 +-
156
target/cris/translate.c | 46 +-
157
target/hppa/translate.c | 35 +-
158
target/i386/tcg/translate.c | 83 +--
159
target/m68k/translate.c | 231 ++++----
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target/mips/tcg/msa_translate.c | 9 -
161
target/mips/tcg/mxu_translate.c | 55 +-
162
target/mips/tcg/octeon_translate.c | 23 -
163
target/mips/tcg/translate.c | 819 +++++------------------------
164
target/mips/tcg/translate_addr_const.c | 7 -
165
target/mips/tcg/tx79_translate.c | 45 +-
166
target/mips/tcg/vr54xx_translate.c | 4 -
167
target/ppc/translate.c | 148 +++---
168
target/rx/translate.c | 84 ++-
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target/s390x/tcg/translate.c | 208 +-------
170
target/sh4/translate.c | 35 +-
171
target/sparc/translate.c | 14 +-
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target/tricore/translate.c | 476 ++++++++---------
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tcg/tcg-op-gvec.c | 1 +
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tcg/tcg-op-vec.c | 35 +-
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tcg/tcg-op.c | 13 +-
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tcg/tcg.c | 17 +-
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target/cris/translate_v10.c.inc | 26 +-
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target/mips/tcg/micromips_translate.c.inc | 12 +-
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target/mips/tcg/nanomips_translate.c.inc | 143 +----
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target/ppc/power8-pmu-regs.c.inc | 4 +-
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target/ppc/translate/fixedpoint-impl.c.inc | 44 +-
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target/ppc/translate/fp-impl.c.inc | 26 +-
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target/ppc/translate/vmx-impl.c.inc | 130 ++---
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target/ppc/translate/vsx-impl.c.inc | 36 +-
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target/s390x/tcg/translate_vx.c.inc | 143 -----
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tcg/i386/tcg-target.c.inc | 9 +-
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67 files changed, 1166 insertions(+), 2388 deletions(-)
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create mode 100644 include/tcg/tcg-temp-internal.h
diff view generated by jsdifflib
[PULL 1/3] exec: flush CPU TB cache in breakpoint_invalidate
Deleted patch
1
From: Max Filippov <jcmvbkbc@gmail.com>
2
1
3
When a breakpoint is inserted at location for which there's currently no
4
virtual to physical translation no action is taken on CPU TB cache. If a
5
TB for that virtual address already exists but is not visible ATM the
6
breakpoint won't be hit next time an instruction at that address will be
7
executed.
8
9
Flush entire CPU TB cache in breakpoint_invalidate to force
10
re-translation of all TBs for the breakpoint address.
11
12
This change fixes the following scenario:
13
- linux user application is running
14
- a breakpoint is inserted from QEMU gdbstub for a user address that is
15
not currently present in the target CPU TLB
16
- an instruction at that address is executed, but the external debugger
17
doesn't get control.
18
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
21
Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
24
exec.c | 15 +++++++--------
25
1 file changed, 7 insertions(+), 8 deletions(-)
26
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
32
33
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
34
{
35
- MemTxAttrs attrs;
36
- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
37
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
38
- if (phys != -1) {
39
- /* Locks grabbed by tb_invalidate_phys_addr */
40
- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
41
- phys | (pc & ~TARGET_PAGE_MASK), attrs);
42
- }
43
+ /*
44
+ * There may not be a virtual to physical translation for the pc
45
+ * right now, but there may exist cached TB for this pc.
46
+ * Flush the whole TB cache to force re-translation of such TBs.
47
+ * This is heavyweight, but we're debugging anyway.
48
+ */
49
+ tb_flush(cpu);
50
}
51
#endif
52
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
[PULL 2/3] tcg: Add support for a helper with 7 arguments
Deleted patch
1
From: Taylor Simpson <tsimpson@quicinc.com>
2
1
3
Currently, helpers can only take up to 6 arguments. This patch adds the
4
capability for up to 7 arguments. I have tested it with the Hexagon port
5
that I am preparing for submission.
6
7
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
8
Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/helper-gen.h | 13 +++++++++++++
12
include/exec/helper-head.h | 2 ++
13
include/exec/helper-proto.h | 6 ++++++
14
include/exec/helper-tcg.h | 7 +++++++
15
4 files changed, 28 insertions(+)
16
17
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/helper-gen.h
20
+++ b/include/exec/helper-gen.h
21
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
22
tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
23
}
24
25
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
26
+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
27
+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
28
+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
29
+ dh_arg_decl(t7, 7)) \
30
+{ \
31
+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
32
+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
33
+ dh_arg(t7, 7) }; \
34
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
35
+}
36
+
37
#include "helper.h"
38
#include "trace/generated-helpers.h"
39
#include "trace/generated-helpers-wrappers.h"
40
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
41
#undef DEF_HELPER_FLAGS_4
42
#undef DEF_HELPER_FLAGS_5
43
#undef DEF_HELPER_FLAGS_6
44
+#undef DEF_HELPER_FLAGS_7
45
#undef GEN_HELPER
46
47
#endif /* HELPER_GEN_H */
48
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/helper-head.h
51
+++ b/include/exec/helper-head.h
52
@@ -XXX,XX +XXX,XX @@
53
DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
54
#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
55
DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
56
+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
57
+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
58
59
/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
60
61
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/exec/helper-proto.h
64
+++ b/include/exec/helper-proto.h
65
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
66
dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
68
69
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
70
+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
71
+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
72
+ dh_ctype(t7));
73
+
74
#include "helper.h"
75
#include "trace/generated-helpers.h"
76
#include "tcg-runtime.h"
77
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
78
#undef DEF_HELPER_FLAGS_4
79
#undef DEF_HELPER_FLAGS_5
80
#undef DEF_HELPER_FLAGS_6
81
+#undef DEF_HELPER_FLAGS_7
82
83
#endif /* HELPER_PROTO_H */
84
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/exec/helper-tcg.h
87
+++ b/include/exec/helper-tcg.h
88
@@ -XXX,XX +XXX,XX @@
89
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
90
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
91
92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
93
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
94
+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
95
+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
96
+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
97
+
98
#include "helper.h"
99
#include "trace/generated-helpers.h"
100
#include "tcg-runtime.h"
101
@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
104
#undef DEF_HELPER_FLAGS_6
105
+#undef DEF_HELPER_FLAGS_7
106
107
#endif /* HELPER_TCG_H */
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_gvec_5_ptr
[PULL v3 73/91] target/arm: Improve trans_BFCI
1
Extend the vector generator infrastructure to handle
1
Reorg temporary usage so that we can use tcg_constant_i32.
2
5 vector arguments.
2
tcg_gen_deposit_i32 already has a width == 32 special case,
3
so remove the check here.
3
4
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
7
---
9
include/tcg/tcg-op-gvec.h | 7 +++++++
8
target/arm/tcg/translate.c | 14 ++++++--------
10
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
9
1 file changed, 6 insertions(+), 8 deletions(-)
11
2 files changed, 39 insertions(+)
12
10
13
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
11
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/include/tcg/tcg-op-gvec.h
13
--- a/target/arm/tcg/translate.c
16
+++ b/include/tcg/tcg-op-gvec.h
14
+++ b/target/arm/tcg/translate.c
17
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
15
@@ -XXX,XX +XXX,XX @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
18
uint32_t maxsz, int32_t data,
16
19
gen_helper_gvec_4_ptr *fn);
17
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
20
18
{
21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
19
- TCGv_i32 tmp;
22
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
20
int msb = a->msb, lsb = a->lsb;
23
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
21
+ TCGv_i32 t_in, t_rd;
24
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
22
int width;
25
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
23
26
+ gen_helper_gvec_5_ptr *fn);
24
if (!ENABLE_ARCH_6T2) {
27
+
25
@@ -XXX,XX +XXX,XX @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
28
/* Expand a gvec operation. Either inline or out-of-line depending on
26
width = msb + 1 - lsb;
29
the actual vector size and the operations supported by the host. */
27
if (a->rn == 15) {
30
typedef struct {
28
/* BFC */
31
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
29
- tmp = tcg_const_i32(0);
32
index XXXXXXX..XXXXXXX 100644
30
+ t_in = tcg_constant_i32(0);
33
--- a/tcg/tcg-op-gvec.c
31
} else {
34
+++ b/tcg/tcg-op-gvec.c
32
/* BFI */
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
33
- tmp = load_reg(s, a->rn);
36
tcg_temp_free_i32(desc);
34
+ t_in = load_reg(s, a->rn);
35
}
36
- if (width != 32) {
37
- TCGv_i32 tmp2 = load_reg(s, a->rd);
38
- tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
39
- }
40
- store_reg(s, a->rd, tmp);
41
+ t_rd = load_reg(s, a->rd);
42
+ tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
43
+ store_reg(s, a->rd, t_rd);
44
return true;
37
}
45
}
38
46
39
+/* Generate a call to a gvec-style helper with five vector operands
40
+ and an extra pointer operand. */
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
44
+ gen_helper_gvec_5_ptr *fn)
45
+{
46
+ TCGv_ptr a0, a1, a2, a3, a4;
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
48
+
49
+ a0 = tcg_temp_new_ptr();
50
+ a1 = tcg_temp_new_ptr();
51
+ a2 = tcg_temp_new_ptr();
52
+ a3 = tcg_temp_new_ptr();
53
+ a4 = tcg_temp_new_ptr();
54
+
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
56
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
57
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
58
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
59
+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
60
+
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
62
+
63
+ tcg_temp_free_ptr(a0);
64
+ tcg_temp_free_ptr(a1);
65
+ tcg_temp_free_ptr(a2);
66
+ tcg_temp_free_ptr(a3);
67
+ tcg_temp_free_ptr(a4);
68
+ tcg_temp_free_i32(desc);
69
+}
70
+
71
/* Return true if we want to implement something of OPRSZ bytes
72
in units of LNSZ. This limits the expansion of inline code. */
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
74
--
47
--
75
2.20.1
48
2.34.1
76
49
77
50
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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