[PULL 0/3] tcg patch queue
[PULL v2 00/62] tcg patch queue
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The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
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v2: Fix mis-attributed --author.
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Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
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r~
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The following changes since commit 627634031092e1514f363fd8659a579398de0f0e:
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Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging (2023-02-28 15:09:18 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230301
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for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
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for you to fetch changes up to 9644e7142a2a2bb4b4743a3a4c940edbab16ca11:
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tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
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tcg: Update docs/devel/tcg-ops.rst for temporary changes (2023-03-01 07:33:28 -1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Fix breakpoint invalidation.
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helper-head: Add fpu/softfloat-types.h
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Add support for tcg helpers with 7 arguments.
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softmmu: Use memmove in flatview_write_continue
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Add support for gvec helpers with 5 arguments.
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tcg: Add sign param to probe_access_flags, probe_access_full
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tcg: Convert TARGET_TB_PCREL to CF_PCREL
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tcg: Simplify temporary lifetimes for translators
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----------------------------------------------------------------
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----------------------------------------------------------------
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Max Filippov (1):
27
Akihiko Odaki (1):
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exec: flush CPU TB cache in breakpoint_invalidate
28
softmmu: Use memmove in flatview_write_continue
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29
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Richard Henderson (1):
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Anton Johansson (27):
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tcg: Add tcg_gen_gvec_5_ptr
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include/exec: Introduce `CF_PCREL`
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target/i386: set `CF_PCREL` in `x86_cpu_realizefn`
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target/arm: set `CF_PCREL` in `arm_cpu_realizefn`
34
accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL`
35
include/exec: Replace `TARGET_TB_PCREL` with `CF_PCREL`
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target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL`
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target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`
38
include/exec: Remove `TARGET_TB_PCREL` define
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target/arm: Remove `TARGET_TB_PCREL` define
40
target/i386: Remove `TARGET_TB_PCREL` define
41
accel/tcg: Move jmp-cache `CF_PCREL` checks to caller
42
accel/tcg: Replace `tb_pc()` with `tb->pc`
43
target/tricore: Replace `tb_pc()` with `tb->pc`
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target/sparc: Replace `tb_pc()` with `tb->pc`
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target/sh4: Replace `tb_pc()` with `tb->pc`
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target/rx: Replace `tb_pc()` with `tb->pc`
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target/riscv: Replace `tb_pc()` with `tb->pc`
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target/openrisc: Replace `tb_pc()` with `tb->pc`
49
target/mips: Replace `tb_pc()` with `tb->pc`
50
target/microblaze: Replace `tb_pc()` with `tb->pc`
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target/loongarch: Replace `tb_pc()` with `tb->pc`
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target/i386: Replace `tb_pc()` with `tb->pc`
53
target/hppa: Replace `tb_pc()` with `tb->pc`
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target/hexagon: Replace `tb_pc()` with `tb->pc`
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target/avr: Replace `tb_pc()` with `tb->pc`
56
target/arm: Replace `tb_pc()` with `tb->pc`
57
include/exec: Remove `tb_pc()`
24
58
25
Taylor Simpson (1):
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Daniel Henrique Barboza (1):
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tcg: Add support for a helper with 7 arguments
60
accel/tcg: Add 'size' param to probe_access_flags()
27
61
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include/exec/helper-gen.h | 13 +++++++++++++
62
Philippe Mathieu-Daudé (1):
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include/exec/helper-head.h | 2 ++
63
exec/helper-head: Include missing "fpu/softfloat-types.h" header
30
include/exec/helper-proto.h | 6 ++++++
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include/exec/helper-tcg.h | 7 +++++++
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include/tcg/tcg-op-gvec.h | 7 +++++++
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exec.c | 15 +++++++--------
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tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
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7 files changed, 74 insertions(+), 8 deletions(-)
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64
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Richard Henderson (32):
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accel/tcg: Add 'size' param to probe_access_full
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tcg: Adjust TCGContext.temps_in_use check
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accel/tcg: Pass max_insn to gen_intermediate_code by pointer
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accel/tcg: Use more accurate max_insns for tb_overflow
70
tcg: Remove branch-to-next regardless of reference count
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tcg: Rename TEMP_LOCAL to TEMP_TB
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tcg: Use noinline for major tcg_gen_code subroutines
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tcg: Add liveness_pass_0
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tcg: Remove TEMP_NORMAL
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tcg: Pass TCGTempKind to tcg_temp_new_internal
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tcg: Use tcg_constant_i32 in tcg_gen_io_start
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tcg: Add tcg_gen_movi_ptr
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tcg: Add tcg_temp_ebb_new_{i32,i64,ptr}
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tcg: Use tcg_temp_ebb_new_* in tcg/
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tcg: Use tcg_constant_ptr in do_dup
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accel/tcg/plugin: Use tcg_temp_ebb_*
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accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers
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tcg: Don't re-use TEMP_TB temporaries
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tcg: Change default temp lifetime to TEMP_TB
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target/arm: Drop copies in gen_sve_{ldr,str}
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target/arm: Don't use tcg_temp_local_new_*
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target/cris: Don't use tcg_temp_local_new
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target/hexagon: Don't use tcg_temp_local_new_*
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target/hexagon/idef-parser: Drop gen_tmp_local
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target/hppa: Don't use tcg_temp_local_new
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target/i386: Don't use tcg_temp_local_new
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target/mips: Don't use tcg_temp_local_new
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target/ppc: Don't use tcg_temp_local_new
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target/xtensa: Don't use tcg_temp_local_new_*
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exec/gen-icount: Don't use tcg_temp_local_new_i32
96
tcg: Remove tcg_temp_local_new_*, tcg_const_local_*
97
tcg: Update docs/devel/tcg-ops.rst for temporary changes
98
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docs/devel/tcg-ops.rst | 230 +++++++++++++----------
100
target/hexagon/idef-parser/README.rst | 4 +-
101
accel/tcg/internal.h | 10 +-
102
accel/tcg/tb-jmp-cache.h | 42 +----
103
include/exec/cpu-defs.h | 3 -
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include/exec/exec-all.h | 26 +--
105
include/exec/gen-icount.h | 12 +-
106
include/exec/helper-head.h | 2 +
107
include/exec/translator.h | 4 +-
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include/tcg/tcg-op.h | 7 +-
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include/tcg/tcg.h | 64 ++++---
110
target/arm/cpu-param.h | 2 -
111
target/arm/tcg/translate-a64.h | 1 -
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target/arm/tcg/translate.h | 2 +-
113
target/hexagon/gen_tcg.h | 4 +-
114
target/i386/cpu-param.h | 4 -
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accel/stubs/tcg-stub.c | 2 +-
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accel/tcg/cpu-exec.c | 62 ++++--
117
accel/tcg/cputlb.c | 21 ++-
118
accel/tcg/perf.c | 2 +-
119
accel/tcg/plugin-gen.c | 32 ++--
120
accel/tcg/tb-maint.c | 10 +-
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accel/tcg/translate-all.c | 18 +-
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accel/tcg/translator.c | 6 +-
123
accel/tcg/user-exec.c | 5 +-
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semihosting/uaccess.c | 2 +-
125
softmmu/physmem.c | 2 +-
126
target/alpha/translate.c | 2 +-
127
target/arm/cpu.c | 17 +-
128
target/arm/ptw.c | 4 +-
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target/arm/tcg/mte_helper.c | 4 +-
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target/arm/tcg/sve_helper.c | 4 +-
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target/arm/tcg/translate-a64.c | 16 +-
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target/arm/tcg/translate-sve.c | 38 +---
133
target/arm/tcg/translate.c | 14 +-
134
target/avr/cpu.c | 3 +-
135
target/avr/translate.c | 2 +-
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target/cris/translate.c | 8 +-
137
target/hexagon/cpu.c | 4 +-
138
target/hexagon/genptr.c | 16 +-
139
target/hexagon/idef-parser/parser-helpers.c | 26 +--
140
target/hexagon/translate.c | 4 +-
141
target/hppa/cpu.c | 8 +-
142
target/hppa/translate.c | 5 +-
143
target/i386/cpu.c | 5 +
144
target/i386/helper.c | 2 +-
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target/i386/tcg/sysemu/excp_helper.c | 4 +-
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target/i386/tcg/tcg-cpu.c | 8 +-
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target/i386/tcg/translate.c | 55 +++---
148
target/loongarch/cpu.c | 6 +-
149
target/loongarch/translate.c | 2 +-
150
target/m68k/translate.c | 2 +-
151
target/microblaze/cpu.c | 4 +-
152
target/microblaze/translate.c | 2 +-
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target/mips/tcg/exception.c | 3 +-
154
target/mips/tcg/sysemu/special_helper.c | 2 +-
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target/mips/tcg/translate.c | 59 ++----
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target/nios2/translate.c | 2 +-
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target/openrisc/cpu.c | 4 +-
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target/openrisc/translate.c | 2 +-
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target/ppc/translate.c | 8 +-
160
target/riscv/cpu.c | 7 +-
161
target/riscv/translate.c | 2 +-
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target/rx/cpu.c | 3 +-
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target/rx/translate.c | 2 +-
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target/s390x/tcg/mem_helper.c | 2 +-
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target/s390x/tcg/translate.c | 2 +-
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target/sh4/cpu.c | 6 +-
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target/sh4/translate.c | 2 +-
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target/sparc/cpu.c | 4 +-
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target/sparc/translate.c | 2 +-
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target/tricore/cpu.c | 3 +-
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target/tricore/translate.c | 2 +-
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target/xtensa/translate.c | 18 +-
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tcg/optimize.c | 2 +-
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tcg/tcg-op-gvec.c | 189 ++++++++++---------
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tcg/tcg-op.c | 258 ++++++++++++-------------
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tcg/tcg.c | 280 ++++++++++++++++------------
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target/cris/translate_v10.c.inc | 10 +-
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target/mips/tcg/nanomips_translate.c.inc | 4 +-
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target/ppc/translate/spe-impl.c.inc | 8 +-
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target/ppc/translate/vmx-impl.c.inc | 4 +-
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target/hexagon/README | 8 +-
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target/hexagon/gen_tcg_funcs.py | 18 +-
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84 files changed, 870 insertions(+), 890 deletions(-)
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diff view generated by jsdifflib
[PULL 1/3] exec: flush CPU TB cache in breakpoint_invalidate
Deleted patch
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From: Max Filippov <jcmvbkbc@gmail.com>
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1
3
When a breakpoint is inserted at location for which there's currently no
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virtual to physical translation no action is taken on CPU TB cache. If a
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TB for that virtual address already exists but is not visible ATM the
6
breakpoint won't be hit next time an instruction at that address will be
7
executed.
8
9
Flush entire CPU TB cache in breakpoint_invalidate to force
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re-translation of all TBs for the breakpoint address.
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12
This change fixes the following scenario:
13
- linux user application is running
14
- a breakpoint is inserted from QEMU gdbstub for a user address that is
15
not currently present in the target CPU TLB
16
- an instruction at that address is executed, but the external debugger
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doesn't get control.
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19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
24
exec.c | 15 +++++++--------
25
1 file changed, 7 insertions(+), 8 deletions(-)
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27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
32
33
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
34
{
35
- MemTxAttrs attrs;
36
- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
37
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
38
- if (phys != -1) {
39
- /* Locks grabbed by tb_invalidate_phys_addr */
40
- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
41
- phys | (pc & ~TARGET_PAGE_MASK), attrs);
42
- }
43
+ /*
44
+ * There may not be a virtual to physical translation for the pc
45
+ * right now, but there may exist cached TB for this pc.
46
+ * Flush the whole TB cache to force re-translation of such TBs.
47
+ * This is heavyweight, but we're debugging anyway.
48
+ */
49
+ tb_flush(cpu);
50
}
51
#endif
52
53
--
54
2.20.1
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56
diff view generated by jsdifflib
[PULL 2/3] tcg: Add support for a helper with 7 arguments
Deleted patch
1
From: Taylor Simpson <tsimpson@quicinc.com>
2
1
3
Currently, helpers can only take up to 6 arguments. This patch adds the
4
capability for up to 7 arguments. I have tested it with the Hexagon port
5
that I am preparing for submission.
6
7
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
8
Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/helper-gen.h | 13 +++++++++++++
12
include/exec/helper-head.h | 2 ++
13
include/exec/helper-proto.h | 6 ++++++
14
include/exec/helper-tcg.h | 7 +++++++
15
4 files changed, 28 insertions(+)
16
17
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/helper-gen.h
20
+++ b/include/exec/helper-gen.h
21
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
22
tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
23
}
24
25
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
26
+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
27
+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
28
+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
29
+ dh_arg_decl(t7, 7)) \
30
+{ \
31
+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
32
+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
33
+ dh_arg(t7, 7) }; \
34
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
35
+}
36
+
37
#include "helper.h"
38
#include "trace/generated-helpers.h"
39
#include "trace/generated-helpers-wrappers.h"
40
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
41
#undef DEF_HELPER_FLAGS_4
42
#undef DEF_HELPER_FLAGS_5
43
#undef DEF_HELPER_FLAGS_6
44
+#undef DEF_HELPER_FLAGS_7
45
#undef GEN_HELPER
46
47
#endif /* HELPER_GEN_H */
48
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/helper-head.h
51
+++ b/include/exec/helper-head.h
52
@@ -XXX,XX +XXX,XX @@
53
DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
54
#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
55
DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
56
+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
57
+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
58
59
/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
60
61
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/exec/helper-proto.h
64
+++ b/include/exec/helper-proto.h
65
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
66
dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
68
69
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
70
+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
71
+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
72
+ dh_ctype(t7));
73
+
74
#include "helper.h"
75
#include "trace/generated-helpers.h"
76
#include "tcg-runtime.h"
77
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
78
#undef DEF_HELPER_FLAGS_4
79
#undef DEF_HELPER_FLAGS_5
80
#undef DEF_HELPER_FLAGS_6
81
+#undef DEF_HELPER_FLAGS_7
82
83
#endif /* HELPER_PROTO_H */
84
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/exec/helper-tcg.h
87
+++ b/include/exec/helper-tcg.h
88
@@ -XXX,XX +XXX,XX @@
89
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
90
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
91
92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
93
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
94
+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
95
+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
96
+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
97
+
98
#include "helper.h"
99
#include "trace/generated-helpers.h"
100
#include "tcg-runtime.h"
101
@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
104
#undef DEF_HELPER_FLAGS_6
105
+#undef DEF_HELPER_FLAGS_7
106
107
#endif /* HELPER_TCG_H */
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_gvec_5_ptr
Deleted patch
1
Extend the vector generator infrastructure to handle
2
5 vector arguments.
3
1
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/tcg/tcg-op-gvec.h | 7 +++++++
10
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
11
2 files changed, 39 insertions(+)
12
13
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/tcg/tcg-op-gvec.h
16
+++ b/include/tcg/tcg-op-gvec.h
17
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
18
uint32_t maxsz, int32_t data,
19
gen_helper_gvec_4_ptr *fn);
20
21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
22
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
23
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
24
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
25
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
26
+ gen_helper_gvec_5_ptr *fn);
27
+
28
/* Expand a gvec operation. Either inline or out-of-line depending on
29
the actual vector size and the operations supported by the host. */
30
typedef struct {
31
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg-op-gvec.c
34
+++ b/tcg/tcg-op-gvec.c
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
36
tcg_temp_free_i32(desc);
37
}
38
39
+/* Generate a call to a gvec-style helper with five vector operands
40
+ and an extra pointer operand. */
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
44
+ gen_helper_gvec_5_ptr *fn)
45
+{
46
+ TCGv_ptr a0, a1, a2, a3, a4;
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
48
+
49
+ a0 = tcg_temp_new_ptr();
50
+ a1 = tcg_temp_new_ptr();
51
+ a2 = tcg_temp_new_ptr();
52
+ a3 = tcg_temp_new_ptr();
53
+ a4 = tcg_temp_new_ptr();
54
+
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
56
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
57
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
58
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
59
+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
60
+
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
62
+
63
+ tcg_temp_free_ptr(a0);
64
+ tcg_temp_free_ptr(a1);
65
+ tcg_temp_free_ptr(a2);
66
+ tcg_temp_free_ptr(a3);
67
+ tcg_temp_free_ptr(a4);
68
+ tcg_temp_free_i32(desc);
69
+}
70
+
71
/* Return true if we want to implement something of OPRSZ bytes
72
in units of LNSZ. This limits the expansion of inline code. */
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
74
--
75
2.20.1
76
77
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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