1
The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
1
The following changes since commit 79b677d658d3d35e1e776826ac4abb28cdce69b8:
2
2
3
Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
3
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2023-02-21 11:28:31 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230221
8
8
9
for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
9
for you to fetch changes up to dbd672c87f19949bb62bfb1fb3a97b9729fd7560:
10
10
11
tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
11
sysemu/os-win32: fix setjmp/longjmp on windows-arm64 (2023-02-21 13:45:48 -1000)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Fix breakpoint invalidation.
14
tcg: Allow first half of insn in ram, and second half in mmio
15
Add support for tcg helpers with 7 arguments.
15
linux-user/sparc: SIGILL for unknown trap vectors
16
Add support for gvec helpers with 5 arguments.
16
linux-user/microblaze: SIGILL for privileged insns
17
linux-user: Fix deadlock while exiting due to signal
18
target/microblaze: Add gdbstub xml
19
util: Adjust cacheflush for windows-arm64
20
include/sysemu/os-win32: Adjust setjmp/longjmp for windows-arm64
17
21
18
----------------------------------------------------------------
22
----------------------------------------------------------------
19
Max Filippov (1):
23
Ilya Leoshkevich (3):
20
exec: flush CPU TB cache in breakpoint_invalidate
24
linux-user: Always exit from exclusive state in fork_end()
25
cpus: Make {start,end}_exclusive() recursive
26
linux-user/microblaze: Handle privileged exception
21
27
22
Richard Henderson (1):
28
Pierrick Bouvier (2):
23
tcg: Add tcg_gen_gvec_5_ptr
29
util/cacheflush: fix cache on windows-arm64
30
sysemu/os-win32: fix setjmp/longjmp on windows-arm64
24
31
25
Taylor Simpson (1):
32
Richard Henderson (3):
26
tcg: Add support for a helper with 7 arguments
33
accel/tcg: Allow the second page of an instruction to be MMIO
34
linux-user/sparc: Raise SIGILL for all unhandled software traps
35
target/microblaze: Add gdbstub xml
27
36
28
include/exec/helper-gen.h | 13 +++++++++++++
37
include/hw/core/cpu.h | 4 +-
29
include/exec/helper-head.h | 2 ++
38
include/sysemu/os-win32.h | 28 ++++++++++--
30
include/exec/helper-proto.h | 6 ++++++
39
target/microblaze/cpu.h | 2 +
31
include/exec/helper-tcg.h | 7 +++++++
40
accel/tcg/translator.c | 12 +++++-
32
include/tcg/tcg-op-gvec.h | 7 +++++++
41
cpus-common.c | 12 +++++-
33
exec.c | 15 +++++++--------
42
linux-user/main.c | 10 +++--
34
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
43
linux-user/microblaze/cpu_loop.c | 10 ++++-
35
7 files changed, 74 insertions(+), 8 deletions(-)
44
linux-user/sparc/cpu_loop.c | 8 ++++
36
45
linux-user/syscall.c | 1 +
46
target/microblaze/cpu.c | 7 ++-
47
target/microblaze/gdbstub.c | 51 ++++++++++++++++------
48
util/cacheflush.c | 14 ++++--
49
configs/targets/microblaze-linux-user.mak | 1 +
50
configs/targets/microblaze-softmmu.mak | 1 +
51
configs/targets/microblazeel-linux-user.mak | 1 +
52
configs/targets/microblazeel-softmmu.mak | 1 +
53
gdb-xml/microblaze-core.xml | 67 +++++++++++++++++++++++++++++
54
gdb-xml/microblaze-stack-protect.xml | 12 ++++++
55
meson.build | 21 +++++++++
56
19 files changed, 229 insertions(+), 34 deletions(-)
57
create mode 100644 gdb-xml/microblaze-core.xml
58
create mode 100644 gdb-xml/microblaze-stack-protect.xml
diff view generated by jsdifflib
New patch
1
If an instruction straddles a page boundary, and the first page
2
was ram, but the second page was MMIO, we would abort. Handle
3
this as if both pages are MMIO, by setting the ram_addr_t for
4
the first page to -1.
1
5
6
Reported-by: Sid Manning <sidneym@quicinc.com>
7
Reported-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
accel/tcg/translator.c | 12 ++++++++++--
12
1 file changed, 10 insertions(+), 2 deletions(-)
13
14
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/accel/tcg/translator.c
17
+++ b/accel/tcg/translator.c
18
@@ -XXX,XX +XXX,XX @@ static void *translator_access(CPUArchState *env, DisasContextBase *db,
19
if (host == NULL) {
20
tb_page_addr_t phys_page =
21
get_page_addr_code_hostp(env, base, &db->host_addr[1]);
22
- /* We cannot handle MMIO as second page. */
23
- assert(phys_page != -1);
24
+
25
+ /*
26
+ * If the second page is MMIO, treat as if the first page
27
+ * was MMIO as well, so that we do not cache the TB.
28
+ */
29
+ if (unlikely(phys_page == -1)) {
30
+ tb_set_page_addr0(tb, -1);
31
+ return NULL;
32
+ }
33
+
34
tb_set_page_addr1(tb, phys_page);
35
#ifdef CONFIG_USER_ONLY
36
page_protect(end);
37
--
38
2.34.1
39
40
diff view generated by jsdifflib
New patch
1
The linux kernel's trap tables vector all unassigned trap
2
numbers to BAD_TRAP, which then raises SIGILL.
1
3
4
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
5
Reported-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
linux-user/sparc/cpu_loop.c | 8 ++++++++
9
1 file changed, 8 insertions(+)
10
11
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/linux-user/sparc/cpu_loop.c
14
+++ b/linux-user/sparc/cpu_loop.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_loop (CPUSPARCState *env)
16
cpu_exec_step_atomic(cs);
17
break;
18
default:
19
+ /*
20
+ * Most software trap numbers vector to BAD_TRAP.
21
+ * Handle anything not explicitly matched above.
22
+ */
23
+ if (trapnr >= TT_TRAP && trapnr <= TT_TRAP + 0x7f) {
24
+ force_sig_fault(TARGET_SIGILL, ILL_ILLTRP, env->pc);
25
+ break;
26
+ }
27
fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
28
cpu_dump_state(cs, stderr, 0);
29
exit(EXIT_FAILURE);
30
--
31
2.34.1
diff view generated by jsdifflib
1
From: Taylor Simpson <tsimpson@quicinc.com>
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
2
3
Currently, helpers can only take up to 6 arguments. This patch adds the
3
fork()ed processes currently start with
4
capability for up to 7 arguments. I have tested it with the Hexagon port
4
current_cpu->in_exclusive_context set, which is, strictly speaking, not
5
that I am preparing for submission.
5
correct, but does not cause problems (even assertion failures).
6
6
7
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
7
With one of the next patches, the code begins to rely on this value, so
8
Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
8
fix it by always calling end_exclusive() in fork_end().
9
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
13
Message-Id: <20230214140829.45392-2-iii@linux.ibm.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
15
---
11
include/exec/helper-gen.h | 13 +++++++++++++
16
linux-user/main.c | 10 ++++++----
12
include/exec/helper-head.h | 2 ++
17
linux-user/syscall.c | 1 +
13
include/exec/helper-proto.h | 6 ++++++
18
2 files changed, 7 insertions(+), 4 deletions(-)
14
include/exec/helper-tcg.h | 7 +++++++
15
4 files changed, 28 insertions(+)
16
19
17
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
20
diff --git a/linux-user/main.c b/linux-user/main.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/helper-gen.h
22
--- a/linux-user/main.c
20
+++ b/include/exec/helper-gen.h
23
+++ b/linux-user/main.c
21
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
24
@@ -XXX,XX +XXX,XX @@ void fork_end(int child)
22
tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
25
}
26
qemu_init_cpu_list();
27
gdbserver_fork(thread_cpu);
28
- /* qemu_init_cpu_list() takes care of reinitializing the
29
- * exclusive state, so we don't need to end_exclusive() here.
30
- */
31
} else {
32
cpu_list_unlock();
33
- end_exclusive();
34
}
35
+ /*
36
+ * qemu_init_cpu_list() reinitialized the child exclusive state, but we
37
+ * also need to keep current_cpu consistent, so call end_exclusive() for
38
+ * both child and parent.
39
+ */
40
+ end_exclusive();
23
}
41
}
24
42
25
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
43
__thread CPUState *thread_cpu;
26
+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
44
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
27
+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
28
+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
29
+ dh_arg_decl(t7, 7)) \
30
+{ \
31
+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
32
+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
33
+ dh_arg(t7, 7) }; \
34
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
35
+}
36
+
37
#include "helper.h"
38
#include "trace/generated-helpers.h"
39
#include "trace/generated-helpers-wrappers.h"
40
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
41
#undef DEF_HELPER_FLAGS_4
42
#undef DEF_HELPER_FLAGS_5
43
#undef DEF_HELPER_FLAGS_6
44
+#undef DEF_HELPER_FLAGS_7
45
#undef GEN_HELPER
46
47
#endif /* HELPER_GEN_H */
48
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
49
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/helper-head.h
46
--- a/linux-user/syscall.c
51
+++ b/include/exec/helper-head.h
47
+++ b/linux-user/syscall.c
52
@@ -XXX,XX +XXX,XX @@
48
@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
53
DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
49
cpu_clone_regs_parent(env, flags);
54
#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
50
fork_end(0);
55
DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
51
}
56
+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
52
+ g_assert(!cpu_in_exclusive_context(cpu));
57
+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
53
}
58
54
return ret;
59
/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
55
}
60
61
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/exec/helper-proto.h
64
+++ b/include/exec/helper-proto.h
65
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
66
dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
68
69
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
70
+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
71
+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
72
+ dh_ctype(t7));
73
+
74
#include "helper.h"
75
#include "trace/generated-helpers.h"
76
#include "tcg-runtime.h"
77
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
78
#undef DEF_HELPER_FLAGS_4
79
#undef DEF_HELPER_FLAGS_5
80
#undef DEF_HELPER_FLAGS_6
81
+#undef DEF_HELPER_FLAGS_7
82
83
#endif /* HELPER_PROTO_H */
84
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/exec/helper-tcg.h
87
+++ b/include/exec/helper-tcg.h
88
@@ -XXX,XX +XXX,XX @@
89
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
90
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
91
92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
93
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
94
+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
95
+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
96
+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
97
+
98
#include "helper.h"
99
#include "trace/generated-helpers.h"
100
#include "tcg-runtime.h"
101
@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
104
#undef DEF_HELPER_FLAGS_6
105
+#undef DEF_HELPER_FLAGS_7
106
107
#endif /* HELPER_TCG_H */
108
--
56
--
109
2.20.1
57
2.34.1
110
58
111
59
diff view generated by jsdifflib
1
Extend the vector generator infrastructure to handle
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
5 vector arguments.
3
2
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Currently dying to one of the core_dump_signal()s deadlocks, because
4
dump_core_and_abort() calls start_exclusive() two times: first via
5
stop_all_tasks(), and then via preexit_cleanup() ->
6
qemu_plugin_user_exit().
7
8
There are a number of ways to solve this: resume after dumping core;
9
check cpu_in_exclusive_context() in qemu_plugin_user_exit(); or make
10
{start,end}_exclusive() recursive. Pick the last option, since it's
11
the most straightforward one.
12
13
Fixes: da91c1920242 ("linux-user: Clean up when exiting due to a signal")
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
16
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
17
Message-Id: <20230214140829.45392-3-iii@linux.ibm.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
19
---
9
include/tcg/tcg-op-gvec.h | 7 +++++++
20
include/hw/core/cpu.h | 4 ++--
10
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
21
cpus-common.c | 12 ++++++++++--
11
2 files changed, 39 insertions(+)
22
2 files changed, 12 insertions(+), 4 deletions(-)
12
23
13
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
24
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
14
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
15
--- a/include/tcg/tcg-op-gvec.h
26
--- a/include/hw/core/cpu.h
16
+++ b/include/tcg/tcg-op-gvec.h
27
+++ b/include/hw/core/cpu.h
17
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
28
@@ -XXX,XX +XXX,XX @@ struct CPUState {
18
uint32_t maxsz, int32_t data,
29
bool unplug;
19
gen_helper_gvec_4_ptr *fn);
30
bool crash_occurred;
20
31
bool exit_request;
21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
32
- bool in_exclusive_context;
22
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
33
+ int exclusive_context_count;
23
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
34
uint32_t cflags_next_tb;
24
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
35
/* updates protected by BQL */
25
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
36
uint32_t interrupt_request;
26
+ gen_helper_gvec_5_ptr *fn);
37
@@ -XXX,XX +XXX,XX @@ void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data
38
*/
39
static inline bool cpu_in_exclusive_context(const CPUState *cpu)
40
{
41
- return cpu->in_exclusive_context;
42
+ return cpu->exclusive_context_count;
43
}
44
45
/**
46
diff --git a/cpus-common.c b/cpus-common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/cpus-common.c
49
+++ b/cpus-common.c
50
@@ -XXX,XX +XXX,XX @@ void start_exclusive(void)
51
CPUState *other_cpu;
52
int running_cpus;
53
54
+ if (current_cpu->exclusive_context_count) {
55
+ current_cpu->exclusive_context_count++;
56
+ return;
57
+ }
27
+
58
+
28
/* Expand a gvec operation. Either inline or out-of-line depending on
59
qemu_mutex_lock(&qemu_cpu_list_lock);
29
the actual vector size and the operations supported by the host. */
60
exclusive_idle();
30
typedef struct {
61
31
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
62
@@ -XXX,XX +XXX,XX @@ void start_exclusive(void)
32
index XXXXXXX..XXXXXXX 100644
63
*/
33
--- a/tcg/tcg-op-gvec.c
64
qemu_mutex_unlock(&qemu_cpu_list_lock);
34
+++ b/tcg/tcg-op-gvec.c
65
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
66
- current_cpu->in_exclusive_context = true;
36
tcg_temp_free_i32(desc);
67
+ current_cpu->exclusive_context_count = 1;
37
}
68
}
38
69
39
+/* Generate a call to a gvec-style helper with five vector operands
70
/* Finish an exclusive operation. */
40
+ and an extra pointer operand. */
71
void end_exclusive(void)
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
72
{
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
73
- current_cpu->in_exclusive_context = false;
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
74
+ current_cpu->exclusive_context_count--;
44
+ gen_helper_gvec_5_ptr *fn)
75
+ if (current_cpu->exclusive_context_count) {
45
+{
76
+ return;
46
+ TCGv_ptr a0, a1, a2, a3, a4;
77
+ }
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
78
48
+
79
qemu_mutex_lock(&qemu_cpu_list_lock);
49
+ a0 = tcg_temp_new_ptr();
80
qatomic_set(&pending_cpus, 0);
50
+ a1 = tcg_temp_new_ptr();
51
+ a2 = tcg_temp_new_ptr();
52
+ a3 = tcg_temp_new_ptr();
53
+ a4 = tcg_temp_new_ptr();
54
+
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
56
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
57
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
58
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
59
+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
60
+
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
62
+
63
+ tcg_temp_free_ptr(a0);
64
+ tcg_temp_free_ptr(a1);
65
+ tcg_temp_free_ptr(a2);
66
+ tcg_temp_free_ptr(a3);
67
+ tcg_temp_free_ptr(a4);
68
+ tcg_temp_free_i32(desc);
69
+}
70
+
71
/* Return true if we want to implement something of OPRSZ bytes
72
in units of LNSZ. This limits the expansion of inline code. */
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
74
--
81
--
75
2.20.1
82
2.34.1
76
83
77
84
diff view generated by jsdifflib
New patch
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
Follow what kernel's full_exception() is doing.
4
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Message-Id: <20230214140829.45392-4-iii@linux.ibm.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
linux-user/microblaze/cpu_loop.c | 10 ++++++++--
11
1 file changed, 8 insertions(+), 2 deletions(-)
12
13
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/microblaze/cpu_loop.c
16
+++ b/linux-user/microblaze/cpu_loop.c
17
@@ -XXX,XX +XXX,XX @@
18
19
void cpu_loop(CPUMBState *env)
20
{
21
+ int trapnr, ret, si_code, sig;
22
CPUState *cs = env_cpu(env);
23
- int trapnr, ret, si_code;
24
25
while (1) {
26
cpu_exec_start(cs);
27
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUMBState *env)
28
env->iflags &= ~(IMM_FLAG | D_FLAG);
29
switch (env->esr & 31) {
30
case ESR_EC_DIVZERO:
31
+ sig = TARGET_SIGFPE;
32
si_code = TARGET_FPE_INTDIV;
33
break;
34
case ESR_EC_FPU:
35
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUMBState *env)
36
* if there's no recognized bit set. Possibly this
37
* implies that si_code is 0, but follow the structure.
38
*/
39
+ sig = TARGET_SIGFPE;
40
si_code = env->fsr;
41
if (si_code & FSR_IO) {
42
si_code = TARGET_FPE_FLTINV;
43
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUMBState *env)
44
si_code = TARGET_FPE_FLTRES;
45
}
46
break;
47
+ case ESR_EC_PRIVINSN:
48
+ sig = SIGILL;
49
+ si_code = ILL_PRVOPC;
50
+ break;
51
default:
52
fprintf(stderr, "Unhandled hw-exception: 0x%x\n",
53
env->esr & ESR_EC_MASK);
54
cpu_dump_state(cs, stderr, 0);
55
exit(EXIT_FAILURE);
56
}
57
- force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
58
+ force_sig_fault(sig, si_code, env->pc);
59
break;
60
61
case EXCP_DEBUG:
62
--
63
2.34.1
diff view generated by jsdifflib
New patch
1
Mirroring the upstream gdb xml files, the two stack boundary
2
registers are separated out.
1
3
4
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/microblaze/cpu.h | 2 +
8
target/microblaze/cpu.c | 7 ++-
9
target/microblaze/gdbstub.c | 51 +++++++++++-----
10
configs/targets/microblaze-linux-user.mak | 1 +
11
configs/targets/microblaze-softmmu.mak | 1 +
12
configs/targets/microblazeel-linux-user.mak | 1 +
13
configs/targets/microblazeel-softmmu.mak | 1 +
14
gdb-xml/microblaze-core.xml | 67 +++++++++++++++++++++
15
gdb-xml/microblaze-stack-protect.xml | 12 ++++
16
9 files changed, 128 insertions(+), 15 deletions(-)
17
create mode 100644 gdb-xml/microblaze-core.xml
18
create mode 100644 gdb-xml/microblaze-stack-protect.xml
19
20
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/microblaze/cpu.h
23
+++ b/target/microblaze/cpu.h
24
@@ -XXX,XX +XXX,XX @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
25
MemTxAttrs *attrs);
26
int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
27
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
28
+int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);
29
+int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg);
30
31
static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
32
{
33
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/microblaze/cpu.c
36
+++ b/target/microblaze/cpu.c
37
@@ -XXX,XX +XXX,XX @@
38
#include "qemu/module.h"
39
#include "hw/qdev-properties.h"
40
#include "exec/exec-all.h"
41
+#include "exec/gdbstub.h"
42
#include "fpu/softfloat-helpers.h"
43
44
static const struct {
45
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_initfn(Object *obj)
46
CPUMBState *env = &cpu->env;
47
48
cpu_set_cpustate_pointers(cpu);
49
+ gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
50
+ mb_cpu_gdb_write_stack_protect, 2,
51
+ "microblaze-stack-protect.xml", 0);
52
53
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
54
55
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
56
cc->sysemu_ops = &mb_sysemu_ops;
57
#endif
58
device_class_set_props(dc, mb_properties);
59
- cc->gdb_num_core_regs = 32 + 27;
60
+ cc->gdb_num_core_regs = 32 + 25;
61
+ cc->gdb_core_xml_file = "microblaze-core.xml";
62
63
cc->disas_set_info = mb_disas_set_info;
64
cc->tcg_ops = &mb_tcg_ops;
65
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/microblaze/gdbstub.c
68
+++ b/target/microblaze/gdbstub.c
69
@@ -XXX,XX +XXX,XX @@ enum {
70
GDB_PVR0 = 32 + 6,
71
GDB_PVR11 = 32 + 17,
72
GDB_EDR = 32 + 18,
73
- GDB_SLR = 32 + 25,
74
- GDB_SHR = 32 + 26,
75
+};
76
+
77
+enum {
78
+ GDB_SP_SHL,
79
+ GDB_SP_SHR,
80
};
81
82
int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
83
@@ -XXX,XX +XXX,XX @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
84
case GDB_EDR:
85
val = env->edr;
86
break;
87
- case GDB_SLR:
88
- val = env->slr;
89
- break;
90
- case GDB_SHR:
91
- val = env->shr;
92
- break;
93
default:
94
/* Other SRegs aren't modeled, so report a value of 0 */
95
val = 0;
96
@@ -XXX,XX +XXX,XX @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
97
return gdb_get_reg32(mem_buf, val);
98
}
99
100
+int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, int n)
101
+{
102
+ uint32_t val;
103
+
104
+ switch (n) {
105
+ case GDB_SP_SHL:
106
+ val = env->slr;
107
+ break;
108
+ case GDB_SP_SHR:
109
+ val = env->shr;
110
+ break;
111
+ default:
112
+ return 0;
113
+ }
114
+ return gdb_get_reg32(mem_buf, val);
115
+}
116
+
117
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
118
{
119
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
120
@@ -XXX,XX +XXX,XX @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
121
case GDB_EDR:
122
env->edr = tmp;
123
break;
124
- case GDB_SLR:
125
- env->slr = tmp;
126
- break;
127
- case GDB_SHR:
128
- env->shr = tmp;
129
- break;
130
+ }
131
+ return 4;
132
+}
133
+
134
+int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int n)
135
+{
136
+ switch (n) {
137
+ case GDB_SP_SHL:
138
+ env->slr = ldl_p(mem_buf);
139
+ break;
140
+ case GDB_SP_SHR:
141
+ env->shr = ldl_p(mem_buf);
142
+ break;
143
+ default:
144
+ return 0;
145
}
146
return 4;
147
}
148
diff --git a/configs/targets/microblaze-linux-user.mak b/configs/targets/microblaze-linux-user.mak
149
index XXXXXXX..XXXXXXX 100644
150
--- a/configs/targets/microblaze-linux-user.mak
151
+++ b/configs/targets/microblaze-linux-user.mak
152
@@ -XXX,XX +XXX,XX @@ TARGET_SYSTBL_ABI=common
153
TARGET_SYSTBL=syscall.tbl
154
TARGET_BIG_ENDIAN=y
155
TARGET_HAS_BFLT=y
156
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
157
diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak
158
index XXXXXXX..XXXXXXX 100644
159
--- a/configs/targets/microblaze-softmmu.mak
160
+++ b/configs/targets/microblaze-softmmu.mak
161
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=microblaze
162
TARGET_BIG_ENDIAN=y
163
TARGET_SUPPORTS_MTTCG=y
164
TARGET_NEED_FDT=y
165
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
166
diff --git a/configs/targets/microblazeel-linux-user.mak b/configs/targets/microblazeel-linux-user.mak
167
index XXXXXXX..XXXXXXX 100644
168
--- a/configs/targets/microblazeel-linux-user.mak
169
+++ b/configs/targets/microblazeel-linux-user.mak
170
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=microblaze
171
TARGET_SYSTBL_ABI=common
172
TARGET_SYSTBL=syscall.tbl
173
TARGET_HAS_BFLT=y
174
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
175
diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak
176
index XXXXXXX..XXXXXXX 100644
177
--- a/configs/targets/microblazeel-softmmu.mak
178
+++ b/configs/targets/microblazeel-softmmu.mak
179
@@ -XXX,XX +XXX,XX @@
180
TARGET_ARCH=microblaze
181
TARGET_SUPPORTS_MTTCG=y
182
TARGET_NEED_FDT=y
183
+TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
184
diff --git a/gdb-xml/microblaze-core.xml b/gdb-xml/microblaze-core.xml
185
new file mode 100644
186
index XXXXXXX..XXXXXXX
187
--- /dev/null
188
+++ b/gdb-xml/microblaze-core.xml
189
@@ -XXX,XX +XXX,XX @@
190
+<?xml version="1.0"?>
191
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
192
+
193
+ Copying and distribution of this file, with or without modification,
194
+ are permitted in any medium without royalty provided the copyright
195
+ notice and this notice are preserved. -->
196
+
197
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
198
+<feature name="org.gnu.gdb.microblaze.core">
199
+ <reg name="r0" bitsize="32" regnum="0"/>
200
+ <reg name="r1" bitsize="32" type="data_ptr"/>
201
+ <reg name="r2" bitsize="32"/>
202
+ <reg name="r3" bitsize="32"/>
203
+ <reg name="r4" bitsize="32"/>
204
+ <reg name="r5" bitsize="32"/>
205
+ <reg name="r6" bitsize="32"/>
206
+ <reg name="r7" bitsize="32"/>
207
+ <reg name="r8" bitsize="32"/>
208
+ <reg name="r9" bitsize="32"/>
209
+ <reg name="r10" bitsize="32"/>
210
+ <reg name="r11" bitsize="32"/>
211
+ <reg name="r12" bitsize="32"/>
212
+ <reg name="r13" bitsize="32"/>
213
+ <reg name="r14" bitsize="32"/>
214
+ <reg name="r15" bitsize="32"/>
215
+ <reg name="r16" bitsize="32"/>
216
+ <reg name="r17" bitsize="32"/>
217
+ <reg name="r18" bitsize="32"/>
218
+ <reg name="r19" bitsize="32"/>
219
+ <reg name="r20" bitsize="32"/>
220
+ <reg name="r21" bitsize="32"/>
221
+ <reg name="r22" bitsize="32"/>
222
+ <reg name="r23" bitsize="32"/>
223
+ <reg name="r24" bitsize="32"/>
224
+ <reg name="r25" bitsize="32"/>
225
+ <reg name="r26" bitsize="32"/>
226
+ <reg name="r27" bitsize="32"/>
227
+ <reg name="r28" bitsize="32"/>
228
+ <reg name="r29" bitsize="32"/>
229
+ <reg name="r30" bitsize="32"/>
230
+ <reg name="r31" bitsize="32"/>
231
+ <reg name="rpc" bitsize="32" type="code_ptr"/>
232
+ <reg name="rmsr" bitsize="32"/>
233
+ <reg name="rear" bitsize="32"/>
234
+ <reg name="resr" bitsize="32"/>
235
+ <reg name="rfsr" bitsize="32"/>
236
+ <reg name="rbtr" bitsize="32"/>
237
+ <reg name="rpvr0" bitsize="32"/>
238
+ <reg name="rpvr1" bitsize="32"/>
239
+ <reg name="rpvr2" bitsize="32"/>
240
+ <reg name="rpvr3" bitsize="32"/>
241
+ <reg name="rpvr4" bitsize="32"/>
242
+ <reg name="rpvr5" bitsize="32"/>
243
+ <reg name="rpvr6" bitsize="32"/>
244
+ <reg name="rpvr7" bitsize="32"/>
245
+ <reg name="rpvr8" bitsize="32"/>
246
+ <reg name="rpvr9" bitsize="32"/>
247
+ <reg name="rpvr10" bitsize="32"/>
248
+ <reg name="rpvr11" bitsize="32"/>
249
+ <reg name="redr" bitsize="32"/>
250
+ <reg name="rpid" bitsize="32"/>
251
+ <reg name="rzpr" bitsize="32"/>
252
+ <reg name="rtlbx" bitsize="32"/>
253
+ <reg name="rtlbsx" bitsize="32"/>
254
+ <reg name="rtlblo" bitsize="32"/>
255
+ <reg name="rtlbhi" bitsize="32"/>
256
+</feature>
257
diff --git a/gdb-xml/microblaze-stack-protect.xml b/gdb-xml/microblaze-stack-protect.xml
258
new file mode 100644
259
index XXXXXXX..XXXXXXX
260
--- /dev/null
261
+++ b/gdb-xml/microblaze-stack-protect.xml
262
@@ -XXX,XX +XXX,XX @@
263
+<?xml version="1.0"?>
264
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
265
+
266
+ Copying and distribution of this file, with or without modification,
267
+ are permitted in any medium without royalty provided the copyright
268
+ notice and this notice are preserved. -->
269
+
270
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
271
+<feature name="org.gnu.gdb.microblaze.stack-protect">
272
+ <reg name="rslr" bitsize="32"/>
273
+ <reg name="rshr" bitsize="32"/>
274
+</feature>
275
--
276
2.34.1
diff view generated by jsdifflib
New patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
ctr_el0 access is privileged on this platform and fails as an illegal
4
instruction.
5
6
Windows does not offer a way to flush data cache from userspace, and
7
only FlushInstructionCache is available in Windows API.
8
9
The generic implementation of flush_idcache_range uses,
10
__builtin___clear_cache, which already use the FlushInstructionCache
11
function. So we rely on that.
12
13
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-Id: <20230221153006.20300-2-pierrick.bouvier@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
---
18
util/cacheflush.c | 14 +++++++++++---
19
1 file changed, 11 insertions(+), 3 deletions(-)
20
21
diff --git a/util/cacheflush.c b/util/cacheflush.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/util/cacheflush.c
24
+++ b/util/cacheflush.c
25
@@ -XXX,XX +XXX,XX @@ static void sys_cache_info(int *isize, int *dsize)
26
static bool have_coherent_icache;
27
#endif
28
29
-#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
30
-/* Apple does not expose CTR_EL0, so we must use system interfaces. */
31
+#if defined(__aarch64__) && !defined(CONFIG_DARWIN) && !defined(CONFIG_WIN32)
32
+/*
33
+ * Apple does not expose CTR_EL0, so we must use system interfaces.
34
+ * Windows neither, but we use a generic implementation of flush_idcache_range
35
+ * in this case.
36
+ */
37
static uint64_t save_ctr_el0;
38
static void arch_cache_info(int *isize, int *dsize)
39
{
40
@@ -XXX,XX +XXX,XX @@ static void __attribute__((constructor)) init_cache_info(void)
41
42
/* Caches are coherent and do not require flushing; symbol inline. */
43
44
-#elif defined(__aarch64__)
45
+#elif defined(__aarch64__) && !defined(CONFIG_WIN32)
46
+/*
47
+ * For Windows, we use generic implementation of flush_idcache_range, that
48
+ * performs a call to FlushInstructionCache, through __builtin___clear_cache.
49
+ */
50
51
#ifdef CONFIG_DARWIN
52
/* Apple does not expose CTR_EL0, so we must use system interfaces. */
53
--
54
2.34.1
diff view generated by jsdifflib
1
From: Max Filippov <jcmvbkbc@gmail.com>
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
2
3
When a breakpoint is inserted at location for which there's currently no
3
Windows implementation of setjmp/longjmp is done in
4
virtual to physical translation no action is taken on CPU TB cache. If a
4
C:/WINDOWS/system32/ucrtbase.dll. Alas, on arm64, it seems to *always*
5
TB for that virtual address already exists but is not visible ATM the
5
perform stack unwinding, which crashes from generated code.
6
breakpoint won't be hit next time an instruction at that address will be
7
executed.
8
6
9
Flush entire CPU TB cache in breakpoint_invalidate to force
7
By using alternative implementation built in mingw, we avoid doing stack
10
re-translation of all TBs for the breakpoint address.
8
unwinding and this fixes crash when calling longjmp.
11
9
12
This change fixes the following scenario:
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
- linux user application is running
11
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
14
- a breakpoint is inserted from QEMU gdbstub for a user address that is
12
Acked-by: Richard Henderson <richard.henderson@linaro.org>
15
not currently present in the target CPU TLB
13
Message-Id: <20230221153006.20300-3-pierrick.bouvier@linaro.org>
16
- an instruction at that address is executed, but the external debugger
17
doesn't get control.
18
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
21
Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
15
---
24
exec.c | 15 +++++++--------
16
include/sysemu/os-win32.h | 28 ++++++++++++++++++++++++----
25
1 file changed, 7 insertions(+), 8 deletions(-)
17
meson.build | 21 +++++++++++++++++++++
18
2 files changed, 45 insertions(+), 4 deletions(-)
26
19
27
diff --git a/exec.c b/exec.c
20
diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h
28
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
22
--- a/include/sysemu/os-win32.h
30
+++ b/exec.c
23
+++ b/include/sysemu/os-win32.h
31
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
24
@@ -XXX,XX +XXX,XX @@ typedef struct sockaddr_un {
32
25
extern "C" {
33
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
34
{
35
- MemTxAttrs attrs;
36
- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
37
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
38
- if (phys != -1) {
39
- /* Locks grabbed by tb_invalidate_phys_addr */
40
- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
41
- phys | (pc & ~TARGET_PAGE_MASK), attrs);
42
- }
43
+ /*
44
+ * There may not be a virtual to physical translation for the pc
45
+ * right now, but there may exist cached TB for this pc.
46
+ * Flush the whole TB cache to force re-translation of such TBs.
47
+ * This is heavyweight, but we're debugging anyway.
48
+ */
49
+ tb_flush(cpu);
50
}
51
#endif
26
#endif
52
27
28
-#if defined(_WIN64)
29
-/* On w64, setjmp is implemented by _setjmp which needs a second parameter.
30
+#if defined(__aarch64__)
31
+/*
32
+ * On windows-arm64, setjmp is available in only one variant, and longjmp always
33
+ * does stack unwinding. This crash with generated code.
34
+ * Thus, we use another implementation of setjmp (not windows one), coming from
35
+ * mingw, which never performs stack unwinding.
36
+ */
37
+#undef setjmp
38
+#undef longjmp
39
+/*
40
+ * These functions are not declared in setjmp.h because __aarch64__ defines
41
+ * setjmp to _setjmpex instead. However, they are still defined in libmingwex.a,
42
+ * which gets linked automatically.
43
+ */
44
+extern int __mingw_setjmp(jmp_buf);
45
+extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
46
+#define setjmp(env) __mingw_setjmp(env)
47
+#define longjmp(env, val) __mingw_longjmp(env, val)
48
+#elif defined(_WIN64)
49
+/*
50
+ * On windows-x64, setjmp is implemented by _setjmp which needs a second parameter.
51
* If this parameter is NULL, longjump does no stack unwinding.
52
* That is what we need for QEMU. Passing the value of register rsp (default)
53
- * lets longjmp try a stack unwinding which will crash with generated code. */
54
+ * lets longjmp try a stack unwinding which will crash with generated code.
55
+ */
56
# undef setjmp
57
# define setjmp(env) _setjmp(env, NULL)
58
-#endif
59
+#endif /* __aarch64__ */
60
/* QEMU uses sigsetjmp()/siglongjmp() as the portable way to specify
61
* "longjmp and don't touch the signal masks". Since we know that the
62
* savemask parameter will always be zero we can safely define these
63
diff --git a/meson.build b/meson.build
64
index XXXXXXX..XXXXXXX 100644
65
--- a/meson.build
66
+++ b/meson.build
67
@@ -XXX,XX +XXX,XX @@ if targetos == 'windows'
68
}''', name: '_lock_file and _unlock_file'))
69
endif
70
71
+if targetos == 'windows'
72
+ mingw_has_setjmp_longjmp = cc.links('''
73
+ #include <setjmp.h>
74
+ int main(void) {
75
+ /*
76
+ * These functions are not available in setjmp header, but may be
77
+ * available at link time, from libmingwex.a.
78
+ */
79
+ extern int __mingw_setjmp(jmp_buf);
80
+ extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int);
81
+ jmp_buf env;
82
+ __mingw_setjmp(env);
83
+ __mingw_longjmp(env, 0);
84
+ }
85
+ ''', name: 'mingw setjmp and longjmp')
86
+
87
+ if cpu == 'aarch64' and not mingw_has_setjmp_longjmp
88
+ error('mingw must provide setjmp/longjmp for windows-arm64')
89
+ endif
90
+endif
91
+
92
########################
93
# Target configuration #
94
########################
53
--
95
--
54
2.20.1
96
2.34.1
55
97
56
98
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