[PULL 0/3] tcg patch queue
[PULL v2 00/20] tcg patch queue
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The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
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v2: Fix incorretly resolved rebase conflict in patch 16.
2
2
3
Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
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4
r~
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The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60:
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-09-02 13:24:28 -0400)
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10
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are available in the Git repository at:
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are available in the Git repository at:
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12
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220904
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14
9
for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
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for you to fetch changes up to cc64de1fdeb81bc1ab8bb6c7c24bfd4fc9b28ef2:
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16
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tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
17
target/riscv: Make translator stop before the end of a page (2022-09-03 09:27:05 +0100)
12
18
13
----------------------------------------------------------------
19
----------------------------------------------------------------
14
Fix breakpoint invalidation.
20
Respect PROT_EXEC in user-only mode.
15
Add support for tcg helpers with 7 arguments.
21
Fix s390x, i386 and riscv for translations crossing a page.
16
Add support for gvec helpers with 5 arguments.
17
22
18
----------------------------------------------------------------
23
----------------------------------------------------------------
19
Max Filippov (1):
24
Ilya Leoshkevich (4):
20
exec: flush CPU TB cache in breakpoint_invalidate
25
linux-user: Clear translations on mprotect()
26
accel/tcg: Introduce is_same_page()
27
target/s390x: Make translator stop before the end of a page
28
target/i386: Make translator stop before the end of a page
21
29
22
Richard Henderson (1):
30
Richard Henderson (16):
23
tcg: Add tcg_gen_gvec_5_ptr
31
linux-user/arm: Mark the commpage executable
32
linux-user/hppa: Allocate page zero as a commpage
33
linux-user/x86_64: Allocate vsyscall page as a commpage
34
linux-user: Honor PT_GNU_STACK
35
tests/tcg/i386: Move smc_code2 to an executable section
36
accel/tcg: Properly implement get_page_addr_code for user-only
37
accel/tcg: Unlock mmap_lock after longjmp
38
accel/tcg: Make tb_htable_lookup static
39
accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c
40
accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp
41
accel/tcg: Document the faulting lookup in tb_lookup_cmp
42
accel/tcg: Remove translator_ldsw
43
accel/tcg: Add pc and host_pc params to gen_intermediate_code
44
accel/tcg: Add fast path for translator_ld*
45
target/riscv: Add MAX_INSN_LEN and insn_len
46
target/riscv: Make translator stop before the end of a page
24
47
25
Taylor Simpson (1):
48
include/elf.h | 1 +
26
tcg: Add support for a helper with 7 arguments
49
include/exec/cpu-common.h | 1 +
27
50
include/exec/exec-all.h | 89 ++++++++----------------
28
include/exec/helper-gen.h | 13 +++++++++++++
51
include/exec/translator.h | 96 ++++++++++++++++---------
29
include/exec/helper-head.h | 2 ++
52
linux-user/arm/target_cpu.h | 4 +-
30
include/exec/helper-proto.h | 6 ++++++
53
linux-user/qemu.h | 1 +
31
include/exec/helper-tcg.h | 7 +++++++
54
accel/tcg/cpu-exec.c | 143 ++++++++++++++++++++------------------
32
include/tcg/tcg-op-gvec.h | 7 +++++++
55
accel/tcg/cputlb.c | 93 +++++++------------------
33
exec.c | 15 +++++++--------
56
accel/tcg/translate-all.c | 29 ++++----
34
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
57
accel/tcg/translator.c | 135 ++++++++++++++++++++++++++---------
35
7 files changed, 74 insertions(+), 8 deletions(-)
58
accel/tcg/user-exec.c | 17 ++++-
36
59
linux-user/elfload.c | 82 ++++++++++++++++++++--
60
linux-user/mmap.c | 6 +-
61
softmmu/physmem.c | 12 ++++
62
target/alpha/translate.c | 5 +-
63
target/arm/translate.c | 5 +-
64
target/avr/translate.c | 5 +-
65
target/cris/translate.c | 5 +-
66
target/hexagon/translate.c | 6 +-
67
target/hppa/translate.c | 5 +-
68
target/i386/tcg/translate.c | 71 +++++++++++--------
69
target/loongarch/translate.c | 6 +-
70
target/m68k/translate.c | 5 +-
71
target/microblaze/translate.c | 5 +-
72
target/mips/tcg/translate.c | 5 +-
73
target/nios2/translate.c | 5 +-
74
target/openrisc/translate.c | 6 +-
75
target/ppc/translate.c | 5 +-
76
target/riscv/translate.c | 32 +++++++--
77
target/rx/translate.c | 5 +-
78
target/s390x/tcg/translate.c | 20 ++++--
79
target/sh4/translate.c | 5 +-
80
target/sparc/translate.c | 5 +-
81
target/tricore/translate.c | 6 +-
82
target/xtensa/translate.c | 6 +-
83
tests/tcg/i386/test-i386.c | 2 +-
84
tests/tcg/riscv64/noexec.c | 79 +++++++++++++++++++++
85
tests/tcg/s390x/noexec.c | 106 ++++++++++++++++++++++++++++
86
tests/tcg/x86_64/noexec.c | 75 ++++++++++++++++++++
87
tests/tcg/multiarch/noexec.c.inc | 139 ++++++++++++++++++++++++++++++++++++
88
tests/tcg/riscv64/Makefile.target | 1 +
89
tests/tcg/s390x/Makefile.target | 1 +
90
tests/tcg/x86_64/Makefile.target | 3 +-
91
43 files changed, 966 insertions(+), 367 deletions(-)
92
create mode 100644 tests/tcg/riscv64/noexec.c
93
create mode 100644 tests/tcg/s390x/noexec.c
94
create mode 100644 tests/tcg/x86_64/noexec.c
95
create mode 100644 tests/tcg/multiarch/noexec.c.inc
diff view generated by jsdifflib
[PULL 1/3] exec: flush CPU TB cache in breakpoint_invalidate
Deleted patch
1
From: Max Filippov <jcmvbkbc@gmail.com>
2
1
3
When a breakpoint is inserted at location for which there's currently no
4
virtual to physical translation no action is taken on CPU TB cache. If a
5
TB for that virtual address already exists but is not visible ATM the
6
breakpoint won't be hit next time an instruction at that address will be
7
executed.
8
9
Flush entire CPU TB cache in breakpoint_invalidate to force
10
re-translation of all TBs for the breakpoint address.
11
12
This change fixes the following scenario:
13
- linux user application is running
14
- a breakpoint is inserted from QEMU gdbstub for a user address that is
15
not currently present in the target CPU TLB
16
- an instruction at that address is executed, but the external debugger
17
doesn't get control.
18
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
21
Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
24
exec.c | 15 +++++++--------
25
1 file changed, 7 insertions(+), 8 deletions(-)
26
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
32
33
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
34
{
35
- MemTxAttrs attrs;
36
- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
37
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
38
- if (phys != -1) {
39
- /* Locks grabbed by tb_invalidate_phys_addr */
40
- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
41
- phys | (pc & ~TARGET_PAGE_MASK), attrs);
42
- }
43
+ /*
44
+ * There may not be a virtual to physical translation for the pc
45
+ * right now, but there may exist cached TB for this pc.
46
+ * Flush the whole TB cache to force re-translation of such TBs.
47
+ * This is heavyweight, but we're debugging anyway.
48
+ */
49
+ tb_flush(cpu);
50
}
51
#endif
52
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
[PULL 2/3] tcg: Add support for a helper with 7 arguments
Deleted patch
1
From: Taylor Simpson <tsimpson@quicinc.com>
2
1
3
Currently, helpers can only take up to 6 arguments. This patch adds the
4
capability for up to 7 arguments. I have tested it with the Hexagon port
5
that I am preparing for submission.
6
7
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
8
Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/helper-gen.h | 13 +++++++++++++
12
include/exec/helper-head.h | 2 ++
13
include/exec/helper-proto.h | 6 ++++++
14
include/exec/helper-tcg.h | 7 +++++++
15
4 files changed, 28 insertions(+)
16
17
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/helper-gen.h
20
+++ b/include/exec/helper-gen.h
21
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
22
tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
23
}
24
25
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
26
+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
27
+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
28
+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
29
+ dh_arg_decl(t7, 7)) \
30
+{ \
31
+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
32
+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
33
+ dh_arg(t7, 7) }; \
34
+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
35
+}
36
+
37
#include "helper.h"
38
#include "trace/generated-helpers.h"
39
#include "trace/generated-helpers-wrappers.h"
40
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
41
#undef DEF_HELPER_FLAGS_4
42
#undef DEF_HELPER_FLAGS_5
43
#undef DEF_HELPER_FLAGS_6
44
+#undef DEF_HELPER_FLAGS_7
45
#undef GEN_HELPER
46
47
#endif /* HELPER_GEN_H */
48
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/helper-head.h
51
+++ b/include/exec/helper-head.h
52
@@ -XXX,XX +XXX,XX @@
53
DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
54
#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
55
DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
56
+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
57
+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
58
59
/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
60
61
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/exec/helper-proto.h
64
+++ b/include/exec/helper-proto.h
65
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
66
dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
67
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
68
69
+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
70
+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
71
+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
72
+ dh_ctype(t7));
73
+
74
#include "helper.h"
75
#include "trace/generated-helpers.h"
76
#include "tcg-runtime.h"
77
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
78
#undef DEF_HELPER_FLAGS_4
79
#undef DEF_HELPER_FLAGS_5
80
#undef DEF_HELPER_FLAGS_6
81
+#undef DEF_HELPER_FLAGS_7
82
83
#endif /* HELPER_PROTO_H */
84
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/exec/helper-tcg.h
87
+++ b/include/exec/helper-tcg.h
88
@@ -XXX,XX +XXX,XX @@
89
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
90
| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
91
92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
93
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
94
+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
95
+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
96
+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
97
+
98
#include "helper.h"
99
#include "trace/generated-helpers.h"
100
#include "tcg-runtime.h"
101
@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
104
#undef DEF_HELPER_FLAGS_6
105
+#undef DEF_HELPER_FLAGS_7
106
107
#endif /* HELPER_TCG_H */
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_gvec_5_ptr
[PULL v2 16/20] accel/tcg: Add fast path for translator_ld*
1
Extend the vector generator infrastructure to handle
1
Cache the translation from guest to host address, so we may
2
5 vector arguments.
2
use direct loads when we hit on the primary translation page.
3
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Look up the second translation page only once, during translation.
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
This obviates another lookup of the second page within tb_gen_code
6
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
6
after translation.
7
8
Fixes a bug in that plugin_insn_append should be passed the bytes
9
in the original memory order, not bswapped by pieces.
10
11
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
12
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
14
---
9
include/tcg/tcg-op-gvec.h | 7 +++++++
15
include/exec/translator.h | 63 +++++++++++--------
10
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
16
accel/tcg/translate-all.c | 23 +++----
11
2 files changed, 39 insertions(+)
17
accel/tcg/translator.c | 126 +++++++++++++++++++++++++++++---------
18
3 files changed, 141 insertions(+), 71 deletions(-)
12
19
13
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
20
diff --git a/include/exec/translator.h b/include/exec/translator.h
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/include/tcg/tcg-op-gvec.h
22
--- a/include/exec/translator.h
16
+++ b/include/tcg/tcg-op-gvec.h
23
+++ b/include/exec/translator.h
17
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
24
@@ -XXX,XX +XXX,XX @@ typedef enum DisasJumpType {
18
uint32_t maxsz, int32_t data,
25
* Architecture-agnostic disassembly context.
19
gen_helper_gvec_4_ptr *fn);
26
*/
20
27
typedef struct DisasContextBase {
21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
28
- const TranslationBlock *tb;
22
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
29
+ TranslationBlock *tb;
23
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
30
target_ulong pc_first;
24
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
31
target_ulong pc_next;
25
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
32
DisasJumpType is_jmp;
26
+ gen_helper_gvec_5_ptr *fn);
33
int num_insns;
27
+
34
int max_insns;
28
/* Expand a gvec operation. Either inline or out-of-line depending on
35
bool singlestep_enabled;
29
the actual vector size and the operations supported by the host. */
36
-#ifdef CONFIG_USER_ONLY
30
typedef struct {
37
- /*
31
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
38
- * Guest address of the last byte of the last protected page.
39
- *
40
- * Pages containing the translated instructions are made non-writable in
41
- * order to achieve consistency in case another thread is modifying the
42
- * code while translate_insn() fetches the instruction bytes piecemeal.
43
- * Such writer threads are blocked on mmap_lock() in page_unprotect().
44
- */
45
- target_ulong page_protect_end;
46
-#endif
47
+ void *host_addr[2];
48
} DisasContextBase;
49
50
/**
51
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
52
* the relevant information at translation time.
53
*/
54
55
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
56
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
57
- abi_ptr pc, bool do_swap); \
58
- static inline type fullname(CPUArchState *env, \
59
- DisasContextBase *dcbase, abi_ptr pc) \
60
- { \
61
- return fullname ## _swap(env, dcbase, pc, false); \
62
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
63
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
64
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
65
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
66
+
67
+static inline uint16_t
68
+translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
69
+ abi_ptr pc, bool do_swap)
70
+{
71
+ uint16_t ret = translator_lduw(env, db, pc);
72
+ if (do_swap) {
73
+ ret = bswap16(ret);
74
}
75
+ return ret;
76
+}
77
78
-#define FOR_EACH_TRANSLATOR_LD(F) \
79
- F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
80
- F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
81
- F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
82
- F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
83
+static inline uint32_t
84
+translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
85
+ abi_ptr pc, bool do_swap)
86
+{
87
+ uint32_t ret = translator_ldl(env, db, pc);
88
+ if (do_swap) {
89
+ ret = bswap32(ret);
90
+ }
91
+ return ret;
92
+}
93
94
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
95
-
96
-#undef GEN_TRANSLATOR_LD
97
+static inline uint64_t
98
+translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
99
+ abi_ptr pc, bool do_swap)
100
+{
101
+ uint64_t ret = translator_ldq(env, db, pc);
102
+ if (do_swap) {
103
+ ret = bswap64(ret);
104
+ }
105
+ return ret;
106
+}
107
108
/*
109
* Return whether addr is on the same page as where disassembly started.
110
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
32
index XXXXXXX..XXXXXXX 100644
111
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg-op-gvec.c
112
--- a/accel/tcg/translate-all.c
34
+++ b/tcg/tcg-op-gvec.c
113
+++ b/accel/tcg/translate-all.c
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
114
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
36
tcg_temp_free_i32(desc);
115
{
116
CPUArchState *env = cpu->env_ptr;
117
TranslationBlock *tb, *existing_tb;
118
- tb_page_addr_t phys_pc, phys_page2;
119
- target_ulong virt_page2;
120
+ tb_page_addr_t phys_pc;
121
tcg_insn_unit *gen_code_buf;
122
int gen_code_size, search_size, max_insns;
123
#ifdef CONFIG_PROFILER
124
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
125
tb->flags = flags;
126
tb->cflags = cflags;
127
tb->trace_vcpu_dstate = *cpu->trace_dstate;
128
+ tb->page_addr[0] = phys_pc;
129
+ tb->page_addr[1] = -1;
130
tcg_ctx->tb_cflags = cflags;
131
tb_overflow:
132
133
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
134
}
135
136
/*
137
- * If the TB is not associated with a physical RAM page then
138
- * it must be a temporary one-insn TB, and we have nothing to do
139
- * except fill in the page_addr[] fields. Return early before
140
- * attempting to link to other TBs or add to the lookup table.
141
+ * If the TB is not associated with a physical RAM page then it must be
142
+ * a temporary one-insn TB, and we have nothing left to do. Return early
143
+ * before attempting to link to other TBs or add to the lookup table.
144
*/
145
- if (phys_pc == -1) {
146
- tb->page_addr[0] = tb->page_addr[1] = -1;
147
+ if (tb->page_addr[0] == -1) {
148
return tb;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
152
*/
153
tcg_tb_insert(tb);
154
155
- /* check next page if needed */
156
- virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
157
- phys_page2 = -1;
158
- if ((pc & TARGET_PAGE_MASK) != virt_page2) {
159
- phys_page2 = get_page_addr_code(env, virt_page2);
160
- }
161
/*
162
* No explicit memory barrier is required -- tb_link_page() makes the
163
* TB visible in a consistent state.
164
*/
165
- existing_tb = tb_link_page(tb, phys_pc, phys_page2);
166
+ existing_tb = tb_link_page(tb, tb->page_addr[0], tb->page_addr[1]);
167
/* if the TB already exists, discard what we just translated */
168
if (unlikely(existing_tb != tb)) {
169
uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
170
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/accel/tcg/translator.c
173
+++ b/accel/tcg/translator.c
174
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
175
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
37
}
176
}
38
177
39
+/* Generate a call to a gvec-style helper with five vector operands
178
-static inline void translator_page_protect(DisasContextBase *dcbase,
40
+ and an extra pointer operand. */
179
- target_ulong pc)
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
180
-{
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
181
-#ifdef CONFIG_USER_ONLY
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
182
- dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
44
+ gen_helper_gvec_5_ptr *fn)
183
- page_protect(pc);
45
+{
184
-#endif
46
+ TCGv_ptr a0, a1, a2, a3, a4;
185
-}
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
186
-
48
+
187
void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
49
+ a0 = tcg_temp_new_ptr();
188
target_ulong pc, void *host_pc,
50
+ a1 = tcg_temp_new_ptr();
189
const TranslatorOps *ops, DisasContextBase *db)
51
+ a2 = tcg_temp_new_ptr();
190
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
52
+ a3 = tcg_temp_new_ptr();
191
db->num_insns = 0;
53
+ a4 = tcg_temp_new_ptr();
192
db->max_insns = max_insns;
54
+
193
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
194
- translator_page_protect(db, db->pc_next);
56
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
195
+ db->host_addr[0] = host_pc;
57
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
196
+ db->host_addr[1] = NULL;
58
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
197
+
59
+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
198
+#ifdef CONFIG_USER_ONLY
60
+
199
+ page_protect(pc);
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
200
+#endif
62
+
201
63
+ tcg_temp_free_ptr(a0);
202
ops->init_disas_context(db, cpu);
64
+ tcg_temp_free_ptr(a1);
203
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
65
+ tcg_temp_free_ptr(a2);
204
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
66
+ tcg_temp_free_ptr(a3);
205
#endif
67
+ tcg_temp_free_ptr(a4);
206
}
68
+ tcg_temp_free_i32(desc);
207
69
+}
208
-static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
70
+
209
- target_ulong pc, size_t len)
71
/* Return true if we want to implement something of OPRSZ bytes
210
+static void *translator_access(CPUArchState *env, DisasContextBase *db,
72
in units of LNSZ. This limits the expansion of inline code. */
211
+ target_ulong pc, size_t len)
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
212
{
213
-#ifdef CONFIG_USER_ONLY
214
- target_ulong end = pc + len - 1;
215
+ void *host;
216
+ target_ulong base, end;
217
+ TranslationBlock *tb;
218
219
- if (end > dcbase->page_protect_end) {
220
- translator_page_protect(dcbase, end);
221
+ tb = db->tb;
222
+
223
+ /* Use slow path if first page is MMIO. */
224
+ if (unlikely(tb->page_addr[0] == -1)) {
225
+ return NULL;
226
}
227
+
228
+ end = pc + len - 1;
229
+ if (likely(is_same_page(db, end))) {
230
+ host = db->host_addr[0];
231
+ base = db->pc_first;
232
+ } else {
233
+ host = db->host_addr[1];
234
+ base = TARGET_PAGE_ALIGN(db->pc_first);
235
+ if (host == NULL) {
236
+ tb->page_addr[1] =
237
+ get_page_addr_code_hostp(env, base, &db->host_addr[1]);
238
+#ifdef CONFIG_USER_ONLY
239
+ page_protect(end);
240
#endif
241
+ /* We cannot handle MMIO as second page. */
242
+ assert(tb->page_addr[1] != -1);
243
+ host = db->host_addr[1];
244
+ }
245
+
246
+ /* Use slow path when crossing pages. */
247
+ if (is_same_page(db, pc)) {
248
+ return NULL;
249
+ }
250
+ }
251
+
252
+ tcg_debug_assert(pc >= base);
253
+ return host + (pc - base);
254
}
255
256
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
257
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
258
- abi_ptr pc, bool do_swap) \
259
- { \
260
- translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
261
- type ret = load_fn(env, pc); \
262
- if (do_swap) { \
263
- ret = swap_fn(ret); \
264
- } \
265
- plugin_insn_append(pc, &ret, sizeof(ret)); \
266
- return ret; \
267
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
268
+{
269
+ uint8_t ret;
270
+ void *p = translator_access(env, db, pc, sizeof(ret));
271
+
272
+ if (p) {
273
+ plugin_insn_append(pc, p, sizeof(ret));
274
+ return ldub_p(p);
275
}
276
+ ret = cpu_ldub_code(env, pc);
277
+ plugin_insn_append(pc, &ret, sizeof(ret));
278
+ return ret;
279
+}
280
281
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
282
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
283
+{
284
+ uint16_t ret, plug;
285
+ void *p = translator_access(env, db, pc, sizeof(ret));
286
287
-#undef GEN_TRANSLATOR_LD
288
+ if (p) {
289
+ plugin_insn_append(pc, p, sizeof(ret));
290
+ return lduw_p(p);
291
+ }
292
+ ret = cpu_lduw_code(env, pc);
293
+ plug = tswap16(ret);
294
+ plugin_insn_append(pc, &plug, sizeof(ret));
295
+ return ret;
296
+}
297
+
298
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
299
+{
300
+ uint32_t ret, plug;
301
+ void *p = translator_access(env, db, pc, sizeof(ret));
302
+
303
+ if (p) {
304
+ plugin_insn_append(pc, p, sizeof(ret));
305
+ return ldl_p(p);
306
+ }
307
+ ret = cpu_ldl_code(env, pc);
308
+ plug = tswap32(ret);
309
+ plugin_insn_append(pc, &plug, sizeof(ret));
310
+ return ret;
311
+}
312
+
313
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
314
+{
315
+ uint64_t ret, plug;
316
+ void *p = translator_access(env, db, pc, sizeof(ret));
317
+
318
+ if (p) {
319
+ plugin_insn_append(pc, p, sizeof(ret));
320
+ return ldq_p(p);
321
+ }
322
+ ret = cpu_ldq_code(env, pc);
323
+ plug = tswap64(ret);
324
+ plugin_insn_append(pc, &plug, sizeof(ret));
325
+ return ret;
326
+}
74
--
327
--
75
2.20.1
328
2.34.1
76
77
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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