[PULL 0/3] tcg patch queue
[PULL v2 00/21] tcg patch queue
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The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
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Version 2: Drop signed 32-bit guest patches while CI failure examined.
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Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
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The following changes since commit 3d1fbc59665ff8a5d74b0fd30583044fe99e1117:
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Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging (2022-03-04 15:31:23 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220304
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for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
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for you to fetch changes up to cf320769476c3e2820be2a6280bfa1e15baf396f:
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tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
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tcg/i386: Implement bitsel for avx512 (2022-03-04 08:50:41 -1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Fix breakpoint invalidation.
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Reorder do_constant_folding_cond test to satisfy valgrind.
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Add support for tcg helpers with 7 arguments.
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Fix value of MAX_OPC_PARAM_IARGS.
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Add support for gvec helpers with 5 arguments.
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Add opcodes for vector nand, nor, eqv.
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Support vector nand, nor, eqv on PPC and S390X hosts.
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Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
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----------------------------------------------------------------
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----------------------------------------------------------------
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Max Filippov (1):
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Alex Bennée (1):
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exec: flush CPU TB cache in breakpoint_invalidate
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tcg/optimize: only read val after const check
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27
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Richard Henderson (1):
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Richard Henderson (19):
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tcg: Add tcg_gen_gvec_5_ptr
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tcg: Add opcodes for vector nand, nor, eqv
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tcg/ppc: Implement vector NAND, NOR, EQV
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tcg/s390x: Implement vector NAND, NOR, EQV
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tcg/i386: Detect AVX512
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tcg/i386: Add tcg_out_evex_opc
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tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
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tcg/i386: Implement avx512 variable shifts
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tcg/i386: Implement avx512 scalar shift
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tcg/i386: Implement avx512 immediate sari shift
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tcg/i386: Implement avx512 immediate rotate
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tcg/i386: Implement avx512 variable rotate
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tcg/i386: Support avx512vbmi2 vector shift-double instructions
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tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
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tcg/i386: Remove rotls_vec from tcg_target_op_def
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tcg/i386: Expand scalar rotate with avx512 insns
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tcg/i386: Implement avx512 min/max/abs
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tcg/i386: Implement avx512 multiply
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tcg/i386: Implement more logical operations for avx512
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tcg/i386: Implement bitsel for avx512
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Taylor Simpson (1):
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Ziqiao Kong (1):
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tcg: Add support for a helper with 7 arguments
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tcg: Set MAX_OPC_PARAM_IARGS to 7
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include/exec/helper-gen.h | 13 +++++++++++++
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include/qemu/cpuid.h | 20 ++-
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include/exec/helper-head.h | 2 ++
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include/tcg/tcg-opc.h | 3 +
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include/exec/helper-proto.h | 6 ++++++
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include/tcg/tcg.h | 5 +-
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include/exec/helper-tcg.h | 7 +++++++
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tcg/aarch64/tcg-target.h | 3 +
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include/tcg/tcg-op-gvec.h | 7 +++++++
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tcg/arm/tcg-target.h | 3 +
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exec.c | 15 +++++++--------
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tcg/i386/tcg-target-con-set.h | 1 +
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tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
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tcg/i386/tcg-target.h | 17 +-
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7 files changed, 74 insertions(+), 8 deletions(-)
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tcg/i386/tcg-target.opc.h | 3 +
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tcg/ppc/tcg-target.h | 3 +
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tcg/s390x/tcg-target.h | 3 +
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tcg/optimize.c | 20 +--
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tcg/tcg-op-vec.c | 27 ++-
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tcg/tcg.c | 6 +
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tcg/i386/tcg-target.c.inc | 387 +++++++++++++++++++++++++++++++++++-------
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tcg/ppc/tcg-target.c.inc | 15 ++
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tcg/s390x/tcg-target.c.inc | 17 ++
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tcg/tci/tcg-target.c.inc | 2 +-
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17 files changed, 441 insertions(+), 94 deletions(-)
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diff view generated by jsdifflib
[PULL 1/3] exec: flush CPU TB cache in breakpoint_invalidate
Deleted patch
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From: Max Filippov <jcmvbkbc@gmail.com>
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1
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When a breakpoint is inserted at location for which there's currently no
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virtual to physical translation no action is taken on CPU TB cache. If a
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TB for that virtual address already exists but is not visible ATM the
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breakpoint won't be hit next time an instruction at that address will be
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executed.
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Flush entire CPU TB cache in breakpoint_invalidate to force
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re-translation of all TBs for the breakpoint address.
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This change fixes the following scenario:
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- linux user application is running
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- a breakpoint is inserted from QEMU gdbstub for a user address that is
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not currently present in the target CPU TLB
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- an instruction at that address is executed, but the external debugger
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doesn't get control.
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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exec.c | 15 +++++++--------
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1 file changed, 7 insertions(+), 8 deletions(-)
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diff --git a/exec.c b/exec.c
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index XXXXXXX..XXXXXXX 100644
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--- a/exec.c
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+++ b/exec.c
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@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
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static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
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{
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- MemTxAttrs attrs;
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- hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
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- int asidx = cpu_asidx_from_attrs(cpu, attrs);
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- if (phys != -1) {
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- /* Locks grabbed by tb_invalidate_phys_addr */
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- tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
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- phys | (pc & ~TARGET_PAGE_MASK), attrs);
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- }
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+ /*
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+ * There may not be a virtual to physical translation for the pc
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+ * right now, but there may exist cached TB for this pc.
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+ * Flush the whole TB cache to force re-translation of such TBs.
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+ * This is heavyweight, but we're debugging anyway.
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+ */
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+ tb_flush(cpu);
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}
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#endif
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--
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2.20.1
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diff view generated by jsdifflib
[PULL 2/3] tcg: Add support for a helper with 7 arguments
Deleted patch
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From: Taylor Simpson <tsimpson@quicinc.com>
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Currently, helpers can only take up to 6 arguments. This patch adds the
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capability for up to 7 arguments. I have tested it with the Hexagon port
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that I am preparing for submission.
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Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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include/exec/helper-gen.h | 13 +++++++++++++
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include/exec/helper-head.h | 2 ++
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include/exec/helper-proto.h | 6 ++++++
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include/exec/helper-tcg.h | 7 +++++++
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4 files changed, 28 insertions(+)
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diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/helper-gen.h
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+++ b/include/exec/helper-gen.h
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@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
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tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \
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}
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+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
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+static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
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+ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
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+ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
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+ dh_arg_decl(t7, 7)) \
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+{ \
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+ TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
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+ dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
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+ dh_arg(t7, 7) }; \
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+ tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \
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+}
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+
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#include "helper.h"
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#include "trace/generated-helpers.h"
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#include "trace/generated-helpers-wrappers.h"
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@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
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#undef DEF_HELPER_FLAGS_4
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#undef DEF_HELPER_FLAGS_5
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#undef DEF_HELPER_FLAGS_6
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+#undef DEF_HELPER_FLAGS_7
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#undef GEN_HELPER
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#endif /* HELPER_GEN_H */
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diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/helper-head.h
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+++ b/include/exec/helper-head.h
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@@ -XXX,XX +XXX,XX @@
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DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5)
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#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \
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DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6)
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+#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \
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+ DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7)
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/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */
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diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/helper-proto.h
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+++ b/include/exec/helper-proto.h
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@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
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dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
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dh_ctype(t4), dh_ctype(t5), dh_ctype(t6));
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+#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \
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+dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
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+ dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
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+ dh_ctype(t7));
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+
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#include "helper.h"
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#include "trace/generated-helpers.h"
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#include "tcg-runtime.h"
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@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
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#undef DEF_HELPER_FLAGS_4
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#undef DEF_HELPER_FLAGS_5
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#undef DEF_HELPER_FLAGS_6
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+#undef DEF_HELPER_FLAGS_7
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#endif /* HELPER_PROTO_H */
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diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/helper-tcg.h
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+++ b/include/exec/helper-tcg.h
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@@ -XXX,XX +XXX,XX @@
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| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
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| dh_sizemask(t5, 5) | dh_sizemask(t6, 6) },
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92
+#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \
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+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
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+ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
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+ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
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+ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) },
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+
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#include "helper.h"
99
#include "trace/generated-helpers.h"
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#include "tcg-runtime.h"
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@@ -XXX,XX +XXX,XX @@
102
#undef DEF_HELPER_FLAGS_4
103
#undef DEF_HELPER_FLAGS_5
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#undef DEF_HELPER_FLAGS_6
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+#undef DEF_HELPER_FLAGS_7
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107
#endif /* HELPER_TCG_H */
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--
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2.20.1
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diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_gvec_5_ptr
Deleted patch
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Extend the vector generator infrastructure to handle
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5 vector arguments.
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1
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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include/tcg/tcg-op-gvec.h | 7 +++++++
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tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
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2 files changed, 39 insertions(+)
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diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/tcg/tcg-op-gvec.h
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+++ b/include/tcg/tcg-op-gvec.h
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@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t maxsz, int32_t data,
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gen_helper_gvec_4_ptr *fn);
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21
+typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
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+ TCGv_ptr, TCGv_ptr, TCGv_i32);
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+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
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+ uint32_t oprsz, uint32_t maxsz, int32_t data,
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+ gen_helper_gvec_5_ptr *fn);
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+
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/* Expand a gvec operation. Either inline or out-of-line depending on
29
the actual vector size and the operations supported by the host. */
30
typedef struct {
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diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
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index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg-op-gvec.c
34
+++ b/tcg/tcg-op-gvec.c
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@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
36
tcg_temp_free_i32(desc);
37
}
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39
+/* Generate a call to a gvec-style helper with five vector operands
40
+ and an extra pointer operand. */
41
+void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
42
+ uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
43
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
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+ gen_helper_gvec_5_ptr *fn)
45
+{
46
+ TCGv_ptr a0, a1, a2, a3, a4;
47
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
48
+
49
+ a0 = tcg_temp_new_ptr();
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+ a1 = tcg_temp_new_ptr();
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+ a2 = tcg_temp_new_ptr();
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+ a3 = tcg_temp_new_ptr();
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+ a4 = tcg_temp_new_ptr();
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+
55
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
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+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
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+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
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+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
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+ tcg_gen_addi_ptr(a4, cpu_env, eofs);
60
+
61
+ fn(a0, a1, a2, a3, a4, ptr, desc);
62
+
63
+ tcg_temp_free_ptr(a0);
64
+ tcg_temp_free_ptr(a1);
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+ tcg_temp_free_ptr(a2);
66
+ tcg_temp_free_ptr(a3);
67
+ tcg_temp_free_ptr(a4);
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+ tcg_temp_free_i32(desc);
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+}
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+
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/* Return true if we want to implement something of OPRSZ bytes
72
in units of LNSZ. This limits the expansion of inline code. */
73
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
74
--
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2.20.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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