1 | The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730: | 1 | Version 4: Drop the cpu_loop noreturn patch. |
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2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000) | 3 | |
4 | r~ | ||
5 | |||
6 | |||
7 | The following changes since commit 4c9af1ea1457782cf0adb293179335ef6de942aa: | ||
8 | |||
9 | gitlab-ci: Make more custom runner jobs manual, and don't allow failure (2021-09-14 17:03:03 +0100) | ||
4 | 10 | ||
5 | are available in the Git repository at: | 11 | are available in the Git repository at: |
6 | 12 | ||
7 | https://github.com/rth7680/qemu.git tags/pull-tcg-20200212 | 13 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914-4 |
8 | 14 | ||
9 | for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2: | 15 | for you to fetch changes up to e028eada62dbfcba134ac5afdefc3aa343ae202f: |
10 | 16 | ||
11 | tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800) | 17 | tcg/arm: More use of the TCGReg enum (2021-09-14 12:00:21 -0700) |
12 | 18 | ||
13 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
14 | Fix breakpoint invalidation. | 20 | Fix translation race condition for user-only. |
15 | Add support for tcg helpers with 7 arguments. | 21 | Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ. |
16 | Add support for gvec helpers with 5 arguments. | 22 | Fix tcg/arm tcg_out_vec_op signature. |
23 | Fix tcg/ppc (32bit) build with clang. | ||
24 | Remove dupluate TCG_KICK_PERIOD definition. | ||
25 | Remove unused tcg_global_reg_new. | ||
26 | Restrict cpu_exec_interrupt and its callees to sysemu. | ||
27 | Cleanups for tcg/arm. | ||
17 | 28 | ||
18 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
19 | Max Filippov (1): | 30 | Bin Meng (1): |
20 | exec: flush CPU TB cache in breakpoint_invalidate | 31 | tcg: Remove tcg_global_reg_new defines |
21 | 32 | ||
22 | Richard Henderson (1): | 33 | Ilya Leoshkevich (3): |
23 | tcg: Add tcg_gen_gvec_5_ptr | 34 | accel/tcg: Add DisasContextBase argument to translator_ld* |
35 | accel/tcg: Clear PAGE_WRITE before translation | ||
36 | accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts | ||
24 | 37 | ||
25 | Taylor Simpson (1): | 38 | Jose R. Ziviani (1): |
26 | tcg: Add support for a helper with 7 arguments | 39 | tcg/arm: Fix tcg_out_vec_op function signature |
27 | 40 | ||
28 | include/exec/helper-gen.h | 13 +++++++++++++ | 41 | Luc Michel (1): |
29 | include/exec/helper-head.h | 2 ++ | 42 | accel/tcg: remove redundant TCG_KICK_PERIOD define |
30 | include/exec/helper-proto.h | 6 ++++++ | ||
31 | include/exec/helper-tcg.h | 7 +++++++ | ||
32 | include/tcg/tcg-op-gvec.h | 7 +++++++ | ||
33 | exec.c | 15 +++++++-------- | ||
34 | tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++ | ||
35 | 7 files changed, 74 insertions(+), 8 deletions(-) | ||
36 | 43 | ||
44 | Philippe Mathieu-Daudé (24): | ||
45 | target/avr: Remove pointless use of CONFIG_USER_ONLY definition | ||
46 | target/i386: Restrict sysemu-only fpu_helper helpers | ||
47 | target/i386: Simplify TARGET_X86_64 #ifdef'ry | ||
48 | target/xtensa: Restrict do_transaction_failed() to sysemu | ||
49 | accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt | ||
50 | target/alpha: Restrict cpu_exec_interrupt() handler to sysemu | ||
51 | target/arm: Restrict cpu_exec_interrupt() handler to sysemu | ||
52 | target/cris: Restrict cpu_exec_interrupt() handler to sysemu | ||
53 | target/hppa: Restrict cpu_exec_interrupt() handler to sysemu | ||
54 | target/i386: Restrict cpu_exec_interrupt() handler to sysemu | ||
55 | target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder | ||
56 | target/m68k: Restrict cpu_exec_interrupt() handler to sysemu | ||
57 | target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu | ||
58 | target/mips: Restrict cpu_exec_interrupt() handler to sysemu | ||
59 | target/nios2: Restrict cpu_exec_interrupt() handler to sysemu | ||
60 | target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu | ||
61 | target/ppc: Restrict cpu_exec_interrupt() handler to sysemu | ||
62 | target/riscv: Restrict cpu_exec_interrupt() handler to sysemu | ||
63 | target/sh4: Restrict cpu_exec_interrupt() handler to sysemu | ||
64 | target/sparc: Restrict cpu_exec_interrupt() handler to sysemu | ||
65 | target/rx: Restrict cpu_exec_interrupt() handler to sysemu | ||
66 | target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu | ||
67 | accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu | ||
68 | user: Remove cpu_get_pic_interrupt() stubs | ||
69 | |||
70 | Richard Henderson (13): | ||
71 | tcg/i386: Split P_VEXW from P_REXW | ||
72 | tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN | ||
73 | tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF | ||
74 | tcg/arm: Remove fallback definition of __ARM_ARCH | ||
75 | tcg/arm: Standardize on tcg_out_<branch>_{reg,imm} | ||
76 | tcg/arm: Simplify use_armv5t_instructions | ||
77 | tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call | ||
78 | tcg/arm: Split out tcg_out_ldstm | ||
79 | tcg/arm: Simplify usage of encode_imm | ||
80 | tcg/arm: Drop inline markers | ||
81 | tcg/arm: Give enum arm_cond_code_e a typedef and use it | ||
82 | tcg/arm: More use of the ARMInsn enum | ||
83 | tcg/arm: More use of the TCGReg enum | ||
84 | |||
85 | include/exec/translate-all.h | 1 + | ||
86 | include/exec/translator.h | 44 +-- | ||
87 | include/hw/core/tcg-cpu-ops.h | 26 +- | ||
88 | include/tcg/tcg-op.h | 2 - | ||
89 | target/alpha/cpu.h | 2 +- | ||
90 | target/arm/arm_ldst.h | 12 +- | ||
91 | target/arm/cpu.h | 3 +- | ||
92 | target/cris/cpu.h | 2 +- | ||
93 | target/hppa/cpu.h | 4 +- | ||
94 | target/i386/cpu.h | 3 + | ||
95 | target/i386/tcg/helper-tcg.h | 2 + | ||
96 | target/m68k/cpu.h | 2 + | ||
97 | target/microblaze/cpu.h | 2 + | ||
98 | target/mips/tcg/tcg-internal.h | 5 +- | ||
99 | target/openrisc/cpu.h | 5 +- | ||
100 | target/ppc/cpu.h | 4 +- | ||
101 | target/riscv/cpu.h | 2 +- | ||
102 | target/rx/cpu.h | 2 + | ||
103 | target/sh4/cpu.h | 4 +- | ||
104 | target/xtensa/cpu.h | 2 + | ||
105 | tcg/arm/tcg-target.h | 27 +- | ||
106 | accel/tcg/cpu-exec.c | 14 +- | ||
107 | accel/tcg/tcg-accel-ops-rr.c | 2 - | ||
108 | accel/tcg/translate-all.c | 59 ++-- | ||
109 | accel/tcg/translator.c | 39 +++ | ||
110 | accel/tcg/user-exec.c | 48 ++- | ||
111 | bsd-user/i386/target_arch_cpu.c | 5 - | ||
112 | bsd-user/x86_64/target_arch_cpu.c | 5 - | ||
113 | linux-user/main.c | 7 - | ||
114 | target/alpha/cpu.c | 2 +- | ||
115 | target/alpha/helper.c | 5 +- | ||
116 | target/alpha/translate.c | 2 +- | ||
117 | target/arm/cpu.c | 7 +- | ||
118 | target/arm/cpu_tcg.c | 6 +- | ||
119 | target/arm/translate-a64.c | 2 +- | ||
120 | target/arm/translate.c | 9 +- | ||
121 | target/avr/cpu.c | 3 - | ||
122 | target/cris/cpu.c | 4 +- | ||
123 | target/cris/helper.c | 17 +- | ||
124 | target/hexagon/translate.c | 3 +- | ||
125 | target/hppa/cpu.c | 2 +- | ||
126 | target/hppa/int_helper.c | 7 +- | ||
127 | target/hppa/translate.c | 5 +- | ||
128 | target/i386/tcg/seg_helper.c | 74 +---- | ||
129 | target/i386/tcg/sysemu/seg_helper.c | 62 ++++ | ||
130 | target/i386/tcg/tcg-cpu.c | 8 +- | ||
131 | target/i386/tcg/translate.c | 10 +- | ||
132 | target/m68k/cpu.c | 2 +- | ||
133 | target/m68k/op_helper.c | 16 +- | ||
134 | target/m68k/translate.c | 2 +- | ||
135 | target/microblaze/cpu.c | 2 +- | ||
136 | target/microblaze/helper.c | 13 +- | ||
137 | target/mips/cpu.c | 2 +- | ||
138 | target/mips/tcg/exception.c | 18 -- | ||
139 | target/mips/tcg/sysemu/tlb_helper.c | 18 ++ | ||
140 | target/mips/tcg/translate.c | 8 +- | ||
141 | target/mips/tcg/user/tlb_helper.c | 5 - | ||
142 | target/nios2/cpu.c | 5 +- | ||
143 | target/openrisc/cpu.c | 2 +- | ||
144 | target/openrisc/interrupt.c | 2 - | ||
145 | target/openrisc/translate.c | 2 +- | ||
146 | target/ppc/cpu_init.c | 2 +- | ||
147 | target/ppc/excp_helper.c | 21 +- | ||
148 | target/ppc/translate.c | 5 +- | ||
149 | target/riscv/cpu.c | 2 +- | ||
150 | target/riscv/cpu_helper.c | 5 - | ||
151 | target/riscv/translate.c | 5 +- | ||
152 | target/rx/cpu.c | 2 +- | ||
153 | target/rx/helper.c | 4 + | ||
154 | target/s390x/tcg/translate.c | 16 +- | ||
155 | target/sh4/cpu.c | 2 +- | ||
156 | target/sh4/helper.c | 9 +- | ||
157 | target/sh4/translate.c | 4 +- | ||
158 | target/sparc/cpu.c | 4 +- | ||
159 | target/sparc/translate.c | 2 +- | ||
160 | target/xtensa/cpu.c | 2 +- | ||
161 | target/xtensa/exc_helper.c | 7 +- | ||
162 | target/xtensa/translate.c | 5 +- | ||
163 | target/mips/tcg/micromips_translate.c.inc | 2 +- | ||
164 | target/mips/tcg/mips16e_translate.c.inc | 4 +- | ||
165 | target/mips/tcg/nanomips_translate.c.inc | 4 +- | ||
166 | tcg/arm/tcg-target.c.inc | 517 ++++++++++++++++-------------- | ||
167 | tcg/i386/tcg-target.c.inc | 13 +- | ||
168 | tcg/ppc/tcg-target.c.inc | 25 +- | ||
169 | target/openrisc/meson.build | 6 +- | ||
170 | 85 files changed, 700 insertions(+), 628 deletions(-) | ||
171 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Max Filippov <jcmvbkbc@gmail.com> | ||
2 | 1 | ||
3 | When a breakpoint is inserted at location for which there's currently no | ||
4 | virtual to physical translation no action is taken on CPU TB cache. If a | ||
5 | TB for that virtual address already exists but is not visible ATM the | ||
6 | breakpoint won't be hit next time an instruction at that address will be | ||
7 | executed. | ||
8 | |||
9 | Flush entire CPU TB cache in breakpoint_invalidate to force | ||
10 | re-translation of all TBs for the breakpoint address. | ||
11 | |||
12 | This change fixes the following scenario: | ||
13 | - linux user application is running | ||
14 | - a breakpoint is inserted from QEMU gdbstub for a user address that is | ||
15 | not currently present in the target CPU TLB | ||
16 | - an instruction at that address is executed, but the external debugger | ||
17 | doesn't get control. | ||
18 | |||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | ||
21 | Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com> | ||
22 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | --- | ||
24 | exec.c | 15 +++++++-------- | ||
25 | 1 file changed, 7 insertions(+), 8 deletions(-) | ||
26 | |||
27 | diff --git a/exec.c b/exec.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/exec.c | ||
30 | +++ b/exec.c | ||
31 | @@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) | ||
32 | |||
33 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | ||
34 | { | ||
35 | - MemTxAttrs attrs; | ||
36 | - hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | ||
37 | - int asidx = cpu_asidx_from_attrs(cpu, attrs); | ||
38 | - if (phys != -1) { | ||
39 | - /* Locks grabbed by tb_invalidate_phys_addr */ | ||
40 | - tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | ||
41 | - phys | (pc & ~TARGET_PAGE_MASK), attrs); | ||
42 | - } | ||
43 | + /* | ||
44 | + * There may not be a virtual to physical translation for the pc | ||
45 | + * right now, but there may exist cached TB for this pc. | ||
46 | + * Flush the whole TB cache to force re-translation of such TBs. | ||
47 | + * This is heavyweight, but we're debugging anyway. | ||
48 | + */ | ||
49 | + tb_flush(cpu); | ||
50 | } | ||
51 | #endif | ||
52 | |||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Taylor Simpson <tsimpson@quicinc.com> | ||
2 | 1 | ||
3 | Currently, helpers can only take up to 6 arguments. This patch adds the | ||
4 | capability for up to 7 arguments. I have tested it with the Hexagon port | ||
5 | that I am preparing for submission. | ||
6 | |||
7 | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> | ||
8 | Message-Id: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | include/exec/helper-gen.h | 13 +++++++++++++ | ||
12 | include/exec/helper-head.h | 2 ++ | ||
13 | include/exec/helper-proto.h | 6 ++++++ | ||
14 | include/exec/helper-tcg.h | 7 +++++++ | ||
15 | 4 files changed, 28 insertions(+) | ||
16 | |||
17 | diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/exec/helper-gen.h | ||
20 | +++ b/include/exec/helper-gen.h | ||
21 | @@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ | ||
22 | tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ | ||
23 | } | ||
24 | |||
25 | +#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ | ||
26 | +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ | ||
27 | + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ | ||
28 | + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ | ||
29 | + dh_arg_decl(t7, 7)) \ | ||
30 | +{ \ | ||
31 | + TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ | ||
32 | + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ | ||
33 | + dh_arg(t7, 7) }; \ | ||
34 | + tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \ | ||
35 | +} | ||
36 | + | ||
37 | #include "helper.h" | ||
38 | #include "trace/generated-helpers.h" | ||
39 | #include "trace/generated-helpers-wrappers.h" | ||
40 | @@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ | ||
41 | #undef DEF_HELPER_FLAGS_4 | ||
42 | #undef DEF_HELPER_FLAGS_5 | ||
43 | #undef DEF_HELPER_FLAGS_6 | ||
44 | +#undef DEF_HELPER_FLAGS_7 | ||
45 | #undef GEN_HELPER | ||
46 | |||
47 | #endif /* HELPER_GEN_H */ | ||
48 | diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/include/exec/helper-head.h | ||
51 | +++ b/include/exec/helper-head.h | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) | ||
54 | #define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \ | ||
55 | DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6) | ||
56 | +#define DEF_HELPER_7(name, ret, t1, t2, t3, t4, t5, t6, t7) \ | ||
57 | + DEF_HELPER_FLAGS_7(name, 0, ret, t1, t2, t3, t4, t5, t6, t7) | ||
58 | |||
59 | /* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */ | ||
60 | |||
61 | diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/include/exec/helper-proto.h | ||
64 | +++ b/include/exec/helper-proto.h | ||
65 | @@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ | ||
66 | dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ | ||
67 | dh_ctype(t4), dh_ctype(t5), dh_ctype(t6)); | ||
68 | |||
69 | +#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \ | ||
70 | +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ | ||
71 | + dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \ | ||
72 | + dh_ctype(t7)); | ||
73 | + | ||
74 | #include "helper.h" | ||
75 | #include "trace/generated-helpers.h" | ||
76 | #include "tcg-runtime.h" | ||
77 | @@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ | ||
78 | #undef DEF_HELPER_FLAGS_4 | ||
79 | #undef DEF_HELPER_FLAGS_5 | ||
80 | #undef DEF_HELPER_FLAGS_6 | ||
81 | +#undef DEF_HELPER_FLAGS_7 | ||
82 | |||
83 | #endif /* HELPER_PROTO_H */ | ||
84 | diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/include/exec/helper-tcg.h | ||
87 | +++ b/include/exec/helper-tcg.h | ||
88 | @@ -XXX,XX +XXX,XX @@ | ||
89 | | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | ||
90 | | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, | ||
91 | |||
92 | +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ | ||
93 | + { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ | ||
94 | + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | ||
95 | + | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | ||
96 | + | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) }, | ||
97 | + | ||
98 | #include "helper.h" | ||
99 | #include "trace/generated-helpers.h" | ||
100 | #include "tcg-runtime.h" | ||
101 | @@ -XXX,XX +XXX,XX @@ | ||
102 | #undef DEF_HELPER_FLAGS_4 | ||
103 | #undef DEF_HELPER_FLAGS_5 | ||
104 | #undef DEF_HELPER_FLAGS_6 | ||
105 | +#undef DEF_HELPER_FLAGS_7 | ||
106 | |||
107 | #endif /* HELPER_TCG_H */ | ||
108 | -- | ||
109 | 2.20.1 | ||
110 | |||
111 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Extend the vector generator infrastructure to handle | ||
2 | 5 vector arguments. | ||
3 | 1 | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | --- | ||
9 | include/tcg/tcg-op-gvec.h | 7 +++++++ | ||
10 | tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++ | ||
11 | 2 files changed, 39 insertions(+) | ||
12 | |||
13 | diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/tcg/tcg-op-gvec.h | ||
16 | +++ b/include/tcg/tcg-op-gvec.h | ||
17 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
18 | uint32_t maxsz, int32_t data, | ||
19 | gen_helper_gvec_4_ptr *fn); | ||
20 | |||
21 | +typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, | ||
22 | + TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
23 | +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
24 | + uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, | ||
25 | + uint32_t oprsz, uint32_t maxsz, int32_t data, | ||
26 | + gen_helper_gvec_5_ptr *fn); | ||
27 | + | ||
28 | /* Expand a gvec operation. Either inline or out-of-line depending on | ||
29 | the actual vector size and the operations supported by the host. */ | ||
30 | typedef struct { | ||
31 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/tcg/tcg-op-gvec.c | ||
34 | +++ b/tcg/tcg-op-gvec.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
36 | tcg_temp_free_i32(desc); | ||
37 | } | ||
38 | |||
39 | +/* Generate a call to a gvec-style helper with five vector operands | ||
40 | + and an extra pointer operand. */ | ||
41 | +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
42 | + uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, | ||
43 | + uint32_t oprsz, uint32_t maxsz, int32_t data, | ||
44 | + gen_helper_gvec_5_ptr *fn) | ||
45 | +{ | ||
46 | + TCGv_ptr a0, a1, a2, a3, a4; | ||
47 | + TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
48 | + | ||
49 | + a0 = tcg_temp_new_ptr(); | ||
50 | + a1 = tcg_temp_new_ptr(); | ||
51 | + a2 = tcg_temp_new_ptr(); | ||
52 | + a3 = tcg_temp_new_ptr(); | ||
53 | + a4 = tcg_temp_new_ptr(); | ||
54 | + | ||
55 | + tcg_gen_addi_ptr(a0, cpu_env, dofs); | ||
56 | + tcg_gen_addi_ptr(a1, cpu_env, aofs); | ||
57 | + tcg_gen_addi_ptr(a2, cpu_env, bofs); | ||
58 | + tcg_gen_addi_ptr(a3, cpu_env, cofs); | ||
59 | + tcg_gen_addi_ptr(a4, cpu_env, eofs); | ||
60 | + | ||
61 | + fn(a0, a1, a2, a3, a4, ptr, desc); | ||
62 | + | ||
63 | + tcg_temp_free_ptr(a0); | ||
64 | + tcg_temp_free_ptr(a1); | ||
65 | + tcg_temp_free_ptr(a2); | ||
66 | + tcg_temp_free_ptr(a3); | ||
67 | + tcg_temp_free_ptr(a4); | ||
68 | + tcg_temp_free_i32(desc); | ||
69 | +} | ||
70 | + | ||
71 | /* Return true if we want to implement something of OPRSZ bytes | ||
72 | in units of LNSZ. This limits the expansion of inline code. */ | ||
73 | static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) | ||
74 | -- | ||
75 | 2.20.1 | ||
76 | |||
77 | diff view generated by jsdifflib |