1 | target-arm queue. The big thing here is the landing of the 3-phase | 1 | Hi; here's the first target-arm pullreq for the 7.0 cycle. |
---|---|---|---|
2 | reset patches... | ||
3 | 2 | ||
3 | thanks | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit 204aa60b37c23a89e690d418f49787d274303ca7: | 6 | The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging (2020-01-30 14:18:45 +0000) | 8 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200130 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215 |
13 | 13 | ||
14 | for you to fetch changes up to dea101a1ae9968c9fec6ab0291489dad7c49f36f: | 14 | for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359: |
15 | 15 | ||
16 | target/arm/cpu: Add the kvm-no-adjvtime CPU property (2020-01-30 16:02:06 +0000) | 16 | tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES | 20 | * ITS: error reporting cleanup |
21 | * target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr | 21 | * aspeed: improve documentation |
22 | * aspeed: some minor bugfixes | 22 | * Fix STM32F2XX USART data register readout |
23 | * aspeed: add eMMC controller model for AST2600 SoC | 23 | * allow emulated GICv3 to be disabled in non-TCG builds |
24 | * hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' | 24 | * fix exception priority for singlestep, misaligned PC, bp, etc |
25 | * New 3-phase reset API for device models | 25 | * Correct calculation of tlb range invalidate length |
26 | * hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit | 26 | * npcm7xx_emc: fix missing queue_flush |
27 | * Arm KVM: stop/restart the guest counter when the VM is stopped and started | 27 | * virt: Add VIOT ACPI table for virtio-iommu |
28 | * target/i386: Use assert() to sanity-check b1 in SSE decode | ||
29 | * Don't include qemu-common unnecessarily | ||
28 | 30 | ||
29 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
30 | Andrew Jeffery (2): | 32 | Alex Bennée (1): |
31 | hw/sd: Configure number of slots exposed by the ASPEED SDHCI model | 33 | hw/intc: clean-up error reporting for failed ITS cmd |
32 | hw/arm: ast2600: Wire up the eMMC controller | ||
33 | 34 | ||
34 | Andrew Jones (6): | 35 | Jean-Philippe Brucker (8): |
35 | target/arm/kvm: trivial: Clean up header documentation | 36 | hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu |
36 | hw/arm/virt: Add missing 5.0 options call to 4.2 options | 37 | hw/arm/virt: Remove device tree restriction for virtio-iommu |
37 | target/arm/kvm64: kvm64 cpus have timer registers | 38 | hw/arm/virt: Reject instantiation of multiple IOMMUs |
38 | tests/arm-cpu-features: Check feature default values | 39 | hw/arm/virt: Use object_property_set instead of qdev_prop_set |
39 | target/arm/kvm: Implement virtual time adjustment | 40 | tests/acpi: allow updates of VIOT expected data files |
40 | target/arm/cpu: Add the kvm-no-adjvtime CPU property | 41 | tests/acpi: add test case for VIOT |
42 | tests/acpi: add expected blobs for VIOT test on q35 machine | ||
43 | tests/acpi: add expected blob for VIOT test on virt machine | ||
41 | 44 | ||
42 | Cédric Le Goater (2): | 45 | Joel Stanley (4): |
43 | ftgmac100: check RX and TX buffer alignment | 46 | docs: aspeed: Add new boards |
44 | hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 | 47 | docs: aspeed: Update OpenBMC image URL |
48 | docs: aspeed: Give an example of booting a kernel | ||
49 | docs: aspeed: ADC is now modelled | ||
45 | 50 | ||
46 | Damien Hedde (11): | 51 | Olivier Hériveaux (1): |
47 | add device_legacy_reset function to prepare for reset api change | 52 | Fix STM32F2XX USART data register readout |
48 | hw/core/qdev: add trace events to help with resettable transition | ||
49 | hw/core: create Resettable QOM interface | ||
50 | hw/core: add Resettable support to BusClass and DeviceClass | ||
51 | hw/core/resettable: add support for changing parent | ||
52 | hw/core/qdev: handle parent bus change regarding resettable | ||
53 | hw/core/qdev: update hotplug reset regarding resettable | ||
54 | hw/core: deprecate old reset functions and introduce new ones | ||
55 | docs/devel/reset.rst: add doc about Resettable interface | ||
56 | vl: replace deprecated qbus_reset_all registration | ||
57 | hw/s390x/ipl: replace deprecated qdev_reset_all registration | ||
58 | 53 | ||
59 | Joel Stanley (1): | 54 | Patrick Venture (1): |
60 | misc/pca9552: Add qom set and get | 55 | hw/net: npcm7xx_emc fix missing queue_flush |
61 | 56 | ||
62 | Peter Maydell (2): | 57 | Peter Maydell (6): |
63 | hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES | 58 | target/i386: Use assert() to sanity-check b1 in SSE decode |
64 | target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr | 59 | include/hw/i386: Don't include qemu-common.h in .h files |
60 | target/hexagon/cpu.h: don't include qemu-common.h | ||
61 | target/rx/cpu.h: Don't include qemu-common.h | ||
62 | hw/arm: Don't include qemu-common.h unnecessarily | ||
63 | target/arm: Correct calculation of tlb range invalidate length | ||
65 | 64 | ||
66 | Philippe Mathieu-Daudé (1): | 65 | Philippe Mathieu-Daudé (2): |
67 | hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' | 66 | hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c |
67 | hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector | ||
68 | 68 | ||
69 | Zenghui Yu (1): | 69 | Richard Henderson (10): |
70 | hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit | 70 | target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn |
71 | target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn | ||
72 | target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn | ||
73 | target/arm: Split arm_pre_translate_insn | ||
74 | target/arm: Advance pc for arch single-step exception | ||
75 | target/arm: Split compute_fsr_fsc out of arm_deliver_fault | ||
76 | target/arm: Take an exception if PC is misaligned | ||
77 | target/arm: Assert thumb pc is aligned | ||
78 | target/arm: Suppress bp for exceptions with more priority | ||
79 | tests/tcg: Add arm and aarch64 pc alignment tests | ||
71 | 80 | ||
72 | hw/core/Makefile.objs | 1 + | 81 | docs/system/arm/aspeed.rst | 26 ++++++++++++---- |
73 | tests/Makefile.include | 1 + | 82 | include/hw/i386/microvm.h | 1 - |
74 | include/hw/arm/aspeed.h | 2 + | 83 | include/hw/i386/x86.h | 1 - |
75 | include/hw/arm/aspeed_soc.h | 2 + | 84 | target/arm/helper.h | 1 + |
76 | include/hw/arm/virt.h | 1 + | 85 | target/arm/syndrome.h | 5 +++ |
77 | include/hw/qdev-core.h | 58 +++++++- | 86 | target/hexagon/cpu.h | 1 - |
78 | include/hw/resettable.h | 247 +++++++++++++++++++++++++++++++++ | 87 | target/rx/cpu.h | 1 - |
79 | include/hw/sd/aspeed_sdhci.h | 1 + | 88 | hw/arm/boot.c | 1 - |
80 | target/arm/cpu.h | 7 + | 89 | hw/arm/digic_boards.c | 1 - |
81 | target/arm/kvm_arm.h | 95 ++++++++++--- | 90 | hw/arm/highbank.c | 1 - |
82 | hw/arm/aspeed.c | 72 ++++++++-- | 91 | hw/arm/npcm7xx_boards.c | 1 - |
83 | hw/arm/aspeed_ast2600.c | 31 ++++- | 92 | hw/arm/sbsa-ref.c | 1 - |
84 | hw/arm/aspeed_soc.c | 2 + | 93 | hw/arm/stm32f405_soc.c | 1 - |
85 | hw/arm/raspi.c | 2 - | 94 | hw/arm/vexpress.c | 1 - |
86 | hw/arm/virt.c | 9 ++ | 95 | hw/arm/virt-acpi-build.c | 7 +++++ |
87 | hw/audio/intel-hda.c | 2 +- | 96 | hw/arm/virt.c | 21 ++++++------- |
88 | hw/core/bus.c | 102 ++++++++++++++ | 97 | hw/char/stm32f2xx_usart.c | 3 +- |
89 | hw/core/or-irq.c | 2 +- | 98 | hw/intc/arm_gicv3.c | 2 +- |
90 | hw/core/qdev.c | 160 ++++++++++++++++++++-- | 99 | hw/intc/arm_gicv3_cpuif.c | 10 +----- |
91 | hw/core/resettable.c | 301 +++++++++++++++++++++++++++++++++++++++++ | 100 | hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++ |
92 | hw/hyperv/hyperv.c | 2 +- | 101 | hw/intc/arm_gicv3_its.c | 39 +++++++++++++++-------- |
93 | hw/i386/microvm.c | 2 +- | 102 | hw/net/npcm7xx_emc.c | 18 +++++------ |
94 | hw/i386/pc.c | 2 +- | 103 | hw/virtio/virtio-iommu-pci.c | 12 ++------ |
95 | hw/ide/microdrive.c | 8 +- | 104 | linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------ |
96 | hw/intc/arm_gicv3_kvm.c | 11 +- | 105 | linux-user/hexagon/cpu_loop.c | 1 + |
97 | hw/intc/spapr_xive.c | 2 +- | 106 | target/arm/debug_helper.c | 23 ++++++++++++++ |
98 | hw/misc/pca9552.c | 90 ++++++++++++ | 107 | target/arm/gdbstub.c | 9 ++++-- |
99 | hw/net/ftgmac100.c | 13 ++ | 108 | target/arm/helper.c | 6 ++-- |
100 | hw/ppc/pnv_psi.c | 4 +- | 109 | target/arm/machine.c | 10 ++++++ |
101 | hw/ppc/spapr_pci.c | 2 +- | 110 | target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++---------- |
102 | hw/ppc/spapr_vio.c | 2 +- | 111 | target/arm/translate-a64.c | 23 ++++++++++++-- |
103 | hw/s390x/ipl.c | 10 +- | 112 | target/arm/translate.c | 58 ++++++++++++++++++++++++++--------- |
104 | hw/s390x/s390-pci-inst.c | 2 +- | 113 | target/i386/tcg/translate.c | 12 ++------ |
105 | hw/scsi/vmw_pvscsi.c | 2 +- | 114 | tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++ |
106 | hw/sd/aspeed_sdhci.c | 11 +- | 115 | tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++ |
107 | hw/sd/omap_mmc.c | 2 +- | 116 | tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++ |
108 | hw/sd/pl181.c | 2 +- | 117 | hw/arm/Kconfig | 1 + |
109 | target/arm/arm-semi.c | 9 ++ | 118 | hw/intc/Kconfig | 5 +++ |
110 | target/arm/cpu.c | 2 + | 119 | hw/intc/meson.build | 11 ++++--- |
111 | target/arm/cpu64.c | 1 + | 120 | tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes |
112 | target/arm/kvm.c | 120 ++++++++++++++++ | 121 | tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes |
113 | target/arm/kvm32.c | 3 + | 122 | tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes |
114 | target/arm/kvm64.c | 4 + | 123 | tests/tcg/aarch64/Makefile.target | 4 +-- |
115 | target/arm/machine.c | 7 + | 124 | tests/tcg/arm/Makefile.target | 4 +++ |
116 | target/arm/monitor.c | 1 + | 125 | 44 files changed, 429 insertions(+), 145 deletions(-) |
117 | tests/qtest/arm-cpu-features.c | 41 ++++-- | 126 | create mode 100644 hw/intc/arm_gicv3_cpuif_common.c |
118 | vl.c | 10 +- | 127 | create mode 100644 tests/tcg/aarch64/pcalign-a64.c |
119 | docs/arm-cpu-features.rst | 37 ++++- | 128 | create mode 100644 tests/tcg/arm/pcalign-a32.c |
120 | docs/devel/index.rst | 1 + | 129 | create mode 100644 tests/data/acpi/q35/DSDT.viot |
121 | docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++ | 130 | create mode 100644 tests/data/acpi/q35/VIOT.viot |
122 | hw/core/trace-events | 27 ++++ | 131 | create mode 100644 tests/data/acpi/virt/VIOT |
123 | 51 files changed, 1727 insertions(+), 90 deletions(-) | ||
124 | create mode 100644 include/hw/resettable.h | ||
125 | create mode 100644 hw/core/resettable.c | ||
126 | create mode 100644 docs/devel/reset.rst | ||
127 | 132 | diff view generated by jsdifflib |
1 | From: Andrew Jeffery <andrew@aj.id.au> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The AST2600 includes a second cut-down version of the SD/MMC controller | 3 | While trying to debug a GIC ITS failure I saw some guest errors that |
4 | found in the AST2500, named the eMMC controller. It's cut down in the | 4 | had poor formatting as well as leaving me confused as to what failed. |
5 | sense that it only supports one slot rather than two, but it brings the | 5 | As most of the checks aren't possible without a valid dte split that |
6 | total number of slots supported by the AST2600 to three. | 6 | check apart and then check the other conditions in steps. This avoids |
7 | us relying on undefined data. | ||
7 | 8 | ||
8 | The existing code assumed that the SD controller always provided two | 9 | I still get a failure with the current kvm-unit-tests but at least I |
9 | slots. Rework the SDHCI object to expose the number of slots as a | 10 | know (partially) why now: |
10 | property to be set by the SoC configuration. | ||
11 | 11 | ||
12 | Signed-off-by: Andrew Jeffery <andrew@aj.id.au> | 12 | Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588 |
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 13 | PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI |
14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 14 | ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0 |
15 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 15 | INT dev_id=2 event_id=20 |
16 | Message-id: 20200114103433.30534-2-clg@kaod.org | 16 | process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0) |
17 | [PMM: fixed up to use device_class_set_props()] | 17 | PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap |
18 | SUMMARY: 6 tests, 1 unexpected failures | ||
19 | |||
20 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org | ||
23 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | ||
24 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 26 | --- |
20 | include/hw/sd/aspeed_sdhci.h | 1 + | 27 | hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------ |
21 | hw/arm/aspeed.c | 2 +- | 28 | 1 file changed, 27 insertions(+), 12 deletions(-) |
22 | hw/arm/aspeed_ast2600.c | 2 ++ | ||
23 | hw/arm/aspeed_soc.c | 2 ++ | ||
24 | hw/sd/aspeed_sdhci.c | 11 +++++++++-- | ||
25 | 5 files changed, 15 insertions(+), 3 deletions(-) | ||
26 | 29 | ||
27 | diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h | 30 | diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c |
28 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/include/hw/sd/aspeed_sdhci.h | 32 | --- a/hw/intc/arm_gicv3_its.c |
30 | +++ b/include/hw/sd/aspeed_sdhci.h | 33 | +++ b/hw/intc/arm_gicv3_its.c |
31 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDHCIState { | 34 | @@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, |
32 | SysBusDevice parent; | 35 | if (res != MEMTX_OK) { |
33 | 36 | return result; | |
34 | SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; | 37 | } |
35 | + uint8_t num_slots; | 38 | + } else { |
36 | 39 | + qemu_log_mask(LOG_GUEST_ERROR, | |
37 | MemoryRegion iomem; | 40 | + "%s: invalid command attributes: " |
38 | qemu_irq irq; | 41 | + "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n", |
39 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 42 | + __func__, dte, devid, res); |
40 | index XXXXXXX..XXXXXXX 100644 | 43 | + return result; |
41 | --- a/hw/arm/aspeed.c | ||
42 | +++ b/hw/arm/aspeed.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
44 | amc->i2c_init(bmc); | ||
45 | } | 44 | } |
46 | 45 | ||
47 | - for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { | 46 | - if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || |
48 | + for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { | 47 | - !cte_valid || (eventid > max_eventid)) { |
49 | SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; | ||
50 | DriveInfo *dinfo = drive_get_next(IF_SD); | ||
51 | BlockBackend *blk; | ||
52 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/hw/arm/aspeed_ast2600.c | ||
55 | +++ b/hw/arm/aspeed_ast2600.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
57 | sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | ||
58 | TYPE_ASPEED_SDHCI); | ||
59 | |||
60 | + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); | ||
61 | + | 48 | + |
62 | /* Init sd card slot class here so that they're under the correct parent */ | 49 | + /* |
63 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | 50 | + * In this implementation, in case of guest errors we ignore the |
64 | sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | 51 | + * command and move onto the next command in the queue. |
65 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 52 | + */ |
66 | index XXXXXXX..XXXXXXX 100644 | 53 | + if (devid > s->dt.maxids.max_devids) { |
67 | --- a/hw/arm/aspeed_soc.c | 54 | qemu_log_mask(LOG_GUEST_ERROR, |
68 | +++ b/hw/arm/aspeed_soc.c | 55 | - "%s: invalid command attributes " |
69 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | 56 | - "devid %d or eventid %d or invalid dte %d or" |
70 | sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | 57 | - "invalid cte %d or invalid ite %d\n", |
71 | TYPE_ASPEED_SDHCI); | 58 | - __func__, devid, eventid, dte_valid, cte_valid, |
72 | 59 | - ite_valid); | |
73 | + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); | 60 | - /* |
61 | - * in this implementation, in case of error | ||
62 | - * we ignore this command and move onto the next | ||
63 | - * command in the queue | ||
64 | - */ | ||
65 | + "%s: invalid command attributes: devid %d>%d", | ||
66 | + __func__, devid, s->dt.maxids.max_devids); | ||
74 | + | 67 | + |
75 | /* Init sd card slot class here so that they're under the correct parent */ | 68 | + } else if (!dte_valid || !ite_valid || !cte_valid) { |
76 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | 69 | + qemu_log_mask(LOG_GUEST_ERROR, |
77 | sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | 70 | + "%s: invalid command attributes: " |
78 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c | 71 | + "dte: %s, ite: %s, cte: %s\n", |
79 | index XXXXXXX..XXXXXXX 100644 | 72 | + __func__, |
80 | --- a/hw/sd/aspeed_sdhci.c | 73 | + dte_valid ? "valid" : "invalid", |
81 | +++ b/hw/sd/aspeed_sdhci.c | 74 | + ite_valid ? "valid" : "invalid", |
82 | @@ -XXX,XX +XXX,XX @@ | 75 | + cte_valid ? "valid" : "invalid"); |
83 | #include "qapi/error.h" | 76 | + } else if (eventid > max_eventid) { |
84 | #include "hw/irq.h" | 77 | + qemu_log_mask(LOG_GUEST_ERROR, |
85 | #include "migration/vmstate.h" | 78 | + "%s: invalid command attributes: eventid %d > %d\n", |
86 | +#include "hw/qdev-properties.h" | 79 | + __func__, eventid, max_eventid); |
87 | 80 | } else { | |
88 | #define ASPEED_SDHCI_INFO 0x00 | 81 | /* |
89 | #define ASPEED_SDHCI_INFO_RESET 0x00030000 | 82 | * Current implementation only supports rdbase == procnum |
90 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) | ||
91 | |||
92 | /* Create input irqs for the slots */ | ||
93 | qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, | ||
94 | - sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); | ||
95 | + sdhci, NULL, sdhci->num_slots); | ||
96 | |||
97 | sysbus_init_irq(sbd, &sdhci->irq); | ||
98 | memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, | ||
99 | sdhci, TYPE_ASPEED_SDHCI, 0x1000); | ||
100 | sysbus_init_mmio(sbd, &sdhci->iomem); | ||
101 | |||
102 | - for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | ||
103 | + for (int i = 0; i < sdhci->num_slots; ++i) { | ||
104 | Object *sdhci_slot = OBJECT(&sdhci->slots[i]); | ||
105 | SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); | ||
106 | |||
107 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdhci = { | ||
108 | }, | ||
109 | }; | ||
110 | |||
111 | +static Property aspeed_sdhci_properties[] = { | ||
112 | + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), | ||
113 | + DEFINE_PROP_END_OF_LIST(), | ||
114 | +}; | ||
115 | + | ||
116 | static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) | ||
117 | { | ||
118 | DeviceClass *dc = DEVICE_CLASS(classp); | ||
119 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) | ||
120 | dc->realize = aspeed_sdhci_realize; | ||
121 | dc->reset = aspeed_sdhci_reset; | ||
122 | dc->vmsd = &vmstate_aspeed_sdhci; | ||
123 | + device_class_set_props(dc, aspeed_sdhci_properties); | ||
124 | } | ||
125 | |||
126 | static TypeInfo aspeed_sdhci_info = { | ||
127 | -- | 83 | -- |
128 | 2.20.1 | 84 | 2.25.1 |
129 | 85 | ||
130 | 86 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | 2 | ||
3 | Following the pattern of the work recently done with the ASPEED GPIO | 3 | Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be |
4 | model, this adds support for inspecting and modifying the PCA9552 LEDs | 4 | removed in v7.0. |
5 | from the monitor. | ||
6 | |||
7 | (qemu) qom-set /machine/unattached/device[17] led0 on | ||
8 | (qemu) qom-set /machine/unattached/device[17] led0 off | ||
9 | (qemu) qom-set /machine/unattached/device[17] led0 pwm0 | ||
10 | (qemu) qom-set /machine/unattached/device[17] led0 pwm1 | ||
11 | 5 | ||
12 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 6 | Signed-off-by: Joel Stanley <joel@jms.id.au> |
13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
14 | Message-id: 20200114103433.30534-6-clg@kaod.org | 8 | Message-id: 20211117065752.330632-2-joel@jms.id.au |
15 | [clg: - removed the "qom-get" examples from the commit log | ||
16 | - merged memory leak fixes from Joel ] | ||
17 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 10 | --- |
21 | hw/misc/pca9552.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++ | 11 | docs/system/arm/aspeed.rst | 7 ++++++- |
22 | 1 file changed, 90 insertions(+) | 12 | 1 file changed, 6 insertions(+), 1 deletion(-) |
23 | 13 | ||
24 | diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
25 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/misc/pca9552.c | 16 | --- a/docs/system/arm/aspeed.rst |
27 | +++ b/hw/misc/pca9552.c | 17 | +++ b/docs/system/arm/aspeed.rst |
28 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines : |
29 | #include "hw/misc/pca9552.h" | 19 | |
30 | #include "hw/misc/pca9552_regs.h" | 20 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC |
31 | #include "migration/vmstate.h" | 21 | - ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
32 | +#include "qapi/error.h" | 22 | +- ``supermicrox11-bmc`` Supermicro X11 BMC |
33 | +#include "qapi/visitor.h" | 23 | |
34 | 24 | AST2500 SoC based machines : | |
35 | #define PCA9552_LED_ON 0x0 | 25 | |
36 | #define PCA9552_LED_OFF 0x1 | 26 | @@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines : |
37 | #define PCA9552_LED_PWM0 0x2 | 27 | - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC |
38 | #define PCA9552_LED_PWM1 0x3 | 28 | - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC |
39 | 29 | - ``sonorapass-bmc`` OCP SonoraPass BMC | |
40 | +static const char *led_state[] = {"on", "off", "pwm0", "pwm1"}; | 30 | -- ``swift-bmc`` OpenPOWER Swift BMC POWER9 |
41 | + | 31 | +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0) |
42 | static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin) | 32 | +- ``fp5280g2-bmc`` Inspur FP5280G2 BMC |
43 | { | 33 | +- ``g220a-bmc`` Bytedance G220A BMC |
44 | uint8_t reg = PCA9552_LS0 + (pin / 4); | 34 | |
45 | @@ -XXX,XX +XXX,XX @@ static int pca9552_event(I2CSlave *i2c, enum i2c_event event) | 35 | AST2600 SoC based machines : |
46 | return 0; | 36 | |
47 | } | 37 | - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) |
48 | 38 | - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC | |
49 | +static void pca9552_get_led(Object *obj, Visitor *v, const char *name, | 39 | +- ``rainier-bmc`` IBM Rainier POWER10 BMC |
50 | + void *opaque, Error **errp) | 40 | +- ``fuji-bmc`` Facebook Fuji BMC |
51 | +{ | 41 | |
52 | + PCA9552State *s = PCA9552(obj); | 42 | Supported devices |
53 | + int led, rc, reg; | 43 | ----------------- |
54 | + uint8_t state; | ||
55 | + | ||
56 | + rc = sscanf(name, "led%2d", &led); | ||
57 | + if (rc != 1) { | ||
58 | + error_setg(errp, "%s: error reading %s", __func__, name); | ||
59 | + return; | ||
60 | + } | ||
61 | + if (led < 0 || led > s->nr_leds) { | ||
62 | + error_setg(errp, "%s invalid led %s", __func__, name); | ||
63 | + return; | ||
64 | + } | ||
65 | + /* | ||
66 | + * Get the LSx register as the qom interface should expose the device | ||
67 | + * state, not the modeled 'input line' behaviour which would come from | ||
68 | + * reading the INPUTx reg | ||
69 | + */ | ||
70 | + reg = PCA9552_LS0 + led / 4; | ||
71 | + state = (pca9552_read(s, reg) >> (led % 8)) & 0x3; | ||
72 | + visit_type_str(v, name, (char **)&led_state[state], errp); | ||
73 | +} | ||
74 | + | ||
75 | +/* | ||
76 | + * Return an LED selector register value based on an existing one, with | ||
77 | + * the appropriate 2-bit state value set for the given LED number (0-3). | ||
78 | + */ | ||
79 | +static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state) | ||
80 | +{ | ||
81 | + return (oldval & (~(0x3 << (led_num << 1)))) | | ||
82 | + ((state & 0x3) << (led_num << 1)); | ||
83 | +} | ||
84 | + | ||
85 | +static void pca9552_set_led(Object *obj, Visitor *v, const char *name, | ||
86 | + void *opaque, Error **errp) | ||
87 | +{ | ||
88 | + PCA9552State *s = PCA9552(obj); | ||
89 | + Error *local_err = NULL; | ||
90 | + int led, rc, reg, val; | ||
91 | + uint8_t state; | ||
92 | + char *state_str; | ||
93 | + | ||
94 | + visit_type_str(v, name, &state_str, &local_err); | ||
95 | + if (local_err) { | ||
96 | + error_propagate(errp, local_err); | ||
97 | + return; | ||
98 | + } | ||
99 | + rc = sscanf(name, "led%2d", &led); | ||
100 | + if (rc != 1) { | ||
101 | + error_setg(errp, "%s: error reading %s", __func__, name); | ||
102 | + return; | ||
103 | + } | ||
104 | + if (led < 0 || led > s->nr_leds) { | ||
105 | + error_setg(errp, "%s invalid led %s", __func__, name); | ||
106 | + return; | ||
107 | + } | ||
108 | + | ||
109 | + for (state = 0; state < ARRAY_SIZE(led_state); state++) { | ||
110 | + if (!strcmp(state_str, led_state[state])) { | ||
111 | + break; | ||
112 | + } | ||
113 | + } | ||
114 | + if (state >= ARRAY_SIZE(led_state)) { | ||
115 | + error_setg(errp, "%s invalid led state %s", __func__, state_str); | ||
116 | + return; | ||
117 | + } | ||
118 | + | ||
119 | + reg = PCA9552_LS0 + led / 4; | ||
120 | + val = pca9552_read(s, reg); | ||
121 | + val = pca955x_ledsel(val, led % 4, state); | ||
122 | + pca9552_write(s, reg, val); | ||
123 | +} | ||
124 | + | ||
125 | static const VMStateDescription pca9552_vmstate = { | ||
126 | .name = "PCA9552", | ||
127 | .version_id = 0, | ||
128 | @@ -XXX,XX +XXX,XX @@ static void pca9552_reset(DeviceState *dev) | ||
129 | static void pca9552_initfn(Object *obj) | ||
130 | { | ||
131 | PCA9552State *s = PCA9552(obj); | ||
132 | + int led; | ||
133 | |||
134 | /* If support for the other PCA955X devices are implemented, these | ||
135 | * constant values might be part of class structure describing the | ||
136 | @@ -XXX,XX +XXX,XX @@ static void pca9552_initfn(Object *obj) | ||
137 | */ | ||
138 | s->max_reg = PCA9552_LS3; | ||
139 | s->nr_leds = 16; | ||
140 | + | ||
141 | + for (led = 0; led < s->nr_leds; led++) { | ||
142 | + char *name; | ||
143 | + | ||
144 | + name = g_strdup_printf("led%d", led); | ||
145 | + object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led, | ||
146 | + NULL, NULL, NULL); | ||
147 | + g_free(name); | ||
148 | + } | ||
149 | } | ||
150 | |||
151 | static void pca9552_class_init(ObjectClass *klass, void *data) | ||
152 | -- | 44 | -- |
153 | 2.20.1 | 45 | 2.25.1 |
154 | 46 | ||
155 | 47 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | 2 | ||
3 | This commit make use of the resettable API to reset the device being | 3 | This is the latest URL for the OpenBMC CI. The old URL still works, but |
4 | hotplugged when it is realized. Also it ensures it is put in a reset | 4 | redirects. |
5 | state coherent with the parent it is plugged into. | ||
6 | 5 | ||
7 | Note that there is a difference in the reset. Instead of resetting | 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
8 | only the hotplugged device, we reset also its subtree (switch to | 7 | Signed-off-by: Joel Stanley <joel@jms.id.au> |
9 | resettable API). This is not expected to be a problem because | 8 | Message-id: 20211117065752.330632-3-joel@jms.id.au |
10 | sub-buses are just realized too. If a hotplugged device has any | ||
11 | sub-buses it is logical to reset them too at this point. | ||
12 | |||
13 | The recently added should_be_hidden and PCI's partially_hotplugged | ||
14 | mechanisms do not interfere with realize operation: | ||
15 | + In the should_be_hidden use case, device creation is | ||
16 | delayed. | ||
17 | + The partially_hotplugged mechanism prevents a device to be | ||
18 | unplugged and unrealized from qdev POV and unrealized. | ||
19 | |||
20 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
22 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
23 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
24 | Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 10 | --- |
27 | include/hw/resettable.h | 11 +++++++++++ | 11 | docs/system/arm/aspeed.rst | 2 +- |
28 | hw/core/qdev.c | 15 ++++++++++++++- | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
29 | 2 files changed, 25 insertions(+), 1 deletion(-) | ||
30 | 13 | ||
31 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
32 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/include/hw/resettable.h | 16 | --- a/docs/system/arm/aspeed.rst |
34 | +++ b/include/hw/resettable.h | 17 | +++ b/docs/system/arm/aspeed.rst |
35 | @@ -XXX,XX +XXX,XX @@ struct ResettableState { | 18 | @@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to |
36 | bool exit_phase_in_progress; | 19 | load a Linux kernel or from a firmware. Images can be downloaded from |
37 | }; | 20 | the OpenBMC jenkins : |
38 | 21 | ||
39 | +/** | 22 | - https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder |
40 | + * resettable_state_clear: | 23 | + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ |
41 | + * Clear the state. It puts the state to the initial (zeroed) state required | 24 | |
42 | + * to reuse an object. Typically used in realize step of base classes | 25 | or directly from the OpenBMC GitHub release repository : |
43 | + * implementing the interface. | ||
44 | + */ | ||
45 | +static inline void resettable_state_clear(ResettableState *state) | ||
46 | +{ | ||
47 | + memset(state, 0, sizeof(ResettableState)); | ||
48 | +} | ||
49 | + | ||
50 | /** | ||
51 | * resettable_reset: | ||
52 | * Trigger a reset on an object @obj of type @type. @obj must implement | ||
53 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/core/qdev.c | ||
56 | +++ b/hw/core/qdev.c | ||
57 | @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) | ||
58 | } | ||
59 | } | ||
60 | |||
61 | + /* | ||
62 | + * Clear the reset state, in case the object was previously unrealized | ||
63 | + * with a dirty state. | ||
64 | + */ | ||
65 | + resettable_state_clear(&dev->reset); | ||
66 | + | ||
67 | QLIST_FOREACH(bus, &dev->child_bus, sibling) { | ||
68 | object_property_set_bool(OBJECT(bus), true, "realized", | ||
69 | &local_err); | ||
70 | @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) | ||
71 | } | ||
72 | } | ||
73 | if (dev->hotplugged) { | ||
74 | - device_legacy_reset(dev); | ||
75 | + /* | ||
76 | + * Reset the device, as well as its subtree which, at this point, | ||
77 | + * should be realized too. | ||
78 | + */ | ||
79 | + resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD); | ||
80 | + resettable_change_parent(OBJECT(dev), OBJECT(dev->parent_bus), | ||
81 | + NULL); | ||
82 | + resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD); | ||
83 | } | ||
84 | dev->pending_deleted_event = false; | ||
85 | 26 | ||
86 | -- | 27 | -- |
87 | 2.20.1 | 28 | 2.25.1 |
88 | 29 | ||
89 | 30 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 3 | A common use case for the ASPEED machine is to boot a Linux kernel. |
4 | Message-id: 20200120101023.16030-2-drjones@redhat.com | 4 | Provide a full example command line. |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | |
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
7 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
8 | Message-id: 20211117065752.330632-4-joel@jms.id.au | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | target/arm/kvm_arm.h | 46 ++++++++++++++++++++++++++------------------ | 11 | docs/system/arm/aspeed.rst | 15 ++++++++++++--- |
9 | 1 file changed, 27 insertions(+), 19 deletions(-) | 12 | 1 file changed, 12 insertions(+), 3 deletions(-) |
10 | 13 | ||
11 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
12 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/kvm_arm.h | 16 | --- a/docs/system/arm/aspeed.rst |
14 | +++ b/target/arm/kvm_arm.h | 17 | +++ b/docs/system/arm/aspeed.rst |
15 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ Missing devices |
16 | int kvm_arm_vcpu_init(CPUState *cs); | 19 | Boot options |
17 | 20 | ------------ | |
18 | /** | 21 | |
19 | - * kvm_arm_vcpu_finalize | 22 | -The Aspeed machines can be started using the ``-kernel`` option to |
20 | + * kvm_arm_vcpu_finalize: | 23 | -load a Linux kernel or from a firmware. Images can be downloaded from |
21 | * @cs: CPUState | 24 | -the OpenBMC jenkins : |
22 | - * @feature: int | 25 | +The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options |
23 | + * @feature: feature to finalize | 26 | +to load a Linux kernel or from a firmware. Images can be downloaded from the |
24 | * | 27 | +OpenBMC jenkins : |
25 | * Finalizes the configuration of the specified VCPU feature by | 28 | |
26 | * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring | 29 | https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ |
27 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, | 30 | |
28 | int kvm_arm_init_cpreg_list(ARMCPU *cpu); | 31 | @@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository : |
29 | 32 | ||
30 | /** | 33 | https://github.com/openbmc/openbmc/releases |
31 | - * kvm_arm_reg_syncs_via_cpreg_list | 34 | |
32 | - * regidx: KVM register index | 35 | +To boot a kernel directly from a Linux build tree: |
33 | + * kvm_arm_reg_syncs_via_cpreg_list: | 36 | + |
34 | + * @regidx: KVM register index | 37 | +.. code-block:: bash |
35 | * | 38 | + |
36 | * Return true if this KVM register should be synchronized via the | 39 | + $ qemu-system-arm -M ast2600-evb -nographic \ |
37 | * cpreg list of arbitrary system registers, false if it is synchronized | 40 | + -kernel arch/arm/boot/zImage \ |
38 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu); | 41 | + -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ |
39 | bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); | 42 | + -initrd rootfs.cpio |
40 | 43 | + | |
41 | /** | 44 | The image should be attached as an MTD drive. Run : |
42 | - * kvm_arm_cpreg_level | 45 | |
43 | - * regidx: KVM register index | 46 | .. code-block:: bash |
44 | + * kvm_arm_cpreg_level: | ||
45 | + * @regidx: KVM register index | ||
46 | * | ||
47 | * Return the level of this coprocessor/system register. Return value is | ||
48 | * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. | ||
49 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_init_serror_injection(CPUState *cs); | ||
50 | * @cpu: ARMCPU | ||
51 | * | ||
52 | * Get VCPU related state from kvm. | ||
53 | + * | ||
54 | + * Returns: 0 if success else < 0 error code | ||
55 | */ | ||
56 | int kvm_get_vcpu_events(ARMCPU *cpu); | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu); | ||
59 | * @cpu: ARMCPU | ||
60 | * | ||
61 | * Put VCPU related state to kvm. | ||
62 | + * | ||
63 | + * Returns: 0 if success else < 0 error code | ||
64 | */ | ||
65 | int kvm_put_vcpu_events(ARMCPU *cpu); | ||
66 | |||
67 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures { | ||
68 | |||
69 | /** | ||
70 | * kvm_arm_get_host_cpu_features: | ||
71 | - * @ahcc: ARMHostCPUClass to fill in | ||
72 | + * @ahcf: ARMHostCPUClass to fill in | ||
73 | * | ||
74 | * Probe the capabilities of the host kernel's preferred CPU and fill | ||
75 | * in the ARMHostCPUClass struct accordingly. | ||
76 | + * | ||
77 | + * Returns true on success and false otherwise. | ||
78 | */ | ||
79 | bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); | ||
80 | |||
81 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); | ||
82 | bool kvm_arm_aarch32_supported(CPUState *cs); | ||
83 | |||
84 | /** | ||
85 | - * bool kvm_arm_pmu_supported: | ||
86 | + * kvm_arm_pmu_supported: | ||
87 | * @cs: CPUState | ||
88 | * | ||
89 | * Returns: true if the KVM VCPU can enable its PMU | ||
90 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs); | ||
91 | bool kvm_arm_pmu_supported(CPUState *cs); | ||
92 | |||
93 | /** | ||
94 | - * bool kvm_arm_sve_supported: | ||
95 | + * kvm_arm_sve_supported: | ||
96 | * @cs: CPUState | ||
97 | * | ||
98 | * Returns true if the KVM VCPU can enable SVE and false otherwise. | ||
99 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_pmu_supported(CPUState *cs); | ||
100 | bool kvm_arm_sve_supported(CPUState *cs); | ||
101 | |||
102 | /** | ||
103 | - * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the | ||
104 | - * IPA address space supported by KVM | ||
105 | - * | ||
106 | + * kvm_arm_get_max_vm_ipa_size: | ||
107 | * @ms: Machine state handle | ||
108 | + * | ||
109 | + * Returns the number of bits in the IPA address space supported by KVM | ||
110 | */ | ||
111 | int kvm_arm_get_max_vm_ipa_size(MachineState *ms); | ||
112 | |||
113 | /** | ||
114 | - * kvm_arm_sync_mpstate_to_kvm | ||
115 | + * kvm_arm_sync_mpstate_to_kvm: | ||
116 | * @cpu: ARMCPU | ||
117 | * | ||
118 | * If supported set the KVM MP_STATE based on QEMU's model. | ||
119 | + * | ||
120 | + * Returns 0 on success and -1 on failure. | ||
121 | */ | ||
122 | int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); | ||
123 | |||
124 | /** | ||
125 | - * kvm_arm_sync_mpstate_to_qemu | ||
126 | + * kvm_arm_sync_mpstate_to_qemu: | ||
127 | * @cpu: ARMCPU | ||
128 | * | ||
129 | * If supported get the MP_STATE from KVM and store in QEMU's model. | ||
130 | + * | ||
131 | + * Returns 0 on success and aborts on failure. | ||
132 | */ | ||
133 | int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); | ||
134 | |||
135 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); | ||
136 | |||
137 | static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
138 | { | ||
139 | - /* This should never actually be called in the "not KVM" case, | ||
140 | + /* | ||
141 | + * This should never actually be called in the "not KVM" case, | ||
142 | * but set up the fields to indicate an error anyway. | ||
143 | */ | ||
144 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; | ||
145 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); | ||
146 | * | ||
147 | * Return: TRUE if any hardware breakpoints in use. | ||
148 | */ | ||
149 | - | ||
150 | bool kvm_arm_hw_debug_active(CPUState *cs); | ||
151 | |||
152 | /** | ||
153 | * kvm_arm_copy_hw_debug_data: | ||
154 | - * | ||
155 | * @ptr: kvm_guest_debug_arch structure | ||
156 | * | ||
157 | * Copy the architecture specific debug registers into the | ||
158 | * kvm_guest_debug ioctl structure. | ||
159 | */ | ||
160 | struct kvm_guest_debug_arch; | ||
161 | - | ||
162 | void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); | ||
163 | |||
164 | /** | ||
165 | - * its_class_name | ||
166 | + * its_class_name: | ||
167 | * | ||
168 | * Return the ITS class name to use depending on whether KVM acceleration | ||
169 | * and KVM CAP_SIGNAL_MSI are supported | ||
170 | -- | 47 | -- |
171 | 2.20.1 | 48 | 2.25.1 |
172 | 49 | ||
173 | 50 | diff view generated by jsdifflib |
1 | The num-lines property of the TYPE_OR_GATE device sets the number | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | of input lines it has. An assert() in or_irq_realize() restricts | ||
3 | this to the maximum supported by the implementation. However we | ||
4 | got the condition in the assert wrong: it should be using <=, | ||
5 | because num-lines == MAX_OR_LINES is permitted, and means that | ||
6 | all entries from 0 to MAX_OR_LINES-1 in the s->levels[] array | ||
7 | are used. | ||
8 | 2 | ||
9 | We didn't notice this previously because no user has so far | 3 | Move it to the supported list. |
10 | needed that many input lines. | ||
11 | 4 | ||
12 | Reported-by: Guenter Roeck <linux@roeck-us.net> | 5 | Signed-off-by: Joel Stanley <joel@jms.id.au> |
6 | Message-id: 20211117065752.330632-5-joel@jms.id.au | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
15 | Reviewed-by: Guenter Roeck <linux@roeck-us.net> | ||
16 | Message-id: 20200120142235.10432-1-peter.maydell@linaro.org | ||
17 | --- | 8 | --- |
18 | hw/core/or-irq.c | 2 +- | 9 | docs/system/arm/aspeed.rst | 2 +- |
19 | 1 file changed, 1 insertion(+), 1 deletion(-) | 10 | 1 file changed, 1 insertion(+), 1 deletion(-) |
20 | 11 | ||
21 | diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c | 12 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
22 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/core/or-irq.c | 14 | --- a/docs/system/arm/aspeed.rst |
24 | +++ b/hw/core/or-irq.c | 15 | +++ b/docs/system/arm/aspeed.rst |
25 | @@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp) | 16 | @@ -XXX,XX +XXX,XX @@ Supported devices |
26 | { | 17 | * Front LEDs (PCA9552 on I2C bus) |
27 | qemu_or_irq *s = OR_IRQ(dev); | 18 | * LPC Peripheral Controller (a subset of subdevices are supported) |
28 | 19 | * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA | |
29 | - assert(s->num_lines < MAX_OR_LINES); | 20 | + * ADC |
30 | + assert(s->num_lines <= MAX_OR_LINES); | 21 | |
31 | 22 | ||
32 | qdev_init_gpio_in(dev, or_irq_handler, s->num_lines); | 23 | Missing devices |
33 | } | 24 | --------------- |
25 | |||
26 | * Coprocessor support | ||
27 | - * ADC (out of tree implementation) | ||
28 | * PWM and Fan Controller | ||
29 | * Slave GPIO Controller | ||
30 | * Super I/O Controller | ||
34 | -- | 31 | -- |
35 | 2.20.1 | 32 | 2.25.1 |
36 | 33 | ||
37 | 34 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Olivier Hériveaux <olivier.heriveaux@ledger.fr> | ||
1 | 2 | ||
3 | Fix issue where the data register may be overwritten by next character | ||
4 | reception before being read and returned. | ||
5 | |||
6 | Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/char/stm32f2xx_usart.c | 3 ++- | ||
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/char/stm32f2xx_usart.c | ||
18 | +++ b/hw/char/stm32f2xx_usart.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, | ||
20 | return retvalue; | ||
21 | case USART_DR: | ||
22 | DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); | ||
23 | + retvalue = s->usart_dr & 0x3FF; | ||
24 | s->usart_sr &= ~USART_SR_RXNE; | ||
25 | qemu_chr_fe_accept_input(&s->chr); | ||
26 | qemu_set_irq(s->irq, 0); | ||
27 | - return s->usart_dr & 0x3FF; | ||
28 | + return retvalue; | ||
29 | case USART_BRR: | ||
30 | return s->usart_brr; | ||
31 | case USART_CR1: | ||
32 | -- | ||
33 | 2.25.1 | ||
34 | |||
35 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | 3 | gicv3_set_gicv3state() is used by arm_gicv3_common.c in |
4 | arm_gicv3_common_realize(). Since we want to restrict | ||
5 | arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state() | ||
6 | to a new file. Add this file to the meson 'specific' | ||
7 | source set, since it needs access to "cpu.h". | ||
8 | |||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20211115223619.2599282-2-philmd@redhat.com |
6 | Message-id: 20200123132823.1117486-10-damien.hedde@greensocs.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 13 | --- |
9 | docs/devel/index.rst | 1 + | 14 | hw/intc/arm_gicv3_cpuif.c | 10 +--------- |
10 | docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++++++ | 15 | hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++ |
11 | 2 files changed, 290 insertions(+) | 16 | hw/intc/meson.build | 1 + |
12 | create mode 100644 docs/devel/reset.rst | 17 | 3 files changed, 24 insertions(+), 9 deletions(-) |
18 | create mode 100644 hw/intc/arm_gicv3_cpuif_common.c | ||
13 | 19 | ||
14 | diff --git a/docs/devel/index.rst b/docs/devel/index.rst | 20 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/devel/index.rst | 22 | --- a/hw/intc/arm_gicv3_cpuif.c |
17 | +++ b/docs/devel/index.rst | 23 | +++ b/hw/intc/arm_gicv3_cpuif.c |
18 | @@ -XXX,XX +XXX,XX @@ Contents: | 24 | @@ -XXX,XX +XXX,XX @@ |
19 | tcg | 25 | /* |
20 | tcg-plugins | 26 | - * ARM Generic Interrupt Controller v3 |
21 | bitops | 27 | + * ARM Generic Interrupt Controller v3 (emulation) |
22 | + reset | 28 | * |
23 | diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst | 29 | * Copyright (c) 2016 Linaro Limited |
30 | * Written by Peter Maydell | ||
31 | @@ -XXX,XX +XXX,XX @@ | ||
32 | #include "hw/irq.h" | ||
33 | #include "cpu.h" | ||
34 | |||
35 | -void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) | ||
36 | -{ | ||
37 | - ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
38 | - CPUARMState *env = &arm_cpu->env; | ||
39 | - | ||
40 | - env->gicv3state = (void *)s; | ||
41 | -}; | ||
42 | - | ||
43 | static GICv3CPUState *icc_cs_from_env(CPUARMState *env) | ||
44 | { | ||
45 | return env->gicv3state; | ||
46 | diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c | ||
24 | new file mode 100644 | 47 | new file mode 100644 |
25 | index XXXXXXX..XXXXXXX | 48 | index XXXXXXX..XXXXXXX |
26 | --- /dev/null | 49 | --- /dev/null |
27 | +++ b/docs/devel/reset.rst | 50 | +++ b/hw/intc/arm_gicv3_cpuif_common.c |
28 | @@ -XXX,XX +XXX,XX @@ | 51 | @@ -XXX,XX +XXX,XX @@ |
52 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
53 | +/* | ||
54 | + * ARM Generic Interrupt Controller v3 | ||
55 | + * | ||
56 | + * Copyright (c) 2016 Linaro Limited | ||
57 | + * Written by Peter Maydell | ||
58 | + * | ||
59 | + * This code is licensed under the GPL, version 2 or (at your option) | ||
60 | + * any later version. | ||
61 | + */ | ||
29 | + | 62 | + |
30 | +======================================= | 63 | +#include "qemu/osdep.h" |
31 | +Reset in QEMU: the Resettable interface | 64 | +#include "gicv3_internal.h" |
32 | +======================================= | 65 | +#include "cpu.h" |
33 | + | 66 | + |
34 | +The reset of qemu objects is handled using the resettable interface declared | 67 | +void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) |
35 | +in ``include/hw/resettable.h``. | 68 | +{ |
69 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
70 | + CPUARMState *env = &arm_cpu->env; | ||
36 | + | 71 | + |
37 | +This interface allows objects to be grouped (on a tree basis); so that the | 72 | + env->gicv3state = (void *)s; |
38 | +whole group can be reset consistently. Each individual member object does not | 73 | +}; |
39 | +have to care about others; in particular, problems of order (which object is | 74 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build |
40 | +reset first) are addressed. | 75 | index XXXXXXX..XXXXXXX 100644 |
41 | + | 76 | --- a/hw/intc/meson.build |
42 | +As of now DeviceClass and BusClass implement this interface. | 77 | +++ b/hw/intc/meson.build |
43 | + | 78 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in |
44 | + | 79 | |
45 | +Triggering reset | 80 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) |
46 | +---------------- | 81 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) |
47 | + | 82 | +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) |
48 | +This section documents the APIs which "users" of a resettable object should use | 83 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) |
49 | +to control it. All resettable control functions must be called while holding | 84 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) |
50 | +the iothread lock. | 85 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) |
51 | + | ||
52 | +You can apply a reset to an object using ``resettable_assert_reset()``. You need | ||
53 | +to call ``resettable_release_reset()`` to release the object from reset. To | ||
54 | +instantly reset an object, without keeping it in reset state, just call | ||
55 | +``resettable_reset()``. These functions take two parameters: a pointer to the | ||
56 | +object to reset and a reset type. | ||
57 | + | ||
58 | +Several types of reset will be supported. For now only cold reset is defined; | ||
59 | +others may be added later. The Resettable interface handles reset types with an | ||
60 | +enum: | ||
61 | + | ||
62 | +``RESET_TYPE_COLD`` | ||
63 | + Cold reset is supported by every resettable object. In QEMU, it means we reset | ||
64 | + to the initial state corresponding to the start of QEMU; this might differ | ||
65 | + from what is a real hardware cold reset. It differs from other resets (like | ||
66 | + warm or bus resets) which may keep certain parts untouched. | ||
67 | + | ||
68 | +Calling ``resettable_reset()`` is equivalent to calling | ||
69 | +``resettable_assert_reset()`` then ``resettable_release_reset()``. It is | ||
70 | +possible to interleave multiple calls to these three functions. There may | ||
71 | +be several reset sources/controllers of a given object. The interface handles | ||
72 | +everything and the different reset controllers do not need to know anything | ||
73 | +about each others. The object will leave reset state only when each other | ||
74 | +controllers end their reset operation. This point is handled internally by | ||
75 | +maintaining a count of in-progress resets; it is crucial to call | ||
76 | +``resettable_release_reset()`` one time and only one time per | ||
77 | +``resettable_assert_reset()`` call. | ||
78 | + | ||
79 | +For now migration of a device or bus in reset is not supported. Care must be | ||
80 | +taken not to delay ``resettable_release_reset()`` after its | ||
81 | +``resettable_assert_reset()`` counterpart. | ||
82 | + | ||
83 | +Note that, since resettable is an interface, the API takes a simple Object as | ||
84 | +parameter. Still, it is a programming error to call a resettable function on a | ||
85 | +non-resettable object and it will trigger a run time assert error. Since most | ||
86 | +calls to resettable interface are done through base class functions, such an | ||
87 | +error is not likely to happen. | ||
88 | + | ||
89 | +For Devices and Buses, the following helper functions exist: | ||
90 | + | ||
91 | +- ``device_cold_reset()`` | ||
92 | +- ``bus_cold_reset()`` | ||
93 | + | ||
94 | +These are simple wrappers around resettable_reset() function; they only cast the | ||
95 | +Device or Bus into an Object and pass the cold reset type. When possible | ||
96 | +prefer to use these functions instead of ``resettable_reset()``. | ||
97 | + | ||
98 | +Device and bus functions co-exist because there can be semantic differences | ||
99 | +between resetting a bus and resetting the controller bridge which owns it. | ||
100 | +For example, consider a SCSI controller. Resetting the controller puts all | ||
101 | +its registers back to what reset state was as well as reset everything on the | ||
102 | +SCSI bus, whereas resetting just the SCSI bus only resets everything that's on | ||
103 | +it but not the controller. | ||
104 | + | ||
105 | + | ||
106 | +Multi-phase mechanism | ||
107 | +--------------------- | ||
108 | + | ||
109 | +This section documents the internals of the resettable interface. | ||
110 | + | ||
111 | +The resettable interface uses a multi-phase system to relieve objects and | ||
112 | +machines from reset ordering problems. To address this, the reset operation | ||
113 | +of an object is split into three well defined phases. | ||
114 | + | ||
115 | +When resetting several objects (for example the whole machine at simulation | ||
116 | +startup), all first phases of all objects are executed, then all second phases | ||
117 | +and then all third phases. | ||
118 | + | ||
119 | +The three phases are: | ||
120 | + | ||
121 | +1. The **enter** phase is executed when the object enters reset. It resets only | ||
122 | + local state of the object; it must not do anything that has a side-effect | ||
123 | + on other objects, such as raising or lowering a qemu_irq line or reading or | ||
124 | + writing guest memory. | ||
125 | + | ||
126 | +2. The **hold** phase is executed for entry into reset, once every object in the | ||
127 | + group which is being reset has had its *enter* phase executed. At this point | ||
128 | + devices can do actions that affect other objects. | ||
129 | + | ||
130 | +3. The **exit** phase is executed when the object leaves the reset state. | ||
131 | + Actions affecting other objects are permitted. | ||
132 | + | ||
133 | +As said in previous section, the interface maintains a count of reset. This | ||
134 | +count is used to ensure phases are executed only when required. *enter* and | ||
135 | +*hold* phases are executed only when asserting reset for the first time | ||
136 | +(if an object is already in reset state when calling | ||
137 | +``resettable_assert_reset()`` or ``resettable_reset()``, they are not | ||
138 | +executed). | ||
139 | +The *exit* phase is executed only when the last reset operation ends. Therefore | ||
140 | +the object does not need to care how many of reset controllers it has and how | ||
141 | +many of them have started a reset. | ||
142 | + | ||
143 | + | ||
144 | +Handling reset in a resettable object | ||
145 | +------------------------------------- | ||
146 | + | ||
147 | +This section documents the APIs that an implementation of a resettable object | ||
148 | +must provide and what functions it has access to. It is intended for people | ||
149 | +who want to implement or convert a class which has the resettable interface; | ||
150 | +for example when specializing an existing device or bus. | ||
151 | + | ||
152 | +Methods to implement | ||
153 | +.................... | ||
154 | + | ||
155 | +Three methods should be defined or left empty. Each method corresponds to a | ||
156 | +phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and | ||
157 | +``phases.exit()``. They all take the object as parameter. The *enter* method | ||
158 | +also take the reset type as second parameter. | ||
159 | + | ||
160 | +When extending an existing class, these methods may need to be extended too. | ||
161 | +The ``resettable_class_set_parent_phases()`` class function may be used to | ||
162 | +backup parent class methods. | ||
163 | + | ||
164 | +Here follows an example to implement reset for a Device which sets an IO while | ||
165 | +in reset. | ||
166 | + | ||
167 | +:: | ||
168 | + | ||
169 | + static void mydev_reset_enter(Object *obj, ResetType type) | ||
170 | + { | ||
171 | + MyDevClass *myclass = MYDEV_GET_CLASS(obj); | ||
172 | + MyDevState *mydev = MYDEV(obj); | ||
173 | + /* call parent class enter phase */ | ||
174 | + if (myclass->parent_phases.enter) { | ||
175 | + myclass->parent_phases.enter(obj, type); | ||
176 | + } | ||
177 | + /* initialize local state only */ | ||
178 | + mydev->var = 0; | ||
179 | + } | ||
180 | + | ||
181 | + static void mydev_reset_hold(Object *obj) | ||
182 | + { | ||
183 | + MyDevClass *myclass = MYDEV_GET_CLASS(obj); | ||
184 | + MyDevState *mydev = MYDEV(obj); | ||
185 | + /* call parent class hold phase */ | ||
186 | + if (myclass->parent_phases.hold) { | ||
187 | + myclass->parent_phases.hold(obj); | ||
188 | + } | ||
189 | + /* set an IO */ | ||
190 | + qemu_set_irq(mydev->irq, 1); | ||
191 | + } | ||
192 | + | ||
193 | + static void mydev_reset_exit(Object *obj) | ||
194 | + { | ||
195 | + MyDevClass *myclass = MYDEV_GET_CLASS(obj); | ||
196 | + MyDevState *mydev = MYDEV(obj); | ||
197 | + /* call parent class exit phase */ | ||
198 | + if (myclass->parent_phases.exit) { | ||
199 | + myclass->parent_phases.exit(obj); | ||
200 | + } | ||
201 | + /* clear an IO */ | ||
202 | + qemu_set_irq(mydev->irq, 0); | ||
203 | + } | ||
204 | + | ||
205 | + typedef struct MyDevClass { | ||
206 | + MyParentClass parent_class; | ||
207 | + /* to store eventual parent reset methods */ | ||
208 | + ResettablePhases parent_phases; | ||
209 | + } MyDevClass; | ||
210 | + | ||
211 | + static void mydev_class_init(ObjectClass *class, void *data) | ||
212 | + { | ||
213 | + MyDevClass *myclass = MYDEV_CLASS(class); | ||
214 | + ResettableClass *rc = RESETTABLE_CLASS(class); | ||
215 | + resettable_class_set_parent_reset_phases(rc, | ||
216 | + mydev_reset_enter, | ||
217 | + mydev_reset_hold, | ||
218 | + mydev_reset_exit, | ||
219 | + &myclass->parent_phases); | ||
220 | + } | ||
221 | + | ||
222 | +In the above example, we override all three phases. It is possible to override | ||
223 | +only some of them by passing NULL instead of a function pointer to | ||
224 | +``resettable_class_set_parent_reset_phases()``. For example, the following will | ||
225 | +only override the *enter* phase and leave *hold* and *exit* untouched:: | ||
226 | + | ||
227 | + resettable_class_set_parent_reset_phases(rc, mydev_reset_enter, | ||
228 | + NULL, NULL, | ||
229 | + &myclass->parent_phases); | ||
230 | + | ||
231 | +This is equivalent to providing a trivial implementation of the hold and exit | ||
232 | +phases which does nothing but call the parent class's implementation of the | ||
233 | +phase. | ||
234 | + | ||
235 | +Polling the reset state | ||
236 | +....................... | ||
237 | + | ||
238 | +Resettable interface provides the ``resettable_is_in_reset()`` function. | ||
239 | +This function returns true if the object parameter is currently under reset. | ||
240 | + | ||
241 | +An object is under reset from the beginning of the *init* phase to the end of | ||
242 | +the *exit* phase. During all three phases, the function will return that the | ||
243 | +object is in reset. | ||
244 | + | ||
245 | +This function may be used if the object behavior has to be adapted | ||
246 | +while in reset state. For example if a device has an irq input, | ||
247 | +it will probably need to ignore it while in reset; then it can for | ||
248 | +example check the reset state at the beginning of the irq callback. | ||
249 | + | ||
250 | +Note that until migration of the reset state is supported, an object | ||
251 | +should not be left in reset. So apart from being currently executing | ||
252 | +one of the reset phases, the only cases when this function will return | ||
253 | +true is if an external interaction (like changing an io) is made during | ||
254 | +*hold* or *exit* phase of another object in the same reset group. | ||
255 | + | ||
256 | +Helpers ``device_is_in_reset()`` and ``bus_is_in_reset()`` are also provided | ||
257 | +for devices and buses and should be preferred. | ||
258 | + | ||
259 | + | ||
260 | +Base class handling of reset | ||
261 | +---------------------------- | ||
262 | + | ||
263 | +This section documents parts of the reset mechanism that you only need to know | ||
264 | +about if you are extending it to work with a new base class other than | ||
265 | +DeviceClass or BusClass, or maintaining the existing code in those classes. Most | ||
266 | +people can ignore it. | ||
267 | + | ||
268 | +Methods to implement | ||
269 | +.................... | ||
270 | + | ||
271 | +There are two other methods that need to exist in a class implementing the | ||
272 | +interface: ``get_state()`` and ``child_foreach()``. | ||
273 | + | ||
274 | +``get_state()`` is simple. *resettable* is an interface and, as a consequence, | ||
275 | +does not have any class state structure. But in order to factorize the code, we | ||
276 | +need one. This method must return a pointer to ``ResettableState`` structure. | ||
277 | +The structure must be allocated by the base class; preferably it should be | ||
278 | +located inside the object instance structure. | ||
279 | + | ||
280 | +``child_foreach()`` is more complex. It should execute the given callback on | ||
281 | +every reset child of the given resettable object. All children must be | ||
282 | +resettable too. Additional parameters (a reset type and an opaque pointer) must | ||
283 | +be passed to the callback too. | ||
284 | + | ||
285 | +In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located | ||
286 | +``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented | ||
287 | +to follow the bus hierarchy; for a bus, it calls the function on every child | ||
288 | +device; for a device, it calls the function on every bus child. When we reset | ||
289 | +the main system bus, we reset the whole machine bus tree. | ||
290 | + | ||
291 | +Changing a resettable parent | ||
292 | +............................ | ||
293 | + | ||
294 | +One thing which should be taken care of by the base class is handling reset | ||
295 | +hierarchy changes. | ||
296 | + | ||
297 | +The reset hierarchy is supposed to be static and built during machine creation. | ||
298 | +But there are actually some exceptions. To cope with this, the resettable API | ||
299 | +provides ``resettable_change_parent()``. This function allows to set, update or | ||
300 | +remove the parent of a resettable object after machine creation is done. As | ||
301 | +parameters, it takes the object being moved, the old parent if any and the new | ||
302 | +parent if any. | ||
303 | + | ||
304 | +This function can be used at any time when not in a reset operation. During | ||
305 | +a reset operation it must be used only in *hold* phase. Using it in *enter* or | ||
306 | +*exit* phase is an error. | ||
307 | +Also it should not be used during machine creation, although it is harmless to | ||
308 | +do so: the function is a no-op as long as old and new parent are NULL or not | ||
309 | +in reset. | ||
310 | + | ||
311 | +There is currently 2 cases where this function is used: | ||
312 | + | ||
313 | +1. *device hotplug*; it means a new device is introduced on a live bus. | ||
314 | + | ||
315 | +2. *hot bus change*; it means an existing live device is added, moved or | ||
316 | + removed in the bus hierarchy. At the moment, it occurs only in the raspi | ||
317 | + machines for changing the sdbus used by sd card. | ||
318 | -- | 86 | -- |
319 | 2.20.1 | 87 | 2.25.1 |
320 | 88 | ||
321 | 89 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | If we know what the default value should be then we can test for | 3 | The TYPE_ARM_GICV3 device is an emulated one. When using |
4 | that as well as the feature existence. | 4 | KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device |
5 | (which uses in-kernel support). | ||
5 | 6 | ||
6 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 7 | When using --with-devices-FOO, it is possible to build a |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | binary with a specific set of devices. When this binary is |
8 | Message-id: 20200120101023.16030-5-drjones@redhat.com | 9 | restricted to KVM accelerator, the TYPE_ARM_GICV3 device is |
10 | irrelevant, and it is desirable to remove it from the binary. | ||
11 | |||
12 | Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector | ||
13 | which select the files required to have the TYPE_ARM_GICV3 | ||
14 | device, but also allowing to de-select this device. | ||
15 | |||
16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Message-id: 20211115223619.2599282-3-philmd@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 20 | --- |
11 | tests/qtest/arm-cpu-features.c | 37 +++++++++++++++++++++++++--------- | 21 | hw/intc/arm_gicv3.c | 2 +- |
12 | 1 file changed, 28 insertions(+), 9 deletions(-) | 22 | hw/intc/Kconfig | 5 +++++ |
23 | hw/intc/meson.build | 10 ++++++---- | ||
24 | 3 files changed, 12 insertions(+), 5 deletions(-) | ||
13 | 25 | ||
14 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | 26 | diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c |
15 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/tests/qtest/arm-cpu-features.c | 28 | --- a/hw/intc/arm_gicv3.c |
17 | +++ b/tests/qtest/arm-cpu-features.c | 29 | +++ b/hw/intc/arm_gicv3.c |
18 | @@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature) | 30 | @@ -XXX,XX +XXX,XX @@ |
19 | qobject_unref(_resp); \ | 31 | /* |
20 | }) | 32 | - * ARM Generic Interrupt Controller v3 |
21 | 33 | + * ARM Generic Interrupt Controller v3 (emulation) | |
22 | +#define assert_feature(qts, cpu_type, feature, expected_value) \ | 34 | * |
23 | +({ \ | 35 | * Copyright (c) 2015 Huawei. |
24 | + QDict *_resp, *_props; \ | 36 | * Copyright (c) 2016 Linaro Limited |
25 | + \ | 37 | diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig |
26 | + _resp = do_query_no_props(qts, cpu_type); \ | 38 | index XXXXXXX..XXXXXXX 100644 |
27 | + g_assert(_resp); \ | 39 | --- a/hw/intc/Kconfig |
28 | + g_assert(resp_has_props(_resp)); \ | 40 | +++ b/hw/intc/Kconfig |
29 | + _props = resp_get_props(_resp); \ | 41 | @@ -XXX,XX +XXX,XX @@ config APIC |
30 | + g_assert(qdict_get(_props, feature)); \ | 42 | select MSI_NONBROKEN |
31 | + g_assert(qdict_get_bool(_props, feature) == (expected_value)); \ | 43 | select I8259 |
32 | + qobject_unref(_resp); \ | 44 | |
33 | +}) | 45 | +config ARM_GIC_TCG |
46 | + bool | ||
47 | + default y | ||
48 | + depends on ARM_GIC && TCG | ||
34 | + | 49 | + |
35 | +#define assert_has_feature_enabled(qts, cpu_type, feature) \ | 50 | config ARM_GIC_KVM |
36 | + assert_feature(qts, cpu_type, feature, true) | 51 | bool |
37 | + | 52 | default y |
38 | +#define assert_has_feature_disabled(qts, cpu_type, feature) \ | 53 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build |
39 | + assert_feature(qts, cpu_type, feature, false) | 54 | index XXXXXXX..XXXXXXX 100644 |
40 | + | 55 | --- a/hw/intc/meson.build |
41 | static void assert_type_full(QTestState *qts) | 56 | +++ b/hw/intc/meson.build |
42 | { | 57 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( |
43 | const char *error; | 58 | 'arm_gic.c', |
44 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data) | 59 | 'arm_gic_common.c', |
45 | assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL); | 60 | 'arm_gicv2m.c', |
46 | 61 | - 'arm_gicv3.c', | |
47 | /* Test expected feature presence/absence for some cpu types */ | 62 | 'arm_gicv3_common.c', |
48 | - assert_has_feature(qts, "max", "pmu"); | 63 | - 'arm_gicv3_dist.c', |
49 | - assert_has_feature(qts, "cortex-a15", "pmu"); | 64 | 'arm_gicv3_its_common.c', |
50 | + assert_has_feature_enabled(qts, "max", "pmu"); | 65 | - 'arm_gicv3_redist.c', |
51 | + assert_has_feature_enabled(qts, "cortex-a15", "pmu"); | 66 | +)) |
52 | assert_has_not_feature(qts, "cortex-a15", "aarch64"); | 67 | +softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( |
53 | 68 | + 'arm_gicv3.c', | |
54 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | 69 | + 'arm_gicv3_dist.c', |
55 | - assert_has_feature(qts, "max", "aarch64"); | 70 | 'arm_gicv3_its.c', |
56 | - assert_has_feature(qts, "max", "sve"); | 71 | + 'arm_gicv3_redist.c', |
57 | - assert_has_feature(qts, "max", "sve128"); | 72 | )) |
58 | - assert_has_feature(qts, "cortex-a57", "pmu"); | 73 | softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) |
59 | - assert_has_feature(qts, "cortex-a57", "aarch64"); | 74 | softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) |
60 | + assert_has_feature_enabled(qts, "max", "aarch64"); | 75 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in |
61 | + assert_has_feature_enabled(qts, "max", "sve"); | 76 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) |
62 | + assert_has_feature_enabled(qts, "max", "sve128"); | 77 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) |
63 | + assert_has_feature_enabled(qts, "cortex-a57", "pmu"); | 78 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) |
64 | + assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); | 79 | -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) |
65 | 80 | +specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) | |
66 | sve_tests_default(qts, "max"); | 81 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) |
67 | 82 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) | |
68 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | 83 | specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) |
69 | QDict *resp; | ||
70 | char *error; | ||
71 | |||
72 | - assert_has_feature(qts, "host", "aarch64"); | ||
73 | - assert_has_feature(qts, "host", "pmu"); | ||
74 | + assert_has_feature_enabled(qts, "host", "aarch64"); | ||
75 | + assert_has_feature_enabled(qts, "host", "pmu"); | ||
76 | |||
77 | assert_error(qts, "cortex-a15", | ||
78 | "We cannot guarantee the CPU type 'cortex-a15' works " | ||
79 | -- | 84 | -- |
80 | 2.20.1 | 85 | 2.25.1 |
81 | 86 | ||
82 | 87 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | kvm-no-adjvtime is a KVM specific CPU property and a first of its | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | kind. To accommodate it we also add kvm_arm_add_vcpu_properties() | ||
5 | and a KVM specific CPU properties description to the CPU features | ||
6 | document. | ||
7 | |||
8 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
9 | Message-id: 20200120101023.16030-7-drjones@redhat.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 6 | --- |
13 | include/hw/arm/virt.h | 1 + | 7 | target/arm/translate-a64.c | 7 ++++--- |
14 | target/arm/kvm_arm.h | 11 ++++++++++ | 8 | 1 file changed, 4 insertions(+), 3 deletions(-) |
15 | hw/arm/virt.c | 8 ++++++++ | ||
16 | target/arm/cpu.c | 2 ++ | ||
17 | target/arm/cpu64.c | 1 + | ||
18 | target/arm/kvm.c | 28 +++++++++++++++++++++++++ | ||
19 | target/arm/monitor.c | 1 + | ||
20 | tests/qtest/arm-cpu-features.c | 4 ++++ | ||
21 | docs/arm-cpu-features.rst | 37 +++++++++++++++++++++++++++++++++- | ||
22 | 9 files changed, 92 insertions(+), 1 deletion(-) | ||
23 | 9 | ||
24 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | 10 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
25 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/hw/arm/virt.h | 12 | --- a/target/arm/translate-a64.c |
27 | +++ b/include/hw/arm/virt.h | 13 | +++ b/target/arm/translate-a64.c |
28 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 14 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
29 | bool smbios_old_sys_ver; | ||
30 | bool no_highmem_ecam; | ||
31 | bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ | ||
32 | + bool kvm_no_adjvtime; | ||
33 | } VirtMachineClass; | ||
34 | |||
35 | typedef struct { | ||
36 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/kvm_arm.h | ||
39 | +++ b/target/arm/kvm_arm.h | ||
40 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); | ||
41 | */ | ||
42 | void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); | ||
43 | |||
44 | +/** | ||
45 | + * kvm_arm_add_vcpu_properties: | ||
46 | + * @obj: The CPU object to add the properties to | ||
47 | + * | ||
48 | + * Add all KVM specific CPU properties to the CPU object. These | ||
49 | + * are the CPU properties with "kvm-" prefixed names. | ||
50 | + */ | ||
51 | +void kvm_arm_add_vcpu_properties(Object *obj); | ||
52 | + | ||
53 | /** | ||
54 | * kvm_arm_aarch32_supported: | ||
55 | * @cs: CPUState | ||
56 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
57 | cpu->host_cpu_probe_failed = true; | ||
58 | } | ||
59 | |||
60 | +static inline void kvm_arm_add_vcpu_properties(Object *obj) {} | ||
61 | + | ||
62 | static inline bool kvm_arm_aarch32_supported(CPUState *cs) | ||
63 | { | 15 | { |
64 | return false; | 16 | DisasContext *s = container_of(dcbase, DisasContext, base); |
65 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 17 | CPUARMState *env = cpu->env_ptr; |
66 | index XXXXXXX..XXXXXXX 100644 | 18 | + uint64_t pc = s->base.pc_next; |
67 | --- a/hw/arm/virt.c | 19 | uint32_t insn; |
68 | +++ b/hw/arm/virt.c | 20 | |
69 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 21 | if (s->ss_active && !s->pstate_ss) { |
70 | } | 22 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
71 | } | ||
72 | |||
73 | + if (vmc->kvm_no_adjvtime && | ||
74 | + object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { | ||
75 | + object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); | ||
76 | + } | ||
77 | + | ||
78 | if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { | ||
79 | object_property_set_bool(cpuobj, false, "pmu", NULL); | ||
80 | } | ||
81 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) | ||
82 | |||
83 | static void virt_machine_4_2_options(MachineClass *mc) | ||
84 | { | ||
85 | + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); | ||
86 | + | ||
87 | virt_machine_5_0_options(mc); | ||
88 | compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); | ||
89 | + vmc->kvm_no_adjvtime = true; | ||
90 | } | ||
91 | DEFINE_VIRT_MACHINE(4, 2) | ||
92 | |||
93 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/cpu.c | ||
96 | +++ b/target/arm/cpu.c | ||
97 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
98 | |||
99 | if (kvm_enabled()) { | ||
100 | kvm_arm_set_cpu_features_from_host(cpu); | ||
101 | + kvm_arm_add_vcpu_properties(obj); | ||
102 | } else { | ||
103 | cortex_a15_initfn(obj); | ||
104 | |||
105 | @@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj) | ||
106 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
107 | aarch64_add_sve_properties(obj); | ||
108 | } | ||
109 | + kvm_arm_add_vcpu_properties(obj); | ||
110 | arm_cpu_post_init(obj); | ||
111 | } | ||
112 | |||
113 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
114 | index XXXXXXX..XXXXXXX 100644 | ||
115 | --- a/target/arm/cpu64.c | ||
116 | +++ b/target/arm/cpu64.c | ||
117 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
118 | |||
119 | if (kvm_enabled()) { | ||
120 | kvm_arm_set_cpu_features_from_host(cpu); | ||
121 | + kvm_arm_add_vcpu_properties(obj); | ||
122 | } else { | ||
123 | uint64_t t; | ||
124 | uint32_t u; | ||
125 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/target/arm/kvm.c | ||
128 | +++ b/target/arm/kvm.c | ||
129 | @@ -XXX,XX +XXX,XX @@ | ||
130 | #include "qemu/timer.h" | ||
131 | #include "qemu/error-report.h" | ||
132 | #include "qemu/main-loop.h" | ||
133 | +#include "qom/object.h" | ||
134 | +#include "qapi/error.h" | ||
135 | #include "sysemu/sysemu.h" | ||
136 | #include "sysemu/kvm.h" | ||
137 | #include "sysemu/kvm_int.h" | ||
138 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
139 | env->features = arm_host_cpu_features.features; | ||
140 | } | ||
141 | |||
142 | +static bool kvm_no_adjvtime_get(Object *obj, Error **errp) | ||
143 | +{ | ||
144 | + return !ARM_CPU(obj)->kvm_adjvtime; | ||
145 | +} | ||
146 | + | ||
147 | +static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) | ||
148 | +{ | ||
149 | + ARM_CPU(obj)->kvm_adjvtime = !value; | ||
150 | +} | ||
151 | + | ||
152 | +/* KVM VCPU properties should be prefixed with "kvm-". */ | ||
153 | +void kvm_arm_add_vcpu_properties(Object *obj) | ||
154 | +{ | ||
155 | + if (!kvm_enabled()) { | ||
156 | + return; | ||
157 | + } | ||
158 | + | ||
159 | + ARM_CPU(obj)->kvm_adjvtime = true; | ||
160 | + object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, | ||
161 | + kvm_no_adjvtime_set, &error_abort); | ||
162 | + object_property_set_description(obj, "kvm-no-adjvtime", | ||
163 | + "Set on to disable the adjustment of " | ||
164 | + "the virtual counter. VM stopped time " | ||
165 | + "will be counted.", &error_abort); | ||
166 | +} | ||
167 | + | ||
168 | bool kvm_arm_pmu_supported(CPUState *cpu) | ||
169 | { | ||
170 | return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3); | ||
171 | diff --git a/target/arm/monitor.c b/target/arm/monitor.c | ||
172 | index XXXXXXX..XXXXXXX 100644 | ||
173 | --- a/target/arm/monitor.c | ||
174 | +++ b/target/arm/monitor.c | ||
175 | @@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = { | ||
176 | "sve128", "sve256", "sve384", "sve512", | ||
177 | "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", | ||
178 | "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", | ||
179 | + "kvm-no-adjvtime", | ||
180 | NULL | ||
181 | }; | ||
182 | |||
183 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | ||
184 | index XXXXXXX..XXXXXXX 100644 | ||
185 | --- a/tests/qtest/arm-cpu-features.c | ||
186 | +++ b/tests/qtest/arm-cpu-features.c | ||
187 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data) | ||
188 | assert_has_feature_enabled(qts, "cortex-a15", "pmu"); | ||
189 | assert_has_not_feature(qts, "cortex-a15", "aarch64"); | ||
190 | |||
191 | + assert_has_not_feature(qts, "max", "kvm-no-adjvtime"); | ||
192 | + | ||
193 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
194 | assert_has_feature_enabled(qts, "max", "aarch64"); | ||
195 | assert_has_feature_enabled(qts, "max", "sve"); | ||
196 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | ||
197 | return; | 23 | return; |
198 | } | 24 | } |
199 | 25 | ||
200 | + assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime"); | 26 | - s->pc_curr = s->base.pc_next; |
201 | + | 27 | - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); |
202 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | 28 | + s->pc_curr = pc; |
203 | bool kvm_supports_sve; | 29 | + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); |
204 | char max_name[8], name[8]; | 30 | s->insn = insn; |
205 | diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst | 31 | - s->base.pc_next += 4; |
206 | index XXXXXXX..XXXXXXX 100644 | 32 | + s->base.pc_next = pc + 4; |
207 | --- a/docs/arm-cpu-features.rst | 33 | |
208 | +++ b/docs/arm-cpu-features.rst | 34 | s->fp_access_checked = false; |
209 | @@ -XXX,XX +XXX,XX @@ supporting the feature or only supporting the feature under certain | 35 | s->sve_access_checked = false; |
210 | configurations. For example, the `aarch64` CPU feature, which, when | ||
211 | disabled, enables the optional AArch32 CPU feature, is only supported | ||
212 | when using the KVM accelerator and when running on a host CPU type that | ||
213 | -supports the feature. | ||
214 | +supports the feature. While `aarch64` currently only works with KVM, | ||
215 | +it could work with TCG. CPU features that are specific to KVM are | ||
216 | +prefixed with "kvm-" and are described in "KVM VCPU Features". | ||
217 | |||
218 | CPU Feature Probing | ||
219 | =================== | ||
220 | @@ -XXX,XX +XXX,XX @@ disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU | ||
221 | properties have special semantics (see "SVE CPU Property Parsing | ||
222 | Semantics"). | ||
223 | |||
224 | +KVM VCPU Features | ||
225 | +================= | ||
226 | + | ||
227 | +KVM VCPU features are CPU features that are specific to KVM, such as | ||
228 | +paravirt features or features that enable CPU virtualization extensions. | ||
229 | +The features' CPU properties are only available when KVM is enabled and | ||
230 | +are named with the prefix "kvm-". KVM VCPU features may be probed, | ||
231 | +enabled, and disabled in the same way as other CPU features. Below is | ||
232 | +the list of KVM VCPU features and their descriptions. | ||
233 | + | ||
234 | + kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This | ||
235 | + means that by default the virtual time | ||
236 | + adjustment is enabled (vtime is *not not* | ||
237 | + adjusted). | ||
238 | + | ||
239 | + When virtual time adjustment is enabled each | ||
240 | + time the VM transitions back to running state | ||
241 | + the VCPU's virtual counter is updated to ensure | ||
242 | + stopped time is not counted. This avoids time | ||
243 | + jumps surprising guest OSes and applications, | ||
244 | + as long as they use the virtual counter for | ||
245 | + timekeeping. However it has the side effect of | ||
246 | + the virtual and physical counters diverging. | ||
247 | + All timekeeping based on the virtual counter | ||
248 | + will appear to lag behind any timekeeping that | ||
249 | + does not subtract VM stopped time. The guest | ||
250 | + may resynchronize its virtual counter with | ||
251 | + other time sources as needed. | ||
252 | + | ||
253 | + Enable kvm-no-adjvtime to disable virtual time | ||
254 | + adjustment, also restoring the legacy (pre-5.0) | ||
255 | + behavior. | ||
256 | + | ||
257 | SVE CPU Properties | ||
258 | ================== | ||
259 | |||
260 | -- | 36 | -- |
261 | 2.20.1 | 37 | 2.25.1 |
262 | 38 | ||
263 | 39 | diff view generated by jsdifflib |
1 | From: Zenghui Yu <yuzenghui@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | restoring GICR_CTLR. Setting PTZ here makes littlt sense in "reduce GIC | ||
5 | initialization time". | ||
6 | |||
7 | And what's worse, PTZ is generally programmed by guest to indicate to the | ||
8 | Redistributor whether the LPI Pending table is zero when enabling LPIs. | ||
9 | If migration is triggered when the PTZ has just been cleared by guest (and | ||
10 | before enabling LPIs), we will see PTZ==1 on the destination side, which | ||
11 | is not as expected. Let's just drop this hackish userspace behavior. | ||
12 | |||
13 | Also take this chance to refine the comment a bit. | ||
14 | |||
15 | Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions") | ||
16 | Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> | ||
17 | Message-id: 20200119133051.642-1-yuzenghui@huawei.com | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 6 | --- |
21 | hw/intc/arm_gicv3_kvm.c | 11 ++++------- | 7 | target/arm/translate.c | 9 +++++---- |
22 | 1 file changed, 4 insertions(+), 7 deletions(-) | 8 | 1 file changed, 5 insertions(+), 4 deletions(-) |
23 | 9 | ||
24 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | 10 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
25 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/intc/arm_gicv3_kvm.c | 12 | --- a/target/arm/translate.c |
27 | +++ b/hw/intc/arm_gicv3_kvm.c | 13 | +++ b/target/arm/translate.c |
28 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s) | 14 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
29 | kvm_gicd_access(s, GICD_CTLR, ®, true); | 15 | { |
30 | 16 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
31 | if (redist_typer & GICR_TYPER_PLPIS) { | 17 | CPUARMState *env = cpu->env_ptr; |
32 | - /* Set base addresses before LPIs are enabled by GICR_CTLR write */ | 18 | + uint32_t pc = dc->base.pc_next; |
33 | + /* | 19 | unsigned int insn; |
34 | + * Restore base addresses before LPIs are potentially enabled by | 20 | |
35 | + * GICR_CTLR write | 21 | if (arm_pre_translate_insn(dc)) { |
36 | + */ | 22 | - dc->base.pc_next += 4; |
37 | for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { | 23 | + dc->base.pc_next = pc + 4; |
38 | GICv3CPUState *c = &s->cpu[ncpu]; | 24 | return; |
39 | 25 | } | |
40 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s) | 26 | |
41 | kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); | 27 | - dc->pc_curr = dc->base.pc_next; |
42 | 28 | - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); | |
43 | reg64 = c->gicr_pendbaser; | 29 | + dc->pc_curr = pc; |
44 | - if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { | 30 | + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); |
45 | - /* Setting PTZ is advised if LPIs are disabled, to reduce | 31 | dc->insn = insn; |
46 | - * GIC initialization time. | 32 | - dc->base.pc_next += 4; |
47 | - */ | 33 | + dc->base.pc_next = pc + 4; |
48 | - reg64 |= GICR_PENDBASER_PTZ; | 34 | disas_arm_insn(dc, insn); |
49 | - } | 35 | |
50 | regl = (uint32_t)reg64; | 36 | arm_post_translate_insn(dc); |
51 | kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); | ||
52 | regh = (uint32_t)(reg64 >> 32); | ||
53 | -- | 37 | -- |
54 | 2.20.1 | 38 | 2.25.1 |
55 | 39 | ||
56 | 40 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The overhead for the OpenBMC firmware images using the a custom U-Boot | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | is around 2 seconds, which is fine, but with a U-Boot from mainline, | ||
5 | it takes an extra 50 seconds or so to reach Linux. A quick survey on | ||
6 | the number of reads performed on the flash memory region gives the | ||
7 | following figures : | ||
8 | |||
9 | OpenBMC U-Boot 922478 (~ 3.5 MBytes) | ||
10 | Mainline U-Boot 20569977 (~ 80 MBytes) | ||
11 | |||
12 | QEMU must be trashing the TCG TBs and reloading text very often. Some | ||
13 | addresses are read more than 250.000 times. Until we find a solution | ||
14 | to improve boot time, execution from MMIO is not activated by default. | ||
15 | |||
16 | Setting this option also breaks migration compatibility. | ||
17 | |||
18 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
21 | Message-id: 20200114103433.30534-5-clg@kaod.org | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | --- | 6 | --- |
24 | include/hw/arm/aspeed.h | 2 ++ | 7 | target/arm/translate.c | 16 ++++++++-------- |
25 | hw/arm/aspeed.c | 44 ++++++++++++++++++++++++++++++++++++----- | 8 | 1 file changed, 8 insertions(+), 8 deletions(-) |
26 | 2 files changed, 41 insertions(+), 5 deletions(-) | ||
27 | 9 | ||
28 | diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h | 10 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
29 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/hw/arm/aspeed.h | 12 | --- a/target/arm/translate.c |
31 | +++ b/include/hw/arm/aspeed.h | 13 | +++ b/target/arm/translate.c |
32 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardState AspeedBoardState; | 14 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
33 | 15 | { | |
34 | typedef struct AspeedMachine { | 16 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
35 | MachineState parent_obj; | 17 | CPUARMState *env = cpu->env_ptr; |
36 | + | 18 | + uint32_t pc = dc->base.pc_next; |
37 | + bool mmio_exec; | 19 | uint32_t insn; |
38 | } AspeedMachine; | 20 | bool is_16bit; |
39 | 21 | ||
40 | #define ASPEED_MACHINE_CLASS(klass) \ | 22 | if (arm_pre_translate_insn(dc)) { |
41 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 23 | - dc->base.pc_next += 2; |
42 | index XXXXXXX..XXXXXXX 100644 | 24 | + dc->base.pc_next = pc + 2; |
43 | --- a/hw/arm/aspeed.c | 25 | return; |
44 | +++ b/hw/arm/aspeed.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
46 | * SoC and 128MB for the AST2500 SoC, which is twice as big as | ||
47 | * needed by the flash modules of the Aspeed machines. | ||
48 | */ | ||
49 | - memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", | ||
50 | - fl->size, &error_abort); | ||
51 | - memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | ||
52 | - boot_rom); | ||
53 | - write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); | ||
54 | + if (ASPEED_MACHINE(machine)->mmio_exec) { | ||
55 | + memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", | ||
56 | + &fl->mmio, 0, fl->size); | ||
57 | + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | ||
58 | + boot_rom); | ||
59 | + } else { | ||
60 | + memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", | ||
61 | + fl->size, &error_abort); | ||
62 | + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | ||
63 | + boot_rom); | ||
64 | + write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); | ||
65 | + } | ||
66 | } | 26 | } |
67 | 27 | ||
68 | aspeed_board_binfo.ram_size = ram_size; | 28 | - dc->pc_curr = dc->base.pc_next; |
69 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) | 29 | - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); |
70 | /* Bus 11: TODO ucd90160@64 */ | 30 | + dc->pc_curr = pc; |
71 | } | 31 | + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); |
72 | 32 | is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); | |
73 | +static bool aspeed_get_mmio_exec(Object *obj, Error **errp) | 33 | - dc->base.pc_next += 2; |
74 | +{ | 34 | + pc += 2; |
75 | + return ASPEED_MACHINE(obj)->mmio_exec; | 35 | if (!is_16bit) { |
76 | +} | 36 | - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, |
77 | + | 37 | - dc->sctlr_b); |
78 | +static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) | 38 | - |
79 | +{ | 39 | + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); |
80 | + ASPEED_MACHINE(obj)->mmio_exec = value; | 40 | insn = insn << 16 | insn2; |
81 | +} | 41 | - dc->base.pc_next += 2; |
82 | + | 42 | + pc += 2; |
83 | +static void aspeed_machine_instance_init(Object *obj) | 43 | } |
84 | +{ | 44 | + dc->base.pc_next = pc; |
85 | + ASPEED_MACHINE(obj)->mmio_exec = false; | 45 | dc->insn = insn; |
86 | +} | 46 | |
87 | + | 47 | if (dc->pstate_il) { |
88 | +static void aspeed_machine_class_props_init(ObjectClass *oc) | ||
89 | +{ | ||
90 | + object_class_property_add_bool(oc, "execute-in-place", | ||
91 | + aspeed_get_mmio_exec, | ||
92 | + aspeed_set_mmio_exec, &error_abort); | ||
93 | + object_class_property_set_description(oc, "execute-in-place", | ||
94 | + "boot directly from CE0 flash device", &error_abort); | ||
95 | +} | ||
96 | + | ||
97 | static void aspeed_machine_class_init(ObjectClass *oc, void *data) | ||
98 | { | ||
99 | MachineClass *mc = MACHINE_CLASS(oc); | ||
100 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) | ||
101 | mc->no_floppy = 1; | ||
102 | mc->no_cdrom = 1; | ||
103 | mc->no_parallel = 1; | ||
104 | + | ||
105 | + aspeed_machine_class_props_init(oc); | ||
106 | } | ||
107 | |||
108 | static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) | ||
109 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { | ||
110 | .name = TYPE_ASPEED_MACHINE, | ||
111 | .parent = TYPE_MACHINE, | ||
112 | .instance_size = sizeof(AspeedMachine), | ||
113 | + .instance_init = aspeed_machine_instance_init, | ||
114 | .class_size = sizeof(AspeedMachineClass), | ||
115 | .class_init = aspeed_machine_class_init, | ||
116 | .abstract = true, | ||
117 | -- | 48 | -- |
118 | 2.20.1 | 49 | 2.25.1 |
119 | 50 | ||
120 | 51 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Deprecate device_legacy_reset(), qdev_reset_all() and | 3 | Create arm_check_ss_active and arm_check_kernelpage. |
4 | qbus_reset_all() to be replaced by new functions | ||
5 | device_cold_reset() and bus_cold_reset() which uses resettable API. | ||
6 | 4 | ||
7 | Also introduce resettable_cold_reset_fn() which may be used as a | 5 | Reverse the order of the tests. While it doesn't matter in practice, |
8 | replacement for qdev_reset_all_fn and qbus_reset_all_fn(). | 6 | because only user-only has a kernel page and user-only never sets |
7 | ss_active, ss_active has priority over execution exceptions and it | ||
8 | is best to keep them in the proper order. | ||
9 | 9 | ||
10 | Following patches will be needed to look at legacy reset call sites | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | and switch to resettable api. The legacy functions will be removed | ||
12 | when unused. | ||
13 | |||
14 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
19 | Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 13 | --- |
22 | include/hw/qdev-core.h | 27 +++++++++++++++++++++++++++ | 14 | target/arm/translate.c | 10 +++++++--- |
23 | include/hw/resettable.h | 9 +++++++++ | 15 | 1 file changed, 7 insertions(+), 3 deletions(-) |
24 | hw/core/bus.c | 5 +++++ | ||
25 | hw/core/qdev.c | 5 +++++ | ||
26 | hw/core/resettable.c | 5 +++++ | ||
27 | 5 files changed, 51 insertions(+) | ||
28 | 16 | ||
29 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
30 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/include/hw/qdev-core.h | 19 | --- a/target/arm/translate.c |
32 | +++ b/include/hw/qdev-core.h | 20 | +++ b/target/arm/translate.c |
33 | @@ -XXX,XX +XXX,XX @@ int qdev_walk_children(DeviceState *dev, | 21 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
34 | qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn, | 22 | dc->insn_start = tcg_last_op(); |
35 | void *opaque); | ||
36 | |||
37 | +/** | ||
38 | + * @qdev_reset_all: | ||
39 | + * Reset @dev. See @qbus_reset_all() for more details. | ||
40 | + * | ||
41 | + * Note: This function is deprecated and will be removed when it becomes unused. | ||
42 | + * Please use device_cold_reset() now. | ||
43 | + */ | ||
44 | void qdev_reset_all(DeviceState *dev); | ||
45 | void qdev_reset_all_fn(void *opaque); | ||
46 | |||
47 | @@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque); | ||
48 | * hard reset means that qbus_reset_all will reset all state of the device. | ||
49 | * For PCI devices, for example, this will include the base address registers | ||
50 | * or configuration space. | ||
51 | + * | ||
52 | + * Note: This function is deprecated and will be removed when it becomes unused. | ||
53 | + * Please use bus_cold_reset() now. | ||
54 | */ | ||
55 | void qbus_reset_all(BusState *bus); | ||
56 | void qbus_reset_all_fn(void *opaque); | ||
57 | |||
58 | +/** | ||
59 | + * device_cold_reset: | ||
60 | + * Reset device @dev and perform a recursive processing using the resettable | ||
61 | + * interface. It triggers a RESET_TYPE_COLD. | ||
62 | + */ | ||
63 | +void device_cold_reset(DeviceState *dev); | ||
64 | + | ||
65 | +/** | ||
66 | + * bus_cold_reset: | ||
67 | + * | ||
68 | + * Reset bus @bus and perform a recursive processing using the resettable | ||
69 | + * interface. It triggers a RESET_TYPE_COLD. | ||
70 | + */ | ||
71 | +void bus_cold_reset(BusState *bus); | ||
72 | + | ||
73 | /** | ||
74 | * device_is_in_reset: | ||
75 | * Return true if the device @dev is currently being reset. | ||
76 | @@ -XXX,XX +XXX,XX @@ void qdev_machine_init(void); | ||
77 | * device_legacy_reset: | ||
78 | * | ||
79 | * Reset a single device (by calling the reset method). | ||
80 | + * Note: This function is deprecated and will be removed when it becomes unused. | ||
81 | + * Please use device_cold_reset() now. | ||
82 | */ | ||
83 | void device_legacy_reset(DeviceState *dev); | ||
84 | |||
85 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/include/hw/resettable.h | ||
88 | +++ b/include/hw/resettable.h | ||
89 | @@ -XXX,XX +XXX,XX @@ bool resettable_is_in_reset(Object *obj); | ||
90 | */ | ||
91 | void resettable_change_parent(Object *obj, Object *newp, Object *oldp); | ||
92 | |||
93 | +/** | ||
94 | + * resettable_cold_reset_fn: | ||
95 | + * Helper to call resettable_reset((Object *) opaque, RESET_TYPE_COLD). | ||
96 | + * | ||
97 | + * This function is typically useful to register a reset handler with | ||
98 | + * qemu_register_reset. | ||
99 | + */ | ||
100 | +void resettable_cold_reset_fn(void *opaque); | ||
101 | + | ||
102 | /** | ||
103 | * resettable_class_set_parent_phases: | ||
104 | * | ||
105 | diff --git a/hw/core/bus.c b/hw/core/bus.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/hw/core/bus.c | ||
108 | +++ b/hw/core/bus.c | ||
109 | @@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus, | ||
110 | return 0; | ||
111 | } | 23 | } |
112 | 24 | ||
113 | +void bus_cold_reset(BusState *bus) | 25 | -static bool arm_pre_translate_insn(DisasContext *dc) |
26 | +static bool arm_check_kernelpage(DisasContext *dc) | ||
27 | { | ||
28 | #ifdef CONFIG_USER_ONLY | ||
29 | /* Intercept jump to the magic kernel page. */ | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc) | ||
31 | return true; | ||
32 | } | ||
33 | #endif | ||
34 | + return false; | ||
35 | +} | ||
36 | |||
37 | +static bool arm_check_ss_active(DisasContext *dc) | ||
114 | +{ | 38 | +{ |
115 | + resettable_reset(OBJECT(bus), RESET_TYPE_COLD); | 39 | if (dc->ss_active && !dc->pstate_ss) { |
116 | +} | 40 | /* Singlestep state is Active-pending. |
117 | + | 41 | * If we're in this state at the start of a TB then either |
118 | bool bus_is_in_reset(BusState *bus) | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
119 | { | 43 | uint32_t pc = dc->base.pc_next; |
120 | return resettable_is_in_reset(OBJECT(bus)); | 44 | unsigned int insn; |
121 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 45 | |
122 | index XXXXXXX..XXXXXXX 100644 | 46 | - if (arm_pre_translate_insn(dc)) { |
123 | --- a/hw/core/qdev.c | 47 | + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
124 | +++ b/hw/core/qdev.c | 48 | dc->base.pc_next = pc + 4; |
125 | @@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque) | 49 | return; |
126 | qbus_reset_all(bus); | ||
127 | } | ||
128 | |||
129 | +void device_cold_reset(DeviceState *dev) | ||
130 | +{ | ||
131 | + resettable_reset(OBJECT(dev), RESET_TYPE_COLD); | ||
132 | +} | ||
133 | + | ||
134 | bool device_is_in_reset(DeviceState *dev) | ||
135 | { | ||
136 | return resettable_is_in_reset(OBJECT(dev)); | ||
137 | diff --git a/hw/core/resettable.c b/hw/core/resettable.c | ||
138 | index XXXXXXX..XXXXXXX 100644 | ||
139 | --- a/hw/core/resettable.c | ||
140 | +++ b/hw/core/resettable.c | ||
141 | @@ -XXX,XX +XXX,XX @@ void resettable_change_parent(Object *obj, Object *newp, Object *oldp) | ||
142 | } | 50 | } |
143 | } | 51 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
144 | 52 | uint32_t insn; | |
145 | +void resettable_cold_reset_fn(void *opaque) | 53 | bool is_16bit; |
146 | +{ | 54 | |
147 | + resettable_reset((Object *) opaque, RESET_TYPE_COLD); | 55 | - if (arm_pre_translate_insn(dc)) { |
148 | +} | 56 | + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
149 | + | 57 | dc->base.pc_next = pc + 2; |
150 | void resettable_class_set_parent_phases(ResettableClass *rc, | 58 | return; |
151 | ResettableEnterPhase enter, | 59 | } |
152 | ResettableHoldPhase hold, | ||
153 | -- | 60 | -- |
154 | 2.20.1 | 61 | 2.25.1 |
155 | 62 | ||
156 | 63 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add the missing GENERIC_TIMER feature to kvm64 cpus. | 3 | The size of the code covered by a TranslationBlock cannot be 0; |
4 | this is checked via assert in tb_gen_code. | ||
4 | 5 | ||
5 | We don't currently use these registers when KVM is enabled, but it's | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | probably best we add the feature flag for consistency and potential | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | future use. There's also precedent, as we add the PMU feature flag to | ||
8 | KVM enabled guests, even though we don't use those registers either. | ||
9 | |||
10 | This change was originally posted as a hunk of a different, never | ||
11 | merged patch from Bijan Mottahedeh. | ||
12 | |||
13 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20200120101023.16030-4-drjones@redhat.com | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 9 | --- |
18 | target/arm/kvm64.c | 1 + | 10 | target/arm/translate-a64.c | 1 + |
19 | 1 file changed, 1 insertion(+) | 11 | 1 file changed, 1 insertion(+) |
20 | 12 | ||
21 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
22 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/kvm64.c | 15 | --- a/target/arm/translate-a64.c |
24 | +++ b/target/arm/kvm64.c | 16 | +++ b/target/arm/translate-a64.c |
25 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | 17 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
26 | set_feature(&features, ARM_FEATURE_NEON); | 18 | assert(s->base.num_insns == 1); |
27 | set_feature(&features, ARM_FEATURE_AARCH64); | 19 | gen_swstep_exception(s, 0, 0); |
28 | set_feature(&features, ARM_FEATURE_PMU); | 20 | s->base.is_jmp = DISAS_NORETURN; |
29 | + set_feature(&features, ARM_FEATURE_GENERIC_TIMER); | 21 | + s->base.pc_next = pc + 4; |
30 | 22 | return; | |
31 | ahcf->features = features; | 23 | } |
32 | 24 | ||
33 | -- | 25 | -- |
34 | 2.20.1 | 26 | 2.25.1 |
35 | 27 | ||
36 | 28 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This commit adds support of Resettable interface to buses and devices: | 3 | We will reuse this section of arm_deliver_fault for |
4 | + ResettableState structure is added in the Bus/Device state | 4 | raising pc alignment faults. |
5 | + Resettable methods are implemented. | ||
6 | + device/bus_is_in_reset function defined | ||
7 | 5 | ||
8 | This commit allows to transition the objects to the new | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | multi-phase interface without changing the reset behavior at all. | ||
10 | Object single reset method can be split into the 3 different phases | ||
11 | but the 3 phases are still executed in a row for a given object. | ||
12 | From the qdev/qbus reset api point of view, nothing is changed. | ||
13 | qdev_reset_all() and qbus_reset_all() are not modified as well as | ||
14 | device_legacy_reset(). | ||
15 | |||
16 | Transition of an object must be done from parent class to child class. | ||
17 | Care has been taken to allow the transition of a parent class | ||
18 | without requiring the child classes to be transitioned at the same | ||
19 | time. Note that SysBus and SysBusDevice class do not need any transition | ||
20 | because they do not override the legacy reset method. | ||
21 | |||
22 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
26 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
27 | Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com | ||
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
29 | --- | 9 | --- |
30 | tests/Makefile.include | 1 + | 10 | target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++---------------- |
31 | include/hw/qdev-core.h | 27 ++++++++++++ | 11 | 1 file changed, 28 insertions(+), 17 deletions(-) |
32 | hw/core/bus.c | 97 ++++++++++++++++++++++++++++++++++++++++++ | ||
33 | hw/core/qdev.c | 93 ++++++++++++++++++++++++++++++++++++++++ | ||
34 | 4 files changed, 218 insertions(+) | ||
35 | 12 | ||
36 | diff --git a/tests/Makefile.include b/tests/Makefile.include | 13 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c |
37 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/tests/Makefile.include | 15 | --- a/target/arm/tlb_helper.c |
39 | +++ b/tests/Makefile.include | 16 | +++ b/target/arm/tlb_helper.c |
40 | @@ -XXX,XX +XXX,XX @@ tests/fp/%: | 17 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, |
41 | tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ | 18 | return syn; |
42 | hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ | ||
43 | hw/core/bus.o \ | ||
44 | + hw/core/resettable.o \ | ||
45 | hw/core/irq.o \ | ||
46 | hw/core/fw-path-provider.o \ | ||
47 | hw/core/reset.o \ | ||
48 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/include/hw/qdev-core.h | ||
51 | +++ b/include/hw/qdev-core.h | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | #include "qemu/bitmap.h" | ||
54 | #include "qom/object.h" | ||
55 | #include "hw/hotplug.h" | ||
56 | +#include "hw/resettable.h" | ||
57 | |||
58 | enum { | ||
59 | DEV_NVECTORS_UNSPECIFIED = -1, | ||
60 | @@ -XXX,XX +XXX,XX @@ typedef struct DeviceClass { | ||
61 | bool hotpluggable; | ||
62 | |||
63 | /* callbacks */ | ||
64 | + /* | ||
65 | + * Reset method here is deprecated and replaced by methods in the | ||
66 | + * resettable class interface to implement a multi-phase reset. | ||
67 | + * TODO: remove once every reset callback is unused | ||
68 | + */ | ||
69 | DeviceReset reset; | ||
70 | DeviceRealize realize; | ||
71 | DeviceUnrealize unrealize; | ||
72 | @@ -XXX,XX +XXX,XX @@ struct NamedGPIOList { | ||
73 | /** | ||
74 | * DeviceState: | ||
75 | * @realized: Indicates whether the device has been fully constructed. | ||
76 | + * @reset: ResettableState for the device; handled by Resettable interface. | ||
77 | * | ||
78 | * This structure should not be accessed directly. We declare it here | ||
79 | * so that it can be embedded in individual device state structures. | ||
80 | @@ -XXX,XX +XXX,XX @@ struct DeviceState { | ||
81 | int num_child_bus; | ||
82 | int instance_id_alias; | ||
83 | int alias_required_for_version; | ||
84 | + ResettableState reset; | ||
85 | }; | ||
86 | |||
87 | struct DeviceListener { | ||
88 | @@ -XXX,XX +XXX,XX @@ typedef struct BusChild { | ||
89 | /** | ||
90 | * BusState: | ||
91 | * @hotplug_handler: link to a hotplug handler associated with bus. | ||
92 | + * @reset: ResettableState for the bus; handled by Resettable interface. | ||
93 | */ | ||
94 | struct BusState { | ||
95 | Object obj; | ||
96 | @@ -XXX,XX +XXX,XX @@ struct BusState { | ||
97 | int num_children; | ||
98 | QTAILQ_HEAD(, BusChild) children; | ||
99 | QLIST_ENTRY(BusState) sibling; | ||
100 | + ResettableState reset; | ||
101 | }; | ||
102 | |||
103 | /** | ||
104 | @@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque); | ||
105 | void qbus_reset_all(BusState *bus); | ||
106 | void qbus_reset_all_fn(void *opaque); | ||
107 | |||
108 | +/** | ||
109 | + * device_is_in_reset: | ||
110 | + * Return true if the device @dev is currently being reset. | ||
111 | + */ | ||
112 | +bool device_is_in_reset(DeviceState *dev); | ||
113 | + | ||
114 | +/** | ||
115 | + * bus_is_in_reset: | ||
116 | + * Return true if the bus @bus is currently being reset. | ||
117 | + */ | ||
118 | +bool bus_is_in_reset(BusState *bus); | ||
119 | + | ||
120 | /* This should go away once we get rid of the NULL bus hack */ | ||
121 | BusState *sysbus_get_default(void); | ||
122 | |||
123 | @@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev); | ||
124 | |||
125 | void device_class_set_props(DeviceClass *dc, Property *props); | ||
126 | |||
127 | +/** | ||
128 | + * device_class_set_parent_reset: | ||
129 | + * TODO: remove the function when DeviceClass's reset method | ||
130 | + * is not used anymore. | ||
131 | + */ | ||
132 | void device_class_set_parent_reset(DeviceClass *dc, | ||
133 | DeviceReset dev_reset, | ||
134 | DeviceReset *parent_reset); | ||
135 | diff --git a/hw/core/bus.c b/hw/core/bus.c | ||
136 | index XXXXXXX..XXXXXXX 100644 | ||
137 | --- a/hw/core/bus.c | ||
138 | +++ b/hw/core/bus.c | ||
139 | @@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus, | ||
140 | return 0; | ||
141 | } | 19 | } |
142 | 20 | ||
143 | +bool bus_is_in_reset(BusState *bus) | 21 | -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
144 | +{ | 22 | - MMUAccessType access_type, |
145 | + return resettable_is_in_reset(OBJECT(bus)); | 23 | - int mmu_idx, ARMMMUFaultInfo *fi) |
24 | +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, | ||
25 | + int target_el, int mmu_idx, uint32_t *ret_fsc) | ||
26 | { | ||
27 | - CPUARMState *env = &cpu->env; | ||
28 | - int target_el; | ||
29 | - bool same_el; | ||
30 | - uint32_t syn, exc, fsr, fsc; | ||
31 | ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); | ||
32 | - | ||
33 | - target_el = exception_target_el(env); | ||
34 | - if (fi->stage2) { | ||
35 | - target_el = 2; | ||
36 | - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; | ||
37 | - if (arm_is_secure_below_el3(env) && fi->s1ns) { | ||
38 | - env->cp15.hpfar_el2 |= HPFAR_NS; | ||
39 | - } | ||
40 | - } | ||
41 | - same_el = (arm_current_el(env) == target_el); | ||
42 | + uint32_t fsr, fsc; | ||
43 | |||
44 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | ||
45 | arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { | ||
46 | @@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, | ||
47 | fsc = 0x3f; | ||
48 | } | ||
49 | |||
50 | + *ret_fsc = fsc; | ||
51 | + return fsr; | ||
146 | +} | 52 | +} |
147 | + | 53 | + |
148 | +static ResettableState *bus_get_reset_state(Object *obj) | 54 | +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
55 | + MMUAccessType access_type, | ||
56 | + int mmu_idx, ARMMMUFaultInfo *fi) | ||
149 | +{ | 57 | +{ |
150 | + BusState *bus = BUS(obj); | 58 | + CPUARMState *env = &cpu->env; |
151 | + return &bus->reset; | 59 | + int target_el; |
152 | +} | 60 | + bool same_el; |
61 | + uint32_t syn, exc, fsr, fsc; | ||
153 | + | 62 | + |
154 | +static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb, | 63 | + target_el = exception_target_el(env); |
155 | + void *opaque, ResetType type) | 64 | + if (fi->stage2) { |
156 | +{ | 65 | + target_el = 2; |
157 | + BusState *bus = BUS(obj); | 66 | + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; |
158 | + BusChild *kid; | 67 | + if (arm_is_secure_below_el3(env) && fi->s1ns) { |
68 | + env->cp15.hpfar_el2 |= HPFAR_NS; | ||
69 | + } | ||
70 | + } | ||
71 | + same_el = (arm_current_el(env) == target_el); | ||
159 | + | 72 | + |
160 | + QTAILQ_FOREACH(kid, &bus->children, sibling) { | 73 | + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); |
161 | + cb(OBJECT(kid->child), opaque, type); | ||
162 | + } | ||
163 | +} | ||
164 | + | 74 | + |
165 | static void qbus_realize(BusState *bus, DeviceState *parent, const char *name) | 75 | if (access_type == MMU_INST_FETCH) { |
166 | { | 76 | syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); |
167 | const char *typename = object_get_typename(OBJECT(bus)); | 77 | exc = EXCP_PREFETCH_ABORT; |
168 | @@ -XXX,XX +XXX,XX @@ static char *default_bus_get_fw_dev_path(DeviceState *dev) | ||
169 | return g_strdup(object_get_typename(OBJECT(dev))); | ||
170 | } | ||
171 | |||
172 | +/** | ||
173 | + * bus_phases_reset: | ||
174 | + * Transition reset method for buses to allow moving | ||
175 | + * smoothly from legacy reset method to multi-phases | ||
176 | + */ | ||
177 | +static void bus_phases_reset(BusState *bus) | ||
178 | +{ | ||
179 | + ResettableClass *rc = RESETTABLE_GET_CLASS(bus); | ||
180 | + | ||
181 | + if (rc->phases.enter) { | ||
182 | + rc->phases.enter(OBJECT(bus), RESET_TYPE_COLD); | ||
183 | + } | ||
184 | + if (rc->phases.hold) { | ||
185 | + rc->phases.hold(OBJECT(bus)); | ||
186 | + } | ||
187 | + if (rc->phases.exit) { | ||
188 | + rc->phases.exit(OBJECT(bus)); | ||
189 | + } | ||
190 | +} | ||
191 | + | ||
192 | +static void bus_transitional_reset(Object *obj) | ||
193 | +{ | ||
194 | + BusClass *bc = BUS_GET_CLASS(obj); | ||
195 | + | ||
196 | + /* | ||
197 | + * This will call either @bus_phases_reset (for multi-phases transitioned | ||
198 | + * buses) or a bus's specific method for not-yet transitioned buses. | ||
199 | + * In both case, it does not reset children. | ||
200 | + */ | ||
201 | + if (bc->reset) { | ||
202 | + bc->reset(BUS(obj)); | ||
203 | + } | ||
204 | +} | ||
205 | + | ||
206 | +/** | ||
207 | + * bus_get_transitional_reset: | ||
208 | + * check if the bus's class is ready for multi-phase | ||
209 | + */ | ||
210 | +static ResettableTrFunction bus_get_transitional_reset(Object *obj) | ||
211 | +{ | ||
212 | + BusClass *dc = BUS_GET_CLASS(obj); | ||
213 | + if (dc->reset != bus_phases_reset) { | ||
214 | + /* | ||
215 | + * dc->reset has been overridden by a subclass, | ||
216 | + * the bus is not ready for multi phase yet. | ||
217 | + */ | ||
218 | + return bus_transitional_reset; | ||
219 | + } | ||
220 | + return NULL; | ||
221 | +} | ||
222 | + | ||
223 | static void bus_class_init(ObjectClass *class, void *data) | ||
224 | { | ||
225 | BusClass *bc = BUS_CLASS(class); | ||
226 | + ResettableClass *rc = RESETTABLE_CLASS(class); | ||
227 | |||
228 | class->unparent = bus_unparent; | ||
229 | bc->get_fw_dev_path = default_bus_get_fw_dev_path; | ||
230 | + | ||
231 | + rc->get_state = bus_get_reset_state; | ||
232 | + rc->child_foreach = bus_reset_child_foreach; | ||
233 | + | ||
234 | + /* | ||
235 | + * @bus_phases_reset is put as the default reset method below, allowing | ||
236 | + * to do the multi-phase transition from base classes to leaf classes. It | ||
237 | + * allows a legacy-reset Bus class to extend a multi-phases-reset | ||
238 | + * Bus class for the following reason: | ||
239 | + * + If a base class B has been moved to multi-phase, then it does not | ||
240 | + * override this default reset method and may have defined phase methods. | ||
241 | + * + A child class C (extending class B) which uses | ||
242 | + * bus_class_set_parent_reset() (or similar means) to override the | ||
243 | + * reset method will still work as expected. @bus_phases_reset function | ||
244 | + * will be registered as the parent reset method and effectively call | ||
245 | + * parent reset phases. | ||
246 | + */ | ||
247 | + bc->reset = bus_phases_reset; | ||
248 | + rc->get_transitional_function = bus_get_transitional_reset; | ||
249 | } | ||
250 | |||
251 | static void qbus_finalize(Object *obj) | ||
252 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo bus_info = { | ||
253 | .instance_init = qbus_initfn, | ||
254 | .instance_finalize = qbus_finalize, | ||
255 | .class_init = bus_class_init, | ||
256 | + .interfaces = (InterfaceInfo[]) { | ||
257 | + { TYPE_RESETTABLE_INTERFACE }, | ||
258 | + { } | ||
259 | + }, | ||
260 | }; | ||
261 | |||
262 | static void bus_register_types(void) | ||
263 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
264 | index XXXXXXX..XXXXXXX 100644 | ||
265 | --- a/hw/core/qdev.c | ||
266 | +++ b/hw/core/qdev.c | ||
267 | @@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque) | ||
268 | qbus_reset_all(bus); | ||
269 | } | ||
270 | |||
271 | +bool device_is_in_reset(DeviceState *dev) | ||
272 | +{ | ||
273 | + return resettable_is_in_reset(OBJECT(dev)); | ||
274 | +} | ||
275 | + | ||
276 | +static ResettableState *device_get_reset_state(Object *obj) | ||
277 | +{ | ||
278 | + DeviceState *dev = DEVICE(obj); | ||
279 | + return &dev->reset; | ||
280 | +} | ||
281 | + | ||
282 | +static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb, | ||
283 | + void *opaque, ResetType type) | ||
284 | +{ | ||
285 | + DeviceState *dev = DEVICE(obj); | ||
286 | + BusState *bus; | ||
287 | + | ||
288 | + QLIST_FOREACH(bus, &dev->child_bus, sibling) { | ||
289 | + cb(OBJECT(bus), opaque, type); | ||
290 | + } | ||
291 | +} | ||
292 | + | ||
293 | /* can be used as ->unplug() callback for the simple cases */ | ||
294 | void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, | ||
295 | DeviceState *dev, Error **errp) | ||
296 | @@ -XXX,XX +XXX,XX @@ device_vmstate_if_get_id(VMStateIf *obj) | ||
297 | return qdev_get_dev_path(dev); | ||
298 | } | ||
299 | |||
300 | +/** | ||
301 | + * device_phases_reset: | ||
302 | + * Transition reset method for devices to allow moving | ||
303 | + * smoothly from legacy reset method to multi-phases | ||
304 | + */ | ||
305 | +static void device_phases_reset(DeviceState *dev) | ||
306 | +{ | ||
307 | + ResettableClass *rc = RESETTABLE_GET_CLASS(dev); | ||
308 | + | ||
309 | + if (rc->phases.enter) { | ||
310 | + rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD); | ||
311 | + } | ||
312 | + if (rc->phases.hold) { | ||
313 | + rc->phases.hold(OBJECT(dev)); | ||
314 | + } | ||
315 | + if (rc->phases.exit) { | ||
316 | + rc->phases.exit(OBJECT(dev)); | ||
317 | + } | ||
318 | +} | ||
319 | + | ||
320 | +static void device_transitional_reset(Object *obj) | ||
321 | +{ | ||
322 | + DeviceClass *dc = DEVICE_GET_CLASS(obj); | ||
323 | + | ||
324 | + /* | ||
325 | + * This will call either @device_phases_reset (for multi-phases transitioned | ||
326 | + * devices) or a device's specific method for not-yet transitioned devices. | ||
327 | + * In both case, it does not reset children. | ||
328 | + */ | ||
329 | + if (dc->reset) { | ||
330 | + dc->reset(DEVICE(obj)); | ||
331 | + } | ||
332 | +} | ||
333 | + | ||
334 | +/** | ||
335 | + * device_get_transitional_reset: | ||
336 | + * check if the device's class is ready for multi-phase | ||
337 | + */ | ||
338 | +static ResettableTrFunction device_get_transitional_reset(Object *obj) | ||
339 | +{ | ||
340 | + DeviceClass *dc = DEVICE_GET_CLASS(obj); | ||
341 | + if (dc->reset != device_phases_reset) { | ||
342 | + /* | ||
343 | + * dc->reset has been overridden by a subclass, | ||
344 | + * the device is not ready for multi phase yet. | ||
345 | + */ | ||
346 | + return device_transitional_reset; | ||
347 | + } | ||
348 | + return NULL; | ||
349 | +} | ||
350 | + | ||
351 | static void device_class_init(ObjectClass *class, void *data) | ||
352 | { | ||
353 | DeviceClass *dc = DEVICE_CLASS(class); | ||
354 | VMStateIfClass *vc = VMSTATE_IF_CLASS(class); | ||
355 | + ResettableClass *rc = RESETTABLE_CLASS(class); | ||
356 | |||
357 | class->unparent = device_unparent; | ||
358 | |||
359 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | ||
360 | dc->hotpluggable = true; | ||
361 | dc->user_creatable = true; | ||
362 | vc->get_id = device_vmstate_if_get_id; | ||
363 | + rc->get_state = device_get_reset_state; | ||
364 | + rc->child_foreach = device_reset_child_foreach; | ||
365 | + | ||
366 | + /* | ||
367 | + * @device_phases_reset is put as the default reset method below, allowing | ||
368 | + * to do the multi-phase transition from base classes to leaf classes. It | ||
369 | + * allows a legacy-reset Device class to extend a multi-phases-reset | ||
370 | + * Device class for the following reason: | ||
371 | + * + If a base class B has been moved to multi-phase, then it does not | ||
372 | + * override this default reset method and may have defined phase methods. | ||
373 | + * + A child class C (extending class B) which uses | ||
374 | + * device_class_set_parent_reset() (or similar means) to override the | ||
375 | + * reset method will still work as expected. @device_phases_reset function | ||
376 | + * will be registered as the parent reset method and effectively call | ||
377 | + * parent reset phases. | ||
378 | + */ | ||
379 | + dc->reset = device_phases_reset; | ||
380 | + rc->get_transitional_function = device_get_transitional_reset; | ||
381 | |||
382 | object_class_property_add_bool(class, "realized", | ||
383 | device_get_realized, device_set_realized, | ||
384 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo device_type_info = { | ||
385 | .class_size = sizeof(DeviceClass), | ||
386 | .interfaces = (InterfaceInfo[]) { | ||
387 | { TYPE_VMSTATE_IF }, | ||
388 | + { TYPE_RESETTABLE_INTERFACE }, | ||
389 | { } | ||
390 | } | ||
391 | }; | ||
392 | -- | 78 | -- |
393 | 2.20.1 | 79 | 2.25.1 |
394 | 80 | ||
395 | 81 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When a VM is stopped (such as when it's paused) guest virtual time | 3 | For A64, any input to an indirect branch can cause this. |
4 | should stop counting. Otherwise, when the VM is resumed it will | 4 | |
5 | experience time jumps and its kernel may report soft lockups. Not | 5 | For A32, many indirect branch paths force the branch to be aligned, |
6 | counting virtual time while the VM is stopped has the side effect | 6 | but BXWritePC does not. This includes the BX instruction but also |
7 | of making the guest's time appear to lag when compared with real | 7 | other interworking changes to PC. Prior to v8, this case is UNDEFINED. |
8 | time, and even with time derived from the physical counter. For | 8 | With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an |
9 | this reason, this change, which is enabled by default, comes with | 9 | exception or force align the PC. |
10 | a KVM CPU feature allowing it to be disabled, restoring legacy | 10 | |
11 | behavior. | 11 | We choose to raise an exception because we have the infrastructure, |
12 | 12 | it makes the generated code for gen_bx simpler, and it has the | |
13 | This patch only provides the implementation of the virtual time | 13 | possibility of catching more guest bugs. |
14 | adjustment. A subsequent patch will provide the CPU property | 14 | |
15 | allowing the change to be enabled and disabled. | 15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
16 | |||
17 | Reported-by: Bijan Mottahedeh <bijan.mottahedeh@oracle.com> | ||
18 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
19 | Message-id: 20200120101023.16030-6-drjones@redhat.com | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 18 | --- |
23 | target/arm/cpu.h | 7 ++++ | 19 | target/arm/helper.h | 1 + |
24 | target/arm/kvm_arm.h | 38 ++++++++++++++++++ | 20 | target/arm/syndrome.h | 5 ++++ |
25 | target/arm/kvm.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ | 21 | linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++--------------- |
26 | target/arm/kvm32.c | 3 ++ | 22 | target/arm/tlb_helper.c | 18 ++++++++++++++ |
27 | target/arm/kvm64.c | 3 ++ | 23 | target/arm/translate-a64.c | 15 ++++++++++++ |
28 | target/arm/machine.c | 7 ++++ | 24 | target/arm/translate.c | 22 ++++++++++++++++- |
29 | 6 files changed, 150 insertions(+) | 25 | 6 files changed, 87 insertions(+), 20 deletions(-) |
30 | 26 | ||
31 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 27 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
32 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/cpu.h | 29 | --- a/target/arm/helper.h |
34 | +++ b/target/arm/cpu.h | 30 | +++ b/target/arm/helper.h |
35 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 31 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, |
36 | /* KVM init features for this CPU */ | 32 | DEF_HELPER_2(exception_internal, void, env, i32) |
37 | uint32_t kvm_init_features[7]; | 33 | DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) |
38 | 34 | DEF_HELPER_2(exception_bkpt_insn, void, env, i32) | |
39 | + /* KVM CPU state */ | 35 | +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) |
40 | + | 36 | DEF_HELPER_1(setend, void, env) |
41 | + /* KVM virtual time adjustment */ | 37 | DEF_HELPER_2(wfi, void, env, i32) |
42 | + bool kvm_adjvtime; | 38 | DEF_HELPER_1(wfe, void, env) |
43 | + bool kvm_vtime_dirty; | 39 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
44 | + uint64_t kvm_vtime; | 40 | index XXXXXXX..XXXXXXX 100644 |
45 | + | 41 | --- a/target/arm/syndrome.h |
46 | /* Uniprocessor system with MP extensions */ | 42 | +++ b/target/arm/syndrome.h |
47 | bool mp_is_up; | 43 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void) |
48 | 44 | return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
49 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/kvm_arm.h | ||
52 | +++ b/target/arm/kvm_arm.h | ||
53 | @@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level); | ||
54 | */ | ||
55 | bool write_kvmstate_to_list(ARMCPU *cpu); | ||
56 | |||
57 | +/** | ||
58 | + * kvm_arm_cpu_pre_save: | ||
59 | + * @cpu: ARMCPU | ||
60 | + * | ||
61 | + * Called after write_kvmstate_to_list() from cpu_pre_save() to update | ||
62 | + * the cpreg list with KVM CPU state. | ||
63 | + */ | ||
64 | +void kvm_arm_cpu_pre_save(ARMCPU *cpu); | ||
65 | + | ||
66 | +/** | ||
67 | + * kvm_arm_cpu_post_load: | ||
68 | + * @cpu: ARMCPU | ||
69 | + * | ||
70 | + * Called from cpu_post_load() to update KVM CPU state from the cpreg list. | ||
71 | + */ | ||
72 | +void kvm_arm_cpu_post_load(ARMCPU *cpu); | ||
73 | + | ||
74 | /** | ||
75 | * kvm_arm_reset_vcpu: | ||
76 | * @cpu: ARMCPU | ||
77 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); | ||
78 | */ | ||
79 | int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); | ||
80 | |||
81 | +/** | ||
82 | + * kvm_arm_get_virtual_time: | ||
83 | + * @cs: CPUState | ||
84 | + * | ||
85 | + * Gets the VCPU's virtual counter and stores it in the KVM CPU state. | ||
86 | + */ | ||
87 | +void kvm_arm_get_virtual_time(CPUState *cs); | ||
88 | + | ||
89 | +/** | ||
90 | + * kvm_arm_put_virtual_time: | ||
91 | + * @cs: CPUState | ||
92 | + * | ||
93 | + * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. | ||
94 | + */ | ||
95 | +void kvm_arm_put_virtual_time(CPUState *cs); | ||
96 | + | ||
97 | +void kvm_arm_vm_state_change(void *opaque, int running, RunState state); | ||
98 | + | ||
99 | int kvm_arm_vgic_probe(void); | ||
100 | |||
101 | void kvm_arm_pmu_set_irq(CPUState *cs, int irq); | ||
102 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} | ||
103 | static inline void kvm_arm_pmu_init(CPUState *cs) {} | ||
104 | |||
105 | static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} | ||
106 | + | ||
107 | +static inline void kvm_arm_get_virtual_time(CPUState *cs) {} | ||
108 | +static inline void kvm_arm_put_virtual_time(CPUState *cs) {} | ||
109 | #endif | ||
110 | |||
111 | static inline const char *gic_class_name(void) | ||
112 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/kvm.c | ||
115 | +++ b/target/arm/kvm.c | ||
116 | @@ -XXX,XX +XXX,XX @@ static int compare_u64(const void *a, const void *b) | ||
117 | return 0; | ||
118 | } | 45 | } |
119 | 46 | ||
120 | +/* | 47 | +static inline uint32_t syn_pcalignment(void) |
121 | + * cpreg_values are sorted in ascending order by KVM register ID | ||
122 | + * (see kvm_arm_init_cpreg_list). This allows us to cheaply find | ||
123 | + * the storage for a KVM register by ID with a binary search. | ||
124 | + */ | ||
125 | +static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) | ||
126 | +{ | 48 | +{ |
127 | + uint64_t *res; | 49 | + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; |
128 | + | ||
129 | + res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, | ||
130 | + sizeof(uint64_t), compare_u64); | ||
131 | + assert(res); | ||
132 | + | ||
133 | + return &cpu->cpreg_values[res - cpu->cpreg_indexes]; | ||
134 | +} | 50 | +} |
135 | + | 51 | + |
136 | /* Initialize the ARMCPU cpreg list according to the kernel's | 52 | #endif /* TARGET_ARM_SYNDROME_H */ |
137 | * definition of what CPU registers it knows about (and throw away | 53 | diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c |
138 | * the previous TCG-created cpreg list). | 54 | index XXXXXXX..XXXXXXX 100644 |
139 | @@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) | 55 | --- a/linux-user/aarch64/cpu_loop.c |
140 | return ok; | 56 | +++ b/linux-user/aarch64/cpu_loop.c |
57 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
58 | break; | ||
59 | case EXCP_PREFETCH_ABORT: | ||
60 | case EXCP_DATA_ABORT: | ||
61 | - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ | ||
62 | ec = syn_get_ec(env->exception.syndrome); | ||
63 | - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); | ||
64 | - | ||
65 | - /* Both EC have the same format for FSC, or close enough. */ | ||
66 | - fsc = extract32(env->exception.syndrome, 0, 6); | ||
67 | - switch (fsc) { | ||
68 | - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ | ||
69 | - si_signo = TARGET_SIGSEGV; | ||
70 | - si_code = TARGET_SEGV_MAPERR; | ||
71 | + switch (ec) { | ||
72 | + case EC_DATAABORT: | ||
73 | + case EC_INSNABORT: | ||
74 | + /* Both EC have the same format for FSC, or close enough. */ | ||
75 | + fsc = extract32(env->exception.syndrome, 0, 6); | ||
76 | + switch (fsc) { | ||
77 | + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ | ||
78 | + si_signo = TARGET_SIGSEGV; | ||
79 | + si_code = TARGET_SEGV_MAPERR; | ||
80 | + break; | ||
81 | + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ | ||
82 | + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ | ||
83 | + si_signo = TARGET_SIGSEGV; | ||
84 | + si_code = TARGET_SEGV_ACCERR; | ||
85 | + break; | ||
86 | + case 0x11: /* Synchronous Tag Check Fault */ | ||
87 | + si_signo = TARGET_SIGSEGV; | ||
88 | + si_code = TARGET_SEGV_MTESERR; | ||
89 | + break; | ||
90 | + case 0x21: /* Alignment fault */ | ||
91 | + si_signo = TARGET_SIGBUS; | ||
92 | + si_code = TARGET_BUS_ADRALN; | ||
93 | + break; | ||
94 | + default: | ||
95 | + g_assert_not_reached(); | ||
96 | + } | ||
97 | break; | ||
98 | - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ | ||
99 | - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ | ||
100 | - si_signo = TARGET_SIGSEGV; | ||
101 | - si_code = TARGET_SEGV_ACCERR; | ||
102 | - break; | ||
103 | - case 0x11: /* Synchronous Tag Check Fault */ | ||
104 | - si_signo = TARGET_SIGSEGV; | ||
105 | - si_code = TARGET_SEGV_MTESERR; | ||
106 | - break; | ||
107 | - case 0x21: /* Alignment fault */ | ||
108 | + case EC_PCALIGNMENT: | ||
109 | si_signo = TARGET_SIGBUS; | ||
110 | si_code = TARGET_BUS_ADRALN; | ||
111 | break; | ||
112 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/tlb_helper.c | ||
115 | +++ b/target/arm/tlb_helper.c | ||
116 | @@ -XXX,XX +XXX,XX @@ | ||
117 | #include "cpu.h" | ||
118 | #include "internals.h" | ||
119 | #include "exec/exec-all.h" | ||
120 | +#include "exec/helper-proto.h" | ||
121 | |||
122 | static inline uint32_t merge_syn_data_abort(uint32_t template_syn, | ||
123 | unsigned int target_el, | ||
124 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | ||
125 | arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); | ||
141 | } | 126 | } |
142 | 127 | ||
143 | +void kvm_arm_cpu_pre_save(ARMCPU *cpu) | 128 | +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) |
144 | +{ | 129 | +{ |
145 | + /* KVM virtual time adjustment */ | 130 | + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; |
146 | + if (cpu->kvm_vtime_dirty) { | 131 | + int target_el = exception_target_el(env); |
147 | + *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; | 132 | + int mmu_idx = cpu_mmu_index(env, true); |
148 | + } | 133 | + uint32_t fsc; |
134 | + | ||
135 | + env->exception.vaddress = pc; | ||
136 | + | ||
137 | + /* | ||
138 | + * Note that the fsc is not applicable to this exception, | ||
139 | + * since any syndrome is pcalignment not insn_abort. | ||
140 | + */ | ||
141 | + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); | ||
142 | + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); | ||
149 | +} | 143 | +} |
150 | + | 144 | + |
151 | +void kvm_arm_cpu_post_load(ARMCPU *cpu) | 145 | #if !defined(CONFIG_USER_ONLY) |
152 | +{ | 146 | |
153 | + /* KVM virtual time adjustment */ | 147 | /* |
154 | + if (cpu->kvm_adjvtime) { | 148 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
155 | + cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); | 149 | index XXXXXXX..XXXXXXX 100644 |
156 | + cpu->kvm_vtime_dirty = true; | 150 | --- a/target/arm/translate-a64.c |
157 | + } | 151 | +++ b/target/arm/translate-a64.c |
158 | +} | 152 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
159 | + | 153 | uint64_t pc = s->base.pc_next; |
160 | void kvm_arm_reset_vcpu(ARMCPU *cpu) | 154 | uint32_t insn; |
161 | { | 155 | |
162 | int ret; | 156 | + /* Singlestep exceptions have the highest priority. */ |
163 | @@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) | 157 | if (s->ss_active && !s->pstate_ss) { |
164 | return 0; | 158 | /* Singlestep state is Active-pending. |
165 | } | 159 | * If we're in this state at the start of a TB then either |
166 | 160 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | |
167 | +void kvm_arm_get_virtual_time(CPUState *cs) | 161 | return; |
168 | +{ | 162 | } |
169 | + ARMCPU *cpu = ARM_CPU(cs); | 163 | |
170 | + struct kvm_one_reg reg = { | 164 | + if (pc & 3) { |
171 | + .id = KVM_REG_ARM_TIMER_CNT, | 165 | + /* |
172 | + .addr = (uintptr_t)&cpu->kvm_vtime, | 166 | + * PC alignment fault. This has priority over the instruction abort |
173 | + }; | 167 | + * that we would receive from a translation fault via arm_ldl_code. |
174 | + int ret; | 168 | + * This should only be possible after an indirect branch, at the |
175 | + | 169 | + * start of the TB. |
176 | + if (cpu->kvm_vtime_dirty) { | 170 | + */ |
171 | + assert(s->base.num_insns == 1); | ||
172 | + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); | ||
173 | + s->base.is_jmp = DISAS_NORETURN; | ||
174 | + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); | ||
177 | + return; | 175 | + return; |
178 | + } | 176 | + } |
179 | + | 177 | + |
180 | + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | 178 | s->pc_curr = pc; |
181 | + if (ret) { | 179 | insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); |
182 | + error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); | 180 | s->insn = insn; |
183 | + abort(); | 181 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
184 | + } | 182 | index XXXXXXX..XXXXXXX 100644 |
185 | + | 183 | --- a/target/arm/translate.c |
186 | + cpu->kvm_vtime_dirty = true; | 184 | +++ b/target/arm/translate.c |
187 | +} | 185 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
188 | + | 186 | uint32_t pc = dc->base.pc_next; |
189 | +void kvm_arm_put_virtual_time(CPUState *cs) | 187 | unsigned int insn; |
190 | +{ | 188 | |
191 | + ARMCPU *cpu = ARM_CPU(cs); | 189 | - if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
192 | + struct kvm_one_reg reg = { | 190 | + /* Singlestep exceptions have the highest priority. */ |
193 | + .id = KVM_REG_ARM_TIMER_CNT, | 191 | + if (arm_check_ss_active(dc)) { |
194 | + .addr = (uintptr_t)&cpu->kvm_vtime, | 192 | + dc->base.pc_next = pc + 4; |
195 | + }; | ||
196 | + int ret; | ||
197 | + | ||
198 | + if (!cpu->kvm_vtime_dirty) { | ||
199 | + return; | 193 | + return; |
200 | + } | 194 | + } |
201 | + | 195 | + |
202 | + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | 196 | + if (pc & 3) { |
203 | + if (ret) { | 197 | + /* |
204 | + error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); | 198 | + * PC alignment fault. This has priority over the instruction abort |
205 | + abort(); | 199 | + * that we would receive from a translation fault via arm_ldl_code |
200 | + * (or the execution of the kernelpage entrypoint). This should only | ||
201 | + * be possible after an indirect branch, at the start of the TB. | ||
202 | + */ | ||
203 | + assert(dc->base.num_insns == 1); | ||
204 | + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); | ||
205 | + dc->base.is_jmp = DISAS_NORETURN; | ||
206 | + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); | ||
207 | + return; | ||
206 | + } | 208 | + } |
207 | + | 209 | + |
208 | + cpu->kvm_vtime_dirty = false; | 210 | + if (arm_check_kernelpage(dc)) { |
209 | +} | 211 | dc->base.pc_next = pc + 4; |
210 | + | 212 | return; |
211 | int kvm_put_vcpu_events(ARMCPU *cpu) | ||
212 | { | ||
213 | CPUARMState *env = &cpu->env; | ||
214 | @@ -XXX,XX +XXX,XX @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) | ||
215 | return MEMTXATTRS_UNSPECIFIED; | ||
216 | } | ||
217 | |||
218 | +void kvm_arm_vm_state_change(void *opaque, int running, RunState state) | ||
219 | +{ | ||
220 | + CPUState *cs = opaque; | ||
221 | + ARMCPU *cpu = ARM_CPU(cs); | ||
222 | + | ||
223 | + if (running) { | ||
224 | + if (cpu->kvm_adjvtime) { | ||
225 | + kvm_arm_put_virtual_time(cs); | ||
226 | + } | ||
227 | + } else { | ||
228 | + if (cpu->kvm_adjvtime) { | ||
229 | + kvm_arm_get_virtual_time(cs); | ||
230 | + } | ||
231 | + } | ||
232 | +} | ||
233 | |||
234 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | ||
235 | { | ||
236 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | ||
237 | index XXXXXXX..XXXXXXX 100644 | ||
238 | --- a/target/arm/kvm32.c | ||
239 | +++ b/target/arm/kvm32.c | ||
240 | @@ -XXX,XX +XXX,XX @@ | ||
241 | #include "qemu-common.h" | ||
242 | #include "cpu.h" | ||
243 | #include "qemu/timer.h" | ||
244 | +#include "sysemu/runstate.h" | ||
245 | #include "sysemu/kvm.h" | ||
246 | #include "kvm_arm.h" | ||
247 | #include "internals.h" | ||
248 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
249 | return -EINVAL; | ||
250 | } | 213 | } |
251 | |||
252 | + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); | ||
253 | + | ||
254 | /* Determine init features for this CPU */ | ||
255 | memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); | ||
256 | if (cpu->start_powered_off) { | ||
257 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
258 | index XXXXXXX..XXXXXXX 100644 | ||
259 | --- a/target/arm/kvm64.c | ||
260 | +++ b/target/arm/kvm64.c | ||
261 | @@ -XXX,XX +XXX,XX @@ | ||
262 | #include "qemu/host-utils.h" | ||
263 | #include "qemu/main-loop.h" | ||
264 | #include "exec/gdbstub.h" | ||
265 | +#include "sysemu/runstate.h" | ||
266 | #include "sysemu/kvm.h" | ||
267 | #include "sysemu/kvm_int.h" | ||
268 | #include "kvm_arm.h" | ||
269 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
270 | return -EINVAL; | ||
271 | } | ||
272 | |||
273 | + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); | ||
274 | + | ||
275 | /* Determine init features for this CPU */ | ||
276 | memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); | ||
277 | if (cpu->start_powered_off) { | ||
278 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
279 | index XXXXXXX..XXXXXXX 100644 | ||
280 | --- a/target/arm/machine.c | ||
281 | +++ b/target/arm/machine.c | ||
282 | @@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque) | ||
283 | /* This should never fail */ | ||
284 | abort(); | ||
285 | } | ||
286 | + | ||
287 | + /* | ||
288 | + * kvm_arm_cpu_pre_save() must be called after | ||
289 | + * write_kvmstate_to_list() | ||
290 | + */ | ||
291 | + kvm_arm_cpu_pre_save(cpu); | ||
292 | } else { | ||
293 | if (!write_cpustate_to_list(cpu, false)) { | ||
294 | /* This should never fail. */ | ||
295 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | ||
296 | * we're using it. | ||
297 | */ | ||
298 | write_list_to_cpustate(cpu); | ||
299 | + kvm_arm_cpu_post_load(cpu); | ||
300 | } else { | ||
301 | if (!write_list_to_cpustate(cpu)) { | ||
302 | return -1; | ||
303 | -- | 214 | -- |
304 | 2.20.1 | 215 | 2.25.1 |
305 | 216 | ||
306 | 217 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Provide a temporary device_legacy_reset function doing what | 3 | Misaligned thumb PC is architecturally impossible. |
4 | device_reset does to prepare for the transition with Resettable | 4 | Assert is better than proceeding, in case we've missed |
5 | API. | 5 | something somewhere. |
6 | 6 | ||
7 | All occurrence of device_reset in the code tree are also replaced | 7 | Expand a comment about aligning the pc in gdbstub. |
8 | by device_legacy_reset. | 8 | Fail an incoming migrate if a thumb pc is misaligned. |
9 | 9 | ||
10 | The new resettable API has different prototype and semantics | ||
11 | (resetting child buses as well as the specified device). Subsequent | ||
12 | commits will make the changeover for each call site individually; once | ||
13 | that is complete device_legacy_reset() will be removed. | ||
14 | |||
15 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
18 | Acked-by: David Gibson <david@gibson.dropbear.id.au> | ||
19 | Acked-by: Cornelia Huck <cohuck@redhat.com> | ||
20 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
21 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
22 | Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | --- | 13 | --- |
25 | include/hw/qdev-core.h | 4 ++-- | 14 | target/arm/gdbstub.c | 9 +++++++-- |
26 | hw/audio/intel-hda.c | 2 +- | 15 | target/arm/machine.c | 10 ++++++++++ |
27 | hw/core/qdev.c | 6 +++--- | 16 | target/arm/translate.c | 3 +++ |
28 | hw/hyperv/hyperv.c | 2 +- | 17 | 3 files changed, 20 insertions(+), 2 deletions(-) |
29 | hw/i386/microvm.c | 2 +- | ||
30 | hw/i386/pc.c | 2 +- | ||
31 | hw/ide/microdrive.c | 8 ++++---- | ||
32 | hw/intc/spapr_xive.c | 2 +- | ||
33 | hw/ppc/pnv_psi.c | 4 ++-- | ||
34 | hw/ppc/spapr_pci.c | 2 +- | ||
35 | hw/ppc/spapr_vio.c | 2 +- | ||
36 | hw/s390x/s390-pci-inst.c | 2 +- | ||
37 | hw/scsi/vmw_pvscsi.c | 2 +- | ||
38 | hw/sd/omap_mmc.c | 2 +- | ||
39 | hw/sd/pl181.c | 2 +- | ||
40 | 15 files changed, 22 insertions(+), 22 deletions(-) | ||
41 | 18 | ||
42 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 19 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
43 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/include/hw/qdev-core.h | 21 | --- a/target/arm/gdbstub.c |
45 | +++ b/include/hw/qdev-core.h | 22 | +++ b/target/arm/gdbstub.c |
46 | @@ -XXX,XX +XXX,XX @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev); | 23 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
47 | void qdev_machine_init(void); | 24 | |
48 | 25 | tmp = ldl_p(mem_buf); | |
49 | /** | 26 | |
50 | - * @device_reset | 27 | - /* Mask out low bit of PC to workaround gdb bugs. This will probably |
51 | + * device_legacy_reset: | 28 | - cause problems if we ever implement the Jazelle DBX extensions. */ |
52 | * | 29 | + /* |
53 | * Reset a single device (by calling the reset method). | 30 | + * Mask out low bits of PC to workaround gdb bugs. |
54 | */ | 31 | + * This avoids an assert in thumb_tr_translate_insn, because it is |
55 | -void device_reset(DeviceState *dev); | 32 | + * architecturally impossible to misalign the pc. |
56 | +void device_legacy_reset(DeviceState *dev); | 33 | + * This will probably cause problems if we ever implement the |
57 | 34 | + * Jazelle DBX extensions. | |
58 | void device_class_set_props(DeviceClass *dc, Property *props); | 35 | + */ |
59 | 36 | if (n == 15) { | |
60 | diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c | 37 | tmp &= ~1; |
38 | } | ||
39 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
62 | --- a/hw/audio/intel-hda.c | 41 | --- a/target/arm/machine.c |
63 | +++ b/hw/audio/intel-hda.c | 42 | +++ b/target/arm/machine.c |
64 | @@ -XXX,XX +XXX,XX @@ static void intel_hda_reset(DeviceState *dev) | 43 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
65 | QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { | 44 | return -1; |
66 | DeviceState *qdev = kid->child; | ||
67 | cdev = HDA_CODEC_DEVICE(qdev); | ||
68 | - device_reset(DEVICE(cdev)); | ||
69 | + device_legacy_reset(DEVICE(cdev)); | ||
70 | d->state_sts |= (1 << cdev->cad); | ||
71 | } | ||
72 | intel_hda_update_irq(d); | ||
73 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/hw/core/qdev.c | ||
76 | +++ b/hw/core/qdev.c | ||
77 | @@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) | ||
78 | |||
79 | static int qdev_reset_one(DeviceState *dev, void *opaque) | ||
80 | { | ||
81 | - device_reset(dev); | ||
82 | + device_legacy_reset(dev); | ||
83 | |||
84 | return 0; | ||
85 | } | ||
86 | @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) | ||
87 | } | ||
88 | } | ||
89 | if (dev->hotplugged) { | ||
90 | - device_reset(dev); | ||
91 | + device_legacy_reset(dev); | ||
92 | } | ||
93 | dev->pending_deleted_event = false; | ||
94 | |||
95 | @@ -XXX,XX +XXX,XX @@ void device_class_set_parent_unrealize(DeviceClass *dc, | ||
96 | dc->unrealize = dev_unrealize; | ||
97 | } | ||
98 | |||
99 | -void device_reset(DeviceState *dev) | ||
100 | +void device_legacy_reset(DeviceState *dev) | ||
101 | { | ||
102 | DeviceClass *klass = DEVICE_GET_CLASS(dev); | ||
103 | |||
104 | diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/hw/hyperv/hyperv.c | ||
107 | +++ b/hw/hyperv/hyperv.c | ||
108 | @@ -XXX,XX +XXX,XX @@ void hyperv_synic_reset(CPUState *cs) | ||
109 | SynICState *synic = get_synic(cs); | ||
110 | |||
111 | if (synic) { | ||
112 | - device_reset(DEVICE(synic)); | ||
113 | + device_legacy_reset(DEVICE(synic)); | ||
114 | } | ||
115 | } | ||
116 | |||
117 | diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/hw/i386/microvm.c | ||
120 | +++ b/hw/i386/microvm.c | ||
121 | @@ -XXX,XX +XXX,XX @@ static void microvm_machine_reset(MachineState *machine) | ||
122 | cpu = X86_CPU(cs); | ||
123 | |||
124 | if (cpu->apic_state) { | ||
125 | - device_reset(cpu->apic_state); | ||
126 | + device_legacy_reset(cpu->apic_state); | ||
127 | } | 45 | } |
128 | } | 46 | } |
129 | } | 47 | + |
130 | diff --git a/hw/i386/pc.c b/hw/i386/pc.c | 48 | + /* |
49 | + * Misaligned thumb pc is architecturally impossible. | ||
50 | + * We have an assert in thumb_tr_translate_insn to verify this. | ||
51 | + * Fail an incoming migrate to avoid this assert. | ||
52 | + */ | ||
53 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
54 | + return -1; | ||
55 | + } | ||
56 | + | ||
57 | if (!kvm_enabled()) { | ||
58 | pmu_op_finish(&cpu->env); | ||
59 | } | ||
60 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
131 | index XXXXXXX..XXXXXXX 100644 | 61 | index XXXXXXX..XXXXXXX 100644 |
132 | --- a/hw/i386/pc.c | 62 | --- a/target/arm/translate.c |
133 | +++ b/hw/i386/pc.c | 63 | +++ b/target/arm/translate.c |
134 | @@ -XXX,XX +XXX,XX @@ static void pc_machine_reset(MachineState *machine) | 64 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
135 | cpu = X86_CPU(cs); | 65 | uint32_t insn; |
136 | 66 | bool is_16bit; | |
137 | if (cpu->apic_state) { | 67 | |
138 | - device_reset(cpu->apic_state); | 68 | + /* Misaligned thumb PC is architecturally impossible. */ |
139 | + device_legacy_reset(cpu->apic_state); | 69 | + assert((dc->base.pc_next & 1) == 0); |
140 | } | 70 | + |
141 | } | 71 | if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
142 | } | 72 | dc->base.pc_next = pc + 2; |
143 | diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c | 73 | return; |
144 | index XXXXXXX..XXXXXXX 100644 | ||
145 | --- a/hw/ide/microdrive.c | ||
146 | +++ b/hw/ide/microdrive.c | ||
147 | @@ -XXX,XX +XXX,XX @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value) | ||
148 | case 0x00: /* Configuration Option Register */ | ||
149 | s->opt = value & 0xcf; | ||
150 | if (value & OPT_SRESET) { | ||
151 | - device_reset(DEVICE(s)); | ||
152 | + device_legacy_reset(DEVICE(s)); | ||
153 | } | ||
154 | md_interrupt_update(s); | ||
155 | break; | ||
156 | @@ -XXX,XX +XXX,XX @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value) | ||
157 | case 0xe: /* Device Control */ | ||
158 | s->ctrl = value; | ||
159 | if (value & CTRL_SRST) { | ||
160 | - device_reset(DEVICE(s)); | ||
161 | + device_legacy_reset(DEVICE(s)); | ||
162 | } | ||
163 | md_interrupt_update(s); | ||
164 | break; | ||
165 | @@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_attach(PCMCIACardState *card) | ||
166 | md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8); | ||
167 | md->io_base = 0x0; | ||
168 | |||
169 | - device_reset(DEVICE(md)); | ||
170 | + device_legacy_reset(DEVICE(md)); | ||
171 | md_interrupt_update(md); | ||
172 | |||
173 | return 0; | ||
174 | @@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_detach(PCMCIACardState *card) | ||
175 | { | ||
176 | MicroDriveState *md = MICRODRIVE(card); | ||
177 | |||
178 | - device_reset(DEVICE(md)); | ||
179 | + device_legacy_reset(DEVICE(md)); | ||
180 | return 0; | ||
181 | } | ||
182 | |||
183 | diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c | ||
184 | index XXXXXXX..XXXXXXX 100644 | ||
185 | --- a/hw/intc/spapr_xive.c | ||
186 | +++ b/hw/intc/spapr_xive.c | ||
187 | @@ -XXX,XX +XXX,XX @@ static target_ulong h_int_reset(PowerPCCPU *cpu, | ||
188 | return H_PARAMETER; | ||
189 | } | ||
190 | |||
191 | - device_reset(DEVICE(xive)); | ||
192 | + device_legacy_reset(DEVICE(xive)); | ||
193 | |||
194 | if (kvm_irqchip_in_kernel()) { | ||
195 | Error *local_err = NULL; | ||
196 | diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c | ||
197 | index XXXXXXX..XXXXXXX 100644 | ||
198 | --- a/hw/ppc/pnv_psi.c | ||
199 | +++ b/hw/ppc/pnv_psi.c | ||
200 | @@ -XXX,XX +XXX,XX @@ static void pnv_psi_reset(DeviceState *dev) | ||
201 | |||
202 | static void pnv_psi_reset_handler(void *dev) | ||
203 | { | ||
204 | - device_reset(DEVICE(dev)); | ||
205 | + device_legacy_reset(DEVICE(dev)); | ||
206 | } | ||
207 | |||
208 | static void pnv_psi_realize(DeviceState *dev, Error **errp) | ||
209 | @@ -XXX,XX +XXX,XX @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, | ||
210 | break; | ||
211 | case PSIHB9_INTERRUPT_CONTROL: | ||
212 | if (val & PSIHB9_IRQ_RESET) { | ||
213 | - device_reset(DEVICE(&psi9->source)); | ||
214 | + device_legacy_reset(DEVICE(&psi9->source)); | ||
215 | } | ||
216 | psi->regs[reg] = val; | ||
217 | break; | ||
218 | diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c | ||
219 | index XXXXXXX..XXXXXXX 100644 | ||
220 | --- a/hw/ppc/spapr_pci.c | ||
221 | +++ b/hw/ppc/spapr_pci.c | ||
222 | @@ -XXX,XX +XXX,XX @@ static int spapr_phb_children_reset(Object *child, void *opaque) | ||
223 | DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); | ||
224 | |||
225 | if (dev) { | ||
226 | - device_reset(dev); | ||
227 | + device_legacy_reset(dev); | ||
228 | } | ||
229 | |||
230 | return 0; | ||
231 | diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c | ||
232 | index XXXXXXX..XXXXXXX 100644 | ||
233 | --- a/hw/ppc/spapr_vio.c | ||
234 | +++ b/hw/ppc/spapr_vio.c | ||
235 | @@ -XXX,XX +XXX,XX @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq) | ||
236 | static void spapr_vio_quiesce_one(SpaprVioDevice *dev) | ||
237 | { | ||
238 | if (dev->tcet) { | ||
239 | - device_reset(DEVICE(dev->tcet)); | ||
240 | + device_legacy_reset(DEVICE(dev->tcet)); | ||
241 | } | ||
242 | free_crq(dev); | ||
243 | } | ||
244 | diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c | ||
245 | index XXXXXXX..XXXXXXX 100644 | ||
246 | --- a/hw/s390x/s390-pci-inst.c | ||
247 | +++ b/hw/s390x/s390-pci-inst.c | ||
248 | @@ -XXX,XX +XXX,XX @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) | ||
249 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); | ||
250 | goto out; | ||
251 | } | ||
252 | - device_reset(DEVICE(pbdev)); | ||
253 | + device_legacy_reset(DEVICE(pbdev)); | ||
254 | pbdev->fh &= ~FH_MASK_ENABLE; | ||
255 | pbdev->state = ZPCI_FS_DISABLED; | ||
256 | stl_p(&ressetpci->fh, pbdev->fh); | ||
257 | diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c | ||
258 | index XXXXXXX..XXXXXXX 100644 | ||
259 | --- a/hw/scsi/vmw_pvscsi.c | ||
260 | +++ b/hw/scsi/vmw_pvscsi.c | ||
261 | @@ -XXX,XX +XXX,XX @@ pvscsi_on_cmd_reset_device(PVSCSIState *s) | ||
262 | |||
263 | if (sdev != NULL) { | ||
264 | s->resetting++; | ||
265 | - device_reset(&sdev->qdev); | ||
266 | + device_legacy_reset(&sdev->qdev); | ||
267 | s->resetting--; | ||
268 | return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | ||
269 | } | ||
270 | diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c | ||
271 | index XXXXXXX..XXXXXXX 100644 | ||
272 | --- a/hw/sd/omap_mmc.c | ||
273 | +++ b/hw/sd/omap_mmc.c | ||
274 | @@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host) | ||
275 | * into any bus, and we must reset it manually. When omap_mmc is | ||
276 | * QOMified this must move into the QOM reset function. | ||
277 | */ | ||
278 | - device_reset(DEVICE(host->card)); | ||
279 | + device_legacy_reset(DEVICE(host->card)); | ||
280 | } | ||
281 | |||
282 | static uint64_t omap_mmc_read(void *opaque, hwaddr offset, | ||
283 | diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c | ||
284 | index XXXXXXX..XXXXXXX 100644 | ||
285 | --- a/hw/sd/pl181.c | ||
286 | +++ b/hw/sd/pl181.c | ||
287 | @@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d) | ||
288 | /* Since we're still using the legacy SD API the card is not plugged | ||
289 | * into any bus, and we must reset it manually. | ||
290 | */ | ||
291 | - device_reset(DEVICE(s->card)); | ||
292 | + device_legacy_reset(DEVICE(s->card)); | ||
293 | } | ||
294 | |||
295 | static void pl181_init(Object *obj) | ||
296 | -- | 74 | -- |
297 | 2.20.1 | 75 | 2.25.1 |
298 | 76 | ||
299 | 77 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add a function resettable_change_parent() to do the required | 3 | Both single-step and pc alignment faults have priority over |
4 | plumbing when changing the parent a of Resettable object. | 4 | breakpoint exceptions. |
5 | 5 | ||
6 | We need to make sure that the reset state of the object remains | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | coherent with the reset state of the new parent. | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | |||
9 | We make the 2 following hypothesis: | ||
10 | + when an object is put in a parent under reset, the object goes in | ||
11 | reset. | ||
12 | + when an object is removed from a parent under reset, the object | ||
13 | leaves reset. | ||
14 | |||
15 | The added function avoids any glitch if both old and new parent are | ||
16 | already in reset. | ||
17 | |||
18 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
21 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
22 | Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | --- | 9 | --- |
25 | include/hw/resettable.h | 16 +++++++++++ | 10 | target/arm/debug_helper.c | 23 +++++++++++++++++++++++ |
26 | hw/core/resettable.c | 62 +++++++++++++++++++++++++++++++++++++++-- | 11 | 1 file changed, 23 insertions(+) |
27 | hw/core/trace-events | 1 + | ||
28 | 3 files changed, 77 insertions(+), 2 deletions(-) | ||
29 | 12 | ||
30 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | 13 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
31 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/include/hw/resettable.h | 15 | --- a/target/arm/debug_helper.c |
33 | +++ b/include/hw/resettable.h | 16 | +++ b/target/arm/debug_helper.c |
34 | @@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type); | 17 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs) |
35 | */ | ||
36 | bool resettable_is_in_reset(Object *obj); | ||
37 | |||
38 | +/** | ||
39 | + * resettable_change_parent: | ||
40 | + * Indicate that the parent of Ressettable @obj is changing from @oldp to @newp. | ||
41 | + * All 3 objects must implement resettable interface. @oldp or @newp may be | ||
42 | + * NULL. | ||
43 | + * | ||
44 | + * This function will adapt the reset state of @obj so that it is coherent | ||
45 | + * with the reset state of @newp. It may trigger @resettable_assert_reset() | ||
46 | + * or @resettable_release_reset(). It will do such things only if the reset | ||
47 | + * state of @newp and @oldp are different. | ||
48 | + * | ||
49 | + * When using this function during reset, it must only be called during | ||
50 | + * a hold phase method. Calling this during enter or exit phase is an error. | ||
51 | + */ | ||
52 | +void resettable_change_parent(Object *obj, Object *newp, Object *oldp); | ||
53 | + | ||
54 | /** | ||
55 | * resettable_class_set_parent_phases: | ||
56 | * | ||
57 | diff --git a/hw/core/resettable.c b/hw/core/resettable.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/hw/core/resettable.c | ||
60 | +++ b/hw/core/resettable.c | ||
61 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); | ||
62 | * enter_phase_in_progress: | ||
63 | * True if we are currently in reset enter phase. | ||
64 | * | ||
65 | - * Note: This flag is only used to guarantee (using asserts) that the reset | ||
66 | - * API is used correctly. We can use a global variable because we rely on the | ||
67 | + * exit_phase_in_progress: | ||
68 | + * count the number of exit phase we are in. | ||
69 | + * | ||
70 | + * Note: These flags are only used to guarantee (using asserts) that the reset | ||
71 | + * API is used correctly. We can use global variables because we rely on the | ||
72 | * iothread mutex to ensure only one reset operation is in a progress at a | ||
73 | * given time. | ||
74 | */ | ||
75 | static bool enter_phase_in_progress; | ||
76 | +static unsigned exit_phase_in_progress; | ||
77 | |||
78 | void resettable_reset(Object *obj, ResetType type) | ||
79 | { | 18 | { |
80 | @@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type) | 19 | ARMCPU *cpu = ARM_CPU(cs); |
81 | trace_resettable_reset_release_begin(obj, type); | 20 | CPUARMState *env = &cpu->env; |
82 | assert(!enter_phase_in_progress); | 21 | + target_ulong pc; |
83 | 22 | int n; | |
84 | + exit_phase_in_progress += 1; | 23 | |
85 | resettable_phase_exit(obj, NULL, type); | 24 | /* |
86 | + exit_phase_in_progress -= 1; | 25 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs) |
87 | 26 | return false; | |
88 | trace_resettable_reset_release_end(obj); | 27 | } |
89 | } | 28 | |
90 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) | 29 | + /* |
91 | trace_resettable_phase_exit_end(obj, obj_typename, s->count); | 30 | + * Single-step exceptions have priority over breakpoint exceptions. |
92 | } | 31 | + * If single-step state is active-pending, suppress the bp. |
93 | 32 | + */ | |
94 | +/* | 33 | + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { |
95 | + * resettable_get_count: | 34 | + return false; |
96 | + * Get the count of the Resettable object @obj. Return 0 if @obj is NULL. | ||
97 | + */ | ||
98 | +static unsigned resettable_get_count(Object *obj) | ||
99 | +{ | ||
100 | + if (obj) { | ||
101 | + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | ||
102 | + return rc->get_state(obj)->count; | ||
103 | + } | 35 | + } |
104 | + return 0; | ||
105 | +} | ||
106 | + | ||
107 | +void resettable_change_parent(Object *obj, Object *newp, Object *oldp) | ||
108 | +{ | ||
109 | + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | ||
110 | + ResettableState *s = rc->get_state(obj); | ||
111 | + unsigned newp_count = resettable_get_count(newp); | ||
112 | + unsigned oldp_count = resettable_get_count(oldp); | ||
113 | + | 36 | + |
114 | + /* | 37 | + /* |
115 | + * Ensure we do not change parent when in enter or exit phase. | 38 | + * PC alignment faults have priority over breakpoint exceptions. |
116 | + * During these phases, the reset subtree being updated is partly in reset | ||
117 | + * and partly not in reset (it depends on the actual position in | ||
118 | + * resettable_child_foreach()s). We are not able to tell in which part is a | ||
119 | + * leaving or arriving device. Thus we cannot set the reset count of the | ||
120 | + * moving device to the proper value. | ||
121 | + */ | 39 | + */ |
122 | + assert(!enter_phase_in_progress && !exit_phase_in_progress); | 40 | + pc = is_a64(env) ? env->pc : env->regs[15]; |
123 | + trace_resettable_change_parent(obj, oldp, oldp_count, newp, newp_count); | 41 | + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { |
42 | + return false; | ||
43 | + } | ||
124 | + | 44 | + |
125 | + /* | 45 | + /* |
126 | + * At most one of the two 'for' loops will be executed below | 46 | + * Instruction aborts have priority over breakpoint exceptions. |
127 | + * in order to cope with the difference between the two counts. | 47 | + * TODO: We would need to look up the page for PC and verify that |
48 | + * it is present and executable. | ||
128 | + */ | 49 | + */ |
129 | + /* if newp is more reset than oldp */ | ||
130 | + for (unsigned i = oldp_count; i < newp_count; i++) { | ||
131 | + resettable_assert_reset(obj, RESET_TYPE_COLD); | ||
132 | + } | ||
133 | + /* | ||
134 | + * if obj is leaving a bus under reset, we need to ensure | ||
135 | + * hold phase is not pending. | ||
136 | + */ | ||
137 | + if (oldp_count && s->hold_phase_pending) { | ||
138 | + resettable_phase_hold(obj, NULL, RESET_TYPE_COLD); | ||
139 | + } | ||
140 | + /* if oldp is more reset than newp */ | ||
141 | + for (unsigned i = newp_count; i < oldp_count; i++) { | ||
142 | + resettable_release_reset(obj, RESET_TYPE_COLD); | ||
143 | + } | ||
144 | +} | ||
145 | + | 50 | + |
146 | void resettable_class_set_parent_phases(ResettableClass *rc, | 51 | for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { |
147 | ResettableEnterPhase enter, | 52 | if (bp_wp_matches(cpu, n, false)) { |
148 | ResettableHoldPhase hold, | 53 | return true; |
149 | diff --git a/hw/core/trace-events b/hw/core/trace-events | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/hw/core/trace-events | ||
152 | +++ b/hw/core/trace-events | ||
153 | @@ -XXX,XX +XXX,XX @@ resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d" | ||
154 | resettable_reset_assert_end(void *obj) "obj=%p" | ||
155 | resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d" | ||
156 | resettable_reset_release_end(void *obj) "obj=%p" | ||
157 | +resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc) "obj=%p from=%p(%d) to=%p(%d)" | ||
158 | resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" | ||
159 | resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d" | ||
160 | resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" | ||
161 | -- | 54 | -- |
162 | 2.20.1 | 55 | 2.25.1 |
163 | 56 | ||
164 | 57 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This commit defines an interface allowing multi-phase reset. This aims | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | to solve a problem of the actual single-phase reset (built in | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | DeviceClass and BusClass): reset behavior is dependent on the order | ||
6 | in which reset handlers are called. In particular doing external | ||
7 | side-effect (like setting an qemu_irq) is problematic because receiving | ||
8 | object may not be reset yet. | ||
9 | |||
10 | The Resettable interface divides the reset in 3 well defined phases. | ||
11 | To reset an object tree, all 1st phases are executed then all 2nd then | ||
12 | all 3rd. See the comments in include/hw/resettable.h for a more complete | ||
13 | description. The interface defines 3 phases to let the future | ||
14 | possibility of holding an object into reset for some time. | ||
15 | |||
16 | The qdev/qbus reset in DeviceClass and BusClass will be modified in | ||
17 | following commits to use this interface. A mechanism is provided | ||
18 | to allow executing a transitional reset handler in place of the 2nd | ||
19 | phase which is executed in children-then-parent order inside a tree. | ||
20 | This will allow to transition devices and buses smoothly while | ||
21 | keeping the exact current qdev/qbus reset behavior for now. | ||
22 | |||
23 | Documentation will be added in a following commit. | ||
24 | |||
25 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
27 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
28 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
29 | Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 6 | --- |
32 | hw/core/Makefile.objs | 1 + | 7 | tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ |
33 | include/hw/resettable.h | 211 +++++++++++++++++++++++++++++++++++ | 8 | tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ |
34 | hw/core/resettable.c | 238 ++++++++++++++++++++++++++++++++++++++++ | 9 | tests/tcg/aarch64/Makefile.target | 4 +-- |
35 | hw/core/trace-events | 17 +++ | 10 | tests/tcg/arm/Makefile.target | 4 +++ |
36 | 4 files changed, 467 insertions(+) | 11 | 4 files changed, 89 insertions(+), 2 deletions(-) |
37 | create mode 100644 include/hw/resettable.h | 12 | create mode 100644 tests/tcg/aarch64/pcalign-a64.c |
38 | create mode 100644 hw/core/resettable.c | 13 | create mode 100644 tests/tcg/arm/pcalign-a32.c |
39 | 14 | ||
40 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | 15 | diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c |
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/core/Makefile.objs | ||
43 | +++ b/hw/core/Makefile.objs | ||
44 | @@ -XXX,XX +XXX,XX @@ | ||
45 | common-obj-y += qdev.o qdev-properties.o | ||
46 | common-obj-y += bus.o | ||
47 | common-obj-y += cpu.o | ||
48 | +common-obj-y += resettable.o | ||
49 | common-obj-y += hotplug.o | ||
50 | common-obj-y += vmstate-if.o | ||
51 | # irq.o needed for qdev GPIO handling: | ||
52 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | ||
53 | new file mode 100644 | 16 | new file mode 100644 |
54 | index XXXXXXX..XXXXXXX | 17 | index XXXXXXX..XXXXXXX |
55 | --- /dev/null | 18 | --- /dev/null |
56 | +++ b/include/hw/resettable.h | 19 | +++ b/tests/tcg/aarch64/pcalign-a64.c |
57 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
58 | +/* | 21 | +/* Test PC misalignment exception */ |
59 | + * Resettable interface header. | ||
60 | + * | ||
61 | + * Copyright (c) 2019 GreenSocs SAS | ||
62 | + * | ||
63 | + * Authors: | ||
64 | + * Damien Hedde | ||
65 | + * | ||
66 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
67 | + * See the COPYING file in the top-level directory. | ||
68 | + */ | ||
69 | + | 22 | + |
70 | +#ifndef HW_RESETTABLE_H | 23 | +#include <assert.h> |
71 | +#define HW_RESETTABLE_H | 24 | +#include <signal.h> |
25 | +#include <stdlib.h> | ||
26 | +#include <stdio.h> | ||
72 | + | 27 | + |
73 | +#include "qom/object.h" | 28 | +static void *expected; |
74 | + | 29 | + |
75 | +#define TYPE_RESETTABLE_INTERFACE "resettable" | 30 | +static void sigbus(int sig, siginfo_t *info, void *vuc) |
31 | +{ | ||
32 | + assert(info->si_code == BUS_ADRALN); | ||
33 | + assert(info->si_addr == expected); | ||
34 | + exit(EXIT_SUCCESS); | ||
35 | +} | ||
76 | + | 36 | + |
77 | +#define RESETTABLE_CLASS(class) \ | 37 | +int main() |
78 | + OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE_INTERFACE) | 38 | +{ |
39 | + void *tmp; | ||
79 | + | 40 | + |
80 | +#define RESETTABLE_GET_CLASS(obj) \ | 41 | + struct sigaction sa = { |
81 | + OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE) | 42 | + .sa_sigaction = sigbus, |
43 | + .sa_flags = SA_SIGINFO | ||
44 | + }; | ||
82 | + | 45 | + |
83 | +typedef struct ResettableState ResettableState; | 46 | + if (sigaction(SIGBUS, &sa, NULL) < 0) { |
47 | + perror("sigaction"); | ||
48 | + return EXIT_FAILURE; | ||
49 | + } | ||
84 | + | 50 | + |
85 | +/** | 51 | + asm volatile("adr %0, 1f + 1\n\t" |
86 | + * ResetType: | 52 | + "str %0, %1\n\t" |
87 | + * Types of reset. | 53 | + "br %0\n" |
88 | + * | 54 | + "1:" |
89 | + * + Cold: reset resulting from a power cycle of the object. | 55 | + : "=&r"(tmp), "=m"(expected)); |
90 | + * | 56 | + abort(); |
91 | + * TODO: Support has to be added to handle more types. In particular, | 57 | +} |
92 | + * ResettableState structure needs to be expanded. | 58 | diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c |
93 | + */ | ||
94 | +typedef enum ResetType { | ||
95 | + RESET_TYPE_COLD, | ||
96 | +} ResetType; | ||
97 | + | ||
98 | +/* | ||
99 | + * ResettableClass: | ||
100 | + * Interface for resettable objects. | ||
101 | + * | ||
102 | + * See docs/devel/reset.rst for more detailed information about how QEMU models | ||
103 | + * reset. This whole API must only be used when holding the iothread mutex. | ||
104 | + * | ||
105 | + * All objects which can be reset must implement this interface; | ||
106 | + * it is usually provided by a base class such as DeviceClass or BusClass. | ||
107 | + * Every Resettable object must maintain some state tracking the | ||
108 | + * progress of a reset operation by providing a ResettableState structure. | ||
109 | + * The functions defined in this module take care of updating the | ||
110 | + * state of the reset. | ||
111 | + * The base class implementation of the interface provides this | ||
112 | + * state and implements the associated method: get_state. | ||
113 | + * | ||
114 | + * Concrete object implementations (typically specific devices | ||
115 | + * such as a UART model) should provide the functions | ||
116 | + * for the phases.enter, phases.hold and phases.exit methods, which | ||
117 | + * they can set in their class init function, either directly or | ||
118 | + * by calling resettable_class_set_parent_phases(). | ||
119 | + * The phase methods are guaranteed to only only ever be called once | ||
120 | + * for any reset event, in the order 'enter', 'hold', 'exit'. | ||
121 | + * An object will always move quickly from 'enter' to 'hold' | ||
122 | + * but might remain in 'hold' for an arbitrary period of time | ||
123 | + * before eventually reset is deasserted and the 'exit' phase is called. | ||
124 | + * Object implementations should be prepared for functions handling | ||
125 | + * inbound connections from other devices (such as qemu_irq handler | ||
126 | + * functions) to be called at any point during reset after their | ||
127 | + * 'enter' method has been called. | ||
128 | + * | ||
129 | + * Users of a resettable object should not call these methods | ||
130 | + * directly, but instead use the function resettable_reset(). | ||
131 | + * | ||
132 | + * @phases.enter: This phase is called when the object enters reset. It | ||
133 | + * should reset local state of the object, but it must not do anything that | ||
134 | + * has a side-effect on other objects, such as raising or lowering a qemu_irq | ||
135 | + * line or reading or writing guest memory. It takes the reset's type as | ||
136 | + * argument. | ||
137 | + * | ||
138 | + * @phases.hold: This phase is called for entry into reset, once every object | ||
139 | + * in the system which is being reset has had its @phases.enter method called. | ||
140 | + * At this point devices can do actions that affect other objects. | ||
141 | + * | ||
142 | + * @phases.exit: This phase is called when the object leaves the reset state. | ||
143 | + * Actions affecting other objects are permitted. | ||
144 | + * | ||
145 | + * @get_state: Mandatory method which must return a pointer to a | ||
146 | + * ResettableState. | ||
147 | + * | ||
148 | + * @get_transitional_function: transitional method to handle Resettable objects | ||
149 | + * not yet fully moved to this interface. It will be removed as soon as it is | ||
150 | + * not needed anymore. This method is optional and may return a pointer to a | ||
151 | + * function to be used instead of the phases. If the method exists and returns | ||
152 | + * a non-NULL function pointer then that function is executed as a replacement | ||
153 | + * of the 'hold' phase method taking the object as argument. The two other phase | ||
154 | + * methods are not executed. | ||
155 | + * | ||
156 | + * @child_foreach: Executes a given callback on every Resettable child. Child | ||
157 | + * in this context means a child in the qbus tree, so the children of a qbus | ||
158 | + * are the devices on it, and the children of a device are all the buses it | ||
159 | + * owns. This is not the same as the QOM object hierarchy. The function takes | ||
160 | + * additional opaque and ResetType arguments which must be passed unmodified to | ||
161 | + * the callback. | ||
162 | + */ | ||
163 | +typedef void (*ResettableEnterPhase)(Object *obj, ResetType type); | ||
164 | +typedef void (*ResettableHoldPhase)(Object *obj); | ||
165 | +typedef void (*ResettableExitPhase)(Object *obj); | ||
166 | +typedef ResettableState * (*ResettableGetState)(Object *obj); | ||
167 | +typedef void (*ResettableTrFunction)(Object *obj); | ||
168 | +typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj); | ||
169 | +typedef void (*ResettableChildCallback)(Object *, void *opaque, | ||
170 | + ResetType type); | ||
171 | +typedef void (*ResettableChildForeach)(Object *obj, | ||
172 | + ResettableChildCallback cb, | ||
173 | + void *opaque, ResetType type); | ||
174 | +typedef struct ResettablePhases { | ||
175 | + ResettableEnterPhase enter; | ||
176 | + ResettableHoldPhase hold; | ||
177 | + ResettableExitPhase exit; | ||
178 | +} ResettablePhases; | ||
179 | +typedef struct ResettableClass { | ||
180 | + InterfaceClass parent_class; | ||
181 | + | ||
182 | + /* Phase methods */ | ||
183 | + ResettablePhases phases; | ||
184 | + | ||
185 | + /* State access method */ | ||
186 | + ResettableGetState get_state; | ||
187 | + | ||
188 | + /* Transitional method for legacy reset compatibility */ | ||
189 | + ResettableGetTrFunction get_transitional_function; | ||
190 | + | ||
191 | + /* Hierarchy handling method */ | ||
192 | + ResettableChildForeach child_foreach; | ||
193 | +} ResettableClass; | ||
194 | + | ||
195 | +/** | ||
196 | + * ResettableState: | ||
197 | + * Structure holding reset related state. The fields should not be accessed | ||
198 | + * directly; the definition is here to allow further inclusion into other | ||
199 | + * objects. | ||
200 | + * | ||
201 | + * @count: Number of reset level the object is into. It is incremented when | ||
202 | + * the reset operation starts and decremented when it finishes. | ||
203 | + * @hold_phase_pending: flag which indicates that we need to invoke the 'hold' | ||
204 | + * phase handler for this object. | ||
205 | + * @exit_phase_in_progress: true if we are currently in the exit phase | ||
206 | + */ | ||
207 | +struct ResettableState { | ||
208 | + unsigned count; | ||
209 | + bool hold_phase_pending; | ||
210 | + bool exit_phase_in_progress; | ||
211 | +}; | ||
212 | + | ||
213 | +/** | ||
214 | + * resettable_reset: | ||
215 | + * Trigger a reset on an object @obj of type @type. @obj must implement | ||
216 | + * Resettable interface. | ||
217 | + * | ||
218 | + * Calling this function is equivalent to calling @resettable_assert_reset() | ||
219 | + * then @resettable_release_reset(). | ||
220 | + */ | ||
221 | +void resettable_reset(Object *obj, ResetType type); | ||
222 | + | ||
223 | +/** | ||
224 | + * resettable_assert_reset: | ||
225 | + * Put an object @obj into reset. @obj must implement Resettable interface. | ||
226 | + * | ||
227 | + * @resettable_release_reset() must eventually be called after this call. | ||
228 | + * There must be one call to @resettable_release_reset() per call of | ||
229 | + * @resettable_assert_reset(), with the same type argument. | ||
230 | + * | ||
231 | + * NOTE: Until support for migration is added, the @resettable_release_reset() | ||
232 | + * must not be delayed. It must occur just after @resettable_assert_reset() so | ||
233 | + * that migration cannot be triggered in between. Prefer using | ||
234 | + * @resettable_reset() for now. | ||
235 | + */ | ||
236 | +void resettable_assert_reset(Object *obj, ResetType type); | ||
237 | + | ||
238 | +/** | ||
239 | + * resettable_release_reset: | ||
240 | + * Release the object @obj from reset. @obj must implement Resettable interface. | ||
241 | + * | ||
242 | + * See @resettable_assert_reset() description for details. | ||
243 | + */ | ||
244 | +void resettable_release_reset(Object *obj, ResetType type); | ||
245 | + | ||
246 | +/** | ||
247 | + * resettable_is_in_reset: | ||
248 | + * Return true if @obj is under reset. | ||
249 | + * | ||
250 | + * @obj must implement Resettable interface. | ||
251 | + */ | ||
252 | +bool resettable_is_in_reset(Object *obj); | ||
253 | + | ||
254 | +/** | ||
255 | + * resettable_class_set_parent_phases: | ||
256 | + * | ||
257 | + * Save @rc current reset phases into @parent_phases and override @rc phases | ||
258 | + * by the given new methods (@enter, @hold and @exit). | ||
259 | + * Each phase is overridden only if the new one is not NULL allowing to | ||
260 | + * override a subset of phases. | ||
261 | + */ | ||
262 | +void resettable_class_set_parent_phases(ResettableClass *rc, | ||
263 | + ResettableEnterPhase enter, | ||
264 | + ResettableHoldPhase hold, | ||
265 | + ResettableExitPhase exit, | ||
266 | + ResettablePhases *parent_phases); | ||
267 | + | ||
268 | +#endif | ||
269 | diff --git a/hw/core/resettable.c b/hw/core/resettable.c | ||
270 | new file mode 100644 | 59 | new file mode 100644 |
271 | index XXXXXXX..XXXXXXX | 60 | index XXXXXXX..XXXXXXX |
272 | --- /dev/null | 61 | --- /dev/null |
273 | +++ b/hw/core/resettable.c | 62 | +++ b/tests/tcg/arm/pcalign-a32.c |
274 | @@ -XXX,XX +XXX,XX @@ | 63 | @@ -XXX,XX +XXX,XX @@ |
275 | +/* | 64 | +/* Test PC misalignment exception */ |
276 | + * Resettable interface. | ||
277 | + * | ||
278 | + * Copyright (c) 2019 GreenSocs SAS | ||
279 | + * | ||
280 | + * Authors: | ||
281 | + * Damien Hedde | ||
282 | + * | ||
283 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
284 | + * See the COPYING file in the top-level directory. | ||
285 | + */ | ||
286 | + | 65 | + |
287 | +#include "qemu/osdep.h" | 66 | +#ifdef __thumb__ |
288 | +#include "qemu/module.h" | 67 | +#error "This test must be compiled for ARM" |
289 | +#include "hw/resettable.h" | 68 | +#endif |
290 | +#include "trace.h" | ||
291 | + | 69 | + |
292 | +/** | 70 | +#include <assert.h> |
293 | + * resettable_phase_enter/hold/exit: | 71 | +#include <signal.h> |
294 | + * Function executing a phase recursively in a resettable object and its | 72 | +#include <stdlib.h> |
295 | + * children. | 73 | +#include <stdio.h> |
296 | + */ | ||
297 | +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type); | ||
298 | +static void resettable_phase_hold(Object *obj, void *opaque, ResetType type); | ||
299 | +static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); | ||
300 | + | 74 | + |
301 | +/** | 75 | +static void *expected; |
302 | + * enter_phase_in_progress: | ||
303 | + * True if we are currently in reset enter phase. | ||
304 | + * | ||
305 | + * Note: This flag is only used to guarantee (using asserts) that the reset | ||
306 | + * API is used correctly. We can use a global variable because we rely on the | ||
307 | + * iothread mutex to ensure only one reset operation is in a progress at a | ||
308 | + * given time. | ||
309 | + */ | ||
310 | +static bool enter_phase_in_progress; | ||
311 | + | 76 | + |
312 | +void resettable_reset(Object *obj, ResetType type) | 77 | +static void sigbus(int sig, siginfo_t *info, void *vuc) |
313 | +{ | 78 | +{ |
314 | + trace_resettable_reset(obj, type); | 79 | + assert(info->si_code == BUS_ADRALN); |
315 | + resettable_assert_reset(obj, type); | 80 | + assert(info->si_addr == expected); |
316 | + resettable_release_reset(obj, type); | 81 | + exit(EXIT_SUCCESS); |
317 | +} | 82 | +} |
318 | + | 83 | + |
319 | +void resettable_assert_reset(Object *obj, ResetType type) | 84 | +int main() |
320 | +{ | 85 | +{ |
321 | + /* TODO: change this assert when adding support for other reset types */ | 86 | + void *tmp; |
322 | + assert(type == RESET_TYPE_COLD); | ||
323 | + trace_resettable_reset_assert_begin(obj, type); | ||
324 | + assert(!enter_phase_in_progress); | ||
325 | + | 87 | + |
326 | + enter_phase_in_progress = true; | 88 | + struct sigaction sa = { |
327 | + resettable_phase_enter(obj, NULL, type); | 89 | + .sa_sigaction = sigbus, |
328 | + enter_phase_in_progress = false; | 90 | + .sa_flags = SA_SIGINFO |
91 | + }; | ||
329 | + | 92 | + |
330 | + resettable_phase_hold(obj, NULL, type); | 93 | + if (sigaction(SIGBUS, &sa, NULL) < 0) { |
94 | + perror("sigaction"); | ||
95 | + return EXIT_FAILURE; | ||
96 | + } | ||
331 | + | 97 | + |
332 | + trace_resettable_reset_assert_end(obj); | 98 | + asm volatile("adr %0, 1f + 2\n\t" |
333 | +} | 99 | + "str %0, %1\n\t" |
334 | + | 100 | + "bx %0\n" |
335 | +void resettable_release_reset(Object *obj, ResetType type) | 101 | + "1:" |
336 | +{ | 102 | + : "=&r"(tmp), "=m"(expected)); |
337 | + /* TODO: change this assert when adding support for other reset types */ | ||
338 | + assert(type == RESET_TYPE_COLD); | ||
339 | + trace_resettable_reset_release_begin(obj, type); | ||
340 | + assert(!enter_phase_in_progress); | ||
341 | + | ||
342 | + resettable_phase_exit(obj, NULL, type); | ||
343 | + | ||
344 | + trace_resettable_reset_release_end(obj); | ||
345 | +} | ||
346 | + | ||
347 | +bool resettable_is_in_reset(Object *obj) | ||
348 | +{ | ||
349 | + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | ||
350 | + ResettableState *s = rc->get_state(obj); | ||
351 | + | ||
352 | + return s->count > 0; | ||
353 | +} | ||
354 | + | ||
355 | +/** | ||
356 | + * resettable_child_foreach: | ||
357 | + * helper to avoid checking the existence of the method. | ||
358 | + */ | ||
359 | +static void resettable_child_foreach(ResettableClass *rc, Object *obj, | ||
360 | + ResettableChildCallback cb, | ||
361 | + void *opaque, ResetType type) | ||
362 | +{ | ||
363 | + if (rc->child_foreach) { | ||
364 | + rc->child_foreach(obj, cb, opaque, type); | ||
365 | + } | ||
366 | +} | ||
367 | + | ||
368 | +/** | ||
369 | + * resettable_get_tr_func: | ||
370 | + * helper to fetch transitional reset callback if any. | ||
371 | + */ | ||
372 | +static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc, | ||
373 | + Object *obj) | ||
374 | +{ | ||
375 | + ResettableTrFunction tr_func = NULL; | ||
376 | + if (rc->get_transitional_function) { | ||
377 | + tr_func = rc->get_transitional_function(obj); | ||
378 | + } | ||
379 | + return tr_func; | ||
380 | +} | ||
381 | + | ||
382 | +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type) | ||
383 | +{ | ||
384 | + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | ||
385 | + ResettableState *s = rc->get_state(obj); | ||
386 | + const char *obj_typename = object_get_typename(obj); | ||
387 | + bool action_needed = false; | ||
388 | + | ||
389 | + /* exit phase has to finish properly before entering back in reset */ | ||
390 | + assert(!s->exit_phase_in_progress); | ||
391 | + | ||
392 | + trace_resettable_phase_enter_begin(obj, obj_typename, s->count, type); | ||
393 | + | ||
394 | + /* Only take action if we really enter reset for the 1st time. */ | ||
395 | + /* | ||
396 | + * TODO: if adding more ResetType support, some additional checks | ||
397 | + * are probably needed here. | ||
398 | + */ | ||
399 | + if (s->count++ == 0) { | ||
400 | + action_needed = true; | ||
401 | + } | ||
402 | + /* | ||
403 | + * We limit the count to an arbitrary "big" value. The value is big | ||
404 | + * enough not to be triggered normally. | ||
405 | + * The assert will stop an infinite loop if there is a cycle in the | ||
406 | + * reset tree. The loop goes through resettable_foreach_child below | ||
407 | + * which at some point will call us again. | ||
408 | + */ | ||
409 | + assert(s->count <= 50); | ||
410 | + | 103 | + |
411 | + /* | 104 | + /* |
412 | + * handle the children even if action_needed is at false so that | 105 | + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns |
413 | + * child counts are incremented too | 106 | + * the address or not. If so, we can legitimately fall through. |
414 | + */ | 107 | + */ |
415 | + resettable_child_foreach(rc, obj, resettable_phase_enter, NULL, type); | 108 | + return EXIT_SUCCESS; |
109 | +} | ||
110 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/tests/tcg/aarch64/Makefile.target | ||
113 | +++ b/tests/tcg/aarch64/Makefile.target | ||
114 | @@ -XXX,XX +XXX,XX @@ VPATH += $(ARM_SRC) | ||
115 | AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 | ||
116 | VPATH += $(AARCH64_SRC) | ||
117 | |||
118 | -# Float-convert Tests | ||
119 | -AARCH64_TESTS=fcvt | ||
120 | +# Base architecture tests | ||
121 | +AARCH64_TESTS=fcvt pcalign-a64 | ||
122 | |||
123 | fcvt: LDFLAGS+=-lm | ||
124 | |||
125 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/tests/tcg/arm/Makefile.target | ||
128 | +++ b/tests/tcg/arm/Makefile.target | ||
129 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
130 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") | ||
131 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) | ||
132 | |||
133 | +# PC alignment test | ||
134 | +ARM_TESTS += pcalign-a32 | ||
135 | +pcalign-a32: CFLAGS+=-marm | ||
416 | + | 136 | + |
417 | + /* execute enter phase for the object if needed */ | 137 | ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) |
418 | + if (action_needed) { | 138 | |
419 | + trace_resettable_phase_enter_exec(obj, obj_typename, type, | 139 | # Semihosting smoke test for linux-user |
420 | + !!rc->phases.enter); | ||
421 | + if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) { | ||
422 | + rc->phases.enter(obj, type); | ||
423 | + } | ||
424 | + s->hold_phase_pending = true; | ||
425 | + } | ||
426 | + trace_resettable_phase_enter_end(obj, obj_typename, s->count); | ||
427 | +} | ||
428 | + | ||
429 | +static void resettable_phase_hold(Object *obj, void *opaque, ResetType type) | ||
430 | +{ | ||
431 | + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | ||
432 | + ResettableState *s = rc->get_state(obj); | ||
433 | + const char *obj_typename = object_get_typename(obj); | ||
434 | + | ||
435 | + /* exit phase has to finish properly before entering back in reset */ | ||
436 | + assert(!s->exit_phase_in_progress); | ||
437 | + | ||
438 | + trace_resettable_phase_hold_begin(obj, obj_typename, s->count, type); | ||
439 | + | ||
440 | + /* handle children first */ | ||
441 | + resettable_child_foreach(rc, obj, resettable_phase_hold, NULL, type); | ||
442 | + | ||
443 | + /* exec hold phase */ | ||
444 | + if (s->hold_phase_pending) { | ||
445 | + s->hold_phase_pending = false; | ||
446 | + ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj); | ||
447 | + trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold); | ||
448 | + if (tr_func) { | ||
449 | + trace_resettable_transitional_function(obj, obj_typename); | ||
450 | + tr_func(obj); | ||
451 | + } else if (rc->phases.hold) { | ||
452 | + rc->phases.hold(obj); | ||
453 | + } | ||
454 | + } | ||
455 | + trace_resettable_phase_hold_end(obj, obj_typename, s->count); | ||
456 | +} | ||
457 | + | ||
458 | +static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) | ||
459 | +{ | ||
460 | + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | ||
461 | + ResettableState *s = rc->get_state(obj); | ||
462 | + const char *obj_typename = object_get_typename(obj); | ||
463 | + | ||
464 | + assert(!s->exit_phase_in_progress); | ||
465 | + trace_resettable_phase_exit_begin(obj, obj_typename, s->count, type); | ||
466 | + | ||
467 | + /* exit_phase_in_progress ensures this phase is 'atomic' */ | ||
468 | + s->exit_phase_in_progress = true; | ||
469 | + resettable_child_foreach(rc, obj, resettable_phase_exit, NULL, type); | ||
470 | + | ||
471 | + assert(s->count > 0); | ||
472 | + if (s->count == 1) { | ||
473 | + trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); | ||
474 | + if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) { | ||
475 | + rc->phases.exit(obj); | ||
476 | + } | ||
477 | + s->count = 0; | ||
478 | + } | ||
479 | + s->exit_phase_in_progress = false; | ||
480 | + trace_resettable_phase_exit_end(obj, obj_typename, s->count); | ||
481 | +} | ||
482 | + | ||
483 | +void resettable_class_set_parent_phases(ResettableClass *rc, | ||
484 | + ResettableEnterPhase enter, | ||
485 | + ResettableHoldPhase hold, | ||
486 | + ResettableExitPhase exit, | ||
487 | + ResettablePhases *parent_phases) | ||
488 | +{ | ||
489 | + *parent_phases = rc->phases; | ||
490 | + if (enter) { | ||
491 | + rc->phases.enter = enter; | ||
492 | + } | ||
493 | + if (hold) { | ||
494 | + rc->phases.hold = hold; | ||
495 | + } | ||
496 | + if (exit) { | ||
497 | + rc->phases.exit = exit; | ||
498 | + } | ||
499 | +} | ||
500 | + | ||
501 | +static const TypeInfo resettable_interface_info = { | ||
502 | + .name = TYPE_RESETTABLE_INTERFACE, | ||
503 | + .parent = TYPE_INTERFACE, | ||
504 | + .class_size = sizeof(ResettableClass), | ||
505 | +}; | ||
506 | + | ||
507 | +static void reset_register_types(void) | ||
508 | +{ | ||
509 | + type_register_static(&resettable_interface_info); | ||
510 | +} | ||
511 | + | ||
512 | +type_init(reset_register_types) | ||
513 | diff --git a/hw/core/trace-events b/hw/core/trace-events | ||
514 | index XXXXXXX..XXXXXXX 100644 | ||
515 | --- a/hw/core/trace-events | ||
516 | +++ b/hw/core/trace-events | ||
517 | @@ -XXX,XX +XXX,XX @@ qbus_reset(void *obj, const char *objtype) "obj=%p(%s)" | ||
518 | qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)" | ||
519 | qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" | ||
520 | qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" | ||
521 | + | ||
522 | +# resettable.c | ||
523 | +resettable_reset(void *obj, int cold) "obj=%p cold=%d" | ||
524 | +resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d" | ||
525 | +resettable_reset_assert_end(void *obj) "obj=%p" | ||
526 | +resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d" | ||
527 | +resettable_reset_release_end(void *obj) "obj=%p" | ||
528 | +resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" | ||
529 | +resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d" | ||
530 | +resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" | ||
531 | +resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" | ||
532 | +resettable_phase_hold_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" | ||
533 | +resettable_phase_hold_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" | ||
534 | +resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" | ||
535 | +resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" | ||
536 | +resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" | ||
537 | +resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)" | ||
538 | -- | 140 | -- |
539 | 2.20.1 | 141 | 2.25.1 |
540 | 142 | ||
541 | 143 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the SSE decode function gen_sse(), we combine a byte | ||
2 | 'b' and a value 'b1' which can be [0..3], and switch on them: | ||
3 | b |= (b1 << 8); | ||
4 | switch (b) { | ||
5 | ... | ||
6 | default: | ||
7 | unknown_op: | ||
8 | gen_unknown_opcode(env, s); | ||
9 | return; | ||
10 | } | ||
1 | 11 | ||
12 | In three cases inside this switch, we were then also checking for | ||
13 | "if (b1 >= 2) { goto unknown_op; }". | ||
14 | However, this can never happen, because the 'case' values in each place | ||
15 | are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3) | ||
16 | cases to the default already. | ||
17 | |||
18 | This check was added in commit c045af25a52e9 in 2010; the added code | ||
19 | was unnecessary then as well, and was apparently intended only to | ||
20 | ensure that we never accidentally ended up indexing off the end | ||
21 | of an sse_op_table with only 2 entries as a result of future bugs | ||
22 | in the decode logic. | ||
23 | |||
24 | Change the checks to assert() instead, and make sure they're always | ||
25 | immediately before the array access they are protecting. | ||
26 | |||
27 | Fixes: Coverity CID 1460207 | ||
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
29 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | --- | ||
31 | target/i386/tcg/translate.c | 12 +++--------- | ||
32 | 1 file changed, 3 insertions(+), 9 deletions(-) | ||
33 | |||
34 | diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/i386/tcg/translate.c | ||
37 | +++ b/target/i386/tcg/translate.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
39 | case 0x171: /* shift xmm, im */ | ||
40 | case 0x172: | ||
41 | case 0x173: | ||
42 | - if (b1 >= 2) { | ||
43 | - goto unknown_op; | ||
44 | - } | ||
45 | val = x86_ldub_code(env, s); | ||
46 | if (is_xmm) { | ||
47 | tcg_gen_movi_tl(s->T0, val); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
49 | offsetof(CPUX86State, mmx_t0.MMX_L(1))); | ||
50 | op1_offset = offsetof(CPUX86State,mmx_t0); | ||
51 | } | ||
52 | + assert(b1 < 2); | ||
53 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + | ||
54 | (((modrm >> 3)) & 7)][b1]; | ||
55 | if (!sse_fn_epp) { | ||
56 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
57 | rm = modrm & 7; | ||
58 | reg = ((modrm >> 3) & 7) | REX_R(s); | ||
59 | mod = (modrm >> 6) & 3; | ||
60 | - if (b1 >= 2) { | ||
61 | - goto unknown_op; | ||
62 | - } | ||
63 | |||
64 | + assert(b1 < 2); | ||
65 | sse_fn_epp = sse_op_table6[b].op[b1]; | ||
66 | if (!sse_fn_epp) { | ||
67 | goto unknown_op; | ||
68 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, | ||
69 | rm = modrm & 7; | ||
70 | reg = ((modrm >> 3) & 7) | REX_R(s); | ||
71 | mod = (modrm >> 6) & 3; | ||
72 | - if (b1 >= 2) { | ||
73 | - goto unknown_op; | ||
74 | - } | ||
75 | |||
76 | + assert(b1 < 2); | ||
77 | sse_fn_eppi = sse_op_table7[b].op[b1]; | ||
78 | if (!sse_fn_eppi) { | ||
79 | goto unknown_op; | ||
80 | -- | ||
81 | 2.25.1 | ||
82 | |||
83 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The qemu-common.h header is not supposed to be included from any | ||
2 | other header files, only from .c files (as documented in a comment at | ||
3 | the start of it). | ||
1 | 4 | ||
5 | include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule. | ||
6 | In fact, the include is not required at all, so we can just drop it | ||
7 | from both files. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/hw/i386/microvm.h | 1 - | ||
15 | include/hw/i386/x86.h | 1 - | ||
16 | 2 files changed, 2 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/i386/microvm.h | ||
21 | +++ b/include/hw/i386/microvm.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | #ifndef HW_I386_MICROVM_H | ||
24 | #define HW_I386_MICROVM_H | ||
25 | |||
26 | -#include "qemu-common.h" | ||
27 | #include "exec/hwaddr.h" | ||
28 | #include "qemu/notify.h" | ||
29 | |||
30 | diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/include/hw/i386/x86.h | ||
33 | +++ b/include/hw/i386/x86.h | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #ifndef HW_I386_X86_H | ||
36 | #define HW_I386_X86_H | ||
37 | |||
38 | -#include "qemu-common.h" | ||
39 | #include "exec/hwaddr.h" | ||
40 | #include "qemu/notify.h" | ||
41 | |||
42 | -- | ||
43 | 2.25.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The qemu-common.h header is not supposed to be included from any | ||
2 | other header files, only from .c files (as documented in a comment at | ||
3 | the start of it). | ||
1 | 4 | ||
5 | Move the include to linux-user/hexagon/cpu_loop.c, which needs it for | ||
6 | the declaration of cpu_exec_step_atomic(). | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
12 | Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/hexagon/cpu.h | 1 - | ||
15 | linux-user/hexagon/cpu_loop.c | 1 + | ||
16 | 2 files changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/hexagon/cpu.h | ||
21 | +++ b/target/hexagon/cpu.h | ||
22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState; | ||
23 | |||
24 | #include "fpu/softfloat-types.h" | ||
25 | |||
26 | -#include "qemu-common.h" | ||
27 | #include "exec/cpu-defs.h" | ||
28 | #include "hex_regs.h" | ||
29 | #include "mmvec/mmvec.h" | ||
30 | diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/linux-user/hexagon/cpu_loop.c | ||
33 | +++ b/linux-user/hexagon/cpu_loop.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | */ | ||
36 | |||
37 | #include "qemu/osdep.h" | ||
38 | +#include "qemu-common.h" | ||
39 | #include "qemu.h" | ||
40 | #include "user-internals.h" | ||
41 | #include "cpu_loop-common.h" | ||
42 | -- | ||
43 | 2.25.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
1 | The guest can use the semihosting API to open a handle | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | corresponding to QEMU's own stdin, stdout, or stderr. | 2 | other header files, only from .c files (as documented in a comment at |
3 | When the guest closes this handle, we should not | 3 | the start of it). |
4 | close the underlying host stdin/stdout/stderr | 4 | |
5 | the way we would do if the handle corresponded to | 5 | Nothing actually relies on target/rx/cpu.h including it, so we can |
6 | a host fd we'd opened on behalf of the guest in SYS_OPEN. | 6 | just drop the include. |
7 | 7 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
11 | Message-id: 20200124172954.28481-1-peter.maydell@linaro.org | 11 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> |
12 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> | ||
13 | Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org | ||
12 | --- | 14 | --- |
13 | target/arm/arm-semi.c | 9 +++++++++ | 15 | target/rx/cpu.h | 1 - |
14 | 1 file changed, 9 insertions(+) | 16 | 1 file changed, 1 deletion(-) |
15 | 17 | ||
16 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 18 | diff --git a/target/rx/cpu.h b/target/rx/cpu.h |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/arm-semi.c | 20 | --- a/target/rx/cpu.h |
19 | +++ b/target/arm/arm-semi.c | 21 | +++ b/target/rx/cpu.h |
20 | @@ -XXX,XX +XXX,XX @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) | 22 | @@ -XXX,XX +XXX,XX @@ |
21 | { | 23 | #define RX_CPU_H |
22 | CPUARMState *env = &cpu->env; | 24 | |
23 | 25 | #include "qemu/bitops.h" | |
24 | + /* | 26 | -#include "qemu-common.h" |
25 | + * Only close the underlying host fd if it's one we opened on behalf | 27 | #include "hw/registerfields.h" |
26 | + * of the guest in SYS_OPEN. | 28 | #include "cpu-qom.h" |
27 | + */ | ||
28 | + if (gf->hostfd == STDIN_FILENO || | ||
29 | + gf->hostfd == STDOUT_FILENO || | ||
30 | + gf->hostfd == STDERR_FILENO) { | ||
31 | + return 0; | ||
32 | + } | ||
33 | return set_swi_errno(env, close(gf->hostfd)); | ||
34 | } | ||
35 | 29 | ||
36 | -- | 30 | -- |
37 | 2.20.1 | 31 | 2.25.1 |
38 | 32 | ||
39 | 33 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | A lot of C files in hw/arm include qemu-common.h when they don't | ||
2 | need anything from it. Drop the include lines. | ||
1 | 3 | ||
4 | omap1.c, pxa2xx.c and strongarm.c retain the include because they | ||
5 | use it for the prototype of qemu_get_timedate(). | ||
6 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> | ||
11 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> | ||
12 | Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/boot.c | 1 - | ||
15 | hw/arm/digic_boards.c | 1 - | ||
16 | hw/arm/highbank.c | 1 - | ||
17 | hw/arm/npcm7xx_boards.c | 1 - | ||
18 | hw/arm/sbsa-ref.c | 1 - | ||
19 | hw/arm/stm32f405_soc.c | 1 - | ||
20 | hw/arm/vexpress.c | 1 - | ||
21 | hw/arm/virt.c | 1 - | ||
22 | 8 files changed, 8 deletions(-) | ||
23 | |||
24 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/arm/boot.c | ||
27 | +++ b/hw/arm/boot.c | ||
28 | @@ -XXX,XX +XXX,XX @@ | ||
29 | */ | ||
30 | |||
31 | #include "qemu/osdep.h" | ||
32 | -#include "qemu-common.h" | ||
33 | #include "qemu/datadir.h" | ||
34 | #include "qemu/error-report.h" | ||
35 | #include "qapi/error.h" | ||
36 | diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/arm/digic_boards.c | ||
39 | +++ b/hw/arm/digic_boards.c | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | |||
42 | #include "qemu/osdep.h" | ||
43 | #include "qapi/error.h" | ||
44 | -#include "qemu-common.h" | ||
45 | #include "qemu/datadir.h" | ||
46 | #include "hw/boards.h" | ||
47 | #include "qemu/error-report.h" | ||
48 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/highbank.c | ||
51 | +++ b/hw/arm/highbank.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | */ | ||
54 | |||
55 | #include "qemu/osdep.h" | ||
56 | -#include "qemu-common.h" | ||
57 | #include "qemu/datadir.h" | ||
58 | #include "qapi/error.h" | ||
59 | #include "hw/sysbus.h" | ||
60 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/hw/arm/npcm7xx_boards.c | ||
63 | +++ b/hw/arm/npcm7xx_boards.c | ||
64 | @@ -XXX,XX +XXX,XX @@ | ||
65 | #include "hw/qdev-core.h" | ||
66 | #include "hw/qdev-properties.h" | ||
67 | #include "qapi/error.h" | ||
68 | -#include "qemu-common.h" | ||
69 | #include "qemu/datadir.h" | ||
70 | #include "qemu/units.h" | ||
71 | #include "sysemu/blockdev.h" | ||
72 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/arm/sbsa-ref.c | ||
75 | +++ b/hw/arm/sbsa-ref.c | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | */ | ||
78 | |||
79 | #include "qemu/osdep.h" | ||
80 | -#include "qemu-common.h" | ||
81 | #include "qemu/datadir.h" | ||
82 | #include "qapi/error.h" | ||
83 | #include "qemu/error-report.h" | ||
84 | diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/arm/stm32f405_soc.c | ||
87 | +++ b/hw/arm/stm32f405_soc.c | ||
88 | @@ -XXX,XX +XXX,XX @@ | ||
89 | |||
90 | #include "qemu/osdep.h" | ||
91 | #include "qapi/error.h" | ||
92 | -#include "qemu-common.h" | ||
93 | #include "exec/address-spaces.h" | ||
94 | #include "sysemu/sysemu.h" | ||
95 | #include "hw/arm/stm32f405_soc.h" | ||
96 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/hw/arm/vexpress.c | ||
99 | +++ b/hw/arm/vexpress.c | ||
100 | @@ -XXX,XX +XXX,XX @@ | ||
101 | |||
102 | #include "qemu/osdep.h" | ||
103 | #include "qapi/error.h" | ||
104 | -#include "qemu-common.h" | ||
105 | #include "qemu/datadir.h" | ||
106 | #include "cpu.h" | ||
107 | #include "hw/sysbus.h" | ||
108 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
109 | index XXXXXXX..XXXXXXX 100644 | ||
110 | --- a/hw/arm/virt.c | ||
111 | +++ b/hw/arm/virt.c | ||
112 | @@ -XXX,XX +XXX,XX @@ | ||
113 | */ | ||
114 | |||
115 | #include "qemu/osdep.h" | ||
116 | -#include "qemu-common.h" | ||
117 | #include "qemu/datadir.h" | ||
118 | #include "qemu/units.h" | ||
119 | #include "qemu/option.h" | ||
120 | -- | ||
121 | 2.25.1 | ||
122 | |||
123 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The calculation of the length of TLB range invalidate operations | ||
2 | in tlbi_aa64_range_get_length() is incorrect in two ways: | ||
3 | * the NUM field is 5 bits, but we read only 4 bits | ||
4 | * we miscalculate the page_shift value, because of an | ||
5 | off-by-one error: | ||
6 | TG 0b00 is invalid | ||
7 | TG 0b01 is 4K granule size == 4096 == 2^12 | ||
8 | TG 0b10 is 16K granule size == 16384 == 2^14 | ||
9 | TG 0b11 is 64K granule size == 65536 == 2^16 | ||
10 | so page_shift should be (TG - 1) * 2 + 12 | ||
1 | 11 | ||
12 | Thanks to the bug report submitter Cha HyunSoo for identifying | ||
13 | both these errors. | ||
14 | |||
15 | Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE") | ||
16 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734 | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
19 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
20 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
21 | Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org | ||
22 | --- | ||
23 | target/arm/helper.c | 6 +++--- | ||
24 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
25 | |||
26 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/helper.c | ||
29 | +++ b/target/arm/helper.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, | ||
31 | uint64_t exponent; | ||
32 | uint64_t length; | ||
33 | |||
34 | - num = extract64(value, 39, 4); | ||
35 | + num = extract64(value, 39, 5); | ||
36 | scale = extract64(value, 44, 2); | ||
37 | page_size_granule = extract64(value, 46, 2); | ||
38 | |||
39 | - page_shift = page_size_granule * 2 + 12; | ||
40 | - | ||
41 | if (page_size_granule == 0) { | ||
42 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", | ||
43 | page_size_granule); | ||
44 | return 0; | ||
45 | } | ||
46 | |||
47 | + page_shift = (page_size_granule - 1) * 2 + 12; | ||
48 | + | ||
49 | exponent = (5 * scale) + 1; | ||
50 | length = (num + 1) << (exponent + page_shift); | ||
51 | |||
52 | -- | ||
53 | 2.25.1 | ||
54 | |||
55 | diff view generated by jsdifflib |
1 | From: Andrew Jeffery <andrew@aj.id.au> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Initialise another SDHCI model instance for the AST2600's eMMC | 3 | The rx_active boolean change to true should always trigger a try_read |
4 | controller and use the SDHCI's num_slots value introduced previously to | 4 | call that flushes the queue. |
5 | determine whether we should create an SD card instance for the new slot. | ||
6 | 5 | ||
7 | Signed-off-by: Andrew Jeffery <andrew@aj.id.au> | 6 | Signed-off-by: Patrick Venture <venture@google.com> |
8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Message-id: 20211203221002.1719306-1-venture@google.com |
10 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
11 | Message-id: 20200114103433.30534-3-clg@kaod.org | ||
12 | [ clg : - removed ternary operator from sdhci_attach_drive() | ||
13 | - renamed SDHCI objects with a '-controller' prefix ] | ||
14 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 10 | --- |
17 | include/hw/arm/aspeed_soc.h | 2 ++ | 11 | hw/net/npcm7xx_emc.c | 18 ++++++++---------- |
18 | hw/arm/aspeed.c | 26 +++++++++++++++++--------- | 12 | 1 file changed, 8 insertions(+), 10 deletions(-) |
19 | hw/arm/aspeed_ast2600.c | 29 ++++++++++++++++++++++++++--- | ||
20 | 3 files changed, 45 insertions(+), 12 deletions(-) | ||
21 | 13 | ||
22 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 14 | diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c |
23 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/include/hw/arm/aspeed_soc.h | 16 | --- a/hw/net/npcm7xx_emc.c |
25 | +++ b/include/hw/arm/aspeed_soc.h | 17 | +++ b/hw/net/npcm7xx_emc.c |
26 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | 18 | @@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) |
27 | AspeedGPIOState gpio; | 19 | emc_set_mista(emc, mista_flag); |
28 | AspeedGPIOState gpio_1_8v; | ||
29 | AspeedSDHCIState sdhci; | ||
30 | + AspeedSDHCIState emmc; | ||
31 | } AspeedSoCState; | ||
32 | |||
33 | #define TYPE_ASPEED_SOC "aspeed-soc" | ||
34 | @@ -XXX,XX +XXX,XX @@ enum { | ||
35 | ASPEED_MII4, | ||
36 | ASPEED_SDRAM, | ||
37 | ASPEED_XDMA, | ||
38 | + ASPEED_EMMC, | ||
39 | }; | ||
40 | |||
41 | #endif /* ASPEED_SOC_H */ | ||
42 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/aspeed.c | ||
45 | +++ b/hw/arm/aspeed.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, | ||
47 | } | ||
48 | } | 20 | } |
49 | 21 | ||
50 | +static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) | 22 | +static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) |
51 | +{ | 23 | +{ |
52 | + DeviceState *card; | 24 | + emc->rx_active = true; |
53 | + | 25 | + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); |
54 | + card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | ||
55 | + TYPE_SD_CARD); | ||
56 | + if (dinfo) { | ||
57 | + qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), | ||
58 | + &error_fatal); | ||
59 | + } | ||
60 | + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); | ||
61 | +} | 26 | +} |
62 | + | 27 | + |
63 | static void aspeed_machine_init(MachineState *machine) | 28 | static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, |
29 | const NPCM7xxEMCTxDesc *tx_desc, | ||
30 | uint32_t desc_addr) | ||
31 | @@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) | ||
32 | return len; | ||
33 | } | ||
34 | |||
35 | -static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) | ||
36 | -{ | ||
37 | - if (emc_can_receive(qemu_get_queue(emc->nic))) { | ||
38 | - qemu_flush_queued_packets(qemu_get_queue(emc->nic)); | ||
39 | - } | ||
40 | -} | ||
41 | - | ||
42 | static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) | ||
64 | { | 43 | { |
65 | AspeedBoardState *bmc; | 44 | NPCM7xxEMCState *emc = opaque; |
66 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | 45 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, |
67 | } | 46 | emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; |
68 | 47 | } | |
69 | for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { | 48 | if (value & REG_MCMDR_RXON) { |
70 | - SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; | 49 | - emc->rx_active = true; |
71 | - DriveInfo *dinfo = drive_get_next(IF_SD); | 50 | + emc_enable_rx_and_flush(emc); |
72 | - BlockBackend *blk; | 51 | } else { |
73 | - DeviceState *card; | 52 | emc_halt_rx(emc, 0); |
74 | + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); | 53 | } |
75 | + } | 54 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, |
76 | 55 | break; | |
77 | - blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | 56 | case REG_RSDR: |
78 | - card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | 57 | if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { |
79 | - TYPE_SD_CARD); | 58 | - emc->rx_active = true; |
80 | - qdev_prop_set_drive(card, "drive", blk, &error_fatal); | 59 | - emc_try_receive_next_packet(emc); |
81 | - object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); | 60 | + emc_enable_rx_and_flush(emc); |
82 | + if (bmc->soc.emmc.num_slots) { | 61 | } |
83 | + sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); | 62 | break; |
84 | } | 63 | case REG_MIIDA: |
85 | |||
86 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); | ||
87 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
88 | index XXXXXXX..XXXXXXX 100644 | ||
89 | --- a/hw/arm/aspeed_ast2600.c | ||
90 | +++ b/hw/arm/aspeed_ast2600.c | ||
91 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
92 | [ASPEED_ADC] = 0x1E6E9000, | ||
93 | [ASPEED_VIDEO] = 0x1E700000, | ||
94 | [ASPEED_SDHCI] = 0x1E740000, | ||
95 | + [ASPEED_EMMC] = 0x1E750000, | ||
96 | [ASPEED_GPIO] = 0x1E780000, | ||
97 | [ASPEED_GPIO_1_8V] = 0x1E780800, | ||
98 | [ASPEED_RTC] = 0x1E781000, | ||
99 | @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { | ||
100 | |||
101 | #define ASPEED_SOC_AST2600_MAX_IRQ 128 | ||
102 | |||
103 | +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ | ||
104 | static const int aspeed_soc_ast2600_irqmap[] = { | ||
105 | [ASPEED_UART1] = 47, | ||
106 | [ASPEED_UART2] = 48, | ||
107 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { | ||
108 | [ASPEED_ADC] = 78, | ||
109 | [ASPEED_XDMA] = 6, | ||
110 | [ASPEED_SDHCI] = 43, | ||
111 | + [ASPEED_EMMC] = 15, | ||
112 | [ASPEED_GPIO] = 40, | ||
113 | [ASPEED_GPIO_1_8V] = 11, | ||
114 | [ASPEED_RTC] = 13, | ||
115 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
116 | sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), | ||
117 | sizeof(s->gpio_1_8v), typename); | ||
118 | |||
119 | - sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | ||
120 | - TYPE_ASPEED_SDHCI); | ||
121 | + sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), | ||
122 | + sizeof(s->sdhci), TYPE_ASPEED_SDHCI); | ||
123 | |||
124 | object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); | ||
125 | |||
126 | /* Init sd card slot class here so that they're under the correct parent */ | ||
127 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | ||
128 | - sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | ||
129 | + sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", | ||
130 | + OBJECT(&s->sdhci.slots[i]), | ||
131 | sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | ||
132 | } | ||
133 | + | ||
134 | + sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), | ||
135 | + sizeof(s->emmc), TYPE_ASPEED_SDHCI); | ||
136 | + | ||
137 | + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); | ||
138 | + | ||
139 | + sysbus_init_child_obj(obj, "emmc-controller.sdhci", | ||
140 | + OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), | ||
141 | + TYPE_SYSBUS_SDHCI); | ||
142 | } | ||
143 | |||
144 | /* | ||
145 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
146 | sc->memmap[ASPEED_SDHCI]); | ||
147 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
148 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | ||
149 | + | ||
150 | + /* eMMC */ | ||
151 | + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); | ||
152 | + if (err) { | ||
153 | + error_propagate(errp, err); | ||
154 | + return; | ||
155 | + } | ||
156 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); | ||
157 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, | ||
158 | + aspeed_soc_get_irq(s, ASPEED_EMMC)); | ||
159 | } | ||
160 | |||
161 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | ||
162 | -- | 64 | -- |
163 | 2.20.1 | 65 | 2.25.1 |
164 | 66 | ||
165 | 67 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Replace deprecated qdev_reset_all by resettable_cold_reset_fn for | 3 | When a virtio-iommu is instantiated, describe it using the ACPI VIOT |
4 | the ipl registration in the main reset handlers. | 4 | table. |
5 | 5 | ||
6 | This does not impact the behavior for the following reasons: | 6 | Acked-by: Igor Mammedov <imammedo@redhat.com> |
7 | + at this point resettable just call the old reset methods of devices | 7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | and buses in the same order than qdev/qbus. | 8 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
9 | + resettable handlers registered with qemu_register_reset are | 9 | Message-id: 20211210170415.583179-2-jean-philippe@linaro.org |
10 | serialized; there is no interleaving. | ||
11 | + eventual explicit calls to legacy reset API (device_reset or | ||
12 | qdev/qbus_reset) inside this reset handler will not be masked out | ||
13 | by resettable mechanism; they do not go through resettable api. | ||
14 | |||
15 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 11 | --- |
23 | hw/s390x/ipl.c | 10 +++++++++- | 12 | hw/arm/virt-acpi-build.c | 7 +++++++ |
24 | 1 file changed, 9 insertions(+), 1 deletion(-) | 13 | hw/arm/Kconfig | 1 + |
14 | 2 files changed, 8 insertions(+) | ||
25 | 15 | ||
26 | diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c | 16 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c |
27 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/s390x/ipl.c | 18 | --- a/hw/arm/virt-acpi-build.c |
29 | +++ b/hw/s390x/ipl.c | 19 | +++ b/hw/arm/virt-acpi-build.c |
30 | @@ -XXX,XX +XXX,XX @@ static void s390_ipl_realize(DeviceState *dev, Error **errp) | 20 | @@ -XXX,XX +XXX,XX @@ |
31 | */ | 21 | #include "kvm_arm.h" |
32 | ipl->compat_start_addr = ipl->start_addr; | 22 | #include "migration/vmstate.h" |
33 | ipl->compat_bios_start_addr = ipl->bios_start_addr; | 23 | #include "hw/acpi/ghes.h" |
34 | - qemu_register_reset(qdev_reset_all_fn, dev); | 24 | +#include "hw/acpi/viot.h" |
35 | + /* | 25 | |
36 | + * Because this Device is not on any bus in the qbus tree (it is | 26 | #define ARM_SPI_BASE 32 |
37 | + * not a sysbus device and it's not on some other bus like a PCI | 27 | |
38 | + * bus) it will not be automatically reset by the 'reset the | 28 | @@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
39 | + * sysbus' hook registered by vl.c like most devices. So we must | 29 | } |
40 | + * manually register a reset hook for it. | 30 | #endif |
41 | + * TODO: there should be a better way to do this. | 31 | |
42 | + */ | 32 | + if (vms->iommu == VIRT_IOMMU_VIRTIO) { |
43 | + qemu_register_reset(resettable_cold_reset_fn, dev); | 33 | + acpi_add_table(table_offsets, tables_blob); |
44 | error: | 34 | + build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, |
45 | error_propagate(errp, err); | 35 | + vms->oem_id, vms->oem_table_id); |
46 | } | 36 | + } |
37 | + | ||
38 | /* XSDT is pointed to by RSDP */ | ||
39 | xsdt = tables_blob->len; | ||
40 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, | ||
41 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/hw/arm/Kconfig | ||
44 | +++ b/hw/arm/Kconfig | ||
45 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | ||
46 | select DIMM | ||
47 | select ACPI_HW_REDUCED | ||
48 | select ACPI_APEI | ||
49 | + select ACPI_VIOT | ||
50 | |||
51 | config CHEETAH | ||
52 | bool | ||
47 | -- | 53 | -- |
48 | 2.20.1 | 54 | 2.25.1 |
49 | 55 | ||
50 | 56 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 3 | virtio-iommu is now supported with ACPI VIOT as well as device tree. |
4 | Message-id: 20200120101023.16030-3-drjones@redhat.com | 4 | Remove the restriction that prevents from instantiating a virtio-iommu |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | device under ACPI. |
6 | |||
7 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
10 | Message-id: 20211210170415.583179-3-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | hw/arm/virt.c | 1 + | 13 | hw/arm/virt.c | 10 ++-------- |
9 | 1 file changed, 1 insertion(+) | 14 | hw/virtio/virtio-iommu-pci.c | 12 ++---------- |
15 | 2 files changed, 4 insertions(+), 18 deletions(-) | ||
10 | 16 | ||
11 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/virt.c | 19 | --- a/hw/arm/virt.c |
14 | +++ b/hw/arm/virt.c | 20 | +++ b/hw/arm/virt.c |
15 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) | 21 | @@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, |
16 | 22 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
17 | static void virt_machine_4_2_options(MachineClass *mc) | 23 | |
18 | { | 24 | if (device_is_dynamic_sysbus(mc, dev) || |
19 | + virt_machine_5_0_options(mc); | 25 | - (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { |
20 | compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); | 26 | + object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
27 | + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | ||
28 | return HOTPLUG_HANDLER(machine); | ||
29 | } | ||
30 | - if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | ||
31 | - VirtMachineState *vms = VIRT_MACHINE(machine); | ||
32 | - | ||
33 | - if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { | ||
34 | - return HOTPLUG_HANDLER(machine); | ||
35 | - } | ||
36 | - } | ||
37 | return NULL; | ||
21 | } | 38 | } |
22 | DEFINE_VIRT_MACHINE(4, 2) | 39 | |
40 | diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/virtio/virtio-iommu-pci.c | ||
43 | +++ b/hw/virtio/virtio-iommu-pci.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) | ||
45 | VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); | ||
46 | |||
47 | if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { | ||
48 | - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); | ||
49 | - | ||
50 | - error_setg(errp, | ||
51 | - "%s machine fails to create iommu-map device tree bindings", | ||
52 | - mc->name); | ||
53 | - error_append_hint(errp, | ||
54 | - "Check your machine implements a hotplug handler " | ||
55 | - "for the virtio-iommu-pci device\n"); | ||
56 | - error_append_hint(errp, "Check the guest is booted without FW or with " | ||
57 | - "-no-acpi\n"); | ||
58 | + error_setg(errp, "Check your machine implements a hotplug handler " | ||
59 | + "for the virtio-iommu-pci device"); | ||
60 | return; | ||
61 | } | ||
62 | for (int i = 0; i < s->nb_reserved_regions; i++) { | ||
23 | -- | 63 | -- |
24 | 2.20.1 | 64 | 2.25.1 |
25 | 65 | ||
26 | 66 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These buffers should be aligned on 16 bytes. | 3 | We do not support instantiating multiple IOMMUs. Before adding a |
4 | virtio-iommu, check that no other IOMMU is present. This will detect | ||
5 | both "iommu=smmuv3" machine parameter and another virtio-iommu instance. | ||
4 | 6 | ||
5 | Ignore invalid RX and TX buffer addresses and log an error. All | 7 | Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings") |
6 | incoming and outgoing traffic will be dropped because no valid RX or | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
7 | TX descriptors will be available. | 9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
8 | 10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | |
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 11 | Message-id: 20211210170415.583179-4-jean-philippe@linaro.org |
10 | Message-id: 20200114103433.30534-4-clg@kaod.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 13 | --- |
14 | hw/net/ftgmac100.c | 13 +++++++++++++ | 14 | hw/arm/virt.c | 5 +++++ |
15 | 1 file changed, 13 insertions(+) | 15 | 1 file changed, 5 insertions(+) |
16 | 16 | ||
17 | diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/net/ftgmac100.c | 19 | --- a/hw/arm/virt.c |
20 | +++ b/hw/net/ftgmac100.c | 20 | +++ b/hw/arm/virt.c |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
22 | uint32_t des3; | 22 | hwaddr db_start = 0, db_end = 0; |
23 | } FTGMAC100Desc; | 23 | char *resv_prop_str; |
24 | 24 | ||
25 | +#define FTGMAC100_DESC_ALIGNMENT 16 | 25 | + if (vms->iommu != VIRT_IOMMU_NONE) { |
26 | + | 26 | + error_setg(errp, "virt machine does not support multiple IOMMUs"); |
27 | /* | ||
28 | * Specific RTL8211E MII Registers | ||
29 | */ | ||
30 | @@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr, | ||
31 | s->itc = value; | ||
32 | break; | ||
33 | case FTGMAC100_RXR_BADR: /* Ring buffer address */ | ||
34 | + if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { | ||
35 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%" | ||
36 | + HWADDR_PRIx "\n", __func__, value); | ||
37 | + return; | 27 | + return; |
38 | + } | 28 | + } |
39 | + | 29 | + |
40 | s->rx_ring = value; | 30 | switch (vms->msi_controller) { |
41 | s->rx_descriptor = s->rx_ring; | 31 | case VIRT_MSI_CTRL_NONE: |
42 | break; | 32 | return; |
43 | @@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr, | ||
44 | break; | ||
45 | |||
46 | case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */ | ||
47 | + if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { | ||
48 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%" | ||
49 | + HWADDR_PRIx "\n", __func__, value); | ||
50 | + return; | ||
51 | + } | ||
52 | s->tx_ring = value; | ||
53 | s->tx_descriptor = s->tx_ring; | ||
54 | break; | ||
55 | -- | 33 | -- |
56 | 2.20.1 | 34 | 2.25.1 |
57 | 35 | ||
58 | 36 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | In qdev_set_parent_bus(), when changing the parent bus of a | 3 | To propagate errors to the caller of the pre_plug callback, use the |
4 | realized device, if the source and destination buses are not in the | 4 | object_poperty_set*() functions directly instead of the qdev_prop_set*() |
5 | same reset state, some adaptations are required. This patch adds | 5 | helpers. |
6 | needed call to resettable_change_parent() to make sure a device reset | ||
7 | state stays coherent with its parent bus. | ||
8 | 6 | ||
9 | The addition is a no-op if: | 7 | Suggested-by: Igor Mammedov <imammedo@redhat.com> |
10 | 1. the device being parented is not realized. | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
11 | 2. the device is realized, but both buses are not under reset. | 9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
12 | 10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | |
13 | Case 2 means that as long as qdev_set_parent_bus() is called | 11 | Message-id: 20211210170415.583179-5-jean-philippe@linaro.org |
14 | during the machine realization procedure (which is before the | ||
15 | machine reset so nothing is in reset), it is a no op. | ||
16 | |||
17 | There are 52 call sites of qdev_set_parent_bus(). All but one fall | ||
18 | into the no-op case: | ||
19 | + 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/ | ||
20 | {vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device | ||
21 | parent bus just before realizing the same vdev(vgpu). | ||
22 | + hw/core/qdev.c: when creating a device in qdev_try_create() | ||
23 | + hw/core/sysbus.c: when initializing a device in the sysbus | ||
24 | + hw/i386/amd_iommu.c: before realizing AMDVIState/pci | ||
25 | + hw/isa/piix4.c: before realizing PIIX4State/rtc | ||
26 | + hw/misc/auxbus.c: when creating an AUXBus | ||
27 | + hw/misc/auxbus.c: when creating an AUXBus child | ||
28 | + hw/misc/macio/macio.c: when initializing a MACIOState child | ||
29 | + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu | ||
30 | + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda | ||
31 | + hw/net/virtio-net.c: Used for migration when using the failover | ||
32 | mechanism to migration a vfio-pci/net. It is | ||
33 | a no-op because at this point the device is | ||
34 | already on the bus. | ||
35 | + hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root | ||
36 | + hw/pci-host/gpex.c: before realizing GPEXHost/root | ||
37 | + hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev | ||
38 | + hw/pci-host/q35.c: before realizing Q35PCIHost/mch | ||
39 | + hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev | ||
40 | + hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root | ||
41 | + hw/s390x/event-facility.c: when creating SCLPEventFacility/ | ||
42 | TYPE_SCLP_QUIESCE | ||
43 | + hw/s390x/event-facility.c: ditto with SCLPEventFacility/ | ||
44 | TYPE_SCLP_CPU_HOTPLUG | ||
45 | + hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice | ||
46 | just after realizing it. Ok because at this point the destination | ||
47 | bus (sysbus) is not in reset; the realize step is before the | ||
48 | machine reset. | ||
49 | + hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below. | ||
50 | + hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs | ||
51 | line in ssi_auto_connect_slave(). Ok because this function is only | ||
52 | used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c, | ||
53 | hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c. | ||
54 | + hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device | ||
55 | + qdev-monitor.c: in device hotplug creation procedure before realize | ||
56 | |||
57 | Note that this commit alone will have no effect, right now there is no | ||
58 | use of resettable API to reset anything. So a bus will never be tagged | ||
59 | as in-reset by this same API. | ||
60 | |||
61 | The one place where side-effect will occurs is in hw/sd/core.c in | ||
62 | sdbus_reparent_card(). This function is only used in the raspi machines, | ||
63 | including during the sysbus reset procedure. This case will be | ||
64 | carrefully handled when doing the multiple phase reset transition. | ||
65 | |||
66 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
67 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
68 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
69 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
70 | Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com | ||
71 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
72 | --- | 13 | --- |
73 | hw/core/qdev.c | 16 +++++++++++----- | 14 | hw/arm/virt.c | 5 +++-- |
74 | 1 file changed, 11 insertions(+), 5 deletions(-) | 15 | 1 file changed, 3 insertions(+), 2 deletions(-) |
75 | 16 | ||
76 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
77 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
78 | --- a/hw/core/qdev.c | 19 | --- a/hw/arm/virt.c |
79 | +++ b/hw/core/qdev.c | 20 | +++ b/hw/arm/virt.c |
80 | @@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child) | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
81 | 22 | db_start, db_end, | |
82 | void qdev_set_parent_bus(DeviceState *dev, BusState *bus) | 23 | VIRTIO_IOMMU_RESV_MEM_T_MSI); |
83 | { | 24 | |
84 | - bool replugging = dev->parent_bus != NULL; | 25 | - qdev_prop_set_uint32(dev, "len-reserved-regions", 1); |
85 | + BusState *old_parent_bus = dev->parent_bus; | 26 | - qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); |
86 | 27 | + object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); | |
87 | - if (replugging) { | 28 | + object_property_set_str(OBJECT(dev), "reserved-regions[0]", |
88 | + if (old_parent_bus) { | 29 | + resv_prop_str, errp); |
89 | trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)), | 30 | g_free(resv_prop_str); |
90 | - dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)), | ||
91 | + old_parent_bus, object_get_typename(OBJECT(old_parent_bus)), | ||
92 | OBJECT(bus), object_get_typename(OBJECT(bus))); | ||
93 | /* | ||
94 | * Keep a reference to the device while it's not plugged into | ||
95 | * any bus, to avoid it potentially evaporating when it is | ||
96 | * dereffed in bus_remove_child(). | ||
97 | + * Also keep the ref of the parent bus until the end, so that | ||
98 | + * we can safely call resettable_change_parent() below. | ||
99 | */ | ||
100 | object_ref(OBJECT(dev)); | ||
101 | bus_remove_child(dev->parent_bus, dev); | ||
102 | - object_unref(OBJECT(dev->parent_bus)); | ||
103 | } | ||
104 | dev->parent_bus = bus; | ||
105 | object_ref(OBJECT(bus)); | ||
106 | bus_add_child(bus, dev); | ||
107 | - if (replugging) { | ||
108 | + if (dev->realized) { | ||
109 | + resettable_change_parent(OBJECT(dev), OBJECT(bus), | ||
110 | + OBJECT(old_parent_bus)); | ||
111 | + } | ||
112 | + if (old_parent_bus) { | ||
113 | + object_unref(OBJECT(old_parent_bus)); | ||
114 | object_unref(OBJECT(dev)); | ||
115 | } | 31 | } |
116 | } | 32 | } |
117 | -- | 33 | -- |
118 | 2.20.1 | 34 | 2.25.1 |
119 | 35 | ||
120 | 36 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Replace deprecated qbus_reset_all by resettable_cold_reset_fn for | 3 | Create empty data files and allow updates for the upcoming VIOT tests. |
4 | the sysbus reset registration. | ||
5 | 4 | ||
6 | Apart for the raspi machines, this does not impact the behavior | 5 | Acked-by: Igor Mammedov <imammedo@redhat.com> |
7 | because: | 6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | + at this point resettable just calls the old reset methods of devices | 7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
9 | and buses in the same order as qdev/qbus. | 8 | Message-id: 20211210170415.583179-6-jean-philippe@linaro.org |
10 | + resettable handlers registered with qemu_register_reset are | ||
11 | serialized; there is no interleaving. | ||
12 | + eventual explicit calls to legacy reset API (device_reset or | ||
13 | qdev/qbus_reset) inside this reset handler will not be masked out | ||
14 | by resettable mechanism; they do not go through resettable api. | ||
15 | |||
16 | For the raspi machines, during the sysbus reset the sd-card is not | ||
17 | reset twice anymore but only once. This is a consequence of switching | ||
18 | both sysbus reset and changing parent to resettable; it detects the | ||
19 | second reset is not needed. This has no impact on the state after | ||
20 | reset; the sd-card reset method only reset local state and query | ||
21 | information from the block backend. | ||
22 | |||
23 | The raspi reset change can be observed by using the following command | ||
24 | (reset will occurs, then do Ctrl-C to end qemu; no firmware is | ||
25 | given here). | ||
26 | qemu-system-aarch64 -M raspi3 \ | ||
27 | -trace resettable_phase_hold_exec \ | ||
28 | -trace qdev_update_parent_bus \ | ||
29 | -trace resettable_change_parent \ | ||
30 | -trace qdev_reset -trace qbus_reset | ||
31 | |||
32 | Before the patch, the qdev/qbus_reset traces show when reset method are | ||
33 | called. After the patch, the resettable_phase_hold_exec show when reset | ||
34 | method are called. | ||
35 | |||
36 | The traced reset order of the raspi3 is listed below. I've added empty | ||
37 | lines and the tree structure. | ||
38 | |||
39 | +->bcm2835-peripherals reset | ||
40 | | | ||
41 | | +->sd-card reset | ||
42 | | +->sd-bus reset | ||
43 | +->bcm2835_gpio reset | ||
44 | | -> dev_update_parent_bus (move the sd-card on the sdhci-bus) | ||
45 | | -> resettable_change_parent | ||
46 | | | ||
47 | +->bcm2835-dma reset | ||
48 | | | ||
49 | | +->bcm2835-sdhost-bus reset | ||
50 | +->bcm2835-sdhost reset | ||
51 | | | ||
52 | | +->sd-card (reset ONLY BEFORE BEFORE THE PATCH) | ||
53 | | +->sdhci-bus reset | ||
54 | +->generic-sdhci reset | ||
55 | | | ||
56 | +->bcm2835-rng reset | ||
57 | +->bcm2835-property reset | ||
58 | +->bcm2835-fb reset | ||
59 | +->bcm2835-mbox reset | ||
60 | +->bcm2835-aux reset | ||
61 | +->pl011 reset | ||
62 | +->bcm2835-ic reset | ||
63 | +->bcm2836-control reset | ||
64 | System reset | ||
65 | |||
66 | In both case, the sd-card is reset (being on bcm2835_gpio/sd-bus) then moved | ||
67 | to generic-sdhci/sdhci-bus by the bcm2835_gpio reset method. | ||
68 | |||
69 | Before the patch, it is then reset again being part of generic-sdhci/sdhci-bus. | ||
70 | After the patch, it considered again for reset but its reset method is not | ||
71 | called because it is already flagged as reset. | ||
72 | |||
73 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
74 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
75 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
76 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
77 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
78 | Message-id: 20200123132823.1117486-11-damien.hedde@greensocs.com | ||
79 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
80 | --- | 10 | --- |
81 | vl.c | 10 +++++++++- | 11 | tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ |
82 | 1 file changed, 9 insertions(+), 1 deletion(-) | 12 | tests/data/acpi/q35/DSDT.viot | 0 |
13 | tests/data/acpi/q35/VIOT.viot | 0 | ||
14 | tests/data/acpi/virt/VIOT | 0 | ||
15 | 4 files changed, 3 insertions(+) | ||
16 | create mode 100644 tests/data/acpi/q35/DSDT.viot | ||
17 | create mode 100644 tests/data/acpi/q35/VIOT.viot | ||
18 | create mode 100644 tests/data/acpi/virt/VIOT | ||
83 | 19 | ||
84 | diff --git a/vl.c b/vl.c | 20 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h |
85 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
86 | --- a/vl.c | 22 | --- a/tests/qtest/bios-tables-test-allowed-diff.h |
87 | +++ b/vl.c | 23 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h |
88 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp) | 24 | @@ -1 +1,4 @@ |
89 | 25 | /* List of comma-separated changed AML files to ignore */ | |
90 | /* TODO: once all bus devices are qdevified, this should be done | 26 | +"tests/data/acpi/virt/VIOT", |
91 | * when bus is created by qdev.c */ | 27 | +"tests/data/acpi/q35/DSDT.viot", |
92 | - qemu_register_reset(qbus_reset_all_fn, sysbus_get_default()); | 28 | +"tests/data/acpi/q35/VIOT.viot", |
93 | + /* | 29 | diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot |
94 | + * TODO: If we had a main 'reset container' that the whole system | 30 | new file mode 100644 |
95 | + * lived in, we could reset that using the multi-phase reset | 31 | index XXXXXXX..XXXXXXX |
96 | + * APIs. For the moment, we just reset the sysbus, which will cause | 32 | diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot |
97 | + * all devices hanging off it (and all their child buses, recursively) | 33 | new file mode 100644 |
98 | + * to be reset. Note that this will *not* reset any Device objects | 34 | index XXXXXXX..XXXXXXX |
99 | + * which are not attached to some part of the qbus tree! | 35 | diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT |
100 | + */ | 36 | new file mode 100644 |
101 | + qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); | 37 | index XXXXXXX..XXXXXXX |
102 | qemu_run_machine_init_done_notifiers(); | ||
103 | |||
104 | if (rom_check_and_register_reset() != 0) { | ||
105 | -- | 38 | -- |
106 | 2.20.1 | 39 | 2.25.1 |
107 | 40 | ||
108 | 41 | diff view generated by jsdifflib |
1 | From: Damien Hedde <damien.hedde@greensocs.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Adds trace events to reset procedure and when updating the parent | 3 | Add two test cases for VIOT, one on the q35 machine and the other on |
4 | bus of a device. | 4 | virt. To test complex topologies the q35 test has two PCIe buses that |
5 | bypass the IOMMU (and are therefore not described by VIOT), and two | ||
6 | buses that are translated by virtio-iommu. | ||
5 | 7 | ||
6 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | 8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
9 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | 11 | Message-id: 20211210170415.583179-7-jean-philippe@linaro.org |
10 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
11 | Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 13 | --- |
14 | hw/core/qdev.c | 29 ++++++++++++++++++++++++++--- | 14 | tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++ |
15 | hw/core/trace-events | 9 +++++++++ | 15 | 1 file changed, 38 insertions(+) |
16 | 2 files changed, 35 insertions(+), 3 deletions(-) | ||
17 | 16 | ||
18 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 17 | diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/core/qdev.c | 19 | --- a/tests/qtest/bios-tables-test.c |
21 | +++ b/hw/core/qdev.c | 20 | +++ b/tests/qtest/bios-tables-test.c |
22 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void) |
23 | #include "hw/boards.h" | 22 | free_test_data(&data); |
24 | #include "hw/sysbus.h" | ||
25 | #include "migration/vmstate.h" | ||
26 | +#include "trace.h" | ||
27 | |||
28 | bool qdev_hotplug = false; | ||
29 | static bool qdev_hot_added = false; | ||
30 | @@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) | ||
31 | bool replugging = dev->parent_bus != NULL; | ||
32 | |||
33 | if (replugging) { | ||
34 | - /* Keep a reference to the device while it's not plugged into | ||
35 | + trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)), | ||
36 | + dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)), | ||
37 | + OBJECT(bus), object_get_typename(OBJECT(bus))); | ||
38 | + /* | ||
39 | + * Keep a reference to the device while it's not plugged into | ||
40 | * any bus, to avoid it potentially evaporating when it is | ||
41 | * dereffed in bus_remove_child(). | ||
42 | */ | ||
43 | @@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) | ||
44 | return hotplug_ctrl; | ||
45 | } | 23 | } |
46 | 24 | ||
47 | +static int qdev_prereset(DeviceState *dev, void *opaque) | 25 | +static void test_acpi_q35_viot(void) |
48 | +{ | 26 | +{ |
49 | + trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev))); | 27 | + test_data data = { |
50 | + return 0; | 28 | + .machine = MACHINE_Q35, |
29 | + .variant = ".viot", | ||
30 | + }; | ||
31 | + | ||
32 | + /* | ||
33 | + * To keep things interesting, two buses bypass the IOMMU. | ||
34 | + * VIOT should only describes the other two buses. | ||
35 | + */ | ||
36 | + test_acpi_one("-machine default_bus_bypass_iommu=on " | ||
37 | + "-device virtio-iommu-pci " | ||
38 | + "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 " | ||
39 | + "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on " | ||
40 | + "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0", | ||
41 | + &data); | ||
42 | + free_test_data(&data); | ||
51 | +} | 43 | +} |
52 | + | 44 | + |
53 | +static int qbus_prereset(BusState *bus, void *opaque) | 45 | +static void test_acpi_virt_viot(void) |
54 | +{ | 46 | +{ |
55 | + trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus))); | 47 | + test_data data = { |
56 | + return 0; | 48 | + .machine = "virt", |
49 | + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", | ||
50 | + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", | ||
51 | + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", | ||
52 | + .ram_start = 0x40000000ULL, | ||
53 | + .scan_len = 128ULL * 1024 * 1024, | ||
54 | + }; | ||
55 | + | ||
56 | + test_acpi_one("-cpu cortex-a57 " | ||
57 | + "-device virtio-iommu-pci", &data); | ||
58 | + free_test_data(&data); | ||
57 | +} | 59 | +} |
58 | + | 60 | + |
59 | static int qdev_reset_one(DeviceState *dev, void *opaque) | 61 | static void test_oem_fields(test_data *data) |
60 | { | 62 | { |
61 | device_legacy_reset(dev); | 63 | int i; |
62 | @@ -XXX,XX +XXX,XX @@ static int qdev_reset_one(DeviceState *dev, void *opaque) | 64 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
63 | static int qbus_reset_one(BusState *bus, void *opaque) | 65 | qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); |
64 | { | 66 | qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); |
65 | BusClass *bc = BUS_GET_CLASS(bus); | 67 | } |
66 | + trace_qbus_reset(bus, object_get_typename(OBJECT(bus))); | 68 | + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); |
67 | if (bc->reset) { | 69 | } else if (strcmp(arch, "aarch64") == 0) { |
68 | bc->reset(bus); | 70 | if (has_tcg) { |
71 | qtest_add_func("acpi/virt", test_acpi_virt_tcg); | ||
72 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) | ||
73 | qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); | ||
74 | qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); | ||
75 | qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); | ||
76 | + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); | ||
77 | } | ||
69 | } | 78 | } |
70 | @@ -XXX,XX +XXX,XX @@ static int qbus_reset_one(BusState *bus, void *opaque) | 79 | ret = g_test_run(); |
71 | |||
72 | void qdev_reset_all(DeviceState *dev) | ||
73 | { | ||
74 | - qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); | ||
75 | + trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev))); | ||
76 | + qdev_walk_children(dev, qdev_prereset, qbus_prereset, | ||
77 | + qdev_reset_one, qbus_reset_one, NULL); | ||
78 | } | ||
79 | |||
80 | void qdev_reset_all_fn(void *opaque) | ||
81 | @@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque) | ||
82 | |||
83 | void qbus_reset_all(BusState *bus) | ||
84 | { | ||
85 | - qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); | ||
86 | + trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus))); | ||
87 | + qbus_walk_children(bus, qdev_prereset, qbus_prereset, | ||
88 | + qdev_reset_one, qbus_reset_one, NULL); | ||
89 | } | ||
90 | |||
91 | void qbus_reset_all_fn(void *opaque) | ||
92 | @@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev) | ||
93 | { | ||
94 | DeviceClass *klass = DEVICE_GET_CLASS(dev); | ||
95 | |||
96 | + trace_qdev_reset(dev, object_get_typename(OBJECT(dev))); | ||
97 | if (klass->reset) { | ||
98 | klass->reset(dev); | ||
99 | } | ||
100 | diff --git a/hw/core/trace-events b/hw/core/trace-events | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/hw/core/trace-events | ||
103 | +++ b/hw/core/trace-events | ||
104 | @@ -XXX,XX +XXX,XX @@ | ||
105 | # loader.c | ||
106 | loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d" | ||
107 | + | ||
108 | +# qdev.c | ||
109 | +qdev_reset(void *obj, const char *objtype) "obj=%p(%s)" | ||
110 | +qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)" | ||
111 | +qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" | ||
112 | +qbus_reset(void *obj, const char *objtype) "obj=%p(%s)" | ||
113 | +qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)" | ||
114 | +qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" | ||
115 | +qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" | ||
116 | -- | 80 | -- |
117 | 2.20.1 | 81 | 2.25.1 |
118 | 82 | ||
119 | 83 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | |
2 | |||
3 | Add expected blobs of the VIOT and DSDT table for the VIOT test on the | ||
4 | q35 machine. | ||
5 | |||
6 | Since the test instantiates a virtio device and two PCIe expander | ||
7 | bridges, DSDT.viot has more blocks than the base DSDT. | ||
8 | |||
9 | The VIOT table generated for the q35 test is: | ||
10 | |||
11 | [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] | ||
12 | [004h 0004 4] Table Length : 00000070 | ||
13 | [008h 0008 1] Revision : 00 | ||
14 | [009h 0009 1] Checksum : 3D | ||
15 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
16 | [010h 0016 8] Oem Table ID : "BXPC " | ||
17 | [018h 0024 4] Oem Revision : 00000001 | ||
18 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
19 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
20 | |||
21 | [024h 0036 2] Node count : 0003 | ||
22 | [026h 0038 2] Node offset : 0030 | ||
23 | [028h 0040 8] Reserved : 0000000000000000 | ||
24 | |||
25 | [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] | ||
26 | [031h 0049 1] Reserved : 00 | ||
27 | [032h 0050 2] Length : 0010 | ||
28 | |||
29 | [034h 0052 2] PCI Segment : 0000 | ||
30 | [036h 0054 2] PCI BDF number : 0010 | ||
31 | [038h 0056 8] Reserved : 0000000000000000 | ||
32 | |||
33 | [040h 0064 1] Type : 01 [PCI Range] | ||
34 | [041h 0065 1] Reserved : 00 | ||
35 | [042h 0066 2] Length : 0018 | ||
36 | |||
37 | [044h 0068 4] Endpoint start : 00003000 | ||
38 | [048h 0072 2] PCI Segment start : 0000 | ||
39 | [04Ah 0074 2] PCI Segment end : 0000 | ||
40 | [04Ch 0076 2] PCI BDF start : 3000 | ||
41 | [04Eh 0078 2] PCI BDF end : 30FF | ||
42 | [050h 0080 2] Output node : 0030 | ||
43 | [052h 0082 6] Reserved : 000000000000 | ||
44 | |||
45 | [058h 0088 1] Type : 01 [PCI Range] | ||
46 | [059h 0089 1] Reserved : 00 | ||
47 | [05Ah 0090 2] Length : 0018 | ||
48 | |||
49 | [05Ch 0092 4] Endpoint start : 00001000 | ||
50 | [060h 0096 2] PCI Segment start : 0000 | ||
51 | [062h 0098 2] PCI Segment end : 0000 | ||
52 | [064h 0100 2] PCI BDF start : 1000 | ||
53 | [066h 0102 2] PCI BDF end : 10FF | ||
54 | [068h 0104 2] Output node : 0030 | ||
55 | [06Ah 0106 6] Reserved : 000000000000 | ||
56 | |||
57 | And the DSDT diff is: | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | * | ||
61 | * Disassembling to symbolic ASL+ operators | ||
62 | * | ||
63 | - * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021 | ||
64 | + * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021 | ||
65 | * | ||
66 | * Original Table Header: | ||
67 | * Signature "DSDT" | ||
68 | - * Length 0x00002061 (8289) | ||
69 | + * Length 0x000024B6 (9398) | ||
70 | * Revision 0x01 **** 32-bit table (V1), no 64-bit math support | ||
71 | - * Checksum 0xFA | ||
72 | + * Checksum 0xA7 | ||
73 | * OEM ID "BOCHS " | ||
74 | * OEM Table ID "BXPC " | ||
75 | * OEM Revision 0x00000001 (1) | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | } | ||
78 | } | ||
79 | |||
80 | + Scope (\_SB) | ||
81 | + { | ||
82 | + Device (PC30) | ||
83 | + { | ||
84 | + Name (_UID, 0x30) // _UID: Unique ID | ||
85 | + Name (_BBN, 0x30) // _BBN: BIOS Bus Number | ||
86 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
87 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
88 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
89 | + { | ||
90 | + CreateDWordField (Arg3, Zero, CDW1) | ||
91 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
92 | + { | ||
93 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
94 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
95 | + Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */ | ||
96 | + Local0 &= 0x1F | ||
97 | + If ((Arg1 != One)) | ||
98 | + { | ||
99 | + CDW1 |= 0x08 | ||
100 | + } | ||
101 | + | ||
102 | + If ((CDW3 != Local0)) | ||
103 | + { | ||
104 | + CDW1 |= 0x10 | ||
105 | + } | ||
106 | + | ||
107 | + CDW3 = Local0 | ||
108 | + } | ||
109 | + Else | ||
110 | + { | ||
111 | + CDW1 |= 0x04 | ||
112 | + } | ||
113 | + | ||
114 | + Return (Arg3) | ||
115 | + } | ||
116 | + | ||
117 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
118 | + { | ||
119 | + Local0 = Package (0x80){} | ||
120 | + Local1 = Zero | ||
121 | + While ((Local1 < 0x80)) | ||
122 | + { | ||
123 | + Local2 = (Local1 >> 0x02) | ||
124 | + Local3 = ((Local1 + Local2) & 0x03) | ||
125 | + If ((Local3 == Zero)) | ||
126 | + { | ||
127 | + Local4 = Package (0x04) | ||
128 | + { | ||
129 | + Zero, | ||
130 | + Zero, | ||
131 | + LNKD, | ||
132 | + Zero | ||
133 | + } | ||
134 | + } | ||
135 | + | ||
136 | + If ((Local3 == One)) | ||
137 | + { | ||
138 | + Local4 = Package (0x04) | ||
139 | + { | ||
140 | + Zero, | ||
141 | + Zero, | ||
142 | + LNKA, | ||
143 | + Zero | ||
144 | + } | ||
145 | + } | ||
146 | + | ||
147 | + If ((Local3 == 0x02)) | ||
148 | + { | ||
149 | + Local4 = Package (0x04) | ||
150 | + { | ||
151 | + Zero, | ||
152 | + Zero, | ||
153 | + LNKB, | ||
154 | + Zero | ||
155 | + } | ||
156 | + } | ||
157 | + | ||
158 | + If ((Local3 == 0x03)) | ||
159 | + { | ||
160 | + Local4 = Package (0x04) | ||
161 | + { | ||
162 | + Zero, | ||
163 | + Zero, | ||
164 | + LNKC, | ||
165 | + Zero | ||
166 | + } | ||
167 | + } | ||
168 | + | ||
169 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
170 | + Local4 [One] = (Local1 & 0x03) | ||
171 | + Local0 [Local1] = Local4 | ||
172 | + Local1++ | ||
173 | + } | ||
174 | + | ||
175 | + Return (Local0) | ||
176 | + } | ||
177 | + | ||
178 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
179 | + { | ||
180 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
181 | + 0x0000, // Granularity | ||
182 | + 0x0030, // Range Minimum | ||
183 | + 0x0030, // Range Maximum | ||
184 | + 0x0000, // Translation Offset | ||
185 | + 0x0001, // Length | ||
186 | + ,, ) | ||
187 | + }) | ||
188 | + } | ||
189 | + } | ||
190 | + | ||
191 | + Scope (\_SB) | ||
192 | + { | ||
193 | + Device (PC20) | ||
194 | + { | ||
195 | + Name (_UID, 0x20) // _UID: Unique ID | ||
196 | + Name (_BBN, 0x20) // _BBN: BIOS Bus Number | ||
197 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
198 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
199 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
200 | + { | ||
201 | + CreateDWordField (Arg3, Zero, CDW1) | ||
202 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
203 | + { | ||
204 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
205 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
206 | + Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */ | ||
207 | + Local0 &= 0x1F | ||
208 | + If ((Arg1 != One)) | ||
209 | + { | ||
210 | + CDW1 |= 0x08 | ||
211 | + } | ||
212 | + | ||
213 | + If ((CDW3 != Local0)) | ||
214 | + { | ||
215 | + CDW1 |= 0x10 | ||
216 | + } | ||
217 | + | ||
218 | + CDW3 = Local0 | ||
219 | + } | ||
220 | + Else | ||
221 | + { | ||
222 | + CDW1 |= 0x04 | ||
223 | + } | ||
224 | + | ||
225 | + Return (Arg3) | ||
226 | + } | ||
227 | + | ||
228 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
229 | + { | ||
230 | + Local0 = Package (0x80){} | ||
231 | + Local1 = Zero | ||
232 | + While ((Local1 < 0x80)) | ||
233 | + { | ||
234 | + Local2 = (Local1 >> 0x02) | ||
235 | + Local3 = ((Local1 + Local2) & 0x03) | ||
236 | + If ((Local3 == Zero)) | ||
237 | + { | ||
238 | + Local4 = Package (0x04) | ||
239 | + { | ||
240 | + Zero, | ||
241 | + Zero, | ||
242 | + LNKD, | ||
243 | + Zero | ||
244 | + } | ||
245 | + } | ||
246 | + | ||
247 | + If ((Local3 == One)) | ||
248 | + { | ||
249 | + Local4 = Package (0x04) | ||
250 | + { | ||
251 | + Zero, | ||
252 | + Zero, | ||
253 | + LNKA, | ||
254 | + Zero | ||
255 | + } | ||
256 | + } | ||
257 | + | ||
258 | + If ((Local3 == 0x02)) | ||
259 | + { | ||
260 | + Local4 = Package (0x04) | ||
261 | + { | ||
262 | + Zero, | ||
263 | + Zero, | ||
264 | + LNKB, | ||
265 | + Zero | ||
266 | + } | ||
267 | + } | ||
268 | + | ||
269 | + If ((Local3 == 0x03)) | ||
270 | + { | ||
271 | + Local4 = Package (0x04) | ||
272 | + { | ||
273 | + Zero, | ||
274 | + Zero, | ||
275 | + LNKC, | ||
276 | + Zero | ||
277 | + } | ||
278 | + } | ||
279 | + | ||
280 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
281 | + Local4 [One] = (Local1 & 0x03) | ||
282 | + Local0 [Local1] = Local4 | ||
283 | + Local1++ | ||
284 | + } | ||
285 | + | ||
286 | + Return (Local0) | ||
287 | + } | ||
288 | + | ||
289 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
290 | + { | ||
291 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
292 | + 0x0000, // Granularity | ||
293 | + 0x0020, // Range Minimum | ||
294 | + 0x0020, // Range Maximum | ||
295 | + 0x0000, // Translation Offset | ||
296 | + 0x0001, // Length | ||
297 | + ,, ) | ||
298 | + }) | ||
299 | + } | ||
300 | + } | ||
301 | + | ||
302 | + Scope (\_SB) | ||
303 | + { | ||
304 | + Device (PC10) | ||
305 | + { | ||
306 | + Name (_UID, 0x10) // _UID: Unique ID | ||
307 | + Name (_BBN, 0x10) // _BBN: BIOS Bus Number | ||
308 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
309 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
310 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
311 | + { | ||
312 | + CreateDWordField (Arg3, Zero, CDW1) | ||
313 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
314 | + { | ||
315 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
316 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
317 | + Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */ | ||
318 | + Local0 &= 0x1F | ||
319 | + If ((Arg1 != One)) | ||
320 | + { | ||
321 | + CDW1 |= 0x08 | ||
322 | + } | ||
323 | + | ||
324 | + If ((CDW3 != Local0)) | ||
325 | + { | ||
326 | + CDW1 |= 0x10 | ||
327 | + } | ||
328 | + | ||
329 | + CDW3 = Local0 | ||
330 | + } | ||
331 | + Else | ||
332 | + { | ||
333 | + CDW1 |= 0x04 | ||
334 | + } | ||
335 | + | ||
336 | + Return (Arg3) | ||
337 | + } | ||
338 | + | ||
339 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
340 | + { | ||
341 | + Local0 = Package (0x80){} | ||
342 | + Local1 = Zero | ||
343 | + While ((Local1 < 0x80)) | ||
344 | + { | ||
345 | + Local2 = (Local1 >> 0x02) | ||
346 | + Local3 = ((Local1 + Local2) & 0x03) | ||
347 | + If ((Local3 == Zero)) | ||
348 | + { | ||
349 | + Local4 = Package (0x04) | ||
350 | + { | ||
351 | + Zero, | ||
352 | + Zero, | ||
353 | + LNKD, | ||
354 | + Zero | ||
355 | + } | ||
356 | + } | ||
357 | + | ||
358 | + If ((Local3 == One)) | ||
359 | + { | ||
360 | + Local4 = Package (0x04) | ||
361 | + { | ||
362 | + Zero, | ||
363 | + Zero, | ||
364 | + LNKA, | ||
365 | + Zero | ||
366 | + } | ||
367 | + } | ||
368 | + | ||
369 | + If ((Local3 == 0x02)) | ||
370 | + { | ||
371 | + Local4 = Package (0x04) | ||
372 | + { | ||
373 | + Zero, | ||
374 | + Zero, | ||
375 | + LNKB, | ||
376 | + Zero | ||
377 | + } | ||
378 | + } | ||
379 | + | ||
380 | + If ((Local3 == 0x03)) | ||
381 | + { | ||
382 | + Local4 = Package (0x04) | ||
383 | + { | ||
384 | + Zero, | ||
385 | + Zero, | ||
386 | + LNKC, | ||
387 | + Zero | ||
388 | + } | ||
389 | + } | ||
390 | + | ||
391 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
392 | + Local4 [One] = (Local1 & 0x03) | ||
393 | + Local0 [Local1] = Local4 | ||
394 | + Local1++ | ||
395 | + } | ||
396 | + | ||
397 | + Return (Local0) | ||
398 | + } | ||
399 | + | ||
400 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
401 | + { | ||
402 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
403 | + 0x0000, // Granularity | ||
404 | + 0x0010, // Range Minimum | ||
405 | + 0x0010, // Range Maximum | ||
406 | + 0x0000, // Translation Offset | ||
407 | + 0x0001, // Length | ||
408 | + ,, ) | ||
409 | + }) | ||
410 | + } | ||
411 | + } | ||
412 | + | ||
413 | Scope (\_SB.PCI0) | ||
414 | { | ||
415 | Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
416 | @@ -XXX,XX +XXX,XX @@ | ||
417 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
418 | 0x0000, // Granularity | ||
419 | 0x0000, // Range Minimum | ||
420 | - 0x00FF, // Range Maximum | ||
421 | + 0x000F, // Range Maximum | ||
422 | 0x0000, // Translation Offset | ||
423 | - 0x0100, // Length | ||
424 | + 0x0010, // Length | ||
425 | ,, ) | ||
426 | IO (Decode16, | ||
427 | 0x0CF8, // Range Minimum | ||
428 | @@ -XXX,XX +XXX,XX @@ | ||
429 | } | ||
430 | } | ||
431 | |||
432 | + Device (S10) | ||
433 | + { | ||
434 | + Name (_ADR, 0x00020000) // _ADR: Address | ||
435 | + } | ||
436 | + | ||
437 | + Device (S18) | ||
438 | + { | ||
439 | + Name (_ADR, 0x00030000) // _ADR: Address | ||
440 | + } | ||
441 | + | ||
442 | + Device (S20) | ||
443 | + { | ||
444 | + Name (_ADR, 0x00040000) // _ADR: Address | ||
445 | + } | ||
446 | + | ||
447 | + Device (S28) | ||
448 | + { | ||
449 | + Name (_ADR, 0x00050000) // _ADR: Address | ||
450 | + } | ||
451 | + | ||
452 | Method (PCNT, 0, NotSerialized) | ||
453 | { | ||
454 | } | ||
455 | |||
456 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
457 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
458 | Message-id: 20211210170415.583179-8-jean-philippe@linaro.org | ||
459 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
460 | --- | ||
461 | tests/qtest/bios-tables-test-allowed-diff.h | 2 -- | ||
462 | tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes | ||
463 | tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes | ||
464 | 3 files changed, 2 deletions(-) | ||
465 | |||
466 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
467 | index XXXXXXX..XXXXXXX 100644 | ||
468 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
469 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
470 | @@ -XXX,XX +XXX,XX @@ | ||
471 | /* List of comma-separated changed AML files to ignore */ | ||
472 | "tests/data/acpi/virt/VIOT", | ||
473 | -"tests/data/acpi/q35/DSDT.viot", | ||
474 | -"tests/data/acpi/q35/VIOT.viot", | ||
475 | diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot | ||
476 | index XXXXXXX..XXXXXXX 100644 | ||
477 | GIT binary patch | ||
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544 | |||
545 | literal 0 | ||
546 | HcmV?d00001 | ||
547 | |||
548 | diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot | ||
549 | index XXXXXXX..XXXXXXX 100644 | ||
550 | GIT binary patch | ||
551 | literal 112 | ||
552 | zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj | ||
553 | Q0Zb)W9Hva*zW_`e0M!8s0RR91 | ||
554 | |||
555 | literal 0 | ||
556 | HcmV?d00001 | ||
557 | |||
558 | -- | ||
559 | 2.25.1 | ||
560 | |||
561 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Since we enabled parallel TCG code generation for softmmu (see | 3 | The VIOT blob contains the following: |
4 | commit 3468b59 "tcg: enable multiple TCG contexts in softmmu") | ||
5 | and its subsequent fix (commit 72649619 "add .min_cpus and | ||
6 | .default_cpus fields to machine_class"), the raspi machines are | ||
7 | restricted to always use their 4 cores: | ||
8 | 4 | ||
9 | See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4): | 5 | [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] |
6 | [004h 0004 4] Table Length : 00000058 | ||
7 | [008h 0008 1] Revision : 00 | ||
8 | [009h 0009 1] Checksum : 66 | ||
9 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
10 | [010h 0016 8] Oem Table ID : "BXPC " | ||
11 | [018h 0024 4] Oem Revision : 00000001 | ||
12 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
13 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
10 | 14 | ||
11 | 222 static void raspi2_machine_init(MachineClass *mc) | 15 | [024h 0036 2] Node count : 0002 |
12 | 223 { | 16 | [026h 0038 2] Node offset : 0030 |
13 | 224 mc->desc = "Raspberry Pi 2"; | 17 | [028h 0040 8] Reserved : 0000000000000000 |
14 | 230 mc->max_cpus = BCM283X_NCPUS; | ||
15 | 231 mc->min_cpus = BCM283X_NCPUS; | ||
16 | 232 mc->default_cpus = BCM283X_NCPUS; | ||
17 | 235 }; | ||
18 | 236 DEFINE_MACHINE("raspi2", raspi2_machine_init) | ||
19 | 18 | ||
20 | We can no longer use the -smp option, as we get: | 19 | [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] |
20 | [031h 0049 1] Reserved : 00 | ||
21 | [032h 0050 2] Length : 0010 | ||
21 | 22 | ||
22 | $ qemu-system-arm -M raspi2 -smp 1 | 23 | [034h 0052 2] PCI Segment : 0000 |
23 | qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4 | 24 | [036h 0054 2] PCI BDF number : 0008 |
25 | [038h 0056 8] Reserved : 0000000000000000 | ||
24 | 26 | ||
25 | Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp, | 27 | [040h 0064 1] Type : 01 [PCI Range] |
26 | remove the unuseful code. | 28 | [041h 0065 1] Reserved : 00 |
29 | [042h 0066 2] Length : 0018 | ||
27 | 30 | ||
28 | We can achieve the same by using the '-global bcm2836.enabled-cpus=1' | 31 | [044h 0068 4] Endpoint start : 00000000 |
29 | option. | 32 | [048h 0072 2] PCI Segment start : 0000 |
33 | [04Ah 0074 2] PCI Segment end : 0000 | ||
34 | [04Ch 0076 2] PCI BDF start : 0000 | ||
35 | [04Eh 0078 2] PCI BDF end : 00FF | ||
36 | [050h 0080 2] Output node : 0030 | ||
37 | [052h 0082 6] Reserved : 000000000000 | ||
30 | 38 | ||
31 | Reported-by: Laurent Bonnans <laurent.bonnans@here.com> | 39 | Acked-by: Ani Sinha <ani@anisinha.ca> |
32 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 40 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
33 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 41 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
34 | Message-id: 20200120235159.18510-2-f4bug@amsat.org | 42 | Message-id: 20211210170415.583179-9-jean-philippe@linaro.org |
35 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 43 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
36 | --- | 44 | --- |
37 | hw/arm/raspi.c | 2 -- | 45 | tests/qtest/bios-tables-test-allowed-diff.h | 1 - |
38 | 1 file changed, 2 deletions(-) | 46 | tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes |
47 | 2 files changed, 1 deletion(-) | ||
39 | 48 | ||
40 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 49 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h |
41 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/hw/arm/raspi.c | 51 | --- a/tests/qtest/bios-tables-test-allowed-diff.h |
43 | +++ b/hw/arm/raspi.c | 52 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h |
44 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | 53 | @@ -1,2 +1 @@ |
45 | /* Setup the SOC */ | 54 | /* List of comma-separated changed AML files to ignore */ |
46 | object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), | 55 | -"tests/data/acpi/virt/VIOT", |
47 | &error_abort); | 56 | diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT |
48 | - object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus", | 57 | index XXXXXXX..XXXXXXX 100644 |
49 | - &error_abort); | 58 | GIT binary patch |
50 | int board_rev = version == 3 ? 0xa02082 : 0xa21041; | 59 | literal 88 |
51 | object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", | 60 | zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX |
52 | &error_abort); | 61 | I{D-Rq0Q5fy0RR91 |
62 | |||
63 | literal 0 | ||
64 | HcmV?d00001 | ||
65 | |||
53 | -- | 66 | -- |
54 | 2.20.1 | 67 | 2.25.1 |
55 | 68 | ||
56 | 69 | diff view generated by jsdifflib |