Series comparison

-[PULL 00/26] target-arm queue
+[PULL 00/24] target-arm queue
-target-arm queue. The big thing here is the landing of the 3-phase
+The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
 reset patches...
--- PMM
+  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
 The following changes since commit 204aa60b37c23a89e690d418f49787d274303ca7:
   Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging (2020-01-30 14:18:45 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200130
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
-for you to fetch changes up to dea101a1ae9968c9fec6ab0291489dad7c49f36f:
+for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
-  target/arm/cpu: Add the kvm-no-adjvtime CPU property (2020-01-30 16:02:06 +0000)
+  target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
+ * more MVE instructions
- * target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
+ * hw/gpio/gpio_pwr: use shutdown function for reboot
- * aspeed: some minor bugfixes
+ * target/arm: Check NaN mode before silencing NaN
- * aspeed: add eMMC controller model for AST2600 SoC
+ * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
- * hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
+ * hw/arm: Add basic power management to raspi.
- * New 3-phase reset API for device models
+ * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
  * hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
  * Arm KVM: stop/restart the guest counter when the VM is stopped and started
 ----------------------------------------------------------------
-Andrew Jeffery (2):
+Joe Komlodi (1):
-      hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
+      target/arm: Check NaN mode before silencing NaN
       hw/arm: ast2600: Wire up the eMMC controller
-Andrew Jones (6):
+Maxim Uvarov (1):
-      target/arm/kvm: trivial: Clean up header documentation
+      hw/gpio/gpio_pwr: use shutdown function for reboot
       hw/arm/virt: Add missing 5.0 options call to 4.2 options
       target/arm/kvm64: kvm64 cpus have timer registers
       tests/arm-cpu-features: Check feature default values
       target/arm/kvm: Implement virtual time adjustment
       target/arm/cpu: Add the kvm-no-adjvtime CPU property
-Cédric Le Goater (2):
+Nolan Leake (1):
-      ftgmac100: check RX and TX buffer alignment
+      hw/arm: Add basic power management to raspi.
       hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0
-Damien Hedde (11):
+Patrick Venture (2):
-      add device_legacy_reset function to prepare for reset api change
+      docs/system/arm: Add quanta-q7l1-bmc reference
-      hw/core/qdev: add trace events to help with resettable transition
+      docs/system/arm: Add quanta-gbs-bmc reference
       hw/core: create Resettable QOM interface
       hw/core: add Resettable support to BusClass and DeviceClass
       hw/core/resettable: add support for changing parent
       hw/core/qdev: handle parent bus change regarding resettable
       hw/core/qdev: update hotplug reset regarding resettable
       hw/core: deprecate old reset functions and introduce new ones
       docs/devel/reset.rst: add doc about Resettable interface
       vl: replace deprecated qbus_reset_all registration
       hw/s390x/ipl: replace deprecated qdev_reset_all registration
-Joel Stanley (1):
+Peter Maydell (18):
-      misc/pca9552: Add qom set and get
+      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
-Peter Maydell (2):
+      target/arm: Make asimd_imm_const() public
-      hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
+      target/arm: Use asimd_imm_const for A64 decode
-      target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
+      target/arm: Use dup_const() instead of bitfield_replicate()
       target/arm: Implement MVE logical immediate insns
       target/arm: Implement MVE vector shift left by immediate insns
       target/arm: Implement MVE vector shift right by immediate insns
       target/arm: Implement MVE VSHLL
       target/arm: Implement MVE VSRI, VSLI
       target/arm: Implement MVE VSHRN, VRSHRN
       target/arm: Implement MVE saturating narrowing shifts
       target/arm: Implement MVE VSHLC
       target/arm: Implement MVE VADDLV
       target/arm: Implement MVE long shifts by immediate
       target/arm: Implement MVE long shifts by register
       target/arm: Implement MVE shifts by immediate
       target/arm: Implement MVE shifts by register
 Philippe Mathieu-Daudé (1):
-      hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
+      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
-Zenghui Yu (1):
+ docs/system/arm/aspeed.rst             |   1 +
-      hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
+ docs/system/arm/nuvoton.rst            |   5 +-
  include/hw/arm/bcm2835_peripherals.h   |   3 +-
  include/hw/misc/bcm2835_powermgt.h     |  29 ++
  target/arm/helper-mve.h                | 108 +++++++
  target/arm/translate.h                 |  41 +++
  target/arm/mve.decode                  | 177 ++++++++++-
  target/arm/t32.decode                  |  71 ++++-
  hw/arm/bcm2835_peripherals.c           |  13 +-
  hw/gpio/gpio_pwr.c                     |   2 +-
  hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
  target/arm/helper-a64.c                |  12 +-
  target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
  target/arm/translate-a64.c             |  86 +-----
  target/arm/translate-mve.c             | 261 +++++++++++++++-
  target/arm/translate-neon.c            |  81 -----
  target/arm/translate.c                 | 327 +++++++++++++++++++-
  target/arm/vfp_helper.c                |  24 +-
  hw/misc/meson.build                    |   1 +
  tests/acceptance/boot_linux_console.py |  43 +++
 files changed, 1760 insertions(+), 209 deletions(-)
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
- hw/core/Makefile.objs          |   1 +
- tests/Makefile.include         |   1 +
- include/hw/arm/aspeed.h        |   2 +
- include/hw/arm/aspeed_soc.h    |   2 +
- include/hw/arm/virt.h          |   1 +
- include/hw/qdev-core.h         |  58 +++++++-
- include/hw/resettable.h        | 247 +++++++++++++++++++++++++++++++++
- include/hw/sd/aspeed_sdhci.h   |   1 +
- target/arm/cpu.h               |   7 +
- target/arm/kvm_arm.h           |  95 ++++++++++---
- hw/arm/aspeed.c                |  72 ++++++++--
- hw/arm/aspeed_ast2600.c        |  31 ++++-
- hw/arm/aspeed_soc.c            |   2 +
- hw/arm/raspi.c                 |   2 -
- hw/arm/virt.c                  |   9 ++
- hw/audio/intel-hda.c           |   2 +-
- hw/core/bus.c                  | 102 ++++++++++++++
- hw/core/or-irq.c               |   2 +-
- hw/core/qdev.c                 | 160 ++++++++++++++++++++--
- hw/core/resettable.c           | 301 +++++++++++++++++++++++++++++++++++++++++
- hw/hyperv/hyperv.c             |   2 +-
- hw/i386/microvm.c              |   2 +-
- hw/i386/pc.c                   |   2 +-
- hw/ide/microdrive.c            |   8 +-
- hw/intc/arm_gicv3_kvm.c        |  11 +-
- hw/intc/spapr_xive.c           |   2 +-
- hw/misc/pca9552.c              |  90 ++++++++++++
- hw/net/ftgmac100.c             |  13 ++
- hw/ppc/pnv_psi.c               |   4 +-
- hw/ppc/spapr_pci.c             |   2 +-
- hw/ppc/spapr_vio.c             |   2 +-
- hw/s390x/ipl.c                 |  10 +-
- hw/s390x/s390-pci-inst.c       |   2 +-
- hw/scsi/vmw_pvscsi.c           |   2 +-
- hw/sd/aspeed_sdhci.c           |  11 +-
- hw/sd/omap_mmc.c               |   2 +-
- hw/sd/pl181.c                  |   2 +-
- target/arm/arm-semi.c          |   9 ++
- target/arm/cpu.c               |   2 +
- target/arm/cpu64.c             |   1 +
- target/arm/kvm.c               | 120 ++++++++++++++++
- target/arm/kvm32.c             |   3 +
- target/arm/kvm64.c             |   4 +
- target/arm/machine.c           |   7 +
- target/arm/monitor.c           |   1 +
- tests/qtest/arm-cpu-features.c |  41 ++++--
- vl.c                           |  10 +-
- docs/arm-cpu-features.rst      |  37 ++++-
- docs/devel/index.rst           |   1 +
- docs/devel/reset.rst           | 289 +++++++++++++++++++++++++++++++++++++++
- hw/core/trace-events           |  27 ++++
-files changed, 1727 insertions(+), 90 deletions(-)
- create mode 100644 include/hw/resettable.h
- create mode 100644 hw/core/resettable.c
- create mode 100644 docs/devel/reset.rst

-[PULL 23/26] target/arm/kvm64: kvm64 cpus have timer registers
+[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
-From: Andrew Jones <drjones@redhat.com>
+From: Patrick Venture <venture@google.com>
-Add the missing GENERIC_TIMER feature to kvm64 cpus.
+Adds a line-item reference to the supported quanta-q71l-bmc aspeed
 entry.
-We don't currently use these registers when KVM is enabled, but it's
+Signed-off-by: Patrick Venture <venture@google.com>
-probably best we add the feature flag for consistency and potential
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
-future use. There's also precedent, as we add the PMU feature flag to
+Message-id: 20210615192848.1065297-2-venture@google.com
 KVM enabled guests, even though we don't use those registers either.
 This change was originally posted as a hunk of a different, never
 merged patch from Bijan Mottahedeh.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200120101023.16030-4-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/kvm64.c | 1 +
+ docs/system/arm/aspeed.rst | 1 +
 file changed, 1 insertion(+)
-diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
+diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm64.c
+--- a/docs/system/arm/aspeed.rst
-+++ b/target/arm/kvm64.c
++++ b/docs/system/arm/aspeed.rst
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
+@@ -XXX,XX +XXX,XX @@ etc.
-     set_feature(&features, ARM_FEATURE_NEON);
+ AST2400 SoC based machines :
-     set_feature(&features, ARM_FEATURE_AARCH64);
-     set_feature(&features, ARM_FEATURE_PMU);
+ - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
-+    set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
++- ``quanta-q71l-bmc``      OpenBMC Quanta BMC
-     ahcf->features = features;
+ AST2500 SoC based machines :
 --
 .20.1

-[PULL 24/26] tests/arm-cpu-features: Check feature default values
+[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
-From: Andrew Jones <drjones@redhat.com>
+From: Patrick Venture <venture@google.com>
-If we know what the default value should be then we can test for
+Add line item reference to quanta-gbs-bmc machine.
 that as well as the feature existence.
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+Signed-off-by: Patrick Venture <venture@google.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20200120101023.16030-5-drjones@redhat.com
+Message-id: 20210615192848.1065297-3-venture@google.com
 [PMM: fixed underline Sphinx warning]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/arm-cpu-features.c | 37 +++++++++++++++++++++++++---------
+ docs/system/arm/nuvoton.rst | 5 +++--
-file changed, 28 insertions(+), 9 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/arm-cpu-features.c
+--- a/docs/system/arm/nuvoton.rst
-+++ b/tests/qtest/arm-cpu-features.c
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature)
+@@ -XXX,XX +XXX,XX @@
-     qobject_unref(_resp);                                              \
+-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
- })
+-=====================================================
++Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
-+#define assert_feature(qts, cpu_type, feature, expected_value)         \
++================================================================
-+({                                                                     \
-+    QDict *_resp, *_props;                                             \
+ The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
-+                                                                       \
+ designed to be used as Baseboard Management Controllers (BMCs) in various
-+    _resp = do_query_no_props(qts, cpu_type);                          \
+@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
-+    g_assert(_resp);                                                   \
+ The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
-+    g_assert(resp_has_props(_resp));                                   \
+ Hyperscale applications. The following machines are based on this chip :
-+    _props = resp_get_props(_resp);                                    \
-+    g_assert(qdict_get(_props, feature));                              \
++- ``quanta-gbs-bmc``    Quanta GBS server BMC
-+    g_assert(qdict_get_bool(_props, feature) == (expected_value));     \
+ - ``quanta-gsj``        Quanta GSJ server BMC
-+    qobject_unref(_resp);                                              \
-+})
+ There are also two more SoCs, NPCM710 and NPCM705, which are single-core
 +
 +#define assert_has_feature_enabled(qts, cpu_type, feature)             \
 +    assert_feature(qts, cpu_type, feature, true)
 +
 +#define assert_has_feature_disabled(qts, cpu_type, feature)            \
 +    assert_feature(qts, cpu_type, feature, false)
 +
  static void assert_type_full(QTestState *qts)
  {
      const char *error;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
      assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
      /* Test expected feature presence/absence for some cpu types */
 -    assert_has_feature(qts, "max", "pmu");
 -    assert_has_feature(qts, "cortex-a15", "pmu");
 +    assert_has_feature_enabled(qts, "max", "pmu");
 +    assert_has_feature_enabled(qts, "cortex-a15", "pmu");
      assert_has_not_feature(qts, "cortex-a15", "aarch64");
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
 -        assert_has_feature(qts, "max", "aarch64");
 -        assert_has_feature(qts, "max", "sve");
 -        assert_has_feature(qts, "max", "sve128");
 -        assert_has_feature(qts, "cortex-a57", "pmu");
 -        assert_has_feature(qts, "cortex-a57", "aarch64");
 +        assert_has_feature_enabled(qts, "max", "aarch64");
 +        assert_has_feature_enabled(qts, "max", "sve");
 +        assert_has_feature_enabled(qts, "max", "sve128");
 +        assert_has_feature_enabled(qts, "cortex-a57", "pmu");
 +        assert_has_feature_enabled(qts, "cortex-a57", "aarch64");
          sve_tests_default(qts, "max");
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
          QDict *resp;
          char *error;
 -        assert_has_feature(qts, "host", "aarch64");
 -        assert_has_feature(qts, "host", "pmu");
 +        assert_has_feature_enabled(qts, "host", "aarch64");
 +        assert_has_feature_enabled(qts, "host", "pmu");
          assert_error(qts, "cortex-a15",
              "We cannot guarantee the CPU type 'cortex-a15' works "
 --
 .20.1

-[PULL 11/26] hw/core: create Resettable QOM interface
+[PULL 03/24] hw/arm: Add basic power management to raspi.
-From: Damien Hedde <damien.hedde@greensocs.com>
+From: Nolan Leake <nolan@sigbus.net>
-This commit defines an interface allowing multi-phase reset. This aims
+This is just enough to make reboot and poweroff work. Works for
-to solve a problem of the actual single-phase reset (built in
+linux, u-boot, and the arm trusted firmware. Not tested, but should
-DeviceClass and BusClass): reset behavior is dependent on the order
+work for plan9, and bare-metal/hobby OSes, since they seem to generally
-in which reset handlers are called. In particular doing external
+do what linux does for reset.
-side-effect (like setting an qemu_irq) is problematic because receiving
-object may not be reset yet.
+The watchdog timer functionality is not yet implemented.
-The Resettable interface divides the reset in 3 well defined phases.
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
-To reset an object tree, all 1st phases are executed then all 2nd then
+Signed-off-by: Nolan Leake <nolan@sigbus.net>
-all 3rd. See the comments in include/hw/resettable.h for a more complete
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-description. The interface defines 3 phases to let the future
+Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-possibility of holding an object into reset for some time.
+Message-id: 20210625210209.1870217-1-nolan@sigbus.net
+[PMM: tweaked commit title; fixed region size to 0x200;
-The qdev/qbus reset in DeviceClass and BusClass will be modified in
+ moved header file to include/]
 following commits to use this interface. A mechanism is provided
 to allow executing a transitional reset handler in place of the 2nd
 phase which is executed in children-then-parent order inside a tree.
 This will allow to transition devices and buses smoothly while
 keeping the exact current qdev/qbus reset behavior for now.
 Documentation will be added in a following commit.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/core/Makefile.objs   |   1 +
+ include/hw/arm/bcm2835_peripherals.h |   3 +-
- include/hw/resettable.h | 211 +++++++++++++++++++++++++++++++++++
+ include/hw/misc/bcm2835_powermgt.h   |  29 +++++
- hw/core/resettable.c    | 238 ++++++++++++++++++++++++++++++++++++++++
+ hw/arm/bcm2835_peripherals.c         |  13 ++-
- hw/core/trace-events    |  17 +++
+ hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
-files changed, 467 insertions(+)
+ hw/misc/meson.build                  |   1 +
- create mode 100644 include/hw/resettable.h
+files changed, 204 insertions(+), 2 deletions(-)
- create mode 100644 hw/core/resettable.c
+ create mode 100644 include/hw/misc/bcm2835_powermgt.h
+ create mode 100644 hw/misc/bcm2835_powermgt.c
-diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/Makefile.objs
+--- a/include/hw/arm/bcm2835_peripherals.h
-+++ b/hw/core/Makefile.objs
++++ b/include/hw/arm/bcm2835_peripherals.h
 @@ -XXX,XX +XXX,XX @@
- common-obj-y += qdev.o qdev-properties.o
+ #include "hw/misc/bcm2835_mphi.h"
- common-obj-y += bus.o
+ #include "hw/misc/bcm2835_thermal.h"
- common-obj-y += cpu.o
+ #include "hw/misc/bcm2835_cprman.h"
-+common-obj-y += resettable.o
++#include "hw/misc/bcm2835_powermgt.h"
- common-obj-y += hotplug.o
+ #include "hw/sd/sdhci.h"
- common-obj-y += vmstate-if.o
+ #include "hw/sd/bcm2835_sdhost.h"
- # irq.o needed for qdev GPIO handling:
+ #include "hw/gpio/bcm2835_gpio.h"
-diff --git a/include/hw/resettable.h b/include/hw/resettable.h
+@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
      BCM2835MphiState mphi;
      UnimplementedDeviceState txp;
      UnimplementedDeviceState armtmr;
 -    UnimplementedDeviceState powermgt;
 +    BCM2835PowerMgtState powermgt;
      BCM2835CprmanState cprman;
      PL011State uart0;
      BCM2835AuxState aux;
 diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/resettable.h
++++ b/include/hw/misc/bcm2835_powermgt.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Resettable interface header.
++ * BCM2835 Power Management emulation
 + *
-+ * Copyright (c) 2019 GreenSocs SAS
++ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
-+ *
++ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
 + * Authors:
 + *   Damien Hedde
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
-+#ifndef HW_RESETTABLE_H
++#ifndef BCM2835_POWERMGT_H
-+#define HW_RESETTABLE_H
++#define BCM2835_POWERMGT_H
 +
 +#include "hw/sysbus.h"
 +#include "qom/object.h"
 +
-+#define TYPE_RESETTABLE_INTERFACE "resettable"
++#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
-+
++OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
-+#define RESETTABLE_CLASS(class) \
++
-+    OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE_INTERFACE)
++struct BCM2835PowerMgtState {
-+
++    SysBusDevice busdev;
-+#define RESETTABLE_GET_CLASS(obj) \
++    MemoryRegion iomem;
-+    OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE)
++
-+
++    uint32_t rstc;
-+typedef struct ResettableState ResettableState;
++    uint32_t rsts;
-+
++    uint32_t wdog;
-+/**
++};
 + * ResetType:
 + * Types of reset.
 + *
 + * + Cold: reset resulting from a power cycle of the object.
 + *
 + * TODO: Support has to be added to handle more types. In particular,
 + * ResettableState structure needs to be expanded.
 + */
 +typedef enum ResetType {
 +    RESET_TYPE_COLD,
 +} ResetType;
 +
 +/*
 + * ResettableClass:
 + * Interface for resettable objects.
 + *
 + * See docs/devel/reset.rst for more detailed information about how QEMU models
 + * reset. This whole API must only be used when holding the iothread mutex.
 + *
 + * All objects which can be reset must implement this interface;
 + * it is usually provided by a base class such as DeviceClass or BusClass.
 + * Every Resettable object must maintain some state tracking the
 + * progress of a reset operation by providing a ResettableState structure.
 + * The functions defined in this module take care of updating the
 + * state of the reset.
 + * The base class implementation of the interface provides this
 + * state and implements the associated method: get_state.
 + *
 + * Concrete object implementations (typically specific devices
 + * such as a UART model) should provide the functions
 + * for the phases.enter, phases.hold and phases.exit methods, which
 + * they can set in their class init function, either directly or
 + * by calling resettable_class_set_parent_phases().
 + * The phase methods are guaranteed to only only ever be called once
 + * for any reset event, in the order 'enter', 'hold', 'exit'.
 + * An object will always move quickly from 'enter' to 'hold'
 + * but might remain in 'hold' for an arbitrary period of time
 + * before eventually reset is deasserted and the 'exit' phase is called.
 + * Object implementations should be prepared for functions handling
 + * inbound connections from other devices (such as qemu_irq handler
 + * functions) to be called at any point during reset after their
 + * 'enter' method has been called.
 + *
 + * Users of a resettable object should not call these methods
 + * directly, but instead use the function resettable_reset().
 + *
 + * @phases.enter: This phase is called when the object enters reset. It
 + * should reset local state of the object, but it must not do anything that
 + * has a side-effect on other objects, such as raising or lowering a qemu_irq
 + * line or reading or writing guest memory. It takes the reset's type as
 + * argument.
 + *
 + * @phases.hold: This phase is called for entry into reset, once every object
 + * in the system which is being reset has had its @phases.enter method called.
 + * At this point devices can do actions that affect other objects.
 + *
 + * @phases.exit: This phase is called when the object leaves the reset state.
 + * Actions affecting other objects are permitted.
 + *
 + * @get_state: Mandatory method which must return a pointer to a
 + * ResettableState.
 + *
 + * @get_transitional_function: transitional method to handle Resettable objects
 + * not yet fully moved to this interface. It will be removed as soon as it is
 + * not needed anymore. This method is optional and may return a pointer to a
 + * function to be used instead of the phases. If the method exists and returns
 + * a non-NULL function pointer then that function is executed as a replacement
 + * of the 'hold' phase method taking the object as argument. The two other phase
 + * methods are not executed.
 + *
 + * @child_foreach: Executes a given callback on every Resettable child. Child
 + * in this context means a child in the qbus tree, so the children of a qbus
 + * are the devices on it, and the children of a device are all the buses it
 + * owns. This is not the same as the QOM object hierarchy. The function takes
 + * additional opaque and ResetType arguments which must be passed unmodified to
 + * the callback.
 + */
 +typedef void (*ResettableEnterPhase)(Object *obj, ResetType type);
 +typedef void (*ResettableHoldPhase)(Object *obj);
 +typedef void (*ResettableExitPhase)(Object *obj);
 +typedef ResettableState * (*ResettableGetState)(Object *obj);
 +typedef void (*ResettableTrFunction)(Object *obj);
 +typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj);
 +typedef void (*ResettableChildCallback)(Object *, void *opaque,
 +                                        ResetType type);
 +typedef void (*ResettableChildForeach)(Object *obj,
 +                                       ResettableChildCallback cb,
 +                                       void *opaque, ResetType type);
 +typedef struct ResettablePhases {
 +    ResettableEnterPhase enter;
 +    ResettableHoldPhase hold;
 +    ResettableExitPhase exit;
 +} ResettablePhases;
 +typedef struct ResettableClass {
 +    InterfaceClass parent_class;
 +
 +    /* Phase methods */
 +    ResettablePhases phases;
 +
 +    /* State access method */
 +    ResettableGetState get_state;
 +
 +    /* Transitional method for legacy reset compatibility */
 +    ResettableGetTrFunction get_transitional_function;
 +
 +    /* Hierarchy handling method */
 +    ResettableChildForeach child_foreach;
 +} ResettableClass;
 +
 +/**
 + * ResettableState:
 + * Structure holding reset related state. The fields should not be accessed
 + * directly; the definition is here to allow further inclusion into other
 + * objects.
 + *
 + * @count: Number of reset level the object is into. It is incremented when
 + * the reset operation starts and decremented when it finishes.
 + * @hold_phase_pending: flag which indicates that we need to invoke the 'hold'
 + * phase handler for this object.
 + * @exit_phase_in_progress: true if we are currently in the exit phase
 + */
 +struct ResettableState {
 +    unsigned count;
 +    bool hold_phase_pending;
 +    bool exit_phase_in_progress;
 +};
 +
 +/**
 + * resettable_reset:
 + * Trigger a reset on an object @obj of type @type. @obj must implement
 + * Resettable interface.
 + *
 + * Calling this function is equivalent to calling @resettable_assert_reset()
 + * then @resettable_release_reset().
 + */
 +void resettable_reset(Object *obj, ResetType type);
 +
 +/**
 + * resettable_assert_reset:
 + * Put an object @obj into reset. @obj must implement Resettable interface.
 + *
 + * @resettable_release_reset() must eventually be called after this call.
 + * There must be one call to @resettable_release_reset() per call of
 + * @resettable_assert_reset(), with the same type argument.
 + *
 + * NOTE: Until support for migration is added, the @resettable_release_reset()
 + * must not be delayed. It must occur just after @resettable_assert_reset() so
 + * that migration cannot be triggered in between. Prefer using
 + * @resettable_reset() for now.
 + */
 +void resettable_assert_reset(Object *obj, ResetType type);
 +
 +/**
 + * resettable_release_reset:
 + * Release the object @obj from reset. @obj must implement Resettable interface.
 + *
 + * See @resettable_assert_reset() description for details.
 + */
 +void resettable_release_reset(Object *obj, ResetType type);
 +
 +/**
 + * resettable_is_in_reset:
 + * Return true if @obj is under reset.
 + *
 + * @obj must implement Resettable interface.
 + */
 +bool resettable_is_in_reset(Object *obj);
 +
 +/**
 + * resettable_class_set_parent_phases:
 + *
 + * Save @rc current reset phases into @parent_phases and override @rc phases
 + * by the given new methods (@enter, @hold and @exit).
 + * Each phase is overridden only if the new one is not NULL allowing to
 + * override a subset of phases.
 + */
 +void resettable_class_set_parent_phases(ResettableClass *rc,
 +                                        ResettableEnterPhase enter,
 +                                        ResettableHoldPhase hold,
 +                                        ResettableExitPhase exit,
 +                                        ResettablePhases *parent_phases);
 +
 +#endif
-diff --git a/hw/core/resettable.c b/hw/core/resettable.c
+diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2835_peripherals.c
 +++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
      object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                     OBJECT(&s->gpu_bus_mr));
 +
 +    /* Power Management */
 +    object_initialize_child(obj, "powermgt", &s->powermgt,
 +                            TYPE_BCM2835_POWERMGT);
  }
  static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
          qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                 INTERRUPT_USB));
 +    /* Power Management */
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
 +        return;
 +    }
 +
 +    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
 +                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
 +
      create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
      create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
 -    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
      create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
      create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
      create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
 diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/core/resettable.c
++++ b/hw/misc/bcm2835_powermgt.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Resettable interface.
++ * BCM2835 Power Management emulation
 + *
-+ * Copyright (c) 2019 GreenSocs SAS
++ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
-+ *
++ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
 + * Authors:
 + *   Damien Hedde
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
++#include "qemu/log.h"
 +#include "qemu/module.h"
-+#include "hw/resettable.h"
++#include "hw/misc/bcm2835_powermgt.h"
-+#include "trace.h"
++#include "migration/vmstate.h"
-+
++#include "sysemu/runstate.h"
-+/**
++
-+ * resettable_phase_enter/hold/exit:
++#define PASSWORD 0x5a000000
-+ * Function executing a phase recursively in a resettable object and its
++#define PASSWORD_MASK 0xff000000
-+ * children.
++
-+ */
++#define R_RSTC 0x1c
-+static void resettable_phase_enter(Object *obj, void *opaque, ResetType type);
++#define V_RSTC_RESET 0x20
-+static void resettable_phase_hold(Object *obj, void *opaque, ResetType type);
++#define R_RSTS 0x20
-+static void resettable_phase_exit(Object *obj, void *opaque, ResetType type);
++#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
-+
++#define R_WDOG 0x24
-+/**
++
-+ * enter_phase_in_progress:
++static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
-+ * True if we are currently in reset enter phase.
++                                      unsigned size)
-+ *
++{
-+ * Note: This flag is only used to guarantee (using asserts) that the reset
++    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
-+ * API is used correctly. We can use a global variable because we rely on the
++    uint32_t res = 0;
-+ * iothread mutex to ensure only one reset operation is in a progress at a
++
-+ * given time.
++    switch (offset) {
-+ */
++    case R_RSTC:
-+static bool enter_phase_in_progress;
++        res = s->rstc;
-+
++        break;
-+void resettable_reset(Object *obj, ResetType type)
++    case R_RSTS:
-+{
++        res = s->rsts;
-+    trace_resettable_reset(obj, type);
++        break;
-+    resettable_assert_reset(obj, type);
++    case R_WDOG:
-+    resettable_release_reset(obj, type);
++        res = s->wdog;
-+}
++        break;
 +
-+void resettable_assert_reset(Object *obj, ResetType type)
++    default:
-+{
++        qemu_log_mask(LOG_UNIMP,
-+    /* TODO: change this assert when adding support for other reset types */
++                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
-+    assert(type == RESET_TYPE_COLD);
++                      "\n", offset);
-+    trace_resettable_reset_assert_begin(obj, type);
++        res = 0;
-+    assert(!enter_phase_in_progress);
++        break;
-+
++    }
-+    enter_phase_in_progress = true;
++
-+    resettable_phase_enter(obj, NULL, type);
++    return res;
-+    enter_phase_in_progress = false;
++}
 +
-+    resettable_phase_hold(obj, NULL, type);
++static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
-+
++                                   uint64_t value, unsigned size)
-+    trace_resettable_reset_assert_end(obj);
++{
-+}
++    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +
-+void resettable_release_reset(Object *obj, ResetType type)
++    if ((value & PASSWORD_MASK) != PASSWORD) {
-+{
++        qemu_log_mask(LOG_GUEST_ERROR,
-+    /* TODO: change this assert when adding support for other reset types */
++                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
-+    assert(type == RESET_TYPE_COLD);
++                      " at offset 0x%08"HWADDR_PRIx"\n",
-+    trace_resettable_reset_release_begin(obj, type);
++                      value, offset);
-+    assert(!enter_phase_in_progress);
++        return;
-+
++    }
-+    resettable_phase_exit(obj, NULL, type);
++
-+
++    value = value & ~PASSWORD_MASK;
-+    trace_resettable_reset_release_end(obj);
++
-+}
++    switch (offset) {
-+
++    case R_RSTC:
-+bool resettable_is_in_reset(Object *obj)
++        s->rstc = value;
-+{
++        if (value & V_RSTC_RESET) {
-+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
++            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
-+    ResettableState *s = rc->get_state(obj);
++                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
-+
++            } else {
-+    return s->count > 0;
++                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-+}
++            }
 +
 +/**
 + * resettable_child_foreach:
 + * helper to avoid checking the existence of the method.
 + */
 +static void resettable_child_foreach(ResettableClass *rc, Object *obj,
 +                                     ResettableChildCallback cb,
 +                                     void *opaque, ResetType type)
 +{
 +    if (rc->child_foreach) {
 +        rc->child_foreach(obj, cb, opaque, type);
 +    }
 +}
 +
 +/**
 + * resettable_get_tr_func:
 + * helper to fetch transitional reset callback if any.
 + */
 +static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc,
 +                                                   Object *obj)
 +{
 +    ResettableTrFunction tr_func = NULL;
 +    if (rc->get_transitional_function) {
 +        tr_func = rc->get_transitional_function(obj);
 +    }
 +    return tr_func;
 +}
 +
 +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type)
 +{
 +    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
 +    ResettableState *s = rc->get_state(obj);
 +    const char *obj_typename = object_get_typename(obj);
 +    bool action_needed = false;
 +
 +    /* exit phase has to finish properly before entering back in reset */
 +    assert(!s->exit_phase_in_progress);
 +
 +    trace_resettable_phase_enter_begin(obj, obj_typename, s->count, type);
 +
 +    /* Only take action if we really enter reset for the 1st time. */
 +    /*
 +     * TODO: if adding more ResetType support, some additional checks
 +     * are probably needed here.
 +     */
 +    if (s->count++ == 0) {
 +        action_needed = true;
 +    }
 +    /*
 +     * We limit the count to an arbitrary "big" value. The value is big
 +     * enough not to be triggered normally.
 +     * The assert will stop an infinite loop if there is a cycle in the
 +     * reset tree. The loop goes through resettable_foreach_child below
 +     * which at some point will call us again.
 +     */
 +    assert(s->count <= 50);
 +
 +    /*
 +     * handle the children even if action_needed is at false so that
 +     * child counts are incremented too
 +     */
 +    resettable_child_foreach(rc, obj, resettable_phase_enter, NULL, type);
 +
 +    /* execute enter phase for the object if needed */
 +    if (action_needed) {
 +        trace_resettable_phase_enter_exec(obj, obj_typename, type,
 +                                          !!rc->phases.enter);
 +        if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) {
 +            rc->phases.enter(obj, type);
 +        }
-+        s->hold_phase_pending = true;
++        break;
-+    }
++    case R_RSTS:
-+    trace_resettable_phase_enter_end(obj, obj_typename, s->count);
++        qemu_log_mask(LOG_UNIMP,
-+}
++                      "bcm2835_powermgt_write: RSTS\n");
-+
++        s->rsts = value;
-+static void resettable_phase_hold(Object *obj, void *opaque, ResetType type)
++        break;
-+{
++    case R_WDOG:
-+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
++        qemu_log_mask(LOG_UNIMP,
-+    ResettableState *s = rc->get_state(obj);
++                      "bcm2835_powermgt_write: WDOG\n");
-+    const char *obj_typename = object_get_typename(obj);
++        s->wdog = value;
-+
++        break;
-+    /* exit phase has to finish properly before entering back in reset */
++
-+    assert(!s->exit_phase_in_progress);
++    default:
-+
++        qemu_log_mask(LOG_UNIMP,
-+    trace_resettable_phase_hold_begin(obj, obj_typename, s->count, type);
++                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
-+
++                      "\n", offset);
-+    /* handle children first */
++        break;
-+    resettable_child_foreach(rc, obj, resettable_phase_hold, NULL, type);
++    }
-+
++}
-+    /* exec hold phase */
++
-+    if (s->hold_phase_pending) {
++static const MemoryRegionOps bcm2835_powermgt_ops = {
-+        s->hold_phase_pending = false;
++    .read = bcm2835_powermgt_read,
-+        ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj);
++    .write = bcm2835_powermgt_write,
-+        trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold);
++    .endianness = DEVICE_NATIVE_ENDIAN,
-+        if (tr_func) {
++    .impl.min_access_size = 4,
-+            trace_resettable_transitional_function(obj, obj_typename);
++    .impl.max_access_size = 4,
-+            tr_func(obj);
++};
-+        } else if (rc->phases.hold) {
++
-+            rc->phases.hold(obj);
++static const VMStateDescription vmstate_bcm2835_powermgt = {
-+        }
++    .name = TYPE_BCM2835_POWERMGT,
-+    }
++    .version_id = 1,
-+    trace_resettable_phase_hold_end(obj, obj_typename, s->count);
++    .minimum_version_id = 1,
-+}
++    .fields = (VMStateField[]) {
-+
++        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
-+static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
++        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
-+{
++        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
-+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
++        VMSTATE_END_OF_LIST()
-+    ResettableState *s = rc->get_state(obj);
++    }
-+    const char *obj_typename = object_get_typename(obj);
++};
 +
-+    assert(!s->exit_phase_in_progress);
++static void bcm2835_powermgt_init(Object *obj)
-+    trace_resettable_phase_exit_begin(obj, obj_typename, s->count, type);
++{
-+
++    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
-+    /* exit_phase_in_progress ensures this phase is 'atomic' */
++
-+    s->exit_phase_in_progress = true;
++    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
-+    resettable_child_foreach(rc, obj, resettable_phase_exit, NULL, type);
++                          TYPE_BCM2835_POWERMGT, 0x200);
-+
++    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
-+    assert(s->count > 0);
++}
-+    if (s->count == 1) {
++
-+        trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit);
++static void bcm2835_powermgt_reset(DeviceState *dev)
-+        if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) {
++{
-+            rc->phases.exit(obj);
++    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
-+        }
++
-+        s->count = 0;
++    /* https://elinux.org/BCM2835_registers#PM */
-+    }
++    s->rstc = 0x00000102;
-+    s->exit_phase_in_progress = false;
++    s->rsts = 0x00001000;
-+    trace_resettable_phase_exit_end(obj, obj_typename, s->count);
++    s->wdog = 0x00000000;
 +}
 +
-+void resettable_class_set_parent_phases(ResettableClass *rc,
++static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
-+                                        ResettableEnterPhase enter,
++{
-+                                        ResettableHoldPhase hold,
++    DeviceClass *dc = DEVICE_CLASS(klass);
-+                                        ResettableExitPhase exit,
++
-+                                        ResettablePhases *parent_phases)
++    dc->reset = bcm2835_powermgt_reset;
-+{
++    dc->vmsd = &vmstate_bcm2835_powermgt;
-+    *parent_phases = rc->phases;
++}
-+    if (enter) {
++
-+        rc->phases.enter = enter;
++static TypeInfo bcm2835_powermgt_info = {
-+    }
++    .name          = TYPE_BCM2835_POWERMGT,
-+    if (hold) {
++    .parent        = TYPE_SYS_BUS_DEVICE,
-+        rc->phases.hold = hold;
++    .instance_size = sizeof(BCM2835PowerMgtState),
-+    }
++    .class_init    = bcm2835_powermgt_class_init,
-+    if (exit) {
++    .instance_init = bcm2835_powermgt_init,
-+        rc->phases.exit = exit;
++};
-+    }
++
-+}
++static void bcm2835_powermgt_register_types(void)
-+
++{
-+static const TypeInfo resettable_interface_info = {
++    type_register_static(&bcm2835_powermgt_info);
-+    .name       = TYPE_RESETTABLE_INTERFACE,
++}
-+    .parent     = TYPE_INTERFACE,
++
-+    .class_size = sizeof(ResettableClass),
++type_init(bcm2835_powermgt_register_types)
-+};
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 +
 +static void reset_register_types(void)
 +{
 +    type_register_static(&resettable_interface_info);
 +}
 +
 +type_init(reset_register_types)
 diff --git a/hw/core/trace-events b/hw/core/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/trace-events
+--- a/hw/misc/meson.build
-+++ b/hw/core/trace-events
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@ qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
- qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
+   'bcm2835_rng.c',
- qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
+   'bcm2835_thermal.c',
- qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
+   'bcm2835_cprman.c',
-+
++  'bcm2835_powermgt.c',
-+# resettable.c
+ ))
-+resettable_reset(void *obj, int cold) "obj=%p cold=%d"
+ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
-+resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d"
+ softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
 +resettable_reset_assert_end(void *obj) "obj=%p"
 +resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d"
 +resettable_reset_release_end(void *obj) "obj=%p"
 +resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
 +resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d"
 +resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
 +resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
 +resettable_phase_hold_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
 +resettable_phase_hold_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
 +resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
 +resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
 +resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
 +resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
 --
 .20.1

-[PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
+[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Since we enabled parallel TCG code generation for softmmu (see
+Add a test booting and quickly shutdown a raspi2 machine,
-commit 3468b59 "tcg: enable multiple TCG contexts in softmmu")
+to test the power management model:
 and its subsequent fix (commit 72649619 "add .min_cpus and
 .default_cpus fields to machine_class"), the raspi machines are
 restricted to always use their 4 cores:
-See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4):
+   (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
   console: [    0.000000] Booting Linux on physical CPU 0xf00
   console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
   console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
   console: [    0.000000] CPU: div instructions available: patching division code
   console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
   console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
   ...
   console: Boot successful.
   console: cat /proc/cpuinfo
   console: / # cat /proc/cpuinfo
   ...
   console: processor      : 3
   console: model name     : ARMv7 Processor rev 5 (v7l)
   console: BogoMIPS       : 125.00
   console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
   console: CPU implementer        : 0x41
   console: CPU architecture: 7
   console: CPU variant    : 0x0
   console: CPU part       : 0xc07
   console: CPU revision   : 5
   console: Hardware       : BCM2835
   console: Revision       : 0000
   console: Serial         : 0000000000000000
   console: cat /proc/iomem
   console: / # cat /proc/iomem
   console: 00000000-3bffffff : System RAM
   console: 00008000-00afffff : Kernel code
   console: 00c00000-00d468ef : Kernel data
   console: 3f006000-3f006fff : dwc_otg
   console: 3f007000-3f007eff : /soc/dma@7e007000
   console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
   console: 3f100000-3f100027 : /soc/watchdog@7e100000
   console: 3f101000-3f102fff : /soc/cprman@7e101000
   console: 3f200000-3f2000b3 : /soc/gpio@7e200000
   PASS (24.59 s)
   RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
   JOB TIME   : 25.02 s
-static void raspi2_machine_init(MachineClass *mc)
-{
-mc->desc = "Raspberry Pi 2";
-mc->max_cpus = BCM283X_NCPUS;
-mc->min_cpus = BCM283X_NCPUS;
-mc->default_cpus = BCM283X_NCPUS;
-};
-DEFINE_MACHINE("raspi2", raspi2_machine_init)
-We can no longer use the -smp option, as we get:
-  $ qemu-system-arm -M raspi2 -smp 1
-  qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4
-Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp,
-remove the unuseful code.
-We can achieve the same by using the '-global bcm2836.enabled-cpus=1'
-option.
-Reported-by: Laurent Bonnans <laurent.bonnans@here.com>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
-Message-id: 20200120235159.18510-2-f4bug@amsat.org
+Message-id: 20210531113837.1689775-1-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/raspi.c | 2 --
+ tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
-file changed, 2 deletions(-)
+file changed, 43 insertions(+)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/tests/acceptance/boot_linux_console.py
-+++ b/hw/arm/raspi.c
++++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+@@ -XXX,XX +XXX,XX @@
-     /* Setup the SOC */
+ from avocado import skip
-     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
+ from avocado import skipUnless
-                                    &error_abort);
+ from avocado_qemu import Test
--    object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus",
++from avocado_qemu import exec_command
--                            &error_abort);
+ from avocado_qemu import exec_command_and_wait_for_pattern
-     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
+ from avocado_qemu import interrupt_interactive_console_until_pattern
-     object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
+ from avocado_qemu import wait_for_console_pattern
-                             &error_abort);
+@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
          """
          self.do_test_arm_raspi2(0)
 +    def test_arm_raspi2_initrd(self):
 +        """
 +        :avocado: tags=arch:arm
 +        :avocado: tags=machine:raspi2
 +        """
 +        deb_url = ('http://archive.raspberrypi.org/debian/'
 +                   'pool/main/r/raspberrypi-firmware/'
 +                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
 +        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
 +        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
 +        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
 +        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
 +
 +        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
 +                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
 +                      'arm/rootfs-armv7a.cpio.gz')
 +        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
 +        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
 +        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
 +        archive.gzip_uncompress(initrd_path_gz, initrd_path)
 +
 +        self.vm.set_console()
 +        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
 +                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
 +                               'panic=-1 noreboot ' +
 +                               'dwc_otg.fiq_fsm_enable=0')
 +        self.vm.add_args('-kernel', kernel_path,
 +                         '-dtb', dtb_path,
 +                         '-initrd', initrd_path,
 +                         '-append', kernel_command_line,
 +                         '-no-reboot')
 +        self.vm.launch()
 +        self.wait_for_console_pattern('Boot successful.')
 +
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
 +                                                'BCM2835')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
 +                                                '/soc/cprman@7e101000')
 +        exec_command(self, 'halt')
 +        # Wait for VM to shut down gracefully
 +        self.vm.wait()
 +
      def test_arm_exynos4210_initrd(self):
          """
          :avocado: tags=arch:arm
 --
 .20.1

-[PULL 22/26] hw/arm/virt: Add missing 5.0 options call to 4.2 options
+[PULL 05/24] target/arm: Check NaN mode before silencing NaN
-From: Andrew Jones <drjones@redhat.com>
+From: Joe Komlodi <joe.komlodi@xilinx.com>
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
-Message-id: 20200120101023.16030-3-drjones@redhat.com
+FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
 assert due to fpst->default_nan_mode being set.
 To avoid this, we check to see what NaN mode we're running in before we call
 floatxx_silence_nan().
 Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 1 +
+ target/arm/helper-a64.c | 12 +++++++++---
-file changed, 1 insertion(+)
+ target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 files changed, 27 insertions(+), 9 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/helper-a64.c
-+++ b/hw/arm/virt.c
++++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0)
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
+         float16 nan = a;
- static void virt_machine_4_2_options(MachineClass *mc)
+         if (float16_is_signaling_nan(a, fpst)) {
- {
+             float_raise(float_flag_invalid, fpst);
-+    virt_machine_5_0_options(mc);
+-            nan = float16_silence_nan(a, fpst);
-     compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
++            if (!fpst->default_nan_mode) {
- }
++                nan = float16_silence_nan(a, fpst);
- DEFINE_VIRT_MACHINE(4, 2)
++            }
          }
          if (fpst->default_nan_mode) {
              nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
          float32 nan = a;
          if (float32_is_signaling_nan(a, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float32_silence_nan(a, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float32_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
          float64 nan = a;
          if (float64_is_signaling_nan(a, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(a, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float64_default_nan(fpst);
 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/vfp_helper.c
 +++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
          float16 nan = f16;
          if (float16_is_signaling_nan(f16, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float16_silence_nan(f16, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float16_silence_nan(f16, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float32_silence_nan(f32, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(f64, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
          float16 nan = f16;
          if (float16_is_signaling_nan(f16, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float16_silence_nan(f16, s);
 +            if (!s->default_nan_mode) {
 +                nan = float16_silence_nan(f16, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float32_silence_nan(f32, s);
 +            if (!s->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float64_silence_nan(f64, s);
 +            if (!s->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float64_default_nan(s);
 --
 .20.1

-[PULL 09/26] add device_legacy_reset function to prepare for reset api change
+[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
-From: Damien Hedde <damien.hedde@greensocs.com>
+From: Maxim Uvarov <maxim.uvarov@linaro.org>
-Provide a temporary device_legacy_reset function doing what
+qemu has 2 type of functions: shutdown and reboot. Shutdown
-device_reset does to prepare for the transition with Resettable
+function has to be used for machine shutdown. Otherwise we cause
-API.
+a reset with a bogus "cause" value, when we intended a shutdown.
-All occurrence of device_reset in the code tree are also replaced
+Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
 by device_legacy_reset.
 The new resettable API has different prototype and semantics
 (resetting child buses as well as the specified device). Subsequent
 commits will make the changeover for each call site individually; once
 that is complete device_legacy_reset() will be removed.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
-Acked-by: David Gibson <david@gibson.dropbear.id.au>
+[PMM: tweaked commit message]
 Acked-by: Cornelia Huck <cohuck@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/qdev-core.h   | 4 ++--
+ hw/gpio/gpio_pwr.c | 2 +-
- hw/audio/intel-hda.c     | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
  hw/core/qdev.c           | 6 +++---
  hw/hyperv/hyperv.c       | 2 +-
  hw/i386/microvm.c        | 2 +-
  hw/i386/pc.c             | 2 +-
  hw/ide/microdrive.c      | 8 ++++----
  hw/intc/spapr_xive.c     | 2 +-
  hw/ppc/pnv_psi.c         | 4 ++--
  hw/ppc/spapr_pci.c       | 2 +-
  hw/ppc/spapr_vio.c       | 2 +-
  hw/s390x/s390-pci-inst.c | 2 +-
  hw/scsi/vmw_pvscsi.c     | 2 +-
  hw/sd/omap_mmc.c         | 2 +-
  hw/sd/pl181.c            | 2 +-
 files changed, 22 insertions(+), 22 deletions(-)
-diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
+diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/qdev-core.h
+--- a/hw/gpio/gpio_pwr.c
-+++ b/include/hw/qdev-core.h
++++ b/hw/gpio/gpio_pwr.c
-@@ -XXX,XX +XXX,XX @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev);
+@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
- void qdev_machine_init(void);
+ static void gpio_pwr_shutdown(void *opaque, int n, int level)
  /**
 - * @device_reset
 + * device_legacy_reset:
   *
   * Reset a single device (by calling the reset method).
   */
 -void device_reset(DeviceState *dev);
 +void device_legacy_reset(DeviceState *dev);
  void device_class_set_props(DeviceClass *dc, Property *props);
 diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/audio/intel-hda.c
 +++ b/hw/audio/intel-hda.c
@@ -XXX,XX +XXX,XX @@ static void intel_hda_reset(DeviceState *dev)
      QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
          DeviceState *qdev = kid->child;
          cdev = HDA_CODEC_DEVICE(qdev);
 -        device_reset(DEVICE(cdev));
 +        device_legacy_reset(DEVICE(cdev));
          d->state_sts |= (1 << cdev->cad);
      }
      intel_hda_update_irq(d);
 diff --git a/hw/core/qdev.c b/hw/core/qdev.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/qdev.c
 +++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev)
  static int qdev_reset_one(DeviceState *dev, void *opaque)
  {
--    device_reset(dev);
+     if (level) {
-+    device_legacy_reset(dev);
+-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
++        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
              }
          }
          if (dev->hotplugged) {
 -            device_reset(dev);
 +            device_legacy_reset(dev);
          }
          dev->pending_deleted_event = false;
@@ -XXX,XX +XXX,XX @@ void device_class_set_parent_unrealize(DeviceClass *dc,
      dc->unrealize = dev_unrealize;
  }
 -void device_reset(DeviceState *dev)
 +void device_legacy_reset(DeviceState *dev)
  {
      DeviceClass *klass = DEVICE_GET_CLASS(dev);
 diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/hyperv/hyperv.c
 +++ b/hw/hyperv/hyperv.c
@@ -XXX,XX +XXX,XX @@ void hyperv_synic_reset(CPUState *cs)
      SynICState *synic = get_synic(cs);
      if (synic) {
 -        device_reset(DEVICE(synic));
 +        device_legacy_reset(DEVICE(synic));
      }
  }
-diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i386/microvm.c
-+++ b/hw/i386/microvm.c
-@@ -XXX,XX +XXX,XX @@ static void microvm_machine_reset(MachineState *machine)
-         cpu = X86_CPU(cs);
-         if (cpu->apic_state) {
--            device_reset(cpu->apic_state);
-+            device_legacy_reset(cpu->apic_state);
-         }
-     }
- }
-diff --git a/hw/i386/pc.c b/hw/i386/pc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i386/pc.c
-+++ b/hw/i386/pc.c
-@@ -XXX,XX +XXX,XX @@ static void pc_machine_reset(MachineState *machine)
-         cpu = X86_CPU(cs);
-         if (cpu->apic_state) {
--            device_reset(cpu->apic_state);
-+            device_legacy_reset(cpu->apic_state);
-         }
-     }
- }
-diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ide/microdrive.c
-+++ b/hw/ide/microdrive.c
-@@ -XXX,XX +XXX,XX @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
-     case 0x00:    /* Configuration Option Register */
-         s->opt = value & 0xcf;
-         if (value & OPT_SRESET) {
--            device_reset(DEVICE(s));
-+            device_legacy_reset(DEVICE(s));
-         }
-         md_interrupt_update(s);
-         break;
-@@ -XXX,XX +XXX,XX @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
-     case 0xe:    /* Device Control */
-         s->ctrl = value;
-         if (value & CTRL_SRST) {
--            device_reset(DEVICE(s));
-+            device_legacy_reset(DEVICE(s));
-         }
-         md_interrupt_update(s);
-         break;
-@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_attach(PCMCIACardState *card)
-     md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
-     md->io_base = 0x0;
--    device_reset(DEVICE(md));
-+    device_legacy_reset(DEVICE(md));
-     md_interrupt_update(md);
-     return 0;
-@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_detach(PCMCIACardState *card)
- {
-     MicroDriveState *md = MICRODRIVE(card);
--    device_reset(DEVICE(md));
-+    device_legacy_reset(DEVICE(md));
-     return 0;
- }
-diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/spapr_xive.c
-+++ b/hw/intc/spapr_xive.c
-@@ -XXX,XX +XXX,XX @@ static target_ulong h_int_reset(PowerPCCPU *cpu,
-         return H_PARAMETER;
-     }
--    device_reset(DEVICE(xive));
-+    device_legacy_reset(DEVICE(xive));
-     if (kvm_irqchip_in_kernel()) {
-         Error *local_err = NULL;
-diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ppc/pnv_psi.c
-+++ b/hw/ppc/pnv_psi.c
-@@ -XXX,XX +XXX,XX @@ static void pnv_psi_reset(DeviceState *dev)
- static void pnv_psi_reset_handler(void *dev)
- {
--    device_reset(DEVICE(dev));
-+    device_legacy_reset(DEVICE(dev));
- }
- static void pnv_psi_realize(DeviceState *dev, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
-         break;
-     case PSIHB9_INTERRUPT_CONTROL:
-         if (val & PSIHB9_IRQ_RESET) {
--            device_reset(DEVICE(&psi9->source));
-+            device_legacy_reset(DEVICE(&psi9->source));
-         }
-         psi->regs[reg] = val;
-         break;
-diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ppc/spapr_pci.c
-+++ b/hw/ppc/spapr_pci.c
-@@ -XXX,XX +XXX,XX @@ static int spapr_phb_children_reset(Object *child, void *opaque)
-     DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
-     if (dev) {
--        device_reset(dev);
-+        device_legacy_reset(dev);
-     }
-     return 0;
-diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ppc/spapr_vio.c
-+++ b/hw/ppc/spapr_vio.c
-@@ -XXX,XX +XXX,XX @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq)
- static void spapr_vio_quiesce_one(SpaprVioDevice *dev)
- {
-     if (dev->tcet) {
--        device_reset(DEVICE(dev->tcet));
-+        device_legacy_reset(DEVICE(dev->tcet));
-     }
-     free_crq(dev);
- }
-diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/s390x/s390-pci-inst.c
-+++ b/hw/s390x/s390-pci-inst.c
-@@ -XXX,XX +XXX,XX @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
-                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
-                 goto out;
-             }
--            device_reset(DEVICE(pbdev));
-+            device_legacy_reset(DEVICE(pbdev));
-             pbdev->fh &= ~FH_MASK_ENABLE;
-             pbdev->state = ZPCI_FS_DISABLED;
-             stl_p(&ressetpci->fh, pbdev->fh);
-diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/scsi/vmw_pvscsi.c
-+++ b/hw/scsi/vmw_pvscsi.c
-@@ -XXX,XX +XXX,XX @@ pvscsi_on_cmd_reset_device(PVSCSIState *s)
-     if (sdev != NULL) {
-         s->resetting++;
--        device_reset(&sdev->qdev);
-+        device_legacy_reset(&sdev->qdev);
-         s->resetting--;
-         return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
-     }
-diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/omap_mmc.c
-+++ b/hw/sd/omap_mmc.c
-@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
-      * into any bus, and we must reset it manually. When omap_mmc is
-      * QOMified this must move into the QOM reset function.
-      */
--    device_reset(DEVICE(host->card));
-+    device_legacy_reset(DEVICE(host->card));
- }
- static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
-diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/pl181.c
-+++ b/hw/sd/pl181.c
-@@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d)
-     /* Since we're still using the legacy SD API the card is not plugged
-      * into any bus, and we must reset it manually.
-      */
--    device_reset(DEVICE(s->card));
-+    device_legacy_reset(DEVICE(s->card));
- }
- static void pl181_init(Object *obj)
 --
 .20.1

-[PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller
+[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
-From: Andrew Jeffery <andrew@aj.id.au>
+In do_ldst(), the calculation of the offset needs to be based on the
 size of the memory access, not the size of the elements in the
 vector.  This meant we were getting it wrong for the widening and
 narrowing variants of the various VLDR and VSTR insns.
-Initialise another SDHCI model instance for the AST2600's eMMC
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-controller and use the SDHCI's num_slots value introduced previously to
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-determine whether we should create an SD card instance for the new slot.
+Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
 ---
  target/arm/translate-mve.c | 17 +++++++++--------
 file changed, 9 insertions(+), 8 deletions(-)
-Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 20200114103433.30534-3-clg@kaod.org
 [ clg : - removed ternary operator from sdhci_attach_drive()
         - renamed SDHCI objects with a '-controller' prefix ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/aspeed_soc.h |  2 ++
  hw/arm/aspeed.c             | 26 +++++++++++++++++---------
  hw/arm/aspeed_ast2600.c     | 29 ++++++++++++++++++++++++++---
 files changed, 45 insertions(+), 12 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
+--- a/target/arm/translate-mve.c
-+++ b/include/hw/arm/aspeed_soc.h
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
+@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
      AspeedGPIOState gpio;
      AspeedGPIOState gpio_1_8v;
      AspeedSDHCIState sdhci;
 +    AspeedSDHCIState emmc;
  } AspeedSoCState;
  #define TYPE_ASPEED_SOC "aspeed-soc"
@@ -XXX,XX +XXX,XX @@ enum {
      ASPEED_MII4,
      ASPEED_SDRAM,
      ASPEED_XDMA,
 +    ASPEED_EMMC,
  };
  #endif /* ASPEED_SOC_H */
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
      }
  }
-+static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
+-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
-+{
++static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
-+        DeviceState *card;
++                    unsigned msize)
 +
 +        card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 +                           TYPE_SD_CARD);
 +        if (dinfo) {
 +            qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo),
 +                                &error_fatal);
 +        }
 +        object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
 +}
 +
  static void aspeed_machine_init(MachineState *machine)
  {
-     AspeedBoardState *bmc;
+     TCGv_i32 addr;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
+     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
          return true;
      }
-     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
+-    offset = a->imm << a->size;
--        SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
++    offset = a->imm << msize;
--        DriveInfo *dinfo = drive_get_next(IF_SD);
+     if (!a->a) {
--        BlockBackend *blk;
+         offset = -offset;
 -        DeviceState *card;
 +        sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
 +    }
 -        blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
 -        card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 -                           TYPE_SD_CARD);
 -        qdev_prop_set_drive(card, "drive", blk, &error_fatal);
 -        object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
 +    if (bmc->soc.emmc.num_slots) {
 +        sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
      }
+@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
-     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
+         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
-diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
+         { NULL, NULL }
-index XXXXXXX..XXXXXXX 100644
+     };
---- a/hw/arm/aspeed_ast2600.c
+-    return do_ldst(s, a, ldstfns[a->size][a->l]);
-+++ b/hw/arm/aspeed_ast2600.c
++    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
-@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
+ }
-     [ASPEED_ADC]       = 0x1E6E9000,
-     [ASPEED_VIDEO]     = 0x1E700000,
+-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
-     [ASPEED_SDHCI]     = 0x1E740000,
++#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
-+    [ASPEED_EMMC]      = 0x1E750000,
+     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
-     [ASPEED_GPIO]      = 0x1E780000,
+     {                                                           \
-     [ASPEED_GPIO_1_8V] = 0x1E780800,
+         static MVEGenLdStFn * const ldstfns[2][2] = {           \
-     [ASPEED_RTC]       = 0x1E781000,
+             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
-@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
+             { NULL, gen_helper_mve_##ULD },                     \
+         };                                                      \
- #define ASPEED_SOC_AST2600_MAX_IRQ 128
+-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
++        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
 +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
  static const int aspeed_soc_ast2600_irqmap[] = {
      [ASPEED_UART1]     = 47,
      [ASPEED_UART2]     = 48,
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
      [ASPEED_ADC]       = 78,
      [ASPEED_XDMA]      = 6,
      [ASPEED_SDHCI]     = 43,
 +    [ASPEED_EMMC]      = 15,
      [ASPEED_GPIO]      = 40,
      [ASPEED_GPIO_1_8V] = 11,
      [ASPEED_RTC]       = 13,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
                            sizeof(s->gpio_1_8v), typename);
 -    sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
 -                          TYPE_ASPEED_SDHCI);
 +    sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
 +                          sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
      object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
      /* Init sd card slot class here so that they're under the correct parent */
      for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
 -        sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
 +        sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
 +                              OBJECT(&s->sdhci.slots[i]),
                                sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
      }
-+
-+    sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
+-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-+                          sizeof(s->emmc), TYPE_ASPEED_SDHCI);
+-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-+
+-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
-+    object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
++DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
-+
++DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
-+    sysbus_init_child_obj(obj, "emmc-controller.sdhci",
++DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
-+                          OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
-+                          TYPE_SYSBUS_SDHCI);
+ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
- }
+ {
  /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
                      sc->memmap[ASPEED_SDHCI]);
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                         aspeed_soc_get_irq(s, ASPEED_SDHCI));
 +
 +    /* eMMC */
 +    object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
 +                       aspeed_soc_get_irq(s, ASPEED_EMMC));
  }
  static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
 --
 .20.1

-[PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
+[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
-From: Andrew Jeffery <andrew@aj.id.au>
+The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
 insns had some bugs:
  * the 32x32 multiply of elements was being done as 32x32->32,
    not 32x32->64
  * we were incorrectly maintaining the accumulator in its full
 -bit form across all 4 beats of the insn; in the pseudocode
    it is squashed back into the 64 bits of the RdaHi:RdaLo
    registers after each beat
-The AST2600 includes a second cut-down version of the SD/MMC controller
+In particular, fixing the second of these allows us to recast
-found in the AST2500, named the eMMC controller. It's cut down in the
+the implementation to avoid 128-bit arithmetic entirely.
 sense that it only supports one slot rather than two, but it brings the
 total number of slots supported by the AST2600 to three.
-The existing code assumed that the SD controller always provided two
+Since the element size here is always 4, we can also drop the
-slots. Rework the SDHCI object to expose the number of slots as a
+parameterization of ESIZE to make the code a little more readable.
 property to be set by the SoC configuration.
-Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 20200114103433.30534-2-clg@kaod.org
 [PMM: fixed up to use device_class_set_props()]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
 ---
- include/hw/sd/aspeed_sdhci.h |  1 +
+ target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
- hw/arm/aspeed.c              |  2 +-
+file changed, 21 insertions(+), 17 deletions(-)
  hw/arm/aspeed_ast2600.c      |  2 ++
  hw/arm/aspeed_soc.c          |  2 ++
  hw/sd/aspeed_sdhci.c         | 11 +++++++++--
 files changed, 15 insertions(+), 3 deletions(-)
-diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/sd/aspeed_sdhci.h
+--- a/target/arm/mve_helper.c
-+++ b/include/hw/sd/aspeed_sdhci.h
++++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDHCIState {
+@@ -XXX,XX +XXX,XX @@
-     SysBusDevice parent;
+  */
-     SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
+ #include "qemu/osdep.h"
-+    uint8_t num_slots;
+-#include "qemu/int128.h"
+ #include "cpu.h"
-     MemoryRegion iomem;
+ #include "internals.h"
-     qemu_irq irq;
+ #include "vec_internal.h"
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
-index XXXXXXX..XXXXXXX 100644
+ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
---- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed.c
+ /*
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
+- * Rounding multiply add long dual accumulate high: we must keep
-         amc->i2c_init(bmc);
+- * a 72-bit internal accumulator value and return the top 64 bits.
 + * Rounding multiply add long dual accumulate high. In the pseudocode
 + * this is implemented with a 72-bit internal accumulator value of which
 + * the top 64 bits are returned. We optimize this to avoid having to
 + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
 + * is squashed back into 64-bits after each beat.
   */
 -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
 +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
      uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                      void *vm, uint64_t a)               \
      {                                                                   \
          uint16_t mask = mve_element_mask(env);                          \
          unsigned e;                                                     \
          TYPE *n = vn, *m = vm;                                          \
 -        Int128 acc = int128_lshift(TO128(a), 8);                        \
 -        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
              if (mask & 1) {                                             \
 +                LTYPE mul;                                              \
                  if (e & 1) {                                            \
 -                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
 -                                            m[H##ESIZE(e)]));           \
 +                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
 +                    if (SUB) {                                          \
 +                        mul = -mul;                                     \
 +                    }                                                   \
                  } else {                                                \
 -                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
 -                                             m[H##ESIZE(e)]));          \
 +                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                  }                                                       \
 -                acc = int128_add(acc, int128_make64(1 << 7));           \
 +                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
 +                a += mul;                                               \
              }                                                           \
          }                                                               \
          mve_advance_vpt(env);                                           \
 -        return int128_getlo(int128_rshift(acc, 8));                     \
 +        return a;                                                       \
      }
--    for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) {
+-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-+    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
+-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
-         SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
++DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
-         DriveInfo *dinfo = drive_get_next(IF_SD);
++DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
-         BlockBackend *blk;
-diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
+-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
-index XXXXXXX..XXXXXXX 100644
++DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
---- a/hw/arm/aspeed_ast2600.c
-+++ b/hw/arm/aspeed_ast2600.c
+-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
+-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
-     sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
++DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
-                           TYPE_ASPEED_SDHCI);
++DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
-+    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
+ /* Vector add across vector */
-+
+ #define DO_VADDV(OP, ESIZE, TYPE)                               \
      /* Init sd card slot class here so that they're under the correct parent */
      for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
          sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc.c
 +++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
      sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
                            TYPE_ASPEED_SDHCI);
 +    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
 +
      /* Init sd card slot class here so that they're under the correct parent */
      for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
          sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
 diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/aspeed_sdhci.c
 +++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/irq.h"
  #include "migration/vmstate.h"
 +#include "hw/qdev-properties.h"
  #define ASPEED_SDHCI_INFO            0x00
  #define  ASPEED_SDHCI_INFO_RESET     0x00030000
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
      /* Create input irqs for the slots */
      qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
 -                                        sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS);
 +                                        sdhci, NULL, sdhci->num_slots);
      sysbus_init_irq(sbd, &sdhci->irq);
      memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
                            sdhci, TYPE_ASPEED_SDHCI, 0x1000);
      sysbus_init_mmio(sbd, &sdhci->iomem);
 -    for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
 +    for (int i = 0; i < sdhci->num_slots; ++i) {
          Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
          SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdhci = {
      },
  };
 +static Property aspeed_sdhci_properties[] = {
 +    DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
  static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(classp);
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
      dc->realize = aspeed_sdhci_realize;
      dc->reset = aspeed_sdhci_reset;
      dc->vmsd = &vmstate_aspeed_sdhci;
 +    device_class_set_props(dc, aspeed_sdhci_properties);
  }
  static TypeInfo aspeed_sdhci_info = {
 --
 .20.1

-[PULL 15/26] hw/core/qdev: update hotplug reset regarding resettable
+[PULL 09/24] target/arm: Make asimd_imm_const() public
-From: Damien Hedde <damien.hedde@greensocs.com>
+The function asimd_imm_const() in translate-neon.c is an
 implementation of the pseudocode AdvSIMDExpandImm(), which we will
 also want for MVE.  Move the implementation to translate.c, with a
 prototype in translate.h.
-This commit make use of the resettable API to reset the device being
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-hotplugged when it is realized. Also it ensures it is put in a reset
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-state coherent with the parent it is plugged into.
+Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
 ---
  target/arm/translate.h      | 16 ++++++++++
  target/arm/translate-neon.c | 63 -------------------------------------
  target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 files changed, 73 insertions(+), 63 deletions(-)
-Note that there is a difference in the reset. Instead of resetting
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 only the hotplugged device, we reset also its subtree (switch to
 resettable API). This is not expected to be a problem because
 sub-buses are just realized too. If a hotplugged device has any
 sub-buses it is logical to reset them too at this point.
 The recently added should_be_hidden and PCI's partially_hotplugged
 mechanisms do not interfere with realize operation:
 + In the should_be_hidden use case, device creation is
 delayed.
 + The partially_hotplugged mechanism prevents a device to be
 unplugged and unrealized from qdev POV and unrealized.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/resettable.h | 11 +++++++++++
  hw/core/qdev.c          | 15 ++++++++++++++-
 files changed, 25 insertions(+), 1 deletion(-)
 diff --git a/include/hw/resettable.h b/include/hw/resettable.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/resettable.h
+--- a/target/arm/translate.h
-+++ b/include/hw/resettable.h
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ struct ResettableState {
+@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
-     bool exit_phase_in_progress;
+     return opc | s->be_data;
- };
+ }
 +/**
-+ * resettable_state_clear:
++ * asimd_imm_const: Expand an encoded SIMD constant value
-+ * Clear the state. It puts the state to the initial (zeroed) state required
++ *
-+ * to reuse an object. Typically used in realize step of base classes
++ * Expand a SIMD constant value. This is essentially the pseudocode
-+ * implementing the interface.
++ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
 + * VMVN and VBIC (when cmode < 14 && op == 1).
 + *
 + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
 + * callers must catch this.
 + *
 + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
 + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 + * we produce an immediate constant value of 0 in these cases.
 + */
-+static inline void resettable_state_clear(ResettableState *state)
++uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 +
  #endif /* TARGET_ARM_TRANSLATE_H */
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
  DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
  DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
 -{
 -    /*
 -     * Expand the encoded constant.
 -     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
 -     * We choose to not special-case this and will behave as if a
 -     * valid constant encoding of 0 had been given.
 -     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
 -     */
 -    switch (cmode) {
 -    case 0: case 1:
 -        /* no-op */
 -        break;
 -    case 2: case 3:
 -        imm <<= 8;
 -        break;
 -    case 4: case 5:
 -        imm <<= 16;
 -        break;
 -    case 6: case 7:
 -        imm <<= 24;
 -        break;
 -    case 8: case 9:
 -        imm |= imm << 16;
 -        break;
 -    case 10: case 11:
 -        imm = (imm << 8) | (imm << 24);
 -        break;
 -    case 12:
 -        imm = (imm << 8) | 0xff;
 -        break;
 -    case 13:
 -        imm = (imm << 16) | 0xffff;
 -        break;
 -    case 14:
 -        if (op) {
 -            /*
 -             * This is the only case where the top and bottom 32 bits
 -             * of the encoded constant differ.
 -             */
 -            uint64_t imm64 = 0;
 -            int n;
 -
 -            for (n = 0; n < 8; n++) {
 -                if (imm & (1 << n)) {
 -                    imm64 |= (0xffULL << (n * 8));
 -                }
 -            }
 -            return imm64;
 -        }
 -        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 -        break;
 -    case 15:
 -        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 -            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 -        break;
 -    }
 -    if (op) {
 -        imm = ~imm;
 -    }
 -    return dup_const(MO_32, imm);
 -}
 -
  static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                          GVecGen2iFn *fn)
  {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
      a64_translate_init();
  }
 +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
 +{
-+    memset(state, 0, sizeof(ResettableState));
++    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
 +    switch (cmode) {
 +    case 0: case 1:
 +        /* no-op */
 +        break;
 +    case 2: case 3:
 +        imm <<= 8;
 +        break;
 +    case 4: case 5:
 +        imm <<= 16;
 +        break;
 +    case 6: case 7:
 +        imm <<= 24;
 +        break;
 +    case 8: case 9:
 +        imm |= imm << 16;
 +        break;
 +    case 10: case 11:
 +        imm = (imm << 8) | (imm << 24);
 +        break;
 +    case 12:
 +        imm = (imm << 8) | 0xff;
 +        break;
 +    case 13:
 +        imm = (imm << 16) | 0xffff;
 +        break;
 +    case 14:
 +        if (op) {
 +            /*
 +             * This is the only case where the top and bottom 32 bits
 +             * of the encoded constant differ.
 +             */
 +            uint64_t imm64 = 0;
 +            int n;
 +
 +            for (n = 0; n < 8; n++) {
 +                if (imm & (1 << n)) {
 +                    imm64 |= (0xffULL << (n * 8));
 +                }
 +            }
 +            return imm64;
 +        }
 +        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 +        break;
 +    case 15:
 +        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 +            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 +        break;
 +    }
 +    if (op) {
 +        imm = ~imm;
 +    }
 +    return dup_const(MO_32, imm);
 +}
 +
- /**
+ /* Generate a label used for skipping this instruction */
-  * resettable_reset:
+ void arm_gen_condlabel(DisasContext *s)
-  * Trigger a reset on an object @obj of type @type. @obj must implement
+ {
 diff --git a/hw/core/qdev.c b/hw/core/qdev.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/qdev.c
 +++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
              }
          }
 +        /*
 +         * Clear the reset state, in case the object was previously unrealized
 +         * with a dirty state.
 +         */
 +        resettable_state_clear(&dev->reset);
 +
          QLIST_FOREACH(bus, &dev->child_bus, sibling) {
              object_property_set_bool(OBJECT(bus), true, "realized",
                                           &local_err);
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
              }
          }
          if (dev->hotplugged) {
 -            device_legacy_reset(dev);
 +            /*
 +             * Reset the device, as well as its subtree which, at this point,
 +             * should be realized too.
 +             */
 +            resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD);
 +            resettable_change_parent(OBJECT(dev), OBJECT(dev->parent_bus),
 +                                     NULL);
 +            resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD);
          }
          dev->pending_deleted_event = false;
 --
 .20.1

-[PULL 26/26] target/arm/cpu: Add the kvm-no-adjvtime CPU property
+[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
-From: Andrew Jones <drjones@redhat.com>
+The A64 AdvSIMD modified-immediate grouping uses almost the same
 constant encoding that A32 Neon does; reuse asimd_imm_const() (to
 which we add the AArch64-specific case for cmode 15 op 1) instead of
 reimplementing it all.
-kvm-no-adjvtime is a KVM specific CPU property and a first of its
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-kind. To accommodate it we also add kvm_arm_add_vcpu_properties()
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-and a KVM specific CPU properties description to the CPU features
+Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
-document.
+---
  target/arm/translate.h     |  3 +-
  target/arm/translate-a64.c | 86 ++++----------------------------------
  target/arm/translate.c     | 17 +++++++-
 files changed, 24 insertions(+), 82 deletions(-)
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 Message-id: 20200120101023.16030-7-drjones@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/virt.h          |  1 +
  target/arm/kvm_arm.h           | 11 ++++++++++
  hw/arm/virt.c                  |  8 ++++++++
  target/arm/cpu.c               |  2 ++
  target/arm/cpu64.c             |  1 +
  target/arm/kvm.c               | 28 +++++++++++++++++++++++++
  target/arm/monitor.c           |  1 +
  tests/qtest/arm-cpu-features.c |  4 ++++
  docs/arm-cpu-features.rst      | 37 +++++++++++++++++++++++++++++++++-
 files changed, 92 insertions(+), 1 deletion(-)
 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/virt.h
+--- a/target/arm/translate.h
-+++ b/include/hw/arm/virt.h
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
-     bool smbios_old_sys_ver;
+  * VMVN and VBIC (when cmode < 14 && op == 1).
-     bool no_highmem_ecam;
+  *
-     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
+  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
-+    bool kvm_no_adjvtime;
+- * callers must catch this.
- } VirtMachineClass;
++ * callers must catch this; we return the 64-bit constant value defined
++ * for AArch64.
- typedef struct {
+  *
-diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
+  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
   * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm_arm.h
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/kvm_arm.h
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
   */
  void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
 +/**
 + * kvm_arm_add_vcpu_properties:
 + * @obj: The CPU object to add the properties to
 + *
 + * Add all KVM specific CPU properties to the CPU object. These
 + * are the CPU properties with "kvm-" prefixed names.
 + */
 +void kvm_arm_add_vcpu_properties(Object *obj);
 +
  /**
   * kvm_arm_aarch32_supported:
   * @cs: CPUState
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
      cpu->host_cpu_probe_failed = true;
  }
 +static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
 +
  static inline bool kvm_arm_aarch32_supported(CPUState *cs)
  {
-     return false;
+     int rd = extract32(insn, 0, 5);
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+     int cmode = extract32(insn, 12, 4);
-index XXXXXXX..XXXXXXX 100644
+-    int cmode_3_1 = extract32(cmode, 1, 3);
---- a/hw/arm/virt.c
+-    int cmode_0 = extract32(cmode, 0, 1);
-+++ b/hw/arm/virt.c
+     int o2 = extract32(insn, 11, 1);
-@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
-             }
+     bool is_neg = extract32(insn, 29, 1);
-         }
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 +        if (vmc->kvm_no_adjvtime &&
 +            object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) {
 +            object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL);
 +        }
 +
          if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
              object_property_set_bool(cpuobj, false, "pmu", NULL);
          }
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0)
  static void virt_machine_4_2_options(MachineClass *mc)
  {
 +    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
 +
      virt_machine_5_0_options(mc);
      compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
 +    vmc->kvm_no_adjvtime = true;
  }
  DEFINE_VIRT_MACHINE(4, 2)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
      if (kvm_enabled()) {
          kvm_arm_set_cpu_features_from_host(cpu);
 +        kvm_arm_add_vcpu_properties(obj);
      } else {
          cortex_a15_initfn(obj);
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
      if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
          aarch64_add_sve_properties(obj);
      }
 +    kvm_arm_add_vcpu_properties(obj);
      arm_cpu_post_init(obj);
  }
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      if (kvm_enabled()) {
          kvm_arm_set_cpu_features_from_host(cpu);
 +        kvm_arm_add_vcpu_properties(obj);
      } else {
          uint64_t t;
          uint32_t u;
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/timer.h"
  #include "qemu/error-report.h"
  #include "qemu/main-loop.h"
 +#include "qom/object.h"
 +#include "qapi/error.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
  #include "sysemu/kvm_int.h"
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
      env->features = arm_host_cpu_features.features;
  }
 +static bool kvm_no_adjvtime_get(Object *obj, Error **errp)
 +{
 +    return !ARM_CPU(obj)->kvm_adjvtime;
 +}
 +
 +static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
 +{
 +    ARM_CPU(obj)->kvm_adjvtime = !value;
 +}
 +
 +/* KVM VCPU properties should be prefixed with "kvm-". */
 +void kvm_arm_add_vcpu_properties(Object *obj)
 +{
 +    if (!kvm_enabled()) {
 +        return;
 +    }
 +
 +    ARM_CPU(obj)->kvm_adjvtime = true;
 +    object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get,
 +                             kvm_no_adjvtime_set, &error_abort);
 +    object_property_set_description(obj, "kvm-no-adjvtime",
 +                                    "Set on to disable the adjustment of "
 +                                    "the virtual counter. VM stopped time "
 +                                    "will be counted.", &error_abort);
 +}
 +
  bool kvm_arm_pmu_supported(CPUState *cpu)
  {
      return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
 diff --git a/target/arm/monitor.c b/target/arm/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/monitor.c
 +++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
      "sve128", "sve256", "sve384", "sve512",
      "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
      "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
 +    "kvm-no-adjvtime",
      NULL
  };
 diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/arm-cpu-features.c
 +++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
      assert_has_feature_enabled(qts, "cortex-a15", "pmu");
      assert_has_not_feature(qts, "cortex-a15", "aarch64");
 +    assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
 +
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
          assert_has_feature_enabled(qts, "max", "aarch64");
          assert_has_feature_enabled(qts, "max", "sve");
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
          return;
      }
-+    assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
+-    /* See AdvSIMDExpandImm() in ARM ARM */
-+
+-    switch (cmode_3_1) {
-     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-         bool kvm_supports_sve;
+-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-         char max_name[8], name[8];
+-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
+-    case 3: /* Replicate(imm8:Zeros(24), 2) */
 -    {
 -        int shift = cmode_3_1 * 8;
 -        imm = bitfield_replicate(abcdefgh << shift, 32);
 -        break;
 -    }
 -    case 4: /* Replicate(Zeros(8):imm8, 4) */
 -    case 5: /* Replicate(imm8:Zeros(8), 4) */
 -    {
 -        int shift = (cmode_3_1 & 0x1) * 8;
 -        imm = bitfield_replicate(abcdefgh << shift, 16);
 -        break;
 -    }
 -    case 6:
 -        if (cmode_0) {
 -            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
 -            imm = (abcdefgh << 16) | 0xffff;
 -        } else {
 -            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
 -            imm = (abcdefgh << 8) | 0xff;
 -        }
 -        imm = bitfield_replicate(imm, 32);
 -        break;
 -    case 7:
 -        if (!cmode_0 && !is_neg) {
 -            imm = bitfield_replicate(abcdefgh, 8);
 -        } else if (!cmode_0 && is_neg) {
 -            int i;
 -            imm = 0;
 -            for (i = 0; i < 8; i++) {
 -                if ((abcdefgh) & (1 << i)) {
 -                    imm |= 0xffULL << (i * 8);
 -                }
 -            }
 -        } else if (cmode_0) {
 -            if (is_neg) {
 -                imm = (abcdefgh & 0x3f) << 48;
 -                if (abcdefgh & 0x80) {
 -                    imm |= 0x8000000000000000ULL;
 -                }
 -                if (abcdefgh & 0x40) {
 -                    imm |= 0x3fc0000000000000ULL;
 -                } else {
 -                    imm |= 0x4000000000000000ULL;
 -                }
 -            } else {
 -                if (o2) {
 -                    /* FMOV (vector, immediate) - half-precision */
 -                    imm = vfp_expand_imm(MO_16, abcdefgh);
 -                    /* now duplicate across the lanes */
 -                    imm = bitfield_replicate(imm, 16);
 -                } else {
 -                    imm = (abcdefgh & 0x3f) << 19;
 -                    if (abcdefgh & 0x80) {
 -                        imm |= 0x80000000;
 -                    }
 -                    if (abcdefgh & 0x40) {
 -                        imm |= 0x3e000000;
 -                    } else {
 -                        imm |= 0x40000000;
 -                    }
 -                    imm |= (imm << 32);
 -                }
 -            }
 -        }
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -
 -    if (cmode_3_1 != 7 && is_neg) {
 -        imm = ~imm;
 +    if (cmode == 15 && o2 && !is_neg) {
 +        /* FMOV (vector, immediate) - half-precision */
 +        imm = vfp_expand_imm(MO_16, abcdefgh);
 +        /* now duplicate across the lanes */
 +        imm = bitfield_replicate(imm, 16);
 +    } else {
 +        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
      }
      if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/arm-cpu-features.rst
+--- a/target/arm/translate.c
-+++ b/docs/arm-cpu-features.rst
++++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ supporting the feature or only supporting the feature under certain
+@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
- configurations.  For example, the `aarch64` CPU feature, which, when
+     case 14:
- disabled, enables the optional AArch32 CPU feature, is only supported
+         if (op) {
- when using the KVM accelerator and when running on a host CPU type that
+             /*
--supports the feature.
+-             * This is the only case where the top and bottom 32 bits
-+supports the feature.  While `aarch64` currently only works with KVM,
+-             * of the encoded constant differ.
-+it could work with TCG.  CPU features that are specific to KVM are
++             * This and cmode == 15 op == 1 are the only cases where
-+prefixed with "kvm-" and are described in "KVM VCPU Features".
++             * the top and bottom 32 bits of the encoded constant differ.
+              */
- CPU Feature Probing
+             uint64_t imm64 = 0;
- ===================
+             int n;
-@@ -XXX,XX +XXX,XX @@ disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
+@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
- properties have special semantics (see "SVE CPU Property Parsing
+         imm |= (imm << 8) | (imm << 16) | (imm << 24);
- Semantics").
+         break;
+     case 15:
-+KVM VCPU Features
++        if (op) {
-+=================
++            /* Reserved encoding for AArch32; valid for AArch64 */
-+
++            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
-+KVM VCPU features are CPU features that are specific to KVM, such as
++            if (imm & 0x80) {
-+paravirt features or features that enable CPU virtualization extensions.
++                imm64 |= 0x8000000000000000ULL;
-+The features' CPU properties are only available when KVM is enabled and
++            }
-+are named with the prefix "kvm-".  KVM VCPU features may be probed,
++            if (imm & 0x40) {
-+enabled, and disabled in the same way as other CPU features.  Below is
++                imm64 |= 0x3fc0000000000000ULL;
-+the list of KVM VCPU features and their descriptions.
++            } else {
-+
++                imm64 |= 0x4000000000000000ULL;
-+  kvm-no-adjvtime          By default kvm-no-adjvtime is disabled.  This
++            }
-+                           means that by default the virtual time
++            return imm64;
-+                           adjustment is enabled (vtime is *not not*
++        }
-+                           adjusted).
+         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-+
+             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-+                           When virtual time adjustment is enabled each
+         break;
 +                           time the VM transitions back to running state
 +                           the VCPU's virtual counter is updated to ensure
 +                           stopped time is not counted.  This avoids time
 +                           jumps surprising guest OSes and applications,
 +                           as long as they use the virtual counter for
 +                           timekeeping.  However it has the side effect of
 +                           the virtual and physical counters diverging.
 +                           All timekeeping based on the virtual counter
 +                           will appear to lag behind any timekeeping that
 +                           does not subtract VM stopped time.  The guest
 +                           may resynchronize its virtual counter with
 +                           other time sources as needed.
 +
 +                           Enable kvm-no-adjvtime to disable virtual time
 +                           adjustment, also restoring the legacy (pre-5.0)
 +                           behavior.
 +
  SVE CPU Properties
  ==================
 --
 .20.1

-[PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
+[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
-The num-lines property of the TYPE_OR_GATE device sets the number
+Use dup_const() instead of bitfield_replicate() in
-of input lines it has. An assert() in or_irq_realize() restricts
+disas_simd_mod_imm().
 this to the maximum supported by the implementation. However we
 got the condition in the assert wrong: it should be using <=,
 because num-lines == MAX_OR_LINES is permitted, and means that
 all entries from 0 to MAX_OR_LINES-1 in the s->levels[] array
 are used.
-We didn't notice this previously because no user has so far
+(We can't replace the other use of bitfield_replicate() in this file,
-needed that many input lines.
+in logic_imm_decode_wmask(), because that location needs to handle 2
 and 4 bit elements, which dup_const() cannot.)
-Reported-by: Guenter Roeck <linux@roeck-us.net>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
 Message-id: 20200120142235.10432-1-peter.maydell@linaro.org
 ---
- hw/core/or-irq.c | 2 +-
+ target/arm/translate-a64.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/or-irq.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/core/or-irq.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
- {
+         /* FMOV (vector, immediate) - half-precision */
-     qemu_or_irq *s = OR_IRQ(dev);
+         imm = vfp_expand_imm(MO_16, abcdefgh);
+         /* now duplicate across the lanes */
--    assert(s->num_lines < MAX_OR_LINES);
+-        imm = bitfield_replicate(imm, 16);
-+    assert(s->num_lines <= MAX_OR_LINES);
++        imm = dup_const(MO_16, imm);
+     } else {
-     qdev_init_gpio_in(dev, or_irq_handler, s->num_lines);
+         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
- }
+     }
 --
 .20.1

-[PULL 17/26] docs/devel/reset.rst: add doc about Resettable interface
+[PULL 12/24] target/arm: Implement MVE logical immediate insns
-From: Damien Hedde <damien.hedde@greensocs.com>
+Implement the MVE logical-immediate insns (VMOV, VMVN,
 VORR and VBIC). These have essentially the same encoding
 as their Neon equivalents, and we implement the decode
 in the same way.
-Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200123132823.1117486-10-damien.hedde@greensocs.com
+Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/devel/index.rst |   1 +
+ target/arm/helper-mve.h    |  4 +++
- docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++++++
+ target/arm/mve.decode      | 17 +++++++++++++
-files changed, 290 insertions(+)
+ target/arm/mve_helper.c    | 24 ++++++++++++++++++
- create mode 100644 docs/devel/reset.rst
+ target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 files changed, 95 insertions(+)
-diff --git a/docs/devel/index.rst b/docs/devel/index.rst
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/devel/index.rst
+--- a/target/arm/helper-mve.h
-+++ b/docs/devel/index.rst
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ Contents:
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
-    tcg
+ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
-    tcg-plugins
+ DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
-    bitops
+ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
-+   reset
++
-diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
++DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
-new file mode 100644
++DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-index XXXXXXX..XXXXXXX
++DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
---- /dev/null
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-+++ b/docs/devel/reset.rst
+index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
 @@ -XXX,XX +XXX,XX @@
+ # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
+ %size_28 28:1 !function=plus_1
++# 1imm format immediate
++%imm_28_16_0 28:1 16:3 0:4
 +
-+=======================================
+ &vldr_vstr rn qd imm p a w size l u
-+Reset in QEMU: the Resettable interface
+ &1op qd qm size
-+=======================================
+ &2op qd qm qn size
  &2scalar qd qn rm size
 +&1imm qd imm cmode op
  @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
  # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
  @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
  @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
       size=%size_28
 +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
  # The _rev suffix indicates that Vn and Vm are reversed. This is
  # the case for shifts. In the Arm ARM these insns are documented
@@ -XXX,XX +XXX,XX @@ VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
  # Predicate operations
  %mask_22_13      22:1 13:3
  VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 +
-+The reset of qemu objects is handled using the resettable interface declared
++# Logical immediate operations (1 reg and modified-immediate)
 +in ``include/hw/resettable.h``.
 +
-+This interface allows objects to be grouped (on a tree basis); so that the
++# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
-+whole group can be reset consistently. Each individual member object does not
++# not in a way we can conveniently represent in decodetree without
-+have to care about others; in particular, problems of order (which object is
++# a lot of repetition:
-+reset first) are addressed.
++# VORR: op=0, (cmode & 1) && cmode < 12
-+
++# VBIC: op=1, (cmode & 1) && cmode < 12
-+As of now DeviceClass and BusClass implement this interface.
++# VMOV: everything else
-+
++# So we have a single decode line and check the cmode/op in the
-+
++# trans function.
-+Triggering reset
++Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-+----------------
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-+
+index XXXXXXX..XXXXXXX 100644
-+This section documents the APIs which "users" of a resettable object should use
+--- a/target/arm/mve_helper.c
-+to control it. All resettable control functions must be called while holding
++++ b/target/arm/mve_helper.c
-+the iothread lock.
+@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
-+
+ DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
-+You can apply a reset to an object using ``resettable_assert_reset()``. You need
+ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
-+to call ``resettable_release_reset()`` to release the object from reset. To
-+instantly reset an object, without keeping it in reset state, just call
++/*
-+``resettable_reset()``. These functions take two parameters: a pointer to the
++ * 1 operand immediates: Vda is destination and possibly also one source.
-+object to reset and a reset type.
++ * All these insns work at 64-bit widths.
-+
++ */
-+Several types of reset will be supported. For now only cold reset is defined;
++#define DO_1OP_IMM(OP, FN)                                              \
-+others may be added later. The Resettable interface handles reset types with an
++    void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm)    \
-+enum:
++    {                                                                   \
-+
++        uint64_t *da = vda;                                             \
-+``RESET_TYPE_COLD``
++        uint16_t mask = mve_element_mask(env);                          \
-+  Cold reset is supported by every resettable object. In QEMU, it means we reset
++        unsigned e;                                                     \
-+  to the initial state corresponding to the start of QEMU; this might differ
++        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
-+  from what is a real hardware cold reset. It differs from other resets (like
++            mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask);            \
-+  warm or bus resets) which may keep certain parts untouched.
++        }                                                               \
-+
++        mve_advance_vpt(env);                                           \
 +Calling ``resettable_reset()`` is equivalent to calling
 +``resettable_assert_reset()`` then ``resettable_release_reset()``. It is
 +possible to interleave multiple calls to these three functions. There may
 +be several reset sources/controllers of a given object. The interface handles
 +everything and the different reset controllers do not need to know anything
 +about each others. The object will leave reset state only when each other
 +controllers end their reset operation. This point is handled internally by
 +maintaining a count of in-progress resets; it is crucial to call
 +``resettable_release_reset()`` one time and only one time per
 +``resettable_assert_reset()`` call.
 +
 +For now migration of a device or bus in reset is not supported. Care must be
 +taken not to delay ``resettable_release_reset()`` after its
 +``resettable_assert_reset()`` counterpart.
 +
 +Note that, since resettable is an interface, the API takes a simple Object as
 +parameter. Still, it is a programming error to call a resettable function on a
 +non-resettable object and it will trigger a run time assert error. Since most
 +calls to resettable interface are done through base class functions, such an
 +error is not likely to happen.
 +
 +For Devices and Buses, the following helper functions exist:
 +
 +- ``device_cold_reset()``
 +- ``bus_cold_reset()``
 +
 +These are simple wrappers around resettable_reset() function; they only cast the
 +Device or Bus into an Object and pass the cold reset type. When possible
 +prefer to use these functions instead of ``resettable_reset()``.
 +
 +Device and bus functions co-exist because there can be semantic differences
 +between resetting a bus and resetting the controller bridge which owns it.
 +For example, consider a SCSI controller. Resetting the controller puts all
 +its registers back to what reset state was as well as reset everything on the
 +SCSI bus, whereas resetting just the SCSI bus only resets everything that's on
 +it but not the controller.
 +
 +
 +Multi-phase mechanism
 +---------------------
 +
 +This section documents the internals of the resettable interface.
 +
 +The resettable interface uses a multi-phase system to relieve objects and
 +machines from reset ordering problems. To address this, the reset operation
 +of an object is split into three well defined phases.
 +
 +When resetting several objects (for example the whole machine at simulation
 +startup), all first phases of all objects are executed, then all second phases
 +and then all third phases.
 +
 +The three phases are:
 +
 +1. The **enter** phase is executed when the object enters reset. It resets only
 +   local state of the object; it must not do anything that has a side-effect
 +   on other objects, such as raising or lowering a qemu_irq line or reading or
 +   writing guest memory.
 +
 +2. The **hold** phase is executed for entry into reset, once every object in the
 +   group which is being reset has had its *enter* phase executed. At this point
 +   devices can do actions that affect other objects.
 +
 +3. The **exit** phase is executed when the object leaves the reset state.
 +   Actions affecting other objects are permitted.
 +
 +As said in previous section, the interface maintains a count of reset. This
 +count is used to ensure phases are executed only when required. *enter* and
 +*hold* phases are executed only when asserting reset for the first time
 +(if an object is already in reset state when calling
 +``resettable_assert_reset()`` or ``resettable_reset()``, they are not
 +executed).
 +The *exit* phase is executed only when the last reset operation ends. Therefore
 +the object does not need to care how many of reset controllers it has and how
 +many of them have started a reset.
 +
 +
 +Handling reset in a resettable object
 +-------------------------------------
 +
 +This section documents the APIs that an implementation of a resettable object
 +must provide and what functions it has access to. It is intended for people
 +who want to implement or convert a class which has the resettable interface;
 +for example when specializing an existing device or bus.
 +
 +Methods to implement
 +....................
 +
 +Three methods should be defined or left empty. Each method corresponds to a
 +phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
 +``phases.exit()``. They all take the object as parameter. The *enter* method
 +also take the reset type as second parameter.
 +
 +When extending an existing class, these methods may need to be extended too.
 +The ``resettable_class_set_parent_phases()`` class function may be used to
 +backup parent class methods.
 +
 +Here follows an example to implement reset for a Device which sets an IO while
 +in reset.
 +
 +::
 +
 +    static void mydev_reset_enter(Object *obj, ResetType type)
 +    {
 +        MyDevClass *myclass = MYDEV_GET_CLASS(obj);
 +        MyDevState *mydev = MYDEV(obj);
 +        /* call parent class enter phase */
 +        if (myclass->parent_phases.enter) {
 +            myclass->parent_phases.enter(obj, type);
 +        }
 +        /* initialize local state only */
 +        mydev->var = 0;
 +    }
 +
-+    static void mydev_reset_hold(Object *obj)
++#define DO_MOVI(N, I) (I)
-+    {
++#define DO_ANDI(N, I) ((N) & (I))
-+        MyDevClass *myclass = MYDEV_GET_CLASS(obj);
++#define DO_ORRI(N, I) ((N) | (I))
-+        MyDevState *mydev = MYDEV(obj);
++
-+        /* call parent class hold phase */
++DO_1OP_IMM(vmovi, DO_MOVI)
-+        if (myclass->parent_phases.hold) {
++DO_1OP_IMM(vandi, DO_ANDI)
-+            myclass->parent_phases.hold(obj);
++DO_1OP_IMM(vorri, DO_ORRI)
-+        }
++
-+        /* set an IO */
+ #define DO_2OP(OP, ESIZE, TYPE, FN)                                     \
-+        qemu_set_irq(mydev->irq, 1);
+     void HELPER(glue(mve_, OP))(CPUARMState *env,                       \
                                  void *vd, void *vn, void *vm)           \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
  /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
  static inline long mve_qreg_offset(unsigned reg)
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      mve_update_eci(s);
      return true;
  }
 +
 +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
 +{
 +    TCGv_ptr qd;
 +    uint64_t imm;
 +
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd) ||
 +        !fn) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    static void mydev_reset_exit(Object *obj)
++    imm = asimd_imm_const(a->imm, a->cmode, a->op);
-+    {
++
-+        MyDevClass *myclass = MYDEV_GET_CLASS(obj);
++    qd = mve_qreg_ptr(a->qd);
-+        MyDevState *mydev = MYDEV(obj);
++    fn(cpu_env, qd, tcg_constant_i64(imm));
-+        /* call parent class exit phase */
++    tcg_temp_free_ptr(qd);
-+        if (myclass->parent_phases.exit) {
++    mve_update_eci(s);
-+            myclass->parent_phases.exit(obj);
++    return true;
 +}
 +
 +static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
 +{
 +    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
 +    MVEGenOneOpImmFn *fn;
 +
 +    if ((a->cmode & 1) && a->cmode < 12) {
 +        if (a->op) {
 +            /*
 +             * For op=1, the immediate will be inverted by asimd_imm_const(),
 +             * so the VBIC becomes a logical AND operation.
 +             */
 +            fn = gen_helper_mve_vandi;
 +        } else {
 +            fn = gen_helper_mve_vorri;
 +        }
-+        /* clear an IO */
++    } else {
-+        qemu_set_irq(mydev->irq, 0);
++        /* There is one unallocated cmode/op combination in this space */
 +        if (a->cmode == 15 && a->op == 1) {
 +            return false;
 +        }
 +        /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
 +        fn = gen_helper_mve_vmovi;
 +    }
-+
++    return do_1imm(s, a, fn);
-+    typedef struct MyDevClass {
++}
 +        MyParentClass parent_class;
 +        /* to store eventual parent reset methods */
 +        ResettablePhases parent_phases;
 +    } MyDevClass;
 +
 +    static void mydev_class_init(ObjectClass *class, void *data)
 +    {
 +        MyDevClass *myclass = MYDEV_CLASS(class);
 +        ResettableClass *rc = RESETTABLE_CLASS(class);
 +        resettable_class_set_parent_reset_phases(rc,
 +                                                 mydev_reset_enter,
 +                                                 mydev_reset_hold,
 +                                                 mydev_reset_exit,
 +                                                 &myclass->parent_phases);
 +    }
 +
 +In the above example, we override all three phases. It is possible to override
 +only some of them by passing NULL instead of a function pointer to
 +``resettable_class_set_parent_reset_phases()``. For example, the following will
 +only override the *enter* phase and leave *hold* and *exit* untouched::
 +
 +    resettable_class_set_parent_reset_phases(rc, mydev_reset_enter,
 +                                             NULL, NULL,
 +                                             &myclass->parent_phases);
 +
 +This is equivalent to providing a trivial implementation of the hold and exit
 +phases which does nothing but call the parent class's implementation of the
 +phase.
 +
 +Polling the reset state
 +.......................
 +
 +Resettable interface provides the ``resettable_is_in_reset()`` function.
 +This function returns true if the object parameter is currently under reset.
 +
 +An object is under reset from the beginning of the *init* phase to the end of
 +the *exit* phase. During all three phases, the function will return that the
 +object is in reset.
 +
 +This function may be used if the object behavior has to be adapted
 +while in reset state. For example if a device has an irq input,
 +it will probably need to ignore it while in reset; then it can for
 +example check the reset state at the beginning of the irq callback.
 +
 +Note that until migration of the reset state is supported, an object
 +should not be left in reset. So apart from being currently executing
 +one of the reset phases, the only cases when this function will return
 +true is if an external interaction (like changing an io) is made during
 +*hold* or *exit* phase of another object in the same reset group.
 +
 +Helpers ``device_is_in_reset()`` and ``bus_is_in_reset()`` are also provided
 +for devices and buses and should be preferred.
 +
 +
 +Base class handling of reset
 +----------------------------
 +
 +This section documents parts of the reset mechanism that you only need to know
 +about if you are extending it to work with a new base class other than
 +DeviceClass or BusClass, or maintaining the existing code in those classes. Most
 +people can ignore it.
 +
 +Methods to implement
 +....................
 +
 +There are two other methods that need to exist in a class implementing the
 +interface: ``get_state()`` and ``child_foreach()``.
 +
 +``get_state()`` is simple. *resettable* is an interface and, as a consequence,
 +does not have any class state structure. But in order to factorize the code, we
 +need one. This method must return a pointer to ``ResettableState`` structure.
 +The structure must be allocated by the base class; preferably it should be
 +located inside the object instance structure.
 +
 +``child_foreach()`` is more complex. It should execute the given callback on
 +every reset child of the given resettable object. All children must be
 +resettable too. Additional parameters (a reset type and an opaque pointer) must
 +be passed to the callback too.
 +
 +In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located
 +``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented
 +to follow the bus hierarchy; for a bus, it calls the function on every child
 +device; for a device, it calls the function on every bus child. When we reset
 +the main system bus, we reset the whole machine bus tree.
 +
 +Changing a resettable parent
 +............................
 +
 +One thing which should be taken care of by the base class is handling reset
 +hierarchy changes.
 +
 +The reset hierarchy is supposed to be static and built during machine creation.
 +But there are actually some exceptions. To cope with this, the resettable API
 +provides ``resettable_change_parent()``. This function allows to set, update or
 +remove the parent of a resettable object after machine creation is done. As
 +parameters, it takes the object being moved, the old parent if any and the new
 +parent if any.
 +
 +This function can be used at any time when not in a reset operation. During
 +a reset operation it must be used only in *hold* phase. Using it in *enter* or
 +*exit* phase is an error.
 +Also it should not be used during machine creation, although it is harmless to
 +do so: the function is a no-op as long as old and new parent are NULL or not
 +in reset.
 +
 +There is currently 2 cases where this function is used:
 +
 +1. *device hotplug*; it means a new device is introduced on a live bus.
 +
 +2. *hot bus change*; it means an existing live device is added, moved or
 +   removed in the bus hierarchy. At the moment, it occurs only in the raspi
 +   machines for changing the sdbus used by sd card.
 --
 .20.1

-[PULL 21/26] target/arm/kvm: trivial: Clean up header documentation
+[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
-From: Andrew Jones <drjones@redhat.com>
+Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
+and VQSHLU.
-Signed-off-by: Andrew Jones <drjones@redhat.com>
-Message-id: 20200120101023.16030-2-drjones@redhat.com
+The size-and-immediate encoding here is the same as Neon, and we
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+handle it the same way neon-dp.decode does.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
 ---
- target/arm/kvm_arm.h | 46 ++++++++++++++++++++++++++------------------
+ target/arm/helper-mve.h    | 16 +++++++++++
-file changed, 27 insertions(+), 19 deletions(-)
+ target/arm/mve.decode      | 23 +++++++++++++++
+ target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
-diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
+ target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
-index XXXXXXX..XXXXXXX 100644
+files changed, 147 insertions(+)
---- a/target/arm/kvm_arm.h
-+++ b/target/arm/kvm_arm.h
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-mve.h
 +++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
  DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 +
 +DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
 @@ -XXX,XX +XXX,XX @@
- int kvm_arm_vcpu_init(CPUState *cs);
+ &2op qd qm qn size
+ &2scalar qd qn rm size
- /**
+ &1imm qd imm cmode op
-- * kvm_arm_vcpu_finalize
++&2shift qd qm shift size
-+ * kvm_arm_vcpu_finalize:
-  * @cs: CPUState
+ @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
-- * @feature: int
+ # Note that both Rn and Qd are 3 bits only (no D bit)
-+ * @feature: feature to finalize
+@@ -XXX,XX +XXX,XX @@
-  *
+ @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
-  * Finalizes the configuration of the specified VCPU feature by
+ @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
-  * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
-@@ -XXX,XX +XXX,XX @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
++@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
- int kvm_arm_init_cpreg_list(ARMCPU *cpu);
++@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
++@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
- /**
++
-- * kvm_arm_reg_syncs_via_cpreg_list
+ # Vector loads and stores
-- * regidx: KVM register index
-+ * kvm_arm_reg_syncs_via_cpreg_list:
+ # Widening loads and narrowing stores:
-+ * @regidx: KVM register index
+@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
-  *
+ # So we have a single decode line and check the cmode/op in the
-  * Return true if this KVM register should be synchronized via the
+ # trans function.
-  * cpreg list of arbitrary system registers, false if it is synchronized
+ Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-@@ -XXX,XX +XXX,XX @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu);
++
- bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx);
++# Shifts by immediate
++
- /**
++VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-- * kvm_arm_cpreg_level
++VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
-- * regidx: KVM register index
++VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
-+ * kvm_arm_cpreg_level:
++
-+ * @regidx: KVM register index
++VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
-  *
++VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
-  * Return the level of this coprocessor/system register.  Return value is
++VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-  * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE.
++
-@@ -XXX,XX +XXX,XX @@ void kvm_arm_init_serror_injection(CPUState *cs);
++VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
-  * @cpu: ARMCPU
++VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
-  *
++VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-  * Get VCPU related state from kvm.
++
-+ *
++VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
-+ * Returns: 0 if success else < 0 error code
++VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
-  */
++VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
- int kvm_get_vcpu_events(ARMCPU *cpu);
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu);
+--- a/target/arm/mve_helper.c
-  * @cpu: ARMCPU
++++ b/target/arm/mve_helper.c
-  *
+@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
-  * Put VCPU related state to kvm.
+     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
-+ *
+ #define DO_UQRSHL_OP(N, M, satp) \
-+ * Returns: 0 if success else < 0 error code
+     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
-  */
++#define DO_SUQSHL_OP(N, M, satp) \
- int kvm_put_vcpu_events(ARMCPU *cpu);
++    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
-@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
+ DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
+ DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
- /**
+@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
-  * kvm_arm_get_host_cpu_features:
+ DO_VADDV(vaddvub, 1, uint8_t)
-- * @ahcc: ARMHostCPUClass to fill in
+ DO_VADDV(vaddvuh, 2, uint16_t)
-+ * @ahcf: ARMHostCPUClass to fill in
+ DO_VADDV(vaddvuw, 4, uint32_t)
-  *
++
-  * Probe the capabilities of the host kernel's preferred CPU and fill
++/* Shifts by immediate */
-  * in the ARMHostCPUClass struct accordingly.
++#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
-+ *
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+ * Returns true on success and false otherwise.
++                                void *vm, uint32_t shift)       \
-  */
++    {                                                           \
- bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
++        TYPE *d = vd, *m = vm;                                  \
++        uint16_t mask = mve_element_mask(env);                  \
-@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
++        unsigned e;                                             \
- bool kvm_arm_aarch32_supported(CPUState *cs);
++        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
++            mergemask(&d[H##ESIZE(e)],                          \
- /**
++                      FN(m[H##ESIZE(e)], shift), mask);         \
-- * bool kvm_arm_pmu_supported:
++        }                                                       \
-+ * kvm_arm_pmu_supported:
++        mve_advance_vpt(env);                                   \
-  * @cs: CPUState
++    }
-  *
++
-  * Returns: true if the KVM VCPU can enable its PMU
++#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
- bool kvm_arm_pmu_supported(CPUState *cs);
++                                void *vm, uint32_t shift)       \
++    {                                                           \
- /**
++        TYPE *d = vd, *m = vm;                                  \
-- * bool kvm_arm_sve_supported:
++        uint16_t mask = mve_element_mask(env);                  \
-+ * kvm_arm_sve_supported:
++        unsigned e;                                             \
-  * @cs: CPUState
++        bool qc = false;                                        \
-  *
++        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
-  * Returns true if the KVM VCPU can enable SVE and false otherwise.
++            bool sat = false;                                   \
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_pmu_supported(CPUState *cs);
++            mergemask(&d[H##ESIZE(e)],                          \
- bool kvm_arm_sve_supported(CPUState *cs);
++                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
++            qc |= sat & mask & 1;                               \
- /**
++        }                                                       \
-- * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
++        if (qc) {                                               \
-- * IPA address space supported by KVM
++            env->vfp.qc[0] = qc;                                \
-- *
++        }                                                       \
-+ * kvm_arm_get_max_vm_ipa_size:
++        mve_advance_vpt(env);                                   \
-  * @ms: Machine state handle
++    }
-+ *
++
-+ * Returns the number of bits in the IPA address space supported by KVM
++/* provide unsigned 2-op shift helpers for all sizes */
-  */
++#define DO_2SHIFT_U(OP, FN)                     \
- int kvm_arm_get_max_vm_ipa_size(MachineState *ms);
++    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
++    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
- /**
++    DO_2SHIFT(OP##w, 4, uint32_t, FN)
-- * kvm_arm_sync_mpstate_to_kvm
++
-+ * kvm_arm_sync_mpstate_to_kvm:
++#define DO_2SHIFT_SAT_U(OP, FN)                 \
-  * @cpu: ARMCPU
++    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
-  *
++    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
-  * If supported set the KVM MP_STATE based on QEMU's model.
++    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
-+ *
++#define DO_2SHIFT_SAT_S(OP, FN)                 \
-+ * Returns 0 on success and -1 on failure.
++    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
-  */
++    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
- int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu);
++    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
++
- /**
++DO_2SHIFT_U(vshli_u, DO_VSHLU)
-- * kvm_arm_sync_mpstate_to_qemu
++DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
-+ * kvm_arm_sync_mpstate_to_qemu:
++DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
-  * @cpu: ARMCPU
++DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
-  *
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-  * If supported get the MP_STATE from KVM and store in QEMU's model.
+index XXXXXXX..XXXXXXX 100644
-+ *
+--- a/target/arm/translate-mve.c
-+ * Returns 0 on success and aborts on failure.
++++ b/target/arm/translate-mve.c
-  */
+@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
- int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
+ typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
-@@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
+ typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
++typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
- static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
+ typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
- {
+ typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
--    /* This should never actually be called in the "not KVM" case,
+ typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
      }
      return do_1imm(s, a, fn);
  }
 +
 +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
 +                      bool negateshift)
 +{
 +    TCGv_ptr qd, qm;
 +    int shift = a->shift;
 +
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd | a->qm) ||
 +        !fn) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
-+     * This should never actually be called in the "not KVM" case,
++     * When we handle a right shift insn using a left-shift helper
-      * but set up the fields to indicate an error anyway.
++     * which permits a negative shift count to indicate a right-shift,
-      */
++     * we must negate the shift count.
-     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
++     */
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit);
++    if (negateshift) {
-  *
++        shift = -shift;
-  * Return: TRUE if any hardware breakpoints in use.
++    }
-  */
++
--
++    qd = mve_qreg_ptr(a->qd);
- bool kvm_arm_hw_debug_active(CPUState *cs);
++    qm = mve_qreg_ptr(a->qm);
++    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
- /**
++    tcg_temp_free_ptr(qd);
-  * kvm_arm_copy_hw_debug_data:
++    tcg_temp_free_ptr(qm);
-- *
++    mve_update_eci(s);
-  * @ptr: kvm_guest_debug_arch structure
++    return true;
-  *
++}
-  * Copy the architecture specific debug registers into the
++
-  * kvm_guest_debug ioctl structure.
++#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
-  */
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
- struct kvm_guest_debug_arch;
++    {                                                           \
--
++        static MVEGenTwoOpShiftFn * const fns[] = {             \
- void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
++            gen_helper_mve_##FN##b,                             \
++            gen_helper_mve_##FN##h,                             \
- /**
++            gen_helper_mve_##FN##w,                             \
-- * its_class_name
++            NULL,                                               \
-+ * its_class_name:
++        };                                                      \
-  *
++        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
-  * Return the ITS class name to use depending on whether KVM acceleration
++    }
-  * and KVM CAP_SIGNAL_MSI are supported
++
 +DO_2SHIFT(VSHLI, vshli_u, false)
 +DO_2SHIFT(VQSHLI_S, vqshli_s, false)
 +DO_2SHIFT(VQSHLI_U, vqshli_u, false)
 +DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 --
 .20.1

-[PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0
+[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
-From: Cédric Le Goater <clg@kaod.org>
+Implement the MVE vector shift right by immediate insns VSHRI and
 VRSHRI.  As with Neon, we implement these by using helper functions
 which perform left shifts but allow negative shift counts to indicate
 right shifts.
-The overhead for the OpenBMC firmware images using the a custom U-Boot
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-is around 2 seconds, which is fine, but with a U-Boot from mainline,
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-it takes an extra 50 seconds or so to reach Linux. A quick survey on
+Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
-the number of reads performed on the flash memory region gives the
+---
-following figures :
+ target/arm/helper-mve.h     | 12 ++++++++++++
  target/arm/translate.h      | 20 ++++++++++++++++++++
  target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
  target/arm/mve_helper.c     |  7 +++++++
  target/arm/translate-mve.c  |  5 +++++
  target/arm/translate-neon.c | 18 ------------------
 files changed, 72 insertions(+), 18 deletions(-)
-  OpenBMC U-Boot      922478 (~ 3.5 MBytes)
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
   Mainline U-Boot   20569977 (~ 80  MBytes)
 QEMU must be trashing the TCG TBs and reloading text very often. Some
 addresses are read more than 250.000 times. Until we find a solution
 to improve boot time, execution from MMIO is not activated by default.
 Setting this option also breaks migration compatibility.
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200114103433.30534-5-clg@kaod.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/aspeed.h |  2 ++
  hw/arm/aspeed.c         | 44 ++++++++++++++++++++++++++++++++++++-----
 files changed, 41 insertions(+), 5 deletions(-)
 diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed.h
+--- a/target/arm/helper-mve.h
-+++ b/include/hw/arm/aspeed.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardState AspeedBoardState;
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
- typedef struct AspeedMachine {
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-     MachineState parent_obj;
 +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
-+    bool mmio_exec;
+ DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- } AspeedMachine;
+ DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #define ASPEED_MACHINE_CLASS(klass) \
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+ DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
+--- a/target/arm/translate.h
-+++ b/hw/arm/aspeed.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
-          * SoC and 128MB for the AST2500 SoC, which is twice as big as
+     return x * 2 + 1;
           * needed by the flash modules of the Aspeed machines.
           */
 -        memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
 -                               fl->size, &error_abort);
 -        memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 -                                    boot_rom);
 -        write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
 +        if (ASPEED_MACHINE(machine)->mmio_exec) {
 +            memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
 +                                     &fl->mmio, 0, fl->size);
 +            memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 +                                        boot_rom);
 +        } else {
 +            memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
 +                                   fl->size, &error_abort);
 +            memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 +                                        boot_rom);
 +            write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
 +        }
      }
      aspeed_board_binfo.ram_size = ram_size;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
      /* Bus 11: TODO ucd90160@64 */
  }
-+static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
++static inline int rsub_64(DisasContext *s, int x)
 +{
-+    return ASPEED_MACHINE(obj)->mmio_exec;
++    return 64 - x;
 +}
 +
-+static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
++static inline int rsub_32(DisasContext *s, int x)
 +{
-+    ASPEED_MACHINE(obj)->mmio_exec = value;
++    return 32 - x;
 +}
 +
-+static void aspeed_machine_instance_init(Object *obj)
++static inline int rsub_16(DisasContext *s, int x)
 +{
-+    ASPEED_MACHINE(obj)->mmio_exec = false;
++    return 16 - x;
 +}
 +
-+static void aspeed_machine_class_props_init(ObjectClass *oc)
++static inline int rsub_8(DisasContext *s, int x)
 +{
-+    object_class_property_add_bool(oc, "execute-in-place",
++    return 8 - x;
 +                                   aspeed_get_mmio_exec,
 +                                   aspeed_set_mmio_exec, &error_abort);
 +    object_class_property_set_description(oc, "execute-in-place",
 +                           "boot directly from CE0 flash device", &error_abort);
 +}
 +
- static void aspeed_machine_class_init(ObjectClass *oc, void *data)
+ static inline int arm_dc_feature(DisasContext *dc, int feature)
  {
-     MachineClass *mc = MACHINE_CLASS(oc);
+     return (dc->features & (1ULL << feature)) != 0;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-     mc->no_floppy = 1;
+index XXXXXXX..XXXXXXX 100644
-     mc->no_cdrom = 1;
+--- a/target/arm/mve.decode
-     mc->no_parallel = 1;
++++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
  @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 +# Right shifts are encoded as N - shift, where N is the element size in bits.
 +%rshift_i5  16:5 !function=rsub_32
 +%rshift_i4  16:4 !function=rsub_16
 +%rshift_i3  16:3 !function=rsub_8
 +
-+    aspeed_machine_class_props_init(oc);
++@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=0 shift=%rshift_i3
 +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=1 shift=%rshift_i4
 +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=2 shift=%rshift_i5
 +
  # Vector loads and stores
  # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 +
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
      DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
      DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_S(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, int8_t, FN)             \
 +    DO_2SHIFT(OP##h, 2, int16_t, FN)            \
 +    DO_2SHIFT(OP##w, 4, int32_t, FN)
  #define DO_2SHIFT_SAT_U(OP, FN)                 \
      DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
  DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_S(vshli_s, DO_VSHLS)
  DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
  DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 +DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 +DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
  DO_2SHIFT(VQSHLI_S, vqshli_s, false)
  DO_2SHIFT(VQSHLI_U, vqshli_u, false)
  DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 +/* These right shifts use a left-shift helper with negated shift count */
 +DO_2SHIFT(VSHRI_S, vshli_s, true)
 +DO_2SHIFT(VSHRI_U, vshli_u, true)
 +DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 +DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
      return x + 1;
  }
- static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
+-static inline int rsub_64(DisasContext *s, int x)
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
+-{
-         .name          = TYPE_ASPEED_MACHINE,
+-    return 64 - x;
-         .parent        = TYPE_MACHINE,
+-}
-         .instance_size = sizeof(AspeedMachine),
+-
-+        .instance_init = aspeed_machine_instance_init,
+-static inline int rsub_32(DisasContext *s, int x)
-         .class_size    = sizeof(AspeedMachineClass),
+-{
-         .class_init    = aspeed_machine_class_init,
+-    return 32 - x;
-         .abstract      = true,
+-}
 -static inline int rsub_16(DisasContext *s, int x)
 -{
 -    return 16 - x;
 -}
 -static inline int rsub_8(DisasContext *s, int x)
 -{
 -    return 8 - x;
 -}
 -
  static inline int neon_3same_fp_size(DisasContext *s, int x)
  {
      /* Convert 0==fp32, 1==fp16 into a MO_* value */
 --
 .20.1

-[PULL 25/26] target/arm/kvm: Implement virtual time adjustment
+[PULL 15/24] target/arm: Implement MVE VSHLL
-From: Andrew Jones <drjones@redhat.com>
+Implement the MVE VHLL (vector shift left long) insn.  This has two
 encodings: the T1 encoding is the usual shift-by-immediate format,
 and the T2 encoding is a special case where the shift count is always
 equal to the element size.
-When a VM is stopped (such as when it's paused) guest virtual time
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-should stop counting. Otherwise, when the VM is resumed it will
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-experience time jumps and its kernel may report soft lockups. Not
+Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
-counting virtual time while the VM is stopped has the side effect
+---
-of making the guest's time appear to lag when compared with real
+ target/arm/helper-mve.h    |  9 +++++++
-time, and even with time derived from the physical counter. For
+ target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
-this reason, this change, which is enabled by default, comes with
+ target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
-a KVM CPU feature allowing it to be disabled, restoring legacy
+ target/arm/translate-mve.c | 15 +++++++++++
-behavior.
+files changed, 105 insertions(+), 4 deletions(-)
-This patch only provides the implementation of the virtual time
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 adjustment. A subsequent patch will provide the CPU property
 allowing the change to be enabled and disabled.
 Reported-by: Bijan Mottahedeh <bijan.mottahedeh@oracle.com>
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Message-id: 20200120101023.16030-6-drjones@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h     |  7 ++++
  target/arm/kvm_arm.h | 38 ++++++++++++++++++
  target/arm/kvm.c     | 92 ++++++++++++++++++++++++++++++++++++++++++++
  target/arm/kvm32.c   |  3 ++
  target/arm/kvm64.c   |  3 ++
  target/arm/machine.c |  7 ++++
 files changed, 150 insertions(+)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/cpu.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     /* KVM init features for this CPU */
+ DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     uint32_t kvm_init_features[7];
+ DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +    /* KVM CPU state */
 +
-+    /* KVM virtual time adjustment */
++DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    bool kvm_adjvtime;
++DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    bool kvm_vtime_dirty;
++DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    uint64_t kvm_vtime;
++DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
  @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
 +@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 +# VSHLL encoding T2 where shift == esize
 +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
 +                qd=%qd qm=%qm size=0 shift=8
 +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
 +                qd=%qd qm=%qm size=1 shift=16
 +
-     /* Uniprocessor system with MP extensions */
+ # Right shifts are encoded as N - shift, where N is the element size in bits.
-     bool mp_is_up;
+ %rshift_i5  16:5 !function=rsub_32
+ %rshift_i4  16:4 !function=rsub_16
-diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
+@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
-index XXXXXXX..XXXXXXX 100644
+ VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
---- a/target/arm/kvm_arm.h
+ VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
-+++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level);
+-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-  */
+-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
- bool write_kvmstate_to_list(ARMCPU *cpu);
++# The VSHLL T2 encoding is not a @2op pattern, but is here because it
++# overlaps what would be size=0b11 VMULH/VRMULH
 +/**
 + * kvm_arm_cpu_pre_save:
 + * @cpu: ARMCPU
 + *
 + * Called after write_kvmstate_to_list() from cpu_pre_save() to update
 + * the cpreg list with KVM CPU state.
 + */
 +void kvm_arm_cpu_pre_save(ARMCPU *cpu);
 +
 +/**
 + * kvm_arm_cpu_post_load:
 + * @cpu: ARMCPU
 + *
 + * Called from cpu_post_load() to update KVM CPU state from the cpreg list.
 + */
 +void kvm_arm_cpu_post_load(ARMCPU *cpu);
 +
  /**
   * kvm_arm_reset_vcpu:
   * @cpu: ARMCPU
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu);
   */
  int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
 +/**
 + * kvm_arm_get_virtual_time:
 + * @cs: CPUState
 + *
 + * Gets the VCPU's virtual counter and stores it in the KVM CPU state.
 + */
 +void kvm_arm_get_virtual_time(CPUState *cs);
 +
 +/**
 + * kvm_arm_put_virtual_time:
 + * @cs: CPUState
 + *
 + * Sets the VCPU's virtual counter to the value stored in the KVM CPU state.
 + */
 +void kvm_arm_put_virtual_time(CPUState *cs);
 +
 +void kvm_arm_vm_state_change(void *opaque, int running, RunState state);
 +
  int kvm_arm_vgic_probe(void);
  void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
  static inline void kvm_arm_pmu_init(CPUState *cs) {}
  static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
 +
 +static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
 +static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
  #endif
  static inline const char *gic_class_name(void)
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static int compare_u64(const void *a, const void *b)
      return 0;
  }
 +/*
 + * cpreg_values are sorted in ascending order by KVM register ID
 + * (see kvm_arm_init_cpreg_list). This allows us to cheaply find
 + * the storage for a KVM register by ID with a binary search.
 + */
 +static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx)
 +{
-+    uint64_t *res;
++  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+
++  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+    res = bsearch(&regidx, cpu->cpreg_indexes, cpu->cpreg_array_len,
-+                  sizeof(uint64_t), compare_u64);
+-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+    assert(res);
+-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+
++  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +    return &cpu->cpreg_values[res - cpu->cpreg_indexes];
 +}
 +
- /* Initialize the ARMCPU cpreg list according to the kernel's
-  * definition of what CPU registers it knows about (and throw away
-  * the previous TCG-created cpreg list).
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
-     return ok;
- }
-+void kvm_arm_cpu_pre_save(ARMCPU *cpu)
 +{
-+    /* KVM virtual time adjustment */
++  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+    if (cpu->kvm_vtime_dirty) {
++  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+        *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime;
++
-+    }
++  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +}
 +
-+void kvm_arm_cpu_post_load(ARMCPU *cpu)
 +{
-+    /* KVM virtual time adjustment */
++  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+    if (cpu->kvm_adjvtime) {
++  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+        cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT);
++
-+        cpu->kvm_vtime_dirty = true;
++  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +    }
 +}
 +
- void kvm_arm_reset_vcpu(ARMCPU *cpu)
- {
-     int ret;
-@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
-     return 0;
- }
-+void kvm_arm_get_virtual_time(CPUState *cs)
 +{
-+    ARMCPU *cpu = ARM_CPU(cs);
++  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+    struct kvm_one_reg reg = {
++  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
 +        .id = KVM_REG_ARM_TIMER_CNT,
 +        .addr = (uintptr_t)&cpu->kvm_vtime,
 +    };
 +    int ret;
 +
-+    if (cpu->kvm_vtime_dirty) {
++  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+        return;
++}
  VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
  VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
 +VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +
 +/*
 + * Long shifts taking half-sized inputs from top or bottom of the input
 + * vector and producing a double-width result. ESIZE, TYPE are for
 + * the input, and LESIZE, LTYPE for the output.
 + * Unlike the normal shift helpers, we do not handle negative shift counts,
 + * because the long shift is strictly left-only.
 + */
 +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
 +                                void *vm, uint32_t shift)               \
 +    {                                                                   \
 +        LTYPE *d = vd;                                                  \
 +        TYPE *m = vm;                                                   \
 +        uint16_t mask = mve_element_mask(env);                          \
 +        unsigned le;                                                    \
 +        assert(shift <= 16);                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
 +            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
 +            mergemask(&d[H##LESIZE(le)], r, mask);                      \
 +        }                                                               \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
-+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
++#define DO_VSHLL_ALL(OP, TOP)                                \
-+    if (ret) {
++    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
-+        error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
++    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
-+        abort();
++    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
 +    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
 +
 +DO_VSHLL_ALL(vshllb, false)
 +DO_VSHLL_ALL(vshllt, true)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
  DO_2SHIFT(VSHRI_U, vshli_u, true)
  DO_2SHIFT(VRSHRI_S, vrshli_s, true)
  DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 +
 +#define DO_VSHLL(INSN, FN)                                      \
 +    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
 +    {                                                           \
 +        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], false);            \
 +    }
 +
-+    cpu->kvm_vtime_dirty = true;
++DO_VSHLL(VSHLL_BS, vshllbs)
-+}
++DO_VSHLL(VSHLL_BU, vshllbu)
-+
++DO_VSHLL(VSHLL_TS, vshllts)
-+void kvm_arm_put_virtual_time(CPUState *cs)
++DO_VSHLL(VSHLL_TU, vshlltu)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    struct kvm_one_reg reg = {
 +        .id = KVM_REG_ARM_TIMER_CNT,
 +        .addr = (uintptr_t)&cpu->kvm_vtime,
 +    };
 +    int ret;
 +
 +    if (!cpu->kvm_vtime_dirty) {
 +        return;
 +    }
 +
 +    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    if (ret) {
 +        error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
 +        abort();
 +    }
 +
 +    cpu->kvm_vtime_dirty = false;
 +}
 +
  int kvm_put_vcpu_events(ARMCPU *cpu)
  {
      CPUARMState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
      return MEMTXATTRS_UNSPECIFIED;
  }
 +void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
 +{
 +    CPUState *cs = opaque;
 +    ARMCPU *cpu = ARM_CPU(cs);
 +
 +    if (running) {
 +        if (cpu->kvm_adjvtime) {
 +            kvm_arm_put_virtual_time(cs);
 +        }
 +    } else {
 +        if (cpu->kvm_adjvtime) {
 +            kvm_arm_get_virtual_time(cs);
 +        }
 +    }
 +}
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "qemu/timer.h"
 +#include "sysemu/runstate.h"
  #include "sysemu/kvm.h"
  #include "kvm_arm.h"
  #include "internals.h"
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          return -EINVAL;
      }
 +    qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
 +
      /* Determine init features for this CPU */
      memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
      if (cpu->start_powered_off) {
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/host-utils.h"
  #include "qemu/main-loop.h"
  #include "exec/gdbstub.h"
 +#include "sysemu/runstate.h"
  #include "sysemu/kvm.h"
  #include "sysemu/kvm_int.h"
  #include "kvm_arm.h"
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          return -EINVAL;
      }
 +    qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
 +
      /* Determine init features for this CPU */
      memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
      if (cpu->start_powered_off) {
 diff --git a/target/arm/machine.c b/target/arm/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/machine.c
 +++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
              /* This should never fail */
              abort();
          }
 +
 +        /*
 +         * kvm_arm_cpu_pre_save() must be called after
 +         * write_kvmstate_to_list()
 +         */
 +        kvm_arm_cpu_pre_save(cpu);
      } else {
          if (!write_cpustate_to_list(cpu, false)) {
              /* This should never fail. */
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
           * we're using it.
           */
          write_list_to_cpustate(cpu);
 +        kvm_arm_cpu_post_load(cpu);
      } else {
          if (!write_list_to_cpustate(cpu)) {
              return -1;
 --
 .20.1

-[PULL 20/26] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
+[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
-From: Zenghui Yu <yuzenghui@huawei.com>
+Implement the MVE VSRI and VSLI insns, which perform a
 shift-and-insert operation.
-If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-restoring GICR_CTLR.  Setting PTZ here makes littlt sense in "reduce GIC
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-initialization time".
+Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  8 ++++++++
  target/arm/mve.decode      |  9 ++++++++
  target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c |  3 +++
 files changed, 62 insertions(+)
-And what's worse, PTZ is generally programmed by guest to indicate to the
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 Redistributor whether the LPI Pending table is zero when enabling LPIs.
 If migration is triggered when the PTZ has just been cleared by guest (and
 before enabling LPIs), we will see PTZ==1 on the destination side, which
 is not as expected.  Let's just drop this hackish userspace behavior.
 Also take this chance to refine the comment a bit.
 Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions")
 Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
 Message-id: 20200119133051.642-1-yuzenghui@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/intc/arm_gicv3_kvm.c | 11 ++++-------
 file changed, 4 insertions(+), 7 deletions(-)
 diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
+--- a/target/arm/helper-mve.h
-+++ b/hw/intc/arm_gicv3_kvm.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     kvm_gicd_access(s, GICD_CTLR, &reg, true);
+ DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     if (redist_typer & GICR_TYPER_PLPIS) {
+ DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
--        /* Set base addresses before LPIs are enabled by GICR_CTLR write */
++
-+        /*
++DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+         * Restore base addresses before LPIs are potentially enabled by
++DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+         * GICR_CTLR write
++DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+         */
++
-         for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
++DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-             GICv3CPUState *c = &s->cpu[ncpu];
++DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s)
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-             kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/mve.decode
-             reg64 = c->gicr_pendbaser;
++++ b/target/arm/mve.decode
--            if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
+@@ -XXX,XX +XXX,XX @@ VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
--                /* Setting PTZ is advised if LPIs are disabled, to reduce
--                 * GIC initialization time.
+ VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
--                 */
+ VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
--                reg64 |= GICR_PENDBASER_PTZ;
++
--            }
++# Shift-and-insert
-             regl = (uint32_t)reg64;
++VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
-             kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
++VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
-             regh = (uint32_t)(reg64 >> 32);
++VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
 +
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +/* Shift-and-insert; we always work with 64 bits at a time */
 +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN)                    \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
 +                                void *vm, uint32_t shift)               \
 +    {                                                                   \
 +        uint64_t *d = vd, *m = vm;                                      \
 +        uint16_t mask;                                                  \
 +        uint64_t shiftmask;                                             \
 +        unsigned e;                                                     \
 +        if (shift == 0 || shift == ESIZE * 8) {                         \
 +            /*                                                          \
 +             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
 +             * The generic logic would give the right answer for 0 but  \
 +             * fails for <dt>.                                          \
 +             */                                                         \
 +            goto done;                                                  \
 +        }                                                               \
 +        assert(shift < ESIZE * 8);                                      \
 +        mask = mve_element_mask(env);                                   \
 +        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \
 +        shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift));     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) |       \
 +                (d[H8(e)] & ~shiftmask);                                \
 +            mergemask(&d[H8(e)], r, mask);                              \
 +        }                                                               \
 +done:                                                                   \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
 +#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
 +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
 +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
 +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
 +
 +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
 +
  /*
   * Long shifts taking half-sized inputs from top or bottom of the input
   * vector and producing a double-width result. ESIZE, TYPE are for
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
  DO_2SHIFT(VRSHRI_S, vrshli_s, true)
  DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 +DO_2SHIFT(VSRI, vsri, false)
 +DO_2SHIFT(VSLI, vsli, false)
 +
  #define DO_VSHLL(INSN, FN)                                      \
      static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
      {                                                           \
 --
 .20.1

-[PULL 13/26] hw/core/resettable: add support for changing parent
+[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
-From: Damien Hedde <damien.hedde@greensocs.com>
+Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
-Add a function resettable_change_parent() to do the required
+do_urshr() is borrowed from sve_helper.c.
 plumbing when changing the parent a of Resettable object.
-We need to make sure that the reset state of the object remains
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-coherent with the reset state of the new parent.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    | 10 ++++++++++
  target/arm/mve.decode      | 11 +++++++++++
  target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c | 15 ++++++++++++++
 files changed, 76 insertions(+)
-We make the 2 following hypothesis:
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 + when an object is put in a parent under reset, the object goes in
 reset.
 + when an object is removed from a parent under reset, the object
 leaves reset.
 The added function avoids any glitch if both old and new parent are
 already in reset.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/resettable.h | 16 +++++++++++
  hw/core/resettable.c    | 62 +++++++++++++++++++++++++++++++++++++++--
  hw/core/trace-events    |  1 +
 files changed, 77 insertions(+), 2 deletions(-)
 diff --git a/include/hw/resettable.h b/include/hw/resettable.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/resettable.h
+--- a/target/arm/helper-mve.h
-+++ b/include/hw/resettable.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type);
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-  */
+ DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- bool resettable_is_in_reset(Object *obj);
+ DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+/**
++
-+ * resettable_change_parent:
++DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ * Indicate that the parent of Ressettable @obj is changing from @oldp to @newp.
++DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ * All 3 objects must implement resettable interface. @oldp or @newp may be
++DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ * NULL.
++DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ *
++
-+ * This function will adapt the reset state of @obj so that it is coherent
++DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ * with the reset state of @newp. It may trigger @resettable_assert_reset()
++DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ * or @resettable_release_reset(). It will do such things only if the reset
++DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ * state of @newp and @oldp are different.
++DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+ *
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-+ * When using this function during reset, it must only be called during
+index XXXXXXX..XXXXXXX 100644
-+ * a hold phase method. Calling this during enter or exit phase is an error.
+--- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
  VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
  VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
  VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 +
 +# Narrowing shifts (which only support b and h sizes)
 +VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 +VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 +VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 +VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 +
 +VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 +VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 +VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 +VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
  DO_VSHLL_ALL(vshllb, false)
  DO_VSHLL_ALL(vshllt, true)
 +
 +/*
 + * Narrowing right shifts, taking a double sized input, shifting it
 + * and putting the result in either the top or bottom half of the output.
 + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
 + */
-+void resettable_change_parent(Object *obj, Object *newp, Object *oldp);
++#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)       \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        LTYPE *m = vm;                                          \
 +        TYPE *d = vd;                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned le;                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            TYPE r = FN(m[H##LESIZE(le)], shift);               \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
- /**
++#define DO_VSHRN_ALL(OP, FN)                                    \
-  * resettable_class_set_parent_phases:
++    DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN)        \
-  *
++    DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN)       \
-diff --git a/hw/core/resettable.c b/hw/core/resettable.c
++    DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN)         \
-index XXXXXXX..XXXXXXX 100644
++    DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
---- a/hw/core/resettable.c
++
-+++ b/hw/core/resettable.c
++static inline uint64_t do_urshr(uint64_t x, unsigned sh)
@@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type);
   * enter_phase_in_progress:
   * True if we are currently in reset enter phase.
   *
 - * Note: This flag is only used to guarantee (using asserts) that the reset
 - * API is used correctly. We can use a global variable because we rely on the
 + * exit_phase_in_progress:
 + * count the number of exit phase we are in.
 + *
 + * Note: These flags are only used to guarantee (using asserts) that the reset
 + * API is used correctly. We can use global variables because we rely on the
   * iothread mutex to ensure only one reset operation is in a progress at a
   * given time.
   */
  static bool enter_phase_in_progress;
 +static unsigned exit_phase_in_progress;
  void resettable_reset(Object *obj, ResetType type)
  {
@@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type)
      trace_resettable_reset_release_begin(obj, type);
      assert(!enter_phase_in_progress);
 +    exit_phase_in_progress += 1;
      resettable_phase_exit(obj, NULL, type);
 +    exit_phase_in_progress -= 1;
      trace_resettable_reset_release_end(obj);
  }
@@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
      trace_resettable_phase_exit_end(obj, obj_typename, s->count);
  }
 +/*
 + * resettable_get_count:
 + * Get the count of the Resettable object @obj. Return 0 if @obj is NULL.
 + */
 +static unsigned resettable_get_count(Object *obj)
 +{
-+    if (obj) {
++    if (likely(sh < 64)) {
-+        ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
++        return (x >> sh) + ((x >> (sh - 1)) & 1);
-+        return rc->get_state(obj)->count;
++    } else if (sh == 64) {
-+    }
++        return x >> 63;
-+    return 0;
++    } else {
-+}
++        return 0;
 +
 +void resettable_change_parent(Object *obj, Object *newp, Object *oldp)
 +{
 +    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
 +    ResettableState *s = rc->get_state(obj);
 +    unsigned newp_count = resettable_get_count(newp);
 +    unsigned oldp_count = resettable_get_count(oldp);
 +
 +    /*
 +     * Ensure we do not change parent when in enter or exit phase.
 +     * During these phases, the reset subtree being updated is partly in reset
 +     * and partly not in reset (it depends on the actual position in
 +     * resettable_child_foreach()s). We are not able to tell in which part is a
 +     * leaving or arriving device. Thus we cannot set the reset count of the
 +     * moving device to the proper value.
 +     */
 +    assert(!enter_phase_in_progress && !exit_phase_in_progress);
 +    trace_resettable_change_parent(obj, oldp, oldp_count, newp, newp_count);
 +
 +    /*
 +     * At most one of the two 'for' loops will be executed below
 +     * in order to cope with the difference between the two counts.
 +     */
 +    /* if newp is more reset than oldp */
 +    for (unsigned i = oldp_count; i < newp_count; i++) {
 +        resettable_assert_reset(obj, RESET_TYPE_COLD);
 +    }
 +    /*
 +     * if obj is leaving a bus under reset, we need to ensure
 +     * hold phase is not pending.
 +     */
 +    if (oldp_count && s->hold_phase_pending) {
 +        resettable_phase_hold(obj, NULL, RESET_TYPE_COLD);
 +    }
 +    /* if oldp is more reset than newp */
 +    for (unsigned i = newp_count; i < oldp_count; i++) {
 +        resettable_release_reset(obj, RESET_TYPE_COLD);
 +    }
 +}
 +
- void resettable_class_set_parent_phases(ResettableClass *rc,
++DO_VSHRN_ALL(vshrn, DO_SHR)
-                                         ResettableEnterPhase enter,
++DO_VSHRN_ALL(vrshrn, do_urshr)
-                                         ResettableHoldPhase hold,
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 diff --git a/hw/core/trace-events b/hw/core/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/trace-events
+--- a/target/arm/translate-mve.c
-+++ b/hw/core/trace-events
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d"
+@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
- resettable_reset_assert_end(void *obj) "obj=%p"
+ DO_VSHLL(VSHLL_BU, vshllbu)
- resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d"
+ DO_VSHLL(VSHLL_TS, vshllts)
- resettable_reset_release_end(void *obj) "obj=%p"
+ DO_VSHLL(VSHLL_TU, vshlltu)
-+resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc) "obj=%p from=%p(%d) to=%p(%d)"
++
- resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
++#define DO_2SHIFT_N(INSN, FN)                                   \
- resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d"
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
- resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
++    {                                                           \
 +        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], false);            \
 +    }
 +
 +DO_2SHIFT_N(VSHRNB, vshrnb)
 +DO_2SHIFT_N(VSHRNT, vshrnt)
 +DO_2SHIFT_N(VRSHRNB, vrshrnb)
 +DO_2SHIFT_N(VRSHRNT, vrshrnt)
 --
 .20.1

-[PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass
+[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
-From: Damien Hedde <damien.hedde@greensocs.com>
+Implement the MVE saturating shift-right-and-narrow insns
+VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
-This commit adds support of Resettable interface to buses and devices:
-+ ResettableState structure is added in the Bus/Device state
+do_srshr() is borrowed from sve_helper.c.
-+ Resettable methods are implemented.
-+ device/bus_is_in_reset function defined
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 This commit allows to transition the objects to the new
 multi-phase interface without changing the reset behavior at all.
 Object single reset method can be split into the 3 different phases
 but the 3 phases are still executed in a row for a given object.
 From the qdev/qbus reset api point of view, nothing is changed.
 qdev_reset_all() and qbus_reset_all() are not modified as well as
 device_legacy_reset().
 Transition of an object must be done from parent class to child class.
 Care has been taken to allow the transition of a parent class
 without requiring the child classes to be transitioned at the same
 time. Note that SysBus and SysBusDevice class do not need any transition
 because they do not override the legacy reset method.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/Makefile.include |  1 +
+ target/arm/helper-mve.h    |  30 +++++++++++
- include/hw/qdev-core.h | 27 ++++++++++++
+ target/arm/mve.decode      |  28 ++++++++++
- hw/core/bus.c          | 97 ++++++++++++++++++++++++++++++++++++++++++
+ target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
- hw/core/qdev.c         | 93 ++++++++++++++++++++++++++++++++++++++++
+ target/arm/translate-mve.c |  12 +++++
-files changed, 218 insertions(+)
+files changed, 174 insertions(+)
-diff --git a/tests/Makefile.include b/tests/Makefile.include
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/tests/Makefile.include
+--- a/target/arm/helper-mve.h
-+++ b/tests/Makefile.include
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ tests/fp/%:
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
+ DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
+ DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     hw/core/bus.o \
+ DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    hw/core/resettable.o \
++
-     hw/core/irq.o \
++DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     hw/core/fw-path-provider.o \
++DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     hw/core/reset.o \
++DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
++DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-index XXXXXXX..XXXXXXX 100644
++
---- a/include/hw/qdev-core.h
++DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+++ b/include/hw/qdev-core.h
++DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@
++DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #include "qemu/bitmap.h"
++DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- #include "qom/object.h"
++
- #include "hw/hotplug.h"
++DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+#include "hw/resettable.h"
++DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- enum {
++DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     DEV_NVECTORS_UNSPECIFIED = -1,
++
-@@ -XXX,XX +XXX,XX @@ typedef struct DeviceClass {
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     bool hotpluggable;
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     /* callbacks */
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    /*
++
-+     * Reset method here is deprecated and replaced by methods in the
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+     * resettable class interface to implement a multi-phase reset.
++DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+     * TODO: remove once every reset callback is unused
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+     */
++DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     DeviceReset reset;
++
-     DeviceRealize realize;
++DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     DeviceUnrealize unrealize;
++DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ struct NamedGPIOList {
++DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- /**
++DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-  * DeviceState:
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-  * @realized: Indicates whether the device has been fully constructed.
+index XXXXXXX..XXXXXXX 100644
-+ * @reset: ResettableState for the device; handled by Resettable interface.
+--- a/target/arm/mve.decode
-  *
++++ b/target/arm/mve.decode
-  * This structure should not be accessed directly.  We declare it here
+@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
-  * so that it can be embedded in individual device state structures.
+ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
-@@ -XXX,XX +XXX,XX @@ struct DeviceState {
+ VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
-     int num_child_bus;
+ VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
-     int instance_id_alias;
++
-     int alias_required_for_version;
++VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
-+    ResettableState reset;
++VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
- };
++VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
++VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
- struct DeviceListener {
++VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
-@@ -XXX,XX +XXX,XX @@ typedef struct BusChild {
++VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
- /**
++VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
-  * BusState:
++VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
-  * @hotplug_handler: link to a hotplug handler associated with bus.
++
-+ * @reset: ResettableState for the bus; handled by Resettable interface.
++VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
-  */
++VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
- struct BusState {
++VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
-     Object obj;
++VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
-@@ -XXX,XX +XXX,XX @@ struct BusState {
++
-     int num_children;
++VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
-     QTAILQ_HEAD(, BusChild) children;
++VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
-     QLIST_ENTRY(BusState) sibling;
++VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
-+    ResettableState reset;
++VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
- };
++VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
++VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
- /**
++VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
-@@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque);
++VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
- void qbus_reset_all(BusState *bus);
++
- void qbus_reset_all_fn(void *opaque);
++VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
++VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
-+/**
++VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
-+ * device_is_in_reset:
++VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
-+ * Return true if the device @dev is currently being reset.
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-+ */
+index XXXXXXX..XXXXXXX 100644
-+bool device_is_in_reset(DeviceState *dev);
+--- a/target/arm/mve_helper.c
-+
++++ b/target/arm/mve_helper.c
-+/**
+@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
-+ * bus_is_in_reset:
+     }
 + * Return true if the bus @bus is currently being reset.
 + */
 +bool bus_is_in_reset(BusState *bus);
 +
  /* This should go away once we get rid of the NULL bus hack */
  BusState *sysbus_get_default(void);
@@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev);
  void device_class_set_props(DeviceClass *dc, Property *props);
 +/**
 + * device_class_set_parent_reset:
 + * TODO: remove the function when DeviceClass's reset method
 + * is not used anymore.
 + */
  void device_class_set_parent_reset(DeviceClass *dc,
                                     DeviceReset dev_reset,
                                     DeviceReset *parent_reset);
 diff --git a/hw/core/bus.c b/hw/core/bus.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/bus.c
 +++ b/hw/core/bus.c
@@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus,
      return 0;
  }
-+bool bus_is_in_reset(BusState *bus)
++static inline int64_t do_srshr(int64_t x, unsigned sh)
 +{
-+    return resettable_is_in_reset(OBJECT(bus));
++    if (likely(sh < 64)) {
-+}
++        return (x >> sh) + ((x >> (sh - 1)) & 1);
-+
++    } else {
-+static ResettableState *bus_get_reset_state(Object *obj)
++        /* Rounding the sign bit always produces 0. */
-+{
++        return 0;
 +    BusState *bus = BUS(obj);
 +    return &bus->reset;
 +}
 +
 +static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
 +                                    void *opaque, ResetType type)
 +{
 +    BusState *bus = BUS(obj);
 +    BusChild *kid;
 +
 +    QTAILQ_FOREACH(kid, &bus->children, sibling) {
 +        cb(OBJECT(kid->child), opaque, type);
 +    }
 +}
 +
- static void qbus_realize(BusState *bus, DeviceState *parent, const char *name)
+ DO_VSHRN_ALL(vshrn, DO_SHR)
- {
+ DO_VSHRN_ALL(vrshrn, do_urshr)
-     const char *typename = object_get_typename(OBJECT(bus));
++
-@@ -XXX,XX +XXX,XX @@ static char *default_bus_get_fw_dev_path(DeviceState *dev)
++static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
-     return g_strdup(object_get_typename(OBJECT(dev)));
++                                 bool *satp)
  }
 +/**
 + * bus_phases_reset:
 + * Transition reset method for buses to allow moving
 + * smoothly from legacy reset method to multi-phases
 + */
 +static void bus_phases_reset(BusState *bus)
 +{
-+    ResettableClass *rc = RESETTABLE_GET_CLASS(bus);
++    if (val > max) {
-+
++        *satp = true;
-+    if (rc->phases.enter) {
++        return max;
-+        rc->phases.enter(OBJECT(bus), RESET_TYPE_COLD);
++    } else if (val < min) {
-+    }
++        *satp = true;
-+    if (rc->phases.hold) {
++        return min;
-+        rc->phases.hold(OBJECT(bus));
++    } else {
-+    }
++        return val;
 +    if (rc->phases.exit) {
 +        rc->phases.exit(OBJECT(bus));
 +    }
 +}
 +
-+static void bus_transitional_reset(Object *obj)
++/* Saturating narrowing right shifts */
-+{
++#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
-+    BusClass *bc = BUS_GET_CLASS(obj);
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+
++                                void *vm, uint32_t shift)       \
-+    /*
++    {                                                           \
-+     * This will call either @bus_phases_reset (for multi-phases transitioned
++        LTYPE *m = vm;                                          \
-+     * buses) or a bus's specific method for not-yet transitioned buses.
++        TYPE *d = vd;                                           \
-+     * In both case, it does not reset children.
++        uint16_t mask = mve_element_mask(env);                  \
-+     */
++        bool qc = false;                                        \
-+    if (bc->reset) {
++        unsigned le;                                            \
-+        bc->reset(BUS(obj));
++        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            bool sat = false;                                   \
 +            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
-+}
++
-+
++#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
-+/**
++    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
-+ * bus_get_transitional_reset:
++    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
-+ * check if the bus's class is ready for multi-phase
++
-+ */
++#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
-+static ResettableTrFunction bus_get_transitional_reset(Object *obj)
++    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
-+{
++    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
-+    BusClass *dc = BUS_GET_CLASS(obj);
++
-+    if (dc->reset != bus_phases_reset) {
++#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
-+        /*
++    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
-+         * dc->reset has been overridden by a subclass,
++    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
-+         * the bus is not ready for multi phase yet.
++
-+         */
++#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
-+        return bus_transitional_reset;
++    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
-+    }
++    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
-+    return NULL;
++
-+}
++#define DO_SHRN_SB(N, M, SATP)                                  \
-+
++    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
- static void bus_class_init(ObjectClass *class, void *data)
++#define DO_SHRN_UB(N, M, SATP)                                  \
- {
++    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
-     BusClass *bc = BUS_CLASS(class);
++#define DO_SHRUN_B(N, M, SATP)                                  \
-+    ResettableClass *rc = RESETTABLE_CLASS(class);
++    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
++
-     class->unparent = bus_unparent;
++#define DO_SHRN_SH(N, M, SATP)                                  \
-     bc->get_fw_dev_path = default_bus_get_fw_dev_path;
++    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
-+
++#define DO_SHRN_UH(N, M, SATP)                                  \
-+    rc->get_state = bus_get_reset_state;
++    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
-+    rc->child_foreach = bus_reset_child_foreach;
++#define DO_SHRUN_H(N, M, SATP)                                  \
-+
++    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
-+    /*
++
-+     * @bus_phases_reset is put as the default reset method below, allowing
++#define DO_RSHRN_SB(N, M, SATP)                                 \
-+     * to do the multi-phase transition from base classes to leaf classes. It
++    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
-+     * allows a legacy-reset Bus class to extend a multi-phases-reset
++#define DO_RSHRN_UB(N, M, SATP)                                 \
-+     * Bus class for the following reason:
++    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
-+     * + If a base class B has been moved to multi-phase, then it does not
++#define DO_RSHRUN_B(N, M, SATP)                                 \
-+     *   override this default reset method and may have defined phase methods.
++    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
-+     * + A child class C (extending class B) which uses
++
-+     *   bus_class_set_parent_reset() (or similar means) to override the
++#define DO_RSHRN_SH(N, M, SATP)                                 \
-+     *   reset method will still work as expected. @bus_phases_reset function
++    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
-+     *   will be registered as the parent reset method and effectively call
++#define DO_RSHRN_UH(N, M, SATP)                                 \
-+     *   parent reset phases.
++    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
-+     */
++#define DO_RSHRUN_H(N, M, SATP)                                 \
-+    bc->reset = bus_phases_reset;
++    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
-+    rc->get_transitional_function = bus_get_transitional_reset;
++
- }
++DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
++DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
- static void qbus_finalize(Object *obj)
++DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo bus_info = {
++DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
-     .instance_init = qbus_initfn,
++DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
-     .instance_finalize = qbus_finalize,
++DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
-     .class_init = bus_class_init,
++
-+    .interfaces = (InterfaceInfo[]) {
++DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
-+        { TYPE_RESETTABLE_INTERFACE },
++DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
-+        { }
++DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
-+    },
++DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
- };
++DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
++DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
- static void bus_register_types(void)
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-diff --git a/hw/core/qdev.c b/hw/core/qdev.c
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
---- a/hw/core/qdev.c
++++ b/target/arm/translate-mve.c
-+++ b/hw/core/qdev.c
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
-@@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque)
+ DO_2SHIFT_N(VSHRNT, vshrnt)
-     qbus_reset_all(bus);
+ DO_2SHIFT_N(VRSHRNB, vrshrnb)
- }
+ DO_2SHIFT_N(VRSHRNT, vrshrnt)
++DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
-+bool device_is_in_reset(DeviceState *dev)
++DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
-+{
++DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
-+    return resettable_is_in_reset(OBJECT(dev));
++DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
-+}
++DO_2SHIFT_N(VQSHRUNB, vqshrunb)
-+
++DO_2SHIFT_N(VQSHRUNT, vqshrunt)
-+static ResettableState *device_get_reset_state(Object *obj)
++DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
-+{
++DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
-+    DeviceState *dev = DEVICE(obj);
++DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
-+    return &dev->reset;
++DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
-+}
++DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
-+
++DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 +static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb,
 +                                       void *opaque, ResetType type)
 +{
 +    DeviceState *dev = DEVICE(obj);
 +    BusState *bus;
 +
 +    QLIST_FOREACH(bus, &dev->child_bus, sibling) {
 +        cb(OBJECT(bus), opaque, type);
 +    }
 +}
 +
  /* can be used as ->unplug() callback for the simple cases */
  void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
                                    DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ device_vmstate_if_get_id(VMStateIf *obj)
      return qdev_get_dev_path(dev);
  }
 +/**
 + * device_phases_reset:
 + * Transition reset method for devices to allow moving
 + * smoothly from legacy reset method to multi-phases
 + */
 +static void device_phases_reset(DeviceState *dev)
 +{
 +    ResettableClass *rc = RESETTABLE_GET_CLASS(dev);
 +
 +    if (rc->phases.enter) {
 +        rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD);
 +    }
 +    if (rc->phases.hold) {
 +        rc->phases.hold(OBJECT(dev));
 +    }
 +    if (rc->phases.exit) {
 +        rc->phases.exit(OBJECT(dev));
 +    }
 +}
 +
 +static void device_transitional_reset(Object *obj)
 +{
 +    DeviceClass *dc = DEVICE_GET_CLASS(obj);
 +
 +    /*
 +     * This will call either @device_phases_reset (for multi-phases transitioned
 +     * devices) or a device's specific method for not-yet transitioned devices.
 +     * In both case, it does not reset children.
 +     */
 +    if (dc->reset) {
 +        dc->reset(DEVICE(obj));
 +    }
 +}
 +
 +/**
 + * device_get_transitional_reset:
 + * check if the device's class is ready for multi-phase
 + */
 +static ResettableTrFunction device_get_transitional_reset(Object *obj)
 +{
 +    DeviceClass *dc = DEVICE_GET_CLASS(obj);
 +    if (dc->reset != device_phases_reset) {
 +        /*
 +         * dc->reset has been overridden by a subclass,
 +         * the device is not ready for multi phase yet.
 +         */
 +        return device_transitional_reset;
 +    }
 +    return NULL;
 +}
 +
  static void device_class_init(ObjectClass *class, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(class);
      VMStateIfClass *vc = VMSTATE_IF_CLASS(class);
 +    ResettableClass *rc = RESETTABLE_CLASS(class);
      class->unparent = device_unparent;
@@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data)
      dc->hotpluggable = true;
      dc->user_creatable = true;
      vc->get_id = device_vmstate_if_get_id;
 +    rc->get_state = device_get_reset_state;
 +    rc->child_foreach = device_reset_child_foreach;
 +
 +    /*
 +     * @device_phases_reset is put as the default reset method below, allowing
 +     * to do the multi-phase transition from base classes to leaf classes. It
 +     * allows a legacy-reset Device class to extend a multi-phases-reset
 +     * Device class for the following reason:
 +     * + If a base class B has been moved to multi-phase, then it does not
 +     *   override this default reset method and may have defined phase methods.
 +     * + A child class C (extending class B) which uses
 +     *   device_class_set_parent_reset() (or similar means) to override the
 +     *   reset method will still work as expected. @device_phases_reset function
 +     *   will be registered as the parent reset method and effectively call
 +     *   parent reset phases.
 +     */
 +    dc->reset = device_phases_reset;
 +    rc->get_transitional_function = device_get_transitional_reset;
      object_class_property_add_bool(class, "realized",
                                     device_get_realized, device_set_realized,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo device_type_info = {
      .class_size = sizeof(DeviceClass),
      .interfaces = (InterfaceInfo[]) {
          { TYPE_VMSTATE_IF },
 +        { TYPE_RESETTABLE_INTERFACE },
          { }
      }
  };
 --
 .20.1

-[PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration
+[PULL 19/24] target/arm: Implement MVE VSHLC
-From: Damien Hedde <damien.hedde@greensocs.com>
+Implement the MVE VSHLC insn, which performs a shift left of the
 entire vector with carry in bits provided from a general purpose
 register and carry out bits written back to that register.
-Replace deprecated qdev_reset_all by resettable_cold_reset_fn for
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-the ipl registration in the main reset handlers.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  2 ++
  target/arm/mve.decode      |  2 ++
  target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 files changed, 72 insertions(+)
-This does not impact the behavior for the following reasons:
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 + at this point resettable just call the old reset methods of devices
   and buses in the same order than qdev/qbus.
 + resettable handlers registered with qemu_register_reset are
   serialized; there is no interleaving.
 + eventual explicit calls to legacy reset API (device_reset or
   qdev/qbus_reset) inside this reset handler will not be masked out
   by resettable mechanism; they do not go through resettable api.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/s390x/ipl.c | 10 +++++++++-
 file changed, 9 insertions(+), 1 deletion(-)
 diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/s390x/ipl.c
+--- a/target/arm/helper-mve.h
-+++ b/hw/s390x/ipl.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-      */
+ DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     ipl->compat_start_addr = ipl->start_addr;
+ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     ipl->compat_bios_start_addr = ipl->bios_start_addr;
+ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
--    qemu_register_reset(qdev_reset_all_fn, dev);
++
 +DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
  VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
  VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
  VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
 +VSHLC             111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
  DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
  DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
  DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 +
 +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
 +                           uint32_t shift)
 +{
 +    uint32_t *d = vd;
 +    uint16_t mask = mve_element_mask(env);
 +    unsigned e;
 +    uint32_t r;
 +
 +    /*
-+     * Because this Device is not on any bus in the qbus tree (it is
++     * For each 32-bit element, we shift it left, bringing in the
-+     * not a sysbus device and it's not on some other bus like a PCI
++     * low 'shift' bits of rdm at the bottom. Bits shifted out at
-+     * bus) it will not be automatically reset by the 'reset the
++     * the top become the new rdm, if the predicate mask permits.
-+     * sysbus' hook registered by vl.c like most devices. So we must
++     * The final rdm value is returned to update the register.
-+     * manually register a reset hook for it.
++     * shift == 0 here means "shift by 32 bits".
 +     * TODO: there should be a better way to do this.
 +     */
-+    qemu_register_reset(resettable_cold_reset_fn, dev);
++    if (shift == 0) {
- error:
++        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
-     error_propagate(errp, err);
++            r = rdm;
- }
++            if (mask & 1) {
 +                rdm = d[H4(e)];
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    } else {
 +        uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
 +
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = (d[H4(e)] << shift) | (rdm & shiftmask);
 +            if (mask & 1) {
 +                rdm = d[H4(e)] >> (32 - shift);
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    }
 +    mve_advance_vpt(env);
 +    return rdm;
 +}
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
  DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
  DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
  DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 +
 +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
 +{
 +    /*
 +     * Whole Vector Left Shift with Carry. The carry is taken
 +     * from a general purpose register and written back there.
 +     * An imm of 0 means "shift by 32".
 +     */
 +    TCGv_ptr qd;
 +    TCGv_i32 rdm;
 +
 +    if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
 +        return false;
 +    }
 +    if (a->rdm == 13 || a->rdm == 15) {
 +        /* CONSTRAINED UNPREDICTABLE: we UNDEF */
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    qd = mve_qreg_ptr(a->qd);
 +    rdm = load_reg(s, a->rdm);
 +    gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
 +    store_reg(s, a->rdm, rdm);
 +    tcg_temp_free_ptr(qd);
 +    mve_update_eci(s);
 +    return true;
 +}
 --
 .20.1

-[PULL 10/26] hw/core/qdev: add trace events to help with resettable transition
+[PULL 20/24] target/arm: Implement MVE VADDLV
-From: Damien Hedde <damien.hedde@greensocs.com>
+Implement the MVE VADDLV insn; this is similar to VADDV, except
 that it accumulates 32-bit elements into a 64-bit accumulator
 stored in a pair of general-purpose registers.
-Adds trace events to reset procedure and when updating the parent
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-bus of a device.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  3 ++
  target/arm/mve.decode      |  6 +++-
  target/arm/mve_helper.c    | 19 ++++++++++++
  target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 files changed, 90 insertions(+), 1 deletion(-)
-Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/core/qdev.c       | 29 ++++++++++++++++++++++++++---
  hw/core/trace-events |  9 +++++++++
 files changed, 35 insertions(+), 3 deletions(-)
 diff --git a/hw/core/qdev.c b/hw/core/qdev.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/qdev.c
+--- a/target/arm/helper-mve.h
-+++ b/hw/core/qdev.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- #include "hw/boards.h"
+ DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- #include "hw/sysbus.h"
+ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- #include "migration/vmstate.h"
-+#include "trace.h"
++DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
++DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
- bool qdev_hotplug = false;
++
- static bool qdev_hot_added = false;
+ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
-@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-     bool replugging = dev->parent_bus != NULL;
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-     if (replugging) {
+index XXXXXXX..XXXXXXX 100644
--        /* Keep a reference to the device while it's not plugged into
+--- a/target/arm/mve.decode
-+        trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
++++ b/target/arm/mve.decode
-+            dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)),
+@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar   1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
-+            OBJECT(bus), object_get_typename(OBJECT(bus)));
+ VQRDMULH_scalar  1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
-+        /*
-+         * Keep a reference to the device while it's not plugged into
+ # Vector add across vector
-          * any bus, to avoid it potentially evaporating when it is
+-VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
-          * dereffed in bus_remove_child().
++{
-          */
++  VADDV          111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
-@@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev)
++  VADDLV         111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
-     return hotplug_ctrl;
++                 rdahi=%rdahi rdalo=%rdalo
 +}
  # Predicate operations
  %mask_22_13      22:1 13:3
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +#define DO_VADDLV(OP, TYPE, LTYPE)                              \
 +    uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
 +                                    uint64_t ra)                \
 +    {                                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        TYPE *m = vm;                                           \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {              \
 +            if (mask & 1) {                                     \
 +                ra += (LTYPE)m[H4(e)];                          \
 +            }                                                   \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +        return ra;                                              \
 +    }                                                           \
 +
 +DO_VADDLV(vaddlv_s, int32_t, int64_t)
 +DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
 +
  /* Shifts by immediate */
  #define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
      void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      return true;
  }
-+static int qdev_prereset(DeviceState *dev, void *opaque)
++static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
 +{
-+    trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev)));
++    /*
-+    return 0;
++     * Vector Add Long Across Vector: accumulate the 32-bit
 +     * elements of the vector into a 64-bit result stored in
 +     * a pair of general-purpose registers.
 +     * No need to check Qm's bank: it is only 3 bits in decode.
 +     */
 +    TCGv_ptr qm;
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!dc_isar_feature(aa32_mve, s)) {
 +        return false;
 +    }
 +    /*
 +     * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
 +     * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
 +     */
 +    if (a->rdahi == 13 || a->rdahi == 15) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
 +     * This insn is subject to beat-wise execution. Partial execution
 +     * of an A=0 (no-accumulate) insn which does not execute the first
 +     * beat must start with the current value of RdaHi:RdaLo, not zero.
 +     */
 +    if (a->a || mve_skip_first_beat(s)) {
 +        /* Accumulate input from RdaHi:RdaLo */
 +        rda = tcg_temp_new_i64();
 +        rdalo = load_reg(s, a->rdalo);
 +        rdahi = load_reg(s, a->rdahi);
 +        tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +        tcg_temp_free_i32(rdalo);
 +        tcg_temp_free_i32(rdahi);
 +    } else {
 +        /* Accumulate starting at zero */
 +        rda = tcg_const_i64(0);
 +    }
 +
 +    qm = mve_qreg_ptr(a->qm);
 +    if (a->u) {
 +        gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
 +    } else {
 +        gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
 +    }
 +    tcg_temp_free_ptr(qm);
 +
 +    rdalo = tcg_temp_new_i32();
 +    rdahi = tcg_temp_new_i32();
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
-+static int qbus_prereset(BusState *bus, void *opaque)
+ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
 +{
 +    trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus)));
 +    return 0;
 +}
 +
  static int qdev_reset_one(DeviceState *dev, void *opaque)
  {
-     device_legacy_reset(dev);
+     TCGv_ptr qd;
@@ -XXX,XX +XXX,XX @@ static int qdev_reset_one(DeviceState *dev, void *opaque)
  static int qbus_reset_one(BusState *bus, void *opaque)
  {
      BusClass *bc = BUS_GET_CLASS(bus);
 +    trace_qbus_reset(bus, object_get_typename(OBJECT(bus)));
      if (bc->reset) {
          bc->reset(bus);
      }
@@ -XXX,XX +XXX,XX @@ static int qbus_reset_one(BusState *bus, void *opaque)
  void qdev_reset_all(DeviceState *dev)
  {
 -    qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
 +    trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev)));
 +    qdev_walk_children(dev, qdev_prereset, qbus_prereset,
 +                       qdev_reset_one, qbus_reset_one, NULL);
  }
  void qdev_reset_all_fn(void *opaque)
@@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque)
  void qbus_reset_all(BusState *bus)
  {
 -    qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
 +    trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus)));
 +    qbus_walk_children(bus, qdev_prereset, qbus_prereset,
 +                       qdev_reset_one, qbus_reset_one, NULL);
  }
  void qbus_reset_all_fn(void *opaque)
@@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev)
  {
      DeviceClass *klass = DEVICE_GET_CLASS(dev);
 +    trace_qdev_reset(dev, object_get_typename(OBJECT(dev)));
      if (klass->reset) {
          klass->reset(dev);
      }
 diff --git a/hw/core/trace-events b/hw/core/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/trace-events
 +++ b/hw/core/trace-events
@@ -XXX,XX +XXX,XX @@
  # loader.c
  loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d"
 +
 +# qdev.c
 +qdev_reset(void *obj, const char *objtype) "obj=%p(%s)"
 +qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
 +qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
 +qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
 +qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
 +qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
 +qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
 --
 .20.1

-[PULL 05/26] ftgmac100: check RX and TX buffer alignment
+[PULL 21/24] target/arm: Implement MVE long shifts by immediate
-From: Cédric Le Goater <clg@kaod.org>
+The MVE extension to v8.1M includes some new shift instructions which
+sit entirely within the non-coprocessor part of the encoding space
-These buffers should be aligned on 16 bytes.
+and which operate only on general-purpose registers.  They take up
+the space which was previously UNPREDICTABLE MOVS and ORRS encodings
-Ignore invalid RX and TX buffer addresses and log an error. All
+with Rm == 13 or 15.
-incoming and outgoing traffic will be dropped because no valid RX or
-TX descriptors will be available.
+Implement the long shifts by immediate, which perform shifts on a
+pair of general-purpose registers treated as a 64-bit quantity, with
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+an immediate shift count between 1 and 32.
-Message-id: 20200114103433.30534-4-clg@kaod.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
 the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
 cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
 is too difficult, because the functions that generate the code are
 shared between a dozen different kinds of arithmetic or logical
 instruction for all A32, T16 and T32 encodings, and for some insns
 and some encodings Rm==13,15 are valid.)
 We make the helper functions we need for UQSHLL and SQSHLL take
 a 32-bit value which the helper casts to int8_t because we'll need
 these helpers also for the shift-by-register insns, where the shift
 count might be < 0 or > 32.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
 ---
- hw/net/ftgmac100.c | 13 +++++++++++++
+ target/arm/helper-mve.h |  3 ++
-file changed, 13 insertions(+)
+ target/arm/translate.h  |  1 +
+ target/arm/t32.decode   | 28 +++++++++++++
-diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
+ target/arm/mve_helper.c | 10 +++++
-index XXXXXXX..XXXXXXX 100644
+ target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
---- a/hw/net/ftgmac100.c
+files changed, 132 insertions(+)
-+++ b/hw/net/ftgmac100.c
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-     uint32_t        des3;
+index XXXXXXX..XXXXXXX 100644
- } FTGMAC100Desc;
+--- a/target/arm/helper-mve.h
++++ b/target/arm/helper-mve.h
-+#define FTGMAC100_DESC_ALIGNMENT 16
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 +
 +DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
  typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 +typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mcr             !extern cp opc1 crn crm opc2 rt
  &mcrr            !extern cp opc1 crm rt rt2
 +&mve_shl_ri      rdalo rdahi shim
 +
 +# rdahi: bits [3:1] from insn, bit 0 is 1
 +# rdalo: bits [3:1] from insn, bit 0 is 0
 +%rdahi_9 9:3 !function=times_2_plus_1
 +%rdalo_17 17:3 !function=times_2
 +
  # Data-processing (register)
  %imm5_12_6       12:3 6:2
@@ -XXX,XX +XXX,XX @@
  @S_xrr_shi       ....... .... .   rn:4 .... .... .. shty:2 rm:4 \
                   &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
 +@mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
 +                 &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
 +
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
    AND_rrri       1110101 0000 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
  {
 +  # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
 +  # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
 +  # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
 +  # they explicitly call unallocated_encoding() for cases that must UNDEF
 +  # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
 +  # the rest fall through (where ORR_rrri and MOV_rxri will end up
 +  # handling them as r13 and r15 accesses with the same semantics as A32).
 +  [
 +    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +
 +    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +  ]
 +
    MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
    ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
  }
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      mve_advance_vpt(env);
      return rdm;
  }
 +
 +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
      return true;
  }
 +/*
 + * v8.1M MVE wide-shifts
 + */
 +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
 +                          WideShiftImmFn *fn)
 +{
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13) {
 +        /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +
 +    rda = tcg_temp_new_i64();
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    fn(rda, rda, a->shim);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
 +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
 +}
 +
 +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
 +}
 +
 +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
 +}
 +
 +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_sqshll);
 +}
 +
 +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_uqshll);
 +}
 +
 +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_srshr64_i64);
 +}
 +
 +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_urshr64_i64);
 +}
 +
  /*
-  * Specific RTL8211E MII Registers
+  * Multiply and multiply accumulate
   */
-@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
-         s->itc = value;
-         break;
-     case FTGMAC100_RXR_BADR: /* Ring buffer address */
-+        if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
-+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%"
-+                          HWADDR_PRIx "\n", __func__, value);
-+            return;
-+        }
-+
-         s->rx_ring = value;
-         s->rx_descriptor = s->rx_ring;
-         break;
-@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
-         break;
-     case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
-+        if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
-+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%"
-+                          HWADDR_PRIx "\n", __func__, value);
-+            return;
-+        }
-         s->tx_ring = value;
-         s->tx_descriptor = s->tx_ring;
-         break;
 --
 .20.1

-[PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
+[PULL 22/24] target/arm: Implement MVE long shifts by register
-The guest can use the semihosting API to open a handle
+Implement the MVE long shifts by register, which perform shifts on a
-corresponding to QEMU's own stdin, stdout, or stderr.
+pair of general-purpose registers treated as a 64-bit quantity, with
-When the guest closes this handle, we should not
+the shift count in another general-purpose register, which might be
-close the underlying host stdin/stdout/stderr
+either positive or negative.
-the way we would do if the handle corresponded to
-a host fd we'd opened on behalf of the guest in SYS_OPEN.
+Like the long-shifts-by-immediate, these encodings sit in the space
 that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
 Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
 also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
 we have to move the CSEL pattern into the same decodetree group.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
 Message-id: 20200124172954.28481-1-peter.maydell@linaro.org
 ---
- target/arm/arm-semi.c | 9 +++++++++
+ target/arm/helper-mve.h |  6 +++
-file changed, 9 insertions(+)
+ target/arm/translate.h  |  1 +
+ target/arm/t32.decode   | 16 +++++--
-diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
+ target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
-index XXXXXXX..XXXXXXX 100644
+ target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
---- a/target/arm/arm-semi.c
+files changed, 182 insertions(+), 3 deletions(-)
-+++ b/target/arm/arm-semi.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf)
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
- {
+index XXXXXXX..XXXXXXX 100644
-     CPUARMState *env = &cpu->env;
+--- a/target/arm/helper-mve.h
++++ b/target/arm/helper-mve.h
-+    /*
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+     * Only close the underlying host fd if it's one we opened on behalf
-+     * of the guest in SYS_OPEN.
+ DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-+     */
-+    if (gf->hostfd == STDIN_FILENO ||
++DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+        gf->hostfd == STDOUT_FILENO ||
++DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+        gf->hostfd == STDERR_FILENO) {
+ DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
  DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
 +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mcrr            !extern cp opc1 crm rt rt2
  &mve_shl_ri      rdalo rdahi shim
 +&mve_shl_rr      rdalo rdahi rm
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
  @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                   &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
 +@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
 +                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
      URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
      SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
      SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +
 +    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
 +    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 +    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
 +    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
 +    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
 +    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
    ]
    MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
    ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
 +
 +  # v8.1M CSEL and friends
 +  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
  }
  {
    MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 -# v8.1M CSEL and friends
 -CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 -
  # Data-processing (register-shifted register)
  MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      return rdm;
  }
 +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
 +}
 +
 +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
 +}
 +
  uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
  }
 +
 +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
 +                                    bool round, uint32_t *sat)
 +{
 +    if (shift <= -48) {
 +        /* Rounding the sign bit always produces 0. */
 +        if (round) {
 +            return 0;
 +        }
 +        return src >> 63;
 +    } else if (shift < 0) {
 +        if (round) {
 +            src >>= -shift - 1;
 +            return (src >> 1) + (src & 1);
 +        }
 +        return src >> -shift;
 +    } else if (shift < 48) {
 +        int64_t val = src << shift;
 +        int64_t extval = sextract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
-     return set_swi_errno(env, close(gf->hostfd));
++
- }
++    *sat = 1;
++    return (1ULL << 47) - (src >= 0);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
 +                                     bool round, uint32_t *sat)
 +{
 +    uint64_t val, extval;
 +
 +    if (shift <= -(48 + round)) {
 +        return 0;
 +    } else if (shift < 0) {
 +        if (round) {
 +            val = src >> (-shift - 1);
 +            val = (val >> 1) + (val & 1);
 +        } else {
 +            val = src >> -shift;
 +        }
 +        extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (shift < 48) {
 +        uint64_t val = src << shift;
 +        uint64_t extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
 +
 +    *sat = 1;
 +    return MAKE_64BIT_MASK(0, 48);
 +}
 +
 +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
      return do_mve_shl_ri(s, a, gen_urshr64_i64);
  }
 +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
 +{
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
 +        a->rm == a->rdahi || a->rm == a->rdalo) {
 +        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    rda = tcg_temp_new_i64();
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
 +    fn(rda, cpu_env, rda, cpu_R[a->rm]);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
 +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
 +}
 +
 +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
 +}
 +
 +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
 +}
 +
 +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
 +}
 +
 +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
 +}
 +
 +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
 .20.1

-[PULL 07/26] misc/pca9552: Add qom set and get
+[PULL 23/24] target/arm: Implement MVE shifts by immediate
-From: Joel Stanley <joel@jms.id.au>
+Implement the MVE shifts by immediate, which perform shifts
+on a single general-purpose register.
-Following the pattern of the work recently done with the ASPEED GPIO
-model, this adds support for inspecting and modifying the PCA9552 LEDs
+These patterns overlap with the long-shift-by-immediates,
-from the monitor.
+so we have to rearrange the grouping a little here.
  (qemu) qom-set  /machine/unattached/device[17] led0 on
  (qemu) qom-set  /machine/unattached/device[17] led0 off
  (qemu) qom-set  /machine/unattached/device[17] led0 pwm0
  (qemu) qom-set  /machine/unattached/device[17] led0 pwm1
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 20200114103433.30534-6-clg@kaod.org
 [clg: - removed the "qom-get" examples from the commit log
       - merged memory leak fixes from Joel ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
 ---
- hw/misc/pca9552.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++
+ target/arm/helper-mve.h |  3 ++
-file changed, 90 insertions(+)
+ target/arm/translate.h  |  1 +
+ target/arm/t32.decode   | 31 ++++++++++++++-----
-diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
+ target/arm/mve_helper.c | 10 ++++++
-index XXXXXXX..XXXXXXX 100644
+ target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
---- a/hw/misc/pca9552.c
+files changed, 104 insertions(+), 9 deletions(-)
-+++ b/hw/misc/pca9552.c
 diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-mve.h
 +++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
  DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
  DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
  DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +
 +DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
 +DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
 @@ -XXX,XX +XXX,XX @@
- #include "hw/misc/pca9552.h"
- #include "hw/misc/pca9552_regs.h"
+ &mve_shl_ri      rdalo rdahi shim
- #include "migration/vmstate.h"
+ &mve_shl_rr      rdalo rdahi rm
-+#include "qapi/error.h"
++&mve_sh_ri       rda shim
-+#include "qapi/visitor.h"
+ # rdahi: bits [3:1] from insn, bit 0 is 1
- #define PCA9552_LED_ON   0x0
+ # rdalo: bits [3:1] from insn, bit 0 is 0
- #define PCA9552_LED_OFF  0x1
+@@ -XXX,XX +XXX,XX @@
- #define PCA9552_LED_PWM0 0x2
+                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
- #define PCA9552_LED_PWM1 0x3
+ @mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                  &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
-+static const char *led_state[] = {"on", "off", "pwm0", "pwm1"};
++@mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
-+
++                 &mve_sh_ri shim=%imm5_12_6
- static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin)
  {
-     uint8_t reg   = PCA9552_LS0 + (pin / 4);
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
-@@ -XXX,XX +XXX,XX @@ static int pca9552_event(I2CSlave *i2c, enum i2c_event event)
+@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
-     return 0;
+   # the rest fall through (where ORR_rrri and MOV_rxri will end up
    # handling them as r13 and r15 accesses with the same semantics as A32).
    [
 -    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    {
 +      UQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 00 1111  @mve_sh_ri
 +      LSLL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +      UQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    }
 -    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 -    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    {
 +      URSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 01 1111  @mve_sh_ri
 +      LSRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +      URSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SRSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 10 1111  @mve_sh_ri
 +      ASRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +      SRSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 11 1111  @mve_sh_ri
 +      SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    }
      LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
      ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
  }
++
-+static void pca9552_get_led(Object *obj, Visitor *v, const char *name,
++uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-+                            void *opaque, Error **errp)
++{
-+{
++    return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
-+    PCA9552State *s = PCA9552(obj);
++}
-+    int led, rc, reg;
++
-+    uint8_t state;
++uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-+
++{
-+    rc = sscanf(name, "led%2d", &led);
++    return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
-+    if (rc != 1) {
++}
-+        error_setg(errp, "%s: error reading %s", __func__, name);
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_movi_i32(d, 0);
 +        return;
 +    }
-+    if (led < 0 || led > s->nr_leds) {
++    t = tcg_temp_new_i32();
-+        error_setg(errp, "%s invalid led %s", __func__, name);
+     tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_sari_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_URSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_extract_i32(d, a, sh - 1, 1);
 +        return;
 +    }
-+    /*
++    t = tcg_temp_new_i32();
-+     * Get the LSx register as the qom interface should expose the device
+     tcg_gen_extract_i32(t, a, sh - 1, 1);
-+     * state, not the modeled 'input line' behaviour which would come from
+     tcg_gen_shri_i32(d, a, sh);
-+     * reading the INPUTx reg
+     tcg_gen_add_i32(d, d, t);
-+     */
+@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
-+    reg = PCA9552_LS0 + led / 4;
+     return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
 +    state = (pca9552_read(s, reg) >> (led % 8)) & 0x3;
 +    visit_type_str(v, name, (char **)&led_state[state], errp);
 +}
 +
 +/*
 + * Return an LED selector register value based on an existing one, with
 + * the appropriate 2-bit state value set for the given LED number (0-3).
 + */
 +static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state)
 +{
 +        return (oldval & (~(0x3 << (led_num << 1)))) |
 +                ((state & 0x3) << (led_num << 1));
 +}
 +
 +static void pca9552_set_led(Object *obj, Visitor *v, const char *name,
 +                            void *opaque, Error **errp)
 +{
 +    PCA9552State *s = PCA9552(obj);
 +    Error *local_err = NULL;
 +    int led, rc, reg, val;
 +    uint8_t state;
 +    char *state_str;
 +
 +    visit_type_str(v, name, &state_str, &local_err);
 +    if (local_err) {
 +        error_propagate(errp, local_err);
 +        return;
 +    }
 +    rc = sscanf(name, "led%2d", &led);
 +    if (rc != 1) {
 +        error_setg(errp, "%s: error reading %s", __func__, name);
 +        return;
 +    }
 +    if (led < 0 || led > s->nr_leds) {
 +        error_setg(errp, "%s invalid led %s", __func__, name);
 +        return;
 +    }
 +
 +    for (state = 0; state < ARRAY_SIZE(led_state); state++) {
 +        if (!strcmp(state_str, led_state[state])) {
 +            break;
 +        }
 +    }
 +    if (state >= ARRAY_SIZE(led_state)) {
 +        error_setg(errp, "%s invalid led state %s", __func__, state_str);
 +        return;
 +    }
 +
 +    reg = PCA9552_LS0 + led / 4;
 +    val = pca9552_read(s, reg);
 +    val = pca955x_ledsel(val, led % 4, state);
 +    pca9552_write(s, reg, val);
 +}
 +
  static const VMStateDescription pca9552_vmstate = {
      .name = "PCA9552",
      .version_id = 0,
@@ -XXX,XX +XXX,XX @@ static void pca9552_reset(DeviceState *dev)
  static void pca9552_initfn(Object *obj)
  {
      PCA9552State *s = PCA9552(obj);
 +    int led;
      /* If support for the other PCA955X devices are implemented, these
       * constant values might be part of class structure describing the
@@ -XXX,XX +XXX,XX @@ static void pca9552_initfn(Object *obj)
       */
      s->max_reg = PCA9552_LS3;
      s->nr_leds = 16;
 +
 +    for (led = 0; led < s->nr_leds; led++) {
 +        char *name;
 +
 +        name = g_strdup_printf("led%d", led);
 +        object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led,
 +                            NULL, NULL, NULL);
 +        g_free(name);
 +    }
  }
- static void pca9552_class_init(ObjectClass *klass, void *data)
++static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
 +{
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rda == 13 || a->rda == 15) {
 +        /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +    fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
 +
 +    return true;
 +}
 +
 +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_urshr32_i32);
 +}
 +
 +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_srshr32_i32);
 +}
 +
 +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_sqshl);
 +}
 +
 +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_uqshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
 .20.1

-[PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable
+Deleted patch
-From: Damien Hedde <damien.hedde@greensocs.com>
-In qdev_set_parent_bus(), when changing the parent bus of a
-realized device, if the source and destination buses are not in the
-same reset state, some adaptations are required. This patch adds
-needed call to resettable_change_parent() to make sure a device reset
-state stays coherent with its parent bus.
-The addition is a no-op if:
-. the device being parented is not realized.
-. the device is realized, but both buses are not under reset.
-Case 2 means that as long as qdev_set_parent_bus() is called
-during the machine realization procedure (which is before the
-machine reset so nothing is in reset), it is a no op.
-There are 52 call sites of qdev_set_parent_bus(). All but one fall
-into the no-op case:
-+ 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/
-  {vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device
-  parent bus just before realizing the same vdev(vgpu).
-+ hw/core/qdev.c: when creating a device in qdev_try_create()
-+ hw/core/sysbus.c: when initializing a device in the sysbus
-+ hw/i386/amd_iommu.c: before realizing AMDVIState/pci
-+ hw/isa/piix4.c: before realizing PIIX4State/rtc
-+ hw/misc/auxbus.c: when creating an AUXBus
-+ hw/misc/auxbus.c: when creating an AUXBus child
-+ hw/misc/macio/macio.c: when initializing a MACIOState child
-+ hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu
-+ hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda
-+ hw/net/virtio-net.c: Used for migration when using the failover
-                       mechanism to migration a vfio-pci/net. It is
-                       a no-op because at this point the device is
-                       already on the bus.
-+ hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root
-+ hw/pci-host/gpex.c: before realizing GPEXHost/root
-+ hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev
-+ hw/pci-host/q35.c: before realizing Q35PCIHost/mch
-+ hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev
-+ hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root
-+ hw/s390x/event-facility.c: when creating SCLPEventFacility/
-                             TYPE_SCLP_QUIESCE
-+ hw/s390x/event-facility.c: ditto with SCLPEventFacility/
-                             TYPE_SCLP_CPU_HOTPLUG
-+ hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice
-  just after realizing it. Ok because at this point the destination
-  bus (sysbus) is not in reset; the realize step is before the
-  machine reset.
-+ hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below.
-+ hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs
-  line in ssi_auto_connect_slave(). Ok because this function is only
-  used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c,
-  hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c.
-+ hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device
-+ qdev-monitor.c: in device hotplug creation procedure before realize
-Note that this commit alone will have no effect, right now there is no
-use of resettable API to reset anything. So a bus will never be tagged
-as in-reset by this same API.
-The one place where side-effect will occurs is in hw/sd/core.c in
-sdbus_reparent_card(). This function is only used in the raspi machines,
-including during the sysbus reset procedure. This case will be
-carrefully handled when doing the multiple phase reset transition.
-Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/core/qdev.c | 16 +++++++++++-----
-file changed, 11 insertions(+), 5 deletions(-)
-diff --git a/hw/core/qdev.c b/hw/core/qdev.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/core/qdev.c
-+++ b/hw/core/qdev.c
-@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
- void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
- {
--    bool replugging = dev->parent_bus != NULL;
-+    BusState *old_parent_bus = dev->parent_bus;
--    if (replugging) {
-+    if (old_parent_bus) {
-         trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
--            dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)),
-+            old_parent_bus, object_get_typename(OBJECT(old_parent_bus)),
-             OBJECT(bus), object_get_typename(OBJECT(bus)));
-         /*
-          * Keep a reference to the device while it's not plugged into
-          * any bus, to avoid it potentially evaporating when it is
-          * dereffed in bus_remove_child().
-+         * Also keep the ref of the parent bus until the end, so that
-+         * we can safely call resettable_change_parent() below.
-          */
-         object_ref(OBJECT(dev));
-         bus_remove_child(dev->parent_bus, dev);
--        object_unref(OBJECT(dev->parent_bus));
-     }
-     dev->parent_bus = bus;
-     object_ref(OBJECT(bus));
-     bus_add_child(bus, dev);
--    if (replugging) {
-+    if (dev->realized) {
-+        resettable_change_parent(OBJECT(dev), OBJECT(bus),
-+                                 OBJECT(old_parent_bus));
-+    }
-+    if (old_parent_bus) {
-+        object_unref(OBJECT(old_parent_bus));
-         object_unref(OBJECT(dev));
-     }
- }
---
-.20.1

-[PULL 16/26] hw/core: deprecate old reset functions and introduce new ones
+[PULL 24/24] target/arm: Implement MVE shifts by register
-From: Damien Hedde <damien.hedde@greensocs.com>
+Implement the MVE shifts by register, which perform
 shifts on a single general-purpose register.
-Deprecate device_legacy_reset(), qdev_reset_all() and
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-qbus_reset_all() to be replaced by new functions
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-device_cold_reset() and bus_cold_reset() which uses resettable API.
+Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h |  2 ++
  target/arm/translate.h  |  1 +
  target/arm/t32.decode   | 18 ++++++++++++++----
  target/arm/mve_helper.c | 10 ++++++++++
  target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 files changed, 57 insertions(+), 4 deletions(-)
-Also introduce resettable_cold_reset_fn() which may be used as a
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 replacement for qdev_reset_all_fn and qbus_reset_all_fn().
 Following patches will be needed to look at legacy reset call sites
 and switch to resettable api. The legacy functions will be removed
 when unused.
 Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/qdev-core.h  | 27 +++++++++++++++++++++++++++
  include/hw/resettable.h |  9 +++++++++
  hw/core/bus.c           |  5 +++++
  hw/core/qdev.c          |  5 +++++
  hw/core/resettable.c    |  5 +++++
 files changed, 51 insertions(+)
 diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/qdev-core.h
+--- a/target/arm/helper-mve.h
-+++ b/include/hw/qdev-core.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ int qdev_walk_children(DeviceState *dev,
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-                        qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
-                        void *opaque);
+ DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+ DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+/**
++DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+ * @qdev_reset_all:
++DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+ * Reset @dev. See @qbus_reset_all() for more details.
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-+ *
+index XXXXXXX..XXXXXXX 100644
-+ * Note: This function is deprecated and will be removed when it becomes unused.
+--- a/target/arm/translate.h
-+ * Please use device_cold_reset() now.
++++ b/target/arm/translate.h
-+ */
+@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
- void qdev_reset_all(DeviceState *dev);
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
- void qdev_reset_all_fn(void *opaque);
+ typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
+ typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
-@@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque);
++typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
-  * hard reset means that qbus_reset_all will reset all state of the device.
-  * For PCI devices, for example, this will include the base address registers
+ /**
-  * or configuration space.
+  * arm_tbflags_from_tb:
-+ *
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-+ * Note: This function is deprecated and will be removed when it becomes unused.
+index XXXXXXX..XXXXXXX 100644
-+ * Please use bus_cold_reset() now.
+--- a/target/arm/t32.decode
-  */
++++ b/target/arm/t32.decode
- void qbus_reset_all(BusState *bus);
+@@ -XXX,XX +XXX,XX @@
- void qbus_reset_all_fn(void *opaque);
+ &mve_shl_ri      rdalo rdahi shim
+ &mve_shl_rr      rdalo rdahi rm
-+/**
+ &mve_sh_ri       rda shim
-+ * device_cold_reset:
++&mve_sh_rr       rda rm
-+ * Reset device @dev and perform a recursive processing using the resettable
-+ * interface. It triggers a RESET_TYPE_COLD.
+ # rdahi: bits [3:1] from insn, bit 0 is 1
-+ */
+ # rdalo: bits [3:1] from insn, bit 0 is 0
-+void device_cold_reset(DeviceState *dev);
+@@ -XXX,XX +XXX,XX @@
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
                   &mve_sh_ri shim=%imm5_12_6
 +@mve_sh_rr       ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
        SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
      }
 -    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
 -    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 -    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
 -    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
 +    {
 +      UQRSHL_rr    1110101 0010 1 ....  ....  1111 0000 1101  @mve_sh_rr
 +      LSLL_rr      1110101 0010 1 ... 0 .... ... 1 0000 1101  @mve_shl_rr
 +      UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101  @mve_shl_rr
 +    }
 +
-+/**
++    {
-+ * bus_cold_reset:
++      SQRSHR_rr    1110101 0010 1 ....  ....  1111 0010 1101  @mve_sh_rr
-+ *
++      ASRL_rr      1110101 0010 1 ... 0 .... ... 1 0010 1101  @mve_shl_rr
-+ * Reset bus @bus and perform a recursive processing using the resettable
++      SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101  @mve_shl_rr
-+ * interface. It triggers a RESET_TYPE_COLD.
++    }
 + */
 +void bus_cold_reset(BusState *bus);
 +
- /**
+     UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
-  * device_is_in_reset:
+     SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
-  * Return true if the device @dev is currently being reset.
+   ]
-@@ -XXX,XX +XXX,XX @@ void qdev_machine_init(void);
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
   * device_legacy_reset:
   *
   * Reset a single device (by calling the reset method).
 + * Note: This function is deprecated and will be removed when it becomes unused.
 + * Please use device_cold_reset() now.
   */
  void device_legacy_reset(DeviceState *dev);
 diff --git a/include/hw/resettable.h b/include/hw/resettable.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/resettable.h
+--- a/target/arm/mve_helper.c
-+++ b/include/hw/resettable.h
++++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ bool resettable_is_in_reset(Object *obj);
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-  */
+ {
- void resettable_change_parent(Object *obj, Object *newp, Object *oldp);
+     return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
+ }
 +/**
 + * resettable_cold_reset_fn:
 + * Helper to call resettable_reset((Object *) opaque, RESET_TYPE_COLD).
 + *
 + * This function is typically useful to register a reset handler with
 + * qemu_register_reset.
 + */
 +void resettable_cold_reset_fn(void *opaque);
 +
- /**
++uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
   * resettable_class_set_parent_phases:
   *
 diff --git a/hw/core/bus.c b/hw/core/bus.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/bus.c
 +++ b/hw/core/bus.c
@@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus,
      return 0;
  }
 +void bus_cold_reset(BusState *bus)
 +{
-+    resettable_reset(OBJECT(bus), RESET_TYPE_COLD);
++    return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
 +}
 +
- bool bus_is_in_reset(BusState *bus)
++uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
- {
++{
-     return resettable_is_in_reset(OBJECT(bus));
++    return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
-diff --git a/hw/core/qdev.c b/hw/core/qdev.c
++}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/qdev.c
+--- a/target/arm/translate.c
-+++ b/hw/core/qdev.c
++++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
-     qbus_reset_all(bus);
+     return do_mve_sh_ri(s, a, gen_mve_uqshl);
  }
-+void device_cold_reset(DeviceState *dev)
++static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
 +{
-+    resettable_reset(OBJECT(dev), RESET_TYPE_COLD);
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
 +        a->rm == a->rda) {
 +        /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
 +    fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
 +    return true;
 +}
 +
- bool device_is_in_reset(DeviceState *dev)
++static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
  {
      return resettable_is_in_reset(OBJECT(dev));
 diff --git a/hw/core/resettable.c b/hw/core/resettable.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/resettable.c
 +++ b/hw/core/resettable.c
@@ -XXX,XX +XXX,XX @@ void resettable_change_parent(Object *obj, Object *newp, Object *oldp)
      }
  }
 +void resettable_cold_reset_fn(void *opaque)
 +{
-+    resettable_reset((Object *) opaque, RESET_TYPE_COLD);
++    return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
 +}
 +
- void resettable_class_set_parent_phases(ResettableClass *rc,
++static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
-                                         ResettableEnterPhase enter,
++{
-                                         ResettableHoldPhase hold,
++    return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
 .20.1

-[PULL 18/26] vl: replace deprecated qbus_reset_all registration
+Deleted patch
-From: Damien Hedde <damien.hedde@greensocs.com>
-Replace deprecated qbus_reset_all by resettable_cold_reset_fn for
-the sysbus reset registration.
-Apart for the raspi machines, this does not impact the behavior
-because:
-+ at this point resettable just calls the old reset methods of devices
-  and buses in the same order as qdev/qbus.
-+ resettable handlers registered with qemu_register_reset are
-  serialized; there is no interleaving.
-+ eventual explicit calls to legacy reset API (device_reset or
-  qdev/qbus_reset) inside this reset handler will not be masked out
-  by resettable mechanism; they do not go through resettable api.
-For the raspi machines, during the sysbus reset the sd-card is not
-reset twice anymore but only once. This is a consequence of switching
-both sysbus reset and changing parent to resettable; it detects the
-second reset is not needed. This has no impact on the state after
-reset; the sd-card reset method only reset local state and query
-information from the block backend.
-The raspi reset change can be observed by using the following command
-(reset will occurs, then do Ctrl-C to end qemu; no firmware is
-given here).
-qemu-system-aarch64 -M raspi3 \
-    -trace resettable_phase_hold_exec \
-    -trace qdev_update_parent_bus \
-    -trace resettable_change_parent \
-    -trace qdev_reset -trace qbus_reset
-Before the patch, the qdev/qbus_reset traces show when reset method are
-called. After the patch, the resettable_phase_hold_exec show when reset
-method are called.
-The traced reset order of the raspi3 is listed below. I've added empty
-lines and the tree structure.
- +->bcm2835-peripherals reset
- |
- |       +->sd-card reset
- |   +->sd-bus reset
- +->bcm2835_gpio reset
- |      -> dev_update_parent_bus (move the sd-card on the sdhci-bus)
- |      -> resettable_change_parent
- |
- +->bcm2835-dma reset
- |
- |   +->bcm2835-sdhost-bus reset
- +->bcm2835-sdhost reset
- |
- |       +->sd-card (reset ONLY BEFORE BEFORE THE PATCH)
- |   +->sdhci-bus reset
- +->generic-sdhci reset
- |
- +->bcm2835-rng reset
- +->bcm2835-property reset
- +->bcm2835-fb reset
- +->bcm2835-mbox reset
- +->bcm2835-aux reset
- +->pl011 reset
- +->bcm2835-ic reset
- +->bcm2836-control reset
-System reset
-In both case, the sd-card is reset (being on bcm2835_gpio/sd-bus) then moved
-to generic-sdhci/sdhci-bus by the bcm2835_gpio reset method.
-Before the patch, it is then reset again being part of generic-sdhci/sdhci-bus.
-After the patch, it considered again for reset but its reset method is not
-called because it is already flagged as reset.
-Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200123132823.1117486-11-damien.hedde@greensocs.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- vl.c | 10 +++++++++-
-file changed, 9 insertions(+), 1 deletion(-)
-diff --git a/vl.c b/vl.c
-index XXXXXXX..XXXXXXX 100644
---- a/vl.c
-+++ b/vl.c
-@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
-     /* TODO: once all bus devices are qdevified, this should be done
-      * when bus is created by qdev.c */
--    qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
-+    /*
-+     * TODO: If we had a main 'reset container' that the whole system
-+     * lived in, we could reset that using the multi-phase reset
-+     * APIs. For the moment, we just reset the sysbus, which will cause
-+     * all devices hanging off it (and all their child buses, recursively)
-+     * to be reset. Note that this will *not* reset any Device objects
-+     * which are not attached to some part of the qbus tree!
-+     */
-+    qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
-     qemu_run_machine_init_done_notifiers();
-     if (rom_check_and_register_reset() != 0) {
---
-.20.1

target-arm queue. The big thing here is the landing of the 3-phase
reset patches...

-- PMM

The following changes since commit 204aa60b37c23a89e690d418f49787d274303ca7:

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging (2020-01-30 14:18:45 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200130

for you to fetch changes up to dea101a1ae9968c9fec6ab0291489dad7c49f36f:

target/arm/cpu: Add the kvm-no-adjvtime CPU property (2020-01-30 16:02:06 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
 * target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr
 * aspeed: some minor bugfixes
 * aspeed: add eMMC controller model for AST2600 SoC
 * hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'
 * New 3-phase reset API for device models
 * hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit
 * Arm KVM: stop/restart the guest counter when the VM is stopped and started

----------------------------------------------------------------
Andrew Jeffery (2):
      hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
      hw/arm: ast2600: Wire up the eMMC controller

Andrew Jones (6):
      target/arm/kvm: trivial: Clean up header documentation
      hw/arm/virt: Add missing 5.0 options call to 4.2 options
      target/arm/kvm64: kvm64 cpus have timer registers
      tests/arm-cpu-features: Check feature default values
      target/arm/kvm: Implement virtual time adjustment
      target/arm/cpu: Add the kvm-no-adjvtime CPU property

Cédric Le Goater (2):
      ftgmac100: check RX and TX buffer alignment
      hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0

Damien Hedde (11):
      add device_legacy_reset function to prepare for reset api change
      hw/core/qdev: add trace events to help with resettable transition
      hw/core: create Resettable QOM interface
      hw/core: add Resettable support to BusClass and DeviceClass
      hw/core/resettable: add support for changing parent
      hw/core/qdev: handle parent bus change regarding resettable
      hw/core/qdev: update hotplug reset regarding resettable
      hw/core: deprecate old reset functions and introduce new ones
      docs/devel/reset.rst: add doc about Resettable interface
      vl: replace deprecated qbus_reset_all registration
      hw/s390x/ipl: replace deprecated qdev_reset_all registration

Joel Stanley (1):
      misc/pca9552: Add qom set and get

Peter Maydell (2):
      hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES
      target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr

Philippe Mathieu-Daudé (1):
      hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus'

Zenghui Yu (1):
      hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit

The num-lines property of the TYPE_OR_GATE device sets the number
of input lines it has. An assert() in or_irq_realize() restricts
this to the maximum supported by the implementation. However we
got the condition in the assert wrong: it should be using <=,
because num-lines == MAX_OR_LINES is permitted, and means that
all entries from 0 to MAX_OR_LINES-1 in the s->levels[] array
are used.

We didn't notice this previously because no user has so far
needed that many input lines.

Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200120142235.10432-1-peter.maydell@linaro.org
---
 hw/core/or-irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/or-irq.c
+++ b/hw/core/or-irq.c
@@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp)
 {
     qemu_or_irq *s = OR_IRQ(dev);
 
-    assert(s->num_lines < MAX_OR_LINES);
+    assert(s->num_lines <= MAX_OR_LINES);
 
     qdev_init_gpio_in(dev, or_irq_handler, s->num_lines);
 }
-- 
2.20.1

The guest can use the semihosting API to open a handle
corresponding to QEMU's own stdin, stdout, or stderr.
When the guest closes this handle, we should not
close the underlying host stdin/stdout/stderr
the way we would do if the handle corresponded to
a host fd we'd opened on behalf of the guest in SYS_OPEN.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200124172954.28481-1-peter.maydell@linaro.org
---
 target/arm/arm-semi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf)
 {
     CPUARMState *env = &cpu->env;
 
+    /*
+     * Only close the underlying host fd if it's one we opened on behalf
+     * of the guest in SYS_OPEN.
+     */
+    if (gf->hostfd == STDIN_FILENO ||
+        gf->hostfd == STDOUT_FILENO ||
+        gf->hostfd == STDERR_FILENO) {
+        return 0;
+    }
     return set_swi_errno(env, close(gf->hostfd));
 }
 
-- 
2.20.1

From: Andrew Jeffery <andrew@aj.id.au>

The AST2600 includes a second cut-down version of the SD/MMC controller
found in the AST2500, named the eMMC controller. It's cut down in the
sense that it only supports one slot rather than two, but it brings the
total number of slots supported by the AST2600 to three.

The existing code assumed that the SD controller always provided two
slots. Rework the SDHCI object to expose the number of slots as a
property to be set by the SoC configuration.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-2-clg@kaod.org
[PMM: fixed up to use device_class_set_props()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/sd/aspeed_sdhci.h |  1 +
 hw/arm/aspeed.c              |  2 +-
 hw/arm/aspeed_ast2600.c      |  2 ++
 hw/arm/aspeed_soc.c          |  2 ++
 hw/sd/aspeed_sdhci.c         | 11 +++++++++--
 5 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/sd/aspeed_sdhci.h
+++ b/include/hw/sd/aspeed_sdhci.h
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDHCIState {
     SysBusDevice parent;
 
     SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
+    uint8_t num_slots;
 
     MemoryRegion iomem;
     qemu_irq irq;
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
         amc->i2c_init(bmc);
     }
 
-    for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) {
+    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
         SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
         DriveInfo *dinfo = drive_get_next(IF_SD);
         BlockBackend *blk;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
                           TYPE_ASPEED_SDHCI);
 
+    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
+
     /* Init sd card slot class here so that they're under the correct parent */
     for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
         sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
     sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
                           TYPE_ASPEED_SDHCI);
 
+    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
+
     /* Init sd card slot class here so that they're under the correct parent */
     for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
         sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/irq.h"
 #include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
 
 #define ASPEED_SDHCI_INFO            0x00
 #define  ASPEED_SDHCI_INFO_RESET     0x00030000
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
 
     /* Create input irqs for the slots */
     qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
-                                        sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS);
+                                        sdhci, NULL, sdhci->num_slots);
 
     sysbus_init_irq(sbd, &sdhci->irq);
     memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
                           sdhci, TYPE_ASPEED_SDHCI, 0x1000);
     sysbus_init_mmio(sbd, &sdhci->iomem);
 
-    for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
+    for (int i = 0; i < sdhci->num_slots; ++i) {
         Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
         SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
 
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdhci = {
     },
 };
 
+static Property aspeed_sdhci_properties[] = {
+    DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(classp);
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
     dc->realize = aspeed_sdhci_realize;
     dc->reset = aspeed_sdhci_reset;
     dc->vmsd = &vmstate_aspeed_sdhci;
+    device_class_set_props(dc, aspeed_sdhci_properties);
 }
 
 static TypeInfo aspeed_sdhci_info = {
-- 
2.20.1

From: Andrew Jeffery <andrew@aj.id.au>

Initialise another SDHCI model instance for the AST2600's eMMC
controller and use the SDHCI's num_slots value introduced previously to
determine whether we should create an SD card instance for the new slot.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-3-clg@kaod.org
[ clg : - removed ternary operator from sdhci_attach_drive()
        - renamed SDHCI objects with a '-controller' prefix ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/aspeed_soc.h |  2 ++
 hw/arm/aspeed.c             | 26 +++++++++++++++++---------
 hw/arm/aspeed_ast2600.c     | 29 ++++++++++++++++++++++++++---
 3 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
     AspeedGPIOState gpio;
     AspeedGPIOState gpio_1_8v;
     AspeedSDHCIState sdhci;
+    AspeedSDHCIState emmc;
 } AspeedSoCState;
 
 #define TYPE_ASPEED_SOC "aspeed-soc"
@@ -XXX,XX +XXX,XX @@ enum {
     ASPEED_MII4,
     ASPEED_SDRAM,
     ASPEED_XDMA,
+    ASPEED_EMMC,
 };
 
 #endif /* ASPEED_SOC_H */
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
     }
 }
 
+static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
+{
+        DeviceState *card;
+
+        card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
+                           TYPE_SD_CARD);
+        if (dinfo) {
+            qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo),
+                                &error_fatal);
+        }
+        object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+}
+
 static void aspeed_machine_init(MachineState *machine)
 {
     AspeedBoardState *bmc;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
     }
 
     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
-        SDHCIState *sdhci = &bmc->soc.sdhci.slots[i];
-        DriveInfo *dinfo = drive_get_next(IF_SD);
-        BlockBackend *blk;
-        DeviceState *card;
+        sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
+    }
 
-        blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
-        card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
-                           TYPE_SD_CARD);
-        qdev_prop_set_drive(card, "drive", blk, &error_fatal);
-        object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+    if (bmc->soc.emmc.num_slots) {
+        sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
     }
 
     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_ADC]       = 0x1E6E9000,
     [ASPEED_VIDEO]     = 0x1E700000,
     [ASPEED_SDHCI]     = 0x1E740000,
+    [ASPEED_EMMC]      = 0x1E750000,
     [ASPEED_GPIO]      = 0x1E780000,
     [ASPEED_GPIO_1_8V] = 0x1E780800,
     [ASPEED_RTC]       = 0x1E781000,
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
 
 #define ASPEED_SOC_AST2600_MAX_IRQ 128
 
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
 static const int aspeed_soc_ast2600_irqmap[] = {
     [ASPEED_UART1]     = 47,
     [ASPEED_UART2]     = 48,
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
     [ASPEED_ADC]       = 78,
     [ASPEED_XDMA]      = 6,
     [ASPEED_SDHCI]     = 43,
+    [ASPEED_EMMC]      = 15,
     [ASPEED_GPIO]      = 40,
     [ASPEED_GPIO_1_8V] = 11,
     [ASPEED_RTC]       = 13,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
                           sizeof(s->gpio_1_8v), typename);
 
-    sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
-                          TYPE_ASPEED_SDHCI);
+    sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci),
+                          sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
 
     object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
 
     /* Init sd card slot class here so that they're under the correct parent */
     for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
-        sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
+        sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
+                              OBJECT(&s->sdhci.slots[i]),
                               sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
     }
+
+    sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc),
+                          sizeof(s->emmc), TYPE_ASPEED_SDHCI);
+
+    object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
+
+    sysbus_init_child_obj(obj, "emmc-controller.sdhci",
+                          OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]),
+                          TYPE_SYSBUS_SDHCI);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
                     sc->memmap[ASPEED_SDHCI]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                        aspeed_soc_get_irq(s, ASPEED_SDHCI));
+
+    /* eMMC */
+    object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
+                       aspeed_soc_get_irq(s, ASPEED_EMMC));
 }
 
 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
-- 
2.20.1

From: Cédric Le Goater <clg@kaod.org>

These buffers should be aligned on 16 bytes.

Ignore invalid RX and TX buffer addresses and log an error. All
incoming and outgoing traffic will be dropped because no valid RX or
TX descriptors will be available.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-4-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/ftgmac100.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint32_t        des3;
 } FTGMAC100Desc;
 
+#define FTGMAC100_DESC_ALIGNMENT 16
+
 /*
  * Specific RTL8211E MII Registers
  */
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
         s->itc = value;
         break;
     case FTGMAC100_RXR_BADR: /* Ring buffer address */
+        if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%"
+                          HWADDR_PRIx "\n", __func__, value);
+            return;
+        }
+
         s->rx_ring = value;
         s->rx_descriptor = s->rx_ring;
         break;
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
         break;
 
     case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
+        if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%"
+                          HWADDR_PRIx "\n", __func__, value);
+            return;
+        }
         s->tx_ring = value;
         s->tx_descriptor = s->tx_ring;
         break;
-- 
2.20.1

From: Cédric Le Goater <clg@kaod.org>

The overhead for the OpenBMC firmware images using the a custom U-Boot
is around 2 seconds, which is fine, but with a U-Boot from mainline,
it takes an extra 50 seconds or so to reach Linux. A quick survey on
the number of reads performed on the flash memory region gives the
following figures :

OpenBMC U-Boot      922478 (~ 3.5 MBytes)
  Mainline U-Boot   20569977 (~ 80  MBytes)

QEMU must be trashing the TCG TBs and reloading text very often. Some
addresses are read more than 250.000 times. Until we find a solution
to improve boot time, execution from MMIO is not activated by default.

Setting this option also breaks migration compatibility.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200114103433.30534-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/aspeed.h |  2 ++
 hw/arm/aspeed.c         | 44 ++++++++++++++++++++++++++++++++++++-----
 2 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardState AspeedBoardState;
 
 typedef struct AspeedMachine {
     MachineState parent_obj;
+
+    bool mmio_exec;
 } AspeedMachine;
 
 #define ASPEED_MACHINE_CLASS(klass) \
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          * SoC and 128MB for the AST2500 SoC, which is twice as big as
          * needed by the flash modules of the Aspeed machines.
          */
-        memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
-                               fl->size, &error_abort);
-        memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
-                                    boot_rom);
-        write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
+        if (ASPEED_MACHINE(machine)->mmio_exec) {
+            memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
+                                     &fl->mmio, 0, fl->size);
+            memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
+                                        boot_rom);
+        } else {
+            memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
+                                   fl->size, &error_abort);
+            memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
+                                        boot_rom);
+            write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
+        }
     }
 
     aspeed_board_binfo.ram_size = ram_size;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
     /* Bus 11: TODO ucd90160@64 */
 }
 
+static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
+{
+    return ASPEED_MACHINE(obj)->mmio_exec;
+}
+
+static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
+{
+    ASPEED_MACHINE(obj)->mmio_exec = value;
+}
+
+static void aspeed_machine_instance_init(Object *obj)
+{
+    ASPEED_MACHINE(obj)->mmio_exec = false;
+}
+
+static void aspeed_machine_class_props_init(ObjectClass *oc)
+{
+    object_class_property_add_bool(oc, "execute-in-place",
+                                   aspeed_get_mmio_exec,
+                                   aspeed_set_mmio_exec, &error_abort);
+    object_class_property_set_description(oc, "execute-in-place",
+                           "boot directly from CE0 flash device", &error_abort);
+}
+
 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->no_parallel = 1;
+
+    aspeed_machine_class_props_init(oc);
 }
 
 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = TYPE_ASPEED_MACHINE,
         .parent        = TYPE_MACHINE,
         .instance_size = sizeof(AspeedMachine),
+        .instance_init = aspeed_machine_instance_init,
         .class_size    = sizeof(AspeedMachineClass),
         .class_init    = aspeed_machine_class_init,
         .abstract      = true,
-- 
2.20.1

From: Joel Stanley <joel@jms.id.au>

Following the pattern of the work recently done with the ASPEED GPIO
model, this adds support for inspecting and modifying the PCA9552 LEDs
from the monitor.

(qemu) qom-set  /machine/unattached/device[17] led0 on
 (qemu) qom-set  /machine/unattached/device[17] led0 off
 (qemu) qom-set  /machine/unattached/device[17] led0 pwm0
 (qemu) qom-set  /machine/unattached/device[17] led0 pwm1

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200114103433.30534-6-clg@kaod.org
[clg: - removed the "qom-get" examples from the commit log
      - merged memory leak fixes from Joel ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/pca9552.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/pca9552.c
+++ b/hw/misc/pca9552.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/pca9552.h"
 #include "hw/misc/pca9552_regs.h"
 #include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
 
 #define PCA9552_LED_ON   0x0
 #define PCA9552_LED_OFF  0x1
 #define PCA9552_LED_PWM0 0x2
 #define PCA9552_LED_PWM1 0x3
 
+static const char *led_state[] = {"on", "off", "pwm0", "pwm1"};
+
 static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin)
 {
     uint8_t reg   = PCA9552_LS0 + (pin / 4);
@@ -XXX,XX +XXX,XX @@ static int pca9552_event(I2CSlave *i2c, enum i2c_event event)
     return 0;
 }
 
+static void pca9552_get_led(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    PCA9552State *s = PCA9552(obj);
+    int led, rc, reg;
+    uint8_t state;
+
+    rc = sscanf(name, "led%2d", &led);
+    if (rc != 1) {
+        error_setg(errp, "%s: error reading %s", __func__, name);
+        return;
+    }
+    if (led < 0 || led > s->nr_leds) {
+        error_setg(errp, "%s invalid led %s", __func__, name);
+        return;
+    }
+    /*
+     * Get the LSx register as the qom interface should expose the device
+     * state, not the modeled 'input line' behaviour which would come from
+     * reading the INPUTx reg
+     */
+    reg = PCA9552_LS0 + led / 4;
+    state = (pca9552_read(s, reg) >> (led % 8)) & 0x3;
+    visit_type_str(v, name, (char **)&led_state[state], errp);
+}
+
+/*
+ * Return an LED selector register value based on an existing one, with
+ * the appropriate 2-bit state value set for the given LED number (0-3).
+ */
+static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state)
+{
+        return (oldval & (~(0x3 << (led_num << 1)))) |
+                ((state & 0x3) << (led_num << 1));
+}
+
+static void pca9552_set_led(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    PCA9552State *s = PCA9552(obj);
+    Error *local_err = NULL;
+    int led, rc, reg, val;
+    uint8_t state;
+    char *state_str;
+
+    visit_type_str(v, name, &state_str, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+    rc = sscanf(name, "led%2d", &led);
+    if (rc != 1) {
+        error_setg(errp, "%s: error reading %s", __func__, name);
+        return;
+    }
+    if (led < 0 || led > s->nr_leds) {
+        error_setg(errp, "%s invalid led %s", __func__, name);
+        return;
+    }
+
+    for (state = 0; state < ARRAY_SIZE(led_state); state++) {
+        if (!strcmp(state_str, led_state[state])) {
+            break;
+        }
+    }
+    if (state >= ARRAY_SIZE(led_state)) {
+        error_setg(errp, "%s invalid led state %s", __func__, state_str);
+        return;
+    }
+
+    reg = PCA9552_LS0 + led / 4;
+    val = pca9552_read(s, reg);
+    val = pca955x_ledsel(val, led % 4, state);
+    pca9552_write(s, reg, val);
+}
+
 static const VMStateDescription pca9552_vmstate = {
     .name = "PCA9552",
     .version_id = 0,
@@ -XXX,XX +XXX,XX @@ static void pca9552_reset(DeviceState *dev)
 static void pca9552_initfn(Object *obj)
 {
     PCA9552State *s = PCA9552(obj);
+    int led;
 
     /* If support for the other PCA955X devices are implemented, these
      * constant values might be part of class structure describing the
@@ -XXX,XX +XXX,XX @@ static void pca9552_initfn(Object *obj)
      */
     s->max_reg = PCA9552_LS3;
     s->nr_leds = 16;
+
+    for (led = 0; led < s->nr_leds; led++) {
+        char *name;
+
+        name = g_strdup_printf("led%d", led);
+        object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led,
+                            NULL, NULL, NULL);
+        g_free(name);
+    }
 }
 
 static void pca9552_class_init(ObjectClass *klass, void *data)
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Since we enabled parallel TCG code generation for softmmu (see
commit 3468b59 "tcg: enable multiple TCG contexts in softmmu")
and its subsequent fix (commit 72649619 "add .min_cpus and
.default_cpus fields to machine_class"), the raspi machines are
restricted to always use their 4 cores:

See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4):

222 static void raspi2_machine_init(MachineClass *mc)
  223 {
  224     mc->desc = "Raspberry Pi 2";
  230     mc->max_cpus = BCM283X_NCPUS;
  231     mc->min_cpus = BCM283X_NCPUS;
  232     mc->default_cpus = BCM283X_NCPUS;
  235 };
  236 DEFINE_MACHINE("raspi2", raspi2_machine_init)

We can no longer use the -smp option, as we get:

$ qemu-system-arm -M raspi2 -smp 1
  qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4

Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp,
remove the unuseful code.

We can achieve the same by using the '-global bcm2836.enabled-cpus=1'
option.

Reported-by: Laurent Bonnans <laurent.bonnans@here.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200120235159.18510-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus",
-                            &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
     object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
                             &error_abort);
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Provide a temporary device_legacy_reset function doing what
device_reset does to prepare for the transition with Resettable
API.

All occurrence of device_reset in the code tree are also replaced
by device_legacy_reset.

The new resettable API has different prototype and semantics
(resetting child buses as well as the specified device). Subsequent
commits will make the changeover for each call site individually; once
that is complete device_legacy_reset() will be removed.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/qdev-core.h   | 4 ++--
 hw/audio/intel-hda.c     | 2 +-
 hw/core/qdev.c           | 6 +++---
 hw/hyperv/hyperv.c       | 2 +-
 hw/i386/microvm.c        | 2 +-
 hw/i386/pc.c             | 2 +-
 hw/ide/microdrive.c      | 8 ++++----
 hw/intc/spapr_xive.c     | 2 +-
 hw/ppc/pnv_psi.c         | 4 ++--
 hw/ppc/spapr_pci.c       | 2 +-
 hw/ppc/spapr_vio.c       | 2 +-
 hw/s390x/s390-pci-inst.c | 2 +-
 hw/scsi/vmw_pvscsi.c     | 2 +-
 hw/sd/omap_mmc.c         | 2 +-
 hw/sd/pl181.c            | 2 +-
 15 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -XXX,XX +XXX,XX @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev);
 void qdev_machine_init(void);
 
 /**
- * @device_reset
+ * device_legacy_reset:
  *
  * Reset a single device (by calling the reset method).
  */
-void device_reset(DeviceState *dev);
+void device_legacy_reset(DeviceState *dev);
 
 void device_class_set_props(DeviceClass *dc, Property *props);
 
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -XXX,XX +XXX,XX @@ static void intel_hda_reset(DeviceState *dev)
     QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
         DeviceState *qdev = kid->child;
         cdev = HDA_CODEC_DEVICE(qdev);
-        device_reset(DEVICE(cdev));
+        device_legacy_reset(DEVICE(cdev));
         d->state_sts |= (1 << cdev->cad);
     }
     intel_hda_update_irq(d);
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev)
 
 static int qdev_reset_one(DeviceState *dev, void *opaque)
 {
-    device_reset(dev);
+    device_legacy_reset(dev);
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
             }
         }
         if (dev->hotplugged) {
-            device_reset(dev);
+            device_legacy_reset(dev);
         }
         dev->pending_deleted_event = false;
 
@@ -XXX,XX +XXX,XX @@ void device_class_set_parent_unrealize(DeviceClass *dc,
     dc->unrealize = dev_unrealize;
 }
 
-void device_reset(DeviceState *dev)
+void device_legacy_reset(DeviceState *dev)
 {
     DeviceClass *klass = DEVICE_GET_CLASS(dev);
 
diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/hyperv/hyperv.c
+++ b/hw/hyperv/hyperv.c
@@ -XXX,XX +XXX,XX @@ void hyperv_synic_reset(CPUState *cs)
     SynICState *synic = get_synic(cs);
 
     if (synic) {
-        device_reset(DEVICE(synic));
+        device_legacy_reset(DEVICE(synic));
     }
 }
 
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -XXX,XX +XXX,XX @@ static void microvm_machine_reset(MachineState *machine)
         cpu = X86_CPU(cs);
 
         if (cpu->apic_state) {
-            device_reset(cpu->apic_state);
+            device_legacy_reset(cpu->apic_state);
         }
     }
 }
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -XXX,XX +XXX,XX @@ static void pc_machine_reset(MachineState *machine)
         cpu = X86_CPU(cs);
 
         if (cpu->apic_state) {
-            device_reset(cpu->apic_state);
+            device_legacy_reset(cpu->apic_state);
         }
     }
 }
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ide/microdrive.c
+++ b/hw/ide/microdrive.c
@@ -XXX,XX +XXX,XX @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
     case 0x00:	/* Configuration Option Register */
         s->opt = value & 0xcf;
         if (value & OPT_SRESET) {
-            device_reset(DEVICE(s));
+            device_legacy_reset(DEVICE(s));
         }
         md_interrupt_update(s);
         break;
@@ -XXX,XX +XXX,XX @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
     case 0xe:	/* Device Control */
         s->ctrl = value;
         if (value & CTRL_SRST) {
-            device_reset(DEVICE(s));
+            device_legacy_reset(DEVICE(s));
         }
         md_interrupt_update(s);
         break;
@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_attach(PCMCIACardState *card)
     md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
     md->io_base = 0x0;
 
-    device_reset(DEVICE(md));
+    device_legacy_reset(DEVICE(md));
     md_interrupt_update(md);
 
     return 0;
@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_detach(PCMCIACardState *card)
 {
     MicroDriveState *md = MICRODRIVE(card);
 
-    device_reset(DEVICE(md));
+    device_legacy_reset(DEVICE(md));
     return 0;
 }
 
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -XXX,XX +XXX,XX @@ static target_ulong h_int_reset(PowerPCCPU *cpu,
         return H_PARAMETER;
     }
 
-    device_reset(DEVICE(xive));
+    device_legacy_reset(DEVICE(xive));
 
     if (kvm_irqchip_in_kernel()) {
         Error *local_err = NULL;
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -XXX,XX +XXX,XX @@ static void pnv_psi_reset(DeviceState *dev)
 
 static void pnv_psi_reset_handler(void *dev)
 {
-    device_reset(DEVICE(dev));
+    device_legacy_reset(DEVICE(dev));
 }
 
 static void pnv_psi_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
         break;
     case PSIHB9_INTERRUPT_CONTROL:
         if (val & PSIHB9_IRQ_RESET) {
-            device_reset(DEVICE(&psi9->source));
+            device_legacy_reset(DEVICE(&psi9->source));
         }
         psi->regs[reg] = val;
         break;
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -XXX,XX +XXX,XX @@ static int spapr_phb_children_reset(Object *child, void *opaque)
     DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
 
     if (dev) {
-        device_reset(dev);
+        device_legacy_reset(dev);
     }
 
     return 0;
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -XXX,XX +XXX,XX @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq)
 static void spapr_vio_quiesce_one(SpaprVioDevice *dev)
 {
     if (dev->tcet) {
-        device_reset(DEVICE(dev->tcet));
+        device_legacy_reset(DEVICE(dev->tcet));
     }
     free_crq(dev);
 }
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -XXX,XX +XXX,XX @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
                 goto out;
             }
-            device_reset(DEVICE(pbdev));
+            device_legacy_reset(DEVICE(pbdev));
             pbdev->fh &= ~FH_MASK_ENABLE;
             pbdev->state = ZPCI_FS_DISABLED;
             stl_p(&ressetpci->fh, pbdev->fh);
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -XXX,XX +XXX,XX @@ pvscsi_on_cmd_reset_device(PVSCSIState *s)
 
     if (sdev != NULL) {
         s->resetting++;
-        device_reset(&sdev->qdev);
+        device_legacy_reset(&sdev->qdev);
         s->resetting--;
         return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
     }
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
      * into any bus, and we must reset it manually. When omap_mmc is
      * QOMified this must move into the QOM reset function.
      */
-    device_reset(DEVICE(host->card));
+    device_legacy_reset(DEVICE(host->card));
 }
 
 static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/pl181.c
+++ b/hw/sd/pl181.c
@@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d)
     /* Since we're still using the legacy SD API the card is not plugged
      * into any bus, and we must reset it manually.
      */
-    device_reset(DEVICE(s->card));
+    device_legacy_reset(DEVICE(s->card));
 }
 
 static void pl181_init(Object *obj)
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Adds trace events to reset procedure and when updating the parent
bus of a device.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/core/qdev.c       | 29 ++++++++++++++++++++++++++---
 hw/core/trace-events |  9 +++++++++
 2 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
+#include "trace.h"
 
 bool qdev_hotplug = false;
 static bool qdev_hot_added = false;
@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
     bool replugging = dev->parent_bus != NULL;
 
     if (replugging) {
-        /* Keep a reference to the device while it's not plugged into
+        trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
+            dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)),
+            OBJECT(bus), object_get_typename(OBJECT(bus)));
+        /*
+         * Keep a reference to the device while it's not plugged into
          * any bus, to avoid it potentially evaporating when it is
          * dereffed in bus_remove_child().
          */
@@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev)
     return hotplug_ctrl;
 }
 
+static int qdev_prereset(DeviceState *dev, void *opaque)
+{
+    trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev)));
+    return 0;
+}
+
+static int qbus_prereset(BusState *bus, void *opaque)
+{
+    trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus)));
+    return 0;
+}
+
 static int qdev_reset_one(DeviceState *dev, void *opaque)
 {
     device_legacy_reset(dev);
@@ -XXX,XX +XXX,XX @@ static int qdev_reset_one(DeviceState *dev, void *opaque)
 static int qbus_reset_one(BusState *bus, void *opaque)
 {
     BusClass *bc = BUS_GET_CLASS(bus);
+    trace_qbus_reset(bus, object_get_typename(OBJECT(bus)));
     if (bc->reset) {
         bc->reset(bus);
     }
@@ -XXX,XX +XXX,XX @@ static int qbus_reset_one(BusState *bus, void *opaque)
 
 void qdev_reset_all(DeviceState *dev)
 {
-    qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
+    trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev)));
+    qdev_walk_children(dev, qdev_prereset, qbus_prereset,
+                       qdev_reset_one, qbus_reset_one, NULL);
 }
 
 void qdev_reset_all_fn(void *opaque)
@@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque)
 
 void qbus_reset_all(BusState *bus)
 {
-    qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL);
+    trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus)));
+    qbus_walk_children(bus, qdev_prereset, qbus_prereset,
+                       qdev_reset_one, qbus_reset_one, NULL);
 }
 
 void qbus_reset_all_fn(void *opaque)
@@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev)
 {
     DeviceClass *klass = DEVICE_GET_CLASS(dev);
 
+    trace_qdev_reset(dev, object_get_typename(OBJECT(dev)));
     if (klass->reset) {
         klass->reset(dev);
     }
diff --git a/hw/core/trace-events b/hw/core/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -XXX,XX +XXX,XX @@
 # loader.c
 loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d"
+
+# qdev.c
+qdev_reset(void *obj, const char *objtype) "obj=%p(%s)"
+qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
+qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
+qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
+qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
+qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
+qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

This commit defines an interface allowing multi-phase reset. This aims
to solve a problem of the actual single-phase reset (built in
DeviceClass and BusClass): reset behavior is dependent on the order
in which reset handlers are called. In particular doing external
side-effect (like setting an qemu_irq) is problematic because receiving
object may not be reset yet.

The Resettable interface divides the reset in 3 well defined phases.
To reset an object tree, all 1st phases are executed then all 2nd then
all 3rd. See the comments in include/hw/resettable.h for a more complete
description. The interface defines 3 phases to let the future
possibility of holding an object into reset for some time.

The qdev/qbus reset in DeviceClass and BusClass will be modified in
following commits to use this interface. A mechanism is provided
to allow executing a transitional reset handler in place of the 2nd
phase which is executed in children-then-parent order inside a tree.
This will allow to transition devices and buses smoothly while
keeping the exact current qdev/qbus reset behavior for now.

Documentation will be added in a following commit.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/core/Makefile.objs   |   1 +
 include/hw/resettable.h | 211 +++++++++++++++++++++++++++++++++++
 hw/core/resettable.c    | 238 ++++++++++++++++++++++++++++++++++++++++
 hw/core/trace-events    |  17 +++
 4 files changed, 467 insertions(+)
 create mode 100644 include/hw/resettable.h
 create mode 100644 hw/core/resettable.c

diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -XXX,XX +XXX,XX @@
 common-obj-y += qdev.o qdev-properties.o
 common-obj-y += bus.o
 common-obj-y += cpu.o
+common-obj-y += resettable.o
 common-obj-y += hotplug.o
 common-obj-y += vmstate-if.o
 # irq.o needed for qdev GPIO handling:
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/resettable.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Resettable interface header.
+ *
+ * Copyright (c) 2019 GreenSocs SAS
+ *
+ * Authors:
+ *   Damien Hedde
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef HW_RESETTABLE_H
+#define HW_RESETTABLE_H
+
+#include "qom/object.h"
+
+#define TYPE_RESETTABLE_INTERFACE "resettable"
+
+#define RESETTABLE_CLASS(class) \
+    OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE_INTERFACE)
+
+#define RESETTABLE_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE)
+
+typedef struct ResettableState ResettableState;
+
+/**
+ * ResetType:
+ * Types of reset.
+ *
+ * + Cold: reset resulting from a power cycle of the object.
+ *
+ * TODO: Support has to be added to handle more types. In particular,
+ * ResettableState structure needs to be expanded.
+ */
+typedef enum ResetType {
+    RESET_TYPE_COLD,
+} ResetType;
+
+/*
+ * ResettableClass:
+ * Interface for resettable objects.
+ *
+ * See docs/devel/reset.rst for more detailed information about how QEMU models
+ * reset. This whole API must only be used when holding the iothread mutex.
+ *
+ * All objects which can be reset must implement this interface;
+ * it is usually provided by a base class such as DeviceClass or BusClass.
+ * Every Resettable object must maintain some state tracking the
+ * progress of a reset operation by providing a ResettableState structure.
+ * The functions defined in this module take care of updating the
+ * state of the reset.
+ * The base class implementation of the interface provides this
+ * state and implements the associated method: get_state.
+ *
+ * Concrete object implementations (typically specific devices
+ * such as a UART model) should provide the functions
+ * for the phases.enter, phases.hold and phases.exit methods, which
+ * they can set in their class init function, either directly or
+ * by calling resettable_class_set_parent_phases().
+ * The phase methods are guaranteed to only only ever be called once
+ * for any reset event, in the order 'enter', 'hold', 'exit'.
+ * An object will always move quickly from 'enter' to 'hold'
+ * but might remain in 'hold' for an arbitrary period of time
+ * before eventually reset is deasserted and the 'exit' phase is called.
+ * Object implementations should be prepared for functions handling
+ * inbound connections from other devices (such as qemu_irq handler
+ * functions) to be called at any point during reset after their
+ * 'enter' method has been called.
+ *
+ * Users of a resettable object should not call these methods
+ * directly, but instead use the function resettable_reset().
+ *
+ * @phases.enter: This phase is called when the object enters reset. It
+ * should reset local state of the object, but it must not do anything that
+ * has a side-effect on other objects, such as raising or lowering a qemu_irq
+ * line or reading or writing guest memory. It takes the reset's type as
+ * argument.
+ *
+ * @phases.hold: This phase is called for entry into reset, once every object
+ * in the system which is being reset has had its @phases.enter method called.
+ * At this point devices can do actions that affect other objects.
+ *
+ * @phases.exit: This phase is called when the object leaves the reset state.
+ * Actions affecting other objects are permitted.
+ *
+ * @get_state: Mandatory method which must return a pointer to a
+ * ResettableState.
+ *
+ * @get_transitional_function: transitional method to handle Resettable objects
+ * not yet fully moved to this interface. It will be removed as soon as it is
+ * not needed anymore. This method is optional and may return a pointer to a
+ * function to be used instead of the phases. If the method exists and returns
+ * a non-NULL function pointer then that function is executed as a replacement
+ * of the 'hold' phase method taking the object as argument. The two other phase
+ * methods are not executed.
+ *
+ * @child_foreach: Executes a given callback on every Resettable child. Child
+ * in this context means a child in the qbus tree, so the children of a qbus
+ * are the devices on it, and the children of a device are all the buses it
+ * owns. This is not the same as the QOM object hierarchy. The function takes
+ * additional opaque and ResetType arguments which must be passed unmodified to
+ * the callback.
+ */
+typedef void (*ResettableEnterPhase)(Object *obj, ResetType type);
+typedef void (*ResettableHoldPhase)(Object *obj);
+typedef void (*ResettableExitPhase)(Object *obj);
+typedef ResettableState * (*ResettableGetState)(Object *obj);
+typedef void (*ResettableTrFunction)(Object *obj);
+typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj);
+typedef void (*ResettableChildCallback)(Object *, void *opaque,
+                                        ResetType type);
+typedef void (*ResettableChildForeach)(Object *obj,
+                                       ResettableChildCallback cb,
+                                       void *opaque, ResetType type);
+typedef struct ResettablePhases {
+    ResettableEnterPhase enter;
+    ResettableHoldPhase hold;
+    ResettableExitPhase exit;
+} ResettablePhases;
+typedef struct ResettableClass {
+    InterfaceClass parent_class;
+
+    /* Phase methods */
+    ResettablePhases phases;
+
+    /* State access method */
+    ResettableGetState get_state;
+
+    /* Transitional method for legacy reset compatibility */
+    ResettableGetTrFunction get_transitional_function;
+
+    /* Hierarchy handling method */
+    ResettableChildForeach child_foreach;
+} ResettableClass;
+
+/**
+ * ResettableState:
+ * Structure holding reset related state. The fields should not be accessed
+ * directly; the definition is here to allow further inclusion into other
+ * objects.
+ *
+ * @count: Number of reset level the object is into. It is incremented when
+ * the reset operation starts and decremented when it finishes.
+ * @hold_phase_pending: flag which indicates that we need to invoke the 'hold'
+ * phase handler for this object.
+ * @exit_phase_in_progress: true if we are currently in the exit phase
+ */
+struct ResettableState {
+    unsigned count;
+    bool hold_phase_pending;
+    bool exit_phase_in_progress;
+};
+
+/**
+ * resettable_reset:
+ * Trigger a reset on an object @obj of type @type. @obj must implement
+ * Resettable interface.
+ *
+ * Calling this function is equivalent to calling @resettable_assert_reset()
+ * then @resettable_release_reset().
+ */
+void resettable_reset(Object *obj, ResetType type);
+
+/**
+ * resettable_assert_reset:
+ * Put an object @obj into reset. @obj must implement Resettable interface.
+ *
+ * @resettable_release_reset() must eventually be called after this call.
+ * There must be one call to @resettable_release_reset() per call of
+ * @resettable_assert_reset(), with the same type argument.
+ *
+ * NOTE: Until support for migration is added, the @resettable_release_reset()
+ * must not be delayed. It must occur just after @resettable_assert_reset() so
+ * that migration cannot be triggered in between. Prefer using
+ * @resettable_reset() for now.
+ */
+void resettable_assert_reset(Object *obj, ResetType type);
+
+/**
+ * resettable_release_reset:
+ * Release the object @obj from reset. @obj must implement Resettable interface.
+ *
+ * See @resettable_assert_reset() description for details.
+ */
+void resettable_release_reset(Object *obj, ResetType type);
+
+/**
+ * resettable_is_in_reset:
+ * Return true if @obj is under reset.
+ *
+ * @obj must implement Resettable interface.
+ */
+bool resettable_is_in_reset(Object *obj);
+
+/**
+ * resettable_class_set_parent_phases:
+ *
+ * Save @rc current reset phases into @parent_phases and override @rc phases
+ * by the given new methods (@enter, @hold and @exit).
+ * Each phase is overridden only if the new one is not NULL allowing to
+ * override a subset of phases.
+ */
+void resettable_class_set_parent_phases(ResettableClass *rc,
+                                        ResettableEnterPhase enter,
+                                        ResettableHoldPhase hold,
+                                        ResettableExitPhase exit,
+                                        ResettablePhases *parent_phases);
+
+#endif
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/core/resettable.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Resettable interface.
+ *
+ * Copyright (c) 2019 GreenSocs SAS
+ *
+ * Authors:
+ *   Damien Hedde
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "hw/resettable.h"
+#include "trace.h"
+
+/**
+ * resettable_phase_enter/hold/exit:
+ * Function executing a phase recursively in a resettable object and its
+ * children.
+ */
+static void resettable_phase_enter(Object *obj, void *opaque, ResetType type);
+static void resettable_phase_hold(Object *obj, void *opaque, ResetType type);
+static void resettable_phase_exit(Object *obj, void *opaque, ResetType type);
+
+/**
+ * enter_phase_in_progress:
+ * True if we are currently in reset enter phase.
+ *
+ * Note: This flag is only used to guarantee (using asserts) that the reset
+ * API is used correctly. We can use a global variable because we rely on the
+ * iothread mutex to ensure only one reset operation is in a progress at a
+ * given time.
+ */
+static bool enter_phase_in_progress;
+
+void resettable_reset(Object *obj, ResetType type)
+{
+    trace_resettable_reset(obj, type);
+    resettable_assert_reset(obj, type);
+    resettable_release_reset(obj, type);
+}
+
+void resettable_assert_reset(Object *obj, ResetType type)
+{
+    /* TODO: change this assert when adding support for other reset types */
+    assert(type == RESET_TYPE_COLD);
+    trace_resettable_reset_assert_begin(obj, type);
+    assert(!enter_phase_in_progress);
+
+    enter_phase_in_progress = true;
+    resettable_phase_enter(obj, NULL, type);
+    enter_phase_in_progress = false;
+
+    resettable_phase_hold(obj, NULL, type);
+
+    trace_resettable_reset_assert_end(obj);
+}
+
+void resettable_release_reset(Object *obj, ResetType type)
+{
+    /* TODO: change this assert when adding support for other reset types */
+    assert(type == RESET_TYPE_COLD);
+    trace_resettable_reset_release_begin(obj, type);
+    assert(!enter_phase_in_progress);
+
+    resettable_phase_exit(obj, NULL, type);
+
+    trace_resettable_reset_release_end(obj);
+}
+
+bool resettable_is_in_reset(Object *obj)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+    ResettableState *s = rc->get_state(obj);
+
+    return s->count > 0;
+}
+
+/**
+ * resettable_child_foreach:
+ * helper to avoid checking the existence of the method.
+ */
+static void resettable_child_foreach(ResettableClass *rc, Object *obj,
+                                     ResettableChildCallback cb,
+                                     void *opaque, ResetType type)
+{
+    if (rc->child_foreach) {
+        rc->child_foreach(obj, cb, opaque, type);
+    }
+}
+
+/**
+ * resettable_get_tr_func:
+ * helper to fetch transitional reset callback if any.
+ */
+static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc,
+                                                   Object *obj)
+{
+    ResettableTrFunction tr_func = NULL;
+    if (rc->get_transitional_function) {
+        tr_func = rc->get_transitional_function(obj);
+    }
+    return tr_func;
+}
+
+static void resettable_phase_enter(Object *obj, void *opaque, ResetType type)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+    ResettableState *s = rc->get_state(obj);
+    const char *obj_typename = object_get_typename(obj);
+    bool action_needed = false;
+
+    /* exit phase has to finish properly before entering back in reset */
+    assert(!s->exit_phase_in_progress);
+
+    trace_resettable_phase_enter_begin(obj, obj_typename, s->count, type);
+
+    /* Only take action if we really enter reset for the 1st time. */
+    /*
+     * TODO: if adding more ResetType support, some additional checks
+     * are probably needed here.
+     */
+    if (s->count++ == 0) {
+        action_needed = true;
+    }
+    /*
+     * We limit the count to an arbitrary "big" value. The value is big
+     * enough not to be triggered normally.
+     * The assert will stop an infinite loop if there is a cycle in the
+     * reset tree. The loop goes through resettable_foreach_child below
+     * which at some point will call us again.
+     */
+    assert(s->count <= 50);
+
+    /*
+     * handle the children even if action_needed is at false so that
+     * child counts are incremented too
+     */
+    resettable_child_foreach(rc, obj, resettable_phase_enter, NULL, type);
+
+    /* execute enter phase for the object if needed */
+    if (action_needed) {
+        trace_resettable_phase_enter_exec(obj, obj_typename, type,
+                                          !!rc->phases.enter);
+        if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) {
+            rc->phases.enter(obj, type);
+        }
+        s->hold_phase_pending = true;
+    }
+    trace_resettable_phase_enter_end(obj, obj_typename, s->count);
+}
+
+static void resettable_phase_hold(Object *obj, void *opaque, ResetType type)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+    ResettableState *s = rc->get_state(obj);
+    const char *obj_typename = object_get_typename(obj);
+
+    /* exit phase has to finish properly before entering back in reset */
+    assert(!s->exit_phase_in_progress);
+
+    trace_resettable_phase_hold_begin(obj, obj_typename, s->count, type);
+
+    /* handle children first */
+    resettable_child_foreach(rc, obj, resettable_phase_hold, NULL, type);
+
+    /* exec hold phase */
+    if (s->hold_phase_pending) {
+        s->hold_phase_pending = false;
+        ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj);
+        trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold);
+        if (tr_func) {
+            trace_resettable_transitional_function(obj, obj_typename);
+            tr_func(obj);
+        } else if (rc->phases.hold) {
+            rc->phases.hold(obj);
+        }
+    }
+    trace_resettable_phase_hold_end(obj, obj_typename, s->count);
+}
+
+static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+    ResettableState *s = rc->get_state(obj);
+    const char *obj_typename = object_get_typename(obj);
+
+    assert(!s->exit_phase_in_progress);
+    trace_resettable_phase_exit_begin(obj, obj_typename, s->count, type);
+
+    /* exit_phase_in_progress ensures this phase is 'atomic' */
+    s->exit_phase_in_progress = true;
+    resettable_child_foreach(rc, obj, resettable_phase_exit, NULL, type);
+
+    assert(s->count > 0);
+    if (s->count == 1) {
+        trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit);
+        if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) {
+            rc->phases.exit(obj);
+        }
+        s->count = 0;
+    }
+    s->exit_phase_in_progress = false;
+    trace_resettable_phase_exit_end(obj, obj_typename, s->count);
+}
+
+void resettable_class_set_parent_phases(ResettableClass *rc,
+                                        ResettableEnterPhase enter,
+                                        ResettableHoldPhase hold,
+                                        ResettableExitPhase exit,
+                                        ResettablePhases *parent_phases)
+{
+    *parent_phases = rc->phases;
+    if (enter) {
+        rc->phases.enter = enter;
+    }
+    if (hold) {
+        rc->phases.hold = hold;
+    }
+    if (exit) {
+        rc->phases.exit = exit;
+    }
+}
+
+static const TypeInfo resettable_interface_info = {
+    .name       = TYPE_RESETTABLE_INTERFACE,
+    .parent     = TYPE_INTERFACE,
+    .class_size = sizeof(ResettableClass),
+};
+
+static void reset_register_types(void)
+{
+    type_register_static(&resettable_interface_info);
+}
+
+type_init(reset_register_types)
diff --git a/hw/core/trace-events b/hw/core/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -XXX,XX +XXX,XX @@ qbus_reset(void *obj, const char *objtype) "obj=%p(%s)"
 qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)"
 qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)"
 qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)"
+
+# resettable.c
+resettable_reset(void *obj, int cold) "obj=%p cold=%d"
+resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d"
+resettable_reset_assert_end(void *obj) "obj=%p"
+resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d"
+resettable_reset_release_end(void *obj) "obj=%p"
+resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
+resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d"
+resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
+resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
+resettable_phase_hold_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
+resettable_phase_hold_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
+resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
+resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d"
+resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
+resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)"
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

This commit adds support of Resettable interface to buses and devices:
+ ResettableState structure is added in the Bus/Device state
+ Resettable methods are implemented.
+ device/bus_is_in_reset function defined

This commit allows to transition the objects to the new
multi-phase interface without changing the reset behavior at all.
Object single reset method can be split into the 3 different phases
but the 3 phases are still executed in a row for a given object.
From the qdev/qbus reset api point of view, nothing is changed.
qdev_reset_all() and qbus_reset_all() are not modified as well as
device_legacy_reset().

Transition of an object must be done from parent class to child class.
Care has been taken to allow the transition of a parent class
without requiring the child classes to be transitioned at the same
time. Note that SysBus and SysBusDevice class do not need any transition
because they do not override the legacy reset method.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/Makefile.include |  1 +
 include/hw/qdev-core.h | 27 ++++++++++++
 hw/core/bus.c          | 97 ++++++++++++++++++++++++++++++++++++++++++
 hw/core/qdev.c         | 93 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 218 insertions(+)

diff --git a/tests/Makefile.include b/tests/Makefile.include
index XXXXXXX..XXXXXXX 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -XXX,XX +XXX,XX @@ tests/fp/%:
 tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
 	hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
 	hw/core/bus.o \
+	hw/core/resettable.o \
 	hw/core/irq.o \
 	hw/core/fw-path-provider.o \
 	hw/core/reset.o \
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitmap.h"
 #include "qom/object.h"
 #include "hw/hotplug.h"
+#include "hw/resettable.h"
 
 enum {
     DEV_NVECTORS_UNSPECIFIED = -1,
@@ -XXX,XX +XXX,XX @@ typedef struct DeviceClass {
     bool hotpluggable;
 
     /* callbacks */
+    /*
+     * Reset method here is deprecated and replaced by methods in the
+     * resettable class interface to implement a multi-phase reset.
+     * TODO: remove once every reset callback is unused
+     */
     DeviceReset reset;
     DeviceRealize realize;
     DeviceUnrealize unrealize;
@@ -XXX,XX +XXX,XX @@ struct NamedGPIOList {
 /**
  * DeviceState:
  * @realized: Indicates whether the device has been fully constructed.
+ * @reset: ResettableState for the device; handled by Resettable interface.
  *
  * This structure should not be accessed directly.  We declare it here
  * so that it can be embedded in individual device state structures.
@@ -XXX,XX +XXX,XX @@ struct DeviceState {
     int num_child_bus;
     int instance_id_alias;
     int alias_required_for_version;
+    ResettableState reset;
 };
 
 struct DeviceListener {
@@ -XXX,XX +XXX,XX @@ typedef struct BusChild {
 /**
  * BusState:
  * @hotplug_handler: link to a hotplug handler associated with bus.
+ * @reset: ResettableState for the bus; handled by Resettable interface.
  */
 struct BusState {
     Object obj;
@@ -XXX,XX +XXX,XX @@ struct BusState {
     int num_children;
     QTAILQ_HEAD(, BusChild) children;
     QLIST_ENTRY(BusState) sibling;
+    ResettableState reset;
 };
 
 /**
@@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque);
 void qbus_reset_all(BusState *bus);
 void qbus_reset_all_fn(void *opaque);
 
+/**
+ * device_is_in_reset:
+ * Return true if the device @dev is currently being reset.
+ */
+bool device_is_in_reset(DeviceState *dev);
+
+/**
+ * bus_is_in_reset:
+ * Return true if the bus @bus is currently being reset.
+ */
+bool bus_is_in_reset(BusState *bus);
+
 /* This should go away once we get rid of the NULL bus hack */
 BusState *sysbus_get_default(void);
 
@@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev);
 
 void device_class_set_props(DeviceClass *dc, Property *props);
 
+/**
+ * device_class_set_parent_reset:
+ * TODO: remove the function when DeviceClass's reset method
+ * is not used anymore.
+ */
 void device_class_set_parent_reset(DeviceClass *dc,
                                    DeviceReset dev_reset,
                                    DeviceReset *parent_reset);
diff --git a/hw/core/bus.c b/hw/core/bus.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/bus.c
+++ b/hw/core/bus.c
@@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus,
     return 0;
 }
 
+bool bus_is_in_reset(BusState *bus)
+{
+    return resettable_is_in_reset(OBJECT(bus));
+}
+
+static ResettableState *bus_get_reset_state(Object *obj)
+{
+    BusState *bus = BUS(obj);
+    return &bus->reset;
+}
+
+static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
+                                    void *opaque, ResetType type)
+{
+    BusState *bus = BUS(obj);
+    BusChild *kid;
+
+    QTAILQ_FOREACH(kid, &bus->children, sibling) {
+        cb(OBJECT(kid->child), opaque, type);
+    }
+}
+
 static void qbus_realize(BusState *bus, DeviceState *parent, const char *name)
 {
     const char *typename = object_get_typename(OBJECT(bus));
@@ -XXX,XX +XXX,XX @@ static char *default_bus_get_fw_dev_path(DeviceState *dev)
     return g_strdup(object_get_typename(OBJECT(dev)));
 }
 
+/**
+ * bus_phases_reset:
+ * Transition reset method for buses to allow moving
+ * smoothly from legacy reset method to multi-phases
+ */
+static void bus_phases_reset(BusState *bus)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(bus);
+
+    if (rc->phases.enter) {
+        rc->phases.enter(OBJECT(bus), RESET_TYPE_COLD);
+    }
+    if (rc->phases.hold) {
+        rc->phases.hold(OBJECT(bus));
+    }
+    if (rc->phases.exit) {
+        rc->phases.exit(OBJECT(bus));
+    }
+}
+
+static void bus_transitional_reset(Object *obj)
+{
+    BusClass *bc = BUS_GET_CLASS(obj);
+
+    /*
+     * This will call either @bus_phases_reset (for multi-phases transitioned
+     * buses) or a bus's specific method for not-yet transitioned buses.
+     * In both case, it does not reset children.
+     */
+    if (bc->reset) {
+        bc->reset(BUS(obj));
+    }
+}
+
+/**
+ * bus_get_transitional_reset:
+ * check if the bus's class is ready for multi-phase
+ */
+static ResettableTrFunction bus_get_transitional_reset(Object *obj)
+{
+    BusClass *dc = BUS_GET_CLASS(obj);
+    if (dc->reset != bus_phases_reset) {
+        /*
+         * dc->reset has been overridden by a subclass,
+         * the bus is not ready for multi phase yet.
+         */
+        return bus_transitional_reset;
+    }
+    return NULL;
+}
+
 static void bus_class_init(ObjectClass *class, void *data)
 {
     BusClass *bc = BUS_CLASS(class);
+    ResettableClass *rc = RESETTABLE_CLASS(class);
 
     class->unparent = bus_unparent;
     bc->get_fw_dev_path = default_bus_get_fw_dev_path;
+
+    rc->get_state = bus_get_reset_state;
+    rc->child_foreach = bus_reset_child_foreach;
+
+    /*
+     * @bus_phases_reset is put as the default reset method below, allowing
+     * to do the multi-phase transition from base classes to leaf classes. It
+     * allows a legacy-reset Bus class to extend a multi-phases-reset
+     * Bus class for the following reason:
+     * + If a base class B has been moved to multi-phase, then it does not
+     *   override this default reset method and may have defined phase methods.
+     * + A child class C (extending class B) which uses
+     *   bus_class_set_parent_reset() (or similar means) to override the
+     *   reset method will still work as expected. @bus_phases_reset function
+     *   will be registered as the parent reset method and effectively call
+     *   parent reset phases.
+     */
+    bc->reset = bus_phases_reset;
+    rc->get_transitional_function = bus_get_transitional_reset;
 }
 
 static void qbus_finalize(Object *obj)
@@ -XXX,XX +XXX,XX @@ static const TypeInfo bus_info = {
     .instance_init = qbus_initfn,
     .instance_finalize = qbus_finalize,
     .class_init = bus_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { TYPE_RESETTABLE_INTERFACE },
+        { }
+    },
 };
 
 static void bus_register_types(void)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque)
     qbus_reset_all(bus);
 }
 
+bool device_is_in_reset(DeviceState *dev)
+{
+    return resettable_is_in_reset(OBJECT(dev));
+}
+
+static ResettableState *device_get_reset_state(Object *obj)
+{
+    DeviceState *dev = DEVICE(obj);
+    return &dev->reset;
+}
+
+static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb,
+                                       void *opaque, ResetType type)
+{
+    DeviceState *dev = DEVICE(obj);
+    BusState *bus;
+
+    QLIST_FOREACH(bus, &dev->child_bus, sibling) {
+        cb(OBJECT(bus), opaque, type);
+    }
+}
+
 /* can be used as ->unplug() callback for the simple cases */
 void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
                                   DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ device_vmstate_if_get_id(VMStateIf *obj)
     return qdev_get_dev_path(dev);
 }
 
+/**
+ * device_phases_reset:
+ * Transition reset method for devices to allow moving
+ * smoothly from legacy reset method to multi-phases
+ */
+static void device_phases_reset(DeviceState *dev)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(dev);
+
+    if (rc->phases.enter) {
+        rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD);
+    }
+    if (rc->phases.hold) {
+        rc->phases.hold(OBJECT(dev));
+    }
+    if (rc->phases.exit) {
+        rc->phases.exit(OBJECT(dev));
+    }
+}
+
+static void device_transitional_reset(Object *obj)
+{
+    DeviceClass *dc = DEVICE_GET_CLASS(obj);
+
+    /*
+     * This will call either @device_phases_reset (for multi-phases transitioned
+     * devices) or a device's specific method for not-yet transitioned devices.
+     * In both case, it does not reset children.
+     */
+    if (dc->reset) {
+        dc->reset(DEVICE(obj));
+    }
+}
+
+/**
+ * device_get_transitional_reset:
+ * check if the device's class is ready for multi-phase
+ */
+static ResettableTrFunction device_get_transitional_reset(Object *obj)
+{
+    DeviceClass *dc = DEVICE_GET_CLASS(obj);
+    if (dc->reset != device_phases_reset) {
+        /*
+         * dc->reset has been overridden by a subclass,
+         * the device is not ready for multi phase yet.
+         */
+        return device_transitional_reset;
+    }
+    return NULL;
+}
+
 static void device_class_init(ObjectClass *class, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(class);
     VMStateIfClass *vc = VMSTATE_IF_CLASS(class);
+    ResettableClass *rc = RESETTABLE_CLASS(class);
 
     class->unparent = device_unparent;
 
@@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data)
     dc->hotpluggable = true;
     dc->user_creatable = true;
     vc->get_id = device_vmstate_if_get_id;
+    rc->get_state = device_get_reset_state;
+    rc->child_foreach = device_reset_child_foreach;
+
+    /*
+     * @device_phases_reset is put as the default reset method below, allowing
+     * to do the multi-phase transition from base classes to leaf classes. It
+     * allows a legacy-reset Device class to extend a multi-phases-reset
+     * Device class for the following reason:
+     * + If a base class B has been moved to multi-phase, then it does not
+     *   override this default reset method and may have defined phase methods.
+     * + A child class C (extending class B) which uses
+     *   device_class_set_parent_reset() (or similar means) to override the
+     *   reset method will still work as expected. @device_phases_reset function
+     *   will be registered as the parent reset method and effectively call
+     *   parent reset phases.
+     */
+    dc->reset = device_phases_reset;
+    rc->get_transitional_function = device_get_transitional_reset;
 
     object_class_property_add_bool(class, "realized",
                                    device_get_realized, device_set_realized,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo device_type_info = {
     .class_size = sizeof(DeviceClass),
     .interfaces = (InterfaceInfo[]) {
         { TYPE_VMSTATE_IF },
+        { TYPE_RESETTABLE_INTERFACE },
         { }
     }
 };
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Add a function resettable_change_parent() to do the required
plumbing when changing the parent a of Resettable object.

We need to make sure that the reset state of the object remains
coherent with the reset state of the new parent.

We make the 2 following hypothesis:
+ when an object is put in a parent under reset, the object goes in
reset.
+ when an object is removed from a parent under reset, the object
leaves reset.

The added function avoids any glitch if both old and new parent are
already in reset.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/resettable.h | 16 +++++++++++
 hw/core/resettable.c    | 62 +++++++++++++++++++++++++++++++++++++++--
 hw/core/trace-events    |  1 +
 3 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettable.h
@@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type);
  */
 bool resettable_is_in_reset(Object *obj);
 
+/**
+ * resettable_change_parent:
+ * Indicate that the parent of Ressettable @obj is changing from @oldp to @newp.
+ * All 3 objects must implement resettable interface. @oldp or @newp may be
+ * NULL.
+ *
+ * This function will adapt the reset state of @obj so that it is coherent
+ * with the reset state of @newp. It may trigger @resettable_assert_reset()
+ * or @resettable_release_reset(). It will do such things only if the reset
+ * state of @newp and @oldp are different.
+ *
+ * When using this function during reset, it must only be called during
+ * a hold phase method. Calling this during enter or exit phase is an error.
+ */
+void resettable_change_parent(Object *obj, Object *newp, Object *oldp);
+
 /**
  * resettable_class_set_parent_phases:
  *
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/resettable.c
+++ b/hw/core/resettable.c
@@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type);
  * enter_phase_in_progress:
  * True if we are currently in reset enter phase.
  *
- * Note: This flag is only used to guarantee (using asserts) that the reset
- * API is used correctly. We can use a global variable because we rely on the
+ * exit_phase_in_progress:
+ * count the number of exit phase we are in.
+ *
+ * Note: These flags are only used to guarantee (using asserts) that the reset
+ * API is used correctly. We can use global variables because we rely on the
  * iothread mutex to ensure only one reset operation is in a progress at a
  * given time.
  */
 static bool enter_phase_in_progress;
+static unsigned exit_phase_in_progress;
 
 void resettable_reset(Object *obj, ResetType type)
 {
@@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type)
     trace_resettable_reset_release_begin(obj, type);
     assert(!enter_phase_in_progress);
 
+    exit_phase_in_progress += 1;
     resettable_phase_exit(obj, NULL, type);
+    exit_phase_in_progress -= 1;
 
     trace_resettable_reset_release_end(obj);
 }
@@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
     trace_resettable_phase_exit_end(obj, obj_typename, s->count);
 }
 
+/*
+ * resettable_get_count:
+ * Get the count of the Resettable object @obj. Return 0 if @obj is NULL.
+ */
+static unsigned resettable_get_count(Object *obj)
+{
+    if (obj) {
+        ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+        return rc->get_state(obj)->count;
+    }
+    return 0;
+}
+
+void resettable_change_parent(Object *obj, Object *newp, Object *oldp)
+{
+    ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
+    ResettableState *s = rc->get_state(obj);
+    unsigned newp_count = resettable_get_count(newp);
+    unsigned oldp_count = resettable_get_count(oldp);
+
+    /*
+     * Ensure we do not change parent when in enter or exit phase.
+     * During these phases, the reset subtree being updated is partly in reset
+     * and partly not in reset (it depends on the actual position in
+     * resettable_child_foreach()s). We are not able to tell in which part is a
+     * leaving or arriving device. Thus we cannot set the reset count of the
+     * moving device to the proper value.
+     */
+    assert(!enter_phase_in_progress && !exit_phase_in_progress);
+    trace_resettable_change_parent(obj, oldp, oldp_count, newp, newp_count);
+
+    /*
+     * At most one of the two 'for' loops will be executed below
+     * in order to cope with the difference between the two counts.
+     */
+    /* if newp is more reset than oldp */
+    for (unsigned i = oldp_count; i < newp_count; i++) {
+        resettable_assert_reset(obj, RESET_TYPE_COLD);
+    }
+    /*
+     * if obj is leaving a bus under reset, we need to ensure
+     * hold phase is not pending.
+     */
+    if (oldp_count && s->hold_phase_pending) {
+        resettable_phase_hold(obj, NULL, RESET_TYPE_COLD);
+    }
+    /* if oldp is more reset than newp */
+    for (unsigned i = newp_count; i < oldp_count; i++) {
+        resettable_release_reset(obj, RESET_TYPE_COLD);
+    }
+}
+
 void resettable_class_set_parent_phases(ResettableClass *rc,
                                         ResettableEnterPhase enter,
                                         ResettableHoldPhase hold,
diff --git a/hw/core/trace-events b/hw/core/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/trace-events
+++ b/hw/core/trace-events
@@ -XXX,XX +XXX,XX @@ resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d"
 resettable_reset_assert_end(void *obj) "obj=%p"
 resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d"
 resettable_reset_release_end(void *obj) "obj=%p"
+resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc) "obj=%p from=%p(%d) to=%p(%d)"
 resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d"
 resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d"
 resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d"
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

In qdev_set_parent_bus(), when changing the parent bus of a
realized device, if the source and destination buses are not in the
same reset state, some adaptations are required. This patch adds
needed call to resettable_change_parent() to make sure a device reset
state stays coherent with its parent bus.

The addition is a no-op if:
1. the device being parented is not realized.
2. the device is realized, but both buses are not under reset.

Case 2 means that as long as qdev_set_parent_bus() is called
during the machine realization procedure (which is before the
machine reset so nothing is in reset), it is a no op.

There are 52 call sites of qdev_set_parent_bus(). All but one fall
into the no-op case:
+ 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/
  {vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device
  parent bus just before realizing the same vdev(vgpu).
+ hw/core/qdev.c: when creating a device in qdev_try_create()
+ hw/core/sysbus.c: when initializing a device in the sysbus
+ hw/i386/amd_iommu.c: before realizing AMDVIState/pci
+ hw/isa/piix4.c: before realizing PIIX4State/rtc
+ hw/misc/auxbus.c: when creating an AUXBus
+ hw/misc/auxbus.c: when creating an AUXBus child
+ hw/misc/macio/macio.c: when initializing a MACIOState child
+ hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu
+ hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda
+ hw/net/virtio-net.c: Used for migration when using the failover
                       mechanism to migration a vfio-pci/net. It is
                       a no-op because at this point the device is
                       already on the bus.
+ hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root
+ hw/pci-host/gpex.c: before realizing GPEXHost/root
+ hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev
+ hw/pci-host/q35.c: before realizing Q35PCIHost/mch
+ hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev
+ hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root
+ hw/s390x/event-facility.c: when creating SCLPEventFacility/
                             TYPE_SCLP_QUIESCE
+ hw/s390x/event-facility.c: ditto with SCLPEventFacility/
                             TYPE_SCLP_CPU_HOTPLUG
+ hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice
  just after realizing it. Ok because at this point the destination
  bus (sysbus) is not in reset; the realize step is before the
  machine reset.
+ hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below.
+ hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs
  line in ssi_auto_connect_slave(). Ok because this function is only
  used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c,
  hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c.
+ hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device
+ qdev-monitor.c: in device hotplug creation procedure before realize

Note that this commit alone will have no effect, right now there is no
use of resettable API to reset anything. So a bus will never be tagged
as in-reset by this same API.

The one place where side-effect will occurs is in hw/sd/core.c in
sdbus_reparent_card(). This function is only used in the raspi machines,
including during the sysbus reset procedure. This case will be
carrefully handled when doing the multiple phase reset transition.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/core/qdev.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
 
 void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
 {
-    bool replugging = dev->parent_bus != NULL;
+    BusState *old_parent_bus = dev->parent_bus;
 
-    if (replugging) {
+    if (old_parent_bus) {
         trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)),
-            dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)),
+            old_parent_bus, object_get_typename(OBJECT(old_parent_bus)),
             OBJECT(bus), object_get_typename(OBJECT(bus)));
         /*
          * Keep a reference to the device while it's not plugged into
          * any bus, to avoid it potentially evaporating when it is
          * dereffed in bus_remove_child().
+         * Also keep the ref of the parent bus until the end, so that
+         * we can safely call resettable_change_parent() below.
          */
         object_ref(OBJECT(dev));
         bus_remove_child(dev->parent_bus, dev);
-        object_unref(OBJECT(dev->parent_bus));
     }
     dev->parent_bus = bus;
     object_ref(OBJECT(bus));
     bus_add_child(bus, dev);
-    if (replugging) {
+    if (dev->realized) {
+        resettable_change_parent(OBJECT(dev), OBJECT(bus),
+                                 OBJECT(old_parent_bus));
+    }
+    if (old_parent_bus) {
+        object_unref(OBJECT(old_parent_bus));
         object_unref(OBJECT(dev));
     }
 }
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

This commit make use of the resettable API to reset the device being
hotplugged when it is realized. Also it ensures it is put in a reset
state coherent with the parent it is plugged into.

Note that there is a difference in the reset. Instead of resetting
only the hotplugged device, we reset also its subtree (switch to
resettable API). This is not expected to be a problem because
sub-buses are just realized too. If a hotplugged device has any
sub-buses it is logical to reset them too at this point.

The recently added should_be_hidden and PCI's partially_hotplugged
mechanisms do not interfere with realize operation:
+ In the should_be_hidden use case, device creation is
delayed.
+ The partially_hotplugged mechanism prevents a device to be
unplugged and unrealized from qdev POV and unrealized.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/resettable.h | 11 +++++++++++
 hw/core/qdev.c          | 15 ++++++++++++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettable.h
@@ -XXX,XX +XXX,XX @@ struct ResettableState {
     bool exit_phase_in_progress;
 };
 
+/**
+ * resettable_state_clear:
+ * Clear the state. It puts the state to the initial (zeroed) state required
+ * to reuse an object. Typically used in realize step of base classes
+ * implementing the interface.
+ */
+static inline void resettable_state_clear(ResettableState *state)
+{
+    memset(state, 0, sizeof(ResettableState));
+}
+
 /**
  * resettable_reset:
  * Trigger a reset on an object @obj of type @type. @obj must implement
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
             }
         }
 
+        /*
+         * Clear the reset state, in case the object was previously unrealized
+         * with a dirty state.
+         */
+        resettable_state_clear(&dev->reset);
+
         QLIST_FOREACH(bus, &dev->child_bus, sibling) {
             object_property_set_bool(OBJECT(bus), true, "realized",
                                          &local_err);
@@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp)
             }
         }
         if (dev->hotplugged) {
-            device_legacy_reset(dev);
+            /*
+             * Reset the device, as well as its subtree which, at this point,
+             * should be realized too.
+             */
+            resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD);
+            resettable_change_parent(OBJECT(dev), OBJECT(dev->parent_bus),
+                                     NULL);
+            resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD);
         }
         dev->pending_deleted_event = false;
 
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Deprecate device_legacy_reset(), qdev_reset_all() and
qbus_reset_all() to be replaced by new functions
device_cold_reset() and bus_cold_reset() which uses resettable API.

Also introduce resettable_cold_reset_fn() which may be used as a
replacement for qdev_reset_all_fn and qbus_reset_all_fn().

Following patches will be needed to look at legacy reset call sites
and switch to resettable api. The legacy functions will be removed
when unused.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/qdev-core.h  | 27 +++++++++++++++++++++++++++
 include/hw/resettable.h |  9 +++++++++
 hw/core/bus.c           |  5 +++++
 hw/core/qdev.c          |  5 +++++
 hw/core/resettable.c    |  5 +++++
 5 files changed, 51 insertions(+)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -XXX,XX +XXX,XX @@ int qdev_walk_children(DeviceState *dev,
                        qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
                        void *opaque);
 
+/**
+ * @qdev_reset_all:
+ * Reset @dev. See @qbus_reset_all() for more details.
+ *
+ * Note: This function is deprecated and will be removed when it becomes unused.
+ * Please use device_cold_reset() now.
+ */
 void qdev_reset_all(DeviceState *dev);
 void qdev_reset_all_fn(void *opaque);
 
@@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque);
  * hard reset means that qbus_reset_all will reset all state of the device.
  * For PCI devices, for example, this will include the base address registers
  * or configuration space.
+ *
+ * Note: This function is deprecated and will be removed when it becomes unused.
+ * Please use bus_cold_reset() now.
  */
 void qbus_reset_all(BusState *bus);
 void qbus_reset_all_fn(void *opaque);
 
+/**
+ * device_cold_reset:
+ * Reset device @dev and perform a recursive processing using the resettable
+ * interface. It triggers a RESET_TYPE_COLD.
+ */
+void device_cold_reset(DeviceState *dev);
+
+/**
+ * bus_cold_reset:
+ *
+ * Reset bus @bus and perform a recursive processing using the resettable
+ * interface. It triggers a RESET_TYPE_COLD.
+ */
+void bus_cold_reset(BusState *bus);
+
 /**
  * device_is_in_reset:
  * Return true if the device @dev is currently being reset.
@@ -XXX,XX +XXX,XX @@ void qdev_machine_init(void);
  * device_legacy_reset:
  *
  * Reset a single device (by calling the reset method).
+ * Note: This function is deprecated and will be removed when it becomes unused.
+ * Please use device_cold_reset() now.
  */
 void device_legacy_reset(DeviceState *dev);
 
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettable.h
@@ -XXX,XX +XXX,XX @@ bool resettable_is_in_reset(Object *obj);
  */
 void resettable_change_parent(Object *obj, Object *newp, Object *oldp);
 
+/**
+ * resettable_cold_reset_fn:
+ * Helper to call resettable_reset((Object *) opaque, RESET_TYPE_COLD).
+ *
+ * This function is typically useful to register a reset handler with
+ * qemu_register_reset.
+ */
+void resettable_cold_reset_fn(void *opaque);
+
 /**
  * resettable_class_set_parent_phases:
  *
diff --git a/hw/core/bus.c b/hw/core/bus.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/bus.c
+++ b/hw/core/bus.c
@@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus,
     return 0;
 }
 
+void bus_cold_reset(BusState *bus)
+{
+    resettable_reset(OBJECT(bus), RESET_TYPE_COLD);
+}
+
 bool bus_is_in_reset(BusState *bus)
 {
     return resettable_is_in_reset(OBJECT(bus));
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque)
     qbus_reset_all(bus);
 }
 
+void device_cold_reset(DeviceState *dev)
+{
+    resettable_reset(OBJECT(dev), RESET_TYPE_COLD);
+}
+
 bool device_is_in_reset(DeviceState *dev)
 {
     return resettable_is_in_reset(OBJECT(dev));
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/resettable.c
+++ b/hw/core/resettable.c
@@ -XXX,XX +XXX,XX @@ void resettable_change_parent(Object *obj, Object *newp, Object *oldp)
     }
 }
 
+void resettable_cold_reset_fn(void *opaque)
+{
+    resettable_reset((Object *) opaque, RESET_TYPE_COLD);
+}
+
 void resettable_class_set_parent_phases(ResettableClass *rc,
                                         ResettableEnterPhase enter,
                                         ResettableHoldPhase hold,
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200123132823.1117486-10-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/devel/index.rst |   1 +
 docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 290 insertions(+)
 create mode 100644 docs/devel/reset.rst

diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/devel/index.rst
+++ b/docs/devel/index.rst
@@ -XXX,XX +XXX,XX @@ Contents:
    tcg
    tcg-plugins
    bitops
+   reset
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/devel/reset.rst
@@ -XXX,XX +XXX,XX @@
+
+=======================================
+Reset in QEMU: the Resettable interface
+=======================================
+
+The reset of qemu objects is handled using the resettable interface declared
+in ``include/hw/resettable.h``.
+
+This interface allows objects to be grouped (on a tree basis); so that the
+whole group can be reset consistently. Each individual member object does not
+have to care about others; in particular, problems of order (which object is
+reset first) are addressed.
+
+As of now DeviceClass and BusClass implement this interface.
+
+
+Triggering reset
+----------------
+
+This section documents the APIs which "users" of a resettable object should use
+to control it. All resettable control functions must be called while holding
+the iothread lock.
+
+You can apply a reset to an object using ``resettable_assert_reset()``. You need
+to call ``resettable_release_reset()`` to release the object from reset. To
+instantly reset an object, without keeping it in reset state, just call
+``resettable_reset()``. These functions take two parameters: a pointer to the
+object to reset and a reset type.
+
+Several types of reset will be supported. For now only cold reset is defined;
+others may be added later. The Resettable interface handles reset types with an
+enum:
+
+``RESET_TYPE_COLD``
+  Cold reset is supported by every resettable object. In QEMU, it means we reset
+  to the initial state corresponding to the start of QEMU; this might differ
+  from what is a real hardware cold reset. It differs from other resets (like
+  warm or bus resets) which may keep certain parts untouched.
+
+Calling ``resettable_reset()`` is equivalent to calling
+``resettable_assert_reset()`` then ``resettable_release_reset()``. It is
+possible to interleave multiple calls to these three functions. There may
+be several reset sources/controllers of a given object. The interface handles
+everything and the different reset controllers do not need to know anything
+about each others. The object will leave reset state only when each other
+controllers end their reset operation. This point is handled internally by
+maintaining a count of in-progress resets; it is crucial to call
+``resettable_release_reset()`` one time and only one time per
+``resettable_assert_reset()`` call.
+
+For now migration of a device or bus in reset is not supported. Care must be
+taken not to delay ``resettable_release_reset()`` after its
+``resettable_assert_reset()`` counterpart.
+
+Note that, since resettable is an interface, the API takes a simple Object as
+parameter. Still, it is a programming error to call a resettable function on a
+non-resettable object and it will trigger a run time assert error. Since most
+calls to resettable interface are done through base class functions, such an
+error is not likely to happen.
+
+For Devices and Buses, the following helper functions exist:
+
+- ``device_cold_reset()``
+- ``bus_cold_reset()``
+
+These are simple wrappers around resettable_reset() function; they only cast the
+Device or Bus into an Object and pass the cold reset type. When possible
+prefer to use these functions instead of ``resettable_reset()``.
+
+Device and bus functions co-exist because there can be semantic differences
+between resetting a bus and resetting the controller bridge which owns it.
+For example, consider a SCSI controller. Resetting the controller puts all
+its registers back to what reset state was as well as reset everything on the
+SCSI bus, whereas resetting just the SCSI bus only resets everything that's on
+it but not the controller.
+
+
+Multi-phase mechanism
+---------------------
+
+This section documents the internals of the resettable interface.
+
+The resettable interface uses a multi-phase system to relieve objects and
+machines from reset ordering problems. To address this, the reset operation
+of an object is split into three well defined phases.
+
+When resetting several objects (for example the whole machine at simulation
+startup), all first phases of all objects are executed, then all second phases
+and then all third phases.
+
+The three phases are:
+
+1. The **enter** phase is executed when the object enters reset. It resets only
+   local state of the object; it must not do anything that has a side-effect
+   on other objects, such as raising or lowering a qemu_irq line or reading or
+   writing guest memory.
+
+2. The **hold** phase is executed for entry into reset, once every object in the
+   group which is being reset has had its *enter* phase executed. At this point
+   devices can do actions that affect other objects.
+
+3. The **exit** phase is executed when the object leaves the reset state.
+   Actions affecting other objects are permitted.
+
+As said in previous section, the interface maintains a count of reset. This
+count is used to ensure phases are executed only when required. *enter* and
+*hold* phases are executed only when asserting reset for the first time
+(if an object is already in reset state when calling
+``resettable_assert_reset()`` or ``resettable_reset()``, they are not
+executed).
+The *exit* phase is executed only when the last reset operation ends. Therefore
+the object does not need to care how many of reset controllers it has and how
+many of them have started a reset.
+
+
+Handling reset in a resettable object
+-------------------------------------
+
+This section documents the APIs that an implementation of a resettable object
+must provide and what functions it has access to. It is intended for people
+who want to implement or convert a class which has the resettable interface;
+for example when specializing an existing device or bus.
+
+Methods to implement
+....................
+
+Three methods should be defined or left empty. Each method corresponds to a
+phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
+``phases.exit()``. They all take the object as parameter. The *enter* method
+also take the reset type as second parameter.
+
+When extending an existing class, these methods may need to be extended too.
+The ``resettable_class_set_parent_phases()`` class function may be used to
+backup parent class methods.
+
+Here follows an example to implement reset for a Device which sets an IO while
+in reset.
+
+::
+
+    static void mydev_reset_enter(Object *obj, ResetType type)
+    {
+        MyDevClass *myclass = MYDEV_GET_CLASS(obj);
+        MyDevState *mydev = MYDEV(obj);
+        /* call parent class enter phase */
+        if (myclass->parent_phases.enter) {
+            myclass->parent_phases.enter(obj, type);
+        }
+        /* initialize local state only */
+        mydev->var = 0;
+    }
+
+    static void mydev_reset_hold(Object *obj)
+    {
+        MyDevClass *myclass = MYDEV_GET_CLASS(obj);
+        MyDevState *mydev = MYDEV(obj);
+        /* call parent class hold phase */
+        if (myclass->parent_phases.hold) {
+            myclass->parent_phases.hold(obj);
+        }
+        /* set an IO */
+        qemu_set_irq(mydev->irq, 1);
+    }
+
+    static void mydev_reset_exit(Object *obj)
+    {
+        MyDevClass *myclass = MYDEV_GET_CLASS(obj);
+        MyDevState *mydev = MYDEV(obj);
+        /* call parent class exit phase */
+        if (myclass->parent_phases.exit) {
+            myclass->parent_phases.exit(obj);
+        }
+        /* clear an IO */
+        qemu_set_irq(mydev->irq, 0);
+    }
+
+    typedef struct MyDevClass {
+        MyParentClass parent_class;
+        /* to store eventual parent reset methods */
+        ResettablePhases parent_phases;
+    } MyDevClass;
+
+    static void mydev_class_init(ObjectClass *class, void *data)
+    {
+        MyDevClass *myclass = MYDEV_CLASS(class);
+        ResettableClass *rc = RESETTABLE_CLASS(class);
+        resettable_class_set_parent_reset_phases(rc,
+                                                 mydev_reset_enter,
+                                                 mydev_reset_hold,
+                                                 mydev_reset_exit,
+                                                 &myclass->parent_phases);
+    }
+
+In the above example, we override all three phases. It is possible to override
+only some of them by passing NULL instead of a function pointer to
+``resettable_class_set_parent_reset_phases()``. For example, the following will
+only override the *enter* phase and leave *hold* and *exit* untouched::
+
+    resettable_class_set_parent_reset_phases(rc, mydev_reset_enter,
+                                             NULL, NULL,
+                                             &myclass->parent_phases);
+
+This is equivalent to providing a trivial implementation of the hold and exit
+phases which does nothing but call the parent class's implementation of the
+phase.
+
+Polling the reset state
+.......................
+
+Resettable interface provides the ``resettable_is_in_reset()`` function.
+This function returns true if the object parameter is currently under reset.
+
+An object is under reset from the beginning of the *init* phase to the end of
+the *exit* phase. During all three phases, the function will return that the
+object is in reset.
+
+This function may be used if the object behavior has to be adapted
+while in reset state. For example if a device has an irq input,
+it will probably need to ignore it while in reset; then it can for
+example check the reset state at the beginning of the irq callback.
+
+Note that until migration of the reset state is supported, an object
+should not be left in reset. So apart from being currently executing
+one of the reset phases, the only cases when this function will return
+true is if an external interaction (like changing an io) is made during
+*hold* or *exit* phase of another object in the same reset group.
+
+Helpers ``device_is_in_reset()`` and ``bus_is_in_reset()`` are also provided
+for devices and buses and should be preferred.
+
+
+Base class handling of reset
+----------------------------
+
+This section documents parts of the reset mechanism that you only need to know
+about if you are extending it to work with a new base class other than
+DeviceClass or BusClass, or maintaining the existing code in those classes. Most
+people can ignore it.
+
+Methods to implement
+....................
+
+There are two other methods that need to exist in a class implementing the
+interface: ``get_state()`` and ``child_foreach()``.
+
+``get_state()`` is simple. *resettable* is an interface and, as a consequence,
+does not have any class state structure. But in order to factorize the code, we
+need one. This method must return a pointer to ``ResettableState`` structure.
+The structure must be allocated by the base class; preferably it should be
+located inside the object instance structure.
+
+``child_foreach()`` is more complex. It should execute the given callback on
+every reset child of the given resettable object. All children must be
+resettable too. Additional parameters (a reset type and an opaque pointer) must
+be passed to the callback too.
+
+In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located
+``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented
+to follow the bus hierarchy; for a bus, it calls the function on every child
+device; for a device, it calls the function on every bus child. When we reset
+the main system bus, we reset the whole machine bus tree.
+
+Changing a resettable parent
+............................
+
+One thing which should be taken care of by the base class is handling reset
+hierarchy changes.
+
+The reset hierarchy is supposed to be static and built during machine creation.
+But there are actually some exceptions. To cope with this, the resettable API
+provides ``resettable_change_parent()``. This function allows to set, update or
+remove the parent of a resettable object after machine creation is done. As
+parameters, it takes the object being moved, the old parent if any and the new
+parent if any.
+
+This function can be used at any time when not in a reset operation. During
+a reset operation it must be used only in *hold* phase. Using it in *enter* or
+*exit* phase is an error.
+Also it should not be used during machine creation, although it is harmless to
+do so: the function is a no-op as long as old and new parent are NULL or not
+in reset.
+
+There is currently 2 cases where this function is used:
+
+1. *device hotplug*; it means a new device is introduced on a live bus.
+
+2. *hot bus change*; it means an existing live device is added, moved or
+   removed in the bus hierarchy. At the moment, it occurs only in the raspi
+   machines for changing the sdbus used by sd card.
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Replace deprecated qbus_reset_all by resettable_cold_reset_fn for
the sysbus reset registration.

Apart for the raspi machines, this does not impact the behavior
because:
+ at this point resettable just calls the old reset methods of devices
  and buses in the same order as qdev/qbus.
+ resettable handlers registered with qemu_register_reset are
  serialized; there is no interleaving.
+ eventual explicit calls to legacy reset API (device_reset or
  qdev/qbus_reset) inside this reset handler will not be masked out
  by resettable mechanism; they do not go through resettable api.

For the raspi machines, during the sysbus reset the sd-card is not
reset twice anymore but only once. This is a consequence of switching
both sysbus reset and changing parent to resettable; it detects the
second reset is not needed. This has no impact on the state after
reset; the sd-card reset method only reset local state and query
information from the block backend.

The raspi reset change can be observed by using the following command
(reset will occurs, then do Ctrl-C to end qemu; no firmware is
given here).
qemu-system-aarch64 -M raspi3 \
    -trace resettable_phase_hold_exec \
    -trace qdev_update_parent_bus \
    -trace resettable_change_parent \
    -trace qdev_reset -trace qbus_reset

Before the patch, the qdev/qbus_reset traces show when reset method are
called. After the patch, the resettable_phase_hold_exec show when reset
method are called.

The traced reset order of the raspi3 is listed below. I've added empty
lines and the tree structure.

+->bcm2835-peripherals reset
 |
 |       +->sd-card reset
 |   +->sd-bus reset
 +->bcm2835_gpio reset
 |      -> dev_update_parent_bus (move the sd-card on the sdhci-bus)
 |      -> resettable_change_parent
 |
 +->bcm2835-dma reset
 |
 |   +->bcm2835-sdhost-bus reset
 +->bcm2835-sdhost reset
 |
 |       +->sd-card (reset ONLY BEFORE BEFORE THE PATCH)
 |   +->sdhci-bus reset
 +->generic-sdhci reset
 |
 +->bcm2835-rng reset
 +->bcm2835-property reset
 +->bcm2835-fb reset
 +->bcm2835-mbox reset
 +->bcm2835-aux reset
 +->pl011 reset
 +->bcm2835-ic reset
 +->bcm2836-control reset
System reset

In both case, the sd-card is reset (being on bcm2835_gpio/sd-bus) then moved
to generic-sdhci/sdhci-bus by the bcm2835_gpio reset method.

Before the patch, it is then reset again being part of generic-sdhci/sdhci-bus.
After the patch, it considered again for reset but its reset method is not
called because it is already flagged as reset.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200123132823.1117486-11-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 vl.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/vl.c b/vl.c
index XXXXXXX..XXXXXXX 100644
--- a/vl.c
+++ b/vl.c
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
 
     /* TODO: once all bus devices are qdevified, this should be done
      * when bus is created by qdev.c */
-    qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
+    /*
+     * TODO: If we had a main 'reset container' that the whole system
+     * lived in, we could reset that using the multi-phase reset
+     * APIs. For the moment, we just reset the sysbus, which will cause
+     * all devices hanging off it (and all their child buses, recursively)
+     * to be reset. Note that this will *not* reset any Device objects
+     * which are not attached to some part of the qbus tree!
+     */
+    qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
     qemu_run_machine_init_done_notifiers();
 
     if (rom_check_and_register_reset() != 0) {
-- 
2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Replace deprecated qdev_reset_all by resettable_cold_reset_fn for
the ipl registration in the main reset handlers.

This does not impact the behavior for the following reasons:
+ at this point resettable just call the old reset methods of devices
  and buses in the same order than qdev/qbus.
+ resettable handlers registered with qemu_register_reset are
  serialized; there is no interleaving.
+ eventual explicit calls to legacy reset API (device_reset or
  qdev/qbus_reset) inside this reset handler will not be masked out
  by resettable mechanism; they do not go through resettable api.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/s390x/ipl.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -XXX,XX +XXX,XX @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
      */
     ipl->compat_start_addr = ipl->start_addr;
     ipl->compat_bios_start_addr = ipl->bios_start_addr;
-    qemu_register_reset(qdev_reset_all_fn, dev);
+    /*
+     * Because this Device is not on any bus in the qbus tree (it is
+     * not a sysbus device and it's not on some other bus like a PCI
+     * bus) it will not be automatically reset by the 'reset the
+     * sysbus' hook registered by vl.c like most devices. So we must
+     * manually register a reset hook for it.
+     * TODO: there should be a better way to do this.
+     */
+    qemu_register_reset(resettable_cold_reset_fn, dev);
 error:
     error_propagate(errp, err);
 }
-- 
2.20.1

From: Zenghui Yu <yuzenghui@huawei.com>

If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when
restoring GICR_CTLR.  Setting PTZ here makes littlt sense in "reduce GIC
initialization time".

And what's worse, PTZ is generally programmed by guest to indicate to the
Redistributor whether the LPI Pending table is zero when enabling LPIs.
If migration is triggered when the PTZ has just been cleared by guest (and
before enabling LPIs), we will see PTZ==1 on the destination side, which
is not as expected.  Let's just drop this hackish userspace behavior.

Also take this chance to refine the comment a bit.

Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20200119133051.642-1-yuzenghui@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_kvm.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s)
     kvm_gicd_access(s, GICD_CTLR, &reg, true);
 
     if (redist_typer & GICR_TYPER_PLPIS) {
-        /* Set base addresses before LPIs are enabled by GICR_CTLR write */
+        /*
+         * Restore base addresses before LPIs are potentially enabled by
+         * GICR_CTLR write
+         */
         for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
             GICv3CPUState *c = &s->cpu[ncpu];
 
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s)
             kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
 
             reg64 = c->gicr_pendbaser;
-            if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
-                /* Setting PTZ is advised if LPIs are disabled, to reduce
-                 * GIC initialization time.
-                 */
-                reg64 |= GICR_PENDBASER_PTZ;
-            }
             regl = (uint32_t)reg64;
             kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
             regh = (uint32_t)(reg64 >> 32);
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-2-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h | 46 ++++++++++++++++++++++++++------------------
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@
 int kvm_arm_vcpu_init(CPUState *cs);
 
 /**
- * kvm_arm_vcpu_finalize
+ * kvm_arm_vcpu_finalize:
  * @cs: CPUState
- * @feature: int
+ * @feature: feature to finalize
  *
  * Finalizes the configuration of the specified VCPU feature by
  * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
@@ -XXX,XX +XXX,XX @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
 int kvm_arm_init_cpreg_list(ARMCPU *cpu);
 
 /**
- * kvm_arm_reg_syncs_via_cpreg_list
- * regidx: KVM register index
+ * kvm_arm_reg_syncs_via_cpreg_list:
+ * @regidx: KVM register index
  *
  * Return true if this KVM register should be synchronized via the
  * cpreg list of arbitrary system registers, false if it is synchronized
@@ -XXX,XX +XXX,XX @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu);
 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx);
 
 /**
- * kvm_arm_cpreg_level
- * regidx: KVM register index
+ * kvm_arm_cpreg_level:
+ * @regidx: KVM register index
  *
  * Return the level of this coprocessor/system register.  Return value is
  * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE.
@@ -XXX,XX +XXX,XX @@ void kvm_arm_init_serror_injection(CPUState *cs);
  * @cpu: ARMCPU
  *
  * Get VCPU related state from kvm.
+ *
+ * Returns: 0 if success else < 0 error code
  */
 int kvm_get_vcpu_events(ARMCPU *cpu);
 
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu);
  * @cpu: ARMCPU
  *
  * Put VCPU related state to kvm.
+ *
+ * Returns: 0 if success else < 0 error code
  */
 int kvm_put_vcpu_events(ARMCPU *cpu);
 
@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
 
 /**
  * kvm_arm_get_host_cpu_features:
- * @ahcc: ARMHostCPUClass to fill in
+ * @ahcf: ARMHostCPUClass to fill in
  *
  * Probe the capabilities of the host kernel's preferred CPU and fill
  * in the ARMHostCPUClass struct accordingly.
+ *
+ * Returns true on success and false otherwise.
  */
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
 
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
 bool kvm_arm_aarch32_supported(CPUState *cs);
 
 /**
- * bool kvm_arm_pmu_supported:
+ * kvm_arm_pmu_supported:
  * @cs: CPUState
  *
  * Returns: true if the KVM VCPU can enable its PMU
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
 bool kvm_arm_pmu_supported(CPUState *cs);
 
 /**
- * bool kvm_arm_sve_supported:
+ * kvm_arm_sve_supported:
  * @cs: CPUState
  *
  * Returns true if the KVM VCPU can enable SVE and false otherwise.
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_pmu_supported(CPUState *cs);
 bool kvm_arm_sve_supported(CPUState *cs);
 
 /**
- * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
- * IPA address space supported by KVM
- *
+ * kvm_arm_get_max_vm_ipa_size:
  * @ms: Machine state handle
+ *
+ * Returns the number of bits in the IPA address space supported by KVM
  */
 int kvm_arm_get_max_vm_ipa_size(MachineState *ms);
 
 /**
- * kvm_arm_sync_mpstate_to_kvm
+ * kvm_arm_sync_mpstate_to_kvm:
  * @cpu: ARMCPU
  *
  * If supported set the KVM MP_STATE based on QEMU's model.
+ *
+ * Returns 0 on success and -1 on failure.
  */
 int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu);
 
 /**
- * kvm_arm_sync_mpstate_to_qemu
+ * kvm_arm_sync_mpstate_to_qemu:
  * @cpu: ARMCPU
  *
  * If supported get the MP_STATE from KVM and store in QEMU's model.
+ *
+ * Returns 0 on success and aborts on failure.
  */
 int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
 
@@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
 
 static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
 {
-    /* This should never actually be called in the "not KVM" case,
+    /*
+     * This should never actually be called in the "not KVM" case,
      * but set up the fields to indicate an error anyway.
      */
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit);
  *
  * Return: TRUE if any hardware breakpoints in use.
  */
-
 bool kvm_arm_hw_debug_active(CPUState *cs);
 
 /**
  * kvm_arm_copy_hw_debug_data:
- *
  * @ptr: kvm_guest_debug_arch structure
  *
  * Copy the architecture specific debug registers into the
  * kvm_guest_debug ioctl structure.
  */
 struct kvm_guest_debug_arch;
-
 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
 
 /**
- * its_class_name
+ * its_class_name:
  *
  * Return the ITS class name to use depending on whether KVM acceleration
  * and KVM CAP_SIGNAL_MSI are supported
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Add the missing GENERIC_TIMER feature to kvm64 cpus.

We don't currently use these registers when KVM is enabled, but it's
probably best we add the feature flag for consistency and potential
future use. There's also precedent, as we add the PMU feature flag to
KVM enabled guests, even though we don't use those registers either.

This change was originally posted as a hunk of a different, never
merged patch from Bijan Mottahedeh.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200120101023.16030-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     set_feature(&features, ARM_FEATURE_NEON);
     set_feature(&features, ARM_FEATURE_AARCH64);
     set_feature(&features, ARM_FEATURE_PMU);
+    set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 
     ahcf->features = features;
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

If we know what the default value should be then we can test for
that as well as the feature existence.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200120101023.16030-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/arm-cpu-features.c | 37 +++++++++++++++++++++++++---------
 1 file changed, 28 insertions(+), 9 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature)
     qobject_unref(_resp);                                              \
 })
 
+#define assert_feature(qts, cpu_type, feature, expected_value)         \
+({                                                                     \
+    QDict *_resp, *_props;                                             \
+                                                                       \
+    _resp = do_query_no_props(qts, cpu_type);                          \
+    g_assert(_resp);                                                   \
+    g_assert(resp_has_props(_resp));                                   \
+    _props = resp_get_props(_resp);                                    \
+    g_assert(qdict_get(_props, feature));                              \
+    g_assert(qdict_get_bool(_props, feature) == (expected_value));     \
+    qobject_unref(_resp);                                              \
+})
+
+#define assert_has_feature_enabled(qts, cpu_type, feature)             \
+    assert_feature(qts, cpu_type, feature, true)
+
+#define assert_has_feature_disabled(qts, cpu_type, feature)            \
+    assert_feature(qts, cpu_type, feature, false)
+
 static void assert_type_full(QTestState *qts)
 {
     const char *error;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
     assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
 
     /* Test expected feature presence/absence for some cpu types */
-    assert_has_feature(qts, "max", "pmu");
-    assert_has_feature(qts, "cortex-a15", "pmu");
+    assert_has_feature_enabled(qts, "max", "pmu");
+    assert_has_feature_enabled(qts, "cortex-a15", "pmu");
     assert_has_not_feature(qts, "cortex-a15", "aarch64");
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
-        assert_has_feature(qts, "max", "aarch64");
-        assert_has_feature(qts, "max", "sve");
-        assert_has_feature(qts, "max", "sve128");
-        assert_has_feature(qts, "cortex-a57", "pmu");
-        assert_has_feature(qts, "cortex-a57", "aarch64");
+        assert_has_feature_enabled(qts, "max", "aarch64");
+        assert_has_feature_enabled(qts, "max", "sve");
+        assert_has_feature_enabled(qts, "max", "sve128");
+        assert_has_feature_enabled(qts, "cortex-a57", "pmu");
+        assert_has_feature_enabled(qts, "cortex-a57", "aarch64");
 
         sve_tests_default(qts, "max");
 
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         QDict *resp;
         char *error;
 
-        assert_has_feature(qts, "host", "aarch64");
-        assert_has_feature(qts, "host", "pmu");
+        assert_has_feature_enabled(qts, "host", "aarch64");
+        assert_has_feature_enabled(qts, "host", "pmu");
 
         assert_error(qts, "cortex-a15",
             "We cannot guarantee the CPU type 'cortex-a15' works "
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

When a VM is stopped (such as when it's paused) guest virtual time
should stop counting. Otherwise, when the VM is resumed it will
experience time jumps and its kernel may report soft lockups. Not
counting virtual time while the VM is stopped has the side effect
of making the guest's time appear to lag when compared with real
time, and even with time derived from the physical counter. For
this reason, this change, which is enabled by default, comes with
a KVM CPU feature allowing it to be disabled, restoring legacy
behavior.

This patch only provides the implementation of the virtual time
adjustment. A subsequent patch will provide the CPU property
allowing the change to be enabled and disabled.

Reported-by: Bijan Mottahedeh <bijan.mottahedeh@oracle.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-6-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  7 ++++
 target/arm/kvm_arm.h | 38 ++++++++++++++++++
 target/arm/kvm.c     | 92 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/kvm32.c   |  3 ++
 target/arm/kvm64.c   |  3 ++
 target/arm/machine.c |  7 ++++
 6 files changed, 150 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     /* KVM init features for this CPU */
     uint32_t kvm_init_features[7];
 
+    /* KVM CPU state */
+
+    /* KVM virtual time adjustment */
+    bool kvm_adjvtime;
+    bool kvm_vtime_dirty;
+    uint64_t kvm_vtime;
+
     /* Uniprocessor system with MP extensions */
     bool mp_is_up;
 
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level);
  */
 bool write_kvmstate_to_list(ARMCPU *cpu);
 
+/**
+ * kvm_arm_cpu_pre_save:
+ * @cpu: ARMCPU
+ *
+ * Called after write_kvmstate_to_list() from cpu_pre_save() to update
+ * the cpreg list with KVM CPU state.
+ */
+void kvm_arm_cpu_pre_save(ARMCPU *cpu);
+
+/**
+ * kvm_arm_cpu_post_load:
+ * @cpu: ARMCPU
+ *
+ * Called from cpu_post_load() to update KVM CPU state from the cpreg list.
+ */
+void kvm_arm_cpu_post_load(ARMCPU *cpu);
+
 /**
  * kvm_arm_reset_vcpu:
  * @cpu: ARMCPU
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu);
  */
 int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
 
+/**
+ * kvm_arm_get_virtual_time:
+ * @cs: CPUState
+ *
+ * Gets the VCPU's virtual counter and stores it in the KVM CPU state.
+ */
+void kvm_arm_get_virtual_time(CPUState *cs);
+
+/**
+ * kvm_arm_put_virtual_time:
+ * @cs: CPUState
+ *
+ * Sets the VCPU's virtual counter to the value stored in the KVM CPU state.
+ */
+void kvm_arm_put_virtual_time(CPUState *cs);
+
+void kvm_arm_vm_state_change(void *opaque, int running, RunState state);
+
 int kvm_arm_vgic_probe(void);
 
 void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
 static inline void kvm_arm_pmu_init(CPUState *cs) {}
 
 static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
+
+static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
+static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
 #endif
 
 static inline const char *gic_class_name(void)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static int compare_u64(const void *a, const void *b)
     return 0;
 }
 
+/*
+ * cpreg_values are sorted in ascending order by KVM register ID
+ * (see kvm_arm_init_cpreg_list). This allows us to cheaply find
+ * the storage for a KVM register by ID with a binary search.
+ */
+static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx)
+{
+    uint64_t *res;
+
+    res = bsearch(&regidx, cpu->cpreg_indexes, cpu->cpreg_array_len,
+                  sizeof(uint64_t), compare_u64);
+    assert(res);
+
+    return &cpu->cpreg_values[res - cpu->cpreg_indexes];
+}
+
 /* Initialize the ARMCPU cpreg list according to the kernel's
  * definition of what CPU registers it knows about (and throw away
  * the previous TCG-created cpreg list).
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
     return ok;
 }
 
+void kvm_arm_cpu_pre_save(ARMCPU *cpu)
+{
+    /* KVM virtual time adjustment */
+    if (cpu->kvm_vtime_dirty) {
+        *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime;
+    }
+}
+
+void kvm_arm_cpu_post_load(ARMCPU *cpu)
+{
+    /* KVM virtual time adjustment */
+    if (cpu->kvm_adjvtime) {
+        cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT);
+        cpu->kvm_vtime_dirty = true;
+    }
+}
+
 void kvm_arm_reset_vcpu(ARMCPU *cpu)
 {
     int ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
     return 0;
 }
 
+void kvm_arm_get_virtual_time(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_ARM_TIMER_CNT,
+        .addr = (uintptr_t)&cpu->kvm_vtime,
+    };
+    int ret;
+
+    if (cpu->kvm_vtime_dirty) {
+        return;
+    }
+
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret) {
+        error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
+        abort();
+    }
+
+    cpu->kvm_vtime_dirty = true;
+}
+
+void kvm_arm_put_virtual_time(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_ARM_TIMER_CNT,
+        .addr = (uintptr_t)&cpu->kvm_vtime,
+    };
+    int ret;
+
+    if (!cpu->kvm_vtime_dirty) {
+        return;
+    }
+
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    if (ret) {
+        error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
+        abort();
+    }
+
+    cpu->kvm_vtime_dirty = false;
+}
+
 int kvm_put_vcpu_events(ARMCPU *cpu)
 {
     CPUARMState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
     return MEMTXATTRS_UNSPECIFIED;
 }
 
+void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
+{
+    CPUState *cs = opaque;
+    ARMCPU *cpu = ARM_CPU(cs);
+
+    if (running) {
+        if (cpu->kvm_adjvtime) {
+            kvm_arm_put_virtual_time(cs);
+        }
+    } else {
+        if (cpu->kvm_adjvtime) {
+            kvm_arm_get_virtual_time(cs);
+        }
+    }
+}
 
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "qemu/timer.h"
+#include "sysemu/runstate.h"
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         return -EINVAL;
     }
 
+    qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
+
     /* Determine init features for this CPU */
     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
     if (cpu->start_powered_off) {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/host-utils.h"
 #include "qemu/main-loop.h"
 #include "exec/gdbstub.h"
+#include "sysemu/runstate.h"
 #include "sysemu/kvm.h"
 #include "sysemu/kvm_int.h"
 #include "kvm_arm.h"
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         return -EINVAL;
     }
 
+    qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
+
     /* Determine init features for this CPU */
     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
     if (cpu->start_powered_off) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
             /* This should never fail */
             abort();
         }
+
+        /*
+         * kvm_arm_cpu_pre_save() must be called after
+         * write_kvmstate_to_list()
+         */
+        kvm_arm_cpu_pre_save(cpu);
     } else {
         if (!write_cpustate_to_list(cpu, false)) {
             /* This should never fail. */
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
          * we're using it.
          */
         write_list_to_cpustate(cpu);
+        kvm_arm_cpu_post_load(cpu);
     } else {
         if (!write_list_to_cpustate(cpu)) {
             return -1;
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

kvm-no-adjvtime is a KVM specific CPU property and a first of its
kind. To accommodate it we also add kvm_arm_add_vcpu_properties()
and a KVM specific CPU properties description to the CPU features
document.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200120101023.16030-7-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h          |  1 +
 target/arm/kvm_arm.h           | 11 ++++++++++
 hw/arm/virt.c                  |  8 ++++++++
 target/arm/cpu.c               |  2 ++
 target/arm/cpu64.c             |  1 +
 target/arm/kvm.c               | 28 +++++++++++++++++++++++++
 target/arm/monitor.c           |  1 +
 tests/qtest/arm-cpu-features.c |  4 ++++
 docs/arm-cpu-features.rst      | 37 +++++++++++++++++++++++++++++++++-
 9 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     bool smbios_old_sys_ver;
     bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
+    bool kvm_no_adjvtime;
 } VirtMachineClass;
 
 typedef struct {
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
  */
 void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
 
+/**
+ * kvm_arm_add_vcpu_properties:
+ * @obj: The CPU object to add the properties to
+ *
+ * Add all KVM specific CPU properties to the CPU object. These
+ * are the CPU properties with "kvm-" prefixed names.
+ */
+void kvm_arm_add_vcpu_properties(Object *obj);
+
 /**
  * kvm_arm_aarch32_supported:
  * @cs: CPUState
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
     cpu->host_cpu_probe_failed = true;
 }
 
+static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
+
 static inline bool kvm_arm_aarch32_supported(CPUState *cs)
 {
     return false;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
             }
         }
 
+        if (vmc->kvm_no_adjvtime &&
+            object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) {
+            object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL);
+        }
+
         if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
             object_property_set_bool(cpuobj, false, "pmu", NULL);
         }
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0)
 
 static void virt_machine_4_2_options(MachineClass *mc)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
     virt_machine_5_0_options(mc);
     compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
+    vmc->kvm_no_adjvtime = true;
 }
 DEFINE_VIRT_MACHINE(4, 2)
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
+        kvm_arm_add_vcpu_properties(obj);
     } else {
         cortex_a15_initfn(obj);
 
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
         aarch64_add_sve_properties(obj);
     }
+    kvm_arm_add_vcpu_properties(obj);
     arm_cpu_post_init(obj);
 }
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
+        kvm_arm_add_vcpu_properties(obj);
     } else {
         uint64_t t;
         uint32_t u;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 #include "qemu/main-loop.h"
+#include "qom/object.h"
+#include "qapi/error.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "sysemu/kvm_int.h"
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
     env->features = arm_host_cpu_features.features;
 }
 
+static bool kvm_no_adjvtime_get(Object *obj, Error **errp)
+{
+    return !ARM_CPU(obj)->kvm_adjvtime;
+}
+
+static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
+{
+    ARM_CPU(obj)->kvm_adjvtime = !value;
+}
+
+/* KVM VCPU properties should be prefixed with "kvm-". */
+void kvm_arm_add_vcpu_properties(Object *obj)
+{
+    if (!kvm_enabled()) {
+        return;
+    }
+
+    ARM_CPU(obj)->kvm_adjvtime = true;
+    object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get,
+                             kvm_no_adjvtime_set, &error_abort);
+    object_property_set_description(obj, "kvm-no-adjvtime",
+                                    "Set on to disable the adjustment of "
+                                    "the virtual counter. VM stopped time "
+                                    "will be counted.", &error_abort);
+}
+
 bool kvm_arm_pmu_supported(CPUState *cpu)
 {
     return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
     "sve128", "sve256", "sve384", "sve512",
     "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
     "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
+    "kvm-no-adjvtime",
     NULL
 };
 
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
     assert_has_feature_enabled(qts, "cortex-a15", "pmu");
     assert_has_not_feature(qts, "cortex-a15", "aarch64");
 
+    assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
+
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         assert_has_feature_enabled(qts, "max", "aarch64");
         assert_has_feature_enabled(qts, "max", "sve");
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         return;
     }
 
+    assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
+
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         bool kvm_supports_sve;
         char max_name[8], name[8];
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ supporting the feature or only supporting the feature under certain
 configurations.  For example, the `aarch64` CPU feature, which, when
 disabled, enables the optional AArch32 CPU feature, is only supported
 when using the KVM accelerator and when running on a host CPU type that
-supports the feature.
+supports the feature.  While `aarch64` currently only works with KVM,
+it could work with TCG.  CPU features that are specific to KVM are
+prefixed with "kvm-" and are described in "KVM VCPU Features".
 
 CPU Feature Probing
 ===================
@@ -XXX,XX +XXX,XX @@ disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
 properties have special semantics (see "SVE CPU Property Parsing
 Semantics").
 
+KVM VCPU Features
+=================
+
+KVM VCPU features are CPU features that are specific to KVM, such as
+paravirt features or features that enable CPU virtualization extensions.
+The features' CPU properties are only available when KVM is enabled and
+are named with the prefix "kvm-".  KVM VCPU features may be probed,
+enabled, and disabled in the same way as other CPU features.  Below is
+the list of KVM VCPU features and their descriptions.
+
+  kvm-no-adjvtime          By default kvm-no-adjvtime is disabled.  This
+                           means that by default the virtual time
+                           adjustment is enabled (vtime is *not not*
+                           adjusted).
+
+                           When virtual time adjustment is enabled each
+                           time the VM transitions back to running state
+                           the VCPU's virtual counter is updated to ensure
+                           stopped time is not counted.  This avoids time
+                           jumps surprising guest OSes and applications,
+                           as long as they use the virtual counter for
+                           timekeeping.  However it has the side effect of
+                           the virtual and physical counters diverging.
+                           All timekeeping based on the virtual counter
+                           will appear to lag behind any timekeeping that
+                           does not subtract VM stopped time.  The guest
+                           may resynchronize its virtual counter with
+                           other time sources as needed.
+
+                           Enable kvm-no-adjvtime to disable virtual time
+                           adjustment, also restoring the legacy (pre-5.0)
+                           behavior.
+
 SVE CPU Properties
 ==================
 
-- 
2.20.1

The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

----------------------------------------------------------------
target-arm queue:
 * more MVE instructions
 * hw/gpio/gpio_pwr: use shutdown function for reboot
 * target/arm: Check NaN mode before silencing NaN
 * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 * hw/arm: Add basic power management to raspi.
 * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

----------------------------------------------------------------
Joe Komlodi (1):
      target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):
      hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):
      hw/arm: Add basic power management to raspi.

Patrick Venture (2):
      docs/system/arm: Add quanta-q7l1-bmc reference
      docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):
      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Make asimd_imm_const() public
      target/arm: Use asimd_imm_const for A64 decode
      target/arm: Use dup_const() instead of bitfield_replicate()
      target/arm: Implement MVE logical immediate insns
      target/arm: Implement MVE vector shift left by immediate insns
      target/arm: Implement MVE vector shift right by immediate insns
      target/arm: Implement MVE VSHLL
      target/arm: Implement MVE VSRI, VSLI
      target/arm: Implement MVE VSHRN, VRSHRN
      target/arm: Implement MVE saturating narrowing shifts
      target/arm: Implement MVE VSHLC
      target/arm: Implement MVE VADDLV
      target/arm: Implement MVE long shifts by immediate
      target/arm: Implement MVE long shifts by register
      target/arm: Implement MVE shifts by immediate
      target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):
      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst             |   1 +
 docs/system/arm/nuvoton.rst            |   5 +-
 include/hw/arm/bcm2835_peripherals.h   |   3 +-
 include/hw/misc/bcm2835_powermgt.h     |  29 ++
 target/arm/helper-mve.h                | 108 +++++++
 target/arm/translate.h                 |  41 +++
 target/arm/mve.decode                  | 177 ++++++++++-
 target/arm/t32.decode                  |  71 ++++-
 hw/arm/bcm2835_peripherals.c           |  13 +-
 hw/gpio/gpio_pwr.c                     |   2 +-
 hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
 target/arm/helper-a64.c                |  12 +-
 target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c             |  86 +-----
 target/arm/translate-mve.c             | 261 +++++++++++++++-
 target/arm/translate-neon.c            |  81 -----
 target/arm/translate.c                 | 327 +++++++++++++++++++-
 target/arm/vfp_helper.c                |  24 +-
 hw/misc/meson.build                    |   1 +
 tests/acceptance/boot_linux_console.py |  43 +++
 20 files changed, 1760 insertions(+), 209 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-=====================================================
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+================================================================
 
 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
 Hyperscale applications. The following machines are based on this chip :
 
+- ``quanta-gbs-bmc``    Quanta GBS server BMC
 - ``quanta-gsj``        Quanta GSJ server BMC
 
 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
-- 
2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
 moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   3 +-
 include/hw/misc/bcm2835_powermgt.h   |  29 +++++
 hw/arm/bcm2835_peripherals.c         |  13 ++-
 hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
 hw/misc/meson.build                  |   1 +
 5 files changed, 204 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_powermgt.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
 #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     BCM2835MphiState mphi;
     UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
-    UnimplementedDeviceState powermgt;
+    BCM2835PowerMgtState powermgt;
     BCM2835CprmanState cprman;
     PL011State uart0;
     BCM2835AuxState aux;
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_powermgt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_POWERMGT_H
+#define BCM2835_POWERMGT_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
+
+struct BCM2835PowerMgtState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+
+    uint32_t rstc;
+    uint32_t rsts;
+    uint32_t wdog;
+};
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
 
     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                    OBJECT(&s->gpu_bus_mr));
+
+    /* Power Management */
+    object_initialize_child(obj, "powermgt", &s->powermgt,
+                            TYPE_BCM2835_POWERMGT);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    /* Power Management */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+
     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/bcm2835_powermgt.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
+
+#define PASSWORD 0x5a000000
+#define PASSWORD_MASK 0xff000000
+
+#define R_RSTC 0x1c
+#define V_RSTC_RESET 0x20
+#define R_RSTS 0x20
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
+#define R_WDOG 0x24
+
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+    uint32_t res = 0;
+
+    switch (offset) {
+    case R_RSTC:
+        res = s->rstc;
+        break;
+    case R_RSTS:
+        res = s->rsts;
+        break;
+    case R_WDOG:
+        res = s->wdog;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        res = 0;
+        break;
+    }
+
+    return res;
+}
+
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+
+    if ((value & PASSWORD_MASK) != PASSWORD) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
+                      " at offset 0x%08"HWADDR_PRIx"\n",
+                      value, offset);
+        return;
+    }
+
+    value = value & ~PASSWORD_MASK;
+
+    switch (offset) {
+    case R_RSTC:
+        s->rstc = value;
+        if (value & V_RSTC_RESET) {
+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+            } else {
+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            }
+        }
+        break;
+    case R_RSTS:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: RSTS\n");
+        s->rsts = value;
+        break;
+    case R_WDOG:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: WDOG\n");
+        s->wdog = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps bcm2835_powermgt_ops = {
+    .read = bcm2835_powermgt_read,
+    .write = bcm2835_powermgt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_powermgt = {
+    .name = TYPE_BCM2835_POWERMGT,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void bcm2835_powermgt_init(Object *obj)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+
+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+                          TYPE_BCM2835_POWERMGT, 0x200);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_powermgt_reset(DeviceState *dev)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+
+    /* https://elinux.org/BCM2835_registers#PM */
+    s->rstc = 0x00000102;
+    s->rsts = 0x00001000;
+    s->wdog = 0x00000000;
+}
+
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = bcm2835_powermgt_reset;
+    dc->vmsd = &vmstate_bcm2835_powermgt;
+}
+
+static TypeInfo bcm2835_powermgt_info = {
+    .name          = TYPE_BCM2835_POWERMGT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835PowerMgtState),
+    .class_init    = bcm2835_powermgt_class_init,
+    .instance_init = bcm2835_powermgt_init,
+};
+
+static void bcm2835_powermgt_register_types(void)
+{
+    type_register_static(&bcm2835_powermgt_info);
+}
+
+type_init(bcm2835_powermgt_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
   'bcm2835_rng.c',
   'bcm2835_thermal.c',
   'bcm2835_cprman.c',
+  'bcm2835_powermgt.c',
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
  console: [    0.000000] Booting Linux on physical CPU 0xf00
  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
  console: [    0.000000] CPU: div instructions available: patching division code
  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
  ...
  console: Boot successful.
  console: cat /proc/cpuinfo
  console: / # cat /proc/cpuinfo
  ...
  console: processor      : 3
  console: model name     : ARMv7 Processor rev 5 (v7l)
  console: BogoMIPS       : 125.00
  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  console: CPU implementer        : 0x41
  console: CPU architecture: 7
  console: CPU variant    : 0x0
  console: CPU part       : 0xc07
  console: CPU revision   : 5
  console: Hardware       : BCM2835
  console: Revision       : 0000
  console: Serial         : 0000000000000000
  console: cat /proc/iomem
  console: / # cat /proc/iomem
  console: 00000000-3bffffff : System RAM
  console: 00008000-00afffff : Kernel code
  console: 00c00000-00d468ef : Kernel data
  console: 3f006000-3f006fff : dwc_otg
  console: 3f007000-3f007eff : /soc/dma@7e007000
  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
  console: 3f100000-3f100027 : /soc/watchdog@7e100000
  console: 3f101000-3f102fff : /soc/cprman@7e101000
  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
  PASS (24.59 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
  JOB TIME   : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@
 from avocado import skip
 from avocado import skipUnless
 from avocado_qemu import Test
+from avocado_qemu import exec_command
 from avocado_qemu import exec_command_and_wait_for_pattern
 from avocado_qemu import interrupt_interactive_console_until_pattern
 from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
         """
         self.do_test_arm_raspi2(0)
 
+    def test_arm_raspi2_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:raspi2
+        """
+        deb_url = ('http://archive.raspberrypi.org/debian/'
+                   'pool/main/r/raspberrypi-firmware/'
+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
+
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv7a.cpio.gz')
+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+                               'panic=-1 noreboot ' +
+                               'dwc_otg.fiq_fsm_enable=0')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'BCM2835')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                '/soc/cprman@7e101000')
+        exec_command(self, 'halt')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_arm_exynos4210_initrd(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.c | 12 +++++++++---
 target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
         float16 nan = a;
         if (float16_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         float32 nan = a;
         if (float32_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         float64 nan = a;
         if (float64_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float64_default_nan(fpst);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(f16, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(f32, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(f64, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float16_silence_nan(f16, s);
+            if (!s->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float32_silence_nan(f32, s);
+            if (!s->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float64_silence_nan(f64, s);
+            if (!s->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float64_default_nan(s);
-- 
2.20.1

From: Maxim Uvarov <maxim.uvarov@linaro.org>

qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/gpio_pwr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/gpio_pwr.c
+++ b/hw/gpio/gpio_pwr.c
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
 static void gpio_pwr_shutdown(void *opaque, int n, int level)
 {
     if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
     }
 }
 
-- 
2.20.1

In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector.  This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
     }
 }
 
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+                    unsigned msize)
 {
     TCGv_i32 addr;
     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
         return true;
     }
 
-    offset = a->imm << a->size;
+    offset = a->imm << msize;
     if (!a->a) {
         offset = -offset;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
         { NULL, NULL }
     };
-    return do_ldst(s, a, ldstfns[a->size][a->l]);
+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 }
 
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
     {                                                           \
         static MVEGenLdStFn * const ldstfns[2][2] = {           \
             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
             { NULL, gen_helper_mve_##ULD },                     \
         };                                                      \
-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
     }
 
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
 
 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 {
-- 
2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
 * the 32x32 multiply of elements was being done as 32x32->32,
   not 32x32->64
 * we were incorrectly maintaining the accumulator in its full
   72-bit form across all 4 beats of the insn; in the pseudocode
   it is squashed back into the 64 bits of the RdaHi:RdaLo
   registers after each beat

In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
---
 target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/int128.h"
 #include "cpu.h"
 #include "internals.h"
 #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
 
 /*
- * Rounding multiply add long dual accumulate high: we must keep
- * a 72-bit internal accumulator value and return the top 64 bits.
+ * Rounding multiply add long dual accumulate high. In the pseudocode
+ * this is implemented with a 72-bit internal accumulator value of which
+ * the top 64 bits are returned. We optimize this to avoid having to
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
+ * is squashed back into 64-bits after each beat.
  */
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                     void *vm, uint64_t a)               \
     {                                                                   \
         uint16_t mask = mve_element_mask(env);                          \
         unsigned e;                                                     \
         TYPE *n = vn, *m = vm;                                          \
-        Int128 acc = int128_lshift(TO128(a), 8);                        \
-        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
             if (mask & 1) {                                             \
+                LTYPE mul;                                              \
                 if (e & 1) {                                            \
-                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
-                                            m[H##ESIZE(e)]));           \
+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
+                    if (SUB) {                                          \
+                        mul = -mul;                                     \
+                    }                                                   \
                 } else {                                                \
-                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
-                                             m[H##ESIZE(e)]));          \
+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                 }                                                       \
-                acc = int128_add(acc, int128_make64(1 << 7));           \
+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
+                a += mul;                                               \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \
-        return int128_getlo(int128_rshift(acc, 8));                     \
+        return a;                                                       \
     }
 
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
 
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
 
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
 
 /* Vector add across vector */
 #define DO_VADDV(OP, ESIZE, TYPE)                               \
-- 
2.20.1

The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE.  Move the implementation to translate.c, with a
prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
---
 target/arm/translate.h      | 16 ++++++++++
 target/arm/translate-neon.c | 63 -------------------------------------
 target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
     return opc | s->be_data;
 }
 
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
 DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
 DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
-    /*
-     * Expand the encoded constant.
-     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-     * We choose to not special-case this and will behave as if a
-     * valid constant encoding of 0 had been given.
-     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
-     */
-    switch (cmode) {
-    case 0: case 1:
-        /* no-op */
-        break;
-    case 2: case 3:
-        imm <<= 8;
-        break;
-    case 4: case 5:
-        imm <<= 16;
-        break;
-    case 6: case 7:
-        imm <<= 24;
-        break;
-    case 8: case 9:
-        imm |= imm << 16;
-        break;
-    case 10: case 11:
-        imm = (imm << 8) | (imm << 24);
-        break;
-    case 12:
-        imm = (imm << 8) | 0xff;
-        break;
-    case 13:
-        imm = (imm << 16) | 0xffff;
-        break;
-    case 14:
-        if (op) {
-            /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
-             */
-            uint64_t imm64 = 0;
-            int n;
-
-            for (n = 0; n < 8; n++) {
-                if (imm & (1 << n)) {
-                    imm64 |= (0xffULL << (n * 8));
-                }
-            }
-            return imm64;
-        }
-        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-        break;
-    case 15:
-        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-        break;
-    }
-    if (op) {
-        imm = ~imm;
-    }
-    return dup_const(MO_32, imm);
-}
-
 static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                         GVecGen2iFn *fn)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
 /* Generate a label used for skipping this instruction */
 void arm_gen_condlabel(DisasContext *s)
 {
-- 
2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
 target/arm/translate.h     |  3 +-
 target/arm/translate-a64.c | 86 ++++----------------------------------
 target/arm/translate.c     | 17 +++++++-
 3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  * VMVN and VBIC (when cmode < 14 && op == 1).
  *
  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
  *
  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int cmode = extract32(insn, 12, 4);
-    int cmode_3_1 = extract32(cmode, 1, 3);
-    int cmode_0 = extract32(cmode, 0, 1);
     int o2 = extract32(insn, 11, 1);
     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
     bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* See AdvSIMDExpandImm() in ARM ARM */
-    switch (cmode_3_1) {
-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-    {
-        int shift = cmode_3_1 * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 32);
-        break;
-    }
-    case 4: /* Replicate(Zeros(8):imm8, 4) */
-    case 5: /* Replicate(imm8:Zeros(8), 4) */
-    {
-        int shift = (cmode_3_1 & 0x1) * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 16);
-        break;
-    }
-    case 6:
-        if (cmode_0) {
-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
-            imm = (abcdefgh << 16) | 0xffff;
-        } else {
-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-            imm = (abcdefgh << 8) | 0xff;
-        }
-        imm = bitfield_replicate(imm, 32);
-        break;
-    case 7:
-        if (!cmode_0 && !is_neg) {
-            imm = bitfield_replicate(abcdefgh, 8);
-        } else if (!cmode_0 && is_neg) {
-            int i;
-            imm = 0;
-            for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
-                    imm |= 0xffULL << (i * 8);
-                }
-            }
-        } else if (cmode_0) {
-            if (is_neg) {
-                imm = (abcdefgh & 0x3f) << 48;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x8000000000000000ULL;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3fc0000000000000ULL;
-                } else {
-                    imm |= 0x4000000000000000ULL;
-                }
-            } else {
-                if (o2) {
-                    /* FMOV (vector, immediate) - half-precision */
-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-                    /* now duplicate across the lanes */
-                    imm = bitfield_replicate(imm, 16);
-                } else {
-                    imm = (abcdefgh & 0x3f) << 19;
-                    if (abcdefgh & 0x80) {
-                        imm |= 0x80000000;
-                    }
-                    if (abcdefgh & 0x40) {
-                        imm |= 0x3e000000;
-                    } else {
-                        imm |= 0x40000000;
-                    }
-                    imm |= (imm << 32);
-                }
-            }
-        }
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (cmode_3_1 != 7 && is_neg) {
-        imm = ~imm;
+    if (cmode == 15 && o2 && !is_neg) {
+        /* FMOV (vector, immediate) - half-precision */
+        imm = vfp_expand_imm(MO_16, abcdefgh);
+        /* now duplicate across the lanes */
+        imm = bitfield_replicate(imm, 16);
+    } else {
+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
 
     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
     case 14:
         if (op) {
             /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
+             * This and cmode == 15 op == 1 are the only cases where
+             * the top and bottom 32 bits of the encoded constant differ.
              */
             uint64_t imm64 = 0;
             int n;
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
         imm |= (imm << 8) | (imm << 16) | (imm << 24);
         break;
     case 15:
+        if (op) {
+            /* Reserved encoding for AArch32; valid for AArch64 */
+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+            if (imm & 0x80) {
+                imm64 |= 0x8000000000000000ULL;
+            }
+            if (imm & 0x40) {
+                imm64 |= 0x3fc0000000000000ULL;
+            } else {
+                imm64 |= 0x4000000000000000ULL;
+            }
+            return imm64;
+        }
         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
         break;
-- 
2.20.1

Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         /* FMOV (vector, immediate) - half-precision */
         imm = vfp_expand_imm(MO_16, abcdefgh);
         /* now duplicate across the lanes */
-        imm = bitfield_replicate(imm, 16);
+        imm = dup_const(MO_16, imm);
     } else {
         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
-- 
2.20.1

Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  4 +++
 target/arm/mve.decode      | 17 +++++++++++++
 target/arm/mve_helper.c    | 24 ++++++++++++++++++
 target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.

The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 16 +++++++++++
 target/arm/mve.decode      | 23 +++++++++++++++
 target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 &2op qd qm qn size
 &2scalar qd qn rm size
 &1imm qd imm cmode op
+&2shift qd qm shift size
 
 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
 # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+
 # Vector loads and stores
 
 # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 # So we have a single decode line and check the cmode/op in the
 # trans function.
 Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+
+# Shifts by immediate
+
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
 #define DO_UQRSHL_OP(N, M, satp) \
     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
+#define DO_SUQSHL_OP(N, M, satp) \
+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
 
 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
 DO_VADDV(vaddvub, 1, uint8_t)
 DO_VADDV(vaddvuh, 2, uint16_t)
 DO_VADDV(vaddvuw, 4, uint32_t)
+
+/* Shifts by immediate */
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift), mask);         \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        bool qc = false;                                        \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            bool sat = false;                                   \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
+            qc |= sat & mask & 1;                               \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+/* provide unsigned 2-op shift helpers for all sizes */
+#define DO_2SHIFT_U(OP, FN)                     \
+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
+
+#define DO_2SHIFT_SAT_U(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
+#define DO_2SHIFT_SAT_S(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
+
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     }
     return do_1imm(s, a, fn);
 }
+
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    TCGv_ptr qd, qm;
+    int shift = a->shift;
+
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
+        !fn) {
+        return false;
+    }
+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * When we handle a right shift insn using a left-shift helper
+     * which permits a negative shift count to indicate a right-shift,
+     * we must negate the shift count.
+     */
+    if (negateshift) {
+        shift = -shift;
+    }
+
+    qd = mve_qreg_ptr(a->qd);
+    qm = mve_qreg_ptr(a->qm);
+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+    tcg_temp_free_ptr(qd);
+    tcg_temp_free_ptr(qm);
+    mve_update_eci(s);
+    return true;
+}
+
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+            gen_helper_mve_##FN##w,                             \
+            NULL,                                               \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+    }
+
+DO_2SHIFT(VSHLI, vshli_u, false)
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
-- 
2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI.  As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
---
 target/arm/helper-mve.h     | 12 ++++++++++++
 target/arm/translate.h      | 20 ++++++++++++++++++++
 target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
 target/arm/mve_helper.c     |  7 +++++++
 target/arm/translate-mve.c  |  5 +++++
 target/arm/translate-neon.c | 18 ------------------
 6 files changed, 72 insertions(+), 18 deletions(-)

Implement the MVE VHLL (vector shift left long) insn.  This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  9 +++++++
 target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
 target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
 target/arm/translate-mve.c | 15 +++++++++++
 4 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+# VSHLL encoding T2 where shift == esize
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=0 shift=8
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=1 shift=16
+
 # Right shifts are encoded as N - shift, where N is the element size in bits.
 %rshift_i5  16:5 !function=rsub_32
 %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 
-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+# overlaps what would be size=0b11 VMULH/VRMULH
+{
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 
-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
 
 VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+
+/*
+ * Long shifts taking half-sized inputs from top or bottom of the input
+ * vector and producing a double-width result. ESIZE, TYPE are for
+ * the input, and LESIZE, LTYPE for the output.
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+ * because the long shift is strictly left-only.
+ */
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+                                void *vm, uint32_t shift)               \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *m = vm;                                                   \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        assert(shift <= 16);                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
+#define DO_VSHLL_ALL(OP, TOP)                                \
+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+
+DO_VSHLL_ALL(vshllb, false)
+DO_VSHLL_ALL(vshllt, true)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
 DO_2SHIFT(VSHRI_U, vshli_u, true)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+
+#define DO_VSHLL(INSN, FN)                                      \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], false);            \
+    }
+
+DO_VSHLL(VSHLL_BS, vshllbs)
+DO_VSHLL(VSHLL_BU, vshllbu)
+DO_VSHLL(VSHLL_TS, vshllts)
+DO_VSHLL(VSHLL_TU, vshlltu)
-- 
2.20.1

Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  8 ++++++++
 target/arm/mve.decode      |  9 ++++++++
 target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  3 +++
 4 files changed, 62 insertions(+)

Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.

do_urshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 11 +++++++++++
 target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 15 ++++++++++++++
 4 files changed, 76 insertions(+)

Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.

do_srshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  30 +++++++++++
 target/arm/mve.decode      |  28 ++++++++++
 target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  12 +++++
 4 files changed, 174 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
     }
 }
 
+static inline int64_t do_srshr(int64_t x, unsigned sh)
+{
+    if (likely(sh < 64)) {
+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+    } else {
+        /* Rounding the sign bit always produces 0. */
+        return 0;
+    }
+}
+
 DO_VSHRN_ALL(vshrn, DO_SHR)
 DO_VSHRN_ALL(vrshrn, do_urshr)
+
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
+                                 bool *satp)
+{
+    if (val > max) {
+        *satp = true;
+        return max;
+    } else if (val < min) {
+        *satp = true;
+        return min;
+    } else {
+        return val;
+    }
+}
+
+/* Saturating narrowing right shifts */
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        LTYPE *m = vm;                                          \
+        TYPE *d = vd;                                           \
+        uint16_t mask = mve_element_mask(env);                  \
+        bool qc = false;                                        \
+        unsigned le;                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+            bool sat = false;                                   \
+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
+
+#define DO_SHRN_SB(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+#define DO_SHRN_UB(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+#define DO_SHRUN_B(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+
+#define DO_SHRN_SH(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+#define DO_SHRN_UH(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+#define DO_SHRUN_H(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+
+#define DO_RSHRN_SB(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+#define DO_RSHRN_UB(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
+#define DO_RSHRUN_B(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
+
+#define DO_RSHRN_SH(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
+#define DO_RSHRN_UH(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
+#define DO_RSHRUN_H(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
+
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
+
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
 DO_2SHIFT_N(VSHRNT, vshrnt)
 DO_2SHIFT_N(VRSHRNB, vrshrnb)
 DO_2SHIFT_N(VRSHRNT, vrshrnt)
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-- 
2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  2 ++
 target/arm/mve.decode      |  2 ++
 target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+)

Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  3 ++
 target/arm/mve.decode      |  6 +++-
 target/arm/mve_helper.c    | 19 ++++++++++++
 target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 1 deletion(-)

The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers.  They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 28 +++++++++++++
 target/arm/mve_helper.c | 10 +++++
 target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)

Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  6 +++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 16 +++++--
 target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 
 /**
  * arm_tbflags_from_tb:
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
 &mcrr            !extern cp opc1 crm rt rt2
 
 &mve_shl_ri      rdalo rdahi shim
+&mve_shl_rr      rdalo rdahi rm
 
 # rdahi: bits [3:1] from insn, bit 0 is 1
 # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
 
 @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 
 {
   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+
+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
   ]
 
   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+
+  # v8.1M CSEL and friends
+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 }
 {
   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
 }
 RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 
-# v8.1M CSEL and friends
-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-
 # Data-processing (register-shifted register)
 
 MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
     return rdm;
 }
 
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
+}
+
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
+}
+
 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 }
+
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
+                                    bool round, uint32_t *sat)
+{
+    if (shift <= -48) {
+        /* Rounding the sign bit always produces 0. */
+        if (round) {
+            return 0;
+        }
+        return src >> 63;
+    } else if (shift < 0) {
+        if (round) {
+            src >>= -shift - 1;
+            return (src >> 1) + (src & 1);
+        }
+        return src >> -shift;
+    } else if (shift < 48) {
+        int64_t val = src << shift;
+        int64_t extval = sextract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return (1ULL << 47) - (src >= 0);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
+                                     bool round, uint32_t *sat)
+{
+    uint64_t val, extval;
+
+    if (shift <= -(48 + round)) {
+        return 0;
+    } else if (shift < 0) {
+        if (round) {
+            val = src >> (-shift - 1);
+            val = (val >> 1) + (val & 1);
+        } else {
+            val = src >> -shift;
+        }
+        extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (shift < 48) {
+        uint64_t val = src << shift;
+        uint64_t extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return MAKE_64BIT_MASK(0, 48);
+}
+
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
     return do_mve_shl_ri(s, a, gen_urshr64_i64);
 }
 
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
+{
+    TCGv_i64 rda;
+    TCGv_i32 rdalo, rdahi;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+        return false;
+    }
+    if (a->rdahi == 15) {
+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
+        return false;
+    }
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
+        a->rm == a->rdahi || a->rm == a->rdalo) {
+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    rda = tcg_temp_new_i64();
+    rdalo = load_reg(s, a->rdalo);
+    rdahi = load_reg(s, a->rdahi);
+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+
+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
+
+    tcg_gen_extrl_i64_i32(rdalo, rda);
+    tcg_gen_extrh_i64_i32(rdahi, rda);
+    store_reg(s, a->rdalo, rdalo);
+    store_reg(s, a->rdahi, rdahi);
+    tcg_temp_free_i64(rda);
+
+    return true;
+}
+
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
+}
+
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+}
+
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
+}
+
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
+}
+
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
+}
+
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
+}
+
 /*
  * Multiply and multiply accumulate
  */
-- 
2.20.1

Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 31 ++++++++++++++-----
 target/arm/mve_helper.c | 10 ++++++
 target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 5 files changed, 104 insertions(+), 9 deletions(-)

Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  2 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 18 ++++++++++++++----
 target/arm/mve_helper.c | 10 ++++++++++
 target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 4 deletions(-)