target-arm queue. The big thing here is the landing of the 3-phase reset patches... -- PMM The following changes since commit 204aa60b37c23a89e690d418f49787d274303ca7: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging (2020-01-30 14:18:45 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200130 for you to fetch changes up to dea101a1ae9968c9fec6ab0291489dad7c49f36f: target/arm/cpu: Add the kvm-no-adjvtime CPU property (2020-01-30 16:02:06 +0000) ---------------------------------------------------------------- target-arm queue: * hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES * target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr * aspeed: some minor bugfixes * aspeed: add eMMC controller model for AST2600 SoC * hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' * New 3-phase reset API for device models * hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit * Arm KVM: stop/restart the guest counter when the VM is stopped and started ---------------------------------------------------------------- Andrew Jeffery (2): hw/sd: Configure number of slots exposed by the ASPEED SDHCI model hw/arm: ast2600: Wire up the eMMC controller Andrew Jones (6): target/arm/kvm: trivial: Clean up header documentation hw/arm/virt: Add missing 5.0 options call to 4.2 options target/arm/kvm64: kvm64 cpus have timer registers tests/arm-cpu-features: Check feature default values target/arm/kvm: Implement virtual time adjustment target/arm/cpu: Add the kvm-no-adjvtime CPU property Cédric Le Goater (2): ftgmac100: check RX and TX buffer alignment hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 Damien Hedde (11): add device_legacy_reset function to prepare for reset api change hw/core/qdev: add trace events to help with resettable transition hw/core: create Resettable QOM interface hw/core: add Resettable support to BusClass and DeviceClass hw/core/resettable: add support for changing parent hw/core/qdev: handle parent bus change regarding resettable hw/core/qdev: update hotplug reset regarding resettable hw/core: deprecate old reset functions and introduce new ones docs/devel/reset.rst: add doc about Resettable interface vl: replace deprecated qbus_reset_all registration hw/s390x/ipl: replace deprecated qdev_reset_all registration Joel Stanley (1): misc/pca9552: Add qom set and get Peter Maydell (2): hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr Philippe Mathieu-Daudé (1): hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' Zenghui Yu (1): hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit hw/core/Makefile.objs | 1 + tests/Makefile.include | 1 + include/hw/arm/aspeed.h | 2 + include/hw/arm/aspeed_soc.h | 2 + include/hw/arm/virt.h | 1 + include/hw/qdev-core.h | 58 +++++++- include/hw/resettable.h | 247 +++++++++++++++++++++++++++++++++ include/hw/sd/aspeed_sdhci.h | 1 + target/arm/cpu.h | 7 + target/arm/kvm_arm.h | 95 ++++++++++--- hw/arm/aspeed.c | 72 ++++++++-- hw/arm/aspeed_ast2600.c | 31 ++++- hw/arm/aspeed_soc.c | 2 + hw/arm/raspi.c | 2 - hw/arm/virt.c | 9 ++ hw/audio/intel-hda.c | 2 +- hw/core/bus.c | 102 ++++++++++++++ hw/core/or-irq.c | 2 +- hw/core/qdev.c | 160 ++++++++++++++++++++-- hw/core/resettable.c | 301 +++++++++++++++++++++++++++++++++++++++++ hw/hyperv/hyperv.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/ide/microdrive.c | 8 +- hw/intc/arm_gicv3_kvm.c | 11 +- hw/intc/spapr_xive.c | 2 +- hw/misc/pca9552.c | 90 ++++++++++++ hw/net/ftgmac100.c | 13 ++ hw/ppc/pnv_psi.c | 4 +- hw/ppc/spapr_pci.c | 2 +- hw/ppc/spapr_vio.c | 2 +- hw/s390x/ipl.c | 10 +- hw/s390x/s390-pci-inst.c | 2 +- hw/scsi/vmw_pvscsi.c | 2 +- hw/sd/aspeed_sdhci.c | 11 +- hw/sd/omap_mmc.c | 2 +- hw/sd/pl181.c | 2 +- target/arm/arm-semi.c | 9 ++ target/arm/cpu.c | 2 + target/arm/cpu64.c | 1 + target/arm/kvm.c | 120 ++++++++++++++++ target/arm/kvm32.c | 3 + target/arm/kvm64.c | 4 + target/arm/machine.c | 7 + target/arm/monitor.c | 1 + tests/qtest/arm-cpu-features.c | 41 ++++-- vl.c | 10 +- docs/arm-cpu-features.rst | 37 ++++- docs/devel/index.rst | 1 + docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++ hw/core/trace-events | 27 ++++ 51 files changed, 1727 insertions(+), 90 deletions(-) create mode 100644 include/hw/resettable.h create mode 100644 hw/core/resettable.c create mode 100644 docs/devel/reset.rst The num-lines property of the TYPE_OR_GATE device sets the number of input lines it has. An assert() in or_irq_realize() restricts this to the maximum supported by the implementation. However we got the condition in the assert wrong: it should be using <=, because num-lines == MAX_OR_LINES is permitted, and means that all entries from 0 to MAX_OR_LINES-1 in the s->levels[] array are used. We didn't notice this previously because no user has so far needed that many input lines. Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200120142235.10432-1-peter.maydell@linaro.org --- hw/core/or-irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/or-irq.c +++ b/hw/core/or-irq.c @@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp) { qemu_or_irq *s = OR_IRQ(dev); - assert(s->num_lines < MAX_OR_LINES); + assert(s->num_lines <= MAX_OR_LINES); qdev_init_gpio_in(dev, or_irq_handler, s->num_lines); } -- 2.20.1 The guest can use the semihosting API to open a handle corresponding to QEMU's own stdin, stdout, or stderr. When the guest closes this handle, we should not close the underlying host stdin/stdout/stderr the way we would do if the handle corresponded to a host fd we'd opened on behalf of the guest in SYS_OPEN. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200124172954.28481-1-peter.maydell@linaro.org --- target/arm/arm-semi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -XXX,XX +XXX,XX @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) { CPUARMState *env = &cpu->env; + /* + * Only close the underlying host fd if it's one we opened on behalf + * of the guest in SYS_OPEN. + */ + if (gf->hostfd == STDIN_FILENO || + gf->hostfd == STDOUT_FILENO || + gf->hostfd == STDERR_FILENO) { + return 0; + } return set_swi_errno(env, close(gf->hostfd)); } -- 2.20.1 From: Andrew Jeffery <andrew@aj.id.au> The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-2-clg@kaod.org [PMM: fixed up to use device_class_set_props()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/sd/aspeed_sdhci.h | 1 + hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 2 ++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/sd/aspeed_sdhci.h +++ b/include/hw/sd/aspeed_sdhci.h @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDHCIState { SysBusDevice parent; SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; + uint8_t num_slots; MemoryRegion iomem; qemu_irq irq; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) amc->i2c_init(bmc); } - for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { + for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; DriveInfo *dinfo = drive_get_next(IF_SD); BlockBackend *blk; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index XXXXXXX..XXXXXXX 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_RESET 0x00030000 @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) /* Create input irqs for the slots */ qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, - sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); + sdhci, NULL, sdhci->num_slots); sysbus_init_irq(sbd, &sdhci->irq); memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, sdhci, TYPE_ASPEED_SDHCI, 0x1000); sysbus_init_mmio(sbd, &sdhci->iomem); - for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { + for (int i = 0; i < sdhci->num_slots; ++i) { Object *sdhci_slot = OBJECT(&sdhci->slots[i]); SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdhci = { }, }; +static Property aspeed_sdhci_properties[] = { + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) dc->realize = aspeed_sdhci_realize; dc->reset = aspeed_sdhci_reset; dc->vmsd = &vmstate_aspeed_sdhci; + device_class_set_props(dc, aspeed_sdhci_properties); } static TypeInfo aspeed_sdhci_info = { -- 2.20.1 From: Andrew Jeffery <andrew@aj.id.au> Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-3-clg@kaod.org [ clg : - removed ternary operator from sdhci_attach_drive() - renamed SDHCI objects with a '-controller' prefix ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed.c | 26 +++++++++++++++++--------- hw/arm/aspeed_ast2600.c | 29 ++++++++++++++++++++++++++--- 3 files changed, 45 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; + AspeedSDHCIState emmc; } AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -XXX,XX +XXX,XX @@ enum { ASPEED_MII4, ASPEED_SDRAM, ASPEED_XDMA, + ASPEED_EMMC, }; #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, } } +static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) +{ + DeviceState *card; + + card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), + TYPE_SD_CARD); + if (dinfo) { + qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); +} + static void aspeed_machine_init(MachineState *machine) { AspeedBoardState *bmc; @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) } for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { - SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; - DriveInfo *dinfo = drive_get_next(IF_SD); - BlockBackend *blk; - DeviceState *card; + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); + } - blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; - card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), - TYPE_SD_CARD); - qdev_prop_set_drive(card, "drive", blk, &error_fatal); - object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); + if (bmc->soc.emmc.num_slots) { + sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); } arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_ADC] = 0x1E6E9000, [ASPEED_VIDEO] = 0x1E700000, [ASPEED_SDHCI] = 0x1E740000, + [ASPEED_EMMC] = 0x1E750000, [ASPEED_GPIO] = 0x1E780000, [ASPEED_GPIO_1_8V] = 0x1E780800, [ASPEED_RTC] = 0x1E781000, @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { #define ASPEED_SOC_AST2600_MAX_IRQ 128 +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_UART1] = 47, [ASPEED_UART2] = 48, @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_ADC] = 78, [ASPEED_XDMA] = 6, [ASPEED_SDHCI] = 43, + [ASPEED_EMMC] = 15, [ASPEED_GPIO] = 40, [ASPEED_GPIO_1_8V] = 11, [ASPEED_RTC] = 13, @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), sizeof(s->gpio_1_8v), typename); - sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), - TYPE_ASPEED_SDHCI); + sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), + sizeof(s->sdhci), TYPE_ASPEED_SDHCI); object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { - sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), + sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", + OBJECT(&s->sdhci.slots[i]), sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); } + + sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), + sizeof(s->emmc), TYPE_ASPEED_SDHCI); + + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); + + sysbus_init_child_obj(obj, "emmc-controller.sdhci", + OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), + TYPE_SYSBUS_SDHCI); } /* @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_SDHCI)); + + /* eMMC */ + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_soc_get_irq(s, ASPEED_EMMC)); } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) -- 2.20.1 From: Cédric Le Goater <clg@kaod.org> These buffers should be aligned on 16 bytes. Ignore invalid RX and TX buffer addresses and log an error. All incoming and outgoing traffic will be dropped because no valid RX or TX descriptors will be available. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-4-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/net/ftgmac100.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index XXXXXXX..XXXXXXX 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -XXX,XX +XXX,XX @@ typedef struct { uint32_t des3; } FTGMAC100Desc; +#define FTGMAC100_DESC_ALIGNMENT 16 + /* * Specific RTL8211E MII Registers */ @@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr, s->itc = value; break; case FTGMAC100_RXR_BADR: /* Ring buffer address */ + if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%" + HWADDR_PRIx "\n", __func__, value); + return; + } + s->rx_ring = value; s->rx_descriptor = s->rx_ring; break; @@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr, break; case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */ + if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%" + HWADDR_PRIx "\n", __func__, value); + return; + } s->tx_ring = value; s->tx_descriptor = s->tx_ring; break; -- 2.20.1 From: Cédric Le Goater <clg@kaod.org> The overhead for the OpenBMC firmware images using the a custom U-Boot is around 2 seconds, which is fine, but with a U-Boot from mainline, it takes an extra 50 seconds or so to reach Linux. A quick survey on the number of reads performed on the flash memory region gives the following figures : OpenBMC U-Boot 922478 (~ 3.5 MBytes) Mainline U-Boot 20569977 (~ 80 MBytes) QEMU must be trashing the TCG TBs and reloading text very often. Some addresses are read more than 250.000 times. Until we find a solution to improve boot time, execution from MMIO is not activated by default. Setting this option also breaks migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200114103433.30534-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 44 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardState AspeedBoardState; typedef struct AspeedMachine { MachineState parent_obj; + + bool mmio_exec; } AspeedMachine; #define ASPEED_MACHINE_CLASS(klass) \ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) * SoC and 128MB for the AST2500 SoC, which is twice as big as * needed by the flash modules of the Aspeed machines. */ - memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", - fl->size, &error_abort); - memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, - boot_rom); - write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); + if (ASPEED_MACHINE(machine)->mmio_exec) { + memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + &fl->mmio, 0, fl->size); + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, + boot_rom); + } else { + memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + fl->size, &error_abort); + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, + boot_rom); + write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); + } } aspeed_board_binfo.ram_size = ram_size; @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) /* Bus 11: TODO ucd90160@64 */ } +static bool aspeed_get_mmio_exec(Object *obj, Error **errp) +{ + return ASPEED_MACHINE(obj)->mmio_exec; +} + +static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) +{ + ASPEED_MACHINE(obj)->mmio_exec = value; +} + +static void aspeed_machine_instance_init(Object *obj) +{ + ASPEED_MACHINE(obj)->mmio_exec = false; +} + +static void aspeed_machine_class_props_init(ObjectClass *oc) +{ + object_class_property_add_bool(oc, "execute-in-place", + aspeed_get_mmio_exec, + aspeed_set_mmio_exec, &error_abort); + object_class_property_set_description(oc, "execute-in-place", + "boot directly from CE0 flash device", &error_abort); +} + static void aspeed_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + + aspeed_machine_class_props_init(oc); } static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, .instance_size = sizeof(AspeedMachine), + .instance_init = aspeed_machine_instance_init, .class_size = sizeof(AspeedMachineClass), .class_init = aspeed_machine_class_init, .abstract = true, -- 2.20.1 From: Joel Stanley <joel@jms.id.au> Following the pattern of the work recently done with the ASPEED GPIO model, this adds support for inspecting and modifying the PCA9552 LEDs from the monitor. (qemu) qom-set /machine/unattached/device[17] led0 on (qemu) qom-set /machine/unattached/device[17] led0 off (qemu) qom-set /machine/unattached/device[17] led0 pwm0 (qemu) qom-set /machine/unattached/device[17] led0 pwm1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-6-clg@kaod.org [clg: - removed the "qom-get" examples from the commit log - merged memory leak fixes from Joel ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/pca9552.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -XXX,XX +XXX,XX @@ #include "hw/misc/pca9552.h" #include "hw/misc/pca9552_regs.h" #include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" #define PCA9552_LED_ON 0x0 #define PCA9552_LED_OFF 0x1 #define PCA9552_LED_PWM0 0x2 #define PCA9552_LED_PWM1 0x3 +static const char *led_state[] = {"on", "off", "pwm0", "pwm1"}; + static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin) { uint8_t reg = PCA9552_LS0 + (pin / 4); @@ -XXX,XX +XXX,XX @@ static int pca9552_event(I2CSlave *i2c, enum i2c_event event) return 0; } +static void pca9552_get_led(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9552State *s = PCA9552(obj); + int led, rc, reg; + uint8_t state; + + rc = sscanf(name, "led%2d", &led); + if (rc != 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (led < 0 || led > s->nr_leds) { + error_setg(errp, "%s invalid led %s", __func__, name); + return; + } + /* + * Get the LSx register as the qom interface should expose the device + * state, not the modeled 'input line' behaviour which would come from + * reading the INPUTx reg + */ + reg = PCA9552_LS0 + led / 4; + state = (pca9552_read(s, reg) >> (led % 8)) & 0x3; + visit_type_str(v, name, (char **)&led_state[state], errp); +} + +/* + * Return an LED selector register value based on an existing one, with + * the appropriate 2-bit state value set for the given LED number (0-3). + */ +static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state) +{ + return (oldval & (~(0x3 << (led_num << 1)))) | + ((state & 0x3) << (led_num << 1)); +} + +static void pca9552_set_led(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9552State *s = PCA9552(obj); + Error *local_err = NULL; + int led, rc, reg, val; + uint8_t state; + char *state_str; + + visit_type_str(v, name, &state_str, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + rc = sscanf(name, "led%2d", &led); + if (rc != 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (led < 0 || led > s->nr_leds) { + error_setg(errp, "%s invalid led %s", __func__, name); + return; + } + + for (state = 0; state < ARRAY_SIZE(led_state); state++) { + if (!strcmp(state_str, led_state[state])) { + break; + } + } + if (state >= ARRAY_SIZE(led_state)) { + error_setg(errp, "%s invalid led state %s", __func__, state_str); + return; + } + + reg = PCA9552_LS0 + led / 4; + val = pca9552_read(s, reg); + val = pca955x_ledsel(val, led % 4, state); + pca9552_write(s, reg, val); +} + static const VMStateDescription pca9552_vmstate = { .name = "PCA9552", .version_id = 0, @@ -XXX,XX +XXX,XX @@ static void pca9552_reset(DeviceState *dev) static void pca9552_initfn(Object *obj) { PCA9552State *s = PCA9552(obj); + int led; /* If support for the other PCA955X devices are implemented, these * constant values might be part of class structure describing the @@ -XXX,XX +XXX,XX @@ static void pca9552_initfn(Object *obj) */ s->max_reg = PCA9552_LS3; s->nr_leds = 16; + + for (led = 0; led < s->nr_leds; led++) { + char *name; + + name = g_strdup_printf("led%d", led); + object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led, + NULL, NULL, NULL); + g_free(name); + } } static void pca9552_class_init(ObjectClass *klass, void *data) -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> Since we enabled parallel TCG code generation for softmmu (see commit 3468b59 "tcg: enable multiple TCG contexts in softmmu") and its subsequent fix (commit 72649619 "add .min_cpus and .default_cpus fields to machine_class"), the raspi machines are restricted to always use their 4 cores: See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4): 222 static void raspi2_machine_init(MachineClass *mc) 223 { 224 mc->desc = "Raspberry Pi 2"; 230 mc->max_cpus = BCM283X_NCPUS; 231 mc->min_cpus = BCM283X_NCPUS; 232 mc->default_cpus = BCM283X_NCPUS; 235 }; 236 DEFINE_MACHINE("raspi2", raspi2_machine_init) We can no longer use the -smp option, as we get: $ qemu-system-arm -M raspi2 -smp 1 qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4 Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp, remove the unuseful code. We can achieve the same by using the '-global bcm2836.enabled-cpus=1' option. Reported-by: Laurent Bonnans <laurent.bonnans@here.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200120235159.18510-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus", - &error_abort); int board_rev = version == 3 ? 0xa02082 : 0xa21041; object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", &error_abort); -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Provide a temporary device_legacy_reset function doing what device_reset does to prepare for the transition with Resettable API. All occurrence of device_reset in the code tree are also replaced by device_legacy_reset. The new resettable API has different prototype and semantics (resetting child buses as well as the specified device). Subsequent commits will make the changeover for each call site individually; once that is complete device_legacy_reset() will be removed. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/qdev-core.h | 4 ++-- hw/audio/intel-hda.c | 2 +- hw/core/qdev.c | 6 +++--- hw/hyperv/hyperv.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/ide/microdrive.c | 8 ++++---- hw/intc/spapr_xive.c | 2 +- hw/ppc/pnv_psi.c | 4 ++-- hw/ppc/spapr_pci.c | 2 +- hw/ppc/spapr_vio.c | 2 +- hw/s390x/s390-pci-inst.c | 2 +- hw/scsi/vmw_pvscsi.c | 2 +- hw/sd/omap_mmc.c | 2 +- hw/sd/pl181.c | 2 +- 15 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -XXX,XX +XXX,XX @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev); void qdev_machine_init(void); /** - * @device_reset + * device_legacy_reset: * * Reset a single device (by calling the reset method). */ -void device_reset(DeviceState *dev); +void device_legacy_reset(DeviceState *dev); void device_class_set_props(DeviceClass *dc, Property *props); diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index XXXXXXX..XXXXXXX 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -XXX,XX +XXX,XX @@ static void intel_hda_reset(DeviceState *dev) QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { DeviceState *qdev = kid->child; cdev = HDA_CODEC_DEVICE(qdev); - device_reset(DEVICE(cdev)); + device_legacy_reset(DEVICE(cdev)); d->state_sts |= (1 << cdev->cad); } intel_hda_update_irq(d); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) static int qdev_reset_one(DeviceState *dev, void *opaque) { - device_reset(dev); + device_legacy_reset(dev); return 0; } @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) } } if (dev->hotplugged) { - device_reset(dev); + device_legacy_reset(dev); } dev->pending_deleted_event = false; @@ -XXX,XX +XXX,XX @@ void device_class_set_parent_unrealize(DeviceClass *dc, dc->unrealize = dev_unrealize; } -void device_reset(DeviceState *dev) +void device_legacy_reset(DeviceState *dev) { DeviceClass *klass = DEVICE_GET_CLASS(dev); diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index XXXXXXX..XXXXXXX 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -XXX,XX +XXX,XX @@ void hyperv_synic_reset(CPUState *cs) SynICState *synic = get_synic(cs); if (synic) { - device_reset(DEVICE(synic)); + device_legacy_reset(DEVICE(synic)); } } diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -XXX,XX +XXX,XX @@ static void microvm_machine_reset(MachineState *machine) cpu = X86_CPU(cs); if (cpu->apic_state) { - device_reset(cpu->apic_state); + device_legacy_reset(cpu->apic_state); } } } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -XXX,XX +XXX,XX @@ static void pc_machine_reset(MachineState *machine) cpu = X86_CPU(cs); if (cpu->apic_state) { - device_reset(cpu->apic_state); + device_legacy_reset(cpu->apic_state); } } } diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ide/microdrive.c +++ b/hw/ide/microdrive.c @@ -XXX,XX +XXX,XX @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value) case 0x00: /* Configuration Option Register */ s->opt = value & 0xcf; if (value & OPT_SRESET) { - device_reset(DEVICE(s)); + device_legacy_reset(DEVICE(s)); } md_interrupt_update(s); break; @@ -XXX,XX +XXX,XX @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value) case 0xe: /* Device Control */ s->ctrl = value; if (value & CTRL_SRST) { - device_reset(DEVICE(s)); + device_legacy_reset(DEVICE(s)); } md_interrupt_update(s); break; @@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_attach(PCMCIACardState *card) md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8); md->io_base = 0x0; - device_reset(DEVICE(md)); + device_legacy_reset(DEVICE(md)); md_interrupt_update(md); return 0; @@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_detach(PCMCIACardState *card) { MicroDriveState *md = MICRODRIVE(card); - device_reset(DEVICE(md)); + device_legacy_reset(DEVICE(md)); return 0; } diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -XXX,XX +XXX,XX @@ static target_ulong h_int_reset(PowerPCCPU *cpu, return H_PARAMETER; } - device_reset(DEVICE(xive)); + device_legacy_reset(DEVICE(xive)); if (kvm_irqchip_in_kernel()) { Error *local_err = NULL; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -XXX,XX +XXX,XX @@ static void pnv_psi_reset(DeviceState *dev) static void pnv_psi_reset_handler(void *dev) { - device_reset(DEVICE(dev)); + device_legacy_reset(DEVICE(dev)); } static void pnv_psi_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, break; case PSIHB9_INTERRUPT_CONTROL: if (val & PSIHB9_IRQ_RESET) { - device_reset(DEVICE(&psi9->source)); + device_legacy_reset(DEVICE(&psi9->source)); } psi->regs[reg] = val; break; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -XXX,XX +XXX,XX @@ static int spapr_phb_children_reset(Object *child, void *opaque) DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); if (dev) { - device_reset(dev); + device_legacy_reset(dev); } return 0; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -XXX,XX +XXX,XX @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq) static void spapr_vio_quiesce_one(SpaprVioDevice *dev) { if (dev->tcet) { - device_reset(DEVICE(dev->tcet)); + device_legacy_reset(DEVICE(dev->tcet)); } free_crq(dev); } diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index XXXXXXX..XXXXXXX 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -XXX,XX +XXX,XX @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); goto out; } - device_reset(DEVICE(pbdev)); + device_legacy_reset(DEVICE(pbdev)); pbdev->fh &= ~FH_MASK_ENABLE; pbdev->state = ZPCI_FS_DISABLED; stl_p(&ressetpci->fh, pbdev->fh); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -XXX,XX +XXX,XX @@ pvscsi_on_cmd_reset_device(PVSCSIState *s) if (sdev != NULL) { s->resetting++; - device_reset(&sdev->qdev); + device_legacy_reset(&sdev->qdev); s->resetting--; return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; } diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host) * into any bus, and we must reset it manually. When omap_mmc is * QOMified this must move into the QOM reset function. */ - device_reset(DEVICE(host->card)); + device_legacy_reset(DEVICE(host->card)); } static uint64_t omap_mmc_read(void *opaque, hwaddr offset, diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c index XXXXXXX..XXXXXXX 100644 --- a/hw/sd/pl181.c +++ b/hw/sd/pl181.c @@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d) /* Since we're still using the legacy SD API the card is not plugged * into any bus, and we must reset it manually. */ - device_reset(DEVICE(s->card)); + device_legacy_reset(DEVICE(s->card)); } static void pl181_init(Object *obj) -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Adds trace events to reset procedure and when updating the parent bus of a device. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/core/qdev.c | 29 ++++++++++++++++++++++++++--- hw/core/trace-events | 9 +++++++++ 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -XXX,XX +XXX,XX @@ #include "hw/boards.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "trace.h" bool qdev_hotplug = false; static bool qdev_hot_added = false; @@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) bool replugging = dev->parent_bus != NULL; if (replugging) { - /* Keep a reference to the device while it's not plugged into + trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)), + dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)), + OBJECT(bus), object_get_typename(OBJECT(bus))); + /* + * Keep a reference to the device while it's not plugged into * any bus, to avoid it potentially evaporating when it is * dereffed in bus_remove_child(). */ @@ -XXX,XX +XXX,XX @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) return hotplug_ctrl; } +static int qdev_prereset(DeviceState *dev, void *opaque) +{ + trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev))); + return 0; +} + +static int qbus_prereset(BusState *bus, void *opaque) +{ + trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus))); + return 0; +} + static int qdev_reset_one(DeviceState *dev, void *opaque) { device_legacy_reset(dev); @@ -XXX,XX +XXX,XX @@ static int qdev_reset_one(DeviceState *dev, void *opaque) static int qbus_reset_one(BusState *bus, void *opaque) { BusClass *bc = BUS_GET_CLASS(bus); + trace_qbus_reset(bus, object_get_typename(OBJECT(bus))); if (bc->reset) { bc->reset(bus); } @@ -XXX,XX +XXX,XX @@ static int qbus_reset_one(BusState *bus, void *opaque) void qdev_reset_all(DeviceState *dev) { - qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); + trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev))); + qdev_walk_children(dev, qdev_prereset, qbus_prereset, + qdev_reset_one, qbus_reset_one, NULL); } void qdev_reset_all_fn(void *opaque) @@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque) void qbus_reset_all(BusState *bus) { - qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); + trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus))); + qbus_walk_children(bus, qdev_prereset, qbus_prereset, + qdev_reset_one, qbus_reset_one, NULL); } void qbus_reset_all_fn(void *opaque) @@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev) { DeviceClass *klass = DEVICE_GET_CLASS(dev); + trace_qdev_reset(dev, object_get_typename(OBJECT(dev))); if (klass->reset) { klass->reset(dev); } diff --git a/hw/core/trace-events b/hw/core/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -XXX,XX +XXX,XX @@ # loader.c loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d" + +# qdev.c +qdev_reset(void *obj, const char *objtype) "obj=%p(%s)" +qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)" +qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" +qbus_reset(void *obj, const char *objtype) "obj=%p(%s)" +qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)" +qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" +qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> This commit defines an interface allowing multi-phase reset. This aims to solve a problem of the actual single-phase reset (built in DeviceClass and BusClass): reset behavior is dependent on the order in which reset handlers are called. In particular doing external side-effect (like setting an qemu_irq) is problematic because receiving object may not be reset yet. The Resettable interface divides the reset in 3 well defined phases. To reset an object tree, all 1st phases are executed then all 2nd then all 3rd. See the comments in include/hw/resettable.h for a more complete description. The interface defines 3 phases to let the future possibility of holding an object into reset for some time. The qdev/qbus reset in DeviceClass and BusClass will be modified in following commits to use this interface. A mechanism is provided to allow executing a transitional reset handler in place of the 2nd phase which is executed in children-then-parent order inside a tree. This will allow to transition devices and buses smoothly while keeping the exact current qdev/qbus reset behavior for now. Documentation will be added in a following commit. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/core/Makefile.objs | 1 + include/hw/resettable.h | 211 +++++++++++++++++++++++++++++++++++ hw/core/resettable.c | 238 ++++++++++++++++++++++++++++++++++++++++ hw/core/trace-events | 17 +++ 4 files changed, 467 insertions(+) create mode 100644 include/hw/resettable.h create mode 100644 hw/core/resettable.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-y += qdev.o qdev-properties.o common-obj-y += bus.o common-obj-y += cpu.o +common-obj-y += resettable.o common-obj-y += hotplug.o common-obj-y += vmstate-if.o # irq.o needed for qdev GPIO handling: diff --git a/include/hw/resettable.h b/include/hw/resettable.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/resettable.h @@ -XXX,XX +XXX,XX @@ +/* + * Resettable interface header. + * + * Copyright (c) 2019 GreenSocs SAS + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_RESETTABLE_H +#define HW_RESETTABLE_H + +#include "qom/object.h" + +#define TYPE_RESETTABLE_INTERFACE "resettable" + +#define RESETTABLE_CLASS(class) \ + OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE_INTERFACE) + +#define RESETTABLE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE) + +typedef struct ResettableState ResettableState; + +/** + * ResetType: + * Types of reset. + * + * + Cold: reset resulting from a power cycle of the object. + * + * TODO: Support has to be added to handle more types. In particular, + * ResettableState structure needs to be expanded. + */ +typedef enum ResetType { + RESET_TYPE_COLD, +} ResetType; + +/* + * ResettableClass: + * Interface for resettable objects. + * + * See docs/devel/reset.rst for more detailed information about how QEMU models + * reset. This whole API must only be used when holding the iothread mutex. + * + * All objects which can be reset must implement this interface; + * it is usually provided by a base class such as DeviceClass or BusClass. + * Every Resettable object must maintain some state tracking the + * progress of a reset operation by providing a ResettableState structure. + * The functions defined in this module take care of updating the + * state of the reset. + * The base class implementation of the interface provides this + * state and implements the associated method: get_state. + * + * Concrete object implementations (typically specific devices + * such as a UART model) should provide the functions + * for the phases.enter, phases.hold and phases.exit methods, which + * they can set in their class init function, either directly or + * by calling resettable_class_set_parent_phases(). + * The phase methods are guaranteed to only only ever be called once + * for any reset event, in the order 'enter', 'hold', 'exit'. + * An object will always move quickly from 'enter' to 'hold' + * but might remain in 'hold' for an arbitrary period of time + * before eventually reset is deasserted and the 'exit' phase is called. + * Object implementations should be prepared for functions handling + * inbound connections from other devices (such as qemu_irq handler + * functions) to be called at any point during reset after their + * 'enter' method has been called. + * + * Users of a resettable object should not call these methods + * directly, but instead use the function resettable_reset(). + * + * @phases.enter: This phase is called when the object enters reset. It + * should reset local state of the object, but it must not do anything that + * has a side-effect on other objects, such as raising or lowering a qemu_irq + * line or reading or writing guest memory. It takes the reset's type as + * argument. + * + * @phases.hold: This phase is called for entry into reset, once every object + * in the system which is being reset has had its @phases.enter method called. + * At this point devices can do actions that affect other objects. + * + * @phases.exit: This phase is called when the object leaves the reset state. + * Actions affecting other objects are permitted. + * + * @get_state: Mandatory method which must return a pointer to a + * ResettableState. + * + * @get_transitional_function: transitional method to handle Resettable objects + * not yet fully moved to this interface. It will be removed as soon as it is + * not needed anymore. This method is optional and may return a pointer to a + * function to be used instead of the phases. If the method exists and returns + * a non-NULL function pointer then that function is executed as a replacement + * of the 'hold' phase method taking the object as argument. The two other phase + * methods are not executed. + * + * @child_foreach: Executes a given callback on every Resettable child. Child + * in this context means a child in the qbus tree, so the children of a qbus + * are the devices on it, and the children of a device are all the buses it + * owns. This is not the same as the QOM object hierarchy. The function takes + * additional opaque and ResetType arguments which must be passed unmodified to + * the callback. + */ +typedef void (*ResettableEnterPhase)(Object *obj, ResetType type); +typedef void (*ResettableHoldPhase)(Object *obj); +typedef void (*ResettableExitPhase)(Object *obj); +typedef ResettableState * (*ResettableGetState)(Object *obj); +typedef void (*ResettableTrFunction)(Object *obj); +typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj); +typedef void (*ResettableChildCallback)(Object *, void *opaque, + ResetType type); +typedef void (*ResettableChildForeach)(Object *obj, + ResettableChildCallback cb, + void *opaque, ResetType type); +typedef struct ResettablePhases { + ResettableEnterPhase enter; + ResettableHoldPhase hold; + ResettableExitPhase exit; +} ResettablePhases; +typedef struct ResettableClass { + InterfaceClass parent_class; + + /* Phase methods */ + ResettablePhases phases; + + /* State access method */ + ResettableGetState get_state; + + /* Transitional method for legacy reset compatibility */ + ResettableGetTrFunction get_transitional_function; + + /* Hierarchy handling method */ + ResettableChildForeach child_foreach; +} ResettableClass; + +/** + * ResettableState: + * Structure holding reset related state. The fields should not be accessed + * directly; the definition is here to allow further inclusion into other + * objects. + * + * @count: Number of reset level the object is into. It is incremented when + * the reset operation starts and decremented when it finishes. + * @hold_phase_pending: flag which indicates that we need to invoke the 'hold' + * phase handler for this object. + * @exit_phase_in_progress: true if we are currently in the exit phase + */ +struct ResettableState { + unsigned count; + bool hold_phase_pending; + bool exit_phase_in_progress; +}; + +/** + * resettable_reset: + * Trigger a reset on an object @obj of type @type. @obj must implement + * Resettable interface. + * + * Calling this function is equivalent to calling @resettable_assert_reset() + * then @resettable_release_reset(). + */ +void resettable_reset(Object *obj, ResetType type); + +/** + * resettable_assert_reset: + * Put an object @obj into reset. @obj must implement Resettable interface. + * + * @resettable_release_reset() must eventually be called after this call. + * There must be one call to @resettable_release_reset() per call of + * @resettable_assert_reset(), with the same type argument. + * + * NOTE: Until support for migration is added, the @resettable_release_reset() + * must not be delayed. It must occur just after @resettable_assert_reset() so + * that migration cannot be triggered in between. Prefer using + * @resettable_reset() for now. + */ +void resettable_assert_reset(Object *obj, ResetType type); + +/** + * resettable_release_reset: + * Release the object @obj from reset. @obj must implement Resettable interface. + * + * See @resettable_assert_reset() description for details. + */ +void resettable_release_reset(Object *obj, ResetType type); + +/** + * resettable_is_in_reset: + * Return true if @obj is under reset. + * + * @obj must implement Resettable interface. + */ +bool resettable_is_in_reset(Object *obj); + +/** + * resettable_class_set_parent_phases: + * + * Save @rc current reset phases into @parent_phases and override @rc phases + * by the given new methods (@enter, @hold and @exit). + * Each phase is overridden only if the new one is not NULL allowing to + * override a subset of phases. + */ +void resettable_class_set_parent_phases(ResettableClass *rc, + ResettableEnterPhase enter, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_phases); + +#endif diff --git a/hw/core/resettable.c b/hw/core/resettable.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/core/resettable.c @@ -XXX,XX +XXX,XX @@ +/* + * Resettable interface. + * + * Copyright (c) 2019 GreenSocs SAS + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "hw/resettable.h" +#include "trace.h" + +/** + * resettable_phase_enter/hold/exit: + * Function executing a phase recursively in a resettable object and its + * children. + */ +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type); +static void resettable_phase_hold(Object *obj, void *opaque, ResetType type); +static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); + +/** + * enter_phase_in_progress: + * True if we are currently in reset enter phase. + * + * Note: This flag is only used to guarantee (using asserts) that the reset + * API is used correctly. We can use a global variable because we rely on the + * iothread mutex to ensure only one reset operation is in a progress at a + * given time. + */ +static bool enter_phase_in_progress; + +void resettable_reset(Object *obj, ResetType type) +{ + trace_resettable_reset(obj, type); + resettable_assert_reset(obj, type); + resettable_release_reset(obj, type); +} + +void resettable_assert_reset(Object *obj, ResetType type) +{ + /* TODO: change this assert when adding support for other reset types */ + assert(type == RESET_TYPE_COLD); + trace_resettable_reset_assert_begin(obj, type); + assert(!enter_phase_in_progress); + + enter_phase_in_progress = true; + resettable_phase_enter(obj, NULL, type); + enter_phase_in_progress = false; + + resettable_phase_hold(obj, NULL, type); + + trace_resettable_reset_assert_end(obj); +} + +void resettable_release_reset(Object *obj, ResetType type) +{ + /* TODO: change this assert when adding support for other reset types */ + assert(type == RESET_TYPE_COLD); + trace_resettable_reset_release_begin(obj, type); + assert(!enter_phase_in_progress); + + resettable_phase_exit(obj, NULL, type); + + trace_resettable_reset_release_end(obj); +} + +bool resettable_is_in_reset(Object *obj) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + + return s->count > 0; +} + +/** + * resettable_child_foreach: + * helper to avoid checking the existence of the method. + */ +static void resettable_child_foreach(ResettableClass *rc, Object *obj, + ResettableChildCallback cb, + void *opaque, ResetType type) +{ + if (rc->child_foreach) { + rc->child_foreach(obj, cb, opaque, type); + } +} + +/** + * resettable_get_tr_func: + * helper to fetch transitional reset callback if any. + */ +static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc, + Object *obj) +{ + ResettableTrFunction tr_func = NULL; + if (rc->get_transitional_function) { + tr_func = rc->get_transitional_function(obj); + } + return tr_func; +} + +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + const char *obj_typename = object_get_typename(obj); + bool action_needed = false; + + /* exit phase has to finish properly before entering back in reset */ + assert(!s->exit_phase_in_progress); + + trace_resettable_phase_enter_begin(obj, obj_typename, s->count, type); + + /* Only take action if we really enter reset for the 1st time. */ + /* + * TODO: if adding more ResetType support, some additional checks + * are probably needed here. + */ + if (s->count++ == 0) { + action_needed = true; + } + /* + * We limit the count to an arbitrary "big" value. The value is big + * enough not to be triggered normally. + * The assert will stop an infinite loop if there is a cycle in the + * reset tree. The loop goes through resettable_foreach_child below + * which at some point will call us again. + */ + assert(s->count <= 50); + + /* + * handle the children even if action_needed is at false so that + * child counts are incremented too + */ + resettable_child_foreach(rc, obj, resettable_phase_enter, NULL, type); + + /* execute enter phase for the object if needed */ + if (action_needed) { + trace_resettable_phase_enter_exec(obj, obj_typename, type, + !!rc->phases.enter); + if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) { + rc->phases.enter(obj, type); + } + s->hold_phase_pending = true; + } + trace_resettable_phase_enter_end(obj, obj_typename, s->count); +} + +static void resettable_phase_hold(Object *obj, void *opaque, ResetType type) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + const char *obj_typename = object_get_typename(obj); + + /* exit phase has to finish properly before entering back in reset */ + assert(!s->exit_phase_in_progress); + + trace_resettable_phase_hold_begin(obj, obj_typename, s->count, type); + + /* handle children first */ + resettable_child_foreach(rc, obj, resettable_phase_hold, NULL, type); + + /* exec hold phase */ + if (s->hold_phase_pending) { + s->hold_phase_pending = false; + ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj); + trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold); + if (tr_func) { + trace_resettable_transitional_function(obj, obj_typename); + tr_func(obj); + } else if (rc->phases.hold) { + rc->phases.hold(obj); + } + } + trace_resettable_phase_hold_end(obj, obj_typename, s->count); +} + +static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + const char *obj_typename = object_get_typename(obj); + + assert(!s->exit_phase_in_progress); + trace_resettable_phase_exit_begin(obj, obj_typename, s->count, type); + + /* exit_phase_in_progress ensures this phase is 'atomic' */ + s->exit_phase_in_progress = true; + resettable_child_foreach(rc, obj, resettable_phase_exit, NULL, type); + + assert(s->count > 0); + if (s->count == 1) { + trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); + if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) { + rc->phases.exit(obj); + } + s->count = 0; + } + s->exit_phase_in_progress = false; + trace_resettable_phase_exit_end(obj, obj_typename, s->count); +} + +void resettable_class_set_parent_phases(ResettableClass *rc, + ResettableEnterPhase enter, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_phases) +{ + *parent_phases = rc->phases; + if (enter) { + rc->phases.enter = enter; + } + if (hold) { + rc->phases.hold = hold; + } + if (exit) { + rc->phases.exit = exit; + } +} + +static const TypeInfo resettable_interface_info = { + .name = TYPE_RESETTABLE_INTERFACE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(ResettableClass), +}; + +static void reset_register_types(void) +{ + type_register_static(&resettable_interface_info); +} + +type_init(reset_register_types) diff --git a/hw/core/trace-events b/hw/core/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -XXX,XX +XXX,XX @@ qbus_reset(void *obj, const char *objtype) "obj=%p(%s)" qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)" qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" + +# resettable.c +resettable_reset(void *obj, int cold) "obj=%p cold=%d" +resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d" +resettable_reset_assert_end(void *obj) "obj=%p" +resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d" +resettable_reset_release_end(void *obj) "obj=%p" +resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" +resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d" +resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" +resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" +resettable_phase_hold_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" +resettable_phase_hold_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" +resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" +resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" +resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" +resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)" -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> This commit adds support of Resettable interface to buses and devices: + ResettableState structure is added in the Bus/Device state + Resettable methods are implemented. + device/bus_is_in_reset function defined This commit allows to transition the objects to the new multi-phase interface without changing the reset behavior at all. Object single reset method can be split into the 3 different phases but the 3 phases are still executed in a row for a given object. From the qdev/qbus reset api point of view, nothing is changed. qdev_reset_all() and qbus_reset_all() are not modified as well as device_legacy_reset(). Transition of an object must be done from parent class to child class. Care has been taken to allow the transition of a parent class without requiring the child classes to be transitioned at the same time. Note that SysBus and SysBusDevice class do not need any transition because they do not override the legacy reset method. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/Makefile.include | 1 + include/hw/qdev-core.h | 27 ++++++++++++ hw/core/bus.c | 97 ++++++++++++++++++++++++++++++++++++++++++ hw/core/qdev.c | 93 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 218 insertions(+) diff --git a/tests/Makefile.include b/tests/Makefile.include index XXXXXXX..XXXXXXX 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -XXX,XX +XXX,XX @@ tests/fp/%: tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ hw/core/bus.o \ + hw/core/resettable.o \ hw/core/irq.o \ hw/core/fw-path-provider.o \ hw/core/reset.o \ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -XXX,XX +XXX,XX @@ #include "qemu/bitmap.h" #include "qom/object.h" #include "hw/hotplug.h" +#include "hw/resettable.h" enum { DEV_NVECTORS_UNSPECIFIED = -1, @@ -XXX,XX +XXX,XX @@ typedef struct DeviceClass { bool hotpluggable; /* callbacks */ + /* + * Reset method here is deprecated and replaced by methods in the + * resettable class interface to implement a multi-phase reset. + * TODO: remove once every reset callback is unused + */ DeviceReset reset; DeviceRealize realize; DeviceUnrealize unrealize; @@ -XXX,XX +XXX,XX @@ struct NamedGPIOList { /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. + * @reset: ResettableState for the device; handled by Resettable interface. * * This structure should not be accessed directly. We declare it here * so that it can be embedded in individual device state structures. @@ -XXX,XX +XXX,XX @@ struct DeviceState { int num_child_bus; int instance_id_alias; int alias_required_for_version; + ResettableState reset; }; struct DeviceListener { @@ -XXX,XX +XXX,XX @@ typedef struct BusChild { /** * BusState: * @hotplug_handler: link to a hotplug handler associated with bus. + * @reset: ResettableState for the bus; handled by Resettable interface. */ struct BusState { Object obj; @@ -XXX,XX +XXX,XX @@ struct BusState { int num_children; QTAILQ_HEAD(, BusChild) children; QLIST_ENTRY(BusState) sibling; + ResettableState reset; }; /** @@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque); void qbus_reset_all(BusState *bus); void qbus_reset_all_fn(void *opaque); +/** + * device_is_in_reset: + * Return true if the device @dev is currently being reset. + */ +bool device_is_in_reset(DeviceState *dev); + +/** + * bus_is_in_reset: + * Return true if the bus @bus is currently being reset. + */ +bool bus_is_in_reset(BusState *bus); + /* This should go away once we get rid of the NULL bus hack */ BusState *sysbus_get_default(void); @@ -XXX,XX +XXX,XX @@ void device_legacy_reset(DeviceState *dev); void device_class_set_props(DeviceClass *dc, Property *props); +/** + * device_class_set_parent_reset: + * TODO: remove the function when DeviceClass's reset method + * is not used anymore. + */ void device_class_set_parent_reset(DeviceClass *dc, DeviceReset dev_reset, DeviceReset *parent_reset); diff --git a/hw/core/bus.c b/hw/core/bus.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus, return 0; } +bool bus_is_in_reset(BusState *bus) +{ + return resettable_is_in_reset(OBJECT(bus)); +} + +static ResettableState *bus_get_reset_state(Object *obj) +{ + BusState *bus = BUS(obj); + return &bus->reset; +} + +static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb, + void *opaque, ResetType type) +{ + BusState *bus = BUS(obj); + BusChild *kid; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + cb(OBJECT(kid->child), opaque, type); + } +} + static void qbus_realize(BusState *bus, DeviceState *parent, const char *name) { const char *typename = object_get_typename(OBJECT(bus)); @@ -XXX,XX +XXX,XX @@ static char *default_bus_get_fw_dev_path(DeviceState *dev) return g_strdup(object_get_typename(OBJECT(dev))); } +/** + * bus_phases_reset: + * Transition reset method for buses to allow moving + * smoothly from legacy reset method to multi-phases + */ +static void bus_phases_reset(BusState *bus) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(bus); + + if (rc->phases.enter) { + rc->phases.enter(OBJECT(bus), RESET_TYPE_COLD); + } + if (rc->phases.hold) { + rc->phases.hold(OBJECT(bus)); + } + if (rc->phases.exit) { + rc->phases.exit(OBJECT(bus)); + } +} + +static void bus_transitional_reset(Object *obj) +{ + BusClass *bc = BUS_GET_CLASS(obj); + + /* + * This will call either @bus_phases_reset (for multi-phases transitioned + * buses) or a bus's specific method for not-yet transitioned buses. + * In both case, it does not reset children. + */ + if (bc->reset) { + bc->reset(BUS(obj)); + } +} + +/** + * bus_get_transitional_reset: + * check if the bus's class is ready for multi-phase + */ +static ResettableTrFunction bus_get_transitional_reset(Object *obj) +{ + BusClass *dc = BUS_GET_CLASS(obj); + if (dc->reset != bus_phases_reset) { + /* + * dc->reset has been overridden by a subclass, + * the bus is not ready for multi phase yet. + */ + return bus_transitional_reset; + } + return NULL; +} + static void bus_class_init(ObjectClass *class, void *data) { BusClass *bc = BUS_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); class->unparent = bus_unparent; bc->get_fw_dev_path = default_bus_get_fw_dev_path; + + rc->get_state = bus_get_reset_state; + rc->child_foreach = bus_reset_child_foreach; + + /* + * @bus_phases_reset is put as the default reset method below, allowing + * to do the multi-phase transition from base classes to leaf classes. It + * allows a legacy-reset Bus class to extend a multi-phases-reset + * Bus class for the following reason: + * + If a base class B has been moved to multi-phase, then it does not + * override this default reset method and may have defined phase methods. + * + A child class C (extending class B) which uses + * bus_class_set_parent_reset() (or similar means) to override the + * reset method will still work as expected. @bus_phases_reset function + * will be registered as the parent reset method and effectively call + * parent reset phases. + */ + bc->reset = bus_phases_reset; + rc->get_transitional_function = bus_get_transitional_reset; } static void qbus_finalize(Object *obj) @@ -XXX,XX +XXX,XX @@ static const TypeInfo bus_info = { .instance_init = qbus_initfn, .instance_finalize = qbus_finalize, .class_init = bus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_RESETTABLE_INTERFACE }, + { } + }, }; static void bus_register_types(void) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque) qbus_reset_all(bus); } +bool device_is_in_reset(DeviceState *dev) +{ + return resettable_is_in_reset(OBJECT(dev)); +} + +static ResettableState *device_get_reset_state(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + return &dev->reset; +} + +static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb, + void *opaque, ResetType type) +{ + DeviceState *dev = DEVICE(obj); + BusState *bus; + + QLIST_FOREACH(bus, &dev->child_bus, sibling) { + cb(OBJECT(bus), opaque, type); + } +} + /* can be used as ->unplug() callback for the simple cases */ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ device_vmstate_if_get_id(VMStateIf *obj) return qdev_get_dev_path(dev); } +/** + * device_phases_reset: + * Transition reset method for devices to allow moving + * smoothly from legacy reset method to multi-phases + */ +static void device_phases_reset(DeviceState *dev) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(dev); + + if (rc->phases.enter) { + rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD); + } + if (rc->phases.hold) { + rc->phases.hold(OBJECT(dev)); + } + if (rc->phases.exit) { + rc->phases.exit(OBJECT(dev)); + } +} + +static void device_transitional_reset(Object *obj) +{ + DeviceClass *dc = DEVICE_GET_CLASS(obj); + + /* + * This will call either @device_phases_reset (for multi-phases transitioned + * devices) or a device's specific method for not-yet transitioned devices. + * In both case, it does not reset children. + */ + if (dc->reset) { + dc->reset(DEVICE(obj)); + } +} + +/** + * device_get_transitional_reset: + * check if the device's class is ready for multi-phase + */ +static ResettableTrFunction device_get_transitional_reset(Object *obj) +{ + DeviceClass *dc = DEVICE_GET_CLASS(obj); + if (dc->reset != device_phases_reset) { + /* + * dc->reset has been overridden by a subclass, + * the device is not ready for multi phase yet. + */ + return device_transitional_reset; + } + return NULL; +} + static void device_class_init(ObjectClass *class, void *data) { DeviceClass *dc = DEVICE_CLASS(class); VMStateIfClass *vc = VMSTATE_IF_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); class->unparent = device_unparent; @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) dc->hotpluggable = true; dc->user_creatable = true; vc->get_id = device_vmstate_if_get_id; + rc->get_state = device_get_reset_state; + rc->child_foreach = device_reset_child_foreach; + + /* + * @device_phases_reset is put as the default reset method below, allowing + * to do the multi-phase transition from base classes to leaf classes. It + * allows a legacy-reset Device class to extend a multi-phases-reset + * Device class for the following reason: + * + If a base class B has been moved to multi-phase, then it does not + * override this default reset method and may have defined phase methods. + * + A child class C (extending class B) which uses + * device_class_set_parent_reset() (or similar means) to override the + * reset method will still work as expected. @device_phases_reset function + * will be registered as the parent reset method and effectively call + * parent reset phases. + */ + dc->reset = device_phases_reset; + rc->get_transitional_function = device_get_transitional_reset; object_class_property_add_bool(class, "realized", device_get_realized, device_set_realized, @@ -XXX,XX +XXX,XX @@ static const TypeInfo device_type_info = { .class_size = sizeof(DeviceClass), .interfaces = (InterfaceInfo[]) { { TYPE_VMSTATE_IF }, + { TYPE_RESETTABLE_INTERFACE }, { } } }; -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Add a function resettable_change_parent() to do the required plumbing when changing the parent a of Resettable object. We need to make sure that the reset state of the object remains coherent with the reset state of the new parent. We make the 2 following hypothesis: + when an object is put in a parent under reset, the object goes in reset. + when an object is removed from a parent under reset, the object leaves reset. The added function avoids any glitch if both old and new parent are already in reset. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/resettable.h | 16 +++++++++++ hw/core/resettable.c | 62 +++++++++++++++++++++++++++++++++++++++-- hw/core/trace-events | 1 + 3 files changed, 77 insertions(+), 2 deletions(-) diff --git a/include/hw/resettable.h b/include/hw/resettable.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type); */ bool resettable_is_in_reset(Object *obj); +/** + * resettable_change_parent: + * Indicate that the parent of Ressettable @obj is changing from @oldp to @newp. + * All 3 objects must implement resettable interface. @oldp or @newp may be + * NULL. + * + * This function will adapt the reset state of @obj so that it is coherent + * with the reset state of @newp. It may trigger @resettable_assert_reset() + * or @resettable_release_reset(). It will do such things only if the reset + * state of @newp and @oldp are different. + * + * When using this function during reset, it must only be called during + * a hold phase method. Calling this during enter or exit phase is an error. + */ +void resettable_change_parent(Object *obj, Object *newp, Object *oldp); + /** * resettable_class_set_parent_phases: * diff --git a/hw/core/resettable.c b/hw/core/resettable.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/resettable.c +++ b/hw/core/resettable.c @@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); * enter_phase_in_progress: * True if we are currently in reset enter phase. * - * Note: This flag is only used to guarantee (using asserts) that the reset - * API is used correctly. We can use a global variable because we rely on the + * exit_phase_in_progress: + * count the number of exit phase we are in. + * + * Note: These flags are only used to guarantee (using asserts) that the reset + * API is used correctly. We can use global variables because we rely on the * iothread mutex to ensure only one reset operation is in a progress at a * given time. */ static bool enter_phase_in_progress; +static unsigned exit_phase_in_progress; void resettable_reset(Object *obj, ResetType type) { @@ -XXX,XX +XXX,XX @@ void resettable_release_reset(Object *obj, ResetType type) trace_resettable_reset_release_begin(obj, type); assert(!enter_phase_in_progress); + exit_phase_in_progress += 1; resettable_phase_exit(obj, NULL, type); + exit_phase_in_progress -= 1; trace_resettable_reset_release_end(obj); } @@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) trace_resettable_phase_exit_end(obj, obj_typename, s->count); } +/* + * resettable_get_count: + * Get the count of the Resettable object @obj. Return 0 if @obj is NULL. + */ +static unsigned resettable_get_count(Object *obj) +{ + if (obj) { + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + return rc->get_state(obj)->count; + } + return 0; +} + +void resettable_change_parent(Object *obj, Object *newp, Object *oldp) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + unsigned newp_count = resettable_get_count(newp); + unsigned oldp_count = resettable_get_count(oldp); + + /* + * Ensure we do not change parent when in enter or exit phase. + * During these phases, the reset subtree being updated is partly in reset + * and partly not in reset (it depends on the actual position in + * resettable_child_foreach()s). We are not able to tell in which part is a + * leaving or arriving device. Thus we cannot set the reset count of the + * moving device to the proper value. + */ + assert(!enter_phase_in_progress && !exit_phase_in_progress); + trace_resettable_change_parent(obj, oldp, oldp_count, newp, newp_count); + + /* + * At most one of the two 'for' loops will be executed below + * in order to cope with the difference between the two counts. + */ + /* if newp is more reset than oldp */ + for (unsigned i = oldp_count; i < newp_count; i++) { + resettable_assert_reset(obj, RESET_TYPE_COLD); + } + /* + * if obj is leaving a bus under reset, we need to ensure + * hold phase is not pending. + */ + if (oldp_count && s->hold_phase_pending) { + resettable_phase_hold(obj, NULL, RESET_TYPE_COLD); + } + /* if oldp is more reset than newp */ + for (unsigned i = newp_count; i < oldp_count; i++) { + resettable_release_reset(obj, RESET_TYPE_COLD); + } +} + void resettable_class_set_parent_phases(ResettableClass *rc, ResettableEnterPhase enter, ResettableHoldPhase hold, diff --git a/hw/core/trace-events b/hw/core/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -XXX,XX +XXX,XX @@ resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d" resettable_reset_assert_end(void *obj) "obj=%p" resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d" resettable_reset_release_end(void *obj) "obj=%p" +resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc) "obj=%p from=%p(%d) to=%p(%d)" resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d" resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> In qdev_set_parent_bus(), when changing the parent bus of a realized device, if the source and destination buses are not in the same reset state, some adaptations are required. This patch adds needed call to resettable_change_parent() to make sure a device reset state stays coherent with its parent bus. The addition is a no-op if: 1. the device being parented is not realized. 2. the device is realized, but both buses are not under reset. Case 2 means that as long as qdev_set_parent_bus() is called during the machine realization procedure (which is before the machine reset so nothing is in reset), it is a no op. There are 52 call sites of qdev_set_parent_bus(). All but one fall into the no-op case: + 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/ {vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device parent bus just before realizing the same vdev(vgpu). + hw/core/qdev.c: when creating a device in qdev_try_create() + hw/core/sysbus.c: when initializing a device in the sysbus + hw/i386/amd_iommu.c: before realizing AMDVIState/pci + hw/isa/piix4.c: before realizing PIIX4State/rtc + hw/misc/auxbus.c: when creating an AUXBus + hw/misc/auxbus.c: when creating an AUXBus child + hw/misc/macio/macio.c: when initializing a MACIOState child + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda + hw/net/virtio-net.c: Used for migration when using the failover mechanism to migration a vfio-pci/net. It is a no-op because at this point the device is already on the bus. + hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root + hw/pci-host/gpex.c: before realizing GPEXHost/root + hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev + hw/pci-host/q35.c: before realizing Q35PCIHost/mch + hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev + hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root + hw/s390x/event-facility.c: when creating SCLPEventFacility/ TYPE_SCLP_QUIESCE + hw/s390x/event-facility.c: ditto with SCLPEventFacility/ TYPE_SCLP_CPU_HOTPLUG + hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice just after realizing it. Ok because at this point the destination bus (sysbus) is not in reset; the realize step is before the machine reset. + hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below. + hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs line in ssi_auto_connect_slave(). Ok because this function is only used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c, hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c. + hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device + qdev-monitor.c: in device hotplug creation procedure before realize Note that this commit alone will have no effect, right now there is no use of resettable API to reset anything. So a bus will never be tagged as in-reset by this same API. The one place where side-effect will occurs is in hw/sd/core.c in sdbus_reparent_card(). This function is only used in the raspi machines, including during the sysbus reset procedure. This case will be carrefully handled when doing the multiple phase reset transition. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/core/qdev.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child) void qdev_set_parent_bus(DeviceState *dev, BusState *bus) { - bool replugging = dev->parent_bus != NULL; + BusState *old_parent_bus = dev->parent_bus; - if (replugging) { + if (old_parent_bus) { trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)), - dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)), + old_parent_bus, object_get_typename(OBJECT(old_parent_bus)), OBJECT(bus), object_get_typename(OBJECT(bus))); /* * Keep a reference to the device while it's not plugged into * any bus, to avoid it potentially evaporating when it is * dereffed in bus_remove_child(). + * Also keep the ref of the parent bus until the end, so that + * we can safely call resettable_change_parent() below. */ object_ref(OBJECT(dev)); bus_remove_child(dev->parent_bus, dev); - object_unref(OBJECT(dev->parent_bus)); } dev->parent_bus = bus; object_ref(OBJECT(bus)); bus_add_child(bus, dev); - if (replugging) { + if (dev->realized) { + resettable_change_parent(OBJECT(dev), OBJECT(bus), + OBJECT(old_parent_bus)); + } + if (old_parent_bus) { + object_unref(OBJECT(old_parent_bus)); object_unref(OBJECT(dev)); } } -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> This commit make use of the resettable API to reset the device being hotplugged when it is realized. Also it ensures it is put in a reset state coherent with the parent it is plugged into. Note that there is a difference in the reset. Instead of resetting only the hotplugged device, we reset also its subtree (switch to resettable API). This is not expected to be a problem because sub-buses are just realized too. If a hotplugged device has any sub-buses it is logical to reset them too at this point. The recently added should_be_hidden and PCI's partially_hotplugged mechanisms do not interfere with realize operation: + In the should_be_hidden use case, device creation is delayed. + The partially_hotplugged mechanism prevents a device to be unplugged and unrealized from qdev POV and unrealized. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/resettable.h | 11 +++++++++++ hw/core/qdev.c | 15 ++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/hw/resettable.h b/include/hw/resettable.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -XXX,XX +XXX,XX @@ struct ResettableState { bool exit_phase_in_progress; }; +/** + * resettable_state_clear: + * Clear the state. It puts the state to the initial (zeroed) state required + * to reuse an object. Typically used in realize step of base classes + * implementing the interface. + */ +static inline void resettable_state_clear(ResettableState *state) +{ + memset(state, 0, sizeof(ResettableState)); +} + /** * resettable_reset: * Trigger a reset on an object @obj of type @type. @obj must implement diff --git a/hw/core/qdev.c b/hw/core/qdev.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) } } + /* + * Clear the reset state, in case the object was previously unrealized + * with a dirty state. + */ + resettable_state_clear(&dev->reset); + QLIST_FOREACH(bus, &dev->child_bus, sibling) { object_property_set_bool(OBJECT(bus), true, "realized", &local_err); @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) } } if (dev->hotplugged) { - device_legacy_reset(dev); + /* + * Reset the device, as well as its subtree which, at this point, + * should be realized too. + */ + resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD); + resettable_change_parent(OBJECT(dev), OBJECT(dev->parent_bus), + NULL); + resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD); } dev->pending_deleted_event = false; -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Deprecate device_legacy_reset(), qdev_reset_all() and qbus_reset_all() to be replaced by new functions device_cold_reset() and bus_cold_reset() which uses resettable API. Also introduce resettable_cold_reset_fn() which may be used as a replacement for qdev_reset_all_fn and qbus_reset_all_fn(). Following patches will be needed to look at legacy reset call sites and switch to resettable api. The legacy functions will be removed when unused. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/qdev-core.h | 27 +++++++++++++++++++++++++++ include/hw/resettable.h | 9 +++++++++ hw/core/bus.c | 5 +++++ hw/core/qdev.c | 5 +++++ hw/core/resettable.c | 5 +++++ 5 files changed, 51 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -XXX,XX +XXX,XX @@ int qdev_walk_children(DeviceState *dev, qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn, void *opaque); +/** + * @qdev_reset_all: + * Reset @dev. See @qbus_reset_all() for more details. + * + * Note: This function is deprecated and will be removed when it becomes unused. + * Please use device_cold_reset() now. + */ void qdev_reset_all(DeviceState *dev); void qdev_reset_all_fn(void *opaque); @@ -XXX,XX +XXX,XX @@ void qdev_reset_all_fn(void *opaque); * hard reset means that qbus_reset_all will reset all state of the device. * For PCI devices, for example, this will include the base address registers * or configuration space. + * + * Note: This function is deprecated and will be removed when it becomes unused. + * Please use bus_cold_reset() now. */ void qbus_reset_all(BusState *bus); void qbus_reset_all_fn(void *opaque); +/** + * device_cold_reset: + * Reset device @dev and perform a recursive processing using the resettable + * interface. It triggers a RESET_TYPE_COLD. + */ +void device_cold_reset(DeviceState *dev); + +/** + * bus_cold_reset: + * + * Reset bus @bus and perform a recursive processing using the resettable + * interface. It triggers a RESET_TYPE_COLD. + */ +void bus_cold_reset(BusState *bus); + /** * device_is_in_reset: * Return true if the device @dev is currently being reset. @@ -XXX,XX +XXX,XX @@ void qdev_machine_init(void); * device_legacy_reset: * * Reset a single device (by calling the reset method). + * Note: This function is deprecated and will be removed when it becomes unused. + * Please use device_cold_reset() now. */ void device_legacy_reset(DeviceState *dev); diff --git a/include/hw/resettable.h b/include/hw/resettable.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -XXX,XX +XXX,XX @@ bool resettable_is_in_reset(Object *obj); */ void resettable_change_parent(Object *obj, Object *newp, Object *oldp); +/** + * resettable_cold_reset_fn: + * Helper to call resettable_reset((Object *) opaque, RESET_TYPE_COLD). + * + * This function is typically useful to register a reset handler with + * qemu_register_reset. + */ +void resettable_cold_reset_fn(void *opaque); + /** * resettable_class_set_parent_phases: * diff --git a/hw/core/bus.c b/hw/core/bus.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -XXX,XX +XXX,XX @@ int qbus_walk_children(BusState *bus, return 0; } +void bus_cold_reset(BusState *bus) +{ + resettable_reset(OBJECT(bus), RESET_TYPE_COLD); +} + bool bus_is_in_reset(BusState *bus) { return resettable_is_in_reset(OBJECT(bus)); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -XXX,XX +XXX,XX @@ void qbus_reset_all_fn(void *opaque) qbus_reset_all(bus); } +void device_cold_reset(DeviceState *dev) +{ + resettable_reset(OBJECT(dev), RESET_TYPE_COLD); +} + bool device_is_in_reset(DeviceState *dev) { return resettable_is_in_reset(OBJECT(dev)); diff --git a/hw/core/resettable.c b/hw/core/resettable.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/resettable.c +++ b/hw/core/resettable.c @@ -XXX,XX +XXX,XX @@ void resettable_change_parent(Object *obj, Object *newp, Object *oldp) } } +void resettable_cold_reset_fn(void *opaque) +{ + resettable_reset((Object *) opaque, RESET_TYPE_COLD); +} + void resettable_class_set_parent_phases(ResettableClass *rc, ResettableEnterPhase enter, ResettableHoldPhase hold, -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200123132823.1117486-10-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- docs/devel/index.rst | 1 + docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 290 insertions(+) create mode 100644 docs/devel/reset.rst diff --git a/docs/devel/index.rst b/docs/devel/index.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -XXX,XX +XXX,XX @@ Contents: tcg tcg-plugins bitops + reset diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/docs/devel/reset.rst @@ -XXX,XX +XXX,XX @@ + +======================================= +Reset in QEMU: the Resettable interface +======================================= + +The reset of qemu objects is handled using the resettable interface declared +in ``include/hw/resettable.h``. + +This interface allows objects to be grouped (on a tree basis); so that the +whole group can be reset consistently. Each individual member object does not +have to care about others; in particular, problems of order (which object is +reset first) are addressed. + +As of now DeviceClass and BusClass implement this interface. + + +Triggering reset +---------------- + +This section documents the APIs which "users" of a resettable object should use +to control it. All resettable control functions must be called while holding +the iothread lock. + +You can apply a reset to an object using ``resettable_assert_reset()``. You need +to call ``resettable_release_reset()`` to release the object from reset. To +instantly reset an object, without keeping it in reset state, just call +``resettable_reset()``. These functions take two parameters: a pointer to the +object to reset and a reset type. + +Several types of reset will be supported. For now only cold reset is defined; +others may be added later. The Resettable interface handles reset types with an +enum: + +``RESET_TYPE_COLD`` + Cold reset is supported by every resettable object. In QEMU, it means we reset + to the initial state corresponding to the start of QEMU; this might differ + from what is a real hardware cold reset. It differs from other resets (like + warm or bus resets) which may keep certain parts untouched. + +Calling ``resettable_reset()`` is equivalent to calling +``resettable_assert_reset()`` then ``resettable_release_reset()``. It is +possible to interleave multiple calls to these three functions. There may +be several reset sources/controllers of a given object. The interface handles +everything and the different reset controllers do not need to know anything +about each others. The object will leave reset state only when each other +controllers end their reset operation. This point is handled internally by +maintaining a count of in-progress resets; it is crucial to call +``resettable_release_reset()`` one time and only one time per +``resettable_assert_reset()`` call. + +For now migration of a device or bus in reset is not supported. Care must be +taken not to delay ``resettable_release_reset()`` after its +``resettable_assert_reset()`` counterpart. + +Note that, since resettable is an interface, the API takes a simple Object as +parameter. Still, it is a programming error to call a resettable function on a +non-resettable object and it will trigger a run time assert error. Since most +calls to resettable interface are done through base class functions, such an +error is not likely to happen. + +For Devices and Buses, the following helper functions exist: + +- ``device_cold_reset()`` +- ``bus_cold_reset()`` + +These are simple wrappers around resettable_reset() function; they only cast the +Device or Bus into an Object and pass the cold reset type. When possible +prefer to use these functions instead of ``resettable_reset()``. + +Device and bus functions co-exist because there can be semantic differences +between resetting a bus and resetting the controller bridge which owns it. +For example, consider a SCSI controller. Resetting the controller puts all +its registers back to what reset state was as well as reset everything on the +SCSI bus, whereas resetting just the SCSI bus only resets everything that's on +it but not the controller. + + +Multi-phase mechanism +--------------------- + +This section documents the internals of the resettable interface. + +The resettable interface uses a multi-phase system to relieve objects and +machines from reset ordering problems. To address this, the reset operation +of an object is split into three well defined phases. + +When resetting several objects (for example the whole machine at simulation +startup), all first phases of all objects are executed, then all second phases +and then all third phases. + +The three phases are: + +1. The **enter** phase is executed when the object enters reset. It resets only + local state of the object; it must not do anything that has a side-effect + on other objects, such as raising or lowering a qemu_irq line or reading or + writing guest memory. + +2. The **hold** phase is executed for entry into reset, once every object in the + group which is being reset has had its *enter* phase executed. At this point + devices can do actions that affect other objects. + +3. The **exit** phase is executed when the object leaves the reset state. + Actions affecting other objects are permitted. + +As said in previous section, the interface maintains a count of reset. This +count is used to ensure phases are executed only when required. *enter* and +*hold* phases are executed only when asserting reset for the first time +(if an object is already in reset state when calling +``resettable_assert_reset()`` or ``resettable_reset()``, they are not +executed). +The *exit* phase is executed only when the last reset operation ends. Therefore +the object does not need to care how many of reset controllers it has and how +many of them have started a reset. + + +Handling reset in a resettable object +------------------------------------- + +This section documents the APIs that an implementation of a resettable object +must provide and what functions it has access to. It is intended for people +who want to implement or convert a class which has the resettable interface; +for example when specializing an existing device or bus. + +Methods to implement +.................... + +Three methods should be defined or left empty. Each method corresponds to a +phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and +``phases.exit()``. They all take the object as parameter. The *enter* method +also take the reset type as second parameter. + +When extending an existing class, these methods may need to be extended too. +The ``resettable_class_set_parent_phases()`` class function may be used to +backup parent class methods. + +Here follows an example to implement reset for a Device which sets an IO while +in reset. + +:: + + static void mydev_reset_enter(Object *obj, ResetType type) + { + MyDevClass *myclass = MYDEV_GET_CLASS(obj); + MyDevState *mydev = MYDEV(obj); + /* call parent class enter phase */ + if (myclass->parent_phases.enter) { + myclass->parent_phases.enter(obj, type); + } + /* initialize local state only */ + mydev->var = 0; + } + + static void mydev_reset_hold(Object *obj) + { + MyDevClass *myclass = MYDEV_GET_CLASS(obj); + MyDevState *mydev = MYDEV(obj); + /* call parent class hold phase */ + if (myclass->parent_phases.hold) { + myclass->parent_phases.hold(obj); + } + /* set an IO */ + qemu_set_irq(mydev->irq, 1); + } + + static void mydev_reset_exit(Object *obj) + { + MyDevClass *myclass = MYDEV_GET_CLASS(obj); + MyDevState *mydev = MYDEV(obj); + /* call parent class exit phase */ + if (myclass->parent_phases.exit) { + myclass->parent_phases.exit(obj); + } + /* clear an IO */ + qemu_set_irq(mydev->irq, 0); + } + + typedef struct MyDevClass { + MyParentClass parent_class; + /* to store eventual parent reset methods */ + ResettablePhases parent_phases; + } MyDevClass; + + static void mydev_class_init(ObjectClass *class, void *data) + { + MyDevClass *myclass = MYDEV_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); + resettable_class_set_parent_reset_phases(rc, + mydev_reset_enter, + mydev_reset_hold, + mydev_reset_exit, + &myclass->parent_phases); + } + +In the above example, we override all three phases. It is possible to override +only some of them by passing NULL instead of a function pointer to +``resettable_class_set_parent_reset_phases()``. For example, the following will +only override the *enter* phase and leave *hold* and *exit* untouched:: + + resettable_class_set_parent_reset_phases(rc, mydev_reset_enter, + NULL, NULL, + &myclass->parent_phases); + +This is equivalent to providing a trivial implementation of the hold and exit +phases which does nothing but call the parent class's implementation of the +phase. + +Polling the reset state +....................... + +Resettable interface provides the ``resettable_is_in_reset()`` function. +This function returns true if the object parameter is currently under reset. + +An object is under reset from the beginning of the *init* phase to the end of +the *exit* phase. During all three phases, the function will return that the +object is in reset. + +This function may be used if the object behavior has to be adapted +while in reset state. For example if a device has an irq input, +it will probably need to ignore it while in reset; then it can for +example check the reset state at the beginning of the irq callback. + +Note that until migration of the reset state is supported, an object +should not be left in reset. So apart from being currently executing +one of the reset phases, the only cases when this function will return +true is if an external interaction (like changing an io) is made during +*hold* or *exit* phase of another object in the same reset group. + +Helpers ``device_is_in_reset()`` and ``bus_is_in_reset()`` are also provided +for devices and buses and should be preferred. + + +Base class handling of reset +---------------------------- + +This section documents parts of the reset mechanism that you only need to know +about if you are extending it to work with a new base class other than +DeviceClass or BusClass, or maintaining the existing code in those classes. Most +people can ignore it. + +Methods to implement +.................... + +There are two other methods that need to exist in a class implementing the +interface: ``get_state()`` and ``child_foreach()``. + +``get_state()`` is simple. *resettable* is an interface and, as a consequence, +does not have any class state structure. But in order to factorize the code, we +need one. This method must return a pointer to ``ResettableState`` structure. +The structure must be allocated by the base class; preferably it should be +located inside the object instance structure. + +``child_foreach()`` is more complex. It should execute the given callback on +every reset child of the given resettable object. All children must be +resettable too. Additional parameters (a reset type and an opaque pointer) must +be passed to the callback too. + +In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located +``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented +to follow the bus hierarchy; for a bus, it calls the function on every child +device; for a device, it calls the function on every bus child. When we reset +the main system bus, we reset the whole machine bus tree. + +Changing a resettable parent +............................ + +One thing which should be taken care of by the base class is handling reset +hierarchy changes. + +The reset hierarchy is supposed to be static and built during machine creation. +But there are actually some exceptions. To cope with this, the resettable API +provides ``resettable_change_parent()``. This function allows to set, update or +remove the parent of a resettable object after machine creation is done. As +parameters, it takes the object being moved, the old parent if any and the new +parent if any. + +This function can be used at any time when not in a reset operation. During +a reset operation it must be used only in *hold* phase. Using it in *enter* or +*exit* phase is an error. +Also it should not be used during machine creation, although it is harmless to +do so: the function is a no-op as long as old and new parent are NULL or not +in reset. + +There is currently 2 cases where this function is used: + +1. *device hotplug*; it means a new device is introduced on a live bus. + +2. *hot bus change*; it means an existing live device is added, moved or + removed in the bus hierarchy. At the moment, it occurs only in the raspi + machines for changing the sdbus used by sd card. -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Replace deprecated qbus_reset_all by resettable_cold_reset_fn for the sysbus reset registration. Apart for the raspi machines, this does not impact the behavior because: + at this point resettable just calls the old reset methods of devices and buses in the same order as qdev/qbus. + resettable handlers registered with qemu_register_reset are serialized; there is no interleaving. + eventual explicit calls to legacy reset API (device_reset or qdev/qbus_reset) inside this reset handler will not be masked out by resettable mechanism; they do not go through resettable api. For the raspi machines, during the sysbus reset the sd-card is not reset twice anymore but only once. This is a consequence of switching both sysbus reset and changing parent to resettable; it detects the second reset is not needed. This has no impact on the state after reset; the sd-card reset method only reset local state and query information from the block backend. The raspi reset change can be observed by using the following command (reset will occurs, then do Ctrl-C to end qemu; no firmware is given here). qemu-system-aarch64 -M raspi3 \ -trace resettable_phase_hold_exec \ -trace qdev_update_parent_bus \ -trace resettable_change_parent \ -trace qdev_reset -trace qbus_reset Before the patch, the qdev/qbus_reset traces show when reset method are called. After the patch, the resettable_phase_hold_exec show when reset method are called. The traced reset order of the raspi3 is listed below. I've added empty lines and the tree structure. +->bcm2835-peripherals reset | | +->sd-card reset | +->sd-bus reset +->bcm2835_gpio reset | -> dev_update_parent_bus (move the sd-card on the sdhci-bus) | -> resettable_change_parent | +->bcm2835-dma reset | | +->bcm2835-sdhost-bus reset +->bcm2835-sdhost reset | | +->sd-card (reset ONLY BEFORE BEFORE THE PATCH) | +->sdhci-bus reset +->generic-sdhci reset | +->bcm2835-rng reset +->bcm2835-property reset +->bcm2835-fb reset +->bcm2835-mbox reset +->bcm2835-aux reset +->pl011 reset +->bcm2835-ic reset +->bcm2836-control reset System reset In both case, the sd-card is reset (being on bcm2835_gpio/sd-bus) then moved to generic-sdhci/sdhci-bus by the bcm2835_gpio reset method. Before the patch, it is then reset again being part of generic-sdhci/sdhci-bus. After the patch, it considered again for reset but its reset method is not called because it is already flagged as reset. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200123132823.1117486-11-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- vl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/vl.c b/vl.c index XXXXXXX..XXXXXXX 100644 --- a/vl.c +++ b/vl.c @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp) /* TODO: once all bus devices are qdevified, this should be done * when bus is created by qdev.c */ - qemu_register_reset(qbus_reset_all_fn, sysbus_get_default()); + /* + * TODO: If we had a main 'reset container' that the whole system + * lived in, we could reset that using the multi-phase reset + * APIs. For the moment, we just reset the sysbus, which will cause + * all devices hanging off it (and all their child buses, recursively) + * to be reset. Note that this will *not* reset any Device objects + * which are not attached to some part of the qbus tree! + */ + qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); qemu_run_machine_init_done_notifiers(); if (rom_check_and_register_reset() != 0) { -- 2.20.1 From: Damien Hedde <damien.hedde@greensocs.com> Replace deprecated qdev_reset_all by resettable_cold_reset_fn for the ipl registration in the main reset handlers. This does not impact the behavior for the following reasons: + at this point resettable just call the old reset methods of devices and buses in the same order than qdev/qbus. + resettable handlers registered with qemu_register_reset are serialized; there is no interleaving. + eventual explicit calls to legacy reset API (device_reset or qdev/qbus_reset) inside this reset handler will not be masked out by resettable mechanism; they do not go through resettable api. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/s390x/ipl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index XXXXXXX..XXXXXXX 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -XXX,XX +XXX,XX @@ static void s390_ipl_realize(DeviceState *dev, Error **errp) */ ipl->compat_start_addr = ipl->start_addr; ipl->compat_bios_start_addr = ipl->bios_start_addr; - qemu_register_reset(qdev_reset_all_fn, dev); + /* + * Because this Device is not on any bus in the qbus tree (it is + * not a sysbus device and it's not on some other bus like a PCI + * bus) it will not be automatically reset by the 'reset the + * sysbus' hook registered by vl.c like most devices. So we must + * manually register a reset hook for it. + * TODO: there should be a better way to do this. + */ + qemu_register_reset(resettable_cold_reset_fn, dev); error: error_propagate(errp, err); } -- 2.20.1 From: Zenghui Yu <yuzenghui@huawei.com> If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when restoring GICR_CTLR. Setting PTZ here makes littlt sense in "reduce GIC initialization time". And what's worse, PTZ is generally programmed by guest to indicate to the Redistributor whether the LPI Pending table is zero when enabling LPIs. If migration is triggered when the PTZ has just been cleared by guest (and before enabling LPIs), we will see PTZ==1 on the destination side, which is not as expected. Let's just drop this hackish userspace behavior. Also take this chance to refine the comment a bit. Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions") Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20200119133051.642-1-yuzenghui@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/intc/arm_gicv3_kvm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicd_access(s, GICD_CTLR, &reg, true); if (redist_typer & GICR_TYPER_PLPIS) { - /* Set base addresses before LPIs are enabled by GICR_CTLR write */ + /* + * Restore base addresses before LPIs are potentially enabled by + * GICR_CTLR write + */ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { GICv3CPUState *c = &s->cpu[ncpu]; @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true); reg64 = c->gicr_pendbaser; - if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { - /* Setting PTZ is advised if LPIs are disabled, to reduce - * GIC initialization time. - */ - reg64 |= GICR_PENDBASER_PTZ; - } regl = (uint32_t)reg64; kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true); regh = (uint32_t)(reg64 >> 32); -- 2.20.1 From: Andrew Jones <drjones@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20200120101023.16030-2-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/kvm_arm.h | 46 ++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs); /** - * kvm_arm_vcpu_finalize + * kvm_arm_vcpu_finalize: * @cs: CPUState - * @feature: int + * @feature: feature to finalize * * Finalizes the configuration of the specified VCPU feature by * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring @@ -XXX,XX +XXX,XX @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, int kvm_arm_init_cpreg_list(ARMCPU *cpu); /** - * kvm_arm_reg_syncs_via_cpreg_list - * regidx: KVM register index + * kvm_arm_reg_syncs_via_cpreg_list: + * @regidx: KVM register index * * Return true if this KVM register should be synchronized via the * cpreg list of arbitrary system registers, false if it is synchronized @@ -XXX,XX +XXX,XX @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu); bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); /** - * kvm_arm_cpreg_level - * regidx: KVM register index + * kvm_arm_cpreg_level: + * @regidx: KVM register index * * Return the level of this coprocessor/system register. Return value is * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. @@ -XXX,XX +XXX,XX @@ void kvm_arm_init_serror_injection(CPUState *cs); * @cpu: ARMCPU * * Get VCPU related state from kvm. + * + * Returns: 0 if success else < 0 error code */ int kvm_get_vcpu_events(ARMCPU *cpu); @@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu); * @cpu: ARMCPU * * Put VCPU related state to kvm. + * + * Returns: 0 if success else < 0 error code */ int kvm_put_vcpu_events(ARMCPU *cpu); @@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures { /** * kvm_arm_get_host_cpu_features: - * @ahcc: ARMHostCPUClass to fill in + * @ahcf: ARMHostCPUClass to fill in * * Probe the capabilities of the host kernel's preferred CPU and fill * in the ARMHostCPUClass struct accordingly. + * + * Returns true on success and false otherwise. */ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); bool kvm_arm_aarch32_supported(CPUState *cs); /** - * bool kvm_arm_pmu_supported: + * kvm_arm_pmu_supported: * @cs: CPUState * * Returns: true if the KVM VCPU can enable its PMU @@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs); bool kvm_arm_pmu_supported(CPUState *cs); /** - * bool kvm_arm_sve_supported: + * kvm_arm_sve_supported: * @cs: CPUState * * Returns true if the KVM VCPU can enable SVE and false otherwise. @@ -XXX,XX +XXX,XX @@ bool kvm_arm_pmu_supported(CPUState *cs); bool kvm_arm_sve_supported(CPUState *cs); /** - * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the - * IPA address space supported by KVM - * + * kvm_arm_get_max_vm_ipa_size: * @ms: Machine state handle + * + * Returns the number of bits in the IPA address space supported by KVM */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms); /** - * kvm_arm_sync_mpstate_to_kvm + * kvm_arm_sync_mpstate_to_kvm: * @cpu: ARMCPU * * If supported set the KVM MP_STATE based on QEMU's model. + * + * Returns 0 on success and -1 on failure. */ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); /** - * kvm_arm_sync_mpstate_to_qemu + * kvm_arm_sync_mpstate_to_qemu: * @cpu: ARMCPU * * If supported get the MP_STATE from KVM and store in QEMU's model. + * + * Returns 0 on success and aborts on failure. */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); @@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { - /* This should never actually be called in the "not KVM" case, + /* + * This should never actually be called in the "not KVM" case, * but set up the fields to indicate an error anyway. */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; @@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); * * Return: TRUE if any hardware breakpoints in use. */ - bool kvm_arm_hw_debug_active(CPUState *cs); /** * kvm_arm_copy_hw_debug_data: - * * @ptr: kvm_guest_debug_arch structure * * Copy the architecture specific debug registers into the * kvm_guest_debug ioctl structure. */ struct kvm_guest_debug_arch; - void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); /** - * its_class_name + * its_class_name: * * Return the ITS class name to use depending on whether KVM acceleration * and KVM CAP_SIGNAL_MSI are supported -- 2.20.1 From: Andrew Jones <drjones@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20200120101023.16030-3-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) static void virt_machine_4_2_options(MachineClass *mc) { + virt_machine_5_0_options(mc); compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } DEFINE_VIRT_MACHINE(4, 2) -- 2.20.1 From: Andrew Jones <drjones@redhat.com> Add the missing GENERIC_TIMER feature to kvm64 cpus. We don't currently use these registers when KVM is enabled, but it's probably best we add the feature flag for consistency and potential future use. There's also precedent, as we add the PMU feature flag to KVM enabled guests, even though we don't use those registers either. This change was originally posted as a hunk of a different, never merged patch from Bijan Mottahedeh. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200120101023.16030-4-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/kvm64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) set_feature(&features, ARM_FEATURE_NEON); set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); + set_feature(&features, ARM_FEATURE_GENERIC_TIMER); ahcf->features = features; -- 2.20.1 From: Andrew Jones <drjones@redhat.com> If we know what the default value should be then we can test for that as well as the feature existence. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200120101023.16030-5-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/qtest/arm-cpu-features.c | 37 +++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature) qobject_unref(_resp); \ }) +#define assert_feature(qts, cpu_type, feature, expected_value) \ +({ \ + QDict *_resp, *_props; \ + \ + _resp = do_query_no_props(qts, cpu_type); \ + g_assert(_resp); \ + g_assert(resp_has_props(_resp)); \ + _props = resp_get_props(_resp); \ + g_assert(qdict_get(_props, feature)); \ + g_assert(qdict_get_bool(_props, feature) == (expected_value)); \ + qobject_unref(_resp); \ +}) + +#define assert_has_feature_enabled(qts, cpu_type, feature) \ + assert_feature(qts, cpu_type, feature, true) + +#define assert_has_feature_disabled(qts, cpu_type, feature) \ + assert_feature(qts, cpu_type, feature, false) + static void assert_type_full(QTestState *qts) { const char *error; @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data) assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL); /* Test expected feature presence/absence for some cpu types */ - assert_has_feature(qts, "max", "pmu"); - assert_has_feature(qts, "cortex-a15", "pmu"); + assert_has_feature_enabled(qts, "max", "pmu"); + assert_has_feature_enabled(qts, "cortex-a15", "pmu"); assert_has_not_feature(qts, "cortex-a15", "aarch64"); if (g_str_equal(qtest_get_arch(), "aarch64")) { - assert_has_feature(qts, "max", "aarch64"); - assert_has_feature(qts, "max", "sve"); - assert_has_feature(qts, "max", "sve128"); - assert_has_feature(qts, "cortex-a57", "pmu"); - assert_has_feature(qts, "cortex-a57", "aarch64"); + assert_has_feature_enabled(qts, "max", "aarch64"); + assert_has_feature_enabled(qts, "max", "sve"); + assert_has_feature_enabled(qts, "max", "sve128"); + assert_has_feature_enabled(qts, "cortex-a57", "pmu"); + assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); sve_tests_default(qts, "max"); @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) QDict *resp; char *error; - assert_has_feature(qts, "host", "aarch64"); - assert_has_feature(qts, "host", "pmu"); + assert_has_feature_enabled(qts, "host", "aarch64"); + assert_has_feature_enabled(qts, "host", "pmu"); assert_error(qts, "cortex-a15", "We cannot guarantee the CPU type 'cortex-a15' works " -- 2.20.1 From: Andrew Jones <drjones@redhat.com> When a VM is stopped (such as when it's paused) guest virtual time should stop counting. Otherwise, when the VM is resumed it will experience time jumps and its kernel may report soft lockups. Not counting virtual time while the VM is stopped has the side effect of making the guest's time appear to lag when compared with real time, and even with time derived from the physical counter. For this reason, this change, which is enabled by default, comes with a KVM CPU feature allowing it to be disabled, restoring legacy behavior. This patch only provides the implementation of the virtual time adjustment. A subsequent patch will provide the CPU property allowing the change to be enabled and disabled. Reported-by: Bijan Mottahedeh <bijan.mottahedeh@oracle.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20200120101023.16030-6-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 7 ++++ target/arm/kvm_arm.h | 38 ++++++++++++++++++ target/arm/kvm.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 3 ++ target/arm/kvm64.c | 3 ++ target/arm/machine.c | 7 ++++ 6 files changed, 150 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; + /* KVM CPU state */ + + /* KVM virtual time adjustment */ + bool kvm_adjvtime; + bool kvm_vtime_dirty; + uint64_t kvm_vtime; + /* Uniprocessor system with MP extensions */ bool mp_is_up; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level); */ bool write_kvmstate_to_list(ARMCPU *cpu); +/** + * kvm_arm_cpu_pre_save: + * @cpu: ARMCPU + * + * Called after write_kvmstate_to_list() from cpu_pre_save() to update + * the cpreg list with KVM CPU state. + */ +void kvm_arm_cpu_pre_save(ARMCPU *cpu); + +/** + * kvm_arm_cpu_post_load: + * @cpu: ARMCPU + * + * Called from cpu_post_load() to update KVM CPU state from the cpreg list. + */ +void kvm_arm_cpu_post_load(ARMCPU *cpu); + /** * kvm_arm_reset_vcpu: * @cpu: ARMCPU @@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); +/** + * kvm_arm_get_virtual_time: + * @cs: CPUState + * + * Gets the VCPU's virtual counter and stores it in the KVM CPU state. + */ +void kvm_arm_get_virtual_time(CPUState *cs); + +/** + * kvm_arm_put_virtual_time: + * @cs: CPUState + * + * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. + */ +void kvm_arm_put_virtual_time(CPUState *cs); + +void kvm_arm_vm_state_change(void *opaque, int running, RunState state); + int kvm_arm_vgic_probe(void); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} static inline void kvm_arm_pmu_init(CPUState *cs) {} static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} + +static inline void kvm_arm_get_virtual_time(CPUState *cs) {} +static inline void kvm_arm_put_virtual_time(CPUState *cs) {} #endif static inline const char *gic_class_name(void) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -XXX,XX +XXX,XX @@ static int compare_u64(const void *a, const void *b) return 0; } +/* + * cpreg_values are sorted in ascending order by KVM register ID + * (see kvm_arm_init_cpreg_list). This allows us to cheaply find + * the storage for a KVM register by ID with a binary search. + */ +static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) +{ + uint64_t *res; + + res = bsearch(&regidx, cpu->cpreg_indexes, cpu->cpreg_array_len, + sizeof(uint64_t), compare_u64); + assert(res); + + return &cpu->cpreg_values[res - cpu->cpreg_indexes]; +} + /* Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). @@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) return ok; } +void kvm_arm_cpu_pre_save(ARMCPU *cpu) +{ + /* KVM virtual time adjustment */ + if (cpu->kvm_vtime_dirty) { + *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; + } +} + +void kvm_arm_cpu_post_load(ARMCPU *cpu) +{ + /* KVM virtual time adjustment */ + if (cpu->kvm_adjvtime) { + cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); + cpu->kvm_vtime_dirty = true; + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) return 0; } +void kvm_arm_get_virtual_time(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + struct kvm_one_reg reg = { + .id = KVM_REG_ARM_TIMER_CNT, + .addr = (uintptr_t)&cpu->kvm_vtime, + }; + int ret; + + if (cpu->kvm_vtime_dirty) { + return; + } + + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg); + if (ret) { + error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); + abort(); + } + + cpu->kvm_vtime_dirty = true; +} + +void kvm_arm_put_virtual_time(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + struct kvm_one_reg reg = { + .id = KVM_REG_ARM_TIMER_CNT, + .addr = (uintptr_t)&cpu->kvm_vtime, + }; + int ret; + + if (!cpu->kvm_vtime_dirty) { + return; + } + + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg); + if (ret) { + error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); + abort(); + } + + cpu->kvm_vtime_dirty = false; +} + int kvm_put_vcpu_events(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -XXX,XX +XXX,XX @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) return MEMTXATTRS_UNSPECIFIED; } +void kvm_arm_vm_state_change(void *opaque, int running, RunState state) +{ + CPUState *cs = opaque; + ARMCPU *cpu = ARM_CPU(cs); + + if (running) { + if (cpu->kvm_adjvtime) { + kvm_arm_put_virtual_time(cs); + } + } else { + if (cpu->kvm_adjvtime) { + kvm_arm_get_virtual_time(cs); + } + } +} int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -XXX,XX +XXX,XX @@ #include "qemu-common.h" #include "cpu.h" #include "qemu/timer.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); if (cpu->start_powered_off) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -XXX,XX +XXX,XX @@ #include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "exec/gdbstub.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); if (cpu->start_powered_off) { diff --git a/target/arm/machine.c b/target/arm/machine.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque) /* This should never fail */ abort(); } + + /* + * kvm_arm_cpu_pre_save() must be called after + * write_kvmstate_to_list() + */ + kvm_arm_cpu_pre_save(cpu); } else { if (!write_cpustate_to_list(cpu, false)) { /* This should never fail. */ @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) * we're using it. */ write_list_to_cpustate(cpu); + kvm_arm_cpu_post_load(cpu); } else { if (!write_list_to_cpustate(cpu)) { return -1; -- 2.20.1 From: Andrew Jones <drjones@redhat.com> kvm-no-adjvtime is a KVM specific CPU property and a first of its kind. To accommodate it we also add kvm_arm_add_vcpu_properties() and a KVM specific CPU properties description to the CPU features document. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20200120101023.16030-7-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/virt.h | 1 + target/arm/kvm_arm.h | 11 ++++++++++ hw/arm/virt.c | 8 ++++++++ target/arm/cpu.c | 2 ++ target/arm/cpu64.c | 1 + target/arm/kvm.c | 28 +++++++++++++++++++++++++ target/arm/monitor.c | 1 + tests/qtest/arm-cpu-features.c | 4 ++++ docs/arm-cpu-features.rst | 37 +++++++++++++++++++++++++++++++++- 9 files changed, 92 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -XXX,XX +XXX,XX @@ typedef struct { bool smbios_old_sys_ver; bool no_highmem_ecam; bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ + bool kvm_no_adjvtime; } VirtMachineClass; typedef struct { diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -XXX,XX +XXX,XX @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); */ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); +/** + * kvm_arm_add_vcpu_properties: + * @obj: The CPU object to add the properties to + * + * Add all KVM specific CPU properties to the CPU object. These + * are the CPU properties with "kvm-" prefixed names. + */ +void kvm_arm_add_vcpu_properties(Object *obj); + /** * kvm_arm_aarch32_supported: * @cs: CPUState @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->host_cpu_probe_failed = true; } +static inline void kvm_arm_add_vcpu_properties(Object *obj) {} + static inline bool kvm_arm_aarch32_supported(CPUState *cs) { return false; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) } } + if (vmc->kvm_no_adjvtime && + object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { + object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); + } + if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { object_property_set_bool(cpuobj, false, "pmu", NULL); } @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) static void virt_machine_4_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_5_0_options(mc); compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); + vmc->kvm_no_adjvtime = true; } DEFINE_VIRT_MACHINE(4, 2) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_add_vcpu_properties(obj); } else { cortex_a15_initfn(obj); @@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } + kvm_arm_add_vcpu_properties(obj); arm_cpu_post_init(obj); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_add_vcpu_properties(obj); } else { uint64_t t; uint32_t u; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -XXX,XX +XXX,XX @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "qom/object.h" +#include "qapi/error.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features = arm_host_cpu_features.features; } +static bool kvm_no_adjvtime_get(Object *obj, Error **errp) +{ + return !ARM_CPU(obj)->kvm_adjvtime; +} + +static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) +{ + ARM_CPU(obj)->kvm_adjvtime = !value; +} + +/* KVM VCPU properties should be prefixed with "kvm-". */ +void kvm_arm_add_vcpu_properties(Object *obj) +{ + if (!kvm_enabled()) { + return; + } + + ARM_CPU(obj)->kvm_adjvtime = true; + object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, + kvm_no_adjvtime_set, &error_abort); + object_property_set_description(obj, "kvm-no-adjvtime", + "Set on to disable the adjustment of " + "the virtual counter. VM stopped time " + "will be counted.", &error_abort); +} + bool kvm_arm_pmu_supported(CPUState *cpu) { return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = { "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", + "kvm-no-adjvtime", NULL }; diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data) assert_has_feature_enabled(qts, "cortex-a15", "pmu"); assert_has_not_feature(qts, "cortex-a15", "aarch64"); + assert_has_not_feature(qts, "max", "kvm-no-adjvtime"); + if (g_str_equal(qtest_get_arch(), "aarch64")) { assert_has_feature_enabled(qts, "max", "aarch64"); assert_has_feature_enabled(qts, "max", "sve"); @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) return; } + assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime"); + if (g_str_equal(qtest_get_arch(), "aarch64")) { bool kvm_supports_sve; char max_name[8], name[8]; diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/arm-cpu-features.rst +++ b/docs/arm-cpu-features.rst @@ -XXX,XX +XXX,XX @@ supporting the feature or only supporting the feature under certain configurations. For example, the `aarch64` CPU feature, which, when disabled, enables the optional AArch32 CPU feature, is only supported when using the KVM accelerator and when running on a host CPU type that -supports the feature. +supports the feature. While `aarch64` currently only works with KVM, +it could work with TCG. CPU features that are specific to KVM are +prefixed with "kvm-" and are described in "KVM VCPU Features". CPU Feature Probing =================== @@ -XXX,XX +XXX,XX @@ disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). +KVM VCPU Features +================= + +KVM VCPU features are CPU features that are specific to KVM, such as +paravirt features or features that enable CPU virtualization extensions. +The features' CPU properties are only available when KVM is enabled and +are named with the prefix "kvm-". KVM VCPU features may be probed, +enabled, and disabled in the same way as other CPU features. Below is +the list of KVM VCPU features and their descriptions. + + kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This + means that by default the virtual time + adjustment is enabled (vtime is *not not* + adjusted). + + When virtual time adjustment is enabled each + time the VM transitions back to running state + the VCPU's virtual counter is updated to ensure + stopped time is not counted. This avoids time + jumps surprising guest OSes and applications, + as long as they use the virtual counter for + timekeeping. However it has the side effect of + the virtual and physical counters diverging. + All timekeeping based on the virtual counter + will appear to lag behind any timekeeping that + does not subtract VM stopped time. The guest + may resynchronize its virtual counter with + other time sources as needed. + + Enable kvm-no-adjvtime to disable virtual time + adjustment, also restoring the legacy (pre-5.0) + behavior. + SVE CPU Properties ================== -- 2.20.1 arm queue; dunno if this will be the last before softfreeze or not, but anyway probably the last large one. New orangepi-pc board model is the big item here. thanks -- PMM The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312 for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837: target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000) ---------------------------------------------------------------- target-arm queue: * Fix various bugs that might result in an assert() due to incorrect hflags for M-profile CPUs * Fix Aspeed SMC Controller user-mode select handling * Report correct (with-tag) address in fault address register when TBI is enabled * cubieboard: make sure SOC object isn't leaked * fsl-imx25: Wire up eSDHC controllers * fsl-imx25: Wire up USB controllers * New board model: orangepi-pc (OrangePi PC) * ARM/KVM: if user doesn't select GIC version and the host kernel can only provide GICv3, use that, rather than defaulting to "fail because GICv2 isn't possible" * kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync ---------------------------------------------------------------- Beata Michalska (1): target/arm: kvm: Inject events at the last stage of sync Cédric Le Goater (2): aspeed/smc: Add some tracing aspeed/smc: Fix User mode select/unselect scheme Eric Auger (6): hw/arm/virt: Document 'max' value in gic-version property description hw/arm/virt: Introduce VirtGICType enum type hw/arm/virt: Introduce finalize_gic_version() target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap hw/arm/virt: kvm: Restructure finalize_gic_version() hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work Guenter Roeck (2): hw/arm/fsl-imx25: Wire up eSDHC controllers hw/arm/fsl-imx25: Wire up USB controllers Igor Mammedov (1): hw/arm/cubieboard: make sure SOC object isn't leaked Niek Linnenbank (13): hw/arm: add Allwinner H3 System-on-Chip hw/arm: add Xunlong Orange Pi PC machine hw/arm/allwinner-h3: add Clock Control Unit hw/arm/allwinner-h3: add USB host controller hw/arm/allwinner-h3: add System Control module hw/arm/allwinner: add CPU Configuration module hw/arm/allwinner: add Security Identifier device hw/arm/allwinner: add SD/MMC host controller hw/arm/allwinner-h3: add EMAC ethernet device hw/arm/allwinner-h3: add Boot ROM support hw/arm/allwinner-h3: add SDRAM controller device hw/arm/allwinner: add RTC device support docs: add Orange Pi PC document Peter Maydell (4): hw/intc/armv7m_nvic: Rebuild hflags on reset target/arm: Update hflags in trans_CPS_v7m() target/arm: Recalculate hflags correctly after writes to CONTROL target/arm: Fix some comment typos Philippe Mathieu-Daudé (5): tests/boot_linux_console: Add a quick test for the OrangePi PC board tests/boot_linux_console: Add initrd test for the Orange Pi PC board tests/boot_linux_console: Add a SD card test for the OrangePi PC board tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC Richard Henderson (2): target/arm: Check addresses for disabled regimes target/arm: Disable clean_data_tbi for system mode Makefile.objs | 1 + hw/arm/Makefile.objs | 1 + hw/misc/Makefile.objs | 5 + hw/net/Makefile.objs | 1 + hw/rtc/Makefile.objs | 1 + hw/sd/Makefile.objs | 1 + hw/usb/hcd-ehci.h | 1 + include/hw/arm/allwinner-a10.h | 4 + include/hw/arm/allwinner-h3.h | 161 ++++++ include/hw/arm/fsl-imx25.h | 18 + include/hw/arm/virt.h | 12 +- include/hw/misc/allwinner-cpucfg.h | 52 ++ include/hw/misc/allwinner-h3-ccu.h | 66 +++ include/hw/misc/allwinner-h3-dramc.h | 106 ++++ include/hw/misc/allwinner-h3-sysctrl.h | 67 +++ include/hw/misc/allwinner-sid.h | 60 +++ include/hw/net/allwinner-sun8i-emac.h | 99 ++++ include/hw/rtc/allwinner-rtc.h | 134 +++++ include/hw/sd/allwinner-sdhost.h | 135 +++++ target/arm/helper.h | 1 + target/arm/kvm_arm.h | 3 + hw/arm/allwinner-a10.c | 19 + hw/arm/allwinner-h3.c | 465 ++++++++++++++++++ hw/arm/cubieboard.c | 18 + hw/arm/fsl-imx25.c | 56 +++ hw/arm/imx25_pdk.c | 16 + hw/arm/orangepi.c | 130 +++++ hw/arm/virt.c | 145 ++++-- hw/intc/armv7m_nvic.c | 6 + hw/misc/allwinner-cpucfg.c | 282 +++++++++++ hw/misc/allwinner-h3-ccu.c | 242 +++++++++ hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++ hw/misc/allwinner-h3-sysctrl.c | 140 ++++++ hw/misc/allwinner-sid.c | 168 +++++++ hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++ hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++ hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++ hw/ssi/aspeed_smc.c | 56 ++- hw/usb/hcd-ehci-sysbus.c | 17 + target/arm/helper.c | 49 +- target/arm/kvm.c | 14 +- target/arm/kvm32.c | 15 +- target/arm/kvm64.c | 15 +- target/arm/translate-a64.c | 11 + target/arm/translate.c | 14 +- MAINTAINERS | 9 + default-configs/arm-softmmu.mak | 1 + docs/system/arm/orangepi.rst | 253 ++++++++++ docs/system/target-arm.rst | 2 + hw/arm/Kconfig | 12 + hw/misc/trace-events | 19 + hw/net/Kconfig | 3 + hw/net/trace-events | 10 + hw/rtc/trace-events | 4 + hw/sd/trace-events | 7 + hw/ssi/trace-events | 10 + tests/acceptance/boot_linux_console.py | 230 +++++++++ 57 files changed, 5787 insertions(+), 74 deletions(-) create mode 100644 include/hw/arm/allwinner-h3.h create mode 100644 include/hw/misc/allwinner-cpucfg.h create mode 100644 include/hw/misc/allwinner-h3-ccu.h create mode 100644 include/hw/misc/allwinner-h3-dramc.h create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h create mode 100644 include/hw/misc/allwinner-sid.h create mode 100644 include/hw/net/allwinner-sun8i-emac.h create mode 100644 include/hw/rtc/allwinner-rtc.h create mode 100644 include/hw/sd/allwinner-sdhost.h create mode 100644 hw/arm/allwinner-h3.c create mode 100644 hw/arm/orangepi.c create mode 100644 hw/misc/allwinner-cpucfg.c create mode 100644 hw/misc/allwinner-h3-ccu.c create mode 100644 hw/misc/allwinner-h3-dramc.c create mode 100644 hw/misc/allwinner-h3-sysctrl.c create mode 100644 hw/misc/allwinner-sid.c create mode 100644 hw/net/allwinner-sun8i-emac.c create mode 100644 hw/rtc/allwinner-rtc.c create mode 100644 hw/sd/allwinner-sdhost.c create mode 100644 docs/system/arm/orangepi.rst create mode 100644 hw/ssi/trace-events Some of an M-profile CPU's cached hflags state depends on state that's in our NVIC object. We already do an hflags rebuild when the NVIC registers are written, but we also need to do this on NVIC reset, because there's no guarantee that this will happen before the CPU reset. This fixes an assertion due to mismatched hflags which happens if the CPU is reset from inside a HardFault handler. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200303174950.3298-2-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev) s->itns[i] = true; } } + + /* + * We updated state that affects the CPU's MMUidx and thus its hflags; + * and we can't guarantee that we run before the CPU reset function. + */ + arm_rebuild_hflags(&s->cpu->env); } static void nvic_systick_trigger(void *opaque, int n, int level) -- 2.20.1 For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index (it changes the NegPri bit). We update the hflags after calls to the v7m_msr helper in trans_MSR_v7m() but forgot to do so in trans_CPS_v7m(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200303174950.3298-3-peter.maydell@linaro.org --- target/arm/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -XXX,XX +XXX,XX @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) { - TCGv_i32 tmp, addr; + TCGv_i32 tmp, addr, el; if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); } + el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_m32(cpu_env, el); + tcg_temp_free_i32(el); tcg_temp_free_i32(tmp); gen_lookup_tb(s); return true; -- 2.20.1 A write to the CONTROL register can change our current EL (by writing to the nPRIV bit). That means that we can't assume that s->current_el is still valid in trans_MSR_v7m() when we try to rebuild the hflags. Add a new helper rebuild_hflags_m32_newel() which, like the existing rebuild_hflags_a32_newel(), recalculates the current EL from scratch, and use it in trans_MSR_v7m(). This fixes an assertion about an hflags mismatch when the guest changes privilege by writing to CONTROL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200303174950.3298-4-peter.maydell@linaro.org --- target/arm/helper.h | 1 + target/arm/helper.c | 12 ++++++++++++ target/arm/translate.c | 7 +++---- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ void arm_rebuild_hflags(CPUARMState *env) env->hflags = rebuild_hflags_internal(env); } +/* + * If we have triggered a EL state change we can't rely on the + * translator having passed it to us, we need to recompute. + */ +void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); +} + void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) { int fp_el = fp_exception_el(env, el); diff --git a/target/arm/translate.c b/target/arm/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) { - TCGv_i32 addr, reg, el; + TCGv_i32 addr, reg; if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) gen_helper_v7m_msr(cpu_env, addr, reg); tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); - el = tcg_const_i32(s->current_el); - gen_helper_rebuild_hflags_m32(cpu_env, el); - tcg_temp_free_i32(el); + /* If we wrote to CONTROL, the EL might have changed */ + gen_helper_rebuild_hflags_m32_newel(cpu_env); gen_lookup_tb(s); return true; } -- 2.20.1 Fix a couple of comment typos. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200303174950.3298-5-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- target/arm/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) /* * If we have triggered a EL state change we can't rely on the - * translator having passed it too us, we need to recompute. + * translator having passed it to us, we need to recompute. */ void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) { diff --git a/target/arm/translate.c b/target/arm/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* - * A write to any coprocessor regiser that ends a TB + * A write to any coprocessor register that ends a TB * must rebuild the hflags for the next TB. */ TCGv_i32 tcg_el = tcg_const_i32(s->current_el); -- 2.20.1 From: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200206112645.21275-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- Makefile.objs | 1 + hw/ssi/aspeed_smc.c | 17 +++++++++++++++++ hw/ssi/trace-events | 9 +++++++++ 3 files changed, 27 insertions(+) create mode 100644 hw/ssi/trace-events diff --git a/Makefile.objs b/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/scsi trace-events-subdirs += hw/sd trace-events-subdirs += hw/sparc trace-events-subdirs += hw/sparc64 +trace-events-subdirs += hw/ssi trace-events-subdirs += hw/timer trace-events-subdirs += hw/tpm trace-events-subdirs += hw/usb diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "exec/address-spaces.h" #include "qemu/units.h" +#include "trace.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, s->ctrl->reg_to_segment(s, new, &seg); + trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); + /* The start address of CS0 is read-only */ if (cs == 0 && seg.addr != s->ctrl->flash_window_base) { qemu_log_mask(LOG_GUEST_ERROR, @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) __func__, aspeed_smc_flash_mode(fl)); } + trace_aspeed_smc_flash_read(fl->id, addr, size, ret, + aspeed_smc_flash_mode(fl)); return ret; } @@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, AspeedSMCState *s = fl->controller; uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3; + trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies, + (uint8_t) data & 0xff); + if (s->snoop_index == SNOOP_OFF) { return false; /* Do nothing */ @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, AspeedSMCState *s = fl->controller; int i; + trace_aspeed_smc_flash_write(fl->id, addr, size, data, + aspeed_smc_flash_mode(fl)); + if (!aspeed_smc_is_writable(fl)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%" HWADDR_PRIx "\n", __func__, addr); @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { + + trace_aspeed_smc_read(addr, size, s->regs[addr]); + return s->regs[addr]; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) __func__, s->regs[R_DMA_FLASH_ADDR]); return; } + trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); /* * When the DMA is on-going, the DMA registers are updated @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, addr >>= 2; + trace_aspeed_smc_write(addr, size, data); + if (addr == s->r_conf || (addr >= s->r_timings && addr < s->r_timings + s->ctrl->nregs_timings) || diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/ssi/trace-events @@ -XXX,XX +XXX,XX @@ +# aspeed_smc.c + +aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]" +aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d" +aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x" +aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d" +aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 +aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" +aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 -- 2.20.1 From: Cédric Le Goater <clg@kaod.org> The Aspeed SMC Controller can operate in different modes : Read, Fast Read, Write and User modes. When the User mode is configured, it selects automatically the SPI slave device until the CE_STOP_ACTIVE bit is set to 1. When any other modes are configured the device is unselected. The HW logic handles the chip select automatically when the flash is accessed through its AHB window. When configuring the CEx Control Register, the User mode logic to select and unselect the slave is incorrect and data corruption can be seen on machines using two chips, witherspoon and romulus. Rework the handler setting the CEx Control Register to fix this issue. Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20200206112645.21275-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++---------------- hw/ssi/trace-events | 1 + 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl) } } -static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl) +static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) { - const AspeedSMCState *s = fl->controller; + AspeedSMCState *s = fl->controller; - return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE; + trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : ""); + + qemu_set_irq(s->cs_lines[fl->id], unselect); } static void aspeed_smc_flash_select(AspeedSMCFlash *fl) { - AspeedSMCState *s = fl->controller; - - s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE; - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); + aspeed_smc_flash_do_select(fl, false); } static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) { - AspeedSMCState *s = fl->controller; - - s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE; - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); + aspeed_smc_flash_do_select(fl, true); } static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_flash_ops = { }, }; -static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl) +static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) { AspeedSMCState *s = fl->controller; + bool unselect; - s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START; + /* User mode selects the CS, other modes unselect */ + unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE; - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); + /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ + if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) && + value & CTRL_CE_STOP_ACTIVE) { + unselect = true; + } + + s->regs[s->r_ctrl0 + fl->id] = value; + + s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; + + aspeed_smc_flash_do_select(fl, unselect); } static void aspeed_smc_reset(DeviceState *d) @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, s->regs[addr] = value; } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { int cs = addr - s->r_ctrl0; - s->regs[addr] = value; - aspeed_smc_flash_update_cs(&s->flashes[cs]); + aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); } else if (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) { int cs = addr - R_SEG_ADDR0; diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -XXX,XX +XXX,XX @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 +aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> We fail to validate the upper bits of a virtual address on a translation disabled regime, as per AArch64.TranslateAddressS1Off. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200308012946.16303-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx)) { - /* MMU disabled. */ + /* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.TranslateAddressS1Off. + */ + if (mmu_idx != ARMMMUIdx_Stage2) { + int r_el = regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax = arm_pamax(env_archcpu(env)); + uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; + int addrtop, tbi; + + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type == MMU_INST_FETCH) { + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi = (tbi >> extract64(address, 55, 1)) & 1; + addrtop = (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) != 0) { + fi->type = ARMFault_AddressSize; + fi->level = 0; + fi->stage2 = false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address = extract64(address, 0, 52); + } + } *phys_ptr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size = TARGET_PAGE_SIZE; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> We must include the tag in the FAR_ELx register when raising an addressing exception. Which means that we should not clear out the tag during translation. We cannot at present comply with this for user mode, so we retain the clean_data_tbi function for the moment, though it no longer does what it says on the tin for system mode. This function is to be replaced with MTE, so don't worry about the slight misnaming. Buglink: https://bugs.launchpad.net/qemu/+bug/1867072 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200308012946.16303-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/translate-a64.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); + /* + * In order to get the correct value in the FAR_ELx register, + * we must present the memory subsystem with the "dirty" address + * including the TBI. In system mode we can make this work via + * the TLB, dropping the TBI during translation. But for user-only + * mode we don't have that option, and must remove the top byte now. + */ +#ifdef CONFIG_USER_ONLY gen_top_byte_ignore(s, clean, addr, s->tbid); +#else + tcg_gen_mov_i64(clean, addr); +#endif return clean; } -- 2.20.1 From: Igor Mammedov <imammedo@redhat.com> SOC object returned by object_new() is leaked in current code. Set SOC parent explicitly to board and then unref to SOC object to make sure that refererence returned by object_new() is taken care of. The SOC object will be kept alive by its parent (machine) and will be automatically freed when MachineState is destroyed. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reported-by: Andrew Jones <drjones@redhat.com> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200303091254.22373-1-imammedo@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/cubieboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) } a10 = AW_A10(object_new(TYPE_AW_A10)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(a10), + &error_abort); + object_unref(OBJECT(a10)); object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err); if (err != NULL) { -- 2.20.1 From: Guenter Roeck <linux@roeck-us.net> Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives provided on the command line to available eSDHC controllers. This patch enables booting the imx25-pdk emulation from SD card. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200310215146.19688-2-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: made commit subject consistent with other patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/fsl-imx25.h | 9 +++++++++ hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++ hw/arm/imx25_pdk.c | 16 ++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/imx_rngc.h" #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" +#include "hw/sd/sdhci.h" #include "exec/memory.h" #include "target/arm/cpu.h" @@ -XXX,XX +XXX,XX @@ #define FSL_IMX25_NUM_EPITS 2 #define FSL_IMX25_NUM_I2CS 3 #define FSL_IMX25_NUM_GPIOS 4 +#define FSL_IMX25_NUM_ESDHCS 2 typedef struct FslIMX25State { /*< private >*/ @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { IMXRNGCState rngc; IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; + SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS]; MemoryRegion rom[2]; MemoryRegion iram; MemoryRegion iram_alias; @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO3_SIZE 0x4000 #define FSL_IMX25_RNGC_ADDR 0x53FB0000 #define FSL_IMX25_RNGC_SIZE 0x4000 +#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000 +#define FSL_IMX25_ESDHC1_SIZE 0x4000 +#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000 +#define FSL_IMX25_ESDHC2_SIZE 0x4000 #define FSL_IMX25_GPIO1_ADDR 0x53FCC000 #define FSL_IMX25_GPIO1_SIZE 0x4000 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO2_IRQ 51 #define FSL_IMX25_GPIO3_IRQ 16 #define FSL_IMX25_GPIO4_IRQ 23 +#define FSL_IMX25_ESDHC1_IRQ 9 +#define FSL_IMX25_ESDHC2_IRQ 8 #endif /* FSL_IMX25_H */ diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -XXX,XX +XXX,XX @@ #include "hw/qdev-properties.h" #include "chardev/char.h" +#define IMX25_ESDHC_CAPABILITIES 0x07e20000 + static void fsl_imx25_init(Object *obj) { FslIMX25State *s = FSL_IMX25(obj); @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj) sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); } + + for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { + sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]), + TYPE_IMX_USDHC); + } } static void fsl_imx25_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) gpio_table[i].irq)); } + /* Initialize all SDHC */ + for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } esdhc_table[FSL_IMX25_NUM_ESDHCS] = { + { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ }, + { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, + }; + + object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version", + &err); + object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, + "capareg", &err); + object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, + qdev_get_gpio_in(DEVICE(&s->avic), + esdhc_table[i].irq)); + } + /* initialize 2 x 16 KB ROM */ memory_region_init_rom(&s->rom[0], NULL, "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -XXX,XX +XXX,XX @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/boards.h" #include "qemu/error-report.h" @@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine) imx25_pdk_binfo.board_id = 1771, imx25_pdk_binfo.nb_cpus = 1; + for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { + BusState *bus; + DeviceState *carddev; + DriveInfo *di; + BlockBackend *blk; + + di = drive_get_next(IF_SD); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus"); + carddev = qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, + "realized", &error_fatal); + } + /* * We test explicitly for qtest here as it is not done (yet?) in * arm_load_kernel(). Without this the "make check" command would -- 2.20.1 From: Guenter Roeck <linux@roeck-us.net> i.MX25 supports two USB controllers. Let's wire them up. With this patch, imx25-pdk can boot from both USB ports. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200310215146.19688-3-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/fsl-imx25.h | 9 +++++++++ hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -XXX,XX +XXX,XX @@ #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" +#include "hw/usb/chipidea.h" #include "exec/memory.h" #include "target/arm/cpu.h" @@ -XXX,XX +XXX,XX @@ #define FSL_IMX25_NUM_I2CS 3 #define FSL_IMX25_NUM_GPIOS 4 #define FSL_IMX25_NUM_ESDHCS 2 +#define FSL_IMX25_NUM_USBS 2 typedef struct FslIMX25State { /*< private >*/ @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS]; + ChipideaState usb[FSL_IMX25_NUM_USBS]; MemoryRegion rom[2]; MemoryRegion iram; MemoryRegion iram_alias; @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO1_SIZE 0x4000 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 #define FSL_IMX25_GPIO2_SIZE 0x4000 +#define FSL_IMX25_USB1_ADDR 0x53FF4000 +#define FSL_IMX25_USB1_SIZE 0x0200 +#define FSL_IMX25_USB2_ADDR 0x53FF4400 +#define FSL_IMX25_USB2_SIZE 0x0200 #define FSL_IMX25_AVIC_ADDR 0x68000000 #define FSL_IMX25_AVIC_SIZE 0x4000 #define FSL_IMX25_IRAM_ADDR 0x78000000 @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO4_IRQ 23 #define FSL_IMX25_ESDHC1_IRQ 9 #define FSL_IMX25_ESDHC2_IRQ 8 +#define FSL_IMX25_USB1_IRQ 37 +#define FSL_IMX25_USB2_IRQ 35 #endif /* FSL_IMX25_H */ diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj) sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC); } + + for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { + sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]), + TYPE_CHIPIDEA); + } + } static void fsl_imx25_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) esdhc_table[i].irq)); } + /* USB */ + for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } usb_table[FSL_IMX25_NUM_USBS] = { + { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ }, + { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ }, + }; + + object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", + &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, + qdev_get_gpio_in(DEVICE(&s->avic), + usb_table[i].irq)); + } + /* initialize 2 x 16 KB ROM */ memory_region_init_rom(&s->rom[0], NULL, "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Allwinner H3 is a System on Chip containing four ARM Cortex A7 processor cores. Features and specifications include DDR2/DDR3 memory, SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and various I/O modules. This commit adds support for the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 106 +++++++++++ hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++ MAINTAINERS | 7 + default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 8 + 6 files changed, 450 insertions(+) create mode 100644 include/hw/arm/allwinner-h3.h create mode 100644 hw/arm/allwinner-h3.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 System on Chip emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 + * processor cores. Features and specifications include DDR2/DDR3 memory, + * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and + * various I/O modules. + * + * This implementation is based on the following datasheet: + * + * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf + * + * The latest datasheet and more info can be found on the Linux Sunxi wiki: + * + * https://linux-sunxi.org/H3 + */ + +#ifndef HW_ARM_ALLWINNER_H3_H +#define HW_ARM_ALLWINNER_H3_H + +#include "qom/object.h" +#include "hw/arm/boot.h" +#include "hw/timer/allwinner-a10-pit.h" +#include "hw/intc/arm_gic.h" +#include "target/arm/cpu.h" + +/** + * Allwinner H3 device list + * + * This enumeration is can be used refer to a particular device in the + * Allwinner H3 SoC. For example, the physical memory base address for + * each device can be found in the AwH3State object in the memmap member + * using the device enum value as index. + * + * @see AwH3State + */ +enum { + AW_H3_SRAM_A1, + AW_H3_SRAM_A2, + AW_H3_SRAM_C, + AW_H3_PIT, + AW_H3_UART0, + AW_H3_UART1, + AW_H3_UART2, + AW_H3_UART3, + AW_H3_GIC_DIST, + AW_H3_GIC_CPU, + AW_H3_GIC_HYP, + AW_H3_GIC_VCPU, + AW_H3_SDRAM +}; + +/** Total number of CPU cores in the H3 SoC */ +#define AW_H3_NUM_CPUS (4) + +/** + * Allwinner H3 object model + * @{ + */ + +/** Object type for the Allwinner H3 SoC */ +#define TYPE_AW_H3 "allwinner-h3" + +/** Convert input object to Allwinner H3 state object */ +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) + +/** @} */ + +/** + * Allwinner H3 object + * + * This struct contains the state of all the devices + * which are currently emulated by the H3 SoC code. + */ +typedef struct AwH3State { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + ARMCPU cpus[AW_H3_NUM_CPUS]; + const hwaddr *memmap; + AwA10PITState timer; + GICState gic; + MemoryRegion sram_a1; + MemoryRegion sram_a2; + MemoryRegion sram_c; +} AwH3State; + +#endif /* HW_ARM_ALLWINNER_H3_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 System on Chip emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "hw/qdev-core.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/char/serial.h" +#include "hw/misc/unimp.h" +#include "sysemu/sysemu.h" +#include "hw/arm/allwinner-h3.h" + +/* Memory map */ +const hwaddr allwinner_h3_memmap[] = { + [AW_H3_SRAM_A1] = 0x00000000, + [AW_H3_SRAM_A2] = 0x00044000, + [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_PIT] = 0x01c20c00, + [AW_H3_UART0] = 0x01c28000, + [AW_H3_UART1] = 0x01c28400, + [AW_H3_UART2] = 0x01c28800, + [AW_H3_UART3] = 0x01c28c00, + [AW_H3_GIC_DIST] = 0x01c81000, + [AW_H3_GIC_CPU] = 0x01c82000, + [AW_H3_GIC_HYP] = 0x01c84000, + [AW_H3_GIC_VCPU] = 0x01c86000, + [AW_H3_SDRAM] = 0x40000000 +}; + +/* List of unimplemented devices */ +struct AwH3Unimplemented { + const char *device_name; + hwaddr base; + hwaddr size; +} unimplemented[] = { + { "d-engine", 0x01000000, 4 * MiB }, + { "d-inter", 0x01400000, 128 * KiB }, + { "syscon", 0x01c00000, 4 * KiB }, + { "dma", 0x01c02000, 4 * KiB }, + { "nfdc", 0x01c03000, 4 * KiB }, + { "ts", 0x01c06000, 4 * KiB }, + { "keymem", 0x01c0b000, 4 * KiB }, + { "lcd0", 0x01c0c000, 4 * KiB }, + { "lcd1", 0x01c0d000, 4 * KiB }, + { "ve", 0x01c0e000, 4 * KiB }, + { "mmc0", 0x01c0f000, 4 * KiB }, + { "mmc1", 0x01c10000, 4 * KiB }, + { "mmc2", 0x01c11000, 4 * KiB }, + { "sid", 0x01c14000, 1 * KiB }, + { "crypto", 0x01c15000, 4 * KiB }, + { "msgbox", 0x01c17000, 4 * KiB }, + { "spinlock", 0x01c18000, 4 * KiB }, + { "usb0-otg", 0x01c19000, 4 * KiB }, + { "usb0-phy", 0x01c1a000, 4 * KiB }, + { "usb1-phy", 0x01c1b000, 4 * KiB }, + { "usb2-phy", 0x01c1c000, 4 * KiB }, + { "usb3-phy", 0x01c1d000, 4 * KiB }, + { "smc", 0x01c1e000, 4 * KiB }, + { "ccu", 0x01c20000, 1 * KiB }, + { "pio", 0x01c20800, 1 * KiB }, + { "owa", 0x01c21000, 1 * KiB }, + { "pwm", 0x01c21400, 1 * KiB }, + { "keyadc", 0x01c21800, 1 * KiB }, + { "pcm0", 0x01c22000, 1 * KiB }, + { "pcm1", 0x01c22400, 1 * KiB }, + { "pcm2", 0x01c22800, 1 * KiB }, + { "audio", 0x01c22c00, 2 * KiB }, + { "smta", 0x01c23400, 1 * KiB }, + { "ths", 0x01c25000, 1 * KiB }, + { "uart0", 0x01c28000, 1 * KiB }, + { "uart1", 0x01c28400, 1 * KiB }, + { "uart2", 0x01c28800, 1 * KiB }, + { "uart3", 0x01c28c00, 1 * KiB }, + { "twi0", 0x01c2ac00, 1 * KiB }, + { "twi1", 0x01c2b000, 1 * KiB }, + { "twi2", 0x01c2b400, 1 * KiB }, + { "scr", 0x01c2c400, 1 * KiB }, + { "emac", 0x01c30000, 64 * KiB }, + { "gpu", 0x01c40000, 64 * KiB }, + { "hstmr", 0x01c60000, 4 * KiB }, + { "dramcom", 0x01c62000, 4 * KiB }, + { "dramctl0", 0x01c63000, 4 * KiB }, + { "dramphy0", 0x01c65000, 4 * KiB }, + { "spi0", 0x01c68000, 4 * KiB }, + { "spi1", 0x01c69000, 4 * KiB }, + { "csi", 0x01cb0000, 320 * KiB }, + { "tve", 0x01e00000, 64 * KiB }, + { "hdmi", 0x01ee0000, 128 * KiB }, + { "rtc", 0x01f00000, 1 * KiB }, + { "r_timer", 0x01f00800, 1 * KiB }, + { "r_intc", 0x01f00c00, 1 * KiB }, + { "r_wdog", 0x01f01000, 1 * KiB }, + { "r_prcm", 0x01f01400, 1 * KiB }, + { "r_twd", 0x01f01800, 1 * KiB }, + { "r_cpucfg", 0x01f01c00, 1 * KiB }, + { "r_cir-rx", 0x01f02000, 1 * KiB }, + { "r_twi", 0x01f02400, 1 * KiB }, + { "r_uart", 0x01f02800, 1 * KiB }, + { "r_pio", 0x01f02c00, 1 * KiB }, + { "r_pwm", 0x01f03800, 1 * KiB }, + { "core-dbg", 0x3f500000, 128 * KiB }, + { "tsgen-ro", 0x3f506000, 4 * KiB }, + { "tsgen-ctl", 0x3f507000, 4 * KiB }, + { "ddr-mem", 0x40000000, 2 * GiB }, + { "n-brom", 0xffff0000, 32 * KiB }, + { "s-brom", 0xffff0000, 64 * KiB } +}; + +/* Per Processor Interrupts */ +enum { + AW_H3_GIC_PPI_MAINT = 9, + AW_H3_GIC_PPI_HYPTIMER = 10, + AW_H3_GIC_PPI_VIRTTIMER = 11, + AW_H3_GIC_PPI_SECTIMER = 13, + AW_H3_GIC_PPI_PHYSTIMER = 14 +}; + +/* Shared Processor Interrupts */ +enum { + AW_H3_GIC_SPI_UART0 = 0, + AW_H3_GIC_SPI_UART1 = 1, + AW_H3_GIC_SPI_UART2 = 2, + AW_H3_GIC_SPI_UART3 = 3, + AW_H3_GIC_SPI_TIMER0 = 18, + AW_H3_GIC_SPI_TIMER1 = 19, +}; + +/* Allwinner H3 general constants */ +enum { + AW_H3_GIC_NUM_SPI = 128 +}; + +static void allwinner_h3_init(Object *obj) +{ + AwH3State *s = AW_H3(obj); + + s->memmap = allwinner_h3_memmap; + + for (int i = 0; i < AW_H3_NUM_CPUS; i++) { + object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]), + ARM_CPU_TYPE_NAME("cortex-a7"), + &error_abort, NULL); + } + + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), + TYPE_ARM_GIC); + + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), + TYPE_AW_A10_PIT); + object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), + "clk0-freq", &error_abort); + object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), + "clk1-freq", &error_abort); +} + +static void allwinner_h3_realize(DeviceState *dev, Error **errp) +{ + AwH3State *s = AW_H3(dev); + unsigned i; + + /* CPUs */ + for (i = 0; i < AW_H3_NUM_CPUS; i++) { + + /* Provide Power State Coordination Interface */ + qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", + QEMU_PSCI_CONDUIT_HVC); + + /* Disable secondary CPUs */ + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", + i > 0); + + /* All exception levels required */ + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); + + /* Mark realized */ + qdev_init_nofail(DEVICE(&s->cpus[i])); + } + + /* Generic Interrupt Controller */ + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + + GIC_INTERNAL); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); + qdev_init_nofail(DEVICE(&s->gic)); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. + */ + for (i = 0; i < AW_H3_NUM_CPUS; i++) { + DeviceState *cpudev = DEVICE(&s->cpus[i]); + int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used for this board. + */ + const int timer_irq[] = { + [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER, + [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER, + [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER, + [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER, + }; + + /* Connect CPU timer outputs to GIC PPI inputs */ + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + timer_irq[irq])); + } + + /* Connect GIC outputs to CPU interrupt inputs */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + /* GIC maintenance signal */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS), + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + AW_H3_GIC_PPI_MAINT)); + } + + /* Timer */ + qdev_init_nofail(DEVICE(&s->timer)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1)); + + /* SRAM */ + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", + 64 * KiB, &error_abort); + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", + 32 * KiB, &error_abort); + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", + 44 * KiB, &error_abort); + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1], + &s->sram_a1); + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2], + &s->sram_a2); + memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], + &s->sram_c); + + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + /* UART1 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1), + 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN); + /* UART2 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2), + 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN); + /* UART3 */ + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3), + 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); + + /* Unimplemented devices */ + for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { + create_unimplemented_device(unimplemented[i].device_name, + unimplemented[i].base, + unimplemented[i].size); + } +} + +static void allwinner_h3_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = allwinner_h3_realize; + /* Reason: uses serial_hd() in realize function */ + dc->user_creatable = false; +} + +static const TypeInfo allwinner_h3_type_info = { + .name = TYPE_AW_H3, + .parent = TYPE_DEVICE, + .instance_size = sizeof(AwH3State), + .instance_init = allwinner_h3_init, + .class_init = allwinner_h3_class_init, +}; + +static void allwinner_h3_register_types(void) +{ + type_register_static(&allwinner_h3_type_info); +} + +type_init(allwinner_h3_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: hw/*/allwinner* F: include/hw/*/allwinner* F: hw/arm/cubieboard.c +Allwinner-h3 +M: Niek Linnenbank <nieklinnenbank@gmail.com> +L: qemu-arm@nongnu.org +S: Maintained +F: hw/*/allwinner-h3* +F: include/hw/*/allwinner-h3* + ARM PrimeCell and CMSDK devices M: Peter Maydell <peter.maydell@linaro.org> L: qemu-arm@nongnu.org diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index XXXXXXX..XXXXXXX 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 select SERIAL select UNIMP +config ALLWINNER_H3 + bool + select ALLWINNER_A10_PIT + select SERIAL + select ARM_TIMER + select ARM_GIC + select UNIMP + config RASPI bool select FRAMEBUFFER -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Xunlong Orange Pi PC is an Allwinner H3 System on Chip based embedded computer with mainline support in both U-Boot and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz, 1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and various other I/O. This commit add support for the Xunlong Orange Pi PC machine. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: KONRAD Frederic <frederic.konrad@adacore.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/Makefile.objs | 2 +- hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 hw/arm/orangepi.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_DIGIC) += digic.o obj-$(CONFIG_OMAP) += omap1.o omap2.o obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/arm/orangepi.c @@ -XXX,XX +XXX,XX @@ +/* + * Orange Pi emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/arm/allwinner-h3.h" +#include "sysemu/sysemu.h" + +static struct arm_boot_info orangepi_binfo = { + .nb_cpus = AW_H3_NUM_CPUS, +}; + +static void orangepi_init(MachineState *machine) +{ + AwH3State *h3; + + /* BIOS is not supported by this board */ + if (bios_name) { + error_report("BIOS not supported for this machine"); + exit(1); + } + + /* This board has fixed size RAM */ + if (machine->ram_size != 1 * GiB) { + error_report("This machine can only be used with 1GiB of RAM"); + exit(1); + } + + /* Only allow Cortex-A7 for this board */ + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { + error_report("This board can only be used with cortex-a7 CPU"); + exit(1); + } + + h3 = AW_H3(object_new(TYPE_AW_H3)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(h3), + &error_abort); + object_unref(OBJECT(h3)); + + /* Setup timer properties */ + object_property_set_int(OBJECT(h3), 32768, "clk0-freq", + &error_abort); + object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq", + &error_abort); + + /* Mark H3 object realized */ + object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); + + /* SDRAM */ + memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], + machine->ram); + + orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM]; + orangepi_binfo.ram_size = machine->ram_size; + arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); +} + +static void orangepi_machine_init(MachineClass *mc) +{ + mc->desc = "Orange Pi PC"; + mc->init = orangepi_init; + mc->min_cpus = AW_H3_NUM_CPUS; + mc->max_cpus = AW_H3_NUM_CPUS; + mc->default_cpus = AW_H3_NUM_CPUS; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + mc->default_ram_size = 1 * GiB; + mc->default_ram_id = "orangepi.ram"; +} + +DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org S: Maintained F: hw/*/allwinner-h3* F: include/hw/*/allwinner-h3* +F: hw/arm/orangepi.c ARM PrimeCell and CMSDK devices M: Peter Maydell <peter.maydell@linaro.org> -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Clock Control Unit is responsible for clock signal generation, configuration and distribution in the Allwinner H3 System on Chip. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 3 + include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++ hw/arm/allwinner-h3.c | 9 +- hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++ 5 files changed, 320 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-h3-ccu.h create mode 100644 hw/misc/allwinner-h3-ccu.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" +#include "hw/misc/allwinner-h3-ccu.h" #include "target/arm/cpu.h" /** @@ -XXX,XX +XXX,XX @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_CCU, AW_H3_PIT, AW_H3_UART0, AW_H3_UART1, @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { ARMCPU cpus[AW_H3_NUM_CPUS]; const hwaddr *memmap; AwA10PITState timer; + AwH3ClockCtlState ccu; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner-h3-ccu.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/misc/allwinner-h3-ccu.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_H3_CCU_H +#define HW_MISC_ALLWINNER_H3_CCU_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by CCU device */ +#define AW_H3_CCU_IOSIZE (0x400) + +/** Total number of known registers */ +#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_H3_CCU "allwinner-h3-ccu" +#define AW_H3_CCU(obj) \ + OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU) + +/** @} */ + +/** + * Allwinner H3 CCU object instance state. + */ +typedef struct AwH3ClockCtlState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_H3_CCU_REGS_NUM]; + +} AwH3ClockCtlState; + +#endif /* HW_MISC_ALLWINNER_H3_CCU_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, [AW_H3_UART1] = 0x01c28400, @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "usb2-phy", 0x01c1c000, 4 * KiB }, { "usb3-phy", 0x01c1d000, 4 * KiB }, { "smc", 0x01c1e000, 4 * KiB }, - { "ccu", 0x01c20000, 1 * KiB }, { "pio", 0x01c20800, 1 * KiB }, { "owa", 0x01c21000, 1 * KiB }, { "pwm", 0x01c21400, 1 * KiB }, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) "clk0-freq", &error_abort); object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq", &error_abort); + + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), + TYPE_AW_H3_CCU); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], &s->sram_c); + /* Clock Control Unit */ + qdev_init_nofail(DEVICE(&s->ccu)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/misc/allwinner-h3-ccu.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 Clock Control Unit emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-ccu.h" + +/* CCU register offsets */ +enum { + REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */ + REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */ + REG_PLL_VIDEO = 0x0010, /* PLL Video Control */ + REG_PLL_VE = 0x0018, /* PLL VE Control */ + REG_PLL_DDR = 0x0020, /* PLL DDR Control */ + REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */ + REG_PLL_GPU = 0x0038, /* PLL GPU Control */ + REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */ + REG_PLL_DE = 0x0048, /* PLL Display Engine Control */ + REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */ + REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */ + REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */ + REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */ + REG_MBUS = 0x00FC, /* MBUS Reset */ + REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */ + REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */ + REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */ + REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */ + REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */ + REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */ + REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */ + REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */ + REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */ + REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */ + REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */ + REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */ + REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */ +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* CCU register flags */ +enum { + REG_DRAM_CFG_UPDATE = (1 << 16), +}; + +enum { + REG_PLL_ENABLE = (1 << 31), + REG_PLL_LOCK = (1 << 28), +}; + + +/* CCU register reset values */ +enum { + REG_PLL_CPUX_RST = 0x00001000, + REG_PLL_AUDIO_RST = 0x00035514, + REG_PLL_VIDEO_RST = 0x03006207, + REG_PLL_VE_RST = 0x03006207, + REG_PLL_DDR_RST = 0x00001000, + REG_PLL_PERIPH0_RST = 0x00041811, + REG_PLL_GPU_RST = 0x03006207, + REG_PLL_PERIPH1_RST = 0x00041811, + REG_PLL_DE_RST = 0x03006207, + REG_CPUX_AXI_RST = 0x00010000, + REG_APB1_RST = 0x00001010, + REG_APB2_RST = 0x01000000, + REG_DRAM_CFG_RST = 0x00000000, + REG_MBUS_RST = 0x80000000, + REG_PLL_TIME0_RST = 0x000000FF, + REG_PLL_TIME1_RST = 0x000000FF, + REG_PLL_CPUX_BIAS_RST = 0x08100200, + REG_PLL_AUDIO_BIAS_RST = 0x10100000, + REG_PLL_VIDEO_BIAS_RST = 0x10100000, + REG_PLL_VE_BIAS_RST = 0x10100000, + REG_PLL_DDR_BIAS_RST = 0x81104000, + REG_PLL_PERIPH0_BIAS_RST = 0x10100010, + REG_PLL_GPU_BIAS_RST = 0x10100000, + REG_PLL_PERIPH1_BIAS_RST = 0x10100010, + REG_PLL_DE_BIAS_RST = 0x10100000, + REG_PLL_CPUX_TUNING_RST = 0x0A101000, + REG_PLL_DDR_TUNING_RST = 0x14880000, +}; + +static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3ClockCtlState *s = AW_H3_CCU(opaque); + const uint32_t idx = REG_INDEX(offset); + + switch (offset) { + case 0x308 ... AW_H3_CCU_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_ccu_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3ClockCtlState *s = AW_H3_CCU(opaque); + const uint32_t idx = REG_INDEX(offset); + + switch (offset) { + case REG_DRAM_CFG: /* DRAM Configuration */ + val &= ~REG_DRAM_CFG_UPDATE; + break; + case REG_PLL_CPUX: /* PLL CPUX Control */ + case REG_PLL_AUDIO: /* PLL Audio Control */ + case REG_PLL_VIDEO: /* PLL Video Control */ + case REG_PLL_VE: /* PLL VE Control */ + case REG_PLL_DDR: /* PLL DDR Control */ + case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */ + case REG_PLL_GPU: /* PLL GPU Control */ + case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */ + case REG_PLL_DE: /* PLL Display Engine Control */ + if (val & REG_PLL_ENABLE) { + val |= REG_PLL_LOCK; + } + break; + case 0x308 ... AW_H3_CCU_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } + + s->regs[idx] = (uint32_t) val; +} + +static const MemoryRegionOps allwinner_h3_ccu_ops = { + .read = allwinner_h3_ccu_read, + .write = allwinner_h3_ccu_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_ccu_reset(DeviceState *dev) +{ + AwH3ClockCtlState *s = AW_H3_CCU(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST; + s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST; + s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST; + s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST; + s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST; + s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST; + s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST; + s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST; + s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST; + s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST; + s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST; + s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST; + s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST; + s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST; +} + +static void allwinner_h3_ccu_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3ClockCtlState *s = AW_H3_CCU(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s, + TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_ccu_vmstate = { + .name = "allwinner-h3-ccu", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_ccu_reset; + dc->vmsd = &allwinner_h3_ccu_vmstate; +} + +static const TypeInfo allwinner_h3_ccu_info = { + .name = TYPE_AW_H3_CCU, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_ccu_init, + .instance_size = sizeof(AwH3ClockCtlState), + .class_init = allwinner_h3_ccu_class_init, +}; + +static void allwinner_h3_ccu_register(void) +{ + type_register_static(&allwinner_h3_ccu_info); +} + +type_init(allwinner_h3_ccu_register) -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Allwinner H3 System on Chip contains multiple USB 2.0 bus connections which provide software access using the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI) interfaces. This commit adds support for both interfaces in the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/usb/hcd-ehci.h | 1 + include/hw/arm/allwinner-h3.h | 8 +++++++ hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++ hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++ hw/arm/Kconfig | 2 ++ 5 files changed, 72 insertions(+) diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index XXXXXXX..XXXXXXX 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -XXX,XX +XXX,XX @@ typedef struct EHCIPCIState { #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" #define TYPE_PLATFORM_EHCI "platform-ehci-usb" #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_EHCI0, + AW_H3_OHCI0, + AW_H3_EHCI1, + AW_H3_OHCI1, + AW_H3_EHCI2, + AW_H3_OHCI2, + AW_H3_EHCI3, + AW_H3_OHCI3, AW_H3_CCU, AW_H3_PIT, AW_H3_UART0, diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ #include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/misc/unimp.h" +#include "hw/usb/hcd-ehci.h" #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_EHCI0] = 0x01c1a000, + [AW_H3_OHCI0] = 0x01c1a400, + [AW_H3_EHCI1] = 0x01c1b000, + [AW_H3_OHCI1] = 0x01c1b400, + [AW_H3_EHCI2] = 0x01c1c000, + [AW_H3_OHCI2] = 0x01c1c400, + [AW_H3_EHCI3] = 0x01c1d000, + [AW_H3_OHCI3] = 0x01c1d400, [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, @@ -XXX,XX +XXX,XX @@ enum { AW_H3_GIC_SPI_UART3 = 3, AW_H3_GIC_SPI_TIMER0 = 18, AW_H3_GIC_SPI_TIMER1 = 19, + AW_H3_GIC_SPI_EHCI0 = 72, + AW_H3_GIC_SPI_OHCI0 = 73, + AW_H3_GIC_SPI_EHCI1 = 74, + AW_H3_GIC_SPI_OHCI1 = 75, + AW_H3_GIC_SPI_EHCI2 = 76, + AW_H3_GIC_SPI_OHCI2 = 77, + AW_H3_GIC_SPI_EHCI3 = 78, + AW_H3_GIC_SPI_OHCI3 = 79, }; /* Allwinner H3 general constants */ @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->ccu)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* Universal Serial Bus */ + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI0)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI1)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI2)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI3)); + + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI0)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI1)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI2)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI3)); + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index XXXXXXX..XXXXXXX 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_exynos4210_type_info = { .class_init = ehci_exynos4210_class_init, }; +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) +{ + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + sec->capsbase = 0x0; + sec->opregbase = 0x10; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo ehci_aw_h3_type_info = { + .name = TYPE_AW_H3_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_aw_h3_class_init, +}; + static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void) type_register_static(&ehci_type_info); type_register_static(&ehci_platform_type_info); type_register_static(&ehci_exynos4210_type_info); + type_register_static(&ehci_aw_h3_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); type_register_static(&ehci_fusbh200_type_info); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3 select ARM_TIMER select ARM_GIC select UNIMP + select USB_OHCI + select USB_EHCI_SYSBUS config RASPI bool -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Allwinner H3 System on Chip has an System Control module that provides system wide generic controls and device information. This commit adds support for the Allwinner H3 System Control module. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 3 + include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++ hw/arm/allwinner-h3.c | 9 +- hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++ 5 files changed, 219 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h create mode 100644 hw/misc/allwinner-h3-sysctrl.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-ccu.h" +#include "hw/misc/allwinner-h3-sysctrl.h" #include "target/arm/cpu.h" /** @@ -XXX,XX +XXX,XX @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_SYSCTRL, AW_H3_EHCI0, AW_H3_OHCI0, AW_H3_EHCI1, @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { const hwaddr *memmap; AwA10PITState timer; AwH3ClockCtlState ccu; + AwH3SysCtrlState sysctrl; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwinner-h3-sysctrl.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/misc/allwinner-h3-sysctrl.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 System Control emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H +#define HW_MISC_ALLWINNER_H3_SYSCTRL_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Highest register address used by System Control device */ +#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30) + +/** Total number of known registers */ +#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \ + sizeof(uint32_t)) + 1) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl" +#define AW_H3_SYSCTRL(obj) \ + OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL) + +/** @} */ + +/** + * Allwinner H3 System Control object instance state + */ +typedef struct AwH3SysCtrlState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_H3_SYSCTRL_REGS_NUM]; + +} AwH3SysCtrlState; + +#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_SYSCTRL] = 0x01c00000, [AW_H3_EHCI0] = 0x01c1a000, [AW_H3_OHCI0] = 0x01c1a400, [AW_H3_EHCI1] = 0x01c1b000, @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { } unimplemented[] = { { "d-engine", 0x01000000, 4 * MiB }, { "d-inter", 0x01400000, 128 * KiB }, - { "syscon", 0x01c00000, 4 * KiB }, { "dma", 0x01c02000, 4 * KiB }, { "nfdc", 0x01c03000, 4 * KiB }, { "ts", 0x01c06000, 4 * KiB }, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), TYPE_AW_H3_CCU); + + sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl), + TYPE_AW_H3_SYSCTRL); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->ccu)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* System Control */ + qdev_init_nofail(DEVICE(&s->sysctrl)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/misc/allwinner-h3-sysctrl.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 System Control emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-h3-sysctrl.h" + +/* System Control register offsets */ +enum { + REG_VER = 0x24, /* Version */ + REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */ +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* System Control register reset values */ +enum { + REG_VER_RST = 0x0, + REG_EMAC_PHY_CLK_RST = 0x58000, +}; + +static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_SYSCTRL_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_SYSCTRL_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_VER: /* Version */ + break; + default: + s->regs[idx] = (uint32_t) val; + break; + } +} + +static const MemoryRegionOps allwinner_h3_sysctrl_ops = { + .read = allwinner_h3_sysctrl_read, + .write = allwinner_h3_sysctrl_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_sysctrl_reset(DeviceState *dev) +{ + AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_VER)] = REG_VER_RST; + s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST; +} + +static void allwinner_h3_sysctrl_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s, + TYPE_AW_H3_SYSCTRL, 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_h3_sysctrl_vmstate = { + .name = "allwinner-h3-sysctrl", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_sysctrl_reset; + dc->vmsd = &allwinner_h3_sysctrl_vmstate; +} + +static const TypeInfo allwinner_h3_sysctrl_info = { + .name = TYPE_AW_H3_SYSCTRL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_sysctrl_init, + .instance_size = sizeof(AwH3SysCtrlState), + .class_init = allwinner_h3_sysctrl_class_init, +}; + +static void allwinner_h3_sysctrl_register(void) +{ + type_register_static(&allwinner_h3_sysctrl_info); +} + +type_init(allwinner_h3_sysctrl_register) -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> Various Allwinner System on Chip designs contain multiple processors that can be configured and reset using the generic CPU Configuration module interface. This commit adds support for the Allwinner CPU configuration interface which emulates the following features: * CPU reset * CPU status Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 3 + include/hw/misc/allwinner-cpucfg.h | 52 ++++++ hw/arm/allwinner-h3.c | 9 +- hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + 6 files changed, 351 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-cpucfg.h create mode 100644 hw/misc/allwinner-cpucfg.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_MACIO) += macio/ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o +obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-ccu.h" +#include "hw/misc/allwinner-cpucfg.h" #include "hw/misc/allwinner-h3-sysctrl.h" #include "target/arm/cpu.h" @@ -XXX,XX +XXX,XX @@ enum { AW_H3_GIC_CPU, AW_H3_GIC_HYP, AW_H3_GIC_VCPU, + AW_H3_CPUCFG, AW_H3_SDRAM }; @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { const hwaddr *memmap; AwA10PITState timer; AwH3ClockCtlState ccu; + AwCpuCfgState cpucfg; AwH3SysCtrlState sysctrl; GICState gic; MemoryRegion sram_a1; diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner-cpucfg.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/misc/allwinner-cpucfg.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner CPU Configuration Module emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_CPUCFG_H +#define HW_MISC_ALLWINNER_CPUCFG_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * Object model + * @{ + */ + +#define TYPE_AW_CPUCFG "allwinner-cpucfg" +#define AW_CPUCFG(obj) \ + OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG) + +/** @} */ + +/** + * Allwinner CPU Configuration Module instance state + */ +typedef struct AwCpuCfgState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t gen_ctrl; + uint32_t super_standby; + uint32_t entry_addr; + +} AwCpuCfgState; + +#endif /* HW_MISC_ALLWINNER_CPUCFG_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_GIC_CPU] = 0x01c82000, [AW_H3_GIC_HYP] = 0x01c84000, [AW_H3_GIC_VCPU] = 0x01c86000, + [AW_H3_CPUCFG] = 0x01f01c00, [AW_H3_SDRAM] = 0x40000000 }; @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "r_wdog", 0x01f01000, 1 * KiB }, { "r_prcm", 0x01f01400, 1 * KiB }, { "r_twd", 0x01f01800, 1 * KiB }, - { "r_cpucfg", 0x01f01c00, 1 * KiB }, { "r_cir-rx", 0x01f02000, 1 * KiB }, { "r_twi", 0x01f02400, 1 * KiB }, { "r_uart", 0x01f02800, 1 * KiB }, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl), TYPE_AW_H3_SYSCTRL); + + sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), + TYPE_AW_CPUCFG); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->sysctrl)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]); + /* CPU Configuration */ + qdev_init_nofail(DEVICE(&s->cpucfg)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/misc/allwinner-cpucfg.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner CPU Configuration Module emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "qemu/timer.h" +#include "hw/core/cpu.h" +#include "target/arm/arm-powerctl.h" +#include "target/arm/cpu.h" +#include "hw/misc/allwinner-cpucfg.h" +#include "trace.h" + +/* CPUCFG register offsets */ +enum { + REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */ + REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */ + REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */ + REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */ + REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */ + REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */ + REG_CPU1_STATUS = 0x0088, /* CPU#1 Status */ + REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */ + REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */ + REG_CPU2_STATUS = 0x00C8, /* CPU#2 Status */ + REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */ + REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */ + REG_CPU3_STATUS = 0x0108, /* CPU#3 Status */ + REG_CPU_SYS_RST = 0x0140, /* CPU System Reset */ + REG_CLK_GATING = 0x0144, /* CPU Clock Gating */ + REG_GEN_CTRL = 0x0184, /* General Control */ + REG_SUPER_STANDBY = 0x01A0, /* Super Standby Flag */ + REG_ENTRY_ADDR = 0x01A4, /* Reset Entry Address */ + REG_DBG_EXTERN = 0x01E4, /* Debug External */ + REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */ + REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */ + REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */ +}; + +/* CPUCFG register flags */ +enum { + CPUX_RESET_RELEASED = ((1 << 1) | (1 << 0)), + CPUX_STATUS_SMP = (1 << 0), + CPU_SYS_RESET_RELEASED = (1 << 0), + CLK_GATING_ENABLE = ((1 << 8) | 0xF), +}; + +/* CPUCFG register reset values */ +enum { + REG_CLK_GATING_RST = 0x0000010F, + REG_GEN_CTRL_RST = 0x00000020, + REG_SUPER_STANDBY_RST = 0x0, + REG_CNT64_CTRL_RST = 0x0, +}; + +/* CPUCFG constants */ +enum { + CPU_EXCEPTION_LEVEL_ON_RESET = 3, /* EL3 */ +}; + +static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id) +{ + int ret; + + trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr); + + ARMCPU *target_cpu = ARM_CPU(arm_get_cpu_by_id(cpu_id)); + if (!target_cpu) { + /* + * Called with a bogus value for cpu_id. Guest error will + * already have been logged, we can simply return here. + */ + return; + } + bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64); + + ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0, + CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64); + if (ret != QEMU_ARM_POWERCTL_RET_SUCCESS) { + error_report("%s: failed to bring up CPU %d: err %d", + __func__, cpu_id, ret); + return; + } +} + +static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwCpuCfgState *s = AW_CPUCFG(opaque); + uint64_t val = 0; + + switch (offset) { + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ + case REG_CPU_SYS_RST: /* CPU System Reset */ + val = CPU_SYS_RESET_RELEASED; + break; + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ + val = CPUX_RESET_RELEASED; + break; + case REG_CPU0_CTRL: /* CPU#0 Control */ + case REG_CPU1_CTRL: /* CPU#1 Control */ + case REG_CPU2_CTRL: /* CPU#2 Control */ + case REG_CPU3_CTRL: /* CPU#3 Control */ + val = 0; + break; + case REG_CPU0_STATUS: /* CPU#0 Status */ + case REG_CPU1_STATUS: /* CPU#1 Status */ + case REG_CPU2_STATUS: /* CPU#2 Status */ + case REG_CPU3_STATUS: /* CPU#3 Status */ + val = CPUX_STATUS_SMP; + break; + case REG_CLK_GATING: /* CPU Clock Gating */ + val = CLK_GATING_ENABLE; + break; + case REG_GEN_CTRL: /* General Control */ + val = s->gen_ctrl; + break; + case REG_SUPER_STANDBY: /* Super Standby Flag */ + val = s->super_standby; + break; + case REG_ENTRY_ADDR: /* Reset Entry Address */ + val = s->entry_addr; + break; + case REG_DBG_EXTERN: /* Debug External */ + case REG_CNT64_CTRL: /* 64-bit Counter Control */ + case REG_CNT64_LOW: /* 64-bit Counter Low */ + case REG_CNT64_HIGH: /* 64-bit Counter High */ + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } + + trace_allwinner_cpucfg_read(offset, val, size); + + return val; +} + +static void allwinner_cpucfg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwCpuCfgState *s = AW_CPUCFG(opaque); + + trace_allwinner_cpucfg_write(offset, val, size); + + switch (offset) { + case REG_CPUS_RST_CTRL: /* CPUs Reset Control */ + case REG_CPU_SYS_RST: /* CPU System Reset */ + break; + case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */ + case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */ + case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */ + case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */ + if (val) { + allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> 6); + } + break; + case REG_CPU0_CTRL: /* CPU#0 Control */ + case REG_CPU1_CTRL: /* CPU#1 Control */ + case REG_CPU2_CTRL: /* CPU#2 Control */ + case REG_CPU3_CTRL: /* CPU#3 Control */ + case REG_CPU0_STATUS: /* CPU#0 Status */ + case REG_CPU1_STATUS: /* CPU#1 Status */ + case REG_CPU2_STATUS: /* CPU#2 Status */ + case REG_CPU3_STATUS: /* CPU#3 Status */ + case REG_CLK_GATING: /* CPU Clock Gating */ + break; + case REG_GEN_CTRL: /* General Control */ + s->gen_ctrl = val; + break; + case REG_SUPER_STANDBY: /* Super Standby Flag */ + s->super_standby = val; + break; + case REG_ENTRY_ADDR: /* Reset Entry Address */ + s->entry_addr = val; + break; + case REG_DBG_EXTERN: /* Debug External */ + case REG_CNT64_CTRL: /* 64-bit Counter Control */ + case REG_CNT64_LOW: /* 64-bit Counter Low */ + case REG_CNT64_HIGH: /* 64-bit Counter High */ + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } +} + +static const MemoryRegionOps allwinner_cpucfg_ops = { + .read = allwinner_cpucfg_read, + .write = allwinner_cpucfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_cpucfg_reset(DeviceState *dev) +{ + AwCpuCfgState *s = AW_CPUCFG(dev); + + /* Set default values for registers */ + s->gen_ctrl = REG_GEN_CTRL_RST; + s->super_standby = REG_SUPER_STANDBY_RST; + s->entry_addr = 0; +} + +static void allwinner_cpucfg_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwCpuCfgState *s = AW_CPUCFG(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s, + TYPE_AW_CPUCFG, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_cpucfg_vmstate = { + .name = "allwinner-cpucfg", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(gen_ctrl, AwCpuCfgState), + VMSTATE_UINT32(super_standby, AwCpuCfgState), + VMSTATE_UINT32(entry_addr, AwCpuCfgState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_cpucfg_reset; + dc->vmsd = &allwinner_cpucfg_vmstate; +} + +static const TypeInfo allwinner_cpucfg_info = { + .name = TYPE_AW_CPUCFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_cpucfg_init, + .instance_size = sizeof(AwCpuCfgState), + .class_init = allwinner_cpucfg_class_init, +}; + +static void allwinner_cpucfg_register(void) +{ + type_register_static(&allwinner_cpucfg_info); +} + +type_init(allwinner_cpucfg_register) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -XXX,XX +XXX,XX @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-cpucfg.c +allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIu32 +allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Security Identifier device found in various Allwinner System on Chip designs gives applications a per-board unique identifier. This commit adds support for the Allwinner Security Identifier using a 128-bit UUID value as input. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 3 + include/hw/misc/allwinner-sid.h | 60 ++++++++++++ hw/arm/allwinner-h3.c | 11 ++- hw/arm/orangepi.c | 8 ++ hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++ hw/misc/trace-events | 4 + 7 files changed, 254 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/allwinner-sid.h create mode 100644 hw/misc/allwinner-sid.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o common-obj-$(CONFIG_NSERIES) += cbus.o common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/allwinner-h3-ccu.h" #include "hw/misc/allwinner-cpucfg.h" #include "hw/misc/allwinner-h3-sysctrl.h" +#include "hw/misc/allwinner-sid.h" #include "target/arm/cpu.h" /** @@ -XXX,XX +XXX,XX @@ enum { AW_H3_SRAM_A2, AW_H3_SRAM_C, AW_H3_SYSCTRL, + AW_H3_SID, AW_H3_EHCI0, AW_H3_OHCI0, AW_H3_EHCI1, @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { AwH3ClockCtlState ccu; AwCpuCfgState cpucfg; AwH3SysCtrlState sysctrl; + AwSidState sid; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-sid.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/misc/allwinner-sid.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner Security ID emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_SID_H +#define HW_MISC_ALLWINNER_SID_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "qemu/uuid.h" + +/** + * Object model + * @{ + */ + +#define TYPE_AW_SID "allwinner-sid" +#define AW_SID(obj) \ + OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID) + +/** @} */ + +/** + * Allwinner Security ID object instance state + */ +typedef struct AwSidState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Control register defines how and what to read */ + uint32_t control; + + /** RdKey register contains the data retrieved by the device */ + uint32_t rdkey; + + /** Stores the emulated device identifier */ + QemuUUID identifier; + +} AwSidState; + +#endif /* HW_MISC_ALLWINNER_SID_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, [AW_H3_SYSCTRL] = 0x01c00000, + [AW_H3_SID] = 0x01c14000, [AW_H3_EHCI0] = 0x01c1a000, [AW_H3_OHCI0] = 0x01c1a400, [AW_H3_EHCI1] = 0x01c1b000, @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "mmc0", 0x01c0f000, 4 * KiB }, { "mmc1", 0x01c10000, 4 * KiB }, { "mmc2", 0x01c11000, 4 * KiB }, - { "sid", 0x01c14000, 1 * KiB }, { "crypto", 0x01c15000, 4 * KiB }, { "msgbox", 0x01c17000, 4 * KiB }, { "spinlock", 0x01c18000, 4 * KiB }, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), TYPE_AW_CPUCFG); + + sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), + TYPE_AW_SID); + object_property_add_alias(obj, "identifier", OBJECT(&s->sid), + "identifier", &error_abort); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->cpucfg)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); + /* Security Identifier */ + qdev_init_nofail(DEVICE(&s->sid)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq", &error_abort); + /* Setup SID properties. Currently using a default fixed SID identifier. */ + if (qemu_uuid_is_null(&h3->sid.identifier)) { + qdev_prop_set_string(DEVICE(h3), "identifier", + "02c00081-1111-2222-3333-000044556677"); + } else if (ldl_be_p(&h3->sid.identifier.data[0]) != 0x02c00081) { + warn_report("Security Identifier value does not include H3 prefix"); + } + /* Mark H3 object realized */ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/misc/allwinner-sid.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner Security ID emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/misc/allwinner-sid.h" +#include "trace.h" + +/* SID register offsets */ +enum { + REG_PRCTL = 0x40, /* Control */ + REG_RDKEY = 0x60, /* Read Key */ +}; + +/* SID register flags */ +enum { + REG_PRCTL_WRITE = 0x0002, /* Unknown write flag */ + REG_PRCTL_OP_LOCK = 0xAC00, /* Lock operation */ +}; + +static uint64_t allwinner_sid_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwSidState *s = AW_SID(opaque); + uint64_t val = 0; + + switch (offset) { + case REG_PRCTL: /* Control */ + val = s->control; + break; + case REG_RDKEY: /* Read Key */ + val = s->rdkey; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_sid_read(offset, val, size); + + return val; +} + +static void allwinner_sid_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwSidState *s = AW_SID(opaque); + + trace_allwinner_sid_write(offset, val, size); + + switch (offset) { + case REG_PRCTL: /* Control */ + s->control = val; + + if ((s->control & REG_PRCTL_OP_LOCK) && + (s->control & REG_PRCTL_WRITE)) { + uint32_t id = s->control >> 16; + + if (id <= sizeof(QemuUUID) - sizeof(s->rdkey)) { + s->rdkey = ldl_be_p(&s->identifier.data[id]); + } + } + s->control &= ~REG_PRCTL_WRITE; + break; + case REG_RDKEY: /* Read Key */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } +} + +static const MemoryRegionOps allwinner_sid_ops = { + .read = allwinner_sid_read, + .write = allwinner_sid_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_sid_reset(DeviceState *dev) +{ + AwSidState *s = AW_SID(dev); + + /* Set default values for registers */ + s->control = 0; + s->rdkey = 0; +} + +static void allwinner_sid_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwSidState *s = AW_SID(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s, + TYPE_AW_SID, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static Property allwinner_sid_properties[] = { + DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription allwinner_sid_vmstate = { + .name = "allwinner-sid", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(control, AwSidState), + VMSTATE_UINT32(rdkey, AwSidState), + VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID), 1), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_sid_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_sid_reset; + dc->vmsd = &allwinner_sid_vmstate; + device_class_set_props(dc, allwinner_sid_properties); +} + +static const TypeInfo allwinner_sid_info = { + .name = TYPE_AW_SID, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_sid_init, + .instance_size = sizeof(AwSidState), + .class_init = allwinner_sid_class_init, +}; + +static void allwinner_sid_register(void) +{ + type_register_static(&allwinner_sid_info); +} + +type_init(allwinner_sid_register) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +# allwinner-sid.c +allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Allwinner System on Chip families sun4i and above contain an integrated storage controller for Secure Digital (SD) and Multi Media Card (MMC) interfaces. This commit adds support for the Allwinner SD/MMC storage controller with the following emulated features: * DMA transfers * Direct FIFO I/O * Short/Long format command responses * Auto-Stop command (CMD12) * Insert & remove card detection The following boards are extended with the SD host controller: * Cubieboard (hw/arm/cubieboard.c) * Orange Pi PC (hw/arm/orangepi.c) Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/sd/Makefile.objs | 1 + include/hw/arm/allwinner-a10.h | 2 + include/hw/arm/allwinner-h3.h | 3 + include/hw/sd/allwinner-sdhost.h | 135 +++++ hw/arm/allwinner-a10.c | 11 + hw/arm/allwinner-h3.c | 15 +- hw/arm/cubieboard.c | 15 + hw/arm/orangepi.c | 16 + hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/sd/trace-events | 7 + 11 files changed, 1059 insertions(+), 1 deletion(-) create mode 100644 include/hw/sd/allwinner-sdhost.h create mode 100644 hw/sd/allwinner-sdhost.c diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o common-obj-$(CONFIG_SDHCI) += sdhci.o common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o common-obj-$(CONFIG_OMAP) += omap_mmc.o common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -XXX,XX +XXX,XX @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/allwinner-a10-pic.h" #include "hw/net/allwinner_emac.h" +#include "hw/sd/allwinner-sdhost.h" #include "hw/ide/ahci.h" #include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ehci.h" @@ -XXX,XX +XXX,XX @@ typedef struct AwA10State { AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; + AwSdHostState mmc0; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/allwinner-cpucfg.h" #include "hw/misc/allwinner-h3-sysctrl.h" #include "hw/misc/allwinner-sid.h" +#include "hw/sd/allwinner-sdhost.h" #include "target/arm/cpu.h" /** @@ -XXX,XX +XXX,XX @@ enum { AW_H3_SRAM_A2, AW_H3_SRAM_C, AW_H3_SYSCTRL, + AW_H3_MMC0, AW_H3_SID, AW_H3_EHCI0, AW_H3_OHCI0, @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { AwCpuCfgState cpucfg; AwH3SysCtrlState sysctrl; AwSidState sid; + AwSdHostState mmc0; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/sd/allwinner-sdhost.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner (sun4i and above) SD Host Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SD_ALLWINNER_SDHOST_H +#define HW_SD_ALLWINNER_SDHOST_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/sd/sd.h" + +/** + * Object model types + * @{ + */ + +/** Generic Allwinner SD Host Controller (abstract) */ +#define TYPE_AW_SDHOST "allwinner-sdhost" + +/** Allwinner sun4i family (A10, A12) */ +#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i" + +/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */ +#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i" + +/** @} */ + +/** + * Object model macros + * @{ + */ + +#define AW_SDHOST(obj) \ + OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST) +#define AW_SDHOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST) +#define AW_SDHOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST) + +/** @} */ + +/** + * Allwinner SD Host Controller object instance state. + */ +typedef struct AwSdHostState { + /*< private >*/ + SysBusDevice busdev; + /*< public >*/ + + /** Secure Digital (SD) bus, which connects to SD card (if present) */ + SDBus sdbus; + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Interrupt output signal to notify CPU */ + qemu_irq irq; + + /** Number of bytes left in current DMA transfer */ + uint32_t transfer_cnt; + + /** + * @name Hardware Registers + * @{ + */ + + uint32_t global_ctl; /**< Global Control */ + uint32_t clock_ctl; /**< Clock Control */ + uint32_t timeout; /**< Timeout */ + uint32_t bus_width; /**< Bus Width */ + uint32_t block_size; /**< Block Size */ + uint32_t byte_count; /**< Byte Count */ + + uint32_t command; /**< Command */ + uint32_t command_arg; /**< Command Argument */ + uint32_t response[4]; /**< Command Response */ + + uint32_t irq_mask; /**< Interrupt Mask */ + uint32_t irq_status; /**< Raw Interrupt Status */ + uint32_t status; /**< Status */ + + uint32_t fifo_wlevel; /**< FIFO Water Level */ + uint32_t fifo_func_sel; /**< FIFO Function Select */ + uint32_t debug_enable; /**< Debug Enable */ + uint32_t auto12_arg; /**< Auto Command 12 Argument */ + uint32_t newtiming_set; /**< SD New Timing Set */ + uint32_t newtiming_debug; /**< SD New Timing Debug */ + uint32_t hardware_rst; /**< Hardware Reset */ + uint32_t dmac; /**< Internal DMA Controller Control */ + uint32_t desc_base; /**< Descriptor List Base Address */ + uint32_t dmac_status; /**< Internal DMA Controller Status */ + uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */ + uint32_t card_threshold; /**< Card Threshold Control */ + uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */ + uint32_t response_crc; /**< Response CRC */ + uint32_t data_crc[8]; /**< Data CRC */ + uint32_t status_crc; /**< Status CRC */ + + /** @} */ + +} AwSdHostState; + +/** + * Allwinner SD Host Controller class-level struct. + * + * This struct is filled by each sunxi device specific code + * such that the generic code can use this struct to support + * all devices. + */ +typedef struct AwSdHostClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + /** Maximum buffer size in bytes per DMA descriptor */ + size_t max_desc_size; + +} AwSdHostClass; + +#endif /* HW_SD_ALLWINNER_SDHOST_H */ diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -XXX,XX +XXX,XX @@ #include "hw/boards.h" #include "hw/usb/hcd-ohci.h" +#define AW_A10_MMC0_BASE 0x01c0f000 #define AW_A10_PIC_REG_BASE 0x01c20400 #define AW_A10_PIT_REG_BASE 0x01c20c00 #define AW_A10_UART0_REG_BASE 0x01c28000 @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI); } } + + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), + TYPE_AW_SDHOST_SUN4I); } static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(dev, 64 + i)); } } + + /* SD/MMC */ + qdev_init_nofail(DEVICE(&s->mmc0)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), + "sd-bus", &error_abort); } static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, [AW_H3_SYSCTRL] = 0x01c00000, + [AW_H3_MMC0] = 0x01c0f000, [AW_H3_SID] = 0x01c14000, [AW_H3_EHCI0] = 0x01c1a000, [AW_H3_OHCI0] = 0x01c1a400, @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "lcd0", 0x01c0c000, 4 * KiB }, { "lcd1", 0x01c0d000, 4 * KiB }, { "ve", 0x01c0e000, 4 * KiB }, - { "mmc0", 0x01c0f000, 4 * KiB }, { "mmc1", 0x01c10000, 4 * KiB }, { "mmc2", 0x01c11000, 4 * KiB }, { "crypto", 0x01c15000, 4 * KiB }, @@ -XXX,XX +XXX,XX @@ enum { AW_H3_GIC_SPI_UART3 = 3, AW_H3_GIC_SPI_TIMER0 = 18, AW_H3_GIC_SPI_TIMER1 = 19, + AW_H3_GIC_SPI_MMC0 = 60, AW_H3_GIC_SPI_EHCI0 = 72, AW_H3_GIC_SPI_OHCI0 = 73, AW_H3_GIC_SPI_EHCI1 = 74, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) TYPE_AW_SID); object_property_add_alias(obj, "identifier", OBJECT(&s->sid), "identifier", &error_abort); + + sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), + TYPE_AW_SDHOST_SUN5I); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->sid)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); + /* SD/MMC */ + qdev_init_nofail(DEVICE(&s->mmc0)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0)); + + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), + "sd-bus", &error_abort); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -XXX,XX +XXX,XX @@ #include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "hw/boards.h" +#include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" static struct arm_boot_info cubieboard_binfo = { @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) { AwA10State *a10; Error *err = NULL; + DriveInfo *di; + BlockBackend *blk; + BusState *bus; + DeviceState *carddev; /* BIOS is not supported by this board */ if (bios_name) { @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) exit(1); } + /* Retrieve SD bus */ + di = drive_get_next(IF_SD); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + bus = qdev_get_child_bus(DEVICE(a10), "sd-bus"); + + /* Plug in SD card */ + carddev = qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); + memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE, machine->ram); diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info orangepi_binfo = { static void orangepi_init(MachineState *machine) { AwH3State *h3; + DriveInfo *di; + BlockBackend *blk; + BusState *bus; + DeviceState *carddev; /* BIOS is not supported by this board */ if (bios_name) { @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) /* Mark H3 object realized */ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); + /* Retrieve SD bus */ + di = drive_get_next(IF_SD); + blk = di ? blk_by_legacy_dinfo(di) : NULL; + bus = qdev_get_child_bus(DEVICE(h3), "sd-bus"); + + /* Plug in SD card */ + carddev = qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); + /* SDRAM */ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], machine->ram); @@ -XXX,XX +XXX,XX @@ static void orangepi_machine_init(MachineClass *mc) { mc->desc = "Orange Pi PC"; mc->init = orangepi_init; + mc->block_default_type = IF_SD; + mc->units_per_default_bus = 1; mc->min_cpus = AW_H3_NUM_CPUS; mc->max_cpus = AW_H3_NUM_CPUS; mc->default_cpus = AW_H3_NUM_CPUS; diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/sd/allwinner-sdhost.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner (sun4i and above) SD Host Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "sysemu/blockdev.h" +#include "hw/irq.h" +#include "hw/sd/allwinner-sdhost.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus" +#define AW_SDHOST_BUS(obj) \ + OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS) + +/* SD Host register offsets */ +enum { + REG_SD_GCTL = 0x00, /* Global Control */ + REG_SD_CKCR = 0x04, /* Clock Control */ + REG_SD_TMOR = 0x08, /* Timeout */ + REG_SD_BWDR = 0x0C, /* Bus Width */ + REG_SD_BKSR = 0x10, /* Block Size */ + REG_SD_BYCR = 0x14, /* Byte Count */ + REG_SD_CMDR = 0x18, /* Command */ + REG_SD_CAGR = 0x1C, /* Command Argument */ + REG_SD_RESP0 = 0x20, /* Response Zero */ + REG_SD_RESP1 = 0x24, /* Response One */ + REG_SD_RESP2 = 0x28, /* Response Two */ + REG_SD_RESP3 = 0x2C, /* Response Three */ + REG_SD_IMKR = 0x30, /* Interrupt Mask */ + REG_SD_MISR = 0x34, /* Masked Interrupt Status */ + REG_SD_RISR = 0x38, /* Raw Interrupt Status */ + REG_SD_STAR = 0x3C, /* Status */ + REG_SD_FWLR = 0x40, /* FIFO Water Level */ + REG_SD_FUNS = 0x44, /* FIFO Function Select */ + REG_SD_DBGC = 0x50, /* Debug Enable */ + REG_SD_A12A = 0x58, /* Auto command 12 argument */ + REG_SD_NTSR = 0x5C, /* SD NewTiming Set */ + REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */ + REG_SD_HWRST = 0x78, /* Hardware Reset Register */ + REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */ + REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ + REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ + REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ + REG_SD_THLDC = 0x100, /* Card Threshold Control */ + REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ + REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ + REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ + REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */ + REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */ + REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */ + REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */ + REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */ + REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */ + REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */ + REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */ + REG_SD_FIFO = 0x200, /* Read/Write FIFO */ +}; + +/* SD Host register flags */ +enum { + SD_GCTL_FIFO_AC_MOD = (1 << 31), + SD_GCTL_DDR_MOD_SEL = (1 << 10), + SD_GCTL_CD_DBC_ENB = (1 << 8), + SD_GCTL_DMA_ENB = (1 << 5), + SD_GCTL_INT_ENB = (1 << 4), + SD_GCTL_DMA_RST = (1 << 2), + SD_GCTL_FIFO_RST = (1 << 1), + SD_GCTL_SOFT_RST = (1 << 0), +}; + +enum { + SD_CMDR_LOAD = (1 << 31), + SD_CMDR_CLKCHANGE = (1 << 21), + SD_CMDR_WRITE = (1 << 10), + SD_CMDR_AUTOSTOP = (1 << 12), + SD_CMDR_DATA = (1 << 9), + SD_CMDR_RESPONSE_LONG = (1 << 7), + SD_CMDR_RESPONSE = (1 << 6), + SD_CMDR_CMDID_MASK = (0x3f), +}; + +enum { + SD_RISR_CARD_REMOVE = (1 << 31), + SD_RISR_CARD_INSERT = (1 << 30), + SD_RISR_SDIO_INTR = (1 << 16), + SD_RISR_AUTOCMD_DONE = (1 << 14), + SD_RISR_DATA_COMPLETE = (1 << 3), + SD_RISR_CMD_COMPLETE = (1 << 2), + SD_RISR_NO_RESPONSE = (1 << 1), +}; + +enum { + SD_STAR_CARD_PRESENT = (1 << 8), +}; + +enum { + SD_IDST_INT_SUMMARY = (1 << 8), + SD_IDST_RECEIVE_IRQ = (1 << 1), + SD_IDST_TRANSMIT_IRQ = (1 << 0), + SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8), + SD_IDST_WR_MASK = (0x3ff), +}; + +/* SD Host register reset values */ +enum { + REG_SD_GCTL_RST = 0x00000300, + REG_SD_CKCR_RST = 0x0, + REG_SD_TMOR_RST = 0xFFFFFF40, + REG_SD_BWDR_RST = 0x0, + REG_SD_BKSR_RST = 0x00000200, + REG_SD_BYCR_RST = 0x00000200, + REG_SD_CMDR_RST = 0x0, + REG_SD_CAGR_RST = 0x0, + REG_SD_RESP_RST = 0x0, + REG_SD_IMKR_RST = 0x0, + REG_SD_MISR_RST = 0x0, + REG_SD_RISR_RST = 0x0, + REG_SD_STAR_RST = 0x00000100, + REG_SD_FWLR_RST = 0x000F0000, + REG_SD_FUNS_RST = 0x0, + REG_SD_DBGC_RST = 0x0, + REG_SD_A12A_RST = 0x0000FFFF, + REG_SD_NTSR_RST = 0x00000001, + REG_SD_SDBG_RST = 0x0, + REG_SD_HWRST_RST = 0x00000001, + REG_SD_DMAC_RST = 0x0, + REG_SD_DLBA_RST = 0x0, + REG_SD_IDST_RST = 0x0, + REG_SD_IDIE_RST = 0x0, + REG_SD_THLDC_RST = 0x0, + REG_SD_DSBD_RST = 0x0, + REG_SD_RES_CRC_RST = 0x0, + REG_SD_DATA_CRC_RST = 0x0, + REG_SD_CRC_STA_RST = 0x0, + REG_SD_FIFO_RST = 0x0, +}; + +/* Data transfer descriptor for DMA */ +typedef struct TransferDescriptor { + uint32_t status; /* Status flags */ + uint32_t size; /* Data buffer size */ + uint32_t addr; /* Data buffer address */ + uint32_t next; /* Physical address of next descriptor */ +} TransferDescriptor; + +/* Data transfer descriptor flags */ +enum { + DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */ + DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */ + DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */ + DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */ + DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */ + DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */ + DESC_SIZE_MASK = (0xfffffffc) +}; + +static void allwinner_sdhost_update_irq(AwSdHostState *s) +{ + uint32_t irq; + + if (s->global_ctl & SD_GCTL_INT_ENB) { + irq = s->irq_status & s->irq_mask; + } else { + irq = 0; + } + + trace_allwinner_sdhost_update_irq(irq); + qemu_set_irq(s->irq, irq); +} + +static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s, + uint32_t bytes) +{ + if (s->transfer_cnt > bytes) { + s->transfer_cnt -= bytes; + } else { + s->transfer_cnt = 0; + } + + if (!s->transfer_cnt) { + s->irq_status |= SD_RISR_DATA_COMPLETE; + } +} + +static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted) +{ + AwSdHostState *s = AW_SDHOST(dev); + + trace_allwinner_sdhost_set_inserted(inserted); + + if (inserted) { + s->irq_status |= SD_RISR_CARD_INSERT; + s->irq_status &= ~SD_RISR_CARD_REMOVE; + s->status |= SD_STAR_CARD_PRESENT; + } else { + s->irq_status &= ~SD_RISR_CARD_INSERT; + s->irq_status |= SD_RISR_CARD_REMOVE; + s->status &= ~SD_STAR_CARD_PRESENT; + } + + allwinner_sdhost_update_irq(s); +} + +static void allwinner_sdhost_send_command(AwSdHostState *s) +{ + SDRequest request; + uint8_t resp[16]; + int rlen; + + /* Auto clear load flag */ + s->command &= ~SD_CMDR_LOAD; + + /* Clock change does not actually interact with the SD bus */ + if (!(s->command & SD_CMDR_CLKCHANGE)) { + + /* Prepare request */ + request.cmd = s->command & SD_CMDR_CMDID_MASK; + request.arg = s->command_arg; + + /* Send request to SD bus */ + rlen = sdbus_do_command(&s->sdbus, &request, resp); + if (rlen < 0) { + goto error; + } + + /* If the command has a response, store it in the response registers */ + if ((s->command & SD_CMDR_RESPONSE)) { + if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) { + s->response[0] = ldl_be_p(&resp[0]); + s->response[1] = s->response[2] = s->response[3] = 0; + + } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) { + s->response[0] = ldl_be_p(&resp[12]); + s->response[1] = ldl_be_p(&resp[8]); + s->response[2] = ldl_be_p(&resp[4]); + s->response[3] = ldl_be_p(&resp[0]); + } else { + goto error; + } + } + } + + /* Set interrupt status bits */ + s->irq_status |= SD_RISR_CMD_COMPLETE; + return; + +error: + s->irq_status |= SD_RISR_NO_RESPONSE; +} + +static void allwinner_sdhost_auto_stop(AwSdHostState *s) +{ + /* + * The stop command (CMD12) ensures the SD bus + * returns to the transfer state. + */ + if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { + /* First save current command registers */ + uint32_t saved_cmd = s->command; + uint32_t saved_arg = s->command_arg; + + /* Prepare stop command (CMD12) */ + s->command &= ~SD_CMDR_CMDID_MASK; + s->command |= 12; /* CMD12 */ + s->command_arg = 0; + + /* Put the command on SD bus */ + allwinner_sdhost_send_command(s); + + /* Restore command values */ + s->command = saved_cmd; + s->command_arg = saved_arg; + + /* Set IRQ status bit for automatic stop done */ + s->irq_status |= SD_RISR_AUTOCMD_DONE; + } +} + +static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, + hwaddr desc_addr, + TransferDescriptor *desc, + bool is_write, uint32_t max_bytes) +{ + AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s); + uint32_t num_done = 0; + uint32_t num_bytes = max_bytes; + uint8_t buf[1024]; + + /* Read descriptor */ + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); + if (desc->size == 0) { + desc->size = klass->max_desc_size; + } else if (desc->size > klass->max_desc_size) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size " + " is out-of-bounds: %" PRIu32 " > %zu", + __func__, desc->size, klass->max_desc_size); + desc->size = klass->max_desc_size; + } + if (desc->size < num_bytes) { + num_bytes = desc->size; + } + + trace_allwinner_sdhost_process_desc(desc_addr, desc->size, + is_write, max_bytes); + + while (num_done < num_bytes) { + /* Try to completely fill the local buffer */ + uint32_t buf_bytes = num_bytes - num_done; + if (buf_bytes > sizeof(buf)) { + buf_bytes = sizeof(buf); + } + + /* Write to SD bus */ + if (is_write) { + cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done, + buf, buf_bytes); + + for (uint32_t i = 0; i < buf_bytes; i++) { + sdbus_write_data(&s->sdbus, buf[i]); + } + + /* Read from SD bus */ + } else { + for (uint32_t i = 0; i < buf_bytes; i++) { + buf[i] = sdbus_read_data(&s->sdbus); + } + cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done, + buf, buf_bytes); + } + num_done += buf_bytes; + } + + /* Clear hold flag and flush descriptor */ + desc->status &= ~DESC_STATUS_HOLD; + cpu_physical_memory_write(desc_addr, desc, sizeof(*desc)); + + return num_done; +} + +static void allwinner_sdhost_dma(AwSdHostState *s) +{ + TransferDescriptor desc; + hwaddr desc_addr = s->desc_base; + bool is_write = (s->command & SD_CMDR_WRITE); + uint32_t bytes_done = 0; + + /* Check if DMA can be performed */ + if (s->byte_count == 0 || s->block_size == 0 || + !(s->global_ctl & SD_GCTL_DMA_ENB)) { + return; + } + + /* + * For read operations, data must be available on the SD bus + * If not, it is an error and we should not act at all + */ + if (!is_write && !sdbus_data_ready(&s->sdbus)) { + return; + } + + /* Process the DMA descriptors until all data is copied */ + while (s->byte_count > 0) { + bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc, + is_write, s->byte_count); + allwinner_sdhost_update_transfer_cnt(s, bytes_done); + + if (bytes_done <= s->byte_count) { + s->byte_count -= bytes_done; + } else { + s->byte_count = 0; + } + + if (desc.status & DESC_STATUS_LAST) { + break; + } else { + desc_addr = desc.next; + } + } + + /* Raise IRQ to signal DMA is completed */ + s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR; + + /* Update DMAC bits */ + s->dmac_status |= SD_IDST_INT_SUMMARY; + + if (is_write) { + s->dmac_status |= SD_IDST_TRANSMIT_IRQ; + } else { + s->dmac_status |= SD_IDST_RECEIVE_IRQ; + } +} + +static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwSdHostState *s = AW_SDHOST(opaque); + uint32_t res = 0; + + switch (offset) { + case REG_SD_GCTL: /* Global Control */ + res = s->global_ctl; + break; + case REG_SD_CKCR: /* Clock Control */ + res = s->clock_ctl; + break; + case REG_SD_TMOR: /* Timeout */ + res = s->timeout; + break; + case REG_SD_BWDR: /* Bus Width */ + res = s->bus_width; + break; + case REG_SD_BKSR: /* Block Size */ + res = s->block_size; + break; + case REG_SD_BYCR: /* Byte Count */ + res = s->byte_count; + break; + case REG_SD_CMDR: /* Command */ + res = s->command; + break; + case REG_SD_CAGR: /* Command Argument */ + res = s->command_arg; + break; + case REG_SD_RESP0: /* Response Zero */ + res = s->response[0]; + break; + case REG_SD_RESP1: /* Response One */ + res = s->response[1]; + break; + case REG_SD_RESP2: /* Response Two */ + res = s->response[2]; + break; + case REG_SD_RESP3: /* Response Three */ + res = s->response[3]; + break; + case REG_SD_IMKR: /* Interrupt Mask */ + res = s->irq_mask; + break; + case REG_SD_MISR: /* Masked Interrupt Status */ + res = s->irq_status & s->irq_mask; + break; + case REG_SD_RISR: /* Raw Interrupt Status */ + res = s->irq_status; + break; + case REG_SD_STAR: /* Status */ + res = s->status; + break; + case REG_SD_FWLR: /* FIFO Water Level */ + res = s->fifo_wlevel; + break; + case REG_SD_FUNS: /* FIFO Function Select */ + res = s->fifo_func_sel; + break; + case REG_SD_DBGC: /* Debug Enable */ + res = s->debug_enable; + break; + case REG_SD_A12A: /* Auto command 12 argument */ + res = s->auto12_arg; + break; + case REG_SD_NTSR: /* SD NewTiming Set */ + res = s->newtiming_set; + break; + case REG_SD_SDBG: /* SD newTiming Set Debug */ + res = s->newtiming_debug; + break; + case REG_SD_HWRST: /* Hardware Reset Register */ + res = s->hardware_rst; + break; + case REG_SD_DMAC: /* Internal DMA Controller Control */ + res = s->dmac; + break; + case REG_SD_DLBA: /* Descriptor List Base Address */ + res = s->desc_base; + break; + case REG_SD_IDST: /* Internal DMA Controller Status */ + res = s->dmac_status; + break; + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ + res = s->dmac_irq; + break; + case REG_SD_THLDC: /* Card Threshold Control */ + res = s->card_threshold; + break; + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ + res = s->startbit_detect; + break; + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ + res = s->response_crc; + break; + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ + res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; + break; + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ + res = s->status_crc; + break; + case REG_SD_FIFO: /* Read/Write FIFO */ + if (sdbus_data_ready(&s->sdbus)) { + res = sdbus_read_data(&s->sdbus); + res |= sdbus_read_data(&s->sdbus) << 8; + res |= sdbus_read_data(&s->sdbus) << 16; + res |= sdbus_read_data(&s->sdbus) << 24; + allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + allwinner_sdhost_auto_stop(s); + allwinner_sdhost_update_irq(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", + __func__); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" + HWADDR_PRIx"\n", __func__, offset); + res = 0; + break; + } + + trace_allwinner_sdhost_read(offset, res, size); + return res; +} + +static void allwinner_sdhost_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + AwSdHostState *s = AW_SDHOST(opaque); + + trace_allwinner_sdhost_write(offset, value, size); + + switch (offset) { + case REG_SD_GCTL: /* Global Control */ + s->global_ctl = value; + s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | + SD_GCTL_SOFT_RST); + allwinner_sdhost_update_irq(s); + break; + case REG_SD_CKCR: /* Clock Control */ + s->clock_ctl = value; + break; + case REG_SD_TMOR: /* Timeout */ + s->timeout = value; + break; + case REG_SD_BWDR: /* Bus Width */ + s->bus_width = value; + break; + case REG_SD_BKSR: /* Block Size */ + s->block_size = value; + break; + case REG_SD_BYCR: /* Byte Count */ + s->byte_count = value; + s->transfer_cnt = value; + break; + case REG_SD_CMDR: /* Command */ + s->command = value; + if (value & SD_CMDR_LOAD) { + allwinner_sdhost_send_command(s); + allwinner_sdhost_dma(s); + allwinner_sdhost_auto_stop(s); + } + allwinner_sdhost_update_irq(s); + break; + case REG_SD_CAGR: /* Command Argument */ + s->command_arg = value; + break; + case REG_SD_RESP0: /* Response Zero */ + s->response[0] = value; + break; + case REG_SD_RESP1: /* Response One */ + s->response[1] = value; + break; + case REG_SD_RESP2: /* Response Two */ + s->response[2] = value; + break; + case REG_SD_RESP3: /* Response Three */ + s->response[3] = value; + break; + case REG_SD_IMKR: /* Interrupt Mask */ + s->irq_mask = value; + allwinner_sdhost_update_irq(s); + break; + case REG_SD_MISR: /* Masked Interrupt Status */ + case REG_SD_RISR: /* Raw Interrupt Status */ + s->irq_status &= ~value; + allwinner_sdhost_update_irq(s); + break; + case REG_SD_STAR: /* Status */ + s->status &= ~value; + allwinner_sdhost_update_irq(s); + break; + case REG_SD_FWLR: /* FIFO Water Level */ + s->fifo_wlevel = value; + break; + case REG_SD_FUNS: /* FIFO Function Select */ + s->fifo_func_sel = value; + break; + case REG_SD_DBGC: /* Debug Enable */ + s->debug_enable = value; + break; + case REG_SD_A12A: /* Auto command 12 argument */ + s->auto12_arg = value; + break; + case REG_SD_NTSR: /* SD NewTiming Set */ + s->newtiming_set = value; + break; + case REG_SD_SDBG: /* SD newTiming Set Debug */ + s->newtiming_debug = value; + break; + case REG_SD_HWRST: /* Hardware Reset Register */ + s->hardware_rst = value; + break; + case REG_SD_DMAC: /* Internal DMA Controller Control */ + s->dmac = value; + allwinner_sdhost_update_irq(s); + break; + case REG_SD_DLBA: /* Descriptor List Base Address */ + s->desc_base = value; + break; + case REG_SD_IDST: /* Internal DMA Controller Status */ + s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); + allwinner_sdhost_update_irq(s); + break; + case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ + s->dmac_irq = value; + allwinner_sdhost_update_irq(s); + break; + case REG_SD_THLDC: /* Card Threshold Control */ + s->card_threshold = value; + break; + case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ + s->startbit_detect = value; + break; + case REG_SD_FIFO: /* Read/Write FIFO */ + sdbus_write_data(&s->sdbus, value & 0xff); + sdbus_write_data(&s->sdbus, (value >> 8) & 0xff); + sdbus_write_data(&s->sdbus, (value >> 16) & 0xff); + sdbus_write_data(&s->sdbus, (value >> 24) & 0xff); + allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + allwinner_sdhost_auto_stop(s); + allwinner_sdhost_update_irq(s); + break; + case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ + case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ + case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ + case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ + case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ + case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ + case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ + case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ + case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ + case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" + HWADDR_PRIx"\n", __func__, offset); + break; + } +} + +static const MemoryRegionOps allwinner_sdhost_ops = { + .read = allwinner_sdhost_read, + .write = allwinner_sdhost_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static const VMStateDescription vmstate_allwinner_sdhost = { + .name = "allwinner-sdhost", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(global_ctl, AwSdHostState), + VMSTATE_UINT32(clock_ctl, AwSdHostState), + VMSTATE_UINT32(timeout, AwSdHostState), + VMSTATE_UINT32(bus_width, AwSdHostState), + VMSTATE_UINT32(block_size, AwSdHostState), + VMSTATE_UINT32(byte_count, AwSdHostState), + VMSTATE_UINT32(transfer_cnt, AwSdHostState), + VMSTATE_UINT32(command, AwSdHostState), + VMSTATE_UINT32(command_arg, AwSdHostState), + VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4), + VMSTATE_UINT32(irq_mask, AwSdHostState), + VMSTATE_UINT32(irq_status, AwSdHostState), + VMSTATE_UINT32(status, AwSdHostState), + VMSTATE_UINT32(fifo_wlevel, AwSdHostState), + VMSTATE_UINT32(fifo_func_sel, AwSdHostState), + VMSTATE_UINT32(debug_enable, AwSdHostState), + VMSTATE_UINT32(auto12_arg, AwSdHostState), + VMSTATE_UINT32(newtiming_set, AwSdHostState), + VMSTATE_UINT32(newtiming_debug, AwSdHostState), + VMSTATE_UINT32(hardware_rst, AwSdHostState), + VMSTATE_UINT32(dmac, AwSdHostState), + VMSTATE_UINT32(desc_base, AwSdHostState), + VMSTATE_UINT32(dmac_status, AwSdHostState), + VMSTATE_UINT32(dmac_irq, AwSdHostState), + VMSTATE_UINT32(card_threshold, AwSdHostState), + VMSTATE_UINT32(startbit_detect, AwSdHostState), + VMSTATE_UINT32(response_crc, AwSdHostState), + VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8), + VMSTATE_UINT32(status_crc, AwSdHostState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_sdhost_init(Object *obj) +{ + AwSdHostState *s = AW_SDHOST(obj); + + qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), + TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); + + memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s, + TYPE_AW_SDHOST, 4 * KiB); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); +} + +static void allwinner_sdhost_reset(DeviceState *dev) +{ + AwSdHostState *s = AW_SDHOST(dev); + + s->global_ctl = REG_SD_GCTL_RST; + s->clock_ctl = REG_SD_CKCR_RST; + s->timeout = REG_SD_TMOR_RST; + s->bus_width = REG_SD_BWDR_RST; + s->block_size = REG_SD_BKSR_RST; + s->byte_count = REG_SD_BYCR_RST; + s->transfer_cnt = 0; + + s->command = REG_SD_CMDR_RST; + s->command_arg = REG_SD_CAGR_RST; + + for (int i = 0; i < ARRAY_SIZE(s->response); i++) { + s->response[i] = REG_SD_RESP_RST; + } + + s->irq_mask = REG_SD_IMKR_RST; + s->irq_status = REG_SD_RISR_RST; + s->status = REG_SD_STAR_RST; + + s->fifo_wlevel = REG_SD_FWLR_RST; + s->fifo_func_sel = REG_SD_FUNS_RST; + s->debug_enable = REG_SD_DBGC_RST; + s->auto12_arg = REG_SD_A12A_RST; + s->newtiming_set = REG_SD_NTSR_RST; + s->newtiming_debug = REG_SD_SDBG_RST; + s->hardware_rst = REG_SD_HWRST_RST; + s->dmac = REG_SD_DMAC_RST; + s->desc_base = REG_SD_DLBA_RST; + s->dmac_status = REG_SD_IDST_RST; + s->dmac_irq = REG_SD_IDIE_RST; + s->card_threshold = REG_SD_THLDC_RST; + s->startbit_detect = REG_SD_DSBD_RST; + s->response_crc = REG_SD_RES_CRC_RST; + + for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) { + s->data_crc[i] = REG_SD_DATA_CRC_RST; + } + + s->status_crc = REG_SD_CRC_STA_RST; +} + +static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data) +{ + SDBusClass *sbc = SD_BUS_CLASS(klass); + + sbc->set_inserted = allwinner_sdhost_set_inserted; +} + +static void allwinner_sdhost_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_sdhost_reset; + dc->vmsd = &vmstate_allwinner_sdhost; +} + +static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data) +{ + AwSdHostClass *sc = AW_SDHOST_CLASS(klass); + sc->max_desc_size = 8 * KiB; +} + +static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) +{ + AwSdHostClass *sc = AW_SDHOST_CLASS(klass); + sc->max_desc_size = 64 * KiB; +} + +static TypeInfo allwinner_sdhost_info = { + .name = TYPE_AW_SDHOST, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_sdhost_init, + .instance_size = sizeof(AwSdHostState), + .class_init = allwinner_sdhost_class_init, + .class_size = sizeof(AwSdHostClass), + .abstract = true, +}; + +static const TypeInfo allwinner_sdhost_sun4i_info = { + .name = TYPE_AW_SDHOST_SUN4I, + .parent = TYPE_AW_SDHOST, + .class_init = allwinner_sdhost_sun4i_class_init, +}; + +static const TypeInfo allwinner_sdhost_sun5i_info = { + .name = TYPE_AW_SDHOST_SUN5I, + .parent = TYPE_AW_SDHOST, + .class_init = allwinner_sdhost_sun5i_class_init, +}; + +static const TypeInfo allwinner_sdhost_bus_info = { + .name = TYPE_AW_SDHOST_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + .class_init = allwinner_sdhost_bus_class_init, +}; + +static void allwinner_sdhost_register_types(void) +{ + type_register_static(&allwinner_sdhost_info); + type_register_static(&allwinner_sdhost_sun4i_info); + type_register_static(&allwinner_sdhost_sun5i_info); + type_register_static(&allwinner_sdhost_bus_info); +} + +type_init(allwinner_sdhost_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3 select UNIMP select USB_OHCI select USB_EHCI_SYSBUS + select SD config RASPI bool diff --git a/hw/sd/trace-events b/hw/sd/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -XXX,XX +XXX,XX @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-sdhost.c +allwinner_sdhost_set_inserted(bool inserted) "inserted %u" +allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32 " is_write %u max_bytes %" PRIu32 +allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32 + # bcm2835_sdhost.c bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC) which provides 10M/100M/1000M Ethernet connectivity. This commit adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc), including emulation for the following functionality: * DMA transfers * MII interface * Transmit CRC calculation Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/net/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 3 + include/hw/net/allwinner-sun8i-emac.h | 99 +++ hw/arm/allwinner-h3.c | 16 +- hw/arm/orangepi.c | 3 + hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/net/Kconfig | 3 + hw/net/trace-events | 10 + 9 files changed, 1006 insertions(+), 1 deletion(-) create mode 100644 include/hw/net/allwinner-sun8i-emac.h create mode 100644 hw/net/allwinner-sun8i-emac.c diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XGMAC) += xgmac.o common-obj-$(CONFIG_MIPSNET) += mipsnet.o common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o +common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o common-obj-$(CONFIG_IMX_FEC) += imx_fec.o common-obj-$(CONFIG_CADENCE) += cadence_gem.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/allwinner-h3-sysctrl.h" #include "hw/misc/allwinner-sid.h" #include "hw/sd/allwinner-sdhost.h" +#include "hw/net/allwinner-sun8i-emac.h" #include "target/arm/cpu.h" /** @@ -XXX,XX +XXX,XX @@ enum { AW_H3_UART1, AW_H3_UART2, AW_H3_UART3, + AW_H3_EMAC, AW_H3_GIC_DIST, AW_H3_GIC_CPU, AW_H3_GIC_HYP, @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { AwH3SysCtrlState sysctrl; AwSidState sid; AwSdHostState mmc0; + AwSun8iEmacState emac; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/net/allwinner-sun8i-emac.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner Sun8i Ethernet MAC emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H +#define HW_NET_ALLWINNER_SUN8I_EMAC_H + +#include "qom/object.h" +#include "net/net.h" +#include "hw/sysbus.h" + +/** + * Object model + * @{ + */ + +#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac" +#define AW_SUN8I_EMAC(obj) \ + OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC) + +/** @} */ + +/** + * Allwinner Sun8i EMAC object instance state + */ +typedef struct AwSun8iEmacState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Interrupt output signal to notify CPU */ + qemu_irq irq; + + /** Generic Network Interface Controller (NIC) for networking API */ + NICState *nic; + + /** Generic Network Interface Controller (NIC) configuration */ + NICConf conf; + + /** + * @name Media Independent Interface (MII) + * @{ + */ + + uint8_t mii_phy_addr; /**< PHY address */ + uint32_t mii_cr; /**< Control */ + uint32_t mii_st; /**< Status */ + uint32_t mii_adv; /**< Advertised Abilities */ + + /** @} */ + + /** + * @name Hardware Registers + * @{ + */ + + uint32_t basic_ctl0; /**< Basic Control 0 */ + uint32_t basic_ctl1; /**< Basic Control 1 */ + uint32_t int_en; /**< Interrupt Enable */ + uint32_t int_sta; /**< Interrupt Status */ + uint32_t frm_flt; /**< Receive Frame Filter */ + + uint32_t rx_ctl0; /**< Receive Control 0 */ + uint32_t rx_ctl1; /**< Receive Control 1 */ + uint32_t rx_desc_head; /**< Receive Descriptor List Address */ + uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */ + + uint32_t tx_ctl0; /**< Transmit Control 0 */ + uint32_t tx_ctl1; /**< Transmit Control 1 */ + uint32_t tx_desc_head; /**< Transmit Descriptor List Address */ + uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */ + uint32_t tx_flowctl; /**< Transmit Flow Control */ + + uint32_t mii_cmd; /**< Management Interface Command */ + uint32_t mii_data; /**< Management Interface Data */ + + /** @} */ + +} AwSun8iEmacState; + +#endif /* HW_NET_ALLWINNER_SUN8I_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_UART1] = 0x01c28400, [AW_H3_UART2] = 0x01c28800, [AW_H3_UART3] = 0x01c28c00, + [AW_H3_EMAC] = 0x01c30000, [AW_H3_GIC_DIST] = 0x01c81000, [AW_H3_GIC_CPU] = 0x01c82000, [AW_H3_GIC_HYP] = 0x01c84000, @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "twi1", 0x01c2b000, 1 * KiB }, { "twi2", 0x01c2b400, 1 * KiB }, { "scr", 0x01c2c400, 1 * KiB }, - { "emac", 0x01c30000, 64 * KiB }, { "gpu", 0x01c40000, 64 * KiB }, { "hstmr", 0x01c60000, 4 * KiB }, { "dramcom", 0x01c62000, 4 * KiB }, @@ -XXX,XX +XXX,XX @@ enum { AW_H3_GIC_SPI_OHCI2 = 77, AW_H3_GIC_SPI_EHCI3 = 78, AW_H3_GIC_SPI_OHCI3 = 79, + AW_H3_GIC_SPI_EMAC = 82 }; /* Allwinner H3 general constants */ @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), TYPE_AW_SDHOST_SUN5I); + + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), + TYPE_AW_SUN8I_EMAC); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), "sd-bus", &error_abort); + /* EMAC */ + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } + qdev_init_nofail(DEVICE(&s->emac)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC)); + /* Universal Serial Bus */ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) warn_report("Security Identifier value does not include H3 prefix"); } + /* Setup EMAC properties */ + object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort); + /* Mark H3 object realized */ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/net/allwinner-sun8i-emac.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner Sun8i Ethernet MAC emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "net/net.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qemu/log.h" +#include "trace.h" +#include "net/checksum.h" +#include "qemu/module.h" +#include "exec/cpu-common.h" +#include "hw/net/allwinner-sun8i-emac.h" + +/* EMAC register offsets */ +enum { + REG_BASIC_CTL_0 = 0x0000, /* Basic Control 0 */ + REG_BASIC_CTL_1 = 0x0004, /* Basic Control 1 */ + REG_INT_STA = 0x0008, /* Interrupt Status */ + REG_INT_EN = 0x000C, /* Interrupt Enable */ + REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */ + REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */ + REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */ + REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */ + REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */ + REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */ + REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */ + REG_FRM_FLT = 0x0038, /* Receive Frame Filter */ + REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */ + REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */ + REG_MII_CMD = 0x0048, /* Management Interface Command */ + REG_MII_DATA = 0x004C, /* Management Interface Data */ + REG_ADDR_HIGH = 0x0050, /* MAC Address High */ + REG_ADDR_LOW = 0x0054, /* MAC Address Low */ + REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */ + REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */ + REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */ + REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */ + REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */ + REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */ + REG_RGMII_STA = 0x00D0, /* RGMII Status */ +}; + +/* EMAC register flags */ +enum { + BASIC_CTL0_100Mbps = (0b11 << 2), + BASIC_CTL0_FD = (1 << 0), + BASIC_CTL1_SOFTRST = (1 << 0), +}; + +enum { + INT_STA_RGMII_LINK = (1 << 16), + INT_STA_RX_EARLY = (1 << 13), + INT_STA_RX_OVERFLOW = (1 << 12), + INT_STA_RX_TIMEOUT = (1 << 11), + INT_STA_RX_DMA_STOP = (1 << 10), + INT_STA_RX_BUF_UA = (1 << 9), + INT_STA_RX = (1 << 8), + INT_STA_TX_EARLY = (1 << 5), + INT_STA_TX_UNDERFLOW = (1 << 4), + INT_STA_TX_TIMEOUT = (1 << 3), + INT_STA_TX_BUF_UA = (1 << 2), + INT_STA_TX_DMA_STOP = (1 << 1), + INT_STA_TX = (1 << 0), +}; + +enum { + INT_EN_RX_EARLY = (1 << 13), + INT_EN_RX_OVERFLOW = (1 << 12), + INT_EN_RX_TIMEOUT = (1 << 11), + INT_EN_RX_DMA_STOP = (1 << 10), + INT_EN_RX_BUF_UA = (1 << 9), + INT_EN_RX = (1 << 8), + INT_EN_TX_EARLY = (1 << 5), + INT_EN_TX_UNDERFLOW = (1 << 4), + INT_EN_TX_TIMEOUT = (1 << 3), + INT_EN_TX_BUF_UA = (1 << 2), + INT_EN_TX_DMA_STOP = (1 << 1), + INT_EN_TX = (1 << 0), +}; + +enum { + TX_CTL0_TX_EN = (1 << 31), + TX_CTL1_TX_DMA_START = (1 << 31), + TX_CTL1_TX_DMA_EN = (1 << 30), + TX_CTL1_TX_FLUSH = (1 << 0), +}; + +enum { + RX_CTL0_RX_EN = (1 << 31), + RX_CTL0_STRIP_FCS = (1 << 28), + RX_CTL0_CRC_IPV4 = (1 << 27), +}; + +enum { + RX_CTL1_RX_DMA_START = (1 << 31), + RX_CTL1_RX_DMA_EN = (1 << 30), + RX_CTL1_RX_MD = (1 << 1), +}; + +enum { + RX_FRM_FLT_DIS_ADDR = (1 << 31), +}; + +enum { + MII_CMD_PHY_ADDR_SHIFT = (12), + MII_CMD_PHY_ADDR_MASK = (0xf000), + MII_CMD_PHY_REG_SHIFT = (4), + MII_CMD_PHY_REG_MASK = (0xf0), + MII_CMD_PHY_RW = (1 << 1), + MII_CMD_PHY_BUSY = (1 << 0), +}; + +enum { + TX_DMA_STA_STOP = (0b000), + TX_DMA_STA_RUN_FETCH = (0b001), + TX_DMA_STA_WAIT_STA = (0b010), +}; + +enum { + RX_DMA_STA_STOP = (0b000), + RX_DMA_STA_RUN_FETCH = (0b001), + RX_DMA_STA_WAIT_FRM = (0b011), +}; + +/* EMAC register reset values */ +enum { + REG_BASIC_CTL_1_RST = 0x08000000, +}; + +/* EMAC constants */ +enum { + AW_SUN8I_EMAC_MIN_PKT_SZ = 64 +}; + +/* Transmit/receive frame descriptor */ +typedef struct FrameDescriptor { + uint32_t status; + uint32_t status2; + uint32_t addr; + uint32_t next; +} FrameDescriptor; + +/* Frame descriptor flags */ +enum { + DESC_STATUS_CTL = (1 << 31), + DESC_STATUS2_BUF_SIZE_MASK = (0x7ff), +}; + +/* Transmit frame descriptor flags */ +enum { + TX_DESC_STATUS_LENGTH_ERR = (1 << 14), + TX_DESC_STATUS2_FIRST_DESC = (1 << 29), + TX_DESC_STATUS2_LAST_DESC = (1 << 30), + TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27), +}; + +/* Receive frame descriptor flags */ +enum { + RX_DESC_STATUS_FIRST_DESC = (1 << 9), + RX_DESC_STATUS_LAST_DESC = (1 << 8), + RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000), + RX_DESC_STATUS_FRM_LEN_SHIFT = (16), + RX_DESC_STATUS_NO_BUF = (1 << 14), + RX_DESC_STATUS_HEADER_ERR = (1 << 7), + RX_DESC_STATUS_LENGTH_ERR = (1 << 4), + RX_DESC_STATUS_CRC_ERR = (1 << 1), + RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0), + RX_DESC_STATUS2_RX_INT_CTL = (1 << 31), +}; + +/* MII register offsets */ +enum { + MII_REG_CR = (0x0), /* Control */ + MII_REG_ST = (0x1), /* Status */ + MII_REG_ID_HIGH = (0x2), /* Identifier High */ + MII_REG_ID_LOW = (0x3), /* Identifier Low */ + MII_REG_ADV = (0x4), /* Advertised abilities */ + MII_REG_LPA = (0x5), /* Link partner abilities */ +}; + +/* MII register flags */ +enum { + MII_REG_CR_RESET = (1 << 15), + MII_REG_CR_POWERDOWN = (1 << 11), + MII_REG_CR_10Mbit = (0), + MII_REG_CR_100Mbit = (1 << 13), + MII_REG_CR_1000Mbit = (1 << 6), + MII_REG_CR_AUTO_NEG = (1 << 12), + MII_REG_CR_AUTO_NEG_RESTART = (1 << 9), + MII_REG_CR_FULLDUPLEX = (1 << 8), +}; + +enum { + MII_REG_ST_100BASE_T4 = (1 << 15), + MII_REG_ST_100BASE_X_FD = (1 << 14), + MII_REG_ST_100BASE_X_HD = (1 << 13), + MII_REG_ST_10_FD = (1 << 12), + MII_REG_ST_10_HD = (1 << 11), + MII_REG_ST_100BASE_T2_FD = (1 << 10), + MII_REG_ST_100BASE_T2_HD = (1 << 9), + MII_REG_ST_AUTONEG_COMPLETE = (1 << 5), + MII_REG_ST_AUTONEG_AVAIL = (1 << 3), + MII_REG_ST_LINK_UP = (1 << 2), +}; + +enum { + MII_REG_LPA_10_HD = (1 << 5), + MII_REG_LPA_10_FD = (1 << 6), + MII_REG_LPA_100_HD = (1 << 7), + MII_REG_LPA_100_FD = (1 << 8), + MII_REG_LPA_PAUSE = (1 << 10), + MII_REG_LPA_ASYMPAUSE = (1 << 11), +}; + +/* MII constants */ +enum { + MII_PHY_ID_HIGH = 0x0044, + MII_PHY_ID_LOW = 0x1400, +}; + +static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s, + bool link_active) +{ + if (link_active) { + s->mii_st |= MII_REG_ST_LINK_UP; + } else { + s->mii_st &= ~MII_REG_ST_LINK_UP; + } +} + +static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s, + bool link_active) +{ + s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG | + MII_REG_CR_FULLDUPLEX; + s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD | + MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD | + MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD | + MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL; + s->mii_adv = 0; + + allwinner_sun8i_emac_mii_set_link(s, link_active); +} + +static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s) +{ + uint8_t addr, reg; + + addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT; + reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT; + + if (addr != s->mii_phy_addr) { + return; + } + + /* Read or write a PHY register? */ + if (s->mii_cmd & MII_CMD_PHY_RW) { + trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data); + + switch (reg) { + case MII_REG_CR: + if (s->mii_data & MII_REG_CR_RESET) { + allwinner_sun8i_emac_mii_reset(s, s->mii_st & + MII_REG_ST_LINK_UP); + } else { + s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET | + MII_REG_CR_AUTO_NEG_RESTART); + } + break; + case MII_REG_ADV: + s->mii_adv = s->mii_data; + break; + case MII_REG_ID_HIGH: + case MII_REG_ID_LOW: + case MII_REG_LPA: + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to " + "unknown MII register 0x%x\n", reg); + break; + } + } else { + switch (reg) { + case MII_REG_CR: + s->mii_data = s->mii_cr; + break; + case MII_REG_ST: + s->mii_data = s->mii_st; + break; + case MII_REG_ID_HIGH: + s->mii_data = MII_PHY_ID_HIGH; + break; + case MII_REG_ID_LOW: + s->mii_data = MII_PHY_ID_LOW; + break; + case MII_REG_ADV: + s->mii_data = s->mii_adv; + break; + case MII_REG_LPA: + s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD | + MII_REG_LPA_100_HD | MII_REG_LPA_100_FD | + MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE; + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to " + "unknown MII register 0x%x\n", reg); + s->mii_data = 0; + break; + } + + trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data); + } +} + +static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s) +{ + qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0); +} + +static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc, + size_t min_size) +{ + uint32_t paddr = desc->next; + + cpu_physical_memory_read(paddr, desc, sizeof(*desc)); + + if ((desc->status & DESC_STATUS_CTL) && + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { + return paddr; + } else { + return 0; + } +} + +static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc, + uint32_t start_addr, + size_t min_size) +{ + uint32_t desc_addr = start_addr; + + /* Note that the list is a cycle. Last entry points back to the head. */ + while (desc_addr != 0) { + cpu_physical_memory_read(desc_addr, desc, sizeof(*desc)); + + if ((desc->status & DESC_STATUS_CTL) && + (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) { + return desc_addr; + } else if (desc->next == start_addr) { + break; + } else { + desc_addr = desc->next; + } + } + + return 0; +} + +static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s, + FrameDescriptor *desc, + size_t min_size) +{ + return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size); +} + +static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s, + FrameDescriptor *desc, + size_t min_size) +{ + return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size); +} + +static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc, + uint32_t phys_addr) +{ + cpu_physical_memory_write(phys_addr, desc, sizeof(*desc)); +} + +static int allwinner_sun8i_emac_can_receive(NetClientState *nc) +{ + AwSun8iEmacState *s = qemu_get_nic_opaque(nc); + FrameDescriptor desc; + + return (s->rx_ctl0 & RX_CTL0_RX_EN) && + (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0); +} + +static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc, + const uint8_t *buf, + size_t size) +{ + AwSun8iEmacState *s = qemu_get_nic_opaque(nc); + FrameDescriptor desc; + size_t bytes_left = size; + size_t desc_bytes = 0; + size_t pad_fcs_size = 4; + size_t padding = 0; + + if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) { + return -1; + } + + s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc, + AW_SUN8I_EMAC_MIN_PKT_SZ); + if (!s->rx_desc_curr) { + s->int_sta |= INT_STA_RX_BUF_UA; + } + + /* Keep filling RX descriptors until the whole frame is written */ + while (s->rx_desc_curr && bytes_left > 0) { + desc.status &= ~DESC_STATUS_CTL; + desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK; + + if (bytes_left == size) { + desc.status |= RX_DESC_STATUS_FIRST_DESC; + } + + if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) < + (bytes_left + pad_fcs_size)) { + desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; + desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT; + } else { + padding = pad_fcs_size; + if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) { + padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left); + } + + desc_bytes = (bytes_left); + desc.status |= RX_DESC_STATUS_LAST_DESC; + desc.status |= (bytes_left + padding) + << RX_DESC_STATUS_FRM_LEN_SHIFT; + } + + cpu_physical_memory_write(desc.addr, buf, desc_bytes); + allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr); + trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr, + desc_bytes); + + /* Check if frame needs to raise the receive interrupt */ + if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) { + s->int_sta |= INT_STA_RX; + } + + /* Increment variables */ + buf += desc_bytes; + bytes_left -= desc_bytes; + + /* Move to the next descriptor */ + s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64); + if (!s->rx_desc_curr) { + /* Not enough buffer space available */ + s->int_sta |= INT_STA_RX_BUF_UA; + s->rx_desc_curr = s->rx_desc_head; + break; + } + } + + /* Report receive DMA is finished */ + s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START; + allwinner_sun8i_emac_update_irq(s); + + return size; +} + +static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s) +{ + NetClientState *nc = qemu_get_queue(s->nic); + FrameDescriptor desc; + size_t bytes = 0; + size_t packet_bytes = 0; + size_t transmitted = 0; + static uint8_t packet_buf[2048]; + + s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0); + + /* Read all transmit descriptors */ + while (s->tx_desc_curr != 0) { + + /* Read from physical memory into packet buffer */ + bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK; + if (bytes + packet_bytes > sizeof(packet_buf)) { + desc.status |= TX_DESC_STATUS_LENGTH_ERR; + break; + } + cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes); + packet_bytes += bytes; + desc.status &= ~DESC_STATUS_CTL; + allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr); + + /* After the last descriptor, send the packet */ + if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) { + if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) { + net_checksum_calculate(packet_buf, packet_bytes); + } + + qemu_send_packet(nc, packet_buf, packet_bytes); + trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr, + bytes); + + packet_bytes = 0; + transmitted++; + } + s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0); + } + + /* Raise transmit completed interrupt */ + if (transmitted > 0) { + s->int_sta |= INT_STA_TX; + s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START; + allwinner_sun8i_emac_update_irq(s); + } +} + +static void allwinner_sun8i_emac_reset(DeviceState *dev) +{ + AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); + NetClientState *nc = qemu_get_queue(s->nic); + + trace_allwinner_sun8i_emac_reset(); + + s->mii_cmd = 0; + s->mii_data = 0; + s->basic_ctl0 = 0; + s->basic_ctl1 = REG_BASIC_CTL_1_RST; + s->int_en = 0; + s->int_sta = 0; + s->frm_flt = 0; + s->rx_ctl0 = 0; + s->rx_ctl1 = RX_CTL1_RX_MD; + s->rx_desc_head = 0; + s->rx_desc_curr = 0; + s->tx_ctl0 = 0; + s->tx_ctl1 = 0; + s->tx_desc_head = 0; + s->tx_desc_curr = 0; + s->tx_flowctl = 0; + + allwinner_sun8i_emac_mii_reset(s, !nc->link_down); +} + +static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); + uint64_t value = 0; + FrameDescriptor desc; + + switch (offset) { + case REG_BASIC_CTL_0: /* Basic Control 0 */ + value = s->basic_ctl0; + break; + case REG_BASIC_CTL_1: /* Basic Control 1 */ + value = s->basic_ctl1; + break; + case REG_INT_STA: /* Interrupt Status */ + value = s->int_sta; + break; + case REG_INT_EN: /* Interupt Enable */ + value = s->int_en; + break; + case REG_TX_CTL_0: /* Transmit Control 0 */ + value = s->tx_ctl0; + break; + case REG_TX_CTL_1: /* Transmit Control 1 */ + value = s->tx_ctl1; + break; + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ + value = s->tx_flowctl; + break; + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ + value = s->tx_desc_head; + break; + case REG_RX_CTL_0: /* Receive Control 0 */ + value = s->rx_ctl0; + break; + case REG_RX_CTL_1: /* Receive Control 1 */ + value = s->rx_ctl1; + break; + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ + value = s->rx_desc_head; + break; + case REG_FRM_FLT: /* Receive Frame Filter */ + value = s->frm_flt; + break; + case REG_RX_HASH_0: /* Receive Hash Table 0 */ + case REG_RX_HASH_1: /* Receive Hash Table 1 */ + break; + case REG_MII_CMD: /* Management Interface Command */ + value = s->mii_cmd; + break; + case REG_MII_DATA: /* Management Interface Data */ + value = s->mii_data; + break; + case REG_ADDR_HIGH: /* MAC Address High */ + value = *(((uint32_t *) (s->conf.macaddr.a)) + 1); + break; + case REG_ADDR_LOW: /* MAC Address Low */ + value = *(uint32_t *) (s->conf.macaddr.a); + break; + case REG_TX_DMA_STA: /* Transmit DMA Status */ + break; + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ + value = s->tx_desc_curr; + break; + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ + if (s->tx_desc_curr != 0) { + cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc)); + value = desc.addr; + } else { + value = 0; + } + break; + case REG_RX_DMA_STA: /* Receive DMA Status */ + break; + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ + value = s->rx_desc_curr; + break; + case REG_RX_CUR_BUF: /* Receive Current Buffer */ + if (s->rx_desc_curr != 0) { + cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc)); + value = desc.addr; + } else { + value = 0; + } + break; + case REG_RGMII_STA: /* RGMII Status */ + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " + "EMAC register 0x" TARGET_FMT_plx "\n", + offset); + } + + trace_allwinner_sun8i_emac_read(offset, value); + return value; +} + +static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque); + NetClientState *nc = qemu_get_queue(s->nic); + + trace_allwinner_sun8i_emac_write(offset, value); + + switch (offset) { + case REG_BASIC_CTL_0: /* Basic Control 0 */ + s->basic_ctl0 = value; + break; + case REG_BASIC_CTL_1: /* Basic Control 1 */ + if (value & BASIC_CTL1_SOFTRST) { + allwinner_sun8i_emac_reset(DEVICE(s)); + value &= ~BASIC_CTL1_SOFTRST; + } + s->basic_ctl1 = value; + if (allwinner_sun8i_emac_can_receive(nc)) { + qemu_flush_queued_packets(nc); + } + break; + case REG_INT_STA: /* Interrupt Status */ + s->int_sta &= ~value; + allwinner_sun8i_emac_update_irq(s); + break; + case REG_INT_EN: /* Interrupt Enable */ + s->int_en = value; + allwinner_sun8i_emac_update_irq(s); + break; + case REG_TX_CTL_0: /* Transmit Control 0 */ + s->tx_ctl0 = value; + break; + case REG_TX_CTL_1: /* Transmit Control 1 */ + s->tx_ctl1 = value; + if (value & TX_CTL1_TX_DMA_EN) { + allwinner_sun8i_emac_transmit(s); + } + break; + case REG_TX_FLOW_CTL: /* Transmit Flow Control */ + s->tx_flowctl = value; + break; + case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ + s->tx_desc_head = value; + s->tx_desc_curr = value; + break; + case REG_RX_CTL_0: /* Receive Control 0 */ + s->rx_ctl0 = value; + break; + case REG_RX_CTL_1: /* Receive Control 1 */ + s->rx_ctl1 = value | RX_CTL1_RX_MD; + if ((value & RX_CTL1_RX_DMA_EN) && + allwinner_sun8i_emac_can_receive(nc)) { + qemu_flush_queued_packets(nc); + } + break; + case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */ + s->rx_desc_head = value; + s->rx_desc_curr = value; + break; + case REG_FRM_FLT: /* Receive Frame Filter */ + s->frm_flt = value; + break; + case REG_RX_HASH_0: /* Receive Hash Table 0 */ + case REG_RX_HASH_1: /* Receive Hash Table 1 */ + break; + case REG_MII_CMD: /* Management Interface Command */ + s->mii_cmd = value & ~MII_CMD_PHY_BUSY; + allwinner_sun8i_emac_mii_cmd(s); + break; + case REG_MII_DATA: /* Management Interface Data */ + s->mii_data = value; + break; + case REG_ADDR_HIGH: /* MAC Address High */ + s->conf.macaddr.a[4] = (value & 0xff); + s->conf.macaddr.a[5] = (value & 0xff00) >> 8; + break; + case REG_ADDR_LOW: /* MAC Address Low */ + s->conf.macaddr.a[0] = (value & 0xff); + s->conf.macaddr.a[1] = (value & 0xff00) >> 8; + s->conf.macaddr.a[2] = (value & 0xff0000) >> 16; + s->conf.macaddr.a[3] = (value & 0xff000000) >> 24; + break; + case REG_TX_DMA_STA: /* Transmit DMA Status */ + case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ + case REG_TX_CUR_BUF: /* Transmit Current Buffer */ + case REG_RX_DMA_STA: /* Receive DMA Status */ + case REG_RX_CUR_DESC: /* Receive Current Descriptor */ + case REG_RX_CUR_BUF: /* Receive Current Buffer */ + case REG_RGMII_STA: /* RGMII Status */ + break; + default: + qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " + "EMAC register 0x" TARGET_FMT_plx "\n", + offset); + } +} + +static void allwinner_sun8i_emac_set_link(NetClientState *nc) +{ + AwSun8iEmacState *s = qemu_get_nic_opaque(nc); + + trace_allwinner_sun8i_emac_set_link(!nc->link_down); + allwinner_sun8i_emac_mii_set_link(s, !nc->link_down); +} + +static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = { + .read = allwinner_sun8i_emac_read, + .write = allwinner_sun8i_emac_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static NetClientInfo net_allwinner_sun8i_emac_info = { + .type = NET_CLIENT_DRIVER_NIC, + .size = sizeof(NICState), + .can_receive = allwinner_sun8i_emac_can_receive, + .receive = allwinner_sun8i_emac_receive, + .link_status_changed = allwinner_sun8i_emac_set_link, +}; + +static void allwinner_sun8i_emac_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwSun8iEmacState *s = AW_SUN8I_EMAC(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops, + s, TYPE_AW_SUN8I_EMAC, 64 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp) +{ + AwSun8iEmacState *s = AW_SUN8I_EMAC(dev); + + qemu_macaddr_default_if_unset(&s->conf.macaddr); + s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf, + object_get_typename(OBJECT(dev)), dev->id, s); + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); +} + +static Property allwinner_sun8i_emac_properties[] = { + DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf), + DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static int allwinner_sun8i_emac_post_load(void *opaque, int version_id) +{ + AwSun8iEmacState *s = opaque; + + allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic)); + + return 0; +} + +static const VMStateDescription vmstate_aw_emac = { + .name = "allwinner-sun8i-emac", + .version_id = 1, + .minimum_version_id = 1, + .post_load = allwinner_sun8i_emac_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState), + VMSTATE_UINT32(mii_cmd, AwSun8iEmacState), + VMSTATE_UINT32(mii_data, AwSun8iEmacState), + VMSTATE_UINT32(mii_cr, AwSun8iEmacState), + VMSTATE_UINT32(mii_st, AwSun8iEmacState), + VMSTATE_UINT32(mii_adv, AwSun8iEmacState), + VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState), + VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState), + VMSTATE_UINT32(int_en, AwSun8iEmacState), + VMSTATE_UINT32(int_sta, AwSun8iEmacState), + VMSTATE_UINT32(frm_flt, AwSun8iEmacState), + VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState), + VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState), + VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState), + VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState), + VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState), + VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState), + VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState), + VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState), + VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = allwinner_sun8i_emac_realize; + dc->reset = allwinner_sun8i_emac_reset; + dc->vmsd = &vmstate_aw_emac; + device_class_set_props(dc, allwinner_sun8i_emac_properties); +} + +static const TypeInfo allwinner_sun8i_emac_info = { + .name = TYPE_AW_SUN8I_EMAC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AwSun8iEmacState), + .instance_init = allwinner_sun8i_emac_init, + .class_init = allwinner_sun8i_emac_class_init, +}; + +static void allwinner_sun8i_emac_register_types(void) +{ + type_register_static(&allwinner_sun8i_emac_info); +} + +type_init(allwinner_sun8i_emac_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 config ALLWINNER_H3 bool select ALLWINNER_A10_PIT + select ALLWINNER_SUN8I_EMAC select SERIAL select ARM_TIMER select ARM_GIC diff --git a/hw/net/Kconfig b/hw/net/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -XXX,XX +XXX,XX @@ config MIPSNET config ALLWINNER_EMAC bool +config ALLWINNER_SUN8I_EMAC + bool + config IMX_FEC bool diff --git a/hw/net/trace-events b/hw/net/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -XXX,XX +XXX,XX @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-sun8i-emac.c +allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 +allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 +allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 +allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 +allwinner_sun8i_emac_reset(void) "HW reset" +allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" +allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 +allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 + # etraxfs_eth.c mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x" mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x" -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> A real Allwinner H3 SoC contains a Boot ROM which is the first code that runs right after the SoC is powered on. The Boot ROM is responsible for loading user code (e.g. a bootloader) from any of the supported external devices and writing the downloaded code to internal SRAM. After loading the SoC begins executing the code written to SRAM. This commits adds emulation of the Boot ROM firmware setup functionality by loading user code from SD card in the A1 SRAM. While the A1 SRAM is 64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects sizes larger than 32KiB. For reference, this behaviour is documented by the Linux Sunxi project wiki at: https://linux-sunxi.org/BROM#U-Boot_SPL_limitations Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++ hw/arm/allwinner-h3.c | 17 +++++++++++++++++ hw/arm/orangepi.c | 5 +++++ 3 files changed, 43 insertions(+) diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/sd/allwinner-sdhost.h" #include "hw/net/allwinner-sun8i-emac.h" #include "target/arm/cpu.h" +#include "sysemu/block-backend.h" /** * Allwinner H3 device list @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { MemoryRegion sram_c; } AwH3State; +/** + * Emulate Boot ROM firmware setup functionality. + * + * A real Allwinner H3 SoC contains a Boot ROM + * which is the first code that runs right after + * the SoC is powered on. The Boot ROM is responsible + * for loading user code (e.g. a bootloader) from any + * of the supported external devices and writing the + * downloaded code to internal SRAM. After loading the SoC + * begins executing the code written to SRAM. + * + * This function emulates the Boot ROM by copying 32 KiB + * of data from the given block device and writes it to + * the start of the first internal SRAM memory. + * + * @s: Allwinner H3 state object pointer + * @blk: Block backend device object pointer + */ +void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk); + #endif /* HW_ARM_ALLWINNER_H3_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ #include "hw/char/serial.h" #include "hw/misc/unimp.h" #include "hw/usb/hcd-ehci.h" +#include "hw/loader.h" #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" @@ -XXX,XX +XXX,XX @@ enum { AW_H3_GIC_NUM_SPI = 128 }; +void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk) +{ + const int64_t rom_size = 32 * KiB; + g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size); + + if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) { + error_setg(&error_fatal, "%s: failed to read BlockBackend data", + __func__); + return; + } + + rom_add_blob("allwinner-h3.bootrom", buffer, rom_size, + rom_size, s->memmap[AW_H3_SRAM_A1], + NULL, NULL, NULL, NULL, false); +} + static void allwinner_h3_init(Object *obj) { AwH3State *s = AW_H3(obj); diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM], machine->ram); + /* Load target kernel or start using BootROM */ + if (!machine->kernel_filename && blk_is_available(blk)) { + /* Use Boot ROM to copy data from SD card to SRAM */ + allwinner_h3_bootrom_setup(h3, blk); + } orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM]; orangepi_binfo.ram_size = machine->ram_size; arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/Makefile.objs | 1 + include/hw/arm/allwinner-h3.h | 5 + include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++ hw/arm/allwinner-h3.c | 19 +- hw/arm/orangepi.c | 6 + hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++ hw/misc/trace-events | 10 + 7 files changed, 502 insertions(+), 3 deletions(-) create mode 100644 include/hw/misc/allwinner-h3-dramc.h create mode 100644 hw/misc/allwinner-h3-dramc.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-ccu.h" #include "hw/misc/allwinner-cpucfg.h" +#include "hw/misc/allwinner-h3-dramc.h" #include "hw/misc/allwinner-h3-sysctrl.h" #include "hw/misc/allwinner-sid.h" #include "hw/sd/allwinner-sdhost.h" @@ -XXX,XX +XXX,XX @@ enum { AW_H3_UART2, AW_H3_UART3, AW_H3_EMAC, + AW_H3_DRAMCOM, + AW_H3_DRAMCTL, + AW_H3_DRAMPHY, AW_H3_GIC_DIST, AW_H3_GIC_CPU, AW_H3_GIC_HYP, @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { AwA10PITState timer; AwH3ClockCtlState ccu; AwCpuCfgState cpucfg; + AwH3DramCtlState dramc; AwH3SysCtrlState sysctrl; AwSidState sid; AwSdHostState mmc0; diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinner-h3-dramc.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/misc/allwinner-h3-dramc.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 SDRAM Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H +#define HW_MISC_ALLWINNER_H3_DRAMC_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "exec/hwaddr.h" + +/** + * Constants + * @{ + */ + +/** Highest register address used by DRAMCOM module */ +#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804) + +/** Total number of known DRAMCOM registers */ +#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \ + sizeof(uint32_t)) + +/** Highest register address used by DRAMCTL module */ +#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c) + +/** Total number of known DRAMCTL registers */ +#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \ + sizeof(uint32_t)) + +/** Highest register address used by DRAMPHY module */ +#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4) + +/** Total number of known DRAMPHY registers */ +#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \ + sizeof(uint32_t)) + +/** @} */ + +/** + * Object model + * @{ + */ + +#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc" +#define AW_H3_DRAMC(obj) \ + OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC) + +/** @} */ + +/** + * Allwinner H3 SDRAM Controller object instance state. + */ +typedef struct AwH3DramCtlState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Physical base address for start of RAM */ + hwaddr ram_addr; + + /** Total RAM size in megabytes */ + uint32_t ram_size; + + /** + * @name Memory Regions + * @{ + */ + + MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */ + MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */ + MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */ + MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */ + MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */ + + /** @} */ + + /** + * @name Hardware Registers + * @{ + */ + + uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */ + uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */ + uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */ + + /** @} */ + +} AwH3DramCtlState; + +#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */ diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_UART2] = 0x01c28800, [AW_H3_UART3] = 0x01c28c00, [AW_H3_EMAC] = 0x01c30000, + [AW_H3_DRAMCOM] = 0x01c62000, + [AW_H3_DRAMCTL] = 0x01c63000, + [AW_H3_DRAMPHY] = 0x01c65000, [AW_H3_GIC_DIST] = 0x01c81000, [AW_H3_GIC_CPU] = 0x01c82000, [AW_H3_GIC_HYP] = 0x01c84000, @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "scr", 0x01c2c400, 1 * KiB }, { "gpu", 0x01c40000, 64 * KiB }, { "hstmr", 0x01c60000, 4 * KiB }, - { "dramcom", 0x01c62000, 4 * KiB }, - { "dramctl0", 0x01c63000, 4 * KiB }, - { "dramphy0", 0x01c65000, 4 * KiB }, { "spi0", 0x01c68000, 4 * KiB }, { "spi1", 0x01c69000, 4 * KiB }, { "csi", 0x01cb0000, 320 * KiB }, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_SUN8I_EMAC); + + sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc), + TYPE_AW_H3_DRAMC); + object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc), + "ram-addr", &error_abort); + object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc), + "ram-size", &error_abort); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3), 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); + /* DRAMC */ + qdev_init_nofail(DEVICE(&s->dramc)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]); + /* Unimplemented devices */ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { create_unimplemented_device(unimplemented[i].device_name, diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine) /* Setup EMAC properties */ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort); + /* DRAMC */ + object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM], + "ram-addr", &error_abort); + object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size", + &error_abort); + /* Mark H3 object realized */ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort); diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/misc/allwinner-h3-dramc.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner H3 SDRAM Controller emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "exec/address-spaces.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "hw/misc/allwinner-h3-dramc.h" +#include "trace.h" + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* DRAMCOM register offsets */ +enum { + REG_DRAMCOM_CR = 0x0000, /* Control Register */ +}; + +/* DRAMCTL register offsets */ +enum { + REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */ + REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */ + REG_DRAMCTL_STATR = 0x0018, /* Status Register */ +}; + +/* DRAMCTL register flags */ +enum { + REG_DRAMCTL_PGSR_INITDONE = (1 << 0), +}; + +enum { + REG_DRAMCTL_STATR_ACTIVE = (1 << 0), +}; + +static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits, + uint8_t bank_bits, uint16_t page_size) +{ + /* + * This function simulates row addressing behavior when bootloader + * software attempts to detect the amount of available SDRAM. In U-Boot + * the controller is configured with the widest row addressing available. + * Then a pattern is written to RAM at an offset on the row boundary size. + * If the value read back equals the value read back from the + * start of RAM, the bootloader knows the amount of row bits. + * + * This function inserts a mirrored memory region when the configured row + * bits are not matching the actual emulated memory, to simulate the + * same behavior on hardware as expected by the bootloader. + */ + uint8_t row_bits_actual = 0; + + /* Calculate the actual row bits using the ram_size property */ + for (uint8_t i = 8; i < 12; i++) { + if (1 << i == s->ram_size) { + row_bits_actual = i + 3; + break; + } + } + + if (s->ram_size == (1 << (row_bits - 3))) { + /* When row bits is the expected value, remove the mirror */ + memory_region_set_enabled(&s->row_mirror_alias, false); + trace_allwinner_h3_dramc_rowmirror_disable(); + + } else if (row_bits_actual) { + /* Row bits not matching ram_size, install the rows mirror */ + hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual + + bank_bits)) * page_size); + + memory_region_set_enabled(&s->row_mirror_alias, true); + memory_region_set_address(&s->row_mirror_alias, row_mirror); + + trace_allwinner_h3_dramc_rowmirror_enable(row_mirror); + } +} + +static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3DramCtlState *s = AW_H3_DRAMC(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_DRAMCOM_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size); + + return s->dramcom[idx]; +} + +static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3DramCtlState *s = AW_H3_DRAMC(opaque); + const uint32_t idx = REG_INDEX(offset); + + trace_allwinner_h3_dramcom_write(offset, val, size); + + if (idx >= AW_H3_DRAMCOM_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_DRAMCOM_CR: /* Control Register */ + allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1, + ((val >> 2) & 0x1) + 2, + 1 << (((val >> 8) & 0xf) + 3)); + break; + default: + break; + }; + + s->dramcom[idx] = (uint32_t) val; +} + +static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3DramCtlState *s = AW_H3_DRAMC(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_DRAMCTL_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size); + + return s->dramctl[idx]; +} + +static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3DramCtlState *s = AW_H3_DRAMC(opaque); + const uint32_t idx = REG_INDEX(offset); + + trace_allwinner_h3_dramctl_write(offset, val, size); + + if (idx >= AW_H3_DRAMCTL_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + switch (offset) { + case REG_DRAMCTL_PIR: /* PHY Initialization Register */ + s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE; + s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE; + break; + default: + break; + } + + s->dramctl[idx] = (uint32_t) val; +} + +static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwH3DramCtlState *s = AW_H3_DRAMC(opaque); + const uint32_t idx = REG_INDEX(offset); + + if (idx >= AW_H3_DRAMPHY_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size); + + return s->dramphy[idx]; +} + +static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwH3DramCtlState *s = AW_H3_DRAMC(opaque); + const uint32_t idx = REG_INDEX(offset); + + trace_allwinner_h3_dramphy_write(offset, val, size); + + if (idx >= AW_H3_DRAMPHY_REGS_NUM) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + s->dramphy[idx] = (uint32_t) val; +} + +static const MemoryRegionOps allwinner_h3_dramcom_ops = { + .read = allwinner_h3_dramcom_read, + .write = allwinner_h3_dramcom_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static const MemoryRegionOps allwinner_h3_dramctl_ops = { + .read = allwinner_h3_dramctl_read, + .write = allwinner_h3_dramctl_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static const MemoryRegionOps allwinner_h3_dramphy_ops = { + .read = allwinner_h3_dramphy_read, + .write = allwinner_h3_dramphy_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_h3_dramc_reset(DeviceState *dev) +{ + AwH3DramCtlState *s = AW_H3_DRAMC(dev); + + /* Set default values for registers */ + memset(&s->dramcom, 0, sizeof(s->dramcom)); + memset(&s->dramctl, 0, sizeof(s->dramctl)); + memset(&s->dramphy, 0, sizeof(s->dramphy)); +} + +static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp) +{ + AwH3DramCtlState *s = AW_H3_DRAMC(dev); + + /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */ + for (uint8_t i = 8; i < 13; i++) { + if (1 << i == s->ram_size) { + break; + } else if (i == 12) { + error_report("%s: ram-size %u MiB is not supported", + __func__, s->ram_size); + exit(1); + } + } + + /* Setup row mirror mappings */ + memory_region_init_ram(&s->row_mirror, OBJECT(s), + "allwinner-h3-dramc.row-mirror", + 4 * KiB, &error_abort); + memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr, + &s->row_mirror, 10); + + memory_region_init_alias(&s->row_mirror_alias, OBJECT(s), + "allwinner-h3-dramc.row-mirror-alias", + &s->row_mirror, 0, 4 * KiB); + memory_region_add_subregion_overlap(get_system_memory(), + s->ram_addr + 1 * MiB, + &s->row_mirror_alias, 10); + memory_region_set_enabled(&s->row_mirror_alias, false); +} + +static void allwinner_h3_dramc_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwH3DramCtlState *s = AW_H3_DRAMC(obj); + + /* DRAMCOM registers */ + memory_region_init_io(&s->dramcom_iomem, OBJECT(s), + &allwinner_h3_dramcom_ops, s, + TYPE_AW_H3_DRAMC, 4 * KiB); + sysbus_init_mmio(sbd, &s->dramcom_iomem); + + /* DRAMCTL registers */ + memory_region_init_io(&s->dramctl_iomem, OBJECT(s), + &allwinner_h3_dramctl_ops, s, + TYPE_AW_H3_DRAMC, 4 * KiB); + sysbus_init_mmio(sbd, &s->dramctl_iomem); + + /* DRAMPHY registers */ + memory_region_init_io(&s->dramphy_iomem, OBJECT(s), + &allwinner_h3_dramphy_ops, s, + TYPE_AW_H3_DRAMC, 4 * KiB); + sysbus_init_mmio(sbd, &s->dramphy_iomem); +} + +static Property allwinner_h3_dramc_properties[] = { + DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0), + DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription allwinner_h3_dramc_vmstate = { + .name = "allwinner-h3-dramc", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM), + VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM), + VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_h3_dramc_reset; + dc->vmsd = &allwinner_h3_dramc_vmstate; + dc->realize = allwinner_h3_dramc_realize; + device_class_set_props(dc, allwinner_h3_dramc_properties); +} + +static const TypeInfo allwinner_h3_dramc_info = { + .name = TYPE_AW_H3_DRAMC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_h3_dramc_init, + .instance_size = sizeof(AwH3DramCtlState), + .class_init = allwinner_h3_dramc_class_init, +}; + +static void allwinner_h3_dramc_register(void) +{ + type_register_static(&allwinner_h3_dramc_info); +} + +type_init(allwinner_h3_dramc_register) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -XXX,XX +XXX,XX @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_ad allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +# allwinner-h3-dramc.c +allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror" +allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: addr 0x%" PRIx64 +allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 + # allwinner-sid.c allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> Allwinner System-on-Chips usually contain a Real Time Clock (RTC) for non-volatile system date and time keeping. This commit adds a generic Allwinner RTC device that supports the RTC devices found in Allwinner SoC family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc). The following RTC functionality and features are implemented: * Year-Month-Day read/write * Hour-Minute-Second read/write * General Purpose storage The following boards are extended with the RTC device: * Cubieboard (hw/arm/cubieboard.c) * Orange Pi PC (hw/arm/orangepi.c) Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/rtc/Makefile.objs | 1 + include/hw/arm/allwinner-a10.h | 2 + include/hw/arm/allwinner-h3.h | 3 + include/hw/rtc/allwinner-rtc.h | 134 +++++++++++ hw/arm/allwinner-a10.c | 8 + hw/arm/allwinner-h3.c | 9 +- hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++ hw/rtc/trace-events | 4 + 8 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 include/hw/rtc/allwinner-rtc.h create mode 100644 hw/rtc/allwinner-rtc.c diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/Makefile.objs +++ b/hw/rtc/Makefile.objs @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MC146818RTC) += mc146818rtc.o common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o +common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -XXX,XX +XXX,XX @@ #include "hw/ide/ahci.h" #include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ehci.h" +#include "hw/rtc/allwinner-rtc.h" #include "target/arm/cpu.h" @@ -XXX,XX +XXX,XX @@ typedef struct AwA10State { AwEmacState emac; AllwinnerAHCIState sata; AwSdHostState mmc0; + AwRtcState rtc; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/allwinner-sid.h" #include "hw/sd/allwinner-sdhost.h" #include "hw/net/allwinner-sun8i-emac.h" +#include "hw/rtc/allwinner-rtc.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" @@ -XXX,XX +XXX,XX @@ enum { AW_H3_GIC_CPU, AW_H3_GIC_HYP, AW_H3_GIC_VCPU, + AW_H3_RTC, AW_H3_CPUCFG, AW_H3_SDRAM }; @@ -XXX,XX +XXX,XX @@ typedef struct AwH3State { AwSidState sid; AwSdHostState mmc0; AwSun8iEmacState emac; + AwRtcState rtc; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/rtc/allwinner-rtc.h @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner Real Time Clock emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_MISC_ALLWINNER_RTC_H +#define HW_MISC_ALLWINNER_RTC_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * Constants + * @{ + */ + +/** Highest register address used by RTC device */ +#define AW_RTC_REGS_MAXADDR (0x200) + +/** Total number of known registers */ +#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t)) + +/** @} */ + +/** + * Object model types + * @{ + */ + +/** Generic Allwinner RTC device (abstract) */ +#define TYPE_AW_RTC "allwinner-rtc" + +/** Allwinner RTC sun4i family (A10, A12) */ +#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i" + +/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */ +#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i" + +/** Allwinner RTC sun7i family (A20) */ +#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i" + +/** @} */ + +/** + * Object model macros + * @{ + */ + +#define AW_RTC(obj) \ + OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC) +#define AW_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC) +#define AW_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC) + +/** @} */ + +/** + * Allwinner RTC per-object instance state. + */ +typedef struct AwRtcState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** + * Actual year represented by the device when year counter is zero + * + * Can be overridden by the user using the corresponding 'base-year' + * property. The base year used by the target OS driver can vary, for + * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000. + */ + int base_year; + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_RTC_REGS_NUM]; + +} AwRtcState; + +/** + * Allwinner RTC class-level struct. + * + * This struct is filled by each sunxi device specific code + * such that the generic code can use this struct to support + * all devices. + */ +typedef struct AwRtcClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + /** Defines device specific register map */ + const uint8_t *regmap; + + /** Size of the regmap in bytes */ + size_t regmap_size; + + /** + * Read device specific register + * + * @offset: register offset to read + * @return true if register read successful, false otherwise + */ + bool (*read)(AwRtcState *s, uint32_t offset); + + /** + * Write device specific register + * + * @offset: register offset to write + * @data: value to set in register + * @return true if register write successful, false otherwise + */ + bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data); + +} AwRtcClass; + +#endif /* HW_MISC_ALLWINNER_RTC_H */ diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -XXX,XX +XXX,XX @@ #define AW_A10_EHCI_BASE 0x01c14000 #define AW_A10_OHCI_BASE 0x01c14400 #define AW_A10_SATA_BASE 0x01c18000 +#define AW_A10_RTC_BASE 0x01c20d00 static void aw_a10_init(Object *obj) { @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), TYPE_AW_SDHOST_SUN4I); + + sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), + TYPE_AW_RTC_SUN4I); } static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), "sd-bus", &error_abort); + + /* RTC */ + qdev_init_nofail(DEVICE(&s->rtc)); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); } static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_GIC_CPU] = 0x01c82000, [AW_H3_GIC_HYP] = 0x01c84000, [AW_H3_GIC_VCPU] = 0x01c86000, + [AW_H3_RTC] = 0x01f00000, [AW_H3_CPUCFG] = 0x01f01c00, [AW_H3_SDRAM] = 0x40000000 }; @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { { "csi", 0x01cb0000, 320 * KiB }, { "tve", 0x01e00000, 64 * KiB }, { "hdmi", 0x01ee0000, 128 * KiB }, - { "rtc", 0x01f00000, 1 * KiB }, { "r_timer", 0x01f00800, 1 * KiB }, { "r_intc", 0x01f00c00, 1 * KiB }, { "r_wdog", 0x01f01000, 1 * KiB }, @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) "ram-addr", &error_abort); object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc), "ram-size", &error_abort); + + sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), + TYPE_AW_RTC_SUN6I); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]); + /* RTC */ + qdev_init_nofail(DEVICE(&s->rtc)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]); + /* Unimplemented devices */ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { create_unimplemented_device(unimplemented[i].device_name, diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/rtc/allwinner-rtc.c @@ -XXX,XX +XXX,XX @@ +/* + * Allwinner Real Time Clock emulation + * + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu-common.h" +#include "hw/qdev-properties.h" +#include "hw/rtc/allwinner-rtc.h" +#include "trace.h" + +/* RTC registers */ +enum { + REG_LOSC = 1, /* Low Oscillator Control */ + REG_YYMMDD, /* RTC Year-Month-Day */ + REG_HHMMSS, /* RTC Hour-Minute-Second */ + REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */ + REG_ALARM1_EN, /* Alarm1 Enable */ + REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */ + REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */ + REG_GP0, /* General Purpose Register 0 */ + REG_GP1, /* General Purpose Register 1 */ + REG_GP2, /* General Purpose Register 2 */ + REG_GP3, /* General Purpose Register 3 */ + + /* sun4i registers */ + REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */ + REG_CPUCFG, /* CPU Configuration Register */ + + /* sun6i registers */ + REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */ + REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */ + REG_ALARM0_COUNTER, /* Alarm0 Counter */ + REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */ + REG_ALARM0_ENABLE, /* Alarm0 Enable */ + REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */ + REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */ + REG_ALARM_CONFIG, /* Alarm Config */ + REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */ + REG_GP4, /* General Purpose Register 4 */ + REG_GP5, /* General Purpose Register 5 */ + REG_GP6, /* General Purpose Register 6 */ + REG_GP7, /* General Purpose Register 7 */ + REG_RTC_DBG, /* RTC Debug Register */ + REG_GPL_HOLD_OUT, /* GPL Hold Output Register */ + REG_VDD_RTC, /* VDD RTC Regulate Register */ + REG_IC_CHARA, /* IC Characteristics Register */ +}; + +/* RTC register flags */ +enum { + REG_LOSC_YMD = (1 << 7), + REG_LOSC_HMS = (1 << 8), +}; + +/* RTC sun4i register map (offset to name) */ +const uint8_t allwinner_rtc_sun4i_regmap[] = { + [0x0000] = REG_LOSC, + [0x0004] = REG_YYMMDD, + [0x0008] = REG_HHMMSS, + [0x000C] = REG_ALARM1_DDHHMMSS, + [0x0010] = REG_ALARM1_WKHHMMSS, + [0x0014] = REG_ALARM1_EN, + [0x0018] = REG_ALARM1_IRQ_EN, + [0x001C] = REG_ALARM1_IRQ_STA, + [0x0020] = REG_GP0, + [0x0024] = REG_GP1, + [0x0028] = REG_GP2, + [0x002C] = REG_GP3, + [0x003C] = REG_CPUCFG, +}; + +/* RTC sun6i register map (offset to name) */ +const uint8_t allwinner_rtc_sun6i_regmap[] = { + [0x0000] = REG_LOSC, + [0x0004] = REG_LOSC_AUTOSTA, + [0x0008] = REG_INT_OSC_PRE, + [0x0010] = REG_YYMMDD, + [0x0014] = REG_HHMMSS, + [0x0020] = REG_ALARM0_COUNTER, + [0x0024] = REG_ALARM0_CUR_VLU, + [0x0028] = REG_ALARM0_ENABLE, + [0x002C] = REG_ALARM0_IRQ_EN, + [0x0030] = REG_ALARM0_IRQ_STA, + [0x0040] = REG_ALARM1_WKHHMMSS, + [0x0044] = REG_ALARM1_EN, + [0x0048] = REG_ALARM1_IRQ_EN, + [0x004C] = REG_ALARM1_IRQ_STA, + [0x0050] = REG_ALARM_CONFIG, + [0x0060] = REG_LOSC_OUT_GATING, + [0x0100] = REG_GP0, + [0x0104] = REG_GP1, + [0x0108] = REG_GP2, + [0x010C] = REG_GP3, + [0x0110] = REG_GP4, + [0x0114] = REG_GP5, + [0x0118] = REG_GP6, + [0x011C] = REG_GP7, + [0x0170] = REG_RTC_DBG, + [0x0180] = REG_GPL_HOLD_OUT, + [0x0190] = REG_VDD_RTC, + [0x01F0] = REG_IC_CHARA, +}; + +static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset) +{ + /* no sun4i specific registers currently implemented */ + return false; +} + +static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset, + uint32_t data) +{ + /* no sun4i specific registers currently implemented */ + return false; +} + +static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset) +{ + const AwRtcClass *c = AW_RTC_GET_CLASS(s); + + switch (c->regmap[offset]) { + case REG_GP4: /* General Purpose Register 4 */ + case REG_GP5: /* General Purpose Register 5 */ + case REG_GP6: /* General Purpose Register 6 */ + case REG_GP7: /* General Purpose Register 7 */ + return true; + default: + break; + } + return false; +} + +static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset, + uint32_t data) +{ + const AwRtcClass *c = AW_RTC_GET_CLASS(s); + + switch (c->regmap[offset]) { + case REG_GP4: /* General Purpose Register 4 */ + case REG_GP5: /* General Purpose Register 5 */ + case REG_GP6: /* General Purpose Register 6 */ + case REG_GP7: /* General Purpose Register 7 */ + return true; + default: + break; + } + return false; +} + +static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwRtcState *s = AW_RTC(opaque); + const AwRtcClass *c = AW_RTC_GET_CLASS(s); + uint64_t val = 0; + + if (offset >= c->regmap_size) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + if (!c->regmap[offset]) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + switch (c->regmap[offset]) { + case REG_LOSC: /* Low Oscillator Control */ + val = s->regs[REG_LOSC]; + s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS); + break; + case REG_YYMMDD: /* RTC Year-Month-Day */ + case REG_HHMMSS: /* RTC Hour-Minute-Second */ + case REG_GP0: /* General Purpose Register 0 */ + case REG_GP1: /* General Purpose Register 1 */ + case REG_GP2: /* General Purpose Register 2 */ + case REG_GP3: /* General Purpose Register 3 */ + val = s->regs[c->regmap[offset]]; + break; + default: + if (!c->read(s, offset)) { + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n", + __func__, (uint32_t)offset); + } + val = s->regs[c->regmap[offset]]; + break; + } + + trace_allwinner_rtc_read(offset, val); + return val; +} + +static void allwinner_rtc_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwRtcState *s = AW_RTC(opaque); + const AwRtcClass *c = AW_RTC_GET_CLASS(s); + + if (offset >= c->regmap_size) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + if (!c->regmap[offset]) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + trace_allwinner_rtc_write(offset, val); + + switch (c->regmap[offset]) { + case REG_YYMMDD: /* RTC Year-Month-Day */ + s->regs[REG_YYMMDD] = val; + s->regs[REG_LOSC] |= REG_LOSC_YMD; + break; + case REG_HHMMSS: /* RTC Hour-Minute-Second */ + s->regs[REG_HHMMSS] = val; + s->regs[REG_LOSC] |= REG_LOSC_HMS; + break; + case REG_GP0: /* General Purpose Register 0 */ + case REG_GP1: /* General Purpose Register 1 */ + case REG_GP2: /* General Purpose Register 2 */ + case REG_GP3: /* General Purpose Register 3 */ + s->regs[c->regmap[offset]] = val; + break; + default: + if (!c->write(s, offset, val)) { + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n", + __func__, (uint32_t)offset); + } + break; + } +} + +static const MemoryRegionOps allwinner_rtc_ops = { + .read = allwinner_rtc_read, + .write = allwinner_rtc_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_rtc_reset(DeviceState *dev) +{ + AwRtcState *s = AW_RTC(dev); + struct tm now; + + /* Clear registers */ + memset(s->regs, 0, sizeof(s->regs)); + + /* Get current datetime */ + qemu_get_timedate(&now, 0); + + /* Set RTC with current datetime */ + if (s->base_year > 1900) { + s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) | + ((now.tm_mon + 1) << 8) | + now.tm_mday; + s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) | + (now.tm_hour << 16) | + (now.tm_min << 8) | + now.tm_sec; + } +} + +static void allwinner_rtc_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwRtcState *s = AW_RTC(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s, + TYPE_AW_RTC, 1 * KiB); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_rtc_vmstate = { + .name = "allwinner-rtc", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static Property allwinner_rtc_properties[] = { + DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void allwinner_rtc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = allwinner_rtc_reset; + dc->vmsd = &allwinner_rtc_vmstate; + device_class_set_props(dc, allwinner_rtc_properties); +} + +static void allwinner_rtc_sun4i_init(Object *obj) +{ + AwRtcState *s = AW_RTC(obj); + s->base_year = 2010; +} + +static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data) +{ + AwRtcClass *arc = AW_RTC_CLASS(klass); + + arc->regmap = allwinner_rtc_sun4i_regmap; + arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap); + arc->read = allwinner_rtc_sun4i_read; + arc->write = allwinner_rtc_sun4i_write; +} + +static void allwinner_rtc_sun6i_init(Object *obj) +{ + AwRtcState *s = AW_RTC(obj); + s->base_year = 1970; +} + +static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data) +{ + AwRtcClass *arc = AW_RTC_CLASS(klass); + + arc->regmap = allwinner_rtc_sun6i_regmap; + arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap); + arc->read = allwinner_rtc_sun6i_read; + arc->write = allwinner_rtc_sun6i_write; +} + +static void allwinner_rtc_sun7i_init(Object *obj) +{ + AwRtcState *s = AW_RTC(obj); + s->base_year = 1970; +} + +static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data) +{ + AwRtcClass *arc = AW_RTC_CLASS(klass); + allwinner_rtc_sun4i_class_init(klass, arc); +} + +static const TypeInfo allwinner_rtc_info = { + .name = TYPE_AW_RTC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_rtc_init, + .instance_size = sizeof(AwRtcState), + .class_init = allwinner_rtc_class_init, + .class_size = sizeof(AwRtcClass), + .abstract = true, +}; + +static const TypeInfo allwinner_rtc_sun4i_info = { + .name = TYPE_AW_RTC_SUN4I, + .parent = TYPE_AW_RTC, + .class_init = allwinner_rtc_sun4i_class_init, + .instance_init = allwinner_rtc_sun4i_init, +}; + +static const TypeInfo allwinner_rtc_sun6i_info = { + .name = TYPE_AW_RTC_SUN6I, + .parent = TYPE_AW_RTC, + .class_init = allwinner_rtc_sun6i_class_init, + .instance_init = allwinner_rtc_sun6i_init, +}; + +static const TypeInfo allwinner_rtc_sun7i_info = { + .name = TYPE_AW_RTC_SUN7I, + .parent = TYPE_AW_RTC, + .class_init = allwinner_rtc_sun7i_class_init, + .instance_init = allwinner_rtc_sun7i_init, +}; + +static void allwinner_rtc_register(void) +{ + type_register_static(&allwinner_rtc_info); + type_register_static(&allwinner_rtc_sun4i_info); + type_register_static(&allwinner_rtc_sun6i_info); + type_register_static(&allwinner_rtc_sun7i_info); +} + +type_init(allwinner_rtc_register) diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/trace-events +++ b/hw/rtc/trace-events @@ -XXX,XX +XXX,XX @@ # See docs/devel/tracing.txt for syntax documentation. +# allwinner-rtc.c +allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64 +allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " value 0x%" PRIx64 + # sun4v-rtc.c sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " value 0x%" PRIx64 sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value 0x%" PRIx64 -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> This test boots a Linux kernel on a OrangePi PC board and verify the serial output is working. The kernel image and DeviceTree blob are built by the Armbian project (based on Debian): https://www.armbian.com/orange-pi-pc/ If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ make check-venv $ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi: console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d console: CPU: div instructions available: patching division code console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache console: OF: fdt: Machine model: Xunlong Orange Pi PC console: Memory policy: Data cache writealloc console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000' console: cma: Failed to reserve 128 MiB console: psci: probing for conduit method from DT. console: psci: PSCIv0.2 detected in firmware. console: psci: Using standard PSCI v0.2 function IDs console: psci: Trusted OS migration not required console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0 console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728 console: Built 1 zonelists, mobility grouping on. Total pages: 32480 console: Kernel command line: printk.time=0 console=ttyS0,115200 PASS (8.59 s) JOB TIME : 8.81 s Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index XXXXXXX..XXXXXXX 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): exec_command_and_wait_for_pattern(self, 'reboot', 'reboot: Restarting system') + def test_arm_orangepi(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200n8 ' + 'earlycon=uart,mmio32,0x1c28000') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-append', kernel_command_line) + self.vm.launch() + console_pattern = 'Kernel command line: %s' % kernel_command_line + self.wait_for_console_pattern(console_pattern) + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> This test boots a Linux kernel on a OrangePi PC board and verify the serial output is working. The kernel image and DeviceTree blob are built by the Armbian project (based on Debian): https://www.armbian.com/orange-pi-pc/ The cpio image used comes from the linux-build-test project: https://github.com/groeck/linux-build-test If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d console: CPU: div instructions available: patching division code console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache console: OF: fdt: Machine model: Xunlong Orange Pi PC [...] console: Trying to unpack rootfs image as initramfs... console: Freeing initrd memory: 3256K console: Freeing unused kernel memory: 1024K console: Run /init as init process console: mount: mounting devtmpfs on /dev failed: Device or resource busy console: Starting logging: OK console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read) console: done. console: Starting network: OK console: Found console ttyS0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: Boot successful. console: cat /proc/cpuinfo console: / # cat /proc/cpuinfo console: processor : 0 console: model name : ARMv7 Processor rev 5 (v7l) console: BogoMIPS : 125.00 console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm console: CPU implementer : 0x41 console: CPU architecture: 7 console: CPU variant : 0x0 console: CPU part : 0xc07 console: CPU revision : 5 [...] console: processor : 3 console: model name : ARMv7 Processor rev 5 (v7l) console: BogoMIPS : 125.00 console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm console: CPU implementer : 0x41 console: CPU architecture: 7 console: CPU variant : 0x0 console: CPU part : 0xc07 console: CPU revision : 5 console: Hardware : Allwinner sun8i Family console: Revision : 0000 console: Serial : 0000000000000000 console: cat /proc/iomem console: / # cat /proc/iomem console: 01000000-010fffff : clock@1000000 console: 01c00000-01c00fff : system-control@1c00000 console: 01c02000-01c02fff : dma-controller@1c02000 [...] console: reboot console: / # reboot console: / # Found console ttyS0 console: Stopping network: OK console: hrtimer: interrupt took 21852064 ns console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read) console: done. console: Stopping logging: OK console: umount: devtmpfs busy - remounted read-only console: umount: can't unmount /: Invalid argument console: The system is going down NOW! console: Sent SIGTERM to all processes console: Sent SIGKILL to all processes console: Requesting system reboot console: reboot: Restarting system PASS (48.32 s) JOB TIME : 49.16 s Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index XXXXXXX..XXXXXXX 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): console_pattern = 'Kernel command line: %s' % kernel_command_line self.wait_for_console_pattern(console_pattern) + def test_arm_orangepi_initrd(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' + 'arm/rootfs-armv7a.cpio.gz') + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') + archive.gzip_uncompress(initrd_path_gz, initrd_path) + + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'panic=-1 noreboot') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-initrd', initrd_path, + '-append', kernel_command_line, + '-no-reboot') + self.vm.launch() + self.wait_for_console_pattern('Boot successful.') + + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', + 'Allwinner sun8i Family') + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', + 'system-control@1c00000') + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The kernel image and DeviceTree blob are built by the Armbian project (based on Debian): https://www.armbian.com/orange-pi-pc/ The SD image is from the kernelci.org project: https://kernelci.org/faq/#the-code If ARM is a target being built, "make check-acceptance" will automatically include this test by the use of the "arch:arm" tags. Alternatively, this test can be run using: $ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d [...] console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0) console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2 console: sunxi-mmc 1c0f000.mmc: Got CD GPIO console: ledtrig-cpu: registered to indicate activity on CPUs console: hidraw: raw HID events driver (C) Jiri Kosina console: usbcore: registered new interface driver usbhid console: usbhid: USB HID core driver console: Initializing XFRM netlink socket console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB console: NET: Registered protocol family 10 console: mmc0: host does not support reading read-only switch, assuming write-enable console: mmc0: Problem switching card into high-speed mode! console: mmc0: new SD card at address 4567 console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB [...] console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null) console: VFS: Mounted root (ext2 filesystem) on device 179:0. console: Run /sbin/init as init process console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl console: Starting syslogd: OK console: Starting klogd: OK console: Populating /dev using udev: udevd[203]: starting version 3.2.7 console: /bin/sh: can't access tty; job control turned off console: cat /proc/partitions console: / # cat /proc/partitions console: major minor #blocks name console: 1 0 4096 ram0 console: 1 1 4096 ram1 console: 1 2 4096 ram2 console: 1 3 4096 ram3 console: 179 0 61440 mmcblk0 console: reboot console: / # reboot console: umount: devtmpfs busy - remounted read-only console: EXT4-fs (mmcblk0): re-mounted. Opts: (null) console: The system is going down NOW! console: Sent SIGTERM to all processes console: Sent SIGKILL to all processes console: Requesting system reboot console: reboot: Restarting system JOB TIME : 68.64 s Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] [NL: extend test with ethernet device checks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index XXXXXXX..XXXXXXX 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): exec_command_and_wait_for_pattern(self, 'reboot', 'reboot: Restarting system') + def test_arm_orangepi_sd(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinuz-4.20.7-sunxi') + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.dtb' + dtb_path = self.extract_from_deb(deb_path, dtb_path) + rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' + 'kci-2019.02/armel/base/rootfs.ext2.xz') + rootfs_hash = '692510cb625efda31640d1de0a8d60e26040f061' + rootfs_path_xz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash) + rootfs_path = os.path.join(self.workdir, 'rootfs.cpio') + archive.lzma_uncompress(rootfs_path_xz, rootfs_path) + + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'root=/dev/mmcblk0 rootwait rw ' + 'panic=-1 noreboot') + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-drive', 'file=' + rootfs_path + ',if=sd,format=raw', + '-append', kernel_command_line, + '-no-reboot') + self.vm.launch() + shell_ready = "/bin/sh: can't access tty; job control turned off" + self.wait_for_console_pattern(shell_ready) + + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', + 'Allwinner sun8i Family') + exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', + 'mmcblk0') + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up', + 'eth0: Link is Up') + exec_command_and_wait_for_pattern(self, 'udhcpc eth0', + 'udhcpc: lease of 10.0.2.15 obtained') + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2', + '3 packets transmitted, 3 packets received, 0% packet loss') + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> This test boots Ubuntu Bionic on a OrangePi PC board. As it requires 1GB of storage, and is slow, this test is disabled on automatic CI testing. It is useful for workstation testing. Currently Avocado timeouts too quickly, so we can't run userland commands. The kernel image and DeviceTree blob are built by the Armbian project (based on Debian): https://www.armbian.com/orange-pi-pc/ The Ubuntu image is downloaded from: https://dl.armbian.com/orangepipc/Bionic_current This test can be run using: $ AVOCADO_ALLOW_LARGE_STORAGE=yes \ avocado --show=app,console run -t machine:orangepi-pc \ tests/acceptance/boot_linux_console.py console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) console: DRAM: 1024 MiB console: Failed to set core voltage! Can't set CPU frequency console: Trying to boot from MMC1 console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology console: CPU: Allwinner H3 (SUN8I 0000) console: Model: Xunlong Orange Pi PC console: DRAM: 1 GiB console: MMC: mmc@1c0f000: 0 [...] console: Uncompressing Linux... done, booting the kernel. console: Booting Linux on physical CPU 0x0 console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019 console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d console: CPU: div instructions available: patching division code console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache console: OF: fdt: Machine model: Xunlong Orange Pi PC [...] console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null) console: done. console: Begin: Running /scripts/local-bottom ... done. console: Begin: Running /scripts/init-bottom ... done. console: systemd[1]: systemd 237 running in system mode. (...) console: systemd[1]: Detected architecture arm. console: Welcome to Ubuntu 18.04.3 LTS! console: systemd[1]: Set hostname to <orangepipc>. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com [NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()] [NL: changed test to boot from SD card via BootROM, added check for 7z] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index XXXXXXX..XXXXXXX 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -XXX,XX +XXX,XX @@ from avocado_qemu import exec_command_and_wait_for_pattern from avocado_qemu import wait_for_console_pattern from avocado.utils import process from avocado.utils import archive +from avocado.utils.path import find_command, CmdNotFoundError +P7ZIP_AVAILABLE = True +try: + find_command('7z') +except CmdNotFoundError: + P7ZIP_AVAILABLE = False class BootLinuxConsole(Test): """ @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): exec_command_and_wait_for_pattern(self, 'reboot', 'reboot: Restarting system') + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') + @skipUnless(P7ZIP_AVAILABLE, '7z not installed') + def test_arm_orangepi_bionic(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + + # This test download a 196MB compressed image and expand it to 932MB... + image_url = ('https://dl.armbian.com/orangepipc/archive/' + 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z') + image_hash = '196a8ffb72b0123d92cea4a070894813d305c71e' + image_path_7z = self.fetch_asset(image_url, asset_hash=image_hash) + image_name = 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.img' + image_path = os.path.join(self.workdir, image_name) + process.run("7z e -o%s %s" % (self.workdir, image_path_7z)) + + self.vm.set_console() + self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw', + '-nic', 'user', + '-no-reboot') + self.vm.launch() + + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0,115200 ' + 'loglevel=7 ' + 'nosmp ' + 'systemd.default_timeout_start_sec=9000 ' + 'systemd.mask=armbian-zram-config.service ' + 'systemd.mask=armbian-ramlog.service') + + self.wait_for_console_pattern('U-Boot SPL') + self.wait_for_console_pattern('Autoboot in ') + exec_command_and_wait_for_pattern(self, ' ', '=>') + exec_command_and_wait_for_pattern(self, "setenv extraargs '" + + kernel_command_line + "'", '=>') + exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...'); + + self.wait_for_console_pattern('systemd[1]: Set hostname ' + + 'to <orangepipc>') + self.wait_for_console_pattern('Starting Load Kernel Modules...') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> This test boots U-Boot then NetBSD (stored on a SD card) on a OrangePi PC board. As it requires ~1.3GB of storage, it is disabled by default. U-Boot is built by the Debian project [1], and the SD card image is provided by the NetBSD organization [2]. Once the compressed SD card image is downloaded (304MB) and extracted, this test is fast: $ AVOCADO_ALLOW_LARGE_STORAGE=yes \ avocado --show=app,console run -t machine:orangepi-pc \ tests/acceptance/boot_linux_console.py console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) console: DRAM: 1024 MiB console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology console: CPU: Allwinner H3 (SUN8I 0000) console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found console: scanning usb for storage devices... 0 Storage Device(s) found console: Hit any key to stop autoboot: 0 console: => setenv bootargs root=ld0a console: => setenv kernel netbsd-GENERIC.ub console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb console: => boot console: ## Booting kernel from Legacy Image at 42000000 ... console: Image Name: NetBSD/earmv7hf 9.0_RC1 console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed) console: XIP Kernel Image (no loading done) console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK console: Starting kernel ... console: [ 1.0000000] NetBSD/evbarm (fdt) booting ... console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020 console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC console: [ 1.0000000] total memory = 1024 MB console: [ 1.0000000] avail memory = 1003 MB console: [ 1.0000000] armfdt0 (root) console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core) console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals ... console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0 console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062> console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x 2511872 sectors console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check system log. console: [ 3.1179868] boot device: ld0 console: [ 3.1470623] root on ld0a dumps on ld0b console: [ 3.2464436] root file system type: ffs console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules console: Mon Feb 17 20:33:35 UTC 2020 console: Starting root file system check: PASS (35.96 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 36.09 s Note, this test only took ~65 seconds to run on Travis-CI, see: [3]. This test is based on a description from Niek Linnenbank from [4]. [1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot [2] https://wiki.netbsd.org/ports/evbarm/allwinner/ [3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778 [4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com [NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index XXXXXXX..XXXXXXX 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -XXX,XX +XXX,XX @@ import shutil from avocado import skipUnless from avocado_qemu import Test from avocado_qemu import exec_command_and_wait_for_pattern +from avocado_qemu import interrupt_interactive_console_until_pattern from avocado_qemu import wait_for_console_pattern from avocado.utils import process from avocado.utils import archive @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): 'to <orangepipc>') self.wait_for_console_pattern('Starting Load Kernel Modules...') + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') + def test_arm_orangepi_uboot_netbsd9(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:orangepi-pc + """ + # This test download a 304MB compressed image and expand it to 1.3GB... + deb_url = ('http://snapshot.debian.org/archive/debian/' + '20200108T145233Z/pool/main/u/u-boot/' + 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb') + deb_hash = 'f67f404a80753ca3d1258f13e38f2b060e13db99' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + # We use the common OrangePi PC 'plus' build of U-Boot for our secondary + # program loader (SPL). We will then set the path to the more specific + # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot prompt, + # before to boot NetBSD. + uboot_path = '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-spl.bin' + uboot_path = self.extract_from_deb(deb_path, uboot_path) + image_url = ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/' + 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz') + image_hash = '2babb29d36d8360adcb39c09e31060945259917a' + image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash) + image_path = os.path.join(self.workdir, 'armv7.img') + image_drive_args = 'if=sd,format=raw,snapshot=on,file=' + image_path + archive.gzip_uncompress(image_path_gz, image_path) + + # dd if=u-boot-sunxi-with-spl.bin of=armv7.img bs=1K seek=8 conv=notrunc + with open(uboot_path, 'rb') as f_in: + with open(image_path, 'r+b') as f_out: + f_out.seek(8 * 1024) + shutil.copyfileobj(f_in, f_out) + + # Extend image, to avoid that NetBSD thinks the partition + # inside the image is larger than device size itself + f_out.seek(0, 2) + f_out.seek(64 * 1024 * 1024, 1) + f_out.write(bytearray([0x00])) + + self.vm.set_console() + self.vm.add_args('-nic', 'user', + '-drive', image_drive_args, + '-global', 'allwinner-rtc.base-year=2000', + '-no-reboot') + self.vm.launch() + wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1') + interrupt_interactive_console_until_pattern(self, + 'Hit any key to stop autoboot:', + 'switch to partitions #0, OK') + + exec_command_and_wait_for_pattern(self, '', '=>') + cmd = 'setenv bootargs root=ld0a' + exec_command_and_wait_for_pattern(self, cmd, '=>') + cmd = 'setenv kernel netbsd-GENERIC.ub' + exec_command_and_wait_for_pattern(self, cmd, '=>') + cmd = 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb' + exec_command_and_wait_for_pattern(self, cmd, '=>') + cmd = ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; " + "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; " + "fdt addr ${fdt_addr_r}; " + "bootm ${kernel_addr_r} - ${fdt_addr_r}'") + exec_command_and_wait_for_pattern(self, cmd, '=>') + + exec_command_and_wait_for_pattern(self, 'boot', + 'Booting kernel from Legacy Image') + wait_for_console_pattern(self, 'Starting kernel ...') + wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)') + # Wait for user-space + wait_for_console_pattern(self, 'Starting root file system check') + def test_s390x_s390_ccw_virtio(self): """ :avocado: tags=arch:s390x -- 2.20.1 From: Niek Linnenbank <nieklinnenbank@gmail.com> The Xunlong Orange Pi PC machine is a functional ARM machine based on the Allwinner H3 System-on-Chip. It supports mainline Linux, U-Boot, NetBSD and is covered by acceptance tests. This commit adds a documentation text file with a description of the machine and instructions for the user. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com [PMM: moved file into docs/system/arm to match the reorg of the arm target part of the docs; tweaked heading to match other boards] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- MAINTAINERS | 1 + docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 2 + 3 files changed, 256 insertions(+) create mode 100644 docs/system/arm/orangepi.rst diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ S: Maintained F: hw/*/allwinner-h3* F: include/hw/*/allwinner-h3* F: hw/arm/orangepi.c +F: docs/system/orangepi.rst ARM PrimeCell and CMSDK devices M: Peter Maydell <peter.maydell@linaro.org> diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/docs/system/arm/orangepi.rst @@ -XXX,XX +XXX,XX @@ +Orange Pi PC (``orangepi-pc``) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The Xunlong Orange Pi PC is an Allwinner H3 System on Chip +based embedded computer with mainline support in both U-Boot +and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz, +1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and +various other I/O. + +Supported devices +""""""""""""""""" + +The Orange Pi PC machine supports the following devices: + + * SMP (Quad Core Cortex-A7) + * Generic Interrupt Controller configuration + * SRAM mappings + * SDRAM controller + * Real Time Clock + * Timer device (re-used from Allwinner A10) + * UART + * SD/MMC storage controller + * EMAC ethernet + * USB 2.0 interfaces + * Clock Control Unit + * System Control module + * Security Identifier device + +Limitations +""""""""""" + +Currently, Orange Pi PC does *not* support the following features: + +- Graphical output via HDMI, GPU and/or the Display Engine +- Audio output +- Hardware Watchdog + +Also see the 'unimplemented' array in the Allwinner H3 SoC module +for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c`` + +Boot options +"""""""""""" + +The Orange Pi PC machine can start using the standard -kernel functionality +for loading a Linux kernel or ELF executable. Additionally, the Orange Pi PC +machine can also emulate the BootROM which is present on an actual Allwinner H3 +based SoC, which loads the bootloader from a SD card, specified via the -sd argument +to qemu-system-arm. + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +- allwinner-rtc.base-year=YYYY + + The Allwinner RTC device is automatically created by the Orange Pi PC machine + and uses a default base year value which can be overridden using the 'base-year' property. + The base year is the actual represented year when the RTC year value is zero. + This option can be used in case the target operating system driver uses a different + base year value. The minimum value for the base year is 1900. + +- allwinner-sid.identifier=abcd1122-a000-b000-c000-12345678ffff + + The Security Identifier value can be read by the guest. + For example, U-Boot uses it to determine a unique MAC address. + +The above machine-specific options can be specified in qemu-system-arm +via the '-global' argument, for example: + +.. code-block:: bash + + $ qemu-system-arm -M orangepi-pc -sd mycard.img \ + -global allwinner-rtc.base-year=2000 + +Running mainline Linux +"""""""""""""""""""""" + +Mainline Linux kernels from 4.19 up to latest master are known to work. +To build a Linux mainline kernel that can be booted by the Orange Pi PC machine, +simply configure the kernel using the sunxi_defconfig configuration: + +.. code-block:: bash + + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make mrproper + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make sunxi_defconfig + +To be able to use USB storage, you need to manually enable the corresponding +configuration item. Start the kconfig configuration tool: + +.. code-block:: bash + + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make menuconfig + +Navigate to the following item, enable it and save your configuration: + + Device Drivers > USB support > USB Mass Storage support + +Build the Linux kernel with: + +.. code-block:: bash + + $ ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- make + +To boot the newly build linux kernel in QEMU with the Orange Pi PC machine, use: + +.. code-block:: bash + + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ + -kernel /path/to/linux/arch/arm/boot/zImage \ + -append 'console=ttyS0,115200' \ + -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb + +Orange Pi PC images +""""""""""""""""""" + +Note that the mainline kernel does not have a root filesystem. You may provide it +with an official Orange Pi PC image from the official website: + + http://www.orangepi.org/downloadresources/ + +Another possibility is to run an Armbian image for Orange Pi PC which +can be downloaded from: + + https://www.armbian.com/orange-pi-pc/ + +Alternatively, you can also choose to build you own image with buildroot +using the orangepi_pc_defconfig. Also see https://buildroot.org for more information. + +You can choose to attach the selected image either as an SD card or as USB mass storage. +For example, to boot using the Orange Pi PC Debian image on SD card, simply add the -sd +argument and provide the proper root= kernel parameter: + +.. code-block:: bash + + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ + -kernel /path/to/linux/arch/arm/boot/zImage \ + -append 'console=ttyS0,115200 root=/dev/mmcblk0p2' \ + -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \ + -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img + +To attach the image as an USB mass storage device to the machine, +simply append to the command: + +.. code-block:: bash + + -drive if=none,id=stick,file=myimage.img \ + -device usb-storage,bus=usb-bus.0,drive=stick + +Instead of providing a custom Linux kernel via the -kernel command you may also +choose to let the Orange Pi PC machine load the bootloader from SD card, just like +a real board would do using the BootROM. Simply pass the selected image via the -sd +argument and remove the -kernel, -append, -dbt and -initrd arguments: + +.. code-block:: bash + + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ + -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img + +Note that both the official Orange Pi PC images and Armbian images start +a lot of userland programs via systemd. Depending on the host hardware and OS, +they may be slow to emulate, especially due to emulating the 4 cores. +To help reduce the performance slow down due to emulating the 4 cores, you can +give the following kernel parameters via U-Boot (or via -append): + +.. code-block:: bash + + => setenv extraargs 'systemd.default_timeout_start_sec=9000 loglevel=7 nosmp console=ttyS0,115200' + +Running U-Boot +"""""""""""""" + +U-Boot mainline can be build and configured using the orangepi_pc_defconfig +using similar commands as describe above for Linux. Note that it is recommended +for development/testing to select the following configuration setting in U-Boot: + + Device Tree Control > Provider for DTB for DT Control > Embedded DTB + +To start U-Boot using the Orange Pi PC machine, provide the +u-boot binary to the -kernel argument: + +.. code-block:: bash + + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ + -kernel /path/to/uboot/u-boot -sd disk.img + +Use the following U-boot commands to load and boot a Linux kernel from SD card: + +.. code-block:: bash + + => setenv bootargs console=ttyS0,115200 + => ext2load mmc 0 0x42000000 zImage + => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb + => bootz 0x42000000 - 0x43000000 + +Running NetBSD +"""""""""""""" + +The NetBSD operating system also includes support for Allwinner H3 based boards, +including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orange Pi PC +board and provides a fully working system with serial console, networking and storage. +For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from: + + https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzimg/armv7.img.gz + +The image requires manually installing U-Boot in the image. Build U-Boot with +the orangepi_pc_defconfig configuration as described in the previous section. +Next, unzip the NetBSD image and write the U-Boot binary including SPL using: + +.. code-block:: bash + + $ gunzip armv7.img.gz + $ dd if=/path/to/u-boot-sunxi-with-spl.bin of=armv7.img bs=1024 seek=8 conv=notrunc + +Finally, before starting the machine the SD image must be extended such +that the NetBSD kernel will not conclude the NetBSD partition is larger than +the emulated SD card: + +.. code-block:: bash + + $ dd if=/dev/zero bs=1M count=64 >> armv7.img + +Start the machine using the following command: + +.. code-block:: bash + + $ qemu-system-arm -M orangepi-pc -nic user -nographic \ + -sd armv7.img -global allwinner-rtc.base-year=2000 + +At the U-Boot stage, interrupt the automatic boot process by pressing a key +and set the following environment variables before booting: + +.. code-block:: bash + + => setenv bootargs root=ld0a + => setenv kernel netbsd-GENERIC.ub + => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb + => setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_addr_r} - ${fdt_addr_r}' + +Optionally you may save the environment variables to SD card with 'saveenv'. +To continue booting simply give the 'boot' command and NetBSD boots. + +Orange Pi PC acceptance tests +""""""""""""""""""""""""""""" + +The Orange Pi PC machine has several acceptance tests included. +To run the whole set of tests, build QEMU from source and simply +provide the following command: + +.. code-block:: bash + + $ AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run \ + -t machine:orangepi-pc tests/acceptance/boot_linux_console.py diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running ``qemu-system-aarch64 --machine help``. .. toctree:: + :maxdepth: 1 arm/integratorcp arm/versatile @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running arm/stellaris arm/musicpal arm/sx1 + arm/orangepi Arm CPU features ================ -- 2.20.1 From: Eric Auger <eric.auger@redhat.com> Mention 'max' value in the gic-version property description. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20200311131618.7187-2-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) virt_set_gic_version, NULL); object_property_set_description(obj, "gic-version", "Set GIC version. " - "Valid values are 2, 3 and host", NULL); + "Valid values are 2, 3, host and max", + NULL); vms->highmem_ecam = !vmc->no_highmem_ecam; -- 2.20.1 From: Eric Auger <eric.auger@redhat.com> We plan to introduce yet another value for the gic version (nosel). As we already use exotic values such as 0 and -1, let's introduce a dedicated enum type and let vms->gic_version take this type. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20200311131618.7187-3-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/virt.h | 11 +++++++++-- hw/arm/virt.c | 30 +++++++++++++++--------------- 2 files changed, 24 insertions(+), 17 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType { VIRT_IOMMU_VIRTIO, } VirtIOMMUType; +typedef enum VirtGICType { + VIRT_GIC_VERSION_MAX, + VIRT_GIC_VERSION_HOST, + VIRT_GIC_VERSION_2, + VIRT_GIC_VERSION_3, +} VirtGICType; + typedef struct MemMapEntry { hwaddr base; hwaddr size; @@ -XXX,XX +XXX,XX @@ typedef struct { bool highmem_ecam; bool its; bool virt; - int32_t gic_version; + VirtGICType gic_version; VirtIOMMUType iommu; uint16_t virtio_iommu_bdf; struct arm_boot_info bootinfo; @@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) uint32_t redist0_capacity = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; - assert(vms->gic_version == 3); + assert(vms->gic_version == VIRT_GIC_VERSION_3); return vms->smp_cpus > redist0_capacity ? 2 : 1; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; } - if (vms->gic_version == 2) { + if (vms->gic_version == VIRT_GIC_VERSION_2) { irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vms->smp_cpus) - 1); @@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); - if (vms->gic_version == 3) { + if (vms->gic_version == VIRT_GIC_VERSION_3) { int nb_redist_regions = virt_gicv3_redist_region_count(vms); qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", @@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) } } - if (vms->gic_version == 2) { + if (vms->gic_version == VIRT_GIC_VERSION_2) { irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vms->smp_cpus) - 1); @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) * purposes are to make TCG consistent (with 64-bit KVM hosts) * and to improve SGI efficiency. */ - if (vms->gic_version == 3) { + if (vms->gic_version == VIRT_GIC_VERSION_3) { clustersz = GICV3_TARGETLIST_BITS; } else { clustersz = GIC_TARGETLIST_BITS; @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) /* We can probe only here because during property set * KVM is not available yet */ - if (vms->gic_version <= 0) { - /* "host" or "max" */ + if (vms->gic_version == VIRT_GIC_VERSION_HOST || + vms->gic_version == VIRT_GIC_VERSION_MAX) { if (!kvm_enabled()) { - if (vms->gic_version == 0) { + if (vms->gic_version == VIRT_GIC_VERSION_HOST) { error_report("gic-version=host requires KVM"); exit(1); } else { /* "max": currently means 3 for TCG */ - vms->gic_version = 3; + vms->gic_version = VIRT_GIC_VERSION_3; } } else { vms->gic_version = kvm_arm_vgic_probe(); @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) /* The maximum number of CPUs depends on the GIC version, or on how * many redistributors we can fit into the memory map. */ - if (vms->gic_version == 3) { + if (vms->gic_version == VIRT_GIC_VERSION_3) { virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; virt_max_cpus += @@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp) static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); - const char *val = vms->gic_version == 3 ? "3" : "2"; + const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; return g_strdup(val); } @@ -XXX,XX +XXX,XX @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp) VirtMachineState *vms = VIRT_MACHINE(obj); if (!strcmp(value, "3")) { - vms->gic_version = 3; + vms->gic_version = VIRT_GIC_VERSION_3; } else if (!strcmp(value, "2")) { - vms->gic_version = 2; + vms->gic_version = VIRT_GIC_VERSION_2; } else if (!strcmp(value, "host")) { - vms->gic_version = 0; /* Will probe later */ + vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ } else if (!strcmp(value, "max")) { - vms->gic_version = -1; /* Will probe later */ + vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ } else { error_setg(errp, "Invalid gic-version value"); error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) "physical address space above 32 bits", NULL); /* Default GIC type is v2 */ - vms->gic_version = 2; + vms->gic_version = VIRT_GIC_VERSION_2; object_property_add_str(obj, "gic-version", virt_get_gic_version, virt_set_gic_version, NULL); object_property_set_description(obj, "gic-version", -- 2.20.1 From: Eric Auger <eric.auger@redhat.com> Let's move the code which freezes which gic-version to be applied in a dedicated function. We also now set by default the VIRT_GIC_VERSION_NO_SET. This eventually turns into the legacy v2 choice in the finalize() function. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20200311131618.7187-4-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 54 ++++++++++++++++++++++++++----------------- 2 files changed, 34 insertions(+), 21 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -XXX,XX +XXX,XX @@ typedef enum VirtGICType { VIRT_GIC_VERSION_HOST, VIRT_GIC_VERSION_2, VIRT_GIC_VERSION_3, + VIRT_GIC_VERSION_NOSEL, } VirtGICType; typedef struct MemMapEntry { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) } } +/* + * finalize_gic_version - Determines the final gic_version + * according to the gic-version property + * + * Default GIC type is v2 + */ +static void finalize_gic_version(VirtMachineState *vms) +{ + if (vms->gic_version == VIRT_GIC_VERSION_HOST || + vms->gic_version == VIRT_GIC_VERSION_MAX) { + if (!kvm_enabled()) { + if (vms->gic_version == VIRT_GIC_VERSION_HOST) { + error_report("gic-version=host requires KVM"); + exit(1); + } else { + /* "max": currently means 3 for TCG */ + vms->gic_version = VIRT_GIC_VERSION_3; + } + } else { + vms->gic_version = kvm_arm_vgic_probe(); + if (!vms->gic_version) { + error_report( + "Unable to determine GIC version supported by host"); + exit(1); + } + } + } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) { + vms->gic_version = VIRT_GIC_VERSION_2; + } +} + static void machvirt_init(MachineState *machine) { VirtMachineState *vms = VIRT_MACHINE(machine); @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) /* We can probe only here because during property set * KVM is not available yet */ - if (vms->gic_version == VIRT_GIC_VERSION_HOST || - vms->gic_version == VIRT_GIC_VERSION_MAX) { - if (!kvm_enabled()) { - if (vms->gic_version == VIRT_GIC_VERSION_HOST) { - error_report("gic-version=host requires KVM"); - exit(1); - } else { - /* "max": currently means 3 for TCG */ - vms->gic_version = VIRT_GIC_VERSION_3; - } - } else { - vms->gic_version = kvm_arm_vgic_probe(); - if (!vms->gic_version) { - error_report( - "Unable to determine GIC version supported by host"); - exit(1); - } - } - } + finalize_gic_version(vms); if (!cpu_type_valid(machine->cpu_type)) { error_report("mach-virt: CPU type %s not supported", machine->cpu_type); @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) "Set on/off to enable/disable using " "physical address space above 32 bits", NULL); - /* Default GIC type is v2 */ - vms->gic_version = VIRT_GIC_VERSION_2; + vms->gic_version = VIRT_GIC_VERSION_NOSEL; object_property_add_str(obj, "gic-version", virt_get_gic_version, virt_set_gic_version, NULL); object_property_set_description(obj, "gic-version", -- 2.20.1 From: Eric Auger <eric.auger@redhat.com> Convert kvm_arm_vgic_probe() so that it returns a bitmap of supported in-kernel emulation VGIC versions instead of the max version: at the moment values can be v2 and v3. This allows to expose the case where the host GICv3 also supports GICv2 emulation. This will be useful to choose the default version in KVM accelerated mode. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200311131618.7187-5-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/kvm_arm.h | 3 +++ hw/arm/virt.c | 11 +++++++++-- target/arm/kvm.c | 14 ++++++++------ 3 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -XXX,XX +XXX,XX @@ #include "exec/memory.h" #include "qemu/error-report.h" +#define KVM_ARM_VGIC_V2 (1 << 0) +#define KVM_ARM_VGIC_V3 (1 << 1) + /** * kvm_arm_vcpu_init: * @cs: CPUState diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) vms->gic_version = VIRT_GIC_VERSION_3; } } else { - vms->gic_version = kvm_arm_vgic_probe(); - if (!vms->gic_version) { + int probe_bitmap = kvm_arm_vgic_probe(); + + if (!probe_bitmap) { error_report( "Unable to determine GIC version supported by host"); exit(1); + } else { + if (probe_bitmap & KVM_ARM_VGIC_V3) { + vms->gic_version = VIRT_GIC_VERSION_3; + } else { + vms->gic_version = VIRT_GIC_VERSION_2; + } } } } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -XXX,XX +XXX,XX @@ int kvm_arch_irqchip_create(KVMState *s) int kvm_arm_vgic_probe(void) { + int val = 0; + if (kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { - return 3; - } else if (kvm_create_device(kvm_state, - KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { - return 2; - } else { - return 0; + val |= KVM_ARM_VGIC_V3; } + if (kvm_create_device(kvm_state, + KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { + val |= KVM_ARM_VGIC_V2; + } + return val; } int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) -- 2.20.1 From: Eric Auger <eric.auger@redhat.com> Restructure the finalize_gic_version with switch cases and clearly separate the following cases: - KVM mode / in-kernel irqchip - KVM mode / userspace irqchip - TCG mode In KVM mode / in-kernel irqchip , we explictly check whether the chosen version is supported by the host. If the end-user explicitly sets v2/v3 and this is not supported by the host, then the user gets an explicit error message. Note that for old kernels where the CREATE_DEVICE ioctl doesn't exist then we will now fail if the user specifically asked for gicv2, where previously we (probably) would have succeeded. In KVM mode / userspace irqchip we immediatly output an error in case the end-user explicitly selected v3. Also we warn the end-user about the unexpected usage of gic-version=host in that case as only userspace GICv2 is supported. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20200311131618.7187-6-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 67 insertions(+), 21 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) */ static void finalize_gic_version(VirtMachineState *vms) { - if (vms->gic_version == VIRT_GIC_VERSION_HOST || - vms->gic_version == VIRT_GIC_VERSION_MAX) { - if (!kvm_enabled()) { - if (vms->gic_version == VIRT_GIC_VERSION_HOST) { - error_report("gic-version=host requires KVM"); - exit(1); - } else { - /* "max": currently means 3 for TCG */ - vms->gic_version = VIRT_GIC_VERSION_3; - } - } else { - int probe_bitmap = kvm_arm_vgic_probe(); + if (kvm_enabled()) { + int probe_bitmap; - if (!probe_bitmap) { + if (!kvm_irqchip_in_kernel()) { + switch (vms->gic_version) { + case VIRT_GIC_VERSION_HOST: + warn_report( + "gic-version=host not relevant with kernel-irqchip=off " + "as only userspace GICv2 is supported. Using v2 ..."); + return; + case VIRT_GIC_VERSION_MAX: + case VIRT_GIC_VERSION_NOSEL: + vms->gic_version = VIRT_GIC_VERSION_2; + return; + case VIRT_GIC_VERSION_2: + return; + case VIRT_GIC_VERSION_3: error_report( - "Unable to determine GIC version supported by host"); + "gic-version=3 is not supported with kernel-irqchip=off"); exit(1); - } else { - if (probe_bitmap & KVM_ARM_VGIC_V3) { - vms->gic_version = VIRT_GIC_VERSION_3; - } else { - vms->gic_version = VIRT_GIC_VERSION_2; - } } } - } else if (vms->gic_version == VIRT_GIC_VERSION_NOSEL) { + + probe_bitmap = kvm_arm_vgic_probe(); + if (!probe_bitmap) { + error_report("Unable to determine GIC version supported by host"); + exit(1); + } + + switch (vms->gic_version) { + case VIRT_GIC_VERSION_HOST: + case VIRT_GIC_VERSION_MAX: + if (probe_bitmap & KVM_ARM_VGIC_V3) { + vms->gic_version = VIRT_GIC_VERSION_3; + } else { + vms->gic_version = VIRT_GIC_VERSION_2; + } + return; + case VIRT_GIC_VERSION_NOSEL: + vms->gic_version = VIRT_GIC_VERSION_2; + break; + case VIRT_GIC_VERSION_2: + case VIRT_GIC_VERSION_3: + break; + } + + /* Check chosen version is effectively supported by the host */ + if (vms->gic_version == VIRT_GIC_VERSION_2 && + !(probe_bitmap & KVM_ARM_VGIC_V2)) { + error_report("host does not support in-kernel GICv2 emulation"); + exit(1); + } else if (vms->gic_version == VIRT_GIC_VERSION_3 && + !(probe_bitmap & KVM_ARM_VGIC_V3)) { + error_report("host does not support in-kernel GICv3 emulation"); + exit(1); + } + return; + } + + /* TCG mode */ + switch (vms->gic_version) { + case VIRT_GIC_VERSION_NOSEL: vms->gic_version = VIRT_GIC_VERSION_2; + break; + case VIRT_GIC_VERSION_MAX: + vms->gic_version = VIRT_GIC_VERSION_3; + break; + case VIRT_GIC_VERSION_HOST: + error_report("gic-version=host requires KVM"); + exit(1); + case VIRT_GIC_VERSION_2: + case VIRT_GIC_VERSION_3: + break; } } -- 2.20.1 From: Eric Auger <eric.auger@redhat.com> At the moment if the end-user does not specify the gic-version along with KVM acceleration, v2 is set by default. However most of the systems now have GICv3 and sometimes they do not support GICv2 compatibility. This patch keeps the default v2 selection in all cases except in the KVM accelerated mode when either - the host does not support GICv2 in-kernel emulation or - number of VCPUS exceeds 8. Those cases did not work anyway so we do not break any compatibility. Now we get v3 selected in such a case. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20200311131618.7187-7-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) */ static void finalize_gic_version(VirtMachineState *vms) { + unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; + if (kvm_enabled()) { int probe_bitmap; @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) } return; case VIRT_GIC_VERSION_NOSEL: - vms->gic_version = VIRT_GIC_VERSION_2; + if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { + vms->gic_version = VIRT_GIC_VERSION_2; + } else if (probe_bitmap & KVM_ARM_VGIC_V3) { + /* + * in case the host does not support v2 in-kernel emulation or + * the end-user requested more than 8 VCPUs we now default + * to v3. In any case defaulting to v2 would be broken. + */ + vms->gic_version = VIRT_GIC_VERSION_3; + } else if (max_cpus > GIC_NCPU) { + error_report("host only supports in-kernel GICv2 emulation " + "but more than 8 vcpus are requested"); + exit(1); + } break; case VIRT_GIC_VERSION_2: case VIRT_GIC_VERSION_3: -- 2.20.1 From: Beata Michalska <beata.michalska@linaro.org> KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified. As such this should be the last step of sync to avoid potential overwriting of whatever changes KVM might have done. Signed-off-by: Beata Michalska <beata.michalska@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20200312003401.29017-2-beata.michalska@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/kvm32.c | 15 ++++++++++----- target/arm/kvm64.c | 15 ++++++++++----- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - ret = kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - write_cpustate_to_list(cpu, true); if (!write_list_to_kvmstate(cpu, level)) { return EINVAL; } + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret = kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + kvm_arm_sync_mpstate_to_kvm(cpu); return ret; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - ret = kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - write_cpustate_to_list(cpu, true); if (!write_list_to_kvmstate(cpu, level)) { return -EINVAL; } + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret = kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + kvm_arm_sync_mpstate_to_kvm(cpu); return ret; -- 2.20.1