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[PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges

Cédric Le Goater posted 2 patches 4 years, 3 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200127144506.11132-1-clg@kaod.org
Maintainers: "Michael S. Tsirkin" <mst@redhat.com>, David Gibson <david@gibson.dropbear.id.au>, "Cédric Le Goater" <clg@kaod.org>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
include/hw/pci-host/pnv_phb3.h      |  164 +++
include/hw/pci-host/pnv_phb3_regs.h |  450 +++++++++
include/hw/pci-host/pnv_phb4.h      |  230 +++++
include/hw/pci-host/pnv_phb4_regs.h |  553 ++++++++++
include/hw/pci/pcie_port.h          |    1 +
include/hw/ppc/pnv.h                |   11 +
include/hw/ppc/pnv_xscom.h          |   20 +
include/hw/ppc/xics.h               |    5 +
hw/intc/xics.c                      |   14 +-
hw/pci-host/pnv_phb3.c              | 1195 ++++++++++++++++++++++
hw/pci-host/pnv_phb3_msi.c          |  349 +++++++
hw/pci-host/pnv_phb3_pbcq.c         |  357 +++++++
hw/pci-host/pnv_phb4.c              | 1438 +++++++++++++++++++++++++++
hw/pci-host/pnv_phb4_pec.c          |  593 +++++++++++
hw/ppc/pnv.c                        |  176 +++-
hw/pci-host/Makefile.objs           |    2 +
hw/ppc/Kconfig                      |    2 +
17 files changed, 5557 insertions(+), 3 deletions(-)
create mode 100644 include/hw/pci-host/pnv_phb3.h
create mode 100644 include/hw/pci-host/pnv_phb3_regs.h
create mode 100644 include/hw/pci-host/pnv_phb4.h
create mode 100644 include/hw/pci-host/pnv_phb4_regs.h
create mode 100644 hw/pci-host/pnv_phb3.c
create mode 100644 hw/pci-host/pnv_phb3_msi.c
create mode 100644 hw/pci-host/pnv_phb3_pbcq.c
create mode 100644 hw/pci-host/pnv_phb4.c
create mode 100644 hw/pci-host/pnv_phb4_pec.c
[PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges
Posted by Cédric Le Goater 4 years, 3 months ago 
Hello,

These are models for the PCIe Host Bridges, PHB3 and PHB4, as found on
POWER8 and POWER9 processors. It includes the PowerBus logic interface
(PBCQ), IOMMU support, a single PCIe Gen.3/4 Root Complex, and support
for MSI and LSI interrupt sources as found on each system depending on
the interrupt controller: XICS or XIVE.

No default device layout is provided and PCI devices can be added on
any of the available PCIe Root Port (pcie.0 .. 2) with address 0x0 as
the firwware (skiboot) only accepts a single device per root port. To
run a simple system with a network and a storage adapters, use a
command line options such as :

  -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
  -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0

  -device megasas,id=scsi0,bus=pcie.1,addr=0x0
  -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
  -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2

If more are needed, include a bridge.

Multi chip is supported, each chip adding its set of PHB controllers
and its PCI busses. The model doesn't emulate the EEH error handling
and cold plugging PHB devices still needs some work.

XICS requires some adjustment to support the PHB3 MSI. The changes are
provided in the PHB3 model but they could be decoupled in prereq patches.

Thanks,

C.

Benjamin Herrenschmidt (1):
  ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

Cédric Le Goater (1):
  ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge

 include/hw/pci-host/pnv_phb3.h      |  164 +++
 include/hw/pci-host/pnv_phb3_regs.h |  450 +++++++++
 include/hw/pci-host/pnv_phb4.h      |  230 +++++
 include/hw/pci-host/pnv_phb4_regs.h |  553 ++++++++++
 include/hw/pci/pcie_port.h          |    1 +
 include/hw/ppc/pnv.h                |   11 +
 include/hw/ppc/pnv_xscom.h          |   20 +
 include/hw/ppc/xics.h               |    5 +
 hw/intc/xics.c                      |   14 +-
 hw/pci-host/pnv_phb3.c              | 1195 ++++++++++++++++++++++
 hw/pci-host/pnv_phb3_msi.c          |  349 +++++++
 hw/pci-host/pnv_phb3_pbcq.c         |  357 +++++++
 hw/pci-host/pnv_phb4.c              | 1438 +++++++++++++++++++++++++++
 hw/pci-host/pnv_phb4_pec.c          |  593 +++++++++++
 hw/ppc/pnv.c                        |  176 +++-
 hw/pci-host/Makefile.objs           |    2 +
 hw/ppc/Kconfig                      |    2 +
 17 files changed, 5557 insertions(+), 3 deletions(-)
 create mode 100644 include/hw/pci-host/pnv_phb3.h
 create mode 100644 include/hw/pci-host/pnv_phb3_regs.h
 create mode 100644 include/hw/pci-host/pnv_phb4.h
 create mode 100644 include/hw/pci-host/pnv_phb4_regs.h
 create mode 100644 hw/pci-host/pnv_phb3.c
 create mode 100644 hw/pci-host/pnv_phb3_msi.c
 create mode 100644 hw/pci-host/pnv_phb3_pbcq.c
 create mode 100644 hw/pci-host/pnv_phb4.c
 create mode 100644 hw/pci-host/pnv_phb4_pec.c

-- 
2.21.1
Re: [PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges
Posted by David Gibson 4 years, 3 months ago 
On Mon, Jan 27, 2020 at 03:45:04PM +0100, Cédric Le Goater wrote:
> Hello,
> 
> These are models for the PCIe Host Bridges, PHB3 and PHB4, as found on
> POWER8 and POWER9 processors. It includes the PowerBus logic interface
> (PBCQ), IOMMU support, a single PCIe Gen.3/4 Root Complex, and support
> for MSI and LSI interrupt sources as found on each system depending on
> the interrupt controller: XICS or XIVE.
> 
> No default device layout is provided and PCI devices can be added on
> any of the available PCIe Root Port (pcie.0 .. 2) with address 0x0 as
> the firwware (skiboot) only accepts a single device per root port. To
> run a simple system with a network and a storage adapters, use a
> command line options such as :
> 
>   -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
>   -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
> 
>   -device megasas,id=scsi0,bus=pcie.1,addr=0x0
>   -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
>   -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
> 
> If more are needed, include a bridge.
> 
> Multi chip is supported, each chip adding its set of PHB controllers
> and its PCI busses. The model doesn't emulate the EEH error handling
> and cold plugging PHB devices still needs some work.
> 
> XICS requires some adjustment to support the PHB3 MSI. The changes are
> provided in the PHB3 model but they could be decoupled in prereq
> patches.

Applied to ppc-for-5.0, thanks.

> 
> Thanks,
> 
> C.
> 
> Benjamin Herrenschmidt (1):
>   ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
> 
> Cédric Le Goater (1):
>   ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge
> 
>  include/hw/pci-host/pnv_phb3.h      |  164 +++
>  include/hw/pci-host/pnv_phb3_regs.h |  450 +++++++++
>  include/hw/pci-host/pnv_phb4.h      |  230 +++++
>  include/hw/pci-host/pnv_phb4_regs.h |  553 ++++++++++
>  include/hw/pci/pcie_port.h          |    1 +
>  include/hw/ppc/pnv.h                |   11 +
>  include/hw/ppc/pnv_xscom.h          |   20 +
>  include/hw/ppc/xics.h               |    5 +
>  hw/intc/xics.c                      |   14 +-
>  hw/pci-host/pnv_phb3.c              | 1195 ++++++++++++++++++++++
>  hw/pci-host/pnv_phb3_msi.c          |  349 +++++++
>  hw/pci-host/pnv_phb3_pbcq.c         |  357 +++++++
>  hw/pci-host/pnv_phb4.c              | 1438 +++++++++++++++++++++++++++
>  hw/pci-host/pnv_phb4_pec.c          |  593 +++++++++++
>  hw/ppc/pnv.c                        |  176 +++-
>  hw/pci-host/Makefile.objs           |    2 +
>  hw/ppc/Kconfig                      |    2 +
>  17 files changed, 5557 insertions(+), 3 deletions(-)
>  create mode 100644 include/hw/pci-host/pnv_phb3.h
>  create mode 100644 include/hw/pci-host/pnv_phb3_regs.h
>  create mode 100644 include/hw/pci-host/pnv_phb4.h
>  create mode 100644 include/hw/pci-host/pnv_phb4_regs.h
>  create mode 100644 hw/pci-host/pnv_phb3.c
>  create mode 100644 hw/pci-host/pnv_phb3_msi.c
>  create mode 100644 hw/pci-host/pnv_phb3_pbcq.c
>  create mode 100644 hw/pci-host/pnv_phb4.c
>  create mode 100644 hw/pci-host/pnv_phb4_pec.c
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
Re: [PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges
Posted by Cédric Le Goater 4 years, 3 months ago 
On 1/29/20 7:31 AM, David Gibson wrote:
> On Mon, Jan 27, 2020 at 03:45:04PM +0100, Cédric Le Goater wrote:
>> Hello,
>>
>> These are models for the PCIe Host Bridges, PHB3 and PHB4, as found on
>> POWER8 and POWER9 processors. It includes the PowerBus logic interface
>> (PBCQ), IOMMU support, a single PCIe Gen.3/4 Root Complex, and support
>> for MSI and LSI interrupt sources as found on each system depending on
>> the interrupt controller: XICS or XIVE.
>>
>> No default device layout is provided and PCI devices can be added on
>> any of the available PCIe Root Port (pcie.0 .. 2) with address 0x0 as
>> the firwware (skiboot) only accepts a single device per root port. To
>> run a simple system with a network and a storage adapters, use a
>> command line options such as :
>>
>>   -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
>>   -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
>>
>>   -device megasas,id=scsi0,bus=pcie.1,addr=0x0
>>   -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
>>   -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
>>
>> If more are needed, include a bridge.
>>
>> Multi chip is supported, each chip adding its set of PHB controllers
>> and its PCI busses. The model doesn't emulate the EEH error handling
>> and cold plugging PHB devices still needs some work.
>>
>> XICS requires some adjustment to support the PHB3 MSI. The changes are
>> provided in the PHB3 model but they could be decoupled in prereq
>> patches.
> 
> Applied to ppc-for-5.0, thanks.

Should we add a default set of devices on PHB1 like found on OpenPOWER 
system ? On a P8 we have  :

 +-[0001:00]---00.0-[01-07]----00.0-[02-07]--+-01.0-[03-04]----00.0-[04]----00.0  ASPEED Technology, Inc. ASPEED Graphics Family
 |                                           +-02.0-[05]----00.0  Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller
 |                                           +-03.0-[06]--+-00.0  Broadcom Inc. and subsidiaries NetXtreme BCM5718 Gigabit Ethernet PCIe
 |                                           |            \-00.1  Broadcom Inc. and subsidiaries NetXtreme BCM5718 Gigabit Ethernet PCIe
 |                                           \-04.0-[07]----00.0  Marvell Technology Group Ltd. 88SE9235 PCIe 2.0 x2 4-port SATA 6 Gb/s Controller


C.
Re: [PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges
Posted by David Gibson 4 years, 3 months ago 
On Wed, Jan 29, 2020 at 02:15:35PM +0100, Cédric Le Goater wrote:
> On 1/29/20 7:31 AM, David Gibson wrote:
> > On Mon, Jan 27, 2020 at 03:45:04PM +0100, Cédric Le Goater wrote:
> >> Hello,
> >>
> >> These are models for the PCIe Host Bridges, PHB3 and PHB4, as found on
> >> POWER8 and POWER9 processors. It includes the PowerBus logic interface
> >> (PBCQ), IOMMU support, a single PCIe Gen.3/4 Root Complex, and support
> >> for MSI and LSI interrupt sources as found on each system depending on
> >> the interrupt controller: XICS or XIVE.
> >>
> >> No default device layout is provided and PCI devices can be added on
> >> any of the available PCIe Root Port (pcie.0 .. 2) with address 0x0 as
> >> the firwware (skiboot) only accepts a single device per root port. To
> >> run a simple system with a network and a storage adapters, use a
> >> command line options such as :
> >>
> >>   -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
> >>   -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
> >>
> >>   -device megasas,id=scsi0,bus=pcie.1,addr=0x0
> >>   -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
> >>   -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
> >>
> >> If more are needed, include a bridge.
> >>
> >> Multi chip is supported, each chip adding its set of PHB controllers
> >> and its PCI busses. The model doesn't emulate the EEH error handling
> >> and cold plugging PHB devices still needs some work.
> >>
> >> XICS requires some adjustment to support the PHB3 MSI. The changes are
> >> provided in the PHB3 model but they could be decoupled in prereq
> >> patches.
> > 
> > Applied to ppc-for-5.0, thanks.
> 
> Should we add a default set of devices on PHB1 like found on OpenPOWER 
> system ? On a P8 we have  :

I think that's kind of up to you.

> 
>  +-[0001:00]---00.0-[01-07]----00.0-[02-07]--+-01.0-[03-04]----00.0-[04]----00.0  ASPEED Technology, Inc. ASPEED Graphics Family
>  |                                           +-02.0-[05]----00.0  Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller
>  |                                           +-03.0-[06]--+-00.0  Broadcom Inc. and subsidiaries NetXtreme BCM5718 Gigabit Ethernet PCIe
>  |                                           |            \-00.1  Broadcom Inc. and subsidiaries NetXtreme BCM5718 Gigabit Ethernet PCIe
>  |                                           \-04.0-[07]----00.0  Marvell Technology Group Ltd. 88SE9235 PCIe 2.0 x2 4-port SATA 6 Gb/s Controller
> 
> 
> C.
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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