From: Eric Auger <eric.auger@redhat.com>

We are missing the VIRT_COMPAT_3_0 definition and setting.

Let's add them.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Message-id: 20181024085602.16611-1-eric.auger@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/virt.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void virt_machine_3_1_options(MachineClass *mc)

}

DEFINE_VIRT_MACHINE_AS_LATEST(3, 1)

+#define VIRT_COMPAT_3_0 \

+ HW_COMPAT_3_0

+

static void virt_3_0_instance_init(Object *obj)

{

virt_3_1_instance_init(obj);

@@ -XXX,XX +XXX,XX @@ static void virt_3_0_instance_init(Object *obj)

static void virt_machine_3_0_options(MachineClass *mc)

{

virt_machine_3_1_options(mc);

+ SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0);

}

DEFINE_VIRT_MACHINE(3, 0)

--

2.19.1

From: Julia Suvorova <jusual@mail.ru>

Not implemented: CTS/NCTS, PSEL*.

Signed-off-by: Julia Suvorova <jusual@mail.ru>

Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/char/Makefile.objs | 1 +

include/hw/char/nrf51_uart.h | 78 +++++++++

hw/char/nrf51_uart.c | 330 +++++++++++++++++++++++++++++++++++

hw/char/trace-events | 4 +

4 files changed, 413 insertions(+)

create mode 100644 include/hw/char/nrf51_uart.h

create mode 100644 hw/char/nrf51_uart.c

diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/char/Makefile.objs

+++ b/hw/char/Makefile.objs

@@ -XXX,XX +XXX,XX @@

common-obj-$(CONFIG_IPACK) += ipoctal232.o

common-obj-$(CONFIG_ESCC) += escc.o

+common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o

common-obj-$(CONFIG_PARALLEL) += parallel.o

common-obj-$(CONFIG_PARALLEL) += parallel-isa.o

common-obj-$(CONFIG_PL011) += pl011.o

diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/char/nrf51_uart.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * nRF51 SoC UART emulation

+ *

+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+ */

+

+#ifndef NRF51_UART_H

+#define NRF51_UART_H

+

+#include "hw/sysbus.h"

+#include "chardev/char-fe.h"

+#include "hw/registerfields.h"

+

+#define UART_FIFO_LENGTH 6

+#define UART_BASE 0x40002000

+#define UART_SIZE 0x1000

+

+#define TYPE_NRF51_UART "nrf51_soc.uart"

+#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UART)

+

+REG32(UART_STARTRX, 0x000)

+REG32(UART_STOPRX, 0x004)

+REG32(UART_STARTTX, 0x008)

+REG32(UART_STOPTX, 0x00C)

+REG32(UART_SUSPEND, 0x01C)

+

+REG32(UART_CTS, 0x100)

+REG32(UART_NCTS, 0x104)

+REG32(UART_RXDRDY, 0x108)

+REG32(UART_TXDRDY, 0x11C)

+REG32(UART_ERROR, 0x124)

+REG32(UART_RXTO, 0x144)

+

+REG32(UART_INTEN, 0x300)

+ FIELD(UART_INTEN, CTS, 0, 1)

+ FIELD(UART_INTEN, NCTS, 1, 1)

+ FIELD(UART_INTEN, RXDRDY, 2, 1)

+ FIELD(UART_INTEN, TXDRDY, 7, 1)

+ FIELD(UART_INTEN, ERROR, 9, 1)

+ FIELD(UART_INTEN, RXTO, 17, 1)

+REG32(UART_INTENSET, 0x304)

+REG32(UART_INTENCLR, 0x308)

+REG32(UART_ERRORSRC, 0x480)

+REG32(UART_ENABLE, 0x500)

+REG32(UART_PSELRTS, 0x508)

+REG32(UART_PSELTXD, 0x50C)

+REG32(UART_PSELCTS, 0x510)

+REG32(UART_PSELRXD, 0x514)

+REG32(UART_RXD, 0x518)

+REG32(UART_TXD, 0x51C)

+REG32(UART_BAUDRATE, 0x524)

+REG32(UART_CONFIG, 0x56C)

+

+typedef struct NRF51UARTState {

+ SysBusDevice parent_obj;

+

+ MemoryRegion iomem;

+ CharBackend chr;

+ qemu_irq irq;

+ guint watch_tag;

+

+ uint8_t rx_fifo[UART_FIFO_LENGTH];

+ unsigned int rx_fifo_pos;

+ unsigned int rx_fifo_len;

+

+ uint32_t reg[0x56C];

+

+ bool rx_started;

+ bool tx_started;

+ bool pending_tx_byte;

+ bool enabled;

+} NRF51UARTState;

+

+#endif

diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/char/nrf51_uart.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * nRF51 SoC UART emulation

+ *

+ * See nRF51 Series Reference Manual, "29 Universal Asynchronous

+ * Receiver/Transmitter" for hardware specifications:

+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf

+ *

+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "hw/char/nrf51_uart.h"

+#include "trace.h"

+

+static void nrf51_uart_update_irq(NRF51UARTState *s)

+{

+ bool irq = false;

+

+ irq |= (s->reg[R_UART_RXDRDY] &&

+ (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));

+ irq |= (s->reg[R_UART_TXDRDY] &&

+ (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));

+ irq |= (s->reg[R_UART_ERROR] &&

+ (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));

+ irq |= (s->reg[R_UART_RXTO] &&

+ (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));

+

+ qemu_set_irq(s->irq, irq);

+}

+

+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)

+{

+ NRF51UARTState *s = NRF51_UART(opaque);

+ uint64_t r;

+

+ if (!s->enabled) {

+ return 0;

+ }

+

+ switch (addr) {

+ case A_UART_RXD:

+ r = s->rx_fifo[s->rx_fifo_pos];

+ if (s->rx_started && s->rx_fifo_len) {

+ s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;

+ s->rx_fifo_len--;

+ if (s->rx_fifo_len) {

+ s->reg[R_UART_RXDRDY] = 1;

+ nrf51_uart_update_irq(s);

+ }

+ qemu_chr_fe_accept_input(&s->chr);

+ }

+ break;

+ case A_UART_INTENSET:

+ case A_UART_INTENCLR:

+ case A_UART_INTEN:

+ r = s->reg[R_UART_INTEN];

+ break;

+ default:

+ r = s->reg[addr / 4];

+ break;

+ }

+

+ trace_nrf51_uart_read(addr, r, size);

+

+ return r;

+}

+

+static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)

+{

+ NRF51UARTState *s = NRF51_UART(opaque);

+ int r;

+ uint8_t c = s->reg[R_UART_TXD];

+

+ s->watch_tag = 0;

+

+ r = qemu_chr_fe_write(&s->chr, &c, 1);

+ if (r <= 0) {

+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,

+ uart_transmit, s);

+ if (!s->watch_tag) {

+ /* The hardware has no transmit error reporting,

+ * so silently drop the byte

+ */

+ goto buffer_drained;

+ }

+ return FALSE;

+ }

+

+buffer_drained:

+ s->reg[R_UART_TXDRDY] = 1;

+ s->pending_tx_byte = false;

+ return FALSE;

+}

+

+static void uart_cancel_transmit(NRF51UARTState *s)

+{

+ if (s->watch_tag) {

+ g_source_remove(s->watch_tag);

+ s->watch_tag = 0;

+ }

+}

+

+static void uart_write(void *opaque, hwaddr addr,

+ uint64_t value, unsigned int size)

+{

+ NRF51UARTState *s = NRF51_UART(opaque);

+

+ trace_nrf51_uart_write(addr, value, size);

+

+ if (!s->enabled && (addr != A_UART_ENABLE)) {

+ return;

+ }

+

+ switch (addr) {

+ case A_UART_TXD:

+ if (!s->pending_tx_byte && s->tx_started) {

+ s->reg[R_UART_TXD] = value;

+ s->pending_tx_byte = true;

+ uart_transmit(NULL, G_IO_OUT, s);

+ }

+ break;

+ case A_UART_INTEN:

+ s->reg[R_UART_INTEN] = value;

+ break;

+ case A_UART_INTENSET:

+ s->reg[R_UART_INTEN] |= value;

+ break;

+ case A_UART_INTENCLR:

+ s->reg[R_UART_INTEN] &= ~value;

+ break;

+ case A_UART_TXDRDY ... A_UART_RXTO:

+ s->reg[addr / 4] = value;

+ break;

+ case A_UART_ERRORSRC:

+ s->reg[addr / 4] &= ~value;

+ break;

+ case A_UART_RXD:

+ break;

+ case A_UART_RXDRDY:

+ if (value == 0) {

+ s->reg[R_UART_RXDRDY] = 0;

+ }

+ break;

+ case A_UART_STARTTX:

+ if (value == 1) {

+ s->tx_started = true;

+ }

+ break;

+ case A_UART_STARTRX:

+ if (value == 1) {

+ s->rx_started = true;

+ }

+ break;

+ case A_UART_ENABLE:

+ if (value) {

+ if (value == 4) {

+ s->enabled = true;

+ }

+ break;

+ }

+ s->enabled = false;

+ value = 1;

+ /* fall through */

+ case A_UART_SUSPEND:

+ case A_UART_STOPTX:

+ if (value == 1) {

+ s->tx_started = false;

+ }

+ /* fall through */

+ case A_UART_STOPRX:

+ if (addr != A_UART_STOPTX && value == 1) {

+ s->rx_started = false;

+ s->reg[R_UART_RXTO] = 1;

+ }

+ break;

+ default:

+ s->reg[addr / 4] = value;

+ break;

+ }

+ nrf51_uart_update_irq(s);

+}

+

+static const MemoryRegionOps uart_ops = {

+ .read = uart_read,

+ .write = uart_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+};

+

+static void nrf51_uart_reset(DeviceState *dev)

+{

+ NRF51UARTState *s = NRF51_UART(dev);

+

+ s->pending_tx_byte = 0;

+

+ uart_cancel_transmit(s);

+

+ memset(s->reg, 0, sizeof(s->reg));

+

+ s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;

+ s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;

+ s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;

+ s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;

+ s->reg[R_UART_BAUDRATE] = 0x4000000;

+

+ s->rx_fifo_len = 0;

+ s->rx_fifo_pos = 0;

+ s->rx_started = false;

+ s->tx_started = false;

+ s->enabled = false;

+}

+

+static void uart_receive(void *opaque, const uint8_t *buf, int size)

+{

+

+ NRF51UARTState *s = NRF51_UART(opaque);

+ int i;

+

+ if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {

+ return;

+ }

+

+ for (i = 0; i < size; i++) {

+ uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;

+ s->rx_fifo[pos] = buf[i];

+ s->rx_fifo_len++;

+ }

+

+ s->reg[R_UART_RXDRDY] = 1;

+ nrf51_uart_update_irq(s);

+}

+

+static int uart_can_receive(void *opaque)

+{

+ NRF51UARTState *s = NRF51_UART(opaque);

+

+ return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;

+}

+

+static void uart_event(void *opaque, int event)

+{

+ NRF51UARTState *s = NRF51_UART(opaque);

+

+ if (event == CHR_EVENT_BREAK) {

+ s->reg[R_UART_ERRORSRC] |= 3;

+ s->reg[R_UART_ERROR] = 1;

+ nrf51_uart_update_irq(s);

+ }

+}

+

+static void nrf51_uart_realize(DeviceState *dev, Error **errp)

+{

+ NRF51UARTState *s = NRF51_UART(dev);

+

+ qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,

+ uart_event, NULL, s, NULL, true);

+}

+

+static void nrf51_uart_init(Object *obj)

+{

+ NRF51UARTState *s = NRF51_UART(obj);

+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

+

+ memory_region_init_io(&s->iomem, obj, &uart_ops, s,

+ "nrf51_soc.uart", UART_SIZE);

+ sysbus_init_mmio(sbd, &s->iomem);

+ sysbus_init_irq(sbd, &s->irq);

+}

+

+static int nrf51_uart_post_load(void *opaque, int version_id)

+{

+ NRF51UARTState *s = NRF51_UART(opaque);

+

+ if (s->pending_tx_byte) {

+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,

+ uart_transmit, s);

+ }

+

+ return 0;

+}

+

+static const VMStateDescription nrf51_uart_vmstate = {

+ .name = "nrf51_soc.uart",

+ .post_load = nrf51_uart_post_load,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),

+ VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),

+ VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),

+ VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),

+ VMSTATE_BOOL(rx_started, NRF51UARTState),

+ VMSTATE_BOOL(tx_started, NRF51UARTState),

+ VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),

+ VMSTATE_BOOL(enabled, NRF51UARTState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static Property nrf51_uart_properties[] = {

+ DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void nrf51_uart_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = nrf51_uart_reset;

+ dc->realize = nrf51_uart_realize;

+ dc->props = nrf51_uart_properties;

+ dc->vmsd = &nrf51_uart_vmstate;

+}

+

+static const TypeInfo nrf51_uart_info = {

+ .name = TYPE_NRF51_UART,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(NRF51UARTState),

+ .instance_init = nrf51_uart_init,

+ .class_init = nrf51_uart_class_init

+};

+

+static void nrf51_uart_register_types(void)

+{

+ type_register_static(&nrf51_uart_info);

+}

+

+type_init(nrf51_uart_register_types)

diff --git a/hw/char/trace-events b/hw/char/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/char/trace-events

+++ b/hw/char/trace-events

@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backe

cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"

cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"

cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"

+

+# hw/char/nrf51_uart.c

+nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"

+nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"

--

2.19.1

From: Julia Suvorova <jusual@mail.ru>

Wire up nRF51 UART in the corresponding SoC.

Signed-off-by: Julia Suvorova <jusual@mail.ru>

Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/arm/nrf51_soc.h | 3 +++

hw/arm/microbit.c | 2 ++

hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++

3 files changed, 25 insertions(+)

diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/nrf51_soc.h

+++ b/include/hw/arm/nrf51_soc.h

@@ -XXX,XX +XXX,XX @@

#include "hw/sysbus.h"

#include "hw/arm/armv7m.h"

+#include "hw/char/nrf51_uart.h"

#define TYPE_NRF51_SOC "nrf51-soc"

#define NRF51_SOC(obj) \

@@ -XXX,XX +XXX,XX @@ typedef struct NRF51State {

/*< public >*/

ARMv7MState cpu;

+ NRF51UARTState uart;

+

MemoryRegion iomem;

MemoryRegion sram;

MemoryRegion flash;

diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/microbit.c

+++ b/hw/arm/microbit.c

@@ -XXX,XX +XXX,XX @@

#include "qapi/error.h"

#include "hw/boards.h"

#include "hw/arm/arm.h"

+#include "sysemu/sysemu.h"

#include "exec/address-spaces.h"

#include "hw/arm/nrf51_soc.h"

@@ -XXX,XX +XXX,XX @@ static void microbit_init(MachineState *machine)

sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),

TYPE_NRF51_SOC);

+ qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));

object_property_set_link(soc, OBJECT(system_memory), "memory",

&error_fatal);

object_property_set_bool(soc, true, "realized", &error_fatal);

diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/nrf51_soc.c

+++ b/hw/arm/nrf51_soc.c

@@ -XXX,XX +XXX,XX @@

#define NRF51822_FLASH_SIZE (256 * 1024)

#define NRF51822_SRAM_SIZE (16 * 1024)

+#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)

+

static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

{

NRF51State *s = NRF51_SOC(dev_soc);

+ MemoryRegion *mr;

Error *err = NULL;

if (!s->board_memory) {

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

}

memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);

+ /* UART */

+ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);

+ memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,

+ qdev_get_gpio_in(DEVICE(&s->cpu),

+ BASE_TO_IRQ(UART_BASE)));

+

create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);

create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);

create_unimplemented_device("nrf51_soc.private",

@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_init(Object *obj)

qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",

ARM_CPU_TYPE_NAME("cortex-m0"));

qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);

+

+ sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),

+ TYPE_NRF51_UART);

+ object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",

+ &error_abort);

}

static Property nrf51_soc_properties[] = {

--

2.19.1

From: Julia Suvorova <jusual@mail.ru>

New mini-kernel test for nRF51 SoC UART.

Signed-off-by: Julia Suvorova <jusual@mail.ru>

Acked-by: Thomas Huth <thuth@redhat.com>

Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

tests/boot-serial-test.c | 19 +++++++++++++++++++

1 file changed, 19 insertions(+)

diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c

index XXXXXXX..XXXXXXX 100644

--- a/tests/boot-serial-test.c

+++ b/tests/boot-serial-test.c

@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_aarch64[] = {

0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */

};

+static const uint8_t kernel_nrf51[] = {

+ 0x00, 0x00, 0x00, 0x00, /* Stack top address */

+ 0x09, 0x00, 0x00, 0x00, /* Reset handler address */

+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get ENABLE */

+ 0x04, 0x21, /* movs r1, #4 */

+ 0x11, 0x60, /* str r1, [r2] */

+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get STARTTX */

+ 0x01, 0x21, /* movs r1, #1 */

+ 0x11, 0x60, /* str r1, [r2] */

+ 0x03, 0x4a, /* ldr r2, [pc, #12] Get TXD */

+ 0x54, 0x21, /* movs r1, 'T' */

+ 0x11, 0x60, /* str r1, [r2] */

+ 0xfe, 0xe7, /* b . */

+ 0x00, 0x25, 0x00, 0x40, /* 0x40002500 = UART ENABLE */

+ 0x08, 0x20, 0x00, 0x40, /* 0x40002008 = UART STARTTX */

+ 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */

+};

+

typedef struct testdef {

const char *arch; /* Target architecture */

const char *machine; /* Name of the machine */

@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {

{ "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },

{ "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),

kernel_aarch64 },

+ { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },

{ NULL }

};

--

2.19.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Shannon Zhao's email at Huawei is bouncing: remove it.

X-Failed-Recipients: zhaoshenglong@huawei.com

** Address not found **

Your message wasn't delivered to zhaoshenglong@huawei.com because the address couldn't be found, or is unable to receive mail.

Note that the section still contains his personal email (see e59f13d76bb).

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Acked-by: Shannon Zhao <shannon.zhaosl@gmail.com>

Message-id: 20181029195931.8747-1-philmd@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

MAINTAINERS | 1 -

1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS

index XXXXXXX..XXXXXXX 100644

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F: hw/*/xlnx*.c

F: include/hw/*/xlnx*.h

ARM ACPI Subsystem

-M: Shannon Zhao <zhaoshenglong@huawei.com>

M: Shannon Zhao <shannon.zhaosl@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

--

2.19.1

From: Prasad J Pandit <pjp@fedoraproject.org>

The high[31:28] bits of 'direction' and 'state' registers of

SA-1100/SA-1110 device are reserved. Setting them may lead to

OOB 's->handler[]' array access issue. Mask off [31:28] bits to

avoid it.

Reported-by: Moguofang <moguofang@huawei.com>

Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>

Message-id: 20181030114635.31232-1-ppandit@redhat.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/strongarm.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/strongarm.c

+++ b/hw/arm/strongarm.c

@@ -XXX,XX +XXX,XX @@ static void strongarm_gpio_write(void *opaque, hwaddr offset,

switch (offset) {

case GPDR: /* GPIO Pin-Direction registers */

- s->dir = value;

+ s->dir = value & 0x0fffffff;

strongarm_gpio_handler_update(s);

break;

case GPSR: /* GPIO Pin-Output Set registers */

- s->olevel |= value;

+ s->olevel |= value & 0x0fffffff;

strongarm_gpio_handler_update(s);

break;

--

2.19.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xilinx_zynq.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xilinx_zynq.c

+++ b/hw/arm/xilinx_zynq.c

@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)

busdev = SYS_BUS_DEVICE(dev);

sysbus_mmio_map(busdev, 0, 0xF8003000);

sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */

- for (n = 0; n < 8; ++n) { /* event irqs */

+ for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */

sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);

}

--

2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

When populating id registers from kvm, on a host that doesn't support

aarch32 mode at all, neither arm_div nor jazelle will be supported either.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20181102102025.3546-1-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 5 +++++

target/arm/cpu.c | 15 +++++++++++++--

2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;

}

+static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)

+{

+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;

+}

+

static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)

{

return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

CPUARMState *env = &cpu->env;

int pagebits;

Error *local_err = NULL;

+ bool no_aa32 = false;

/* If we needed to query the host kernel for the CPU features

* then it's possible that might have failed in the initfn, but

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

set_feature(env, ARM_FEATURE_V7VE);

}

}

+

+ /*

+ * There exist AArch64 cpus without AArch32 support. When KVM

+ * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.

+ * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.

+ */

+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {

+ no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);

+ }

+

if (arm_feature(env, ARM_FEATURE_V7VE)) {

/* v7 Virtualization Extensions. In real hardware this implies

* EL2 and also the presence of the Security Extensions.

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

* Presence of EL2 itself is ARM_FEATURE_EL2, and of the

* Security Extensions is ARM_FEATURE_EL3.

*/

- assert(cpu_isar_feature(arm_div, cpu));

+ assert(no_aa32 || cpu_isar_feature(arm_div, cpu));

set_feature(env, ARM_FEATURE_LPAE);

set_feature(env, ARM_FEATURE_V7);

}

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

if (arm_feature(env, ARM_FEATURE_V6)) {

set_feature(env, ARM_FEATURE_V5);

if (!arm_feature(env, ARM_FEATURE_M)) {

- assert(cpu_isar_feature(jazelle, cpu));

+ assert(no_aa32 || cpu_isar_feature(jazelle, cpu));

set_feature(env, ARM_FEATURE_AUXCR);

}

}

--

2.19.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add a model of Xilinx Versal SoC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/Makefile.objs | 1 +

include/hw/arm/xlnx-versal.h | 122 +++++++++++

hw/arm/xlnx-versal.c | 323 ++++++++++++++++++++++++++++

default-configs/aarch64-softmmu.mak | 1 +

4 files changed, 447 insertions(+)

create mode 100644 include/hw/arm/xlnx-versal.h

create mode 100644 hw/arm/xlnx-versal.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o

obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o

obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o

obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o

+obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o

obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o

obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/arm/xlnx-versal.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Model of the Xilinx Versal

+ *

+ * Copyright (c) 2018 Xilinx Inc.

+ * Written by Edgar E. Iglesias

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+ */

+

+#ifndef XLNX_VERSAL_H

+#define XLNX_VERSAL_H

+

+#include "hw/sysbus.h"

+#include "hw/arm/arm.h"

+#include "hw/intc/arm_gicv3.h"

+

+#define TYPE_XLNX_VERSAL "xlnx-versal"

+#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)

+

+#define XLNX_VERSAL_NR_ACPUS 2

+#define XLNX_VERSAL_NR_UARTS 2

+#define XLNX_VERSAL_NR_GEMS 2

+#define XLNX_VERSAL_NR_IRQS 256

+

+typedef struct Versal {

+ /*< private >*/

+ SysBusDevice parent_obj;

+

+ /*< public >*/

+ struct {

+ struct {

+ MemoryRegion mr;

+ ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];

+ GICv3State gic;

+ } apu;

+ } fpd;

+

+ MemoryRegion mr_ps;

+

+ struct {

+ /* 4 ranges to access DDR. */

+ MemoryRegion mr_ddr_ranges[4];

+ } noc;

+

+ struct {

+ MemoryRegion mr_ocm;

+

+ struct {

+ SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];

+ SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];

+ } iou;

+ } lpd;

+

+ struct {

+ MemoryRegion *mr_ddr;

+ uint32_t psci_conduit;

+ } cfg;

+} Versal;

+

+/* Memory-map and IRQ definitions. Copied a subset from

+ * auto-generated files. */

+

+#define VERSAL_GIC_MAINT_IRQ 9

+#define VERSAL_TIMER_VIRT_IRQ 11

+#define VERSAL_TIMER_S_EL1_IRQ 13

+#define VERSAL_TIMER_NS_EL1_IRQ 14

+#define VERSAL_TIMER_NS_EL2_IRQ 10

+

+#define VERSAL_UART0_IRQ_0 18

+#define VERSAL_UART1_IRQ_0 19

+#define VERSAL_GEM0_IRQ_0 56

+#define VERSAL_GEM0_WAKE_IRQ_0 57

+#define VERSAL_GEM1_IRQ_0 58

+#define VERSAL_GEM1_WAKE_IRQ_0 59

+

+/* Architecturally eserved IRQs suitable for virtualization. */

+#define VERSAL_RSVD_HIGH_IRQ_FIRST 160

+#define VERSAL_RSVD_HIGH_IRQ_LAST 255

+

+#define MM_TOP_RSVD 0xa0000000U

+#define MM_TOP_RSVD_SIZE 0x4000000

+#define MM_GIC_APU_DIST_MAIN 0xf9000000U

+#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000

+#define MM_GIC_APU_REDIST_0 0xf9080000U

+#define MM_GIC_APU_REDIST_0_SIZE 0x80000

+

+#define MM_UART0 0xff000000U

+#define MM_UART0_SIZE 0x10000

+#define MM_UART1 0xff010000U

+#define MM_UART1_SIZE 0x10000

+

+#define MM_GEM0 0xff0c0000U

+#define MM_GEM0_SIZE 0x10000

+#define MM_GEM1 0xff0d0000U

+#define MM_GEM1_SIZE 0x10000

+

+#define MM_OCM 0xfffc0000U

+#define MM_OCM_SIZE 0x40000

+

+#define MM_TOP_DDR 0x0

+#define MM_TOP_DDR_SIZE 0x80000000U

+#define MM_TOP_DDR_2 0x800000000ULL

+#define MM_TOP_DDR_2_SIZE 0x800000000ULL

+#define MM_TOP_DDR_3 0xc000000000ULL

+#define MM_TOP_DDR_3_SIZE 0x4000000000ULL

+#define MM_TOP_DDR_4 0x10000000000ULL

+#define MM_TOP_DDR_4_SIZE 0xb780000000ULL

+

+#define MM_PSM_START 0xffc80000U

+#define MM_PSM_END 0xffcf0000U

+

+#define MM_CRL 0xff5e0000U

+#define MM_CRL_SIZE 0x300000

+#define MM_IOU_SCNTR 0xff130000U

+#define MM_IOU_SCNTR_SIZE 0x10000

+#define MM_IOU_SCNTRS 0xff140000U

+#define MM_IOU_SCNTRS_SIZE 0x10000

+#define MM_FPD_CRF 0xfd1a0000U

+#define MM_FPD_CRF_SIZE 0x140000

+#endif

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Xilinx Versal SoC model.

+ *

+ * Copyright (c) 2018 Xilinx Inc.

+ * Written by Edgar E. Iglesias

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu-common.h"

+#include "qemu/log.h"

+#include "hw/sysbus.h"

+#include "net/net.h"

+#include "sysemu/sysemu.h"

+#include "sysemu/kvm.h"

+#include "hw/arm/arm.h"

+#include "kvm_arm.h"

+#include "hw/misc/unimp.h"

+#include "hw/intc/arm_gicv3_common.h"

+#include "hw/arm/xlnx-versal.h"

+

+#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")

+#define GEM_REVISION 0x40070106

+

+static void versal_create_apu_cpus(Versal *s)

+{

+ int i;

+

+ for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {

+ Object *obj;

+ char *name;

+

+ obj = object_new(XLNX_VERSAL_ACPU_TYPE);

+ if (!obj) {

+ /* Secondary CPUs start in PSCI powered-down state */

+ error_report("Unable to create apu.cpu[%d] of type %s",

+ i, XLNX_VERSAL_ACPU_TYPE);

+ exit(EXIT_FAILURE);

+ }

+

+ name = g_strdup_printf("apu-cpu[%d]", i);

+ object_property_add_child(OBJECT(s), name, obj, &error_fatal);

+ g_free(name);

+

+ object_property_set_int(obj, s->cfg.psci_conduit,

+ "psci-conduit", &error_abort);

+ if (i) {

+ object_property_set_bool(obj, true,

+ "start-powered-off", &error_abort);

+ }

+

+ object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),

+ "core-count", &error_abort);

+ object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",

+ &error_abort);

+ object_property_set_bool(obj, true, "realized", &error_fatal);

+ s->fpd.apu.cpu[i] = ARM_CPU(obj);

+ }

+}

+

+static void versal_create_apu_gic(Versal *s, qemu_irq *pic)

+{

+ static const uint64_t addrs[] = {

+ MM_GIC_APU_DIST_MAIN,

+ MM_GIC_APU_REDIST_0

+ };

+ SysBusDevice *gicbusdev;

+ DeviceState *gicdev;

+ int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);

+ int i;

+

+ sysbus_init_child_obj(OBJECT(s), "apu-gic",

+ &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),

+ gicv3_class_name());

+ gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);

+ gicdev = DEVICE(&s->fpd.apu.gic);

+ qdev_prop_set_uint32(gicdev, "revision", 3);

+ qdev_prop_set_uint32(gicdev, "num-cpu", 2);

+ qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);

+ qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);

+ qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);

+ qdev_prop_set_bit(gicdev, "has-security-extensions", true);

+

+ object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",

+ &error_fatal);

+

+ for (i = 0; i < ARRAY_SIZE(addrs); i++) {

+ MemoryRegion *mr;

+

+ mr = sysbus_mmio_get_region(gicbusdev, i);

+ memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);

+ }

+

+ for (i = 0; i < nr_apu_cpus; i++) {

+ DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);

+ int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;

+ qemu_irq maint_irq;

+ int ti;

+ /* Mapping from the output timer irq lines from the CPU to the

+ * GIC PPI inputs.

+ */

+ const int timer_irq[] = {

+ [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,

+ [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,

+ [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ,

+ [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ,

+ };

+

+ for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {

+ qdev_connect_gpio_out(cpudev, ti,

+ qdev_get_gpio_in(gicdev,

+ ppibase + timer_irq[ti]));

+ }

+ maint_irq = qdev_get_gpio_in(gicdev,

+ ppibase + VERSAL_GIC_MAINT_IRQ);

+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",

+ 0, maint_irq);

+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));

+ sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,

+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));

+ sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,

+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));

+ sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,

+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));

+ }

+

+ for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {

+ pic[i] = qdev_get_gpio_in(gicdev, i);

+ }

+}

+

+static void versal_create_uarts(Versal *s, qemu_irq *pic)

+{

+ int i;

+

+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {

+ static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};

+ static const uint64_t addrs[] = { MM_UART0, MM_UART1 };

+ char *name = g_strdup_printf("uart%d", i);

+ DeviceState *dev;

+ MemoryRegion *mr;

+

+ dev = qdev_create(NULL, "pl011");

+ s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);

+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));