The following changes since commit b7c359c748a2e3ccb97a184b9739feb2cd48de2f:

Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-01-23 14:38:43 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200123

for you to fetch changes up to 53c75ad8e72dc3a5102de7ed21e4990969cb0a19:

hw/arm/exynos4210: Connect serial port DMA busy signals with pl330 (2020-01-23 15:22:42 +0000)

* fix bug in PAuth emulation

* add PMU to Cortex-R5, Cortex-R5F

* qemu-nbd: Convert documentation to rST

* qemu-block-drivers: Convert documentation to rST

* Fix Exynos4210 UART DMA support

* Various minor code cleanups

Andrew Jones (1):

target/arm/arch_dump: Add SVE notes

Clement Deschamps (1):

target/arm: add PMU feature to cortex-r5 and cortex-r5f

Guenter Roeck (8):

dma/pl330: Convert to support tracing

hw/core/or-irq: Increase limit of or-lines to 48

hw/arm/exynos4210: Fix DMA initialization

hw/char/exynos4210_uart: Convert to support tracing

hw/char/exynos4210_uart: Implement post_load function

hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts

hw/char/exynos4210_uart: Add receive DMA support

hw/arm/exynos4210: Connect serial port DMA busy signals with pl330

Keqian Zhu (2):

hw/acpi: Remove extra indent in ACPI GED hotplug cb

hw/arm: Use helper function to trigger hotplug handler plug

Peter Maydell (3):

qemu-nbd: Convert invocation documentation to rST

docs: Create stub system manual

qemu-block-drivers: Convert to rST

Philippe Mathieu-Daudé (1):

hw/misc/stm32f4xx_syscfg: Fix copy/paste error

Richard Henderson (3):

tests/tcg/aarch64: Fix compilation parameters for pauth-%

tests/tcg/aarch64: Add pauth-3

tests/tcg/aarch64: Add pauth-4

Vincent Dehors (1):

target/arm: Fix PAuth sbox functions

Makefile | 37 +-

tests/tcg/aarch64/Makefile.softmmu-target | 5 +-

tests/tcg/aarch64/Makefile.target | 3 +-

include/elf.h | 1 +

include/hw/arm/exynos4210.h | 4 +

include/hw/or-irq.h | 2 +-

target/arm/cpu.h | 25 +

hw/acpi/generic_event_device.c | 2 +-

hw/arm/exynos4210.c | 77 ++-

hw/arm/virt.c | 6 +-

hw/char/exynos4210_uart.c | 245 +++++---

hw/dma/pl330.c | 88 +--

hw/misc/stm32f4xx_syscfg.c | 2 +-

target/arm/arch_dump.c | 124 +++-

target/arm/cpu.c | 1 +

target/arm/kvm64.c | 24 -

target/arm/pauth_helper.c | 4 +-

tests/tcg/aarch64/pauth-1.c | 2 -

tests/tcg/aarch64/pauth-2.c | 2 -

tests/tcg/aarch64/pauth-4.c | 25 +

tests/tcg/aarch64/system/pauth-3.c | 40 ++

MAINTAINERS | 1 +

docs/index.html.in | 1 +

docs/interop/conf.py | 4 +-

docs/interop/index.rst | 1 +

docs/interop/qemu-nbd.rst | 263 ++++++++

docs/interop/qemu-option-trace.rst.inc | 30 +

docs/qemu-block-drivers.texi | 889 ---------------------------

docs/system/conf.py | 22 +

docs/system/index.rst | 17 +

docs/system/qemu-block-drivers.rst | 985 ++++++++++++++++++++++++++++++

hw/char/trace-events | 20 +

hw/dma/trace-events | 24 +

qemu-doc.texi | 18 -

qemu-nbd.texi | 214 -------

qemu-option-trace.texi | 4 +

qemu-options.hx | 2 +-

37 files changed, 1897 insertions(+), 1317 deletions(-)

create mode 100644 tests/tcg/aarch64/pauth-4.c

create mode 100644 tests/tcg/aarch64/system/pauth-3.c

create mode 100644 docs/interop/qemu-nbd.rst

create mode 100644 docs/interop/qemu-option-trace.rst.inc

delete mode 100644 docs/qemu-block-drivers.texi

create mode 100644 docs/system/conf.py

create mode 100644 docs/system/index.rst

create mode 100644 docs/system/qemu-block-drivers.rst

delete mode 100644 qemu-nbd.texi

From: Guenter Roeck <linux@roeck-us.net>

The Exynos4210 serial driver uses an interrupt line to signal if receive

data is available. Connect that interrupt with the DMA controller's

'peripheral busy' gpio pin to stop the DMA if there is no more receive

data available. Without this patch, receive DMA runs wild and fills the

entire receive DMA buffer with invalid data.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Message-id: 20200123052540.6132-9-linux@roeck-us.net

hw/arm/exynos4210.c | 42 +++++++++++++++++++++++++++++-------------

1 file changed, 29 insertions(+), 13 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c

--- a/hw/arm/exynos4210.c

+++ b/hw/arm/exynos4210.c

@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)

return (0x9 << ARM_AFF1_SHIFT) | cpu;

}

-static void pl330_create(uint32_t base, qemu_or_irq *orgate, qemu_irq irq,

- int nreq, int nevents, int width)

+static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,

+ qemu_irq irq, int nreq, int nevents, int width)

{

SysBusDevice *busdev;

DeviceState *dev;

@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_or_irq *orgate, qemu_irq irq,

sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));

}

qdev_connect_gpio_out(DEVICE(orgate), 0, irq);

+ return dev;

}

static void exynos4210_realize(DeviceState *socdev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)

MemoryRegion *system_mem = get_system_memory();

qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];

SysBusDevice *busdev;

- DeviceState *dev;

+ DeviceState *dev, *uart[4], *pl330[3];

int i, n;

for (n = 0; n < EXYNOS4210_NCPUS; n++) {

@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)

/*** UARTs ***/

- exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,

+ uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,

EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),

s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);

- exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,

+ uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,

EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),

s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);

- exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,

+ uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,

EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),

s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);

- exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,

+ uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,

EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),

s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);

@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)

s->irq_table[exynos4210_get_irq(28, 3)]);

/*** DMA controllers ***/

- pl330_create(EXYNOS4210_PL330_BASE0_ADDR, &s->pl330_irq_orgate[0],

- s->irq_table[exynos4210_get_irq(21, 0)], 32, 32, 32);

- pl330_create(EXYNOS4210_PL330_BASE1_ADDR, &s->pl330_irq_orgate[1],

- s->irq_table[exynos4210_get_irq(21, 1)], 32, 32, 32);

- pl330_create(EXYNOS4210_PL330_BASE2_ADDR, &s->pl330_irq_orgate[2],

- s->irq_table[exynos4210_get_irq(20, 1)], 1, 31, 64);

+ pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR,

+ &s->pl330_irq_orgate[0],

+ s->irq_table[exynos4210_get_irq(21, 0)],

+ 32, 32, 32);

+ pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR,

+ &s->pl330_irq_orgate[1],

+ s->irq_table[exynos4210_get_irq(21, 1)],

+ 32, 32, 32);

+ pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR,

+ &s->pl330_irq_orgate[2],

+ s->irq_table[exynos4210_get_irq(20, 1)],

+ 1, 31, 64);

+

+ sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1,

+ qdev_get_gpio_in(pl330[0], 15));

+ sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1,

+ qdev_get_gpio_in(pl330[1], 15));

+ sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1,

+ qdev_get_gpio_in(pl330[0], 17));

+ sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1,

+ qdev_get_gpio_in(pl330[1], 17));

}

static void exynos4210_init(Object *obj)

2.20.1

From: Guenter Roeck <linux@roeck-us.net>

The driver already implements a receive FIFO, but it does not

handle receive FIFO trigger levels and timeout. Implement the

missing functionality.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Message-id: 20200123052540.6132-7-linux@roeck-us.net

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/char/exynos4210_uart.c | 117 ++++++++++++++++++++++++++++++--------

hw/char/trace-events | 3 +-

2 files changed, 94 insertions(+), 26 deletions(-)

diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c

--- a/hw/char/exynos4210_uart.c

+++ b/hw/char/exynos4210_uart.c

@@ -XXX,XX +XXX,XX @@

#include "migration/vmstate.h"

#include "qemu/error-report.h"

#include "qemu/module.h"

+#include "qemu/timer.h"

#include "chardev/char-fe.h"

#include "chardev/char-serial.h"

@@ -XXX,XX +XXX,XX @@ static const Exynos4210UartReg exynos4210_uart_regs[] = {

#define ULCON_STOP_BIT_SHIFT 1

/* UART Tx/Rx Status */

+#define UTRSTAT_Rx_TIMEOUT 0x8

#define UTRSTAT_TRANSMITTER_EMPTY 0x4

#define UTRSTAT_Tx_BUFFER_EMPTY 0x2

#define UTRSTAT_Rx_BUFFER_DATA_READY 0x1

@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartState {

Exynos4210UartFIFO rx;

Exynos4210UartFIFO tx;

+ QEMUTimer *fifo_timeout_timer;

+ uint64_t wordtime; /* word time in ns */

+

CharBackend chr;

qemu_irq irq;

@@ -XXX,XX +XXX,XX @@ static void fifo_reset(Exynos4210UartFIFO *q)

q->rp = 0;

-static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)

+static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel,

+ uint32_t reg)

{

- uint32_t level = 0;

- uint32_t reg;

+ uint32_t level;

- reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>

- UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;

-

- switch (s->channel) {

+ switch (channel) {

case 0:

level = reg * 32;

break;

@@ -XXX,XX +XXX,XX @@ static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState

break;

default:

level = 0;

- trace_exynos_uart_channel_error(s->channel);

+ trace_exynos_uart_channel_error(channel);

+ break;

}

-

return level;

}

+static uint32_t

+exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)

+ uint32_t reg;

+

+ reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>

+ UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;

+

+ return exynos4210_uart_FIFO_trigger_level(s->channel, reg);

+static uint32_t

+exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s)

+{

+ uint32_t reg;

+

+ reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >>

+ UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1;

+

+ return exynos4210_uart_FIFO_trigger_level(s->channel, reg);

+}

+

static void exynos4210_uart_update_irq(Exynos4210UartState *s)

/*

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_update_irq(Exynos4210UartState *s)

* transmit FIFO is smaller than the trigger level.

*/

if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {

-

uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>

UFSTAT_Tx_FIFO_COUNT_SHIFT;

if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {

s->reg[I_(UINTSP)] |= UINTSP_TXD;

}

+

+ /*

+ * Rx interrupt if trigger level is reached or if rx timeout

+ * interrupt is disabled and there is data in the receive buffer

+ */

+ count = fifo_elements_number(&s->rx);

+ if ((count && !(s->reg[I_(UCON)] & 0x80)) ||

+ count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) {

+ s->reg[I_(UINTSP)] |= UINTSP_RXD;

+ timer_del(s->fifo_timeout_timer);

+ }

+ } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) {

+ s->reg[I_(UINTSP)] |= UINTSP_RXD;

}

s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_update_irq(Exynos4210UartState *s)

}

}

+static void exynos4210_uart_timeout_int(void *opaque)

+{

+ Exynos4210UartState *s = opaque;

+

+ trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)],

+ s->reg[I_(UINTSP)]);

+

+ if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) ||

+ (s->reg[I_(UCON)] & (1 << 11))) {

+ s->reg[I_(UINTSP)] |= UINTSP_RXD;

+ s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT;

+ exynos4210_uart_update_irq(s);

+ }

+}

+

static void exynos4210_uart_update_parameters(Exynos4210UartState *s)

{

int speed, parity, data_bits, stop_bits;

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s)

ssp.data_bits = data_bits;

ssp.stop_bits = stop_bits;

+ s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed;

+

qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

trace_exynos_uart_update_params(

- s->channel, speed, parity, data_bits, stop_bits);

+ s->channel, speed, parity, data_bits, stop_bits, s->wordtime);

+}

+

+static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s)

+{

+ if (s->reg[I_(UCON)] & 0x80) {

+ uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime;

+

+ timer_mod(s->fifo_timeout_timer,

+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);

+ } else {

+ timer_del(s->fifo_timeout_timer);

+ }

}

static void exynos4210_uart_write(void *opaque, hwaddr offset,

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_write(void *opaque, hwaddr offset,

exynos4210_uart_update_irq(s);

break;

case UTRSTAT:

+ if (val & UTRSTAT_Rx_TIMEOUT) {

+ s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT;

+ }

+ break;

case UERSTAT:

case UFSTAT:

case UMSTAT:

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_write(void *opaque, hwaddr offset,

break;

}

static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,

unsigned size)

{

@@ -XXX,XX +XXX,XX @@ static int exynos4210_uart_can_receive(void *opaque)

return fifo_empty_elements_number(&s->rx);

}

-

static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)

{

Exynos4210UartState *s = (Exynos4210UartState *)opaque;

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)

if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {

if (fifo_empty_elements_number(&s->rx) < size) {

- for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {

- fifo_store(&s->rx, buf[i]);

- }

+ size = fifo_empty_elements_number(&s->rx);

s->reg[I_(UINTSP)] |= UINTSP_ERROR;

- s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;

- } else {

- for (i = 0; i < size; i++) {

- fifo_store(&s->rx, buf[i]);

- }

- s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;

}

- /* XXX: Around here we maybe should check Rx trigger level */

- s->reg[I_(UINTSP)] |= UINTSP_RXD;

+ for (i = 0; i < size; i++) {

+ fifo_store(&s->rx, buf[i]);

+ }

+ exynos4210_uart_rx_timeout_set(s);

} else {

s->reg[I_(URXH)] = buf[0];

- s->reg[I_(UINTSP)] |= UINTSP_RXD;

- s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;

}

+ s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;

exynos4210_uart_update_irq(s);

}

@@ -XXX,XX +XXX,XX @@ static int exynos4210_uart_post_load(void *opaque, int version_id)

Exynos4210UartState *s = (Exynos4210UartState *)opaque;

exynos4210_uart_update_parameters(s);

+ exynos4210_uart_rx_timeout_set(s);

return 0;

}

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_init(Object *obj)

SysBusDevice *dev = SYS_BUS_DEVICE(obj);

Exynos4210UartState *s = EXYNOS4210_UART(dev);

+ s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,

+ exynos4210_uart_timeout_int, s);

+ s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600;

+

/* memory mapping */

memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,

"exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);

diff --git a/hw/char/trace-events b/hw/char/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/char/trace-events

+++ b/hw/char/trace-events

@@ -XXX,XX +XXX,XX @@ nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PR

# exynos4210_uart.c

exynos_uart_irq_raised(uint32_t channel, uint32_t reg) "UART%d: IRQ raised: 0x%08"PRIx32

exynos_uart_irq_lowered(uint32_t channel) "UART%d: IRQ lowered"

-exynos_uart_update_params(uint32_t channel, int speed, uint8_t parity, int data, int stop) "UART%d: speed: %d, parity: %c, data bits: %d, stop bits: %d"

+exynos_uart_update_params(uint32_t channel, int speed, uint8_t parity, int data, int stop, uint64_t wordtime) "UART%d: speed: %d, parity: %c, data bits: %d, stop bits: %d wordtime: %"PRId64"ns"

exynos_uart_write(uint32_t channel, uint32_t offset, const char *name, uint64_t val) "UART%d: <0x%04x> %s <- 0x%" PRIx64

exynos_uart_read(uint32_t channel, uint32_t offset, const char *name, uint64_t val) "UART%d: <0x%04x> %s -> 0x%" PRIx64

exynos_uart_rx_fifo_reset(uint32_t channel) "UART%d: Rx FIFO Reset"

@@ -XXX,XX +XXX,XX @@ exynos_uart_rx_error(uint32_t channel) "UART%d: Rx error"

exynos_uart_wo_read(uint32_t channel, const char *name, uint32_t reg) "UART%d: Trying to read from WO register: %s [0x%04"PRIx32"]"

exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d"

exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d"

+exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: Rx timeout stat=0x%x intsp=0x%x"

2.20.1

From: Andrew Jones <drjones@redhat.com>

When dumping a guest with dump-guest-memory also dump the SVE

registers if they are in use.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Message-id: 20200120101832.18781-1-drjones@redhat.com

[PMM: fixed checkpatch nits]

include/elf.h | 1 +

target/arm/cpu.h | 25 +++++++++

target/arm/arch_dump.c | 124 ++++++++++++++++++++++++++++++++++++++++-

target/arm/kvm64.c | 24 --------

4 files changed, 148 insertions(+), 26 deletions(-)

diff --git a/include/elf.h b/include/elf.h

--- a/include/elf.h

+++ b/include/elf.h

@@ -XXX,XX +XXX,XX @@ typedef struct elf64_shdr {

#define NT_ARM_HW_BREAK 0x402 /* ARM hardware breakpoint registers */

#define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */

#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */

+#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */

/*

* Physical entry point into the kernel.

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);

void aarch64_sve_change_el(CPUARMState *env, int old_el,

int new_el, bool el0_a64);

void aarch64_add_sve_properties(Object *obj);

+/*

+ * SVE registers are encoded in KVM's memory in an endianness-invariant format.

+ * The byte at offset i from the start of the in-memory representation contains

+ * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the

+ * lowest offsets are stored in the lowest memory addresses, then that nearly

+ * matches QEMU's representation, which is to use an array of host-endian

+ * uint64_t's, where the lower offsets are at the lower indices. To complete

+ * the translation we just need to byte swap the uint64_t's on big-endian hosts.

+ */

+static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)

+{

+#ifdef HOST_WORDS_BIGENDIAN

+ int i;

+

+ for (i = 0; i < nr; ++i) {

+ dst[i] = bswap64(src[i]);

+ return dst;

+#else

+ return src;

+#endif

#else

static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }

static inline void aarch64_sve_change_el(CPUARMState *env, int o,

diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/arch_dump.c

+++ b/target/arm/arch_dump.c

@@ -XXX,XX +XXX,XX @@ struct aarch64_user_vfp_state {

QEMU_BUILD_BUG_ON(sizeof(struct aarch64_user_vfp_state) != 528);

+/* struct user_sve_header from arch/arm64/include/uapi/asm/ptrace.h */

+struct aarch64_user_sve_header {

+ uint32_t size;

+ uint32_t max_size;

+ uint16_t vl;

+ uint16_t max_vl;

+ uint16_t flags;

+ uint16_t reserved;

+} QEMU_PACKED;

struct aarch64_note {

Elf64_Nhdr hdr;

char name[8]; /* align_up(sizeof("CORE"), 4) */

union {

struct aarch64_elf_prstatus prstatus;

struct aarch64_user_vfp_state vfp;

+ struct aarch64_user_sve_header sve;

};

} QEMU_PACKED;

@@ -XXX,XX +XXX,XX @@ struct aarch64_note {

(AARCH64_NOTE_HEADER_SIZE + sizeof(struct aarch64_elf_prstatus))

#define AARCH64_PRFPREG_NOTE_SIZE \

(AARCH64_NOTE_HEADER_SIZE + sizeof(struct aarch64_user_vfp_state))

+#define AARCH64_SVE_NOTE_SIZE(env) \

+ (AARCH64_NOTE_HEADER_SIZE + sve_size(env))

static void aarch64_note_init(struct aarch64_note *note, DumpState *s,

const char *name, Elf64_Word namesz,

@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,

return 0;

}

+#ifdef TARGET_AARCH64

+static off_t sve_zreg_offset(uint32_t vq, int n)

+{

+ off_t off = sizeof(struct aarch64_user_sve_header);

+ return ROUND_UP(off, 16) + vq * 16 * n;

+static off_t sve_preg_offset(uint32_t vq, int n)

+ return sve_zreg_offset(vq, 32) + vq * 16 / 8 * n;

+static off_t sve_fpsr_offset(uint32_t vq)

+{

+ off_t off = sve_preg_offset(vq, 17);

+ return ROUND_UP(off, 16);

+}

+

+static off_t sve_fpcr_offset(uint32_t vq)

+{

+ return sve_fpsr_offset(vq) + sizeof(uint32_t);

+}

+

+static uint32_t sve_current_vq(CPUARMState *env)

+{

+ return sve_zcr_len_for_el(env, arm_current_el(env)) + 1;

+}

+

+static size_t sve_size_vq(uint32_t vq)

+{

+ off_t off = sve_fpcr_offset(vq) + sizeof(uint32_t);

+ return ROUND_UP(off, 16);

+}

+

+static size_t sve_size(CPUARMState *env)

+{

+ return sve_size_vq(sve_current_vq(env));

+}

+

+static int aarch64_write_elf64_sve(WriteCoreDumpFunction f,

+ CPUARMState *env, int cpuid,

+ DumpState *s)

+{

+ struct aarch64_note *note;

+ ARMCPU *cpu = env_archcpu(env);

+ uint32_t vq = sve_current_vq(env);

+ uint64_t tmp[ARM_MAX_VQ * 2], *r;

+ uint32_t fpr;

+ uint8_t *buf;

+ int ret, i;

+

+ note = g_malloc0(AARCH64_SVE_NOTE_SIZE(env));

+ buf = (uint8_t *)&note->sve;

+

+ aarch64_note_init(note, s, "LINUX", 6, NT_ARM_SVE, sve_size_vq(vq));

+

+ note->sve.size = cpu_to_dump32(s, sve_size_vq(vq));

+ note->sve.max_size = cpu_to_dump32(s, sve_size_vq(cpu->sve_max_vq));

+ note->sve.vl = cpu_to_dump16(s, vq * 16);

+ note->sve.max_vl = cpu_to_dump16(s, cpu->sve_max_vq * 16);

+ note->sve.flags = cpu_to_dump16(s, 1);

+

+ for (i = 0; i < 32; ++i) {

+ r = sve_bswap64(tmp, &env->vfp.zregs[i].d[0], vq * 2);

+ memcpy(&buf[sve_zreg_offset(vq, i)], r, vq * 16);

+ }

+

+ for (i = 0; i < 17; ++i) {

+ r = sve_bswap64(tmp, r = &env->vfp.pregs[i].p[0],

+ DIV_ROUND_UP(vq * 2, 8));

+ memcpy(&buf[sve_preg_offset(vq, i)], r, vq * 16 / 8);

+ }

+

+ fpr = cpu_to_dump32(s, vfp_get_fpsr(env));

+ memcpy(&buf[sve_fpsr_offset(vq)], &fpr, sizeof(uint32_t));

+

+ fpr = cpu_to_dump32(s, vfp_get_fpcr(env));

+ memcpy(&buf[sve_fpcr_offset(vq)], &fpr, sizeof(uint32_t));

+

+ ret = f(note, AARCH64_SVE_NOTE_SIZE(env), s);

+ g_free(note);

+

+ if (ret < 0) {

+ return -1;

+ }

+

+ return 0;

+}

+#endif

+

int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,

int cpuid, void *opaque)

{

struct aarch64_note note;

- CPUARMState *env = &ARM_CPU(cs)->env;

+ ARMCPU *cpu = ARM_CPU(cs);

+ CPUARMState *env = &cpu->env;

DumpState *s = opaque;

uint64_t pstate, sp;

int ret, i;

@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,

return -1;

}

- return aarch64_write_elf64_prfpreg(f, env, cpuid, s);

+ ret = aarch64_write_elf64_prfpreg(f, env, cpuid, s);

+ if (ret) {

+ return ret;

+ }

+

+#ifdef TARGET_AARCH64

+ if (cpu_isar_feature(aa64_sve, cpu)) {

+ ret = aarch64_write_elf64_sve(f, env, cpuid, s);

+ }

+#endif

+

+ return ret;

/* struct pt_regs from arch/arm/include/asm/ptrace.h */

@@ -XXX,XX +XXX,XX @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)

if (class == ELFCLASS64) {

note_size = AARCH64_PRSTATUS_NOTE_SIZE;

note_size += AARCH64_PRFPREG_NOTE_SIZE;

+#ifdef TARGET_AARCH64

+ if (cpu_isar_feature(aa64_sve, cpu)) {

+ note_size += AARCH64_SVE_NOTE_SIZE(env);

+ }

+#endif

} else {

note_size = ARM_PRSTATUS_NOTE_SIZE;

if (arm_feature(env, ARM_FEATURE_VFP)) {

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm64.c

+++ b/target/arm/kvm64.c

@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_fpsimd(CPUState *cs)

return 0;

}

-/*

- * SVE registers are encoded in KVM's memory in an endianness-invariant format.

- * The byte at offset i from the start of the in-memory representation contains

- * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the

- * lowest offsets are stored in the lowest memory addresses, then that nearly

- * matches QEMU's representation, which is to use an array of host-endian

- * uint64_t's, where the lower offsets are at the lower indices. To complete

- * the translation we just need to byte swap the uint64_t's on big-endian hosts.

- */

-static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)

-#ifdef HOST_WORDS_BIGENDIAN

- int i;

- for (i = 0; i < nr; ++i) {

- dst[i] = bswap64(src[i]);

- return dst;

-#else

- return src;

-#endif

/*

* KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits

* and PREGS and the FFR have a slice size of 256 bits. However we simply hard

2.20.1

From: Guenter Roeck <linux@roeck-us.net>

To support receive DMA, we need to inform the DMA controller if receive data

is available. Otherwise the DMA controller keeps requesting data, causing

receive errors.

Implement this using an interrupt line. The instantiating code then needs

to connect the interrupt with the matching DMA controller GPIO pin.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Message-id: 20200123052540.6132-8-linux@roeck-us.net

hw/char/exynos4210_uart.c | 24 ++++++++++++++++++++++++

hw/char/trace-events | 2 ++

2 files changed, 26 insertions(+)

diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c

--- a/hw/char/exynos4210_uart.c

+++ b/hw/char/exynos4210_uart.c

@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartState {

CharBackend chr;

qemu_irq irq;

+ qemu_irq dmairq;

uint32_t channel;

@@ -XXX,XX +XXX,XX @@ exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s)

return exynos4210_uart_FIFO_trigger_level(s->channel, reg);

}

+/*

+ * Update Rx DMA busy signal if Rx DMA is enabled. For simplicity,

+ * mark DMA as busy if DMA is enabled and the receive buffer is empty.

+ */

+static void exynos4210_uart_update_dmabusy(Exynos4210UartState *s)

+{

+ bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02;

+ uint32_t count = fifo_elements_number(&s->rx);

+

+ if (rx_dma_enabled && !count) {

+ qemu_irq_raise(s->dmairq);

+ trace_exynos_uart_dmabusy(s->channel);

+ } else {

+ qemu_irq_lower(s->dmairq);

+ trace_exynos_uart_dmaready(s->channel);

+ }

+}

+

static void exynos4210_uart_update_irq(Exynos4210UartState *s)

{

/*

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_update_irq(Exynos4210UartState *s)

count = fifo_elements_number(&s->rx);

if ((count && !(s->reg[I_(UCON)] & 0x80)) ||

count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) {

+ exynos4210_uart_update_dmabusy(s);

s->reg[I_(UINTSP)] |= UINTSP_RXD;

timer_del(s->fifo_timeout_timer);

}

} else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) {

+ exynos4210_uart_update_dmabusy(s);

s->reg[I_(UINTSP)] |= UINTSP_RXD;

}

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_timeout_int(void *opaque)

(s->reg[I_(UCON)] & (1 << 11))) {

s->reg[I_(UINTSP)] |= UINTSP_RXD;

s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT;

+ exynos4210_uart_update_dmabusy(s);

exynos4210_uart_update_irq(s);

@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,

s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;

res = s->reg[I_(URXH)];

}

+ exynos4210_uart_update_dmabusy(s);

trace_exynos_uart_read(s->channel, offset,

exynos4210_uart_regname(offset), res);

return res;

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_init(Object *obj)

sysbus_init_mmio(dev, &s->iomem);

sysbus_init_irq(dev, &s->irq);

+ sysbus_init_irq(dev, &s->dmairq);

static void exynos4210_uart_realize(DeviceState *dev, Error **errp)

diff --git a/hw/char/trace-events b/hw/char/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/char/trace-events

+++ b/hw/char/trace-events

@@ -XXX,XX +XXX,XX @@ nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64

nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"

# exynos4210_uart.c

+exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"

+exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"

exynos_uart_irq_raised(uint32_t channel, uint32_t reg) "UART%d: IRQ raised: 0x%08"PRIx32

exynos_uart_irq_lowered(uint32_t channel) "UART%d: IRQ lowered"

exynos_uart_update_params(uint32_t channel, int speed, uint8_t parity, int data, int stop, uint64_t wordtime) "UART%d: speed: %d, parity: %c, data bits: %d, stop bits: %d wordtime: %"PRId64"ns"

2.20.1

From: Guenter Roeck <linux@roeck-us.net>

After restoring a VM, serial parameters need to be updated to reflect

restored register values. Implement a post_load function to handle this

situation.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Message-id: 20200123052540.6132-6-linux@roeck-us.net

hw/char/exynos4210_uart.c | 10 ++++++++++

1 file changed, 10 insertions(+)

diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c

--- a/hw/char/exynos4210_uart.c

+++ b/hw/char/exynos4210_uart.c

@@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_reset(DeviceState *dev)

trace_exynos_uart_rxsize(s->channel, s->rx.size);

+static int exynos4210_uart_post_load(void *opaque, int version_id)

+{

+ Exynos4210UartState *s = (Exynos4210UartState *)opaque;

+

+ exynos4210_uart_update_parameters(s);

+

+ return 0;

+}

+

static const VMStateDescription vmstate_exynos4210_uart_fifo = {

.name = "exynos4210.uart.fifo",

.version_id = 1,

.minimum_version_id = 1,

+ .post_load = exynos4210_uart_post_load,

.fields = (VMStateField[]) {

VMSTATE_UINT32(sp, Exynos4210UartFIFO),

VMSTATE_UINT32(rp, Exynos4210UartFIFO),

2.20.1

The qemu-block-drivers documentation is currently in

docs/qemu-block-drivers.texi in Texinfo format, which we present

to the user as:

* a qemu-block-drivers manpage

* a section of the main qemu-doc HTML documentation

Convert the documentation to rST format, and present it to

the user as:

* a qemu-block-drivers manpage

* part of the system/ Sphinx manual

This follows the same pattern we've done for qemu-ga and qemu-nbd.

We have to drop a cross-reference from the documentation of the

-cdrom option back to the qemu-block-drivers documentation, since

they're no longer within the same texinfo document.

As noted in a comment, the manpage output is slightly compromised

due to limitations in Sphinx. In an ideal world, the HTML output

would have the various headings like 'Disk image file formats'

as top-level section headings (which then appear in the overall

system manual's table-of-contents), and it would not have the

section headings which make sense only for the manpage like

'synopsis', 'description', and 'see also'. Unfortunately, the

mechanism Sphinx provides for restricting pieces of documentation

is limited to the point of being flawed: the 'only::' directive

is implemented as a filter that is applied at a very late stage

in the document processing pipeline, rather than as an early

equivalent of an #ifdef. This means that Sphinx's process of

identifying which section heading markup styles are which levels

of heading gets confused if the 'only::' directive contains

section headings which would affect the heading-level of a

later heading. I have opted to prioritise making the HTML format

look better, with the compromise being that in the manpage

the 'Disk image file formats' &c headings are top-level headings

rather than being sub-headings under the traditional 'Description'

top-level section title.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Acked-by: Stefan Hajnoczi <stefanha@redhat.com>

Message-id: 20200116141511.16849-4-peter.maydell@linaro.org

---

Makefile | 11 +-

docs/qemu-block-drivers.texi | 889 --------------------------

docs/system/conf.py | 7 +

docs/system/index.rst | 1 +

docs/system/qemu-block-drivers.rst | 985 +++++++++++++++++++++++++++++

qemu-doc.texi | 12 -

qemu-options.hx | 2 +-

7 files changed, 1000 insertions(+), 907 deletions(-)

delete mode 100644 docs/qemu-block-drivers.texi

create mode 100644 docs/system/qemu-block-drivers.rst

diff --git a/Makefile b/Makefile

--- a/Makefile

+++ b/Makefile

@@ -XXX,XX +XXX,XX @@ ifdef BUILD_DOCS

DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1

DOCS+=$(MANUAL_BUILDDIR)/interop/qemu-nbd.8

DOCS+=$(MANUAL_BUILDDIR)/interop/qemu-ga.8

+DOCS+=$(MANUAL_BUILDDIR)/system/qemu-block-drivers.7

DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7

DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7

-DOCS+=docs/qemu-block-drivers.7

DOCS+=docs/qemu-cpu-models.7

DOCS+=$(MANUAL_BUILDDIR)/index.html

ifdef CONFIG_VIRTFS

@@ -XXX,XX +XXX,XX @@ distclean: clean

    rm -f docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt

    rm -f docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf

    rm -f docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html

-    rm -f docs/qemu-block-drivers.7

    rm -f docs/qemu-cpu-models.7

    rm -rf .doctrees

    $(call clean-manual,devel)

@@ -XXX,XX +XXX,XX @@ ifdef CONFIG_POSIX

    $(INSTALL_DATA) qemu.1 "$(DESTDIR)$(mandir)/man1"

    $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man7"

    $(INSTALL_DATA) docs/interop/qemu-qmp-ref.7 "$(DESTDIR)$(mandir)/man7"

-    $(INSTALL_DATA) docs/qemu-block-drivers.7 "$(DESTDIR)$(mandir)/man7"

+    $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu-block-drivers.7 "$(DESTDIR)$(mandir)/man7"

    $(INSTALL_DATA) docs/qemu-cpu-models.7 "$(DESTDIR)$(mandir)/man7"

ifeq ($(CONFIG_TOOLS),y)

    $(INSTALL_DATA) qemu-img.1 "$(DESTDIR)$(mandir)/man1"

@@ -XXX,XX +XXX,XX @@ $(MANUAL_BUILDDIR)/interop/qemu-ga.8: $(call manual-deps,interop)

$(MANUAL_BUILDDIR)/interop/qemu-nbd.8: $(call manual-deps,interop)

    $(call build-manual,interop,man)

+$(MANUAL_BUILDDIR)/system/qemu-block-drivers.7: $(call manual-deps,system)

+    $(call build-manual,system,man)

+

$(MANUAL_BUILDDIR)/index.html: $(SRC_PATH)/docs/index.html.in qemu-version.h

    @mkdir -p "$(MANUAL_BUILDDIR)"

    $(call quiet-command, sed "s|@@VERSION@@|${VERSION}|g" $< >$@, \

@@ -XXX,XX +XXX,XX @@ qemu.1: qemu-doc.texi qemu-options.texi qemu-monitor.texi qemu-monitor-info.texi

qemu.1: qemu-option-trace.texi

qemu-img.1: qemu-img.texi qemu-option-trace.texi qemu-img-cmds.texi

fsdev/virtfs-proxy-helper.1: fsdev/virtfs-proxy-helper.texi

-docs/qemu-block-drivers.7: docs/qemu-block-drivers.texi

docs/qemu-cpu-models.7: docs/qemu-cpu-models.texi

scripts/qemu-trace-stap.1: scripts/qemu-trace-stap.texi

@@ -XXX,XX +XXX,XX @@ qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \

    qemu-img.texi qemu-options.texi \

    qemu-tech.texi qemu-option-trace.texi \

    qemu-deprecated.texi qemu-monitor.texi qemu-img-cmds.texi \

-    qemu-monitor-info.texi docs/qemu-block-drivers.texi \

+    qemu-monitor-info.texi \

    docs/qemu-cpu-models.texi docs/security.texi

docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \

diff --git a/docs/qemu-block-drivers.texi b/docs/qemu-block-drivers.texi

deleted file mode 100644

index XXXXXXX..XXXXXXX

--- a/docs/qemu-block-drivers.texi

+++ /dev/null

@@ -XXX,XX +XXX,XX @@

-@c man begin SYNOPSIS

-QEMU block driver reference manual

-@c man end

-@set qemu_system qemu-system-x86_64

-

-@c man begin DESCRIPTION

-

-@node disk_images_formats

-@subsection Disk image file formats

-

-QEMU supports many image file formats that can be used with VMs as well as with

-any of the tools (like @code{qemu-img}). This includes the preferred formats

-raw and qcow2 as well as formats that are supported for compatibility with

-older QEMU versions or other hypervisors.

-

-Depending on the image format, different options can be passed to

-@code{qemu-img create} and @code{qemu-img convert} using the @code{-o} option.

-This section describes each format and the options that are supported for it.

-

-@table @option

-@item raw

-

-Raw disk image format. This format has the advantage of

-being simple and easily exportable to all other emulators. If your

-file system supports @emph{holes} (for example in ext2 or ext3 on

-Linux or NTFS on Windows), then only the written sectors will reserve

-space. Use @code{qemu-img info} to know the real size used by the

-image or @code{ls -ls} on Unix/Linux.

-

-Supported options:

-@table @code

-@item preallocation

-Preallocation mode (allowed values: @code{off}, @code{falloc}, @code{full}).

-@code{falloc} mode preallocates space for image by calling posix_fallocate().

-@code{full} mode preallocates space for image by writing data to underlying

-storage. This data may or may not be zero, depending on the storage location.

-@end table

-

-@item qcow2

-QEMU image format, the most versatile format. Use it to have smaller

-images (useful if your filesystem does not supports holes, for example

-on Windows), zlib based compression and support of multiple VM

-snapshots.

-

-Supported options:

-@table @code

-@item compat

-Determines the qcow2 version to use. @code{compat=0.10} uses the

-traditional image format that can be read by any QEMU since 0.10.

-@code{compat=1.1} enables image format extensions that only QEMU 1.1 and

-newer understand (this is the default). Amongst others, this includes

-zero clusters, which allow efficient copy-on-read for sparse images.

-

-@item backing_file

-File name of a base image (see @option{create} subcommand)

-@item backing_fmt

-Image format of the base image

-@item encryption

-This option is deprecated and equivalent to @code{encrypt.format=aes}

-

-@item encrypt.format

-

-If this is set to @code{luks}, it requests that the qcow2 payload (not

-qcow2 header) be encrypted using the LUKS format. The passphrase to

-use to unlock the LUKS key slot is given by the @code{encrypt.key-secret}

-parameter. LUKS encryption parameters can be tuned with the other

-@code{encrypt.*} parameters.

-

-If this is set to @code{aes}, the image is encrypted with 128-bit AES-CBC.

-The encryption key is given by the @code{encrypt.key-secret} parameter.

-This encryption format is considered to be flawed by modern cryptography

-standards, suffering from a number of design problems:

-

-@itemize @minus

-@item The AES-CBC cipher is used with predictable initialization vectors based

-on the sector number. This makes it vulnerable to chosen plaintext attacks

-which can reveal the existence of encrypted data.

-@item The user passphrase is directly used as the encryption key. A poorly

-chosen or short passphrase will compromise the security of the encryption.

-@item In the event of the passphrase being compromised there is no way to

-change the passphrase to protect data in any qcow images. The files must

-be cloned, using a different encryption passphrase in the new file. The

-original file must then be securely erased using a program like shred,

-though even this is ineffective with many modern storage technologies.

-@end itemize

-

-The use of this is no longer supported in system emulators. Support only

-remains in the command line utilities, for the purposes of data liberation

-and interoperability with old versions of QEMU. The @code{luks} format

-should be used instead.

-

-@item encrypt.key-secret

-

-Provides the ID of a @code{secret} object that contains the passphrase

-(@code{encrypt.format=luks}) or encryption key (@code{encrypt.format=aes}).

-

-@item encrypt.cipher-alg

-