Series comparison

-[PULL 00/16] tcg patch queue
+[PULL 00/30] tcg patch queue
-The following changes since commit 3e08b2b9cb64bff2b73fa9128c0e49bfcde0dd40:
+The following changes since commit 36eae3a732a1f2aa81391e871ac0e9bb3233e7d7:
-  Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200121' into staging (2020-01-21 15:29:25 +0000)
+  Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-migration-20220302b' into staging (2022-03-02 20:55:48 +0000)
 are available in the Git repository at:
-  https://github.com/rth7680/qemu.git tags/pull-tcg-20200121
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220303
-for you to fetch changes up to 75fa376cdab5e5db2c7fdd107358e16f95503ac6:
+for you to fetch changes up to f23e6de25c31cadd9a3b7122f9384e6b259ce37f:
-  scripts/git.orderfile: Display decodetree before C source (2020-01-21 15:26:09 -1000)
+  tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 (2022-03-03 10:47:20 -1000)
 ----------------------------------------------------------------
-Remove another limit to NB_MMU_MODES.
+Reorder do_constant_folding_cond test to satisfy valgrind.
-Fix compilation using uclibc.
+Fix value of MAX_OPC_PARAM_IARGS.
-Fix defaulting of -accel parameters.
+Add opcodes for vector nand, nor, eqv.
-Tidy cputlb basic routines.
+Support vector nand, nor, eqv on PPC and S390X hosts.
-Adjust git.orderfile for decodetree.
+Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
 Support 32-bit guest addresses as signed values.
 ----------------------------------------------------------------
-Carlos Santos (1):
+Alex Bennée (1):
-      util/cacheinfo: fix crash when compiling with uClibc
+      tcg/optimize: only read val after const check
-Philippe Mathieu-Daudé (1):
+Richard Henderson (28):
-      scripts/git.orderfile: Display decodetree before C source
+      tcg: Add opcodes for vector nand, nor, eqv
       tcg/ppc: Implement vector NAND, NOR, EQV
       tcg/s390x: Implement vector NAND, NOR, EQV
       tcg/i386: Detect AVX512
       tcg/i386: Add tcg_out_evex_opc
       tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
       tcg/i386: Implement avx512 variable shifts
       tcg/i386: Implement avx512 scalar shift
       tcg/i386: Implement avx512 immediate sari shift
       tcg/i386: Implement avx512 immediate rotate
       tcg/i386: Implement avx512 variable rotate
       tcg/i386: Support avx512vbmi2 vector shift-double instructions
       tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
       tcg/i386: Remove rotls_vec from tcg_target_op_def
       tcg/i386: Expand scalar rotate with avx512 insns
       tcg/i386: Implement avx512 min/max/abs
       tcg/i386: Implement avx512 multiply
       tcg/i386: Implement more logical operations for avx512
       tcg/i386: Implement bitsel for avx512
       tcg: Add TCG_TARGET_SIGNED_ADDR32
       accel/tcg: Split out g2h_tlbe
       accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
       accel/tcg: Add guest_base_signed_addr32 for user-only
       linux-user: Support TCG_TARGET_SIGNED_ADDR32
       tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
       tcg/mips: Support TCG_TARGET_SIGNED_ADDR32
       tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
       tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32
-Richard Henderson (14):
+Ziqiao Kong (1):
-      cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN
+      tcg: Set MAX_OPC_PARAM_IARGS to 7
       vl: Remove unused variable in configure_accelerators
       vl: Reduce scope of variables in configure_accelerators
       vl: Remove useless test in configure_accelerators
       vl: Only choose enabled accelerators in configure_accelerators
       cputlb: Merge tlb_table_flush_by_mmuidx into tlb_flush_one_mmuidx_locked
       cputlb: Make tlb_n_entries private to cputlb.c
       cputlb: Pass CPUTLBDescFast to tlb_n_entries and sizeof_tlb
       cputlb: Hoist tlb portions in tlb_mmu_resize_locked
       cputlb: Hoist tlb portions in tlb_flush_one_mmuidx_locked
       cputlb: Split out tlb_mmu_flush_locked
       cputlb: Partially merge tlb_dyn_init into tlb_init
       cputlb: Initialize tlbs as flushed
       cputlb: Hoist timestamp outside of loops over tlbs
- include/exec/cpu_ldst.h |   5 -
+ include/exec/cpu-all.h            |  20 +-
- accel/tcg/cputlb.c      | 287 +++++++++++++++++++++++++++++++++---------------
+ include/exec/cpu_ldst.h           |   3 +-
- util/cacheinfo.c        |  10 +-
+ include/qemu/cpuid.h              |  20 +-
- vl.c                    |  27 +++--
+ include/tcg/tcg-opc.h             |   3 +
- scripts/git.orderfile   |   3 +
+ include/tcg/tcg.h                 |   5 +-
-files changed, 223 insertions(+), 109 deletions(-)
+ tcg/aarch64/tcg-target-sa32.h     |   7 +
  tcg/aarch64/tcg-target.h          |   3 +
  tcg/arm/tcg-target-sa32.h         |   1 +
  tcg/arm/tcg-target.h              |   3 +
  tcg/i386/tcg-target-con-set.h     |   1 +
  tcg/i386/tcg-target-sa32.h        |   1 +
  tcg/i386/tcg-target.h             |  17 +-
  tcg/i386/tcg-target.opc.h         |   3 +
  tcg/loongarch64/tcg-target-sa32.h |   1 +
  tcg/mips/tcg-target-sa32.h        |   9 +
  tcg/ppc/tcg-target-sa32.h         |   1 +
  tcg/ppc/tcg-target.h              |   3 +
  tcg/riscv/tcg-target-sa32.h       |   5 +
  tcg/s390x/tcg-target-sa32.h       |   1 +
  tcg/s390x/tcg-target.h            |   3 +
  tcg/sparc/tcg-target-sa32.h       |   1 +
  tcg/tci/tcg-target-sa32.h         |   1 +
  accel/tcg/cputlb.c                |  36 ++--
  bsd-user/main.c                   |   4 +
  linux-user/elfload.c              |  62 ++++--
  linux-user/main.c                 |   3 +
  tcg/optimize.c                    |  20 +-
  tcg/tcg-op-vec.c                  |  27 ++-
  tcg/tcg.c                         |  10 +
  tcg/aarch64/tcg-target.c.inc      |  81 +++++---
  tcg/i386/tcg-target.c.inc         | 387 +++++++++++++++++++++++++++++++-------
  tcg/loongarch64/tcg-target.c.inc  |  15 +-
  tcg/mips/tcg-target.c.inc         |  10 +-
  tcg/ppc/tcg-target.c.inc          |  15 ++
  tcg/riscv/tcg-target.c.inc        |   8 +-
  tcg/s390x/tcg-target.c.inc        |  17 ++
  tcg/tci/tcg-target.c.inc          |   2 +-
 files changed, 640 insertions(+), 169 deletions(-)
  create mode 100644 tcg/aarch64/tcg-target-sa32.h
  create mode 100644 tcg/arm/tcg-target-sa32.h
  create mode 100644 tcg/i386/tcg-target-sa32.h
  create mode 100644 tcg/loongarch64/tcg-target-sa32.h
  create mode 100644 tcg/mips/tcg-target-sa32.h
  create mode 100644 tcg/ppc/tcg-target-sa32.h
  create mode 100644 tcg/riscv/tcg-target-sa32.h
  create mode 100644 tcg/s390x/tcg-target-sa32.h
  create mode 100644 tcg/sparc/tcg-target-sa32.h
  create mode 100644 tcg/tci/tcg-target-sa32.h

-New patch
+[PULL 01/30] tcg/optimize: only read val after const check
+From: Alex Bennée <alex.bennee@linaro.org>
+valgrind pointed out that arg_info()->val can be undefined which will
+be the case if the arguments are not constant. The ordering of the
+checks will have ensured we never relied on an undefined value but for
+the sake of completeness re-order the code to be clear.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/optimize.c | 8 ++++----
+file changed, 4 insertions(+), 4 deletions(-)
+diff --git a/tcg/optimize.c b/tcg/optimize.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/optimize.c
++++ b/tcg/optimize.c
+@@ -XXX,XX +XXX,XX @@ static bool do_constant_folding_cond_eq(TCGCond c)
+ static int do_constant_folding_cond(TCGType type, TCGArg x,
+                                     TCGArg y, TCGCond c)
+ {
+-    uint64_t xv = arg_info(x)->val;
+-    uint64_t yv = arg_info(y)->val;
+-
+     if (arg_is_const(x) && arg_is_const(y)) {
++        uint64_t xv = arg_info(x)->val;
++        uint64_t yv = arg_info(y)->val;
++
+         switch (type) {
+         case TCG_TYPE_I32:
+             return do_constant_folding_cond_32(xv, yv, c);
+@@ -XXX,XX +XXX,XX @@ static int do_constant_folding_cond(TCGType type, TCGArg x,
+         }
+     } else if (args_are_copies(x, y)) {
+         return do_constant_folding_cond_eq(c);
+-    } else if (arg_is_const(y) && yv == 0) {
++    } else if (arg_is_const(y) && arg_info(y)->val == 0) {
+         switch (c) {
+         case TCG_COND_LTU:
+             return 0;
+--
+.25.1

-New patch
+[PULL 02/30] tcg: Set MAX_OPC_PARAM_IARGS to 7
+From: Ziqiao Kong <ziqiaokong@gmail.com>
+The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
+thus the MAX_OPC_PARAM_IARGS should be 7.
+Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
+Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
+Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com>
+Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments")
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ include/tcg/tcg.h        | 2 +-
+ tcg/tci/tcg-target.c.inc | 2 +-
+files changed, 2 insertions(+), 2 deletions(-)
+diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/tcg/tcg.h
++++ b/include/tcg/tcg.h
+@@ -XXX,XX +XXX,XX @@
+ #else
+ #define MAX_OPC_PARAM_PER_ARG 1
+ #endif
+-#define MAX_OPC_PARAM_IARGS 6
++#define MAX_OPC_PARAM_IARGS 7
+ #define MAX_OPC_PARAM_OARGS 1
+ #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
+diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/tci/tcg-target.c.inc
++++ b/tcg/tci/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
+     TCG_REG_R0,
+ };
+-#if MAX_OPC_PARAM_IARGS != 6
++#if MAX_OPC_PARAM_IARGS != 7
+ # error Fix needed, number of supported input arguments changed!
+ #endif
+--
+.25.1

-New patch
+[PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv
+We've had placeholders for these opcodes for a while,
 and should have support on ppc, s390x and avx512 hosts.
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
  include/tcg/tcg-opc.h    |  3 +++
  include/tcg/tcg.h        |  3 +++
  tcg/aarch64/tcg-target.h |  3 +++
  tcg/arm/tcg-target.h     |  3 +++
  tcg/i386/tcg-target.h    |  3 +++
  tcg/ppc/tcg-target.h     |  3 +++
  tcg/s390x/tcg-target.h   |  3 +++
  tcg/optimize.c           | 12 ++++++------
  tcg/tcg-op-vec.c         | 27 ++++++++++++++++++---------
  tcg/tcg.c                |  6 ++++++
 files changed, 51 insertions(+), 15 deletions(-)
 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg-opc.h
 +++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(or_vec, 1, 2, 0, IMPLVEC)
  DEF(xor_vec, 1, 2, 0, IMPLVEC)
  DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
  DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
 +DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec))
 +DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec))
 +DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec))
  DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
  DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg.h
 +++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
  #define TCG_TARGET_HAS_not_vec          0
  #define TCG_TARGET_HAS_andc_vec         0
  #define TCG_TARGET_HAS_orc_vec          0
 +#define TCG_TARGET_HAS_nand_vec         0
 +#define TCG_TARGET_HAS_nor_vec          0
 +#define TCG_TARGET_HAS_eqv_vec          0
  #define TCG_TARGET_HAS_roti_vec         0
  #define TCG_TARGET_HAS_rots_vec         0
  #define TCG_TARGET_HAS_rotv_vec         0
 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/aarch64/tcg-target.h
 +++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #define TCG_TARGET_HAS_andc_vec         1
  #define TCG_TARGET_HAS_orc_vec          1
 +#define TCG_TARGET_HAS_nand_vec         0
 +#define TCG_TARGET_HAS_nor_vec          0
 +#define TCG_TARGET_HAS_eqv_vec          0
  #define TCG_TARGET_HAS_not_vec          1
  #define TCG_TARGET_HAS_neg_vec          1
  #define TCG_TARGET_HAS_abs_vec          1
 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.h
 +++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
  #define TCG_TARGET_HAS_andc_vec         1
  #define TCG_TARGET_HAS_orc_vec          1
 +#define TCG_TARGET_HAS_nand_vec         0
 +#define TCG_TARGET_HAS_nor_vec          0
 +#define TCG_TARGET_HAS_eqv_vec          0
  #define TCG_TARGET_HAS_not_vec          1
  #define TCG_TARGET_HAS_neg_vec          1
  #define TCG_TARGET_HAS_abs_vec          1
 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.h
 +++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
  #define TCG_TARGET_HAS_andc_vec         1
  #define TCG_TARGET_HAS_orc_vec          0
 +#define TCG_TARGET_HAS_nand_vec         0
 +#define TCG_TARGET_HAS_nor_vec          0
 +#define TCG_TARGET_HAS_eqv_vec          0
  #define TCG_TARGET_HAS_not_vec          0
  #define TCG_TARGET_HAS_neg_vec          0
  #define TCG_TARGET_HAS_abs_vec          1
 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.h
 +++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
  #define TCG_TARGET_HAS_andc_vec         1
  #define TCG_TARGET_HAS_orc_vec          have_isa_2_07
 +#define TCG_TARGET_HAS_nand_vec         0
 +#define TCG_TARGET_HAS_nor_vec          0
 +#define TCG_TARGET_HAS_eqv_vec          0
  #define TCG_TARGET_HAS_not_vec          1
  #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
  #define TCG_TARGET_HAS_abs_vec          0
 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/s390x/tcg-target.h
 +++ b/tcg/s390x/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
  #define TCG_TARGET_HAS_andc_vec       1
  #define TCG_TARGET_HAS_orc_vec        HAVE_FACILITY(VECTOR_ENH1)
 +#define TCG_TARGET_HAS_nand_vec       0
 +#define TCG_TARGET_HAS_nor_vec        0
 +#define TCG_TARGET_HAS_eqv_vec        0
  #define TCG_TARGET_HAS_not_vec        1
  #define TCG_TARGET_HAS_neg_vec        1
  #define TCG_TARGET_HAS_abs_vec        1
 diff --git a/tcg/optimize.c b/tcg/optimize.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/optimize.c
 +++ b/tcg/optimize.c
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
      CASE_OP_32_64_VEC(orc):
          return x | ~y;
 -    CASE_OP_32_64(eqv):
 +    CASE_OP_32_64_VEC(eqv):
          return ~(x ^ y);
 -    CASE_OP_32_64(nand):
 +    CASE_OP_32_64_VEC(nand):
          return ~(x & y);
 -    CASE_OP_32_64(nor):
 +    CASE_OP_32_64_VEC(nor):
          return ~(x | y);
      case INDEX_op_clz_i32:
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
          case INDEX_op_dup2_vec:
              done = fold_dup2(&ctx, op);
              break;
 -        CASE_OP_32_64(eqv):
 +        CASE_OP_32_64_VEC(eqv):
              done = fold_eqv(&ctx, op);
              break;
          CASE_OP_32_64(extract):
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
          CASE_OP_32_64(mulu2):
              done = fold_multiply2(&ctx, op);
              break;
 -        CASE_OP_32_64(nand):
 +        CASE_OP_32_64_VEC(nand):
              done = fold_nand(&ctx, op);
              break;
          CASE_OP_32_64(neg):
              done = fold_neg(&ctx, op);
              break;
 -        CASE_OP_32_64(nor):
 +        CASE_OP_32_64_VEC(nor):
              done = fold_nor(&ctx, op);
              break;
          CASE_OP_32_64_VEC(not):
 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg-op-vec.c
 +++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
  void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
  {
 -    /* TODO: Add TCG_TARGET_HAS_nand_vec when adding a backend supports it. */
 -    tcg_gen_and_vec(0, r, a, b);
 -    tcg_gen_not_vec(0, r, r);
 +    if (TCG_TARGET_HAS_nand_vec) {
 +        vec_gen_op3(INDEX_op_nand_vec, 0, r, a, b);
 +    } else {
 +        tcg_gen_and_vec(0, r, a, b);
 +        tcg_gen_not_vec(0, r, r);
 +    }
  }
  void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
  {
 -    /* TODO: Add TCG_TARGET_HAS_nor_vec when adding a backend supports it. */
 -    tcg_gen_or_vec(0, r, a, b);
 -    tcg_gen_not_vec(0, r, r);
 +    if (TCG_TARGET_HAS_nor_vec) {
 +        vec_gen_op3(INDEX_op_nor_vec, 0, r, a, b);
 +    } else {
 +        tcg_gen_or_vec(0, r, a, b);
 +        tcg_gen_not_vec(0, r, r);
 +    }
  }
  void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
  {
 -    /* TODO: Add TCG_TARGET_HAS_eqv_vec when adding a backend supports it. */
 -    tcg_gen_xor_vec(0, r, a, b);
 -    tcg_gen_not_vec(0, r, r);
 +    if (TCG_TARGET_HAS_eqv_vec) {
 +        vec_gen_op3(INDEX_op_eqv_vec, 0, r, a, b);
 +    } else {
 +        tcg_gen_xor_vec(0, r, a, b);
 +        tcg_gen_not_vec(0, r, r);
 +    }
  }
  static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
          return have_vec && TCG_TARGET_HAS_andc_vec;
      case INDEX_op_orc_vec:
          return have_vec && TCG_TARGET_HAS_orc_vec;
 +    case INDEX_op_nand_vec:
 +        return have_vec && TCG_TARGET_HAS_nand_vec;
 +    case INDEX_op_nor_vec:
 +        return have_vec && TCG_TARGET_HAS_nor_vec;
 +    case INDEX_op_eqv_vec:
 +        return have_vec && TCG_TARGET_HAS_eqv_vec;
      case INDEX_op_mul_vec:
          return have_vec && TCG_TARGET_HAS_mul_vec;
      case INDEX_op_shli_vec:
 --
 .25.1

-New patch
+[PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/ppc/tcg-target.h     |  6 +++---
+ tcg/ppc/tcg-target.c.inc | 15 +++++++++++++++
+files changed, 18 insertions(+), 3 deletions(-)
+diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/ppc/tcg-target.h
++++ b/tcg/ppc/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
+ #define TCG_TARGET_HAS_andc_vec         1
+ #define TCG_TARGET_HAS_orc_vec          have_isa_2_07
+-#define TCG_TARGET_HAS_nand_vec         0
+-#define TCG_TARGET_HAS_nor_vec          0
+-#define TCG_TARGET_HAS_eqv_vec          0
++#define TCG_TARGET_HAS_nand_vec         have_isa_2_07
++#define TCG_TARGET_HAS_nor_vec          1
++#define TCG_TARGET_HAS_eqv_vec          have_isa_2_07
+ #define TCG_TARGET_HAS_not_vec          1
+ #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
+ #define TCG_TARGET_HAS_abs_vec          0
+diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/ppc/tcg-target.c.inc
++++ b/tcg/ppc/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_xor_vec:
+     case INDEX_op_andc_vec:
+     case INDEX_op_not_vec:
++    case INDEX_op_nor_vec:
++    case INDEX_op_eqv_vec:
++    case INDEX_op_nand_vec:
+         return 1;
+     case INDEX_op_orc_vec:
+         return have_isa_2_07;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     case INDEX_op_orc_vec:
+         insn = VORC;
+         break;
++    case INDEX_op_nand_vec:
++        insn = VNAND;
++        break;
++    case INDEX_op_nor_vec:
++        insn = VNOR;
++        break;
++    case INDEX_op_eqv_vec:
++        insn = VEQV;
++        break;
+     case INDEX_op_cmp_vec:
+         switch (args[3]) {
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_xor_vec:
+     case INDEX_op_andc_vec:
+     case INDEX_op_orc_vec:
++    case INDEX_op_nor_vec:
++    case INDEX_op_eqv_vec:
++    case INDEX_op_nand_vec:
+     case INDEX_op_cmp_vec:
+     case INDEX_op_ssadd_vec:
+     case INDEX_op_sssub_vec:
+--
+.25.1

-New patch
+[PULL 05/30] tcg/s390x: Implement vector NAND, NOR, EQV
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/s390x/tcg-target.h     |  6 +++---
+ tcg/s390x/tcg-target.c.inc | 17 +++++++++++++++++
+files changed, 20 insertions(+), 3 deletions(-)
+diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/s390x/tcg-target.h
++++ b/tcg/s390x/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
+ #define TCG_TARGET_HAS_andc_vec       1
+ #define TCG_TARGET_HAS_orc_vec        HAVE_FACILITY(VECTOR_ENH1)
+-#define TCG_TARGET_HAS_nand_vec       0
+-#define TCG_TARGET_HAS_nor_vec        0
+-#define TCG_TARGET_HAS_eqv_vec        0
++#define TCG_TARGET_HAS_nand_vec       HAVE_FACILITY(VECTOR_ENH1)
++#define TCG_TARGET_HAS_nor_vec        1
++#define TCG_TARGET_HAS_eqv_vec        HAVE_FACILITY(VECTOR_ENH1)
+ #define TCG_TARGET_HAS_not_vec        1
+ #define TCG_TARGET_HAS_neg_vec        1
+ #define TCG_TARGET_HAS_abs_vec        1
+diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/s390x/tcg-target.c.inc
++++ b/tcg/s390x/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
+     VRRc_VMXL   = 0xe7fd,
+     VRRc_VN     = 0xe768,
+     VRRc_VNC    = 0xe769,
++    VRRc_VNN    = 0xe76e,
+     VRRc_VNO    = 0xe76b,
++    VRRc_VNX    = 0xe76c,
+     VRRc_VO     = 0xe76a,
+     VRRc_VOC    = 0xe76f,
+     VRRc_VPKS   = 0xe797,   /* we leave the m5 cs field 0 */
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     case INDEX_op_xor_vec:
+         tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
+         break;
++    case INDEX_op_nand_vec:
++        tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0);
++        break;
++    case INDEX_op_nor_vec:
++        tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0);
++        break;
++    case INDEX_op_eqv_vec:
++        tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0);
++        break;
+     case INDEX_op_shli_vec:
+         tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_and_vec:
+     case INDEX_op_andc_vec:
+     case INDEX_op_bitsel_vec:
++    case INDEX_op_eqv_vec:
++    case INDEX_op_nand_vec:
+     case INDEX_op_neg_vec:
++    case INDEX_op_nor_vec:
+     case INDEX_op_not_vec:
+     case INDEX_op_or_vec:
+     case INDEX_op_orc_vec:
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_or_vec:
+     case INDEX_op_orc_vec:
+     case INDEX_op_xor_vec:
++    case INDEX_op_nand_vec:
++    case INDEX_op_nor_vec:
++    case INDEX_op_eqv_vec:
+     case INDEX_op_cmp_vec:
+     case INDEX_op_mul_vec:
+     case INDEX_op_rotlv_vec:
+--
+.25.1

-[PULL 06/16] vl: Only choose enabled accelerators in configure_accelerators
+[PULL 06/30] tcg/i386: Detect AVX512
-By choosing "tcg:kvm" when kvm is not enabled, we generate
+There are some operation sizes in some subsets of AVX512 that
-an incorrect warning: "invalid accelerator kvm".
+are missing from previous iterations of AVX.  Detect them.
-At the same time, use g_str_has_suffix rather than open-coding
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 the same operation.
 Presumably the inverse is also true with --disable-tcg.
 Fixes: 28a0961757fc
 Acked-by: Paolo Bonzini <pbonzini@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- vl.c | 21 +++++++++++++--------
+ include/qemu/cpuid.h      | 20 +++++++++++++++++---
-file changed, 13 insertions(+), 8 deletions(-)
+ tcg/i386/tcg-target.h     |  4 ++++
  tcg/i386/tcg-target.c.inc | 24 ++++++++++++++++++++++--
 files changed, 43 insertions(+), 5 deletions(-)
-diff --git a/vl.c b/vl.c
+diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
 index XXXXXXX..XXXXXXX 100644
---- a/vl.c
+--- a/include/qemu/cpuid.h
-+++ b/vl.c
++++ b/include/qemu/cpuid.h
-@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
+@@ -XXX,XX +XXX,XX @@
+ #ifndef bit_AVX2
-         if (accel == NULL) {
+ #define bit_AVX2        (1 << 5)
-             /* Select the default accelerator */
+ #endif
--            if (!accel_find("tcg") && !accel_find("kvm")) {
+-#ifndef bit_AVX512F
--                error_report("No accelerator selected and"
+-#define bit_AVX512F        (1 << 16)
--                             " no default accelerator available");
+-#endif
--                exit(1);
+ #ifndef bit_BMI2
--            } else {
+ #define bit_BMI2        (1 << 8)
--                int pnlen = strlen(progname);
+ #endif
--                if (pnlen >= 3 && g_str_equal(&progname[pnlen - 3], "kvm")) {
++#ifndef bit_AVX512F
-+            bool have_tcg = accel_find("tcg");
++#define bit_AVX512F     (1 << 16)
-+            bool have_kvm = accel_find("kvm");
++#endif
 +#ifndef bit_AVX512DQ
 +#define bit_AVX512DQ    (1 << 17)
 +#endif
 +#ifndef bit_AVX512BW
 +#define bit_AVX512BW    (1 << 30)
 +#endif
 +#ifndef bit_AVX512VL
 +#define bit_AVX512VL    (1u << 31)
 +#endif
 +
-+            if (have_tcg && have_kvm) {
++/* Leaf 7, %ecx */
-+                if (g_str_has_suffix(progname, "kvm")) {
++#ifndef bit_AVX512VBMI2
-                     /* If the program name ends with "kvm", we prefer KVM */
++#define bit_AVX512VBMI2 (1 << 6)
-                     accel = "kvm:tcg";
++#endif
-                 } else {
-                     accel = "tcg:kvm";
+ /* Leaf 0x80000001, %ecx */
-                 }
+ #ifndef bit_LZCNT
-+            } else if (have_kvm) {
+diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
-+                accel = "kvm";
+index XXXXXXX..XXXXXXX 100644
-+            } else if (have_tcg) {
+--- a/tcg/i386/tcg-target.h
-+                accel = "tcg";
++++ b/tcg/i386/tcg-target.h
-+            } else {
+@@ -XXX,XX +XXX,XX @@ extern bool have_bmi1;
-+                error_report("No accelerator selected and"
+ extern bool have_popcnt;
-+                             " no default accelerator available");
+ extern bool have_avx1;
-+                exit(1);
+ extern bool have_avx2;
 +extern bool have_avx512bw;
 +extern bool have_avx512dq;
 +extern bool have_avx512vbmi2;
 +extern bool have_avx512vl;
  extern bool have_movbe;
  /* optional instructions */
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ bool have_bmi1;
  bool have_popcnt;
  bool have_avx1;
  bool have_avx2;
 +bool have_avx512bw;
 +bool have_avx512dq;
 +bool have_avx512vbmi2;
 +bool have_avx512vl;
  bool have_movbe;
  #ifdef CONFIG_CPUID_H
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
  static void tcg_target_init(TCGContext *s)
  {
  #ifdef CONFIG_CPUID_H
 -    unsigned a, b, c, d, b7 = 0;
 +    unsigned a, b, c, d, b7 = 0, c7 = 0;
      unsigned max = __get_cpuid_max(0, 0);
      if (max >= 7) {
          /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs.  */
 -        __cpuid_count(7, 0, a, b7, c, d);
 +        __cpuid_count(7, 0, a, b7, c7, d);
          have_bmi1 = (b7 & bit_BMI) != 0;
          have_bmi2 = (b7 & bit_BMI2) != 0;
      }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
              if ((xcrl & 6) == 6) {
                  have_avx1 = (c & bit_AVX) != 0;
                  have_avx2 = (b7 & bit_AVX2) != 0;
 +
 +                /*
 +                 * There are interesting instructions in AVX512, so long
 +                 * as we have AVX512VL, which indicates support for EVEX
 +                 * on sizes smaller than 512 bits.  We are required to
 +                 * check that OPMASK and all extended ZMM state are enabled
 +                 * even if we're not using them -- the insns will fault.
 +                 */
 +                if ((xcrl & 0xe0) == 0xe0
 +                    && (b7 & bit_AVX512F)
 +                    && (b7 & bit_AVX512VL)) {
 +                    have_avx512vl = true;
 +                    have_avx512bw = (b7 & bit_AVX512BW) != 0;
 +                    have_avx512dq = (b7 & bit_AVX512DQ) != 0;
 +                    have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0;
 +                }
              }
          }
--
+     }
          accel_list = g_strsplit(accel, ":", 0);
          for (tmp = accel_list; *tmp; tmp++) {
 --
-.20.1
+.25.1

-[PULL 12/16] cputlb: Split out tlb_mmu_flush_locked
+[PULL 07/30] tcg/i386: Add tcg_out_evex_opc
-We will want to be able to flush a tlb without resizing.
+The evex encoding is added here, for use in a subsequent patch.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 15 ++++++++++-----
+ tcg/i386/tcg-target.c.inc | 51 ++++++++++++++++++++++++++++++++++++++-
-file changed, 10 insertions(+), 5 deletions(-)
+file changed, 50 insertions(+), 1 deletion(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/i386/tcg-target.c.inc
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     }
+ #define P_SIMDF3        0x20000         /* 0xf3 opcode prefix */
  #define P_SIMDF2        0x40000         /* 0xf2 opcode prefix */
  #define P_VEXL          0x80000         /* Set VEX.L = 1 */
 +#define P_EVEX          0x100000        /* Requires EVEX encoding */
  #define OPC_ARITH_EvIz    (0x81)
  #define OPC_ARITH_EvIb    (0x83)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
      tcg_out8(s, opc);
  }
--static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
++static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v,
-+static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
++                             int rm, int index)
  {
 -    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
 -    CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
 -
 -    tlb_mmu_resize_locked(desc, fast);
      desc->n_used_entries = 0;
      desc->large_page_addr = -1;
      desc->large_page_mask = -1;
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
      memset(desc->vtable, -1, sizeof(desc->vtable));
  }
 +static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
 +{
-+    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
++    /* The entire 4-byte evex prefix; with R' and V' set. */
-+    CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
++    uint32_t p = 0x08041062;
 +    int mm, pp;
 +
-+    tlb_mmu_resize_locked(desc, fast);
++    tcg_debug_assert(have_avx512vl);
-+    tlb_mmu_flush_locked(desc, fast);
++
 +    /* EVEX.mm */
 +    if (opc & P_EXT3A) {
 +        mm = 3;
 +    } else if (opc & P_EXT38) {
 +        mm = 2;
 +    } else if (opc & P_EXT) {
 +        mm = 1;
 +    } else {
 +        g_assert_not_reached();
 +    }
 +
 +    /* EVEX.pp */
 +    if (opc & P_DATA16) {
 +        pp = 1;                          /* 0x66 */
 +    } else if (opc & P_SIMDF3) {
 +        pp = 2;                          /* 0xf3 */
 +    } else if (opc & P_SIMDF2) {
 +        pp = 3;                          /* 0xf2 */
 +    } else {
 +        pp = 0;
 +    }
 +
 +    p = deposit32(p, 8, 2, mm);
 +    p = deposit32(p, 13, 1, (rm & 8) == 0);             /* EVEX.RXB.B */
 +    p = deposit32(p, 14, 1, (index & 8) == 0);          /* EVEX.RXB.X */
 +    p = deposit32(p, 15, 1, (r & 8) == 0);              /* EVEX.RXB.R */
 +    p = deposit32(p, 16, 2, pp);
 +    p = deposit32(p, 19, 4, ~v);
 +    p = deposit32(p, 23, 1, (opc & P_VEXW) != 0);
 +    p = deposit32(p, 29, 2, (opc & P_VEXL) != 0);
 +
 +    tcg_out32(s, p);
 +    tcg_out8(s, opc);
 +}
 +
- static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
+ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
  {
-     env_tlb(env)->d[mmu_idx].n_used_entries++;
+-    tcg_out_vex_opc(s, opc, r, v, rm, 0);
 +    if (opc & P_EVEX) {
 +        tcg_out_evex_opc(s, opc, r, v, rm, 0);
 +    } else {
 +        tcg_out_vex_opc(s, opc, r, v, rm, 0);
 +    }
      tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
  }
 --
-.20.1
+.25.1

-New patch
+[PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
+The condition for UMIN/UMAX availability is about to change;
+use the canonical version.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.c.inc | 8 ++++----
+file changed, 4 insertions(+), 4 deletions(-)
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
+         fixup = NEED_SWAP | NEED_INV;
+         break;
+     case TCG_COND_LEU:
+-        if (vece <= MO_32) {
++        if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) {
+             fixup = NEED_UMIN;
+         } else {
+             fixup = NEED_BIAS | NEED_INV;
+         }
+         break;
+     case TCG_COND_GTU:
+-        if (vece <= MO_32) {
++        if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) {
+             fixup = NEED_UMIN | NEED_INV;
+         } else {
+             fixup = NEED_BIAS;
+         }
+         break;
+     case TCG_COND_GEU:
+-        if (vece <= MO_32) {
++        if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) {
+             fixup = NEED_UMAX;
+         } else {
+             fixup = NEED_BIAS | NEED_SWAP | NEED_INV;
+         }
+         break;
+     case TCG_COND_LTU:
+-        if (vece <= MO_32) {
++        if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) {
+             fixup = NEED_UMAX | NEED_INV;
+         } else {
+             fixup = NEED_BIAS | NEED_SWAP;
+--
+.25.1

-New patch
+[PULL 09/30] tcg/i386: Implement avx512 variable shifts
+AVX512VL has VPSRAVQ, and
+AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
+file changed, 24 insertions(+), 8 deletions(-)
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
+ #define OPC_VPERMQ      (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
+ #define OPC_VPERM2I128  (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
++#define OPC_VPSLLVW     (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSLLVD     (0x47 | P_EXT38 | P_DATA16)
+ #define OPC_VPSLLVQ     (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
++#define OPC_VPSRAVW     (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSRAVD     (0x46 | P_EXT38 | P_DATA16)
++#define OPC_VPSRAVQ     (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSRLVW     (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSRLVD     (0x45 | P_EXT38 | P_DATA16)
+ #define OPC_VPSRLVQ     (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
+ #define OPC_VZEROUPPER  (0x77 | P_EXT)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
+     };
+     static int const shlv_insn[4] = {
+-        /* TODO: AVX512 adds support for MO_16.  */
+-        OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
++        OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
+     };
+     static int const shrv_insn[4] = {
+-        /* TODO: AVX512 adds support for MO_16.  */
+-        OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
++        OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ
+     };
+     static int const sarv_insn[4] = {
+-        /* TODO: AVX512 adds support for MO_16, MO_64.  */
+-        OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
++        OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ
+     };
+     static int const shls_insn[4] = {
+         OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_shlv_vec:
+     case INDEX_op_shrv_vec:
+-        return have_avx2 && vece >= MO_32;
++        switch (vece) {
++        case MO_16:
++            return have_avx512bw;
++        case MO_32:
++        case MO_64:
++            return have_avx2;
++        }
++        return 0;
+     case INDEX_op_sarv_vec:
+-        return have_avx2 && vece == MO_32;
++        switch (vece) {
++        case MO_16:
++            return have_avx512bw;
++        case MO_32:
++            return have_avx2;
++        case MO_64:
++            return have_avx512vl;
++        }
++        return 0;
+     case INDEX_op_rotlv_vec:
+     case INDEX_op_rotrv_vec:
+         return have_avx2 && vece >= MO_32 ? -1 : 0;
+--
+.25.1

-New patch
+[PULL 10/30] tcg/i386: Implement avx512 scalar shift
+AVX512VL has VPSRAQ.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.c.inc | 12 ++++++++++--
+file changed, 10 insertions(+), 2 deletions(-)
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ #define OPC_PSLLQ       (0xf3 | P_EXT | P_DATA16)
+ #define OPC_PSRAW       (0xe1 | P_EXT | P_DATA16)
+ #define OPC_PSRAD       (0xe2 | P_EXT | P_DATA16)
++#define OPC_VPSRAQ      (0x72 | P_EXT | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_PSRLW       (0xd1 | P_EXT | P_DATA16)
+ #define OPC_PSRLD       (0xd2 | P_EXT | P_DATA16)
+ #define OPC_PSRLQ       (0xd3 | P_EXT | P_DATA16)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ
+     };
+     static int const sars_insn[4] = {
+-        OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
++        OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ
+     };
+     static int const abs_insn[4] = {
+         /* TODO: AVX512 adds support for MO_64.  */
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_shrs_vec:
+         return vece >= MO_16;
+     case INDEX_op_sars_vec:
+-        return vece >= MO_16 && vece <= MO_32;
++        switch (vece) {
++        case MO_16:
++        case MO_32:
++            return 1;
++        case MO_64:
++            return have_avx512vl;
++        }
++        return 0;
+     case INDEX_op_rotls_vec:
+         return vece >= MO_16 ? -1 : 0;
+--
+.25.1

-New patch
+[PULL 11/30] tcg/i386: Implement avx512 immediate sari shift
+AVX512 has VPSRAQ with immediate operand, in the same form as
+with AVX, but requires EVEX encoding and W1.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++---------
+file changed, 21 insertions(+), 9 deletions(-)
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         break;
+     case INDEX_op_shli_vec:
++        insn = shift_imm_insn[vece];
+         sub = 6;
+         goto gen_shift;
+     case INDEX_op_shri_vec:
++        insn = shift_imm_insn[vece];
+         sub = 2;
+         goto gen_shift;
+     case INDEX_op_sari_vec:
+-        tcg_debug_assert(vece != MO_64);
++        if (vece == MO_64) {
++            insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX;
++        } else {
++            insn = shift_imm_insn[vece];
++        }
+         sub = 4;
+     gen_shift:
+         tcg_debug_assert(vece != MO_8);
+-        insn = shift_imm_insn[vece];
+         if (type == TCG_TYPE_V256) {
+             insn |= P_VEXL;
+         }
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+         return vece == MO_8 ? -1 : 1;
+     case INDEX_op_sari_vec:
+-        /* We must expand the operation for MO_8.  */
+-        if (vece == MO_8) {
++        switch (vece) {
++        case MO_8:
+             return -1;
+-        }
+-        /* We can emulate this for MO_64, but it does not pay off
+-           unless we're producing at least 4 values.  */
+-        if (vece == MO_64) {
++        case MO_16:
++        case MO_32:
++            return 1;
++        case MO_64:
++            if (have_avx512vl) {
++                return 1;
++            }
++            /*
++             * We can emulate this for MO_64, but it does not pay off
++             * unless we're producing at least 4 values.
++             */
+             return type >= TCG_TYPE_V256 ? -1 : 0;
+         }
+-        return 1;
++        return 0;
+     case INDEX_op_shls_vec:
+     case INDEX_op_shrs_vec:
+--
+.25.1

-New patch
+[PULL 12/30] tcg/i386: Implement avx512 immediate rotate
+AVX512VL has VPROLD and VPROLQ, layered onto the same
+opcode as PSHIFTD, but requires EVEX encoding and W1.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.h     |  2 +-
+ tcg/i386/tcg-target.c.inc | 15 +++++++++++++--
+files changed, 14 insertions(+), 3 deletions(-)
+diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.h
++++ b/tcg/i386/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
+ #define TCG_TARGET_HAS_not_vec          0
+ #define TCG_TARGET_HAS_neg_vec          0
+ #define TCG_TARGET_HAS_abs_vec          1
+-#define TCG_TARGET_HAS_roti_vec         0
++#define TCG_TARGET_HAS_roti_vec         have_avx512vl
+ #define TCG_TARGET_HAS_rots_vec         0
+ #define TCG_TARGET_HAS_rotv_vec         0
+ #define TCG_TARGET_HAS_shi_vec          1
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ #define OPC_PSHUFLW     (0x70 | P_EXT | P_SIMDF2)
+ #define OPC_PSHUFHW     (0x70 | P_EXT | P_SIMDF3)
+ #define OPC_PSHIFTW_Ib  (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
+-#define OPC_PSHIFTD_Ib  (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
++#define OPC_PSHIFTD_Ib  (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */
+ #define OPC_PSHIFTQ_Ib  (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
+ #define OPC_PSLLW       (0xf1 | P_EXT | P_DATA16)
+ #define OPC_PSLLD       (0xf2 | P_EXT | P_DATA16)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+             insn = shift_imm_insn[vece];
+         }
+         sub = 4;
++        goto gen_shift;
++    case INDEX_op_rotli_vec:
++        insn = OPC_PSHIFTD_Ib | P_EVEX;  /* VPROL[DQ] */
++        if (vece == MO_64) {
++            insn |= P_VEXW;
++        }
++        sub = 1;
++        goto gen_shift;
+     gen_shift:
+         tcg_debug_assert(vece != MO_8);
+         if (type == TCG_TYPE_V256) {
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_shli_vec:
+     case INDEX_op_shri_vec:
+     case INDEX_op_sari_vec:
++    case INDEX_op_rotli_vec:
+     case INDEX_op_x86_psrldq_vec:
+         return C_O1_I1(x, x);
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_xor_vec:
+     case INDEX_op_andc_vec:
+         return 1;
+-    case INDEX_op_rotli_vec:
+     case INDEX_op_cmp_vec:
+     case INDEX_op_cmpsel_vec:
+         return -1;
++    case INDEX_op_rotli_vec:
++        return have_avx512vl && vece >= MO_32 ? 1 : -1;
++
+     case INDEX_op_shli_vec:
+     case INDEX_op_shri_vec:
+         /* We must expand the operation for MO_8.  */
+--
+.25.1

-New patch
+[PULL 13/30] tcg/i386: Implement avx512 variable rotate
+AVX512VL has VPROLVD and VPRORVQ.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.h     |  2 +-
+ tcg/i386/tcg-target.c.inc | 25 ++++++++++++++++++++++++-
+files changed, 25 insertions(+), 2 deletions(-)
+diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.h
++++ b/tcg/i386/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
+ #define TCG_TARGET_HAS_abs_vec          1
+ #define TCG_TARGET_HAS_roti_vec         have_avx512vl
+ #define TCG_TARGET_HAS_rots_vec         0
+-#define TCG_TARGET_HAS_rotv_vec         0
++#define TCG_TARGET_HAS_rotv_vec         have_avx512vl
+ #define TCG_TARGET_HAS_shi_vec          1
+ #define TCG_TARGET_HAS_shs_vec          1
+ #define TCG_TARGET_HAS_shv_vec          have_avx2
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
+ #define OPC_VPERMQ      (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
+ #define OPC_VPERM2I128  (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
++#define OPC_VPROLVD     (0x15 | P_EXT38 | P_DATA16 | P_EVEX)
++#define OPC_VPROLVQ     (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPRORVD     (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
++#define OPC_VPRORVQ     (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSLLVW     (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSLLVD     (0x47 | P_EXT38 | P_DATA16)
+ #define OPC_VPSLLVQ     (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     static int const umax_insn[4] = {
+         OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
+     };
++    static int const rotlv_insn[4] = {
++        OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
++    };
++    static int const rotrv_insn[4] = {
++        OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ
++    };
+     static int const shlv_insn[4] = {
+         OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
+     };
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     case INDEX_op_sarv_vec:
+         insn = sarv_insn[vece];
+         goto gen_simd;
++    case INDEX_op_rotlv_vec:
++        insn = rotlv_insn[vece];
++        goto gen_simd;
++    case INDEX_op_rotrv_vec:
++        insn = rotrv_insn[vece];
++        goto gen_simd;
+     case INDEX_op_shls_vec:
+         insn = shls_insn[vece];
+         goto gen_simd;
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_shlv_vec:
+     case INDEX_op_shrv_vec:
+     case INDEX_op_sarv_vec:
++    case INDEX_op_rotlv_vec:
++    case INDEX_op_rotrv_vec:
+     case INDEX_op_shls_vec:
+     case INDEX_op_shrs_vec:
+     case INDEX_op_sars_vec:
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+         return 0;
+     case INDEX_op_rotlv_vec:
+     case INDEX_op_rotrv_vec:
+-        return have_avx2 && vece >= MO_32 ? -1 : 0;
++        switch (vece) {
++        case MO_32:
++        case MO_64:
++            return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
++        }
++        return 0;
+     case INDEX_op_mul_vec:
+         if (vece == MO_8) {
+--
+.25.1

-New patch
+[PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions
+We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target-con-set.h |  1 +
+ tcg/i386/tcg-target.opc.h     |  3 +++
+ tcg/i386/tcg-target.c.inc     | 38 +++++++++++++++++++++++++++++++++++
+files changed, 42 insertions(+)
+diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target-con-set.h
++++ b/tcg/i386/tcg-target-con-set.h
+@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rI)
+ C_O1_I2(x, x, x)
+ C_N1_I2(r, r, r)
+ C_N1_I2(r, r, rW)
++C_O1_I3(x, 0, x, x)
+ C_O1_I3(x, x, x, x)
+ C_O1_I4(r, r, re, r, 0)
+ C_O1_I4(r, r, r, ri, ri)
+diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.opc.h
++++ b/tcg/i386/tcg-target.opc.h
+@@ -XXX,XX +XXX,XX @@ DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
+ DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
+ DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
+ DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
++DEF(x86_vpshldi_vec, 1, 2, 1, IMPLVEC)
++DEF(x86_vpshldv_vec, 1, 3, 0, IMPLVEC)
++DEF(x86_vpshrdv_vec, 1, 3, 0, IMPLVEC)
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ #define OPC_VPROLVQ     (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPRORVD     (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
+ #define OPC_VPRORVQ     (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSHLDW     (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSHLDD     (0x71 | P_EXT3A | P_DATA16 | P_EVEX)
++#define OPC_VPSHLDQ     (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSHLDVW    (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSHLDVD    (0x71 | P_EXT38 | P_DATA16 | P_EVEX)
++#define OPC_VPSHLDVQ    (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSHRDVW    (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
++#define OPC_VPSHRDVD    (0x73 | P_EXT38 | P_DATA16 | P_EVEX)
++#define OPC_VPSHRDVQ    (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSLLVW     (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+ #define OPC_VPSLLVD     (0x47 | P_EXT38 | P_DATA16)
+ #define OPC_VPSLLVQ     (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     static int const sars_insn[4] = {
+         OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ
+     };
++    static int const vpshldi_insn[4] = {
++        OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ
++    };
++    static int const vpshldv_insn[4] = {
++        OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ
++    };
++    static int const vpshrdv_insn[4] = {
++        OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ
++    };
+     static int const abs_insn[4] = {
+         /* TODO: AVX512 adds support for MO_64.  */
+         OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     case INDEX_op_x86_packus_vec:
+         insn = packus_insn[vece];
+         goto gen_simd;
++    case INDEX_op_x86_vpshldv_vec:
++        insn = vpshldv_insn[vece];
++        a1 = a2;
++        a2 = args[3];
++        goto gen_simd;
++    case INDEX_op_x86_vpshrdv_vec:
++        insn = vpshrdv_insn[vece];
++        a1 = a2;
++        a2 = args[3];
++        goto gen_simd;
+ #if TCG_TARGET_REG_BITS == 32
+     case INDEX_op_dup2_vec:
+         /* First merge the two 32-bit inputs to a single 64-bit element. */
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         insn = OPC_VPERM2I128;
+         sub = args[3];
+         goto gen_simd_imm8;
++    case INDEX_op_x86_vpshldi_vec:
++        insn = vpshldi_insn[vece];
++        sub = args[3];
++        goto gen_simd_imm8;
+     gen_simd_imm8:
++        tcg_debug_assert(insn != OPC_UD2);
+         if (type == TCG_TYPE_V256) {
+             insn |= P_VEXL;
+         }
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_x86_vperm2i128_vec:
+     case INDEX_op_x86_punpckl_vec:
+     case INDEX_op_x86_punpckh_vec:
++    case INDEX_op_x86_vpshldi_vec:
+ #if TCG_TARGET_REG_BITS == 32
+     case INDEX_op_dup2_vec:
+ #endif
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_x86_psrldq_vec:
+         return C_O1_I1(x, x);
++    case INDEX_op_x86_vpshldv_vec:
++    case INDEX_op_x86_vpshrdv_vec:
++        return C_O1_I3(x, 0, x, x);
++
+     case INDEX_op_x86_vpblendvb_vec:
+         return C_O1_I3(x, x, x, x);
+--
+.25.1

-[PULL 10/16] cputlb: Hoist tlb portions in tlb_mmu_resize_locked
+[PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
-No functional change, but the smaller expressions make
+While there are no specific 16-bit rotate instructions, there
-the code easier to read.
+are double-word shifts, which can perform the same operation.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 35 +++++++++++++++++------------------
+ tcg/i386/tcg-target.c.inc | 18 +++++++++++++++++-
-file changed, 17 insertions(+), 18 deletions(-)
+file changed, 17 insertions(+), 1 deletion(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/i386/tcg-target.c.inc
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_rotlv_vec:
- /**
+     case INDEX_op_rotrv_vec:
-  * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
+         switch (vece) {
-- * @env: CPU that owns the TLB
++        case MO_16:
-- * @mmu_idx: MMU index of the TLB
++            return have_avx512vbmi2 ? -1 : 0;
-+ * @desc: The CPUTLBDesc portion of the TLB
+         case MO_32:
-+ * @fast: The CPUTLBDescFast portion of the same TLB
+         case MO_64:
-  *
+             return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
-  * Called with tlb_lock_held.
+@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotli(TCGType type, unsigned vece,
   *
@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)
   * high), since otherwise we are likely to have a significant amount of
   * conflict misses.
   */
 -static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
 +static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
  {
 -    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
 -    size_t old_size = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);
 +    size_t old_size = tlb_n_entries(fast);
      size_t rate;
      size_t new_size = old_size;
      int64_t now = get_clock_realtime();
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
          return;
      }
--    g_free(env_tlb(env)->f[mmu_idx].table);
++    if (have_avx512vbmi2) {
--    g_free(env_tlb(env)->d[mmu_idx].iotlb);
++        vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece,
-+    g_free(fast->table);
++                  tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm);
-+    g_free(desc->iotlb);
++        return;
++    }
      tlb_window_reset(desc, now, 0);
      /* desc->n_used_entries is cleared by the caller */
 -    env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
 -    env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);
 -    env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);
 +    fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
 +    fast->table = g_try_new(CPUTLBEntry, new_size);
 +    desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
 +
-     /*
+     t = tcg_temp_new_vec(type);
-      * If the allocations fail, try smaller sizes. We just freed some
+     tcg_gen_shli_vec(vece, t, v1, imm);
-      * memory, so going back to half of new_size has a good chance of working.
+     tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
-@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
+@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotls(TCGType type, unsigned vece,
-      * allocations to fail though, so we progressively reduce the allocation
+ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
-      * size, aborting if we cannot even allocate the smallest TLB we support.
+                             TCGv_vec v1, TCGv_vec sh, bool right)
       */
 -    while (env_tlb(env)->f[mmu_idx].table == NULL ||
 -           env_tlb(env)->d[mmu_idx].iotlb == NULL) {
 +    while (fast->table == NULL || desc->iotlb == NULL) {
          if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
              error_report("%s: %s", __func__, strerror(errno));
              abort();
          }
          new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS);
 -        env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
 +        fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
 -        g_free(env_tlb(env)->f[mmu_idx].table);
 -        g_free(env_tlb(env)->d[mmu_idx].iotlb);
 -        env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);
 -        env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);
 +        g_free(fast->table);
 +        g_free(desc->iotlb);
 +        fast->table = g_try_new(CPUTLBEntry, new_size);
 +        desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
      }
  }
  static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
  {
--    tlb_mmu_resize_locked(env, mmu_idx);
+-    TCGv_vec t = tcg_temp_new_vec(type);
-+    tlb_mmu_resize_locked(&env_tlb(env)->d[mmu_idx], &env_tlb(env)->f[mmu_idx]);
++    TCGv_vec t;
-     env_tlb(env)->d[mmu_idx].n_used_entries = 0;
-     env_tlb(env)->d[mmu_idx].large_page_addr = -1;
++    if (have_avx512vbmi2) {
-     env_tlb(env)->d[mmu_idx].large_page_mask = -1;
++        vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec,
 +                  type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(sh));
 +        return;
 +    }
 +
 +    t = tcg_temp_new_vec(type);
      tcg_gen_dupi_vec(vece, t, 8 << vece);
      tcg_gen_sub_vec(vece, t, t, sh);
      if (right) {
 --
-.20.1
+.25.1

-New patch
+[PULL 16/30] tcg/i386: Remove rotls_vec from tcg_target_op_def
+There is no such instruction on x86, so we should
+not be pretending it has arguments.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/i386/tcg-target.c.inc | 1 -
+file changed, 1 deletion(-)
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/i386/tcg-target.c.inc
++++ b/tcg/i386/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_shls_vec:
+     case INDEX_op_shrs_vec:
+     case INDEX_op_sars_vec:
+-    case INDEX_op_rotls_vec:
+     case INDEX_op_cmp_vec:
+     case INDEX_op_x86_shufps_vec:
+     case INDEX_op_x86_blend_vec:
+--
+.25.1

-[PULL 13/16] cputlb: Partially merge tlb_dyn_init into tlb_init
+[PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns
-Merge into the only caller, but at the same time split
+Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V;
-out tlb_mmu_init to initialize a single tlb entry.
+expand 16-bit scalar rotate with VPSHLDV.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 33 ++++++++++++++++-----------------
+ tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++----------------
-file changed, 16 insertions(+), 17 deletions(-)
+file changed, 29 insertions(+), 20 deletions(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/i386/tcg-target.c.inc
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
+@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotli(TCGType type, unsigned vece,
-     desc->window_max_entries = max_entries;
+     tcg_temp_free_vec(t);
  }
--static void tlb_dyn_init(CPUArchState *env)
+-static void expand_vec_rotls(TCGType type, unsigned vece,
 -                             TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
 -{
--    int i;
+-    TCGv_i32 rsh;
 -    TCGv_vec t;
 -
--    for (i = 0; i < NB_MMU_MODES; i++) {
+-    tcg_debug_assert(vece != MO_8);
 -        CPUTLBDesc *desc = &env_tlb(env)->d[i];
 -        size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
 -
--        tlb_window_reset(desc, get_clock_realtime(), 0);
+-    t = tcg_temp_new_vec(type);
--        desc->n_used_entries = 0;
+-    rsh = tcg_temp_new_i32();
--        env_tlb(env)->f[i].mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
+-
--        env_tlb(env)->f[i].table = g_new(CPUTLBEntry, n_entries);
+-    tcg_gen_neg_i32(rsh, lsh);
--        env_tlb(env)->d[i].iotlb = g_new(CPUIOTLBEntry, n_entries);
+-    tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
--    }
+-    tcg_gen_shls_vec(vece, t, v1, lsh);
 -    tcg_gen_shrs_vec(vece, v0, v1, rsh);
 -    tcg_gen_or_vec(vece, v0, v0, t);
 -    tcg_temp_free_vec(t);
 -    tcg_temp_free_i32(rsh);
 -}
 -
- /**
+ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
-  * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
+                             TCGv_vec v1, TCGv_vec sh, bool right)
-  * @desc: The CPUTLBDesc portion of the TLB
+ {
-@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
+@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
-     tlb_mmu_flush_locked(desc, fast);
+     tcg_temp_free_vec(t);
  }
-+static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
++static void expand_vec_rotls(TCGType type, unsigned vece,
 +                             TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
 +{
-+    size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
++    TCGv_vec t = tcg_temp_new_vec(type);
 +
-+    tlb_window_reset(desc, now, 0);
++    tcg_debug_assert(vece != MO_8);
-+    desc->n_used_entries = 0;
++
-+    fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
++    if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) {
-+    fast->table = g_new(CPUTLBEntry, n_entries);
++        tcg_gen_dup_i32_vec(vece, t, lsh);
-+    desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
++        if (vece >= MO_32) {
 +            tcg_gen_rotlv_vec(vece, v0, v1, t);
 +        } else {
 +            expand_vec_rotv(type, vece, v0, v1, t, false);
 +        }
 +    } else {
 +        TCGv_i32 rsh = tcg_temp_new_i32();
 +
 +        tcg_gen_neg_i32(rsh, lsh);
 +        tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
 +        tcg_gen_shls_vec(vece, t, v1, lsh);
 +        tcg_gen_shrs_vec(vece, v0, v1, rsh);
 +        tcg_gen_or_vec(vece, v0, v0, t);
 +
 +        tcg_temp_free_i32(rsh);
 +    }
 +
 +    tcg_temp_free_vec(t);
 +}
 +
- static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
+ static void expand_vec_mul(TCGType type, unsigned vece,
                             TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
  {
-     env_tlb(env)->d[mmu_idx].n_used_entries++;
-@@ -XXX,XX +XXX,XX @@ static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx)
- void tlb_init(CPUState *cpu)
- {
-     CPUArchState *env = cpu->env_ptr;
-+    int64_t now = get_clock_realtime();
-+    int i;
-     qemu_spin_init(&env_tlb(env)->c.lock);
-     /* Ensure that cpu_reset performs a full flush.  */
-     env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;
--    tlb_dyn_init(env);
-+    for (i = 0; i < NB_MMU_MODES; i++) {
-+        tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);
-+    }
- }
- /* flush_all_helper: run fn across all cpus
 --
-.20.1
+.25.1

-[PULL 16/16] scripts/git.orderfile: Display decodetree before C source
+[PULL 18/30] tcg/i386: Implement avx512 min/max/abs
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ.
-To avoid scrolling each instruction when reviewing tcg
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 helpers written for the decodetree script, display the
 .decode files (similar to header declarations) before
 the C source (implementation of previous declarations).
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-Id: <20191230082856.30556-1-philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- scripts/git.orderfile | 3 +++
+ tcg/i386/tcg-target.c.inc | 18 +++++++++++-------
-file changed, 3 insertions(+)
+file changed, 11 insertions(+), 7 deletions(-)
-diff --git a/scripts/git.orderfile b/scripts/git.orderfile
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/scripts/git.orderfile
+--- a/tcg/i386/tcg-target.c.inc
-+++ b/scripts/git.orderfile
++++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ qga/*.json
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
- # headers
+ #define OPC_PABSB       (0x1c | P_EXT38 | P_DATA16)
- *.h
+ #define OPC_PABSW       (0x1d | P_EXT38 | P_DATA16)
+ #define OPC_PABSD       (0x1e | P_EXT38 | P_DATA16)
-+# decoding tree specification
++#define OPC_VPABSQ      (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
-+*.decode
+ #define OPC_PACKSSDW    (0x6b | P_EXT | P_DATA16)
-+
+ #define OPC_PACKSSWB    (0x63 | P_EXT | P_DATA16)
- # code
+ #define OPC_PACKUSDW    (0x2b | P_EXT38 | P_DATA16)
- *.c
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
  #define OPC_PMAXSB      (0x3c | P_EXT38 | P_DATA16)
  #define OPC_PMAXSW      (0xee | P_EXT | P_DATA16)
  #define OPC_PMAXSD      (0x3d | P_EXT38 | P_DATA16)
 +#define OPC_VPMAXSQ     (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
  #define OPC_PMAXUB      (0xde | P_EXT | P_DATA16)
  #define OPC_PMAXUW      (0x3e | P_EXT38 | P_DATA16)
  #define OPC_PMAXUD      (0x3f | P_EXT38 | P_DATA16)
 +#define OPC_VPMAXUQ     (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
  #define OPC_PMINSB      (0x38 | P_EXT38 | P_DATA16)
  #define OPC_PMINSW      (0xea | P_EXT | P_DATA16)
  #define OPC_PMINSD      (0x39 | P_EXT38 | P_DATA16)
 +#define OPC_VPMINSQ     (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
  #define OPC_PMINUB      (0xda | P_EXT | P_DATA16)
  #define OPC_PMINUW      (0x3a | P_EXT38 | P_DATA16)
  #define OPC_PMINUD      (0x3b | P_EXT38 | P_DATA16)
 +#define OPC_VPMINUQ     (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
  #define OPC_PMOVSXBW    (0x20 | P_EXT38 | P_DATA16)
  #define OPC_PMOVSXWD    (0x23 | P_EXT38 | P_DATA16)
  #define OPC_PMOVSXDQ    (0x25 | P_EXT38 | P_DATA16)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
          OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
      };
      static int const smin_insn[4] = {
 -        OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2
 +        OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ
      };
      static int const smax_insn[4] = {
 -        OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2
 +        OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ
      };
      static int const umin_insn[4] = {
 -        OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2
 +        OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ
      };
      static int const umax_insn[4] = {
 -        OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
 +        OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ
      };
      static int const rotlv_insn[4] = {
          OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
          OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ
      };
      static int const abs_insn[4] = {
 -        /* TODO: AVX512 adds support for MO_64.  */
 -        OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
 +        OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ
      };
      TCGType type = vecl + TCG_TYPE_V64;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_umin_vec:
      case INDEX_op_umax_vec:
      case INDEX_op_abs_vec:
 -        return vece <= MO_32;
 +        return vece <= MO_32 || have_avx512vl;
      default:
          return 0;
 --
-.20.1
+.25.1

-[PULL 11/16] cputlb: Hoist tlb portions in tlb_flush_one_mmuidx_locked
+[PULL 19/30] tcg/i386: Implement avx512 multiply
-No functional change, but the smaller expressions make
+AVX512DQ has VPMULLQ.
 the code easier to read.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 19 ++++++++++---------
+ tcg/i386/tcg-target.c.inc | 12 ++++++------
-file changed, 10 insertions(+), 9 deletions(-)
+file changed, 6 insertions(+), 6 deletions(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/i386/tcg-target.c.inc
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ #define OPC_PMOVZXDQ    (0x35 | P_EXT38 | P_DATA16)
- static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
+ #define OPC_PMULLW      (0xd5 | P_EXT | P_DATA16)
- {
+ #define OPC_PMULLD      (0x40 | P_EXT38 | P_DATA16)
--    tlb_mmu_resize_locked(&env_tlb(env)->d[mmu_idx], &env_tlb(env)->f[mmu_idx]);
++#define OPC_VPMULLQ     (0x40 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
--    env_tlb(env)->d[mmu_idx].n_used_entries = 0;
+ #define OPC_POR         (0xeb | P_EXT | P_DATA16)
--    env_tlb(env)->d[mmu_idx].large_page_addr = -1;
+ #define OPC_PSHUFB      (0x00 | P_EXT38 | P_DATA16)
--    env_tlb(env)->d[mmu_idx].large_page_mask = -1;
+ #define OPC_PSHUFD      (0x70 | P_EXT | P_DATA16)
--    env_tlb(env)->d[mmu_idx].vindex = 0;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
--    memset(env_tlb(env)->f[mmu_idx].table, -1,
+         OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2
--           sizeof_tlb(&env_tlb(env)->f[mmu_idx]));
+     };
--    memset(env_tlb(env)->d[mmu_idx].vtable, -1,
+     static int const mul_insn[4] = {
--           sizeof(env_tlb(env)->d[0].vtable));
+-        OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
-+    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
++        OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_VPMULLQ
-+    CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
+     };
-+
+     static int const shift_imm_insn[4] = {
-+    tlb_mmu_resize_locked(desc, fast);
+         OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
-+    desc->n_used_entries = 0;
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-+    desc->large_page_addr = -1;
+         return 0;
-+    desc->large_page_mask = -1;
-+    desc->vindex = 0;
+     case INDEX_op_mul_vec:
-+    memset(fast->table, -1, sizeof_tlb(fast));
+-        if (vece == MO_8) {
-+    memset(desc->vtable, -1, sizeof(desc->vtable));
+-            /* We can expand the operation for MO_8.  */
- }
++        switch (vece) {
++        case MO_8:
- static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
+             return -1;
 -        }
 -        if (vece == MO_64) {
 -            return 0;
 +        case MO_64:
 +            return have_avx512dq;
          }
          return 1;
 --
-.20.1
+.25.1

-[PULL 09/16] cputlb: Pass CPUTLBDescFast to tlb_n_entries and sizeof_tlb
+[PULL 20/30] tcg/i386: Implement more logical operations for avx512
-We do not need the entire CPUArchState to compute these values.
+AVX512VL has a general ternary logic operation, VPTERNLOGQ,
 which can implement NOT, ORC, NAND, NOR, EQV.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 15 ++++++++-------
+ tcg/i386/tcg-target.h     | 10 +++++-----
-file changed, 8 insertions(+), 7 deletions(-)
+ tcg/i386/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
 files changed, 39 insertions(+), 5 deletions(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/i386/tcg-target.h
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
+@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
- QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
+ #define TCG_TARGET_HAS_v256             have_avx2
- #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
+ #define TCG_TARGET_HAS_andc_vec         1
--static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
+-#define TCG_TARGET_HAS_orc_vec          0
-+static inline size_t tlb_n_entries(CPUTLBDescFast *fast)
+-#define TCG_TARGET_HAS_nand_vec         0
- {
+-#define TCG_TARGET_HAS_nor_vec          0
--    return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
+-#define TCG_TARGET_HAS_eqv_vec          0
-+    return (fast->mask >> CPU_TLB_ENTRY_BITS) + 1;
+-#define TCG_TARGET_HAS_not_vec          0
- }
++#define TCG_TARGET_HAS_orc_vec          have_avx512vl
++#define TCG_TARGET_HAS_nand_vec         have_avx512vl
--static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
++#define TCG_TARGET_HAS_nor_vec          have_avx512vl
-+static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
++#define TCG_TARGET_HAS_eqv_vec          have_avx512vl
- {
++#define TCG_TARGET_HAS_not_vec          have_avx512vl
--    return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS);
+ #define TCG_TARGET_HAS_neg_vec          0
-+    return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
+ #define TCG_TARGET_HAS_abs_vec          1
- }
+ #define TCG_TARGET_HAS_roti_vec         have_avx512vl
+diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
- static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)
+--- a/tcg/i386/tcg-target.c.inc
- static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
++++ b/tcg/i386/tcg-target.c.inc
- {
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
+ #define OPC_VPSRLVW     (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
--    size_t old_size = tlb_n_entries(env, mmu_idx);
+ #define OPC_VPSRLVD     (0x45 | P_EXT38 | P_DATA16)
-+    size_t old_size = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);
+ #define OPC_VPSRLVQ     (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
-     size_t rate;
++#define OPC_VPTERNLOGQ  (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
-     size_t new_size = old_size;
+ #define OPC_VZEROUPPER  (0x77 | P_EXT)
-     int64_t now = get_clock_realtime();
+ #define OPC_XCHG_ax_r32    (0x90)
-@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
-     env_tlb(env)->d[mmu_idx].large_page_addr = -1;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-     env_tlb(env)->d[mmu_idx].large_page_mask = -1;
+         insn = vpshldi_insn[vece];
-     env_tlb(env)->d[mmu_idx].vindex = 0;
+         sub = args[3];
--    memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
+         goto gen_simd_imm8;
-+    memset(env_tlb(env)->f[mmu_idx].table, -1,
++
-+           sizeof_tlb(&env_tlb(env)->f[mmu_idx]));
++    case INDEX_op_not_vec:
-     memset(env_tlb(env)->d[mmu_idx].vtable, -1,
++        insn = OPC_VPTERNLOGQ;
-            sizeof(env_tlb(env)->d[0].vtable));
++        a2 = a1;
- }
++        sub = 0x33; /* !B */
-@@ -XXX,XX +XXX,XX @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
++        goto gen_simd_imm8;
-     qemu_spin_lock(&env_tlb(env)->c.lock);
++    case INDEX_op_nor_vec:
-     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
++        insn = OPC_VPTERNLOGQ;
-         unsigned int i;
++        sub = 0x11; /* norCB */
--        unsigned int n = tlb_n_entries(env, mmu_idx);
++        goto gen_simd_imm8;
-+        unsigned int n = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);
++    case INDEX_op_nand_vec:
++        insn = OPC_VPTERNLOGQ;
-         for (i = 0; i < n; i++) {
++        sub = 0x77; /* nandCB */
-             tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i],
++        goto gen_simd_imm8;
 +    case INDEX_op_eqv_vec:
 +        insn = OPC_VPTERNLOGQ;
 +        sub = 0x99; /* xnorCB */
 +        goto gen_simd_imm8;
 +    case INDEX_op_orc_vec:
 +        insn = OPC_VPTERNLOGQ;
 +        sub = 0xdd; /* orB!C */
 +        goto gen_simd_imm8;
 +
      gen_simd_imm8:
          tcg_debug_assert(insn != OPC_UD2);
          if (type == TCG_TYPE_V256) {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_or_vec:
      case INDEX_op_xor_vec:
      case INDEX_op_andc_vec:
 +    case INDEX_op_orc_vec:
 +    case INDEX_op_nand_vec:
 +    case INDEX_op_nor_vec:
 +    case INDEX_op_eqv_vec:
      case INDEX_op_ssadd_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_sssub_vec:
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_abs_vec:
      case INDEX_op_dup_vec:
 +    case INDEX_op_not_vec:
      case INDEX_op_shli_vec:
      case INDEX_op_shri_vec:
      case INDEX_op_sari_vec:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_or_vec:
      case INDEX_op_xor_vec:
      case INDEX_op_andc_vec:
 +    case INDEX_op_orc_vec:
 +    case INDEX_op_nand_vec:
 +    case INDEX_op_nor_vec:
 +    case INDEX_op_eqv_vec:
 +    case INDEX_op_not_vec:
          return 1;
      case INDEX_op_cmp_vec:
      case INDEX_op_cmpsel_vec:
 --
-.20.1
+.25.1

-[PULL 05/16] vl: Remove useless test in configure_accelerators
+[PULL 21/30] tcg/i386: Implement bitsel for avx512
-The result of g_strsplit is never NULL.
+The general ternary logic operation can implement BITSEL.
 Funnel the 4-operand operation into three variants of the
 -operand instruction, depending on input operand overlap.
-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- vl.c | 2 +-
+ tcg/i386/tcg-target.h     |  2 +-
-file changed, 1 insertion(+), 1 deletion(-)
+ tcg/i386/tcg-target.c.inc | 20 +++++++++++++++++++-
 files changed, 20 insertions(+), 2 deletions(-)
-diff --git a/vl.c b/vl.c
+diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
---- a/vl.c
+--- a/tcg/i386/tcg-target.h
-+++ b/vl.c
++++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
+@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
+ #define TCG_TARGET_HAS_mul_vec          1
-         accel_list = g_strsplit(accel, ":", 0);
+ #define TCG_TARGET_HAS_sat_vec          1
+ #define TCG_TARGET_HAS_minmax_vec       1
--        for (tmp = accel_list; tmp && *tmp; tmp++) {
+-#define TCG_TARGET_HAS_bitsel_vec       0
-+        for (tmp = accel_list; *tmp; tmp++) {
++#define TCG_TARGET_HAS_bitsel_vec       have_avx512vl
-             /*
+ #define TCG_TARGET_HAS_cmpsel_vec       -1
-              * Filter invalid accelerators here, to prevent obscenities
-              * such as "-machine accel=tcg,,thread=single".
+ #define TCG_TARGET_deposit_i32_valid(ofs, len) \
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      TCGType type = vecl + TCG_TYPE_V64;
      int insn, sub;
 -    TCGArg a0, a1, a2;
 +    TCGArg a0, a1, a2, a3;
      a0 = args[0];
      a1 = args[1];
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
          sub = 0xdd; /* orB!C */
          goto gen_simd_imm8;
 +    case INDEX_op_bitsel_vec:
 +        insn = OPC_VPTERNLOGQ;
 +        a3 = args[3];
 +        if (a0 == a1) {
 +            a1 = a2;
 +            a2 = a3;
 +            sub = 0xca; /* A?B:C */
 +        } else if (a0 == a2) {
 +            a2 = a3;
 +            sub = 0xe2; /* B?A:C */
 +        } else {
 +            tcg_out_mov(s, type, a0, a3);
 +            sub = 0xb8; /* B?C:A */
 +        }
 +        goto gen_simd_imm8;
 +
      gen_simd_imm8:
          tcg_debug_assert(insn != OPC_UD2);
          if (type == TCG_TYPE_V256) {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_x86_vpshrdv_vec:
          return C_O1_I3(x, 0, x, x);
 +    case INDEX_op_bitsel_vec:
      case INDEX_op_x86_vpblendvb_vec:
          return C_O1_I3(x, x, x, x);
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_nor_vec:
      case INDEX_op_eqv_vec:
      case INDEX_op_not_vec:
 +    case INDEX_op_bitsel_vec:
          return 1;
      case INDEX_op_cmp_vec:
      case INDEX_op_cmpsel_vec:
 --
-.20.1
+.25.1

-[PULL 04/16] vl: Reduce scope of variables in configure_accelerators
+[PULL 22/30] tcg: Add TCG_TARGET_SIGNED_ADDR32
-The accel_list and tmp variables are only used when manufacturing
+Define as 0 for all tcg hosts.  Put this in a separate header,
--machine accel, options based on -accel.
+because we'll want this in places that do not ordinarily have
 access to all of tcg/tcg.h.
-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
+Reviewed-by: WANG Xuerui <git@xen0n.name>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- vl.c | 3 ++-
+ tcg/aarch64/tcg-target-sa32.h     | 1 +
-file changed, 2 insertions(+), 1 deletion(-)
+ tcg/arm/tcg-target-sa32.h         | 1 +
  tcg/i386/tcg-target-sa32.h        | 1 +
  tcg/loongarch64/tcg-target-sa32.h | 1 +
  tcg/mips/tcg-target-sa32.h        | 1 +
  tcg/ppc/tcg-target-sa32.h         | 1 +
  tcg/riscv/tcg-target-sa32.h       | 1 +
  tcg/s390x/tcg-target-sa32.h       | 1 +
  tcg/sparc/tcg-target-sa32.h       | 1 +
  tcg/tci/tcg-target-sa32.h         | 1 +
  tcg/tcg.c                         | 4 ++++
 files changed, 14 insertions(+)
  create mode 100644 tcg/aarch64/tcg-target-sa32.h
  create mode 100644 tcg/arm/tcg-target-sa32.h
  create mode 100644 tcg/i386/tcg-target-sa32.h
  create mode 100644 tcg/loongarch64/tcg-target-sa32.h
  create mode 100644 tcg/mips/tcg-target-sa32.h
  create mode 100644 tcg/ppc/tcg-target-sa32.h
  create mode 100644 tcg/riscv/tcg-target-sa32.h
  create mode 100644 tcg/s390x/tcg-target-sa32.h
  create mode 100644 tcg/sparc/tcg-target-sa32.h
  create mode 100644 tcg/tci/tcg-target-sa32.h
-diff --git a/vl.c b/vl.c
+diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/aarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/arm/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/i386/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/loongarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/mips/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/ppc/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/riscv/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/s390x/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/sparc/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/tci/tcg-target-sa32.h
@@ -0,0 +1 @@
 +#define TCG_TARGET_SIGNED_ADDR32 0
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
---- a/vl.c
+--- a/tcg/tcg.c
-+++ b/vl.c
++++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static int do_configure_accelerator(void *opaque, QemuOpts *opts, Error **errp)
+@@ -XXX,XX +XXX,XX @@
- static void configure_accelerators(const char *progname)
+ #include "exec/log.h"
- {
+ #include "tcg/tcg-ldst.h"
-     const char *accel;
+ #include "tcg-internal.h"
--    char **accel_list, **tmp;
++#include "tcg-target-sa32.h"
      bool init_failed = false;
      qemu_opts_foreach(qemu_find_opts("icount"),
@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
      accel = qemu_opt_get(qemu_get_machine_opts(), "accel");
      if (QTAILQ_EMPTY(&qemu_accel_opts.head)) {
 +        char **accel_list, **tmp;
 +
-         if (accel == NULL) {
++/* Sanity check for TCG_TARGET_SIGNED_ADDR32. */
-             /* Select the default accelerator */
++QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS == 32 && TCG_TARGET_SIGNED_ADDR32);
-             if (!accel_find("tcg") && !accel_find("kvm")) {
  #ifdef CONFIG_TCG_INTERPRETER
  #include <ffi.h>
 --
-.20.1
+.25.1

-[PULL 07/16] cputlb: Merge tlb_table_flush_by_mmuidx into tlb_flush_one_mmuidx_locked
+[PULL 23/30] accel/tcg: Split out g2h_tlbe
-There is only one caller for tlb_table_flush_by_mmuidx.  Place
+Create a new function to combine a CPUTLBEntry addend
-the result at the earlier line number, due to an expected user
+with the guest address to form a host address.
 in the near future.
+Reviewed-by: WANG Xuerui <git@xen0n.name>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 19 +++++++------------
+ accel/tcg/cputlb.c | 24 ++++++++++++++----------
-file changed, 7 insertions(+), 12 deletions(-)
+file changed, 14 insertions(+), 10 deletions(-)
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/cputlb.c
 +++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
+@@ -XXX,XX +XXX,XX @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
      return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
  }
 +static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
 +{
 +    return tlb->addend + (uintptr_t)gaddr;
 +}
 +
  static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
                               size_t max_entries)
  {
@@ -XXX,XX +XXX,XX @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
      if ((addr & (TLB_INVALID_MASK | TLB_MMIO |
                   TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) {
 -        addr &= TARGET_PAGE_MASK;
 -        addr += tlb_entry->addend;
 +        addr = g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK);
          if ((addr - start) < length) {
  #if TCG_OVERSIZED_GUEST
              tlb_entry->addr_write |= TLB_NOTDIRTY;
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
          return -1;
      }
+-    p = (void *)((uintptr_t)addr + entry->addend);
++    p = (void *)g2h_tlbe(entry, addr);
+     if (hostp) {
+         *hostp = p;
+     }
+@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
+     }
+     /* Everything else is RAM. */
+-    *phost = (void *)((uintptr_t)addr + entry->addend);
++    *phost = (void *)g2h_tlbe(entry, addr);
+     return flags;
  }
--static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx)
+@@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
-+static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
+             data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
- {
+         } else {
-     tlb_mmu_resize_locked(env, mmu_idx);
+             data->is_io = false;
--    memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
+-            data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
-     env_tlb(env)->d[mmu_idx].n_used_entries = 0;
++            data->v.ram.hostaddr = (void *)g2h_tlbe(tlbe, addr);
-+    env_tlb(env)->d[mmu_idx].large_page_addr = -1;
+         }
-+    env_tlb(env)->d[mmu_idx].large_page_mask = -1;
+         return true;
-+    env_tlb(env)->d[mmu_idx].vindex = 0;
+     } else {
-+    memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
+@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
-+    memset(env_tlb(env)->d[mmu_idx].vtable, -1,
+         goto stop_the_world;
-+           sizeof(env_tlb(env)->d[0].vtable));
+     }
 -    hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
 +    hostaddr = (void *)g2h_tlbe(tlbe, addr);
      if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
          notdirty_write(env_cpu(env), addr, size,
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
                              access_type, op ^ (need_swap * MO_BSWAP));
          }
 -        haddr = (void *)((uintptr_t)addr + entry->addend);
 +        haddr = (void *)g2h_tlbe(entry, addr);
          /*
           * Keep these two load_memop separate to ensure that the compiler
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
          return res & MAKE_64BIT_MASK(0, size * 8);
      }
 -    haddr = (void *)((uintptr_t)addr + entry->addend);
 +    haddr = (void *)g2h_tlbe(entry, addr);
      return load_memop(haddr, op);
  }
- static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
+@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
-@@ -XXX,XX +XXX,XX @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide)
+             notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
-     *pelide = elide;
+         }
 -        haddr = (void *)((uintptr_t)addr + entry->addend);
 +        haddr = (void *)g2h_tlbe(entry, addr);
          /*
           * Keep these two store_memop separate to ensure that the compiler
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
          return;
      }
 -    haddr = (void *)((uintptr_t)addr + entry->addend);
 +    haddr = (void *)g2h_tlbe(entry, addr);
      store_memop(haddr, val, op);
  }
--static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
--{
--    tlb_table_flush_by_mmuidx(env, mmu_idx);
--    env_tlb(env)->d[mmu_idx].large_page_addr = -1;
--    env_tlb(env)->d[mmu_idx].large_page_mask = -1;
--    env_tlb(env)->d[mmu_idx].vindex = 0;
--    memset(env_tlb(env)->d[mmu_idx].vtable, -1,
--           sizeof(env_tlb(env)->d[0].vtable));
--}
--
- static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
- {
-     CPUArchState *env = cpu->env_ptr;
 --
-.20.1
+.25.1

-[PULL 01/16] cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN
+[PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
-In target/arm we will shortly have "too many" mmu_idx.
+When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
-The current minimum barrier is caused by the way in which
+allow the 32-bit guest address to be sign extended within the
-tlb_flush_page_by_mmuidx is coded.
+-bit host register instead of zero extended.
-We can remove this limitation by allocating memory for
+This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
-consumption by the worker.  Let us assume that this is
+which naturally sign-extend 32-bit values, in contrast to x86_64
-the unlikely case, as will be the case for the majority
+and AArch64 which zero-extend them.
 of targets which have so far satisfied the BUILD_BUG_ON,
 and only allocate memory when necessary.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 167 +++++++++++++++++++++++++++++++++++----------
+ accel/tcg/cputlb.c | 12 +++++++++++-
-file changed, 132 insertions(+), 35 deletions(-)
+file changed, 11 insertions(+), 1 deletion(-)
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/cputlb.c
 +++ b/accel/tcg/cputlb.c
-@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,
+@@ -XXX,XX +XXX,XX @@
-     }
+ #include "qemu/plugin-memory.h"
  #endif
  #include "tcg/tcg-ldst.h"
 +#include "tcg-target-sa32.h"
  /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
  /* #define DEBUG_TLB */
@@ -XXX,XX +XXX,XX @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
  static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
  {
 +    if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
 +        return tlb->addend + (int32_t)gaddr;
 +    }
      return tlb->addend + (uintptr_t)gaddr;
  }
--/* As we are going to hijack the bottom bits of the page address for a
+@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
-- * mmuidx bit mask we need to fail to build if we can't do that
+     desc->iotlb[index].attrs = attrs;
-+/**
-+ * tlb_flush_page_by_mmuidx_async_0:
+     /* Now calculate the new entry */
-+ * @cpu: cpu on which to flush
+-    tn.addend = addend - vaddr_page;
 + * @addr: page of virtual address to flush
 + * @idxmap: set of mmu_idx to flush
 + *
 + * Helper for tlb_flush_page_by_mmuidx and friends, flush one page
 + * at @addr from the tlbs indicated by @idxmap from @cpu.
   */
 -QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN);
 -
 -static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
 -                                                run_on_cpu_data data)
 +static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,
 +                                             target_ulong addr,
 +                                             uint16_t idxmap)
  {
      CPUArchState *env = cpu->env_ptr;
 -    target_ulong addr_and_mmuidx = (target_ulong) data.target_ptr;
 -    target_ulong addr = addr_and_mmuidx & TARGET_PAGE_MASK;
 -    unsigned long mmu_idx_bitmap = addr_and_mmuidx & ALL_MMUIDX_BITS;
      int mmu_idx;
      assert_cpu_is_self(cpu);
 -    tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n",
 -              addr, mmu_idx_bitmap);
 +    tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%x\n", addr, idxmap);
      qemu_spin_lock(&env_tlb(env)->c.lock);
      for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
 -        if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
 +        if ((idxmap >> mmu_idx) & 1) {
              tlb_flush_page_locked(env, mmu_idx, addr);
          }
      }
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
      tb_flush_jmp_cache(cpu, addr);
  }
 +/**
 + * tlb_flush_page_by_mmuidx_async_1:
 + * @cpu: cpu on which to flush
 + * @data: encoded addr + idxmap
 + *
 + * Helper for tlb_flush_page_by_mmuidx and friends, called through
 + * async_run_on_cpu.  The idxmap parameter is encoded in the page
 + * offset of the target_ptr field.  This limits the set of mmu_idx
 + * that can be passed via this method.
 + */
 +static void tlb_flush_page_by_mmuidx_async_1(CPUState *cpu,
 +                                             run_on_cpu_data data)
 +{
 +    target_ulong addr_and_idxmap = (target_ulong) data.target_ptr;
 +    target_ulong addr = addr_and_idxmap & TARGET_PAGE_MASK;
 +    uint16_t idxmap = addr_and_idxmap & ~TARGET_PAGE_MASK;
 +
-+    tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap);
++    if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
-+}
++        tn.addend = addend - (int32_t)vaddr_page;
 +
 +typedef struct {
 +    target_ulong addr;
 +    uint16_t idxmap;
 +} TLBFlushPageByMMUIdxData;
 +
 +/**
 + * tlb_flush_page_by_mmuidx_async_2:
 + * @cpu: cpu on which to flush
 + * @data: allocated addr + idxmap
 + *
 + * Helper for tlb_flush_page_by_mmuidx and friends, called through
 + * async_run_on_cpu.  The addr+idxmap parameters are stored in a
 + * TLBFlushPageByMMUIdxData structure that has been allocated
 + * specifically for this helper.  Free the structure when done.
 + */
 +static void tlb_flush_page_by_mmuidx_async_2(CPUState *cpu,
 +                                             run_on_cpu_data data)
 +{
 +    TLBFlushPageByMMUIdxData *d = data.host_ptr;
 +
 +    tlb_flush_page_by_mmuidx_async_0(cpu, d->addr, d->idxmap);
 +    g_free(d);
 +}
 +
  void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap)
  {
 -    target_ulong addr_and_mmu_idx;
 -
      tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%" PRIx16 "\n", addr, idxmap);
      /* This should already be page aligned */
 -    addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
 -    addr_and_mmu_idx |= idxmap;
 +    addr &= TARGET_PAGE_MASK;
 -    if (!qemu_cpu_is_self(cpu)) {
 -        async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work,
 -                         RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
 +    if (qemu_cpu_is_self(cpu)) {
 +        tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap);
 +    } else if (idxmap < TARGET_PAGE_SIZE) {
 +        /*
 +         * Most targets have only a few mmu_idx.  In the case where
 +         * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid
 +         * allocating memory for this operation.
 +         */
 +        async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_1,
 +                         RUN_ON_CPU_TARGET_PTR(addr | idxmap));
      } else {
 -        tlb_flush_page_by_mmuidx_async_work(
 -            cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
 +        TLBFlushPageByMMUIdxData *d = g_new(TLBFlushPageByMMUIdxData, 1);
 +
 +        /* Otherwise allocate a structure, freed by the worker.  */
 +        d->addr = addr;
 +        d->idxmap = idxmap;
 +        async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_2,
 +                         RUN_ON_CPU_HOST_PTR(d));
      }
  }
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
  void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr,
                                         uint16_t idxmap)
  {
 -    const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work;
 -    target_ulong addr_and_mmu_idx;
 -
      tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap);
      /* This should already be page aligned */
 -    addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
 -    addr_and_mmu_idx |= idxmap;
 +    addr &= TARGET_PAGE_MASK;
 -    flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
 -    fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
 +    /*
 +     * Allocate memory to hold addr+idxmap only when needed.
 +     * See tlb_flush_page_by_mmuidx for details.
 +     */
 +    if (idxmap < TARGET_PAGE_SIZE) {
 +        flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1,
 +                         RUN_ON_CPU_TARGET_PTR(addr | idxmap));
 +    } else {
-+        CPUState *dst_cpu;
++        tn.addend = addend - vaddr_page;
 +
 +        /* Allocate a separate data block for each destination cpu.  */
 +        CPU_FOREACH(dst_cpu) {
 +            if (dst_cpu != src_cpu) {
 +                TLBFlushPageByMMUIdxData *d
 +                    = g_new(TLBFlushPageByMMUIdxData, 1);
 +
 +                d->addr = addr;
 +                d->idxmap = idxmap;
 +                async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2,
 +                                 RUN_ON_CPU_HOST_PTR(d));
 +            }
 +        }
 +    }
 +
-+    tlb_flush_page_by_mmuidx_async_0(src_cpu, addr, idxmap);
+     if (prot & PAGE_READ) {
- }
+         tn.addr_read = address;
+         if (wp_flags & BP_MEM_READ) {
  void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
                                                target_ulong addr,
                                                uint16_t idxmap)
  {
 -    const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work;
 -    target_ulong addr_and_mmu_idx;
 -
      tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap);
      /* This should already be page aligned */
 -    addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
 -    addr_and_mmu_idx |= idxmap;
 +    addr &= TARGET_PAGE_MASK;
 -    flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
 -    async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
 +    /*
 +     * Allocate memory to hold addr+idxmap only when needed.
 +     * See tlb_flush_page_by_mmuidx for details.
 +     */
 +    if (idxmap < TARGET_PAGE_SIZE) {
 +        flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1,
 +                         RUN_ON_CPU_TARGET_PTR(addr | idxmap));
 +        async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_1,
 +                              RUN_ON_CPU_TARGET_PTR(addr | idxmap));
 +    } else {
 +        CPUState *dst_cpu;
 +        TLBFlushPageByMMUIdxData *d;
 +
 +        /* Allocate a separate data block for each destination cpu.  */
 +        CPU_FOREACH(dst_cpu) {
 +            if (dst_cpu != src_cpu) {
 +                d = g_new(TLBFlushPageByMMUIdxData, 1);
 +                d->addr = addr;
 +                d->idxmap = idxmap;
 +                async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2,
 +                                 RUN_ON_CPU_HOST_PTR(d));
 +            }
 +        }
 +
 +        d = g_new(TLBFlushPageByMMUIdxData, 1);
 +        d->addr = addr;
 +        d->idxmap = idxmap;
 +        async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_2,
 +                              RUN_ON_CPU_HOST_PTR(d));
 +    }
  }
  void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr)
 --
-.20.1
+.25.1

-[PULL 08/16] cputlb: Make tlb_n_entries private to cputlb.c
+[PULL 25/30] accel/tcg: Add guest_base_signed_addr32 for user-only
-There are no users of this function outside cputlb.c,
+While the host may prefer to treat 32-bit addresses as signed,
-and its interface will change in the next patch.
+there are edge cases of guests that cannot be implemented with
 addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Therefore, default to guest_base_signed_addr32 false, and allow
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+probe_guest_base to determine whether it is possible to set it
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+to true.  A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will
 have to cope with either setting for user-only.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/exec/cpu_ldst.h | 5 -----
+ include/exec/cpu-all.h  | 16 ++++++++++++++++
- accel/tcg/cputlb.c      | 5 +++++
+ include/exec/cpu_ldst.h |  3 ++-
-files changed, 5 insertions(+), 5 deletions(-)
+ bsd-user/main.c         |  4 ++++
  linux-user/main.c       |  3 +++
 files changed, 25 insertions(+), 1 deletion(-)
+diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/exec/cpu-all.h
++++ b/include/exec/cpu-all.h
+@@ -XXX,XX +XXX,XX @@ static inline void tswap64s(uint64_t *s)
+ #if defined(CONFIG_USER_ONLY)
+ #include "exec/user/abitypes.h"
++#include "tcg-target-sa32.h"
+ /* On some host systems the guest address space is reserved on the host.
+  * This allows the guest address space to be offset to a convenient location.
+@@ -XXX,XX +XXX,XX @@ extern uintptr_t guest_base;
+ extern bool have_guest_base;
+ extern unsigned long reserved_va;
++#if TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32
++extern bool guest_base_signed_addr32;
++#else
++#define guest_base_signed_addr32  false
++#endif
++
++static inline void set_guest_base_signed_addr32(void)
++{
++#ifdef guest_base_signed_addr32
++    qemu_build_not_reached();
++#else
++    guest_base_signed_addr32 = true;
++#endif
++}
++
+ /*
+  * Limit the guest addresses as best we can.
+  *
 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/exec/cpu_ldst.h
 +++ b/include/exec/cpu_ldst.h
-@@ -XXX,XX +XXX,XX @@ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
+@@ -XXX,XX +XXX,XX @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)
-     return (addr >> TARGET_PAGE_BITS) & size_mask;
+ /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
  static inline void *g2h_untagged(abi_ptr x)
  {
 -    return (void *)((uintptr_t)(x) + guest_base);
 +    uintptr_t hx = guest_base_signed_addr32 ? (int32_t)x : (uintptr_t)x;
 +    return (void *)(guest_base + hx);
  }
--static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
+ static inline void *g2h(CPUState *cs, abi_ptr x)
--{
+diff --git a/bsd-user/main.c b/bsd-user/main.c
 -    return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
 -}
 -
  /* Find the TLB entry corresponding to the mmu_idx + address pair.  */
  static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
                                       target_ulong addr)
 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/bsd-user/main.c
-+++ b/accel/tcg/cputlb.c
++++ b/bsd-user/main.c
-@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
+@@ -XXX,XX +XXX,XX @@
- QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
+ int singlestep;
- #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
+ uintptr_t guest_base;
+ bool have_guest_base;
-+static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
++#ifndef guest_base_signed_addr32
-+{
++bool guest_base_signed_addr32;
-+    return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
++#endif
 +}
 +
- static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
+ /*
- {
+  * When running 32-on-64 we should make sure we can fit all of the possible
-     return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS);
+  * guest address space into a contiguous chunk of virtual host memory.
 diff --git a/linux-user/main.c b/linux-user/main.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/main.c
 +++ b/linux-user/main.c
@@ -XXX,XX +XXX,XX @@ static const char *seed_optarg;
  unsigned long mmap_min_addr;
  uintptr_t guest_base;
  bool have_guest_base;
 +#ifndef guest_base_signed_addr32
 +bool guest_base_signed_addr32;
 +#endif
  /*
   * Used to implement backwards-compatibility for the `-strace`, and
 --
-.20.1
+.25.1

-[PULL 03/16] vl: Remove unused variable in configure_accelerators
+[PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32
-The accel_initialised variable no longer has any setters.
+When using reserved_va, which is the default for a 64-bit host
 and a 32-bit guest, set guest_base_signed_addr32 if requested
 by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows.
-Fixes: 6f6e1698a68c
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Acked-by: Paolo Bonzini <pbonzini@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- vl.c | 3 +--
+ include/exec/cpu-all.h |  4 ---
-file changed, 1 insertion(+), 2 deletions(-)
+ linux-user/elfload.c   | 62 ++++++++++++++++++++++++++++++++++--------
 files changed, 50 insertions(+), 16 deletions(-)
-diff --git a/vl.c b/vl.c
+diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
 index XXXXXXX..XXXXXXX 100644
---- a/vl.c
+--- a/include/exec/cpu-all.h
-+++ b/vl.c
++++ b/include/exec/cpu-all.h
-@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
+@@ -XXX,XX +XXX,XX @@ extern const TargetPageBits target_page;
  #define PAGE_RESET     0x0040
  /* For linux-user, indicates that the page is MAP_ANON. */
  #define PAGE_ANON      0x0080
 -
 -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
 -/* FIXME: Code that sets/uses this is broken and needs to go away.  */
  #define PAGE_RESERVED  0x0100
 -#endif
  /* Target-specific bits that will be used via page_get_flags().  */
  #define PAGE_TARGET_1  0x0200
  #define PAGE_TARGET_2  0x0400
 diff --git a/linux-user/elfload.c b/linux-user/elfload.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/elfload.c
 +++ b/linux-user/elfload.c
@@ -XXX,XX +XXX,XX @@ static void pgb_dynamic(const char *image_name, long align)
  static void pgb_reserved_va(const char *image_name, abi_ulong guest_loaddr,
                              abi_ulong guest_hiaddr, long align)
  {
-     const char *accel;
+-    int flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE;
-     char **accel_list, **tmp;
++    int flags = (MAP_ANONYMOUS | MAP_PRIVATE |
--    bool accel_initialised = false;
++                 MAP_NORESERVE | MAP_FIXED_NOREPLACE);
-     bool init_failed = false;
++    unsigned long local_rva = reserved_va;
++    bool protect_wrap = false;
-     qemu_opts_foreach(qemu_find_opts("icount"),
+     void *addr, *test;
-@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
+-    if (guest_hiaddr > reserved_va) {
-         accel_list = g_strsplit(accel, ":", 0);
++    if (guest_hiaddr > local_rva) {
+         error_report("%s: requires more than reserved virtual "
--        for (tmp = accel_list; !accel_initialised && tmp && *tmp; tmp++) {
+                      "address space (0x%" PRIx64 " > 0x%lx)",
-+        for (tmp = accel_list; tmp && *tmp; tmp++) {
+-                     image_name, (uint64_t)guest_hiaddr, reserved_va);
-             /*
++                     image_name, (uint64_t)guest_hiaddr, local_rva);
-              * Filter invalid accelerators here, to prevent obscenities
+         exit(EXIT_FAILURE);
-              * such as "-machine accel=tcg,,thread=single".
+     }
 -    /* Widen the "image" to the entire reserved address space. */
 -    pgb_static(image_name, 0, reserved_va, align);
 +    if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
 +        if (guest_loaddr < 0x80000000u && guest_hiaddr > 0x80000000u) {
 +            /*
 +             * The executable itself wraps on signed addresses.
 +             * Without per-page translation, we must keep the
 +             * guest address 0x7fff_ffff adjacent to 0x8000_0000
 +             * consecutive in host memory: unsigned addresses.
 +             */
 +        } else {
 +            set_guest_base_signed_addr32();
 +            if (local_rva <= 0x80000000u) {
 +                /* No guest addresses are "negative": win! */
 +            } else {
 +                /* Begin by allocating the entire address space. */
 +                local_rva = 0xfffffffful + 1;
 +                protect_wrap = true;
 +            }
 +        }
 +    }
 -    /* osdep.h defines this as 0 if it's missing */
 -    flags |= MAP_FIXED_NOREPLACE;
 +    /* Widen the "image" to the entire reserved address space. */
 +    pgb_static(image_name, 0, local_rva, align);
 +    assert(guest_base != 0);
      /* Reserve the memory on the host. */
 -    assert(guest_base != 0);
      test = g2h_untagged(0);
 -    addr = mmap(test, reserved_va, PROT_NONE, flags, -1, 0);
 +    addr = mmap(test, local_rva, PROT_NONE, flags, -1, 0);
      if (addr == MAP_FAILED || addr != test) {
 +        /*
 +         * If protect_wrap, we could try again with the original reserved_va
 +         * setting, but the edge case of low ulimit vm setting on a 64-bit
 +         * host is probably useless.
 +         */
          error_report("Unable to reserve 0x%lx bytes of virtual address "
 -                     "space at %p (%s) for use as guest address space (check your"
 -                     "virtual memory ulimit setting, min_mmap_addr or reserve less "
 -                     "using -R option)", reserved_va, test, strerror(errno));
 +                     "space at %p (%s) for use as guest address space "
 +                     "(check your virtual memory ulimit setting, "
 +                     "min_mmap_addr or reserve less using -R option)",
 +                     local_rva, test, strerror(errno));
          exit(EXIT_FAILURE);
      }
 +    if (protect_wrap) {
 +        /*
 +         * Prevent the page just before 0x80000000 from being allocated.
 +         * This prevents a single guest object/allocation from crossing
 +         * the signed wrap, and thus being discontiguous in host memory.
 +         */
 +        page_set_flags(0x7fffffff & TARGET_PAGE_MASK, 0x80000000u,
 +                       PAGE_RESERVED);
 +        /* Adjust guest_base so that 0 is in the middle of the reservation. */
 +        guest_base += 0x80000000ul;
 +    }
 +
      qemu_log_mask(CPU_LOG_PAGE, "%s: base @ %p for %lu bytes\n",
                    __func__, addr, reserved_va);
  }
 --
-.20.1
+.25.1

-New patch
+[PULL 27/30] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
+AArch64 has both sign and zero-extending addressing modes, which
+means that either treatment of guest addresses is equally efficient.
+Enabling this for AArch64 gives us testing of the feature in CI.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/aarch64/tcg-target-sa32.h |  8 +++-
+ tcg/aarch64/tcg-target.c.inc  | 81 ++++++++++++++++++++++++-----------
+files changed, 64 insertions(+), 25 deletions(-)
+diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/aarch64/tcg-target-sa32.h
++++ b/tcg/aarch64/tcg-target-sa32.h
+@@ -1 +1,7 @@
+-#define TCG_TARGET_SIGNED_ADDR32 0
++/*
++ * AArch64 has both SXTW and UXTW addressing modes, which means that
++ * it is agnostic to how guest addresses should be represented.
++ * Because aarch64 is more common than the other hosts that will
++ * want to use this feature, enable it for continuous testing.
++ */
++#define TCG_TARGET_SIGNED_ADDR32 1
+diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/aarch64/tcg-target.c.inc
++++ b/tcg/aarch64/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     LDST_LD_S_W = 3,  /* load and sign-extend into Wt */
+ } AArch64LdstType;
++/*
++ * See aarch64/instrs/extendreg/DecodeRegExtend
++ * But note that option<1> == 0 is UNDEFINED for LDR/STR.
++ */
++typedef enum {
++    LDST_EXT_UXTW = 2,  /* zero-extend from uint32_t */
++    LDST_EXT_UXTX = 3,  /* zero-extend from uint64_t (i.e. no extension) */
++    LDST_EXT_SXTW = 6,  /* sign-extend from int32_t */
++} AArch64LdstExt;
++
+ /* We encode the format of the insn into the beginning of the name, so that
+    we can have the preprocessor help "typecheck" the insn vs the output
+    function.  Arm didn't provide us with nice names for the formats, so we
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
+ }
+ static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
+-                              TCGReg rd, TCGReg base, TCGType ext,
++                              TCGReg rd, TCGReg base, AArch64LdstExt option,
+                               TCGReg regoff)
+ {
+     /* Note the AArch64Insn constants above are for C3.3.12.  Adjust.  */
+     tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
+-              0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
++              option << 13 | base << 5 | (rd & 0x1f));
+ }
+ static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
+     /* Worst-case scenario, move offset to temp register, use reg offset.  */
+     tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
+-    tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
++    tcg_out_ldst_r(s, insn, rd, rn, LDST_EXT_UXTX, TCG_REG_TMP);
+ }
+ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
+                                    TCGReg data_r, TCGReg addr_r,
+-                                   TCGType otype, TCGReg off_r)
++                                   AArch64LdstExt option, TCGReg off_r)
+ {
+     switch (memop & MO_SSIZE) {
+     case MO_UB:
+-        tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, option, off_r);
+         break;
+     case MO_SB:
+         tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
+-                       data_r, addr_r, otype, off_r);
++                       data_r, addr_r, option, off_r);
+         break;
+     case MO_UW:
+-        tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, option, off_r);
+         break;
+     case MO_SW:
+         tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
+-                       data_r, addr_r, otype, off_r);
++                       data_r, addr_r, option, off_r);
+         break;
+     case MO_UL:
+-        tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, option, off_r);
+         break;
+     case MO_SL:
+-        tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, option, off_r);
+         break;
+     case MO_UQ:
+-        tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, option, off_r);
+         break;
+     default:
+         tcg_abort();
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
+ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
+                                    TCGReg data_r, TCGReg addr_r,
+-                                   TCGType otype, TCGReg off_r)
++                                   AArch64LdstExt option, TCGReg off_r)
+ {
+     switch (memop & MO_SIZE) {
+     case MO_8:
+-        tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, option, off_r);
+         break;
+     case MO_16:
+-        tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, option, off_r);
+         break;
+     case MO_32:
+-        tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, option, off_r);
+         break;
+     case MO_64:
+-        tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
++        tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, option, off_r);
+         break;
+     default:
+         tcg_abort();
+     }
+ }
++/*
++ * Bits for the option field of LDR/STR (register),
++ * for application to a guest address.
++ */
++static AArch64LdstExt ldst_ext_option(void)
++{
++#ifdef CONFIG_USER_ONLY
++    bool signed_addr32 = guest_base_signed_addr32;
++#else
++    bool signed_addr32 = TCG_TARGET_SIGNED_ADDR32;
++#endif
++
++    if (TARGET_LONG_BITS == 64) {
++        return LDST_EXT_UXTX;
++    } else if (signed_addr32) {
++        return LDST_EXT_SXTW;
++    } else {
++        return LDST_EXT_UXTW;
++    }
++}
++
+ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+                             MemOpIdx oi, TCGType ext)
+ {
+     MemOp memop = get_memop(oi);
+-    const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
++    AArch64LdstExt option = ldst_ext_option();
+     /* Byte swapping is left to middle-end expansion. */
+     tcg_debug_assert((memop & MO_BSWAP) == 0);
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+     tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
+     tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+-                           TCG_REG_X1, otype, addr_reg);
++                           TCG_REG_X1, option, addr_reg);
+     add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
+                         s->code_ptr, label_ptr);
+ #else /* !CONFIG_SOFTMMU */
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+     }
+     if (USE_GUEST_BASE) {
+         tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+-                               TCG_REG_GUEST_BASE, otype, addr_reg);
++                               TCG_REG_GUEST_BASE, option, addr_reg);
+     } else {
++        /* This case is always a 64-bit guest with no extension. */
+         tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+-                               addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
++                               addr_reg, LDST_EXT_UXTX, TCG_REG_XZR);
+     }
+ #endif /* CONFIG_SOFTMMU */
+ }
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+                             MemOpIdx oi)
+ {
+     MemOp memop = get_memop(oi);
+-    const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
++    AArch64LdstExt option = ldst_ext_option();
+     /* Byte swapping is left to middle-end expansion. */
+     tcg_debug_assert((memop & MO_BSWAP) == 0);
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+     tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
+     tcg_out_qemu_st_direct(s, memop, data_reg,
+-                           TCG_REG_X1, otype, addr_reg);
++                           TCG_REG_X1, option, addr_reg);
+     add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
+                         data_reg, addr_reg, s->code_ptr, label_ptr);
+ #else /* !CONFIG_SOFTMMU */
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+     }
+     if (USE_GUEST_BASE) {
+         tcg_out_qemu_st_direct(s, memop, data_reg,
+-                               TCG_REG_GUEST_BASE, otype, addr_reg);
++                               TCG_REG_GUEST_BASE, option, addr_reg);
+     } else {
++        /* This case is always a 64-bit guest with no extension. */
+         tcg_out_qemu_st_direct(s, memop, data_reg,
+-                               addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
++                               addr_reg, LDST_EXT_UXTX, TCG_REG_XZR);
+     }
+ #endif /* CONFIG_SOFTMMU */
+ }
+--
+.25.1

-[PULL 15/16] cputlb: Hoist timestamp outside of loops over tlbs
+[PULL 28/30] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32
-Do not call get_clock_realtime() in tlb_mmu_resize_locked,
+All 32-bit mips operations sign-extend the output, so we are easily
-but hoist outside of any loop over a set of tlbs.  This is
+able to keep TCG_TYPE_I32 values sign-extended in host registers.
 only two (indirect) callers, tlb_flush_by_mmuidx_async_work
 and tlb_flush_page_locked, so not onerous.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 14 ++++++++------
+ tcg/mips/tcg-target-sa32.h |  8 ++++++++
-file changed, 8 insertions(+), 6 deletions(-)
+ tcg/mips/tcg-target.c.inc  | 10 ++--------
 files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/mips/tcg-target-sa32.h
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/mips/tcg-target-sa32.h
-@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
+@@ -1 +1,9 @@
-  * high), since otherwise we are likely to have a significant amount of
++/*
-  * conflict misses.
++ * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32;
-  */
++ * TCG expects this to only be set for 64-bit hosts.
--static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
++ */
-+static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
++#ifdef __mips64
-+                                  int64_t now)
++#define TCG_TARGET_SIGNED_ADDR32 1
- {
++#else
-     size_t old_size = tlb_n_entries(fast);
+ #define TCG_TARGET_SIGNED_ADDR32 0
-     size_t rate;
++#endif
-     size_t new_size = old_size;
+diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
--    int64_t now = get_clock_realtime();
+index XXXXXXX..XXXXXXX 100644
-     int64_t window_len_ms = 100;
+--- a/tcg/mips/tcg-target.c.inc
-     int64_t window_len_ns = window_len_ms * 1000 * 1000;
++++ b/tcg/mips/tcg-target.c.inc
-     bool window_expired = now > desc->window_begin_ns + window_len_ns;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
-@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
+                      TCG_TMP0, TCG_TMP3, cmp_off);
      memset(desc->vtable, -1, sizeof(desc->vtable));
  }
 -static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
 +static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx,
 +                                        int64_t now)
  {
      CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
      CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
 -    tlb_mmu_resize_locked(desc, fast);
 +    tlb_mmu_resize_locked(desc, fast, now);
      tlb_mmu_flush_locked(desc, fast);
  }
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
      CPUArchState *env = cpu->env_ptr;
      uint16_t asked = data.host_int;
      uint16_t all_dirty, work, to_clean;
 +    int64_t now = get_clock_realtime();
      assert_cpu_is_self(cpu);
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
      for (work = to_clean; work != 0; work &= work - 1) {
          int mmu_idx = ctz32(work);
 -        tlb_flush_one_mmuidx_locked(env, mmu_idx);
 +        tlb_flush_one_mmuidx_locked(env, mmu_idx, now);
      }
-     qemu_spin_unlock(&env_tlb(env)->c.lock);
+-    /* Zero extend a 32-bit guest address for a 64-bit host. */
-@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,
+-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-         tlb_debug("forcing full flush midx %d ("
+-        tcg_out_ext32u(s, base, addrl);
-                   TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
+-        addrl = base;
-                   midx, lp_addr, lp_mask);
+-    }
--        tlb_flush_one_mmuidx_locked(env, midx);
+-
-+        tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());
+     /*
-     } else {
+      * Mask the page bits, keeping the alignment bits to compare against.
-         if (tlb_flush_entry_locked(tlb_entry(env, midx, page), page)) {
+      * For unaligned accesses, compare against the end of the access to
-             tlb_n_used_entries_dec(env, midx);
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
                          data_regl, data_regh, addr_regl, addr_regh,
                          s->code_ptr, label_ptr);
  #else
 -    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 +    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
          tcg_out_ext32u(s, base, addr_regl);
          addr_regl = base;
      }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
                          data_regl, data_regh, addr_regl, addr_regh,
                          s->code_ptr, label_ptr);
  #else
 -    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 +    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
          tcg_out_ext32u(s, base, addr_regl);
          addr_regl = base;
      }
 --
-.20.1
+.25.1

-[PULL 14/16] cputlb: Initialize tlbs as flushed
+[PULL 29/30] tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
-There's little point in leaving these data structures half initialized,
+All RV64 32-bit operations sign-extend the output, so we are easily
-and relying on a flush to be done during reset.
+able to keep TCG_TYPE_I32 values sign-extended in host registers.
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/cputlb.c | 5 +++--
+ tcg/riscv/tcg-target-sa32.h | 6 +++++-
-file changed, 3 insertions(+), 2 deletions(-)
+ tcg/riscv/tcg-target.c.inc  | 8 ++------
 files changed, 7 insertions(+), 7 deletions(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/tcg/riscv/tcg-target-sa32.h
-+++ b/accel/tcg/cputlb.c
++++ b/tcg/riscv/tcg-target-sa32.h
-@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
+@@ -1 +1,5 @@
-     fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
+-#define TCG_TARGET_SIGNED_ADDR32 0
-     fast->table = g_new(CPUTLBEntry, n_entries);
++/*
-     desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
++ * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32;
-+    tlb_mmu_flush_locked(desc, fast);
++ * TCG expects this to only be set for 64-bit hosts.
 + */
 +#define TCG_TARGET_SIGNED_ADDR32  (__riscv_xlen == 64)
 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/riscv/tcg-target.c.inc
 +++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
      tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
      /* TLB Hit - translate address using addend.  */
 -    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 -        tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
 -        addrl = TCG_REG_TMP0;
 -    }
      tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
  }
- static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
-@@ -XXX,XX +XXX,XX @@ void tlb_init(CPUState *cpu)
+                         data_regl, data_regh, addr_regl, addr_regh,
+                         s->code_ptr, label_ptr);
-     qemu_spin_init(&env_tlb(env)->c.lock);
+ #else
+-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
--    /* Ensure that cpu_reset performs a full flush.  */
++    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
--    env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;
+         tcg_out_ext32u(s, base, addr_regl);
-+    /* All tlbs are initialized flushed. */
+         addr_regl = base;
-+    env_tlb(env)->c.dirty = 0;
+     }
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
-     for (i = 0; i < NB_MMU_MODES; i++) {
+                         data_regl, data_regh, addr_regl, addr_regh,
-         tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);
+                         s->code_ptr, label_ptr);
  #else
 -    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 +    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
          tcg_out_ext32u(s, base, addr_regl);
          addr_regl = base;
      }
 --
-.20.1
+.25.1

-[PULL 02/16] util/cacheinfo: fix crash when compiling with uClibc
+[PULL 30/30] tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32
-From: Carlos Santos <casantos@redhat.com>
+All 32-bit LoongArch operations sign-extend the output, so we are easily
 able to keep TCG_TYPE_I32 values sign-extended in host registers.
-uClibc defines _SC_LEVEL1_ICACHE_LINESIZE and _SC_LEVEL1_DCACHE_LINESIZE
+Cc: WANG Xuerui <git@xen0n.name>
-but the corresponding sysconf calls returns -1, which is a valid result,
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 meaning that the limit is indeterminate.
 Handle this situation using the fallback values instead of crashing due
 to an assertion failure.
 Signed-off-by: Carlos Santos <casantos@redhat.com>
 Message-Id: <20191017123713.30192-1-casantos@redhat.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- util/cacheinfo.c | 10 ++++++++--
+ tcg/loongarch64/tcg-target-sa32.h |  2 +-
-file changed, 8 insertions(+), 2 deletions(-)
+ tcg/loongarch64/tcg-target.c.inc  | 15 ++++++---------
 files changed, 7 insertions(+), 10 deletions(-)
-diff --git a/util/cacheinfo.c b/util/cacheinfo.c
+diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
 index XXXXXXX..XXXXXXX 100644
---- a/util/cacheinfo.c
+--- a/tcg/loongarch64/tcg-target-sa32.h
-+++ b/util/cacheinfo.c
++++ b/tcg/loongarch64/tcg-target-sa32.h
-@@ -XXX,XX +XXX,XX @@ static void sys_cache_info(int *isize, int *dsize)
+@@ -1 +1 @@
- static void sys_cache_info(int *isize, int *dsize)
+-#define TCG_TARGET_SIGNED_ADDR32 0
 +#define TCG_TARGET_SIGNED_ADDR32 1
 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/loongarch64/tcg-target.c.inc
 +++ b/tcg/loongarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
      return tcg_out_fail_alignment(s, l);
  }
 -#endif /* CONFIG_SOFTMMU */
 -
  /*
   * `ext32u` the address register into the temp register given,
   * if target is 32-bit, no-op otherwise.
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
  static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s,
                                            TCGReg addr, TCGReg tmp)
  {
- # ifdef _SC_LEVEL1_ICACHE_LINESIZE
+-    if (TARGET_LONG_BITS == 32) {
--    *isize = sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
++    if (TARGET_LONG_BITS == 32 && !guest_base_signed_addr32) {
-+    int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
+         tcg_out_ext32u(s, tmp, addr);
-+    if (tmp_isize > 0) {
+         return tmp;
-+        *isize = tmp_isize;
+     }
-+    }
+     return addr;
  # endif
  # ifdef _SC_LEVEL1_DCACHE_LINESIZE
 -    *dsize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
 +    int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
 +    if (tmp_dsize > 0) {
 +        *dsize = tmp_dsize;
 +    }
  # endif
  }
- #endif /* sys_cache_info */
++#endif /* CONFIG_SOFTMMU */
  static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj,
                                     TCGReg rk, MemOp opc, TCGType type)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
      tcg_insn_unit *label_ptr[1];
  #else
      unsigned a_bits;
 -#endif
      TCGReg base;
 +#endif
      data_regl = *args++;
      addr_regl = *args++;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
  #if defined(CONFIG_SOFTMMU)
      tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1);
 -    base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
 -    tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type);
 +    tcg_out_qemu_ld_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc, type);
      add_qemu_ldst_label(s, 1, oi, type,
                          data_regl, addr_regl,
                          s->code_ptr, label_ptr);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
      tcg_insn_unit *label_ptr[1];
  #else
      unsigned a_bits;
 -#endif
      TCGReg base;
 +#endif
      data_regl = *args++;
      addr_regl = *args++;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
  #if defined(CONFIG_SOFTMMU)
      tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0);
 -    base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
 -    tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc);
 +    tcg_out_qemu_st_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc);
      add_qemu_ldst_label(s, 0, oi,
 , /* type param is unused for stores */
                          data_regl, addr_regl,
 --
-.20.1
+.25.1

The following changes since commit 3e08b2b9cb64bff2b73fa9128c0e49bfcde0dd40:

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200121' into staging (2020-01-21 15:29:25 +0000)

are available in the Git repository at:

https://github.com/rth7680/qemu.git tags/pull-tcg-20200121

for you to fetch changes up to 75fa376cdab5e5db2c7fdd107358e16f95503ac6:

scripts/git.orderfile: Display decodetree before C source (2020-01-21 15:26:09 -1000)

----------------------------------------------------------------
Remove another limit to NB_MMU_MODES.
Fix compilation using uclibc.
Fix defaulting of -accel parameters.
Tidy cputlb basic routines.
Adjust git.orderfile for decodetree.

----------------------------------------------------------------
Carlos Santos (1):
      util/cacheinfo: fix crash when compiling with uClibc

Philippe Mathieu-Daudé (1):
      scripts/git.orderfile: Display decodetree before C source

Richard Henderson (14):
      cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN
      vl: Remove unused variable in configure_accelerators
      vl: Reduce scope of variables in configure_accelerators
      vl: Remove useless test in configure_accelerators
      vl: Only choose enabled accelerators in configure_accelerators
      cputlb: Merge tlb_table_flush_by_mmuidx into tlb_flush_one_mmuidx_locked
      cputlb: Make tlb_n_entries private to cputlb.c
      cputlb: Pass CPUTLBDescFast to tlb_n_entries and sizeof_tlb
      cputlb: Hoist tlb portions in tlb_mmu_resize_locked
      cputlb: Hoist tlb portions in tlb_flush_one_mmuidx_locked
      cputlb: Split out tlb_mmu_flush_locked
      cputlb: Partially merge tlb_dyn_init into tlb_init
      cputlb: Initialize tlbs as flushed
      cputlb: Hoist timestamp outside of loops over tlbs

In target/arm we will shortly have "too many" mmu_idx.
The current minimum barrier is caused by the way in which
tlb_flush_page_by_mmuidx is coded.

We can remove this limitation by allocating memory for
consumption by the worker.  Let us assume that this is
the unlikely case, as will be the case for the majority
of targets which have so far satisfied the BUILD_BUG_ON,
and only allocate memory when necessary.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 167 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 132 insertions(+), 35 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,
     }
 }
 
-/* As we are going to hijack the bottom bits of the page address for a
- * mmuidx bit mask we need to fail to build if we can't do that
+/**
+ * tlb_flush_page_by_mmuidx_async_0:
+ * @cpu: cpu on which to flush
+ * @addr: page of virtual address to flush
+ * @idxmap: set of mmu_idx to flush
+ *
+ * Helper for tlb_flush_page_by_mmuidx and friends, flush one page
+ * at @addr from the tlbs indicated by @idxmap from @cpu.
  */
-QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN);
-
-static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
-                                                run_on_cpu_data data)
+static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,
+                                             target_ulong addr,
+                                             uint16_t idxmap)
 {
     CPUArchState *env = cpu->env_ptr;
-    target_ulong addr_and_mmuidx = (target_ulong) data.target_ptr;
-    target_ulong addr = addr_and_mmuidx & TARGET_PAGE_MASK;
-    unsigned long mmu_idx_bitmap = addr_and_mmuidx & ALL_MMUIDX_BITS;
     int mmu_idx;
 
     assert_cpu_is_self(cpu);
 
-    tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n",
-              addr, mmu_idx_bitmap);
+    tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%x\n", addr, idxmap);
 
     qemu_spin_lock(&env_tlb(env)->c.lock);
     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
-        if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
+        if ((idxmap >> mmu_idx) & 1) {
             tlb_flush_page_locked(env, mmu_idx, addr);
         }
     }
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
     tb_flush_jmp_cache(cpu, addr);
 }
 
+/**
+ * tlb_flush_page_by_mmuidx_async_1:
+ * @cpu: cpu on which to flush
+ * @data: encoded addr + idxmap
+ *
+ * Helper for tlb_flush_page_by_mmuidx and friends, called through
+ * async_run_on_cpu.  The idxmap parameter is encoded in the page
+ * offset of the target_ptr field.  This limits the set of mmu_idx
+ * that can be passed via this method.
+ */
+static void tlb_flush_page_by_mmuidx_async_1(CPUState *cpu,
+                                             run_on_cpu_data data)
+{
+    target_ulong addr_and_idxmap = (target_ulong) data.target_ptr;
+    target_ulong addr = addr_and_idxmap & TARGET_PAGE_MASK;
+    uint16_t idxmap = addr_and_idxmap & ~TARGET_PAGE_MASK;
+
+    tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap);
+}
+
+typedef struct {
+    target_ulong addr;
+    uint16_t idxmap;
+} TLBFlushPageByMMUIdxData;
+
+/**
+ * tlb_flush_page_by_mmuidx_async_2:
+ * @cpu: cpu on which to flush
+ * @data: allocated addr + idxmap
+ *
+ * Helper for tlb_flush_page_by_mmuidx and friends, called through
+ * async_run_on_cpu.  The addr+idxmap parameters are stored in a
+ * TLBFlushPageByMMUIdxData structure that has been allocated
+ * specifically for this helper.  Free the structure when done.
+ */
+static void tlb_flush_page_by_mmuidx_async_2(CPUState *cpu,
+                                             run_on_cpu_data data)
+{
+    TLBFlushPageByMMUIdxData *d = data.host_ptr;
+
+    tlb_flush_page_by_mmuidx_async_0(cpu, d->addr, d->idxmap);
+    g_free(d);
+}
+
 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap)
 {
-    target_ulong addr_and_mmu_idx;
-
     tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%" PRIx16 "\n", addr, idxmap);
 
     /* This should already be page aligned */
-    addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
-    addr_and_mmu_idx |= idxmap;
+    addr &= TARGET_PAGE_MASK;
 
-    if (!qemu_cpu_is_self(cpu)) {
-        async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work,
-                         RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
+    if (qemu_cpu_is_self(cpu)) {
+        tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap);
+    } else if (idxmap < TARGET_PAGE_SIZE) {
+        /*
+         * Most targets have only a few mmu_idx.  In the case where
+         * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid
+         * allocating memory for this operation.
+         */
+        async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_1,
+                         RUN_ON_CPU_TARGET_PTR(addr | idxmap));
     } else {
-        tlb_flush_page_by_mmuidx_async_work(
-            cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
+        TLBFlushPageByMMUIdxData *d = g_new(TLBFlushPageByMMUIdxData, 1);
+
+        /* Otherwise allocate a structure, freed by the worker.  */
+        d->addr = addr;
+        d->idxmap = idxmap;
+        async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_2,
+                         RUN_ON_CPU_HOST_PTR(d));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr,
                                        uint16_t idxmap)
 {
-    const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work;
-    target_ulong addr_and_mmu_idx;
-
     tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap);
 
     /* This should already be page aligned */
-    addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
-    addr_and_mmu_idx |= idxmap;
+    addr &= TARGET_PAGE_MASK;
 
-    flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
-    fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
+    /*
+     * Allocate memory to hold addr+idxmap only when needed.
+     * See tlb_flush_page_by_mmuidx for details.
+     */
+    if (idxmap < TARGET_PAGE_SIZE) {
+        flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1,
+                         RUN_ON_CPU_TARGET_PTR(addr | idxmap));
+    } else {
+        CPUState *dst_cpu;
+
+        /* Allocate a separate data block for each destination cpu.  */
+        CPU_FOREACH(dst_cpu) {
+            if (dst_cpu != src_cpu) {
+                TLBFlushPageByMMUIdxData *d
+                    = g_new(TLBFlushPageByMMUIdxData, 1);
+
+                d->addr = addr;
+                d->idxmap = idxmap;
+                async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2,
+                                 RUN_ON_CPU_HOST_PTR(d));
+            }
+        }
+    }
+
+    tlb_flush_page_by_mmuidx_async_0(src_cpu, addr, idxmap);
 }
 
 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
                                               target_ulong addr,
                                               uint16_t idxmap)
 {
-    const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work;
-    target_ulong addr_and_mmu_idx;
-
     tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap);
 
     /* This should already be page aligned */
-    addr_and_mmu_idx = addr & TARGET_PAGE_MASK;
-    addr_and_mmu_idx |= idxmap;
+    addr &= TARGET_PAGE_MASK;
 
-    flush_all_helper(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
-    async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));
+    /*
+     * Allocate memory to hold addr+idxmap only when needed.
+     * See tlb_flush_page_by_mmuidx for details.
+     */
+    if (idxmap < TARGET_PAGE_SIZE) {
+        flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1,
+                         RUN_ON_CPU_TARGET_PTR(addr | idxmap));
+        async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_1,
+                              RUN_ON_CPU_TARGET_PTR(addr | idxmap));
+    } else {
+        CPUState *dst_cpu;
+        TLBFlushPageByMMUIdxData *d;
+
+        /* Allocate a separate data block for each destination cpu.  */
+        CPU_FOREACH(dst_cpu) {
+            if (dst_cpu != src_cpu) {
+                d = g_new(TLBFlushPageByMMUIdxData, 1);
+                d->addr = addr;
+                d->idxmap = idxmap;
+                async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2,
+                                 RUN_ON_CPU_HOST_PTR(d));
+            }
+        }
+
+        d = g_new(TLBFlushPageByMMUIdxData, 1);
+        d->addr = addr;
+        d->idxmap = idxmap;
+        async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_2,
+                              RUN_ON_CPU_HOST_PTR(d));
+    }
 }
 
 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr)
-- 
2.20.1

From: Carlos Santos <casantos@redhat.com>

uClibc defines _SC_LEVEL1_ICACHE_LINESIZE and _SC_LEVEL1_DCACHE_LINESIZE
but the corresponding sysconf calls returns -1, which is a valid result,
meaning that the limit is indeterminate.

Handle this situation using the fallback values instead of crashing due
to an assertion failure.

Signed-off-by: Carlos Santos <casantos@redhat.com>
Message-Id: <20191017123713.30192-1-casantos@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 util/cacheinfo.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index XXXXXXX..XXXXXXX 100644
--- a/util/cacheinfo.c
+++ b/util/cacheinfo.c
@@ -XXX,XX +XXX,XX @@ static void sys_cache_info(int *isize, int *dsize)
 static void sys_cache_info(int *isize, int *dsize)
 {
 # ifdef _SC_LEVEL1_ICACHE_LINESIZE
-    *isize = sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
+    int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
+    if (tmp_isize > 0) {
+        *isize = tmp_isize;
+    }
 # endif
 # ifdef _SC_LEVEL1_DCACHE_LINESIZE
-    *dsize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
+    int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
+    if (tmp_dsize > 0) {
+        *dsize = tmp_dsize;
+    }
 # endif
 }
 #endif /* sys_cache_info */
-- 
2.20.1

The accel_initialised variable no longer has any setters.

Fixes: 6f6e1698a68c
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 vl.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/vl.c b/vl.c
index XXXXXXX..XXXXXXX 100644
--- a/vl.c
+++ b/vl.c
@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
 {
     const char *accel;
     char **accel_list, **tmp;
-    bool accel_initialised = false;
     bool init_failed = false;
 
     qemu_opts_foreach(qemu_find_opts("icount"),
@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
 
         accel_list = g_strsplit(accel, ":", 0);
 
-        for (tmp = accel_list; !accel_initialised && tmp && *tmp; tmp++) {
+        for (tmp = accel_list; tmp && *tmp; tmp++) {
             /*
              * Filter invalid accelerators here, to prevent obscenities
              * such as "-machine accel=tcg,,thread=single".
-- 
2.20.1

The accel_list and tmp variables are only used when manufacturing
-machine accel, options based on -accel.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 vl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/vl.c b/vl.c
index XXXXXXX..XXXXXXX 100644
--- a/vl.c
+++ b/vl.c
@@ -XXX,XX +XXX,XX @@ static int do_configure_accelerator(void *opaque, QemuOpts *opts, Error **errp)
 static void configure_accelerators(const char *progname)
 {
     const char *accel;
-    char **accel_list, **tmp;
     bool init_failed = false;
 
     qemu_opts_foreach(qemu_find_opts("icount"),
@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
 
     accel = qemu_opt_get(qemu_get_machine_opts(), "accel");
     if (QTAILQ_EMPTY(&qemu_accel_opts.head)) {
+        char **accel_list, **tmp;
+
         if (accel == NULL) {
             /* Select the default accelerator */
             if (!accel_find("tcg") && !accel_find("kvm")) {
-- 
2.20.1

By choosing "tcg:kvm" when kvm is not enabled, we generate
an incorrect warning: "invalid accelerator kvm".

At the same time, use g_str_has_suffix rather than open-coding
the same operation.

Presumably the inverse is also true with --disable-tcg.

Fixes: 28a0961757fc
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 vl.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/vl.c b/vl.c
index XXXXXXX..XXXXXXX 100644
--- a/vl.c
+++ b/vl.c
@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)
 
         if (accel == NULL) {
             /* Select the default accelerator */
-            if (!accel_find("tcg") && !accel_find("kvm")) {
-                error_report("No accelerator selected and"
-                             " no default accelerator available");
-                exit(1);
-            } else {
-                int pnlen = strlen(progname);
-                if (pnlen >= 3 && g_str_equal(&progname[pnlen - 3], "kvm")) {
+            bool have_tcg = accel_find("tcg");
+            bool have_kvm = accel_find("kvm");
+
+            if (have_tcg && have_kvm) {
+                if (g_str_has_suffix(progname, "kvm")) {
                     /* If the program name ends with "kvm", we prefer KVM */
                     accel = "kvm:tcg";
                 } else {
                     accel = "tcg:kvm";
                 }
+            } else if (have_kvm) {
+                accel = "kvm";
+            } else if (have_tcg) {
+                accel = "tcg";
+            } else {
+                error_report("No accelerator selected and"
+                             " no default accelerator available");
+                exit(1);
             }
         }
-
         accel_list = g_strsplit(accel, ":", 0);
 
         for (tmp = accel_list; *tmp; tmp++) {
-- 
2.20.1

There is only one caller for tlb_table_flush_by_mmuidx.  Place
the result at the earlier line number, due to an expected user
in the near future.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
     }
 }
 
-static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx)
+static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
 {
     tlb_mmu_resize_locked(env, mmu_idx);
-    memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
     env_tlb(env)->d[mmu_idx].n_used_entries = 0;
+    env_tlb(env)->d[mmu_idx].large_page_addr = -1;
+    env_tlb(env)->d[mmu_idx].large_page_mask = -1;
+    env_tlb(env)->d[mmu_idx].vindex = 0;
+    memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
+    memset(env_tlb(env)->d[mmu_idx].vtable, -1,
+           sizeof(env_tlb(env)->d[0].vtable));
 }
 
 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
@@ -XXX,XX +XXX,XX @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide)
     *pelide = elide;
 }
 
-static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
-{
-    tlb_table_flush_by_mmuidx(env, mmu_idx);
-    env_tlb(env)->d[mmu_idx].large_page_addr = -1;
-    env_tlb(env)->d[mmu_idx].large_page_mask = -1;
-    env_tlb(env)->d[mmu_idx].vindex = 0;
-    memset(env_tlb(env)->d[mmu_idx].vtable, -1,
-           sizeof(env_tlb(env)->d[0].vtable));
-}
-
 static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
 {
     CPUArchState *env = cpu->env_ptr;
-- 
2.20.1

There are no users of this function outside cputlb.c,
and its interface will change in the next patch.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h | 5 -----
 accel/tcg/cputlb.c      | 5 +++++
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -XXX,XX +XXX,XX @@ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
     return (addr >> TARGET_PAGE_BITS) & size_mask;
 }
 
-static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
-{
-    return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
-}
-
 /* Find the TLB entry corresponding to the mmu_idx + address pair.  */
 static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
                                      target_ulong addr)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
 QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
 #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
 
+static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
+{
+    return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
+}
+
 static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
 {
     return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS);
-- 
2.20.1

We do not need the entire CPUArchState to compute these values.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data));
 QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
 #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
 
-static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
+static inline size_t tlb_n_entries(CPUTLBDescFast *fast)
 {
-    return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
+    return (fast->mask >> CPU_TLB_ENTRY_BITS) + 1;
 }
 
-static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
+static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
 {
-    return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS);
+    return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
 }
 
 static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)
 static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
 {
     CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
-    size_t old_size = tlb_n_entries(env, mmu_idx);
+    size_t old_size = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);
     size_t rate;
     size_t new_size = old_size;
     int64_t now = get_clock_realtime();
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
     env_tlb(env)->d[mmu_idx].large_page_addr = -1;
     env_tlb(env)->d[mmu_idx].large_page_mask = -1;
     env_tlb(env)->d[mmu_idx].vindex = 0;
-    memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
+    memset(env_tlb(env)->f[mmu_idx].table, -1,
+           sizeof_tlb(&env_tlb(env)->f[mmu_idx]));
     memset(env_tlb(env)->d[mmu_idx].vtable, -1,
            sizeof(env_tlb(env)->d[0].vtable));
 }
@@ -XXX,XX +XXX,XX @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
     qemu_spin_lock(&env_tlb(env)->c.lock);
     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
         unsigned int i;
-        unsigned int n = tlb_n_entries(env, mmu_idx);
+        unsigned int n = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);
 
         for (i = 0; i < n; i++) {
             tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i],
-- 
2.20.1

No functional change, but the smaller expressions make
the code easier to read.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)
 
 /**
  * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
- * @env: CPU that owns the TLB
- * @mmu_idx: MMU index of the TLB
+ * @desc: The CPUTLBDesc portion of the TLB
+ * @fast: The CPUTLBDescFast portion of the same TLB
  *
  * Called with tlb_lock_held.
  *
@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)
  * high), since otherwise we are likely to have a significant amount of
  * conflict misses.
  */
-static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
+static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
 {
-    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
-    size_t old_size = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);
+    size_t old_size = tlb_n_entries(fast);
     size_t rate;
     size_t new_size = old_size;
     int64_t now = get_clock_realtime();
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
         return;
     }
 
-    g_free(env_tlb(env)->f[mmu_idx].table);
-    g_free(env_tlb(env)->d[mmu_idx].iotlb);
+    g_free(fast->table);
+    g_free(desc->iotlb);
 
     tlb_window_reset(desc, now, 0);
     /* desc->n_used_entries is cleared by the caller */
-    env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
-    env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);
-    env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);
+    fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
+    fast->table = g_try_new(CPUTLBEntry, new_size);
+    desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
+
     /*
      * If the allocations fail, try smaller sizes. We just freed some
      * memory, so going back to half of new_size has a good chance of working.
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
      * allocations to fail though, so we progressively reduce the allocation
      * size, aborting if we cannot even allocate the smallest TLB we support.
      */
-    while (env_tlb(env)->f[mmu_idx].table == NULL ||
-           env_tlb(env)->d[mmu_idx].iotlb == NULL) {
+    while (fast->table == NULL || desc->iotlb == NULL) {
         if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
             error_report("%s: %s", __func__, strerror(errno));
             abort();
         }
         new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS);
-        env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
+        fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
 
-        g_free(env_tlb(env)->f[mmu_idx].table);
-        g_free(env_tlb(env)->d[mmu_idx].iotlb);
-        env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);
-        env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);
+        g_free(fast->table);
+        g_free(desc->iotlb);
+        fast->table = g_try_new(CPUTLBEntry, new_size);
+        desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
     }
 }
 
 static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
 {
-    tlb_mmu_resize_locked(env, mmu_idx);
+    tlb_mmu_resize_locked(&env_tlb(env)->d[mmu_idx], &env_tlb(env)->f[mmu_idx]);
     env_tlb(env)->d[mmu_idx].n_used_entries = 0;
     env_tlb(env)->d[mmu_idx].large_page_addr = -1;
     env_tlb(env)->d[mmu_idx].large_page_mask = -1;
-- 
2.20.1

No functional change, but the smaller expressions make
the code easier to read.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
 
 static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
 {
-    tlb_mmu_resize_locked(&env_tlb(env)->d[mmu_idx], &env_tlb(env)->f[mmu_idx]);
-    env_tlb(env)->d[mmu_idx].n_used_entries = 0;
-    env_tlb(env)->d[mmu_idx].large_page_addr = -1;
-    env_tlb(env)->d[mmu_idx].large_page_mask = -1;
-    env_tlb(env)->d[mmu_idx].vindex = 0;
-    memset(env_tlb(env)->f[mmu_idx].table, -1,
-           sizeof_tlb(&env_tlb(env)->f[mmu_idx]));
-    memset(env_tlb(env)->d[mmu_idx].vtable, -1,
-           sizeof(env_tlb(env)->d[0].vtable));
+    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
+    CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
+
+    tlb_mmu_resize_locked(desc, fast);
+    desc->n_used_entries = 0;
+    desc->large_page_addr = -1;
+    desc->large_page_mask = -1;
+    desc->vindex = 0;
+    memset(fast->table, -1, sizeof_tlb(fast));
+    memset(desc->vtable, -1, sizeof(desc->vtable));
 }
 
 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
-- 
2.20.1

We will want to be able to flush a tlb without resizing.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
     }
 }
 
-static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
+static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
 {
-    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
-    CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
-
-    tlb_mmu_resize_locked(desc, fast);
     desc->n_used_entries = 0;
     desc->large_page_addr = -1;
     desc->large_page_mask = -1;
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
     memset(desc->vtable, -1, sizeof(desc->vtable));
 }
 
+static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
+{
+    CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
+    CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
+
+    tlb_mmu_resize_locked(desc, fast);
+    tlb_mmu_flush_locked(desc, fast);
+}
+
 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
 {
     env_tlb(env)->d[mmu_idx].n_used_entries++;
-- 
2.20.1

Merge into the only caller, but at the same time split
out tlb_mmu_init to initialize a single tlb entry.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 33 ++++++++++++++++-----------------
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
     desc->window_max_entries = max_entries;
 }
 
-static void tlb_dyn_init(CPUArchState *env)
-{
-    int i;
-
-    for (i = 0; i < NB_MMU_MODES; i++) {
-        CPUTLBDesc *desc = &env_tlb(env)->d[i];
-        size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
-
-        tlb_window_reset(desc, get_clock_realtime(), 0);
-        desc->n_used_entries = 0;
-        env_tlb(env)->f[i].mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
-        env_tlb(env)->f[i].table = g_new(CPUTLBEntry, n_entries);
-        env_tlb(env)->d[i].iotlb = g_new(CPUIOTLBEntry, n_entries);
-    }
-}
-
 /**
  * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
  * @desc: The CPUTLBDesc portion of the TLB
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
     tlb_mmu_flush_locked(desc, fast);
 }
 
+static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
+{
+    size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
+
+    tlb_window_reset(desc, now, 0);
+    desc->n_used_entries = 0;
+    fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
+    fast->table = g_new(CPUTLBEntry, n_entries);
+    desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
+}
+
 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
 {
     env_tlb(env)->d[mmu_idx].n_used_entries++;
@@ -XXX,XX +XXX,XX @@ static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx)
 void tlb_init(CPUState *cpu)
 {
     CPUArchState *env = cpu->env_ptr;
+    int64_t now = get_clock_realtime();
+    int i;
 
     qemu_spin_init(&env_tlb(env)->c.lock);
 
     /* Ensure that cpu_reset performs a full flush.  */
     env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;
 
-    tlb_dyn_init(env);
+    for (i = 0; i < NB_MMU_MODES; i++) {
+        tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);
+    }
 }
 
 /* flush_all_helper: run fn across all cpus
-- 
2.20.1

There's little point in leaving these data structures half initialized,
and relying on a flush to be done during reset.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
     fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
     fast->table = g_new(CPUTLBEntry, n_entries);
     desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
+    tlb_mmu_flush_locked(desc, fast);
 }
 
 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
@@ -XXX,XX +XXX,XX @@ void tlb_init(CPUState *cpu)
 
     qemu_spin_init(&env_tlb(env)->c.lock);
 
-    /* Ensure that cpu_reset performs a full flush.  */
-    env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;
+    /* All tlbs are initialized flushed. */
+    env_tlb(env)->c.dirty = 0;
 
     for (i = 0; i < NB_MMU_MODES; i++) {
         tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);
-- 
2.20.1

Do not call get_clock_realtime() in tlb_mmu_resize_locked,
but hoist outside of any loop over a set of tlbs.  This is
only two (indirect) callers, tlb_flush_by_mmuidx_async_work
and tlb_flush_page_locked, so not onerous.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
  * high), since otherwise we are likely to have a significant amount of
  * conflict misses.
  */
-static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
+static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
+                                  int64_t now)
 {
     size_t old_size = tlb_n_entries(fast);
     size_t rate;
     size_t new_size = old_size;
-    int64_t now = get_clock_realtime();
     int64_t window_len_ms = 100;
     int64_t window_len_ns = window_len_ms * 1000 * 1000;
     bool window_expired = now > desc->window_begin_ns + window_len_ns;
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
     memset(desc->vtable, -1, sizeof(desc->vtable));
 }
 
-static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
+static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx,
+                                        int64_t now)
 {
     CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
     CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];
 
-    tlb_mmu_resize_locked(desc, fast);
+    tlb_mmu_resize_locked(desc, fast, now);
     tlb_mmu_flush_locked(desc, fast);
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
     CPUArchState *env = cpu->env_ptr;
     uint16_t asked = data.host_int;
     uint16_t all_dirty, work, to_clean;
+    int64_t now = get_clock_realtime();
 
     assert_cpu_is_self(cpu);
 
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
 
     for (work = to_clean; work != 0; work &= work - 1) {
         int mmu_idx = ctz32(work);
-        tlb_flush_one_mmuidx_locked(env, mmu_idx);
+        tlb_flush_one_mmuidx_locked(env, mmu_idx, now);
     }
 
     qemu_spin_unlock(&env_tlb(env)->c.lock);
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,
         tlb_debug("forcing full flush midx %d ("
                   TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
                   midx, lp_addr, lp_mask);
-        tlb_flush_one_mmuidx_locked(env, midx);
+        tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());
     } else {
         if (tlb_flush_entry_locked(tlb_entry(env, midx, page), page)) {
             tlb_n_used_entries_dec(env, midx);
-- 
2.20.1

The following changes since commit 36eae3a732a1f2aa81391e871ac0e9bb3233e7d7:

Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-migration-20220302b' into staging (2022-03-02 20:55:48 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220303

for you to fetch changes up to f23e6de25c31cadd9a3b7122f9384e6b259ce37f:

tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 (2022-03-03 10:47:20 -1000)

----------------------------------------------------------------
Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vector nand, nor, eqv.
Support vector nand, nor, eqv on PPC and S390X hosts.
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
Support 32-bit guest addresses as signed values.

----------------------------------------------------------------
Alex Bennée (1):
      tcg/optimize: only read val after const check

Richard Henderson (28):
      tcg: Add opcodes for vector nand, nor, eqv
      tcg/ppc: Implement vector NAND, NOR, EQV
      tcg/s390x: Implement vector NAND, NOR, EQV
      tcg/i386: Detect AVX512
      tcg/i386: Add tcg_out_evex_opc
      tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
      tcg/i386: Implement avx512 variable shifts
      tcg/i386: Implement avx512 scalar shift
      tcg/i386: Implement avx512 immediate sari shift
      tcg/i386: Implement avx512 immediate rotate
      tcg/i386: Implement avx512 variable rotate
      tcg/i386: Support avx512vbmi2 vector shift-double instructions
      tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
      tcg/i386: Remove rotls_vec from tcg_target_op_def
      tcg/i386: Expand scalar rotate with avx512 insns
      tcg/i386: Implement avx512 min/max/abs
      tcg/i386: Implement avx512 multiply
      tcg/i386: Implement more logical operations for avx512
      tcg/i386: Implement bitsel for avx512
      tcg: Add TCG_TARGET_SIGNED_ADDR32
      accel/tcg: Split out g2h_tlbe
      accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
      accel/tcg: Add guest_base_signed_addr32 for user-only
      linux-user: Support TCG_TARGET_SIGNED_ADDR32
      tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
      tcg/mips: Support TCG_TARGET_SIGNED_ADDR32
      tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
      tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32

Ziqiao Kong (1):
      tcg: Set MAX_OPC_PARAM_IARGS to 7

include/exec/cpu-all.h            |  20 +-
 include/exec/cpu_ldst.h           |   3 +-
 include/qemu/cpuid.h              |  20 +-
 include/tcg/tcg-opc.h             |   3 +
 include/tcg/tcg.h                 |   5 +-
 tcg/aarch64/tcg-target-sa32.h     |   7 +
 tcg/aarch64/tcg-target.h          |   3 +
 tcg/arm/tcg-target-sa32.h         |   1 +
 tcg/arm/tcg-target.h              |   3 +
 tcg/i386/tcg-target-con-set.h     |   1 +
 tcg/i386/tcg-target-sa32.h        |   1 +
 tcg/i386/tcg-target.h             |  17 +-
 tcg/i386/tcg-target.opc.h         |   3 +
 tcg/loongarch64/tcg-target-sa32.h |   1 +
 tcg/mips/tcg-target-sa32.h        |   9 +
 tcg/ppc/tcg-target-sa32.h         |   1 +
 tcg/ppc/tcg-target.h              |   3 +
 tcg/riscv/tcg-target-sa32.h       |   5 +
 tcg/s390x/tcg-target-sa32.h       |   1 +
 tcg/s390x/tcg-target.h            |   3 +
 tcg/sparc/tcg-target-sa32.h       |   1 +
 tcg/tci/tcg-target-sa32.h         |   1 +
 accel/tcg/cputlb.c                |  36 ++--
 bsd-user/main.c                   |   4 +
 linux-user/elfload.c              |  62 ++++--
 linux-user/main.c                 |   3 +
 tcg/optimize.c                    |  20 +-
 tcg/tcg-op-vec.c                  |  27 ++-
 tcg/tcg.c                         |  10 +
 tcg/aarch64/tcg-target.c.inc      |  81 +++++---
 tcg/i386/tcg-target.c.inc         | 387 +++++++++++++++++++++++++++++++-------
 tcg/loongarch64/tcg-target.c.inc  |  15 +-
 tcg/mips/tcg-target.c.inc         |  10 +-
 tcg/ppc/tcg-target.c.inc          |  15 ++
 tcg/riscv/tcg-target.c.inc        |   8 +-
 tcg/s390x/tcg-target.c.inc        |  17 ++
 tcg/tci/tcg-target.c.inc          |   2 +-
 37 files changed, 640 insertions(+), 169 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-sa32.h
 create mode 100644 tcg/arm/tcg-target-sa32.h
 create mode 100644 tcg/i386/tcg-target-sa32.h
 create mode 100644 tcg/loongarch64/tcg-target-sa32.h
 create mode 100644 tcg/mips/tcg-target-sa32.h
 create mode 100644 tcg/ppc/tcg-target-sa32.h
 create mode 100644 tcg/riscv/tcg-target-sa32.h
 create mode 100644 tcg/s390x/tcg-target-sa32.h
 create mode 100644 tcg/sparc/tcg-target-sa32.h
 create mode 100644 tcg/tci/tcg-target-sa32.h

From: Alex Bennée <alex.bennee@linaro.org>

valgrind pointed out that arg_info()->val can be undefined which will
be the case if the arguments are not constant. The ordering of the
checks will have ensured we never relied on an undefined value but for
the sake of completeness re-order the code to be clear.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/optimize.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tcg/optimize.c b/tcg/optimize.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -XXX,XX +XXX,XX @@ static bool do_constant_folding_cond_eq(TCGCond c)
 static int do_constant_folding_cond(TCGType type, TCGArg x,
                                     TCGArg y, TCGCond c)
 {
-    uint64_t xv = arg_info(x)->val;
-    uint64_t yv = arg_info(y)->val;
-
     if (arg_is_const(x) && arg_is_const(y)) {
+        uint64_t xv = arg_info(x)->val;
+        uint64_t yv = arg_info(y)->val;
+
         switch (type) {
         case TCG_TYPE_I32:
             return do_constant_folding_cond_32(xv, yv, c);
@@ -XXX,XX +XXX,XX @@ static int do_constant_folding_cond(TCGType type, TCGArg x,
         }
     } else if (args_are_copies(x, y)) {
         return do_constant_folding_cond_eq(c);
-    } else if (arg_is_const(y) && yv == 0) {
+    } else if (arg_is_const(y) && arg_info(y)->val == 0) {
         switch (c) {
         case TCG_COND_LTU:
             return 0;
-- 
2.25.1

From: Ziqiao Kong <ziqiaokong@gmail.com>

The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
thus the MAX_OPC_PARAM_IARGS should be 7.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com>
Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h        | 2 +-
 tcg/tci/tcg-target.c.inc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@
 #else
 #define MAX_OPC_PARAM_PER_ARG 1
 #endif
-#define MAX_OPC_PARAM_IARGS 6
+#define MAX_OPC_PARAM_IARGS 7
 #define MAX_OPC_PARAM_OARGS 1
 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
 
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R0,
 };
 
-#if MAX_OPC_PARAM_IARGS != 6
+#if MAX_OPC_PARAM_IARGS != 7
 # error Fix needed, number of supported input arguments changed!
 #endif
 
-- 
2.25.1

We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-opc.h    |  3 +++
 include/tcg/tcg.h        |  3 +++
 tcg/aarch64/tcg-target.h |  3 +++
 tcg/arm/tcg-target.h     |  3 +++
 tcg/i386/tcg-target.h    |  3 +++
 tcg/ppc/tcg-target.h     |  3 +++
 tcg/s390x/tcg-target.h   |  3 +++
 tcg/optimize.c           | 12 ++++++------
 tcg/tcg-op-vec.c         | 27 ++++++++++++++++++---------
 tcg/tcg.c                |  6 ++++++
 10 files changed, 51 insertions(+), 15 deletions(-)

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -XXX,XX +XXX,XX @@ DEF(or_vec, 1, 2, 0, IMPLVEC)
 DEF(xor_vec, 1, 2, 0, IMPLVEC)
 DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
 DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
+DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec))
+DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec))
+DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec))
 DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
 
 DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_andc_vec         0
 #define TCG_TARGET_HAS_orc_vec          0
+#define TCG_TARGET_HAS_nand_vec         0
+#define TCG_TARGET_HAS_nor_vec          0
+#define TCG_TARGET_HAS_eqv_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 
 #define TCG_TARGET_HAS_andc_vec         1
 #define TCG_TARGET_HAS_orc_vec          1
+#define TCG_TARGET_HAS_nand_vec         0
+#define TCG_TARGET_HAS_nor_vec          0
+#define TCG_TARGET_HAS_eqv_vec          0
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          1
 #define TCG_TARGET_HAS_abs_vec          1
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 
 #define TCG_TARGET_HAS_andc_vec         1
 #define TCG_TARGET_HAS_orc_vec          1
+#define TCG_TARGET_HAS_nand_vec         0
+#define TCG_TARGET_HAS_nor_vec          0
+#define TCG_TARGET_HAS_eqv_vec          0
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          1
 #define TCG_TARGET_HAS_abs_vec          1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
 
 #define TCG_TARGET_HAS_andc_vec         1
 #define TCG_TARGET_HAS_orc_vec          0
+#define TCG_TARGET_HAS_nand_vec         0
+#define TCG_TARGET_HAS_nor_vec          0
+#define TCG_TARGET_HAS_eqv_vec          0
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_abs_vec          1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 
 #define TCG_TARGET_HAS_andc_vec         1
 #define TCG_TARGET_HAS_orc_vec          have_isa_2_07
+#define TCG_TARGET_HAS_nand_vec         0
+#define TCG_TARGET_HAS_nor_vec          0
+#define TCG_TARGET_HAS_eqv_vec          0
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
 #define TCG_TARGET_HAS_abs_vec          0
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
 
 #define TCG_TARGET_HAS_andc_vec       1
 #define TCG_TARGET_HAS_orc_vec        HAVE_FACILITY(VECTOR_ENH1)
+#define TCG_TARGET_HAS_nand_vec       0
+#define TCG_TARGET_HAS_nor_vec        0
+#define TCG_TARGET_HAS_eqv_vec        0
 #define TCG_TARGET_HAS_not_vec        1
 #define TCG_TARGET_HAS_neg_vec        1
 #define TCG_TARGET_HAS_abs_vec        1
diff --git a/tcg/optimize.c b/tcg/optimize.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
     CASE_OP_32_64_VEC(orc):
         return x | ~y;
 
-    CASE_OP_32_64(eqv):
+    CASE_OP_32_64_VEC(eqv):
         return ~(x ^ y);
 
-    CASE_OP_32_64(nand):
+    CASE_OP_32_64_VEC(nand):
         return ~(x & y);
 
-    CASE_OP_32_64(nor):
+    CASE_OP_32_64_VEC(nor):
         return ~(x | y);
 
     case INDEX_op_clz_i32:
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
         case INDEX_op_dup2_vec:
             done = fold_dup2(&ctx, op);
             break;
-        CASE_OP_32_64(eqv):
+        CASE_OP_32_64_VEC(eqv):
             done = fold_eqv(&ctx, op);
             break;
         CASE_OP_32_64(extract):
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
         CASE_OP_32_64(mulu2):
             done = fold_multiply2(&ctx, op);
             break;
-        CASE_OP_32_64(nand):
+        CASE_OP_32_64_VEC(nand):
             done = fold_nand(&ctx, op);
             break;
         CASE_OP_32_64(neg):
             done = fold_neg(&ctx, op);
             break;
-        CASE_OP_32_64(nor):
+        CASE_OP_32_64_VEC(nor):
             done = fold_nor(&ctx, op);
             break;
         CASE_OP_32_64_VEC(not):
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 
 void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 {
-    /* TODO: Add TCG_TARGET_HAS_nand_vec when adding a backend supports it. */
-    tcg_gen_and_vec(0, r, a, b);
-    tcg_gen_not_vec(0, r, r);
+    if (TCG_TARGET_HAS_nand_vec) {
+        vec_gen_op3(INDEX_op_nand_vec, 0, r, a, b);
+    } else {
+        tcg_gen_and_vec(0, r, a, b);
+        tcg_gen_not_vec(0, r, r);
+    }
 }
 
 void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 {
-    /* TODO: Add TCG_TARGET_HAS_nor_vec when adding a backend supports it. */
-    tcg_gen_or_vec(0, r, a, b);
-    tcg_gen_not_vec(0, r, r);
+    if (TCG_TARGET_HAS_nor_vec) {
+        vec_gen_op3(INDEX_op_nor_vec, 0, r, a, b);
+    } else {
+        tcg_gen_or_vec(0, r, a, b);
+        tcg_gen_not_vec(0, r, r);
+    }
 }
 
 void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
 {
-    /* TODO: Add TCG_TARGET_HAS_eqv_vec when adding a backend supports it. */
-    tcg_gen_xor_vec(0, r, a, b);
-    tcg_gen_not_vec(0, r, r);
+    if (TCG_TARGET_HAS_eqv_vec) {
+        vec_gen_op3(INDEX_op_eqv_vec, 0, r, a, b);
+    } else {
+        tcg_gen_xor_vec(0, r, a, b);
+        tcg_gen_not_vec(0, r, r);
+    }
 }
 
 static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
         return have_vec && TCG_TARGET_HAS_andc_vec;
     case INDEX_op_orc_vec:
         return have_vec && TCG_TARGET_HAS_orc_vec;
+    case INDEX_op_nand_vec:
+        return have_vec && TCG_TARGET_HAS_nand_vec;
+    case INDEX_op_nor_vec:
+        return have_vec && TCG_TARGET_HAS_nor_vec;
+    case INDEX_op_eqv_vec:
+        return have_vec && TCG_TARGET_HAS_eqv_vec;
     case INDEX_op_mul_vec:
         return have_vec && TCG_TARGET_HAS_mul_vec;
     case INDEX_op_shli_vec:
-- 
2.25.1

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target.h     |  6 +++---
 tcg/ppc/tcg-target.c.inc | 15 +++++++++++++++
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 
 #define TCG_TARGET_HAS_andc_vec         1
 #define TCG_TARGET_HAS_orc_vec          have_isa_2_07
-#define TCG_TARGET_HAS_nand_vec         0
-#define TCG_TARGET_HAS_nor_vec          0
-#define TCG_TARGET_HAS_eqv_vec          0
+#define TCG_TARGET_HAS_nand_vec         have_isa_2_07
+#define TCG_TARGET_HAS_nor_vec          1
+#define TCG_TARGET_HAS_eqv_vec          have_isa_2_07
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          have_isa_3_00
 #define TCG_TARGET_HAS_abs_vec          0
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_xor_vec:
     case INDEX_op_andc_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_nor_vec:
+    case INDEX_op_eqv_vec:
+    case INDEX_op_nand_vec:
         return 1;
     case INDEX_op_orc_vec:
         return have_isa_2_07;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_orc_vec:
         insn = VORC;
         break;
+    case INDEX_op_nand_vec:
+        insn = VNAND;
+        break;
+    case INDEX_op_nor_vec:
+        insn = VNOR;
+        break;
+    case INDEX_op_eqv_vec:
+        insn = VEQV;
+        break;
 
     case INDEX_op_cmp_vec:
         switch (args[3]) {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_xor_vec:
     case INDEX_op_andc_vec:
     case INDEX_op_orc_vec:
+    case INDEX_op_nor_vec:
+    case INDEX_op_eqv_vec:
+    case INDEX_op_nand_vec:
     case INDEX_op_cmp_vec:
     case INDEX_op_ssadd_vec:
     case INDEX_op_sssub_vec:
-- 
2.25.1

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.h     |  6 +++---
 tcg/s390x/tcg-target.c.inc | 17 +++++++++++++++++
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
 
 #define TCG_TARGET_HAS_andc_vec       1
 #define TCG_TARGET_HAS_orc_vec        HAVE_FACILITY(VECTOR_ENH1)
-#define TCG_TARGET_HAS_nand_vec       0
-#define TCG_TARGET_HAS_nor_vec        0
-#define TCG_TARGET_HAS_eqv_vec        0
+#define TCG_TARGET_HAS_nand_vec       HAVE_FACILITY(VECTOR_ENH1)
+#define TCG_TARGET_HAS_nor_vec        1
+#define TCG_TARGET_HAS_eqv_vec        HAVE_FACILITY(VECTOR_ENH1)
 #define TCG_TARGET_HAS_not_vec        1
 #define TCG_TARGET_HAS_neg_vec        1
 #define TCG_TARGET_HAS_abs_vec        1
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
     VRRc_VMXL   = 0xe7fd,
     VRRc_VN     = 0xe768,
     VRRc_VNC    = 0xe769,
+    VRRc_VNN    = 0xe76e,
     VRRc_VNO    = 0xe76b,
+    VRRc_VNX    = 0xe76c,
     VRRc_VO     = 0xe76a,
     VRRc_VOC    = 0xe76f,
     VRRc_VPKS   = 0xe797,   /* we leave the m5 cs field 0 */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
         break;
+    case INDEX_op_nand_vec:
+        tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0);
+        break;
+    case INDEX_op_nor_vec:
+        tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0);
+        break;
+    case INDEX_op_eqv_vec:
+        tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0);
+        break;
 
     case INDEX_op_shli_vec:
         tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_and_vec:
     case INDEX_op_andc_vec:
     case INDEX_op_bitsel_vec:
+    case INDEX_op_eqv_vec:
+    case INDEX_op_nand_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_nor_vec:
     case INDEX_op_not_vec:
     case INDEX_op_or_vec:
     case INDEX_op_orc_vec:
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_or_vec:
     case INDEX_op_orc_vec:
     case INDEX_op_xor_vec:
+    case INDEX_op_nand_vec:
+    case INDEX_op_nor_vec:
+    case INDEX_op_eqv_vec:
     case INDEX_op_cmp_vec:
     case INDEX_op_mul_vec:
     case INDEX_op_rotlv_vec:
-- 
2.25.1

There are some operation sizes in some subsets of AVX512 that
are missing from previous iterations of AVX.  Detect them.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/qemu/cpuid.h      | 20 +++++++++++++++++---
 tcg/i386/tcg-target.h     |  4 ++++
 tcg/i386/tcg-target.c.inc | 24 ++++++++++++++++++++++--
 3 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/cpuid.h
+++ b/include/qemu/cpuid.h
@@ -XXX,XX +XXX,XX @@
 #ifndef bit_AVX2
 #define bit_AVX2        (1 << 5)
 #endif
-#ifndef bit_AVX512F
-#define bit_AVX512F        (1 << 16)
-#endif
 #ifndef bit_BMI2
 #define bit_BMI2        (1 << 8)
 #endif
+#ifndef bit_AVX512F
+#define bit_AVX512F     (1 << 16)
+#endif
+#ifndef bit_AVX512DQ
+#define bit_AVX512DQ    (1 << 17)
+#endif
+#ifndef bit_AVX512BW
+#define bit_AVX512BW    (1 << 30)
+#endif
+#ifndef bit_AVX512VL
+#define bit_AVX512VL    (1u << 31)
+#endif
+
+/* Leaf 7, %ecx */
+#ifndef bit_AVX512VBMI2
+#define bit_AVX512VBMI2 (1 << 6)
+#endif
 
 /* Leaf 0x80000001, %ecx */
 #ifndef bit_LZCNT
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_bmi1;
 extern bool have_popcnt;
 extern bool have_avx1;
 extern bool have_avx2;
+extern bool have_avx512bw;
+extern bool have_avx512dq;
+extern bool have_avx512vbmi2;
+extern bool have_avx512vl;
 extern bool have_movbe;
 
 /* optional instructions */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ bool have_bmi1;
 bool have_popcnt;
 bool have_avx1;
 bool have_avx2;
+bool have_avx512bw;
+bool have_avx512dq;
+bool have_avx512vbmi2;
+bool have_avx512vl;
 bool have_movbe;
 
 #ifdef CONFIG_CPUID_H
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
 static void tcg_target_init(TCGContext *s)
 {
 #ifdef CONFIG_CPUID_H
-    unsigned a, b, c, d, b7 = 0;
+    unsigned a, b, c, d, b7 = 0, c7 = 0;
     unsigned max = __get_cpuid_max(0, 0);
 
     if (max >= 7) {
         /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs.  */
-        __cpuid_count(7, 0, a, b7, c, d);
+        __cpuid_count(7, 0, a, b7, c7, d);
         have_bmi1 = (b7 & bit_BMI) != 0;
         have_bmi2 = (b7 & bit_BMI2) != 0;
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
             if ((xcrl & 6) == 6) {
                 have_avx1 = (c & bit_AVX) != 0;
                 have_avx2 = (b7 & bit_AVX2) != 0;
+
+                /*
+                 * There are interesting instructions in AVX512, so long
+                 * as we have AVX512VL, which indicates support for EVEX
+                 * on sizes smaller than 512 bits.  We are required to
+                 * check that OPMASK and all extended ZMM state are enabled
+                 * even if we're not using them -- the insns will fault.
+                 */
+                if ((xcrl & 0xe0) == 0xe0
+                    && (b7 & bit_AVX512F)
+                    && (b7 & bit_AVX512VL)) {
+                    have_avx512vl = true;
+                    have_avx512bw = (b7 & bit_AVX512BW) != 0;
+                    have_avx512dq = (b7 & bit_AVX512DQ) != 0;
+                    have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0;
+                }
             }
         }
     }
-- 
2.25.1

The evex encoding is added here, for use in a subsequent patch.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 51 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)

The condition for UMIN/UMAX availability is about to change;
use the canonical version.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
         fixup = NEED_SWAP | NEED_INV;
         break;
     case TCG_COND_LEU:
-        if (vece <= MO_32) {
+        if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) {
             fixup = NEED_UMIN;
         } else {
             fixup = NEED_BIAS | NEED_INV;
         }
         break;
     case TCG_COND_GTU:
-        if (vece <= MO_32) {
+        if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) {
             fixup = NEED_UMIN | NEED_INV;
         } else {
             fixup = NEED_BIAS;
         }
         break;
     case TCG_COND_GEU:
-        if (vece <= MO_32) {
+        if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) {
             fixup = NEED_UMAX;
         } else {
             fixup = NEED_BIAS | NEED_SWAP | NEED_INV;
         }
         break;
     case TCG_COND_LTU:
-        if (vece <= MO_32) {
+        if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) {
             fixup = NEED_UMAX | NEED_INV;
         } else {
             fixup = NEED_BIAS | NEED_SWAP;
-- 
2.25.1

AVX512VL has VPSRAVQ, and
AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
 #define OPC_VPERMQ      (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
 #define OPC_VPERM2I128  (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPSLLVW     (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSLLVD     (0x47 | P_EXT38 | P_DATA16)
 #define OPC_VPSLLVQ     (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
+#define OPC_VPSRAVW     (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSRAVD     (0x46 | P_EXT38 | P_DATA16)
+#define OPC_VPSRAVQ     (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSRLVW     (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSRLVD     (0x45 | P_EXT38 | P_DATA16)
 #define OPC_VPSRLVQ     (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
 #define OPC_VZEROUPPER  (0x77 | P_EXT)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
     };
     static int const shlv_insn[4] = {
-        /* TODO: AVX512 adds support for MO_16.  */
-        OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
+        OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
     };
     static int const shrv_insn[4] = {
-        /* TODO: AVX512 adds support for MO_16.  */
-        OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
+        OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ
     };
     static int const sarv_insn[4] = {
-        /* TODO: AVX512 adds support for MO_16, MO_64.  */
-        OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
+        OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ
     };
     static int const shls_insn[4] = {
         OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 
     case INDEX_op_shlv_vec:
     case INDEX_op_shrv_vec:
-        return have_avx2 && vece >= MO_32;
+        switch (vece) {
+        case MO_16:
+            return have_avx512bw;
+        case MO_32:
+        case MO_64:
+            return have_avx2;
+        }
+        return 0;
     case INDEX_op_sarv_vec:
-        return have_avx2 && vece == MO_32;
+        switch (vece) {
+        case MO_16:
+            return have_avx512bw;
+        case MO_32:
+            return have_avx2;
+        case MO_64:
+            return have_avx512vl;
+        }
+        return 0;
     case INDEX_op_rotlv_vec:
     case INDEX_op_rotrv_vec:
         return have_avx2 && vece >= MO_32 ? -1 : 0;
-- 
2.25.1

AVX512VL has VPSRAQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

AVX512 has VPSRAQ with immediate operand, in the same form as
with AVX, but requires EVEX encoding and W1.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         break;
 
     case INDEX_op_shli_vec:
+        insn = shift_imm_insn[vece];
         sub = 6;
         goto gen_shift;
     case INDEX_op_shri_vec:
+        insn = shift_imm_insn[vece];
         sub = 2;
         goto gen_shift;
     case INDEX_op_sari_vec:
-        tcg_debug_assert(vece != MO_64);
+        if (vece == MO_64) {
+            insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX;
+        } else {
+            insn = shift_imm_insn[vece];
+        }
         sub = 4;
     gen_shift:
         tcg_debug_assert(vece != MO_8);
-        insn = shift_imm_insn[vece];
         if (type == TCG_TYPE_V256) {
             insn |= P_VEXL;
         }
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
         return vece == MO_8 ? -1 : 1;
 
     case INDEX_op_sari_vec:
-        /* We must expand the operation for MO_8.  */
-        if (vece == MO_8) {
+        switch (vece) {
+        case MO_8:
             return -1;
-        }
-        /* We can emulate this for MO_64, but it does not pay off
-           unless we're producing at least 4 values.  */
-        if (vece == MO_64) {
+        case MO_16:
+        case MO_32:
+            return 1;
+        case MO_64:
+            if (have_avx512vl) {
+                return 1;
+            }
+            /*
+             * We can emulate this for MO_64, but it does not pay off
+             * unless we're producing at least 4 values.
+             */
             return type >= TCG_TYPE_V256 ? -1 : 0;
         }
-        return 1;
+        return 0;
 
     case INDEX_op_shls_vec:
     case INDEX_op_shrs_vec:
-- 
2.25.1

AVX512VL has VPROLD and VPROLQ, layered onto the same
opcode as PSHIFTD, but requires EVEX encoding and W1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.h     |  2 +-
 tcg/i386/tcg-target.c.inc | 15 +++++++++++++--
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_abs_vec          1
-#define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_roti_vec         have_avx512vl
 #define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          1
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_PSHUFLW     (0x70 | P_EXT | P_SIMDF2)
 #define OPC_PSHUFHW     (0x70 | P_EXT | P_SIMDF3)
 #define OPC_PSHIFTW_Ib  (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
-#define OPC_PSHIFTD_Ib  (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTD_Ib  (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */
 #define OPC_PSHIFTQ_Ib  (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
 #define OPC_PSLLW       (0xf1 | P_EXT | P_DATA16)
 #define OPC_PSLLD       (0xf2 | P_EXT | P_DATA16)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
             insn = shift_imm_insn[vece];
         }
         sub = 4;
+        goto gen_shift;
+    case INDEX_op_rotli_vec:
+        insn = OPC_PSHIFTD_Ib | P_EVEX;  /* VPROL[DQ] */
+        if (vece == MO_64) {
+            insn |= P_VEXW;
+        }
+        sub = 1;
+        goto gen_shift;
     gen_shift:
         tcg_debug_assert(vece != MO_8);
         if (type == TCG_TYPE_V256) {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
+    case INDEX_op_rotli_vec:
     case INDEX_op_x86_psrldq_vec:
         return C_O1_I1(x, x);
 
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_xor_vec:
     case INDEX_op_andc_vec:
         return 1;
-    case INDEX_op_rotli_vec:
     case INDEX_op_cmp_vec:
     case INDEX_op_cmpsel_vec:
         return -1;
 
+    case INDEX_op_rotli_vec:
+        return have_avx512vl && vece >= MO_32 ? 1 : -1;
+
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
         /* We must expand the operation for MO_8.  */
-- 
2.25.1

AVX512VL has VPROLVD and VPRORVQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.h     |  2 +-
 tcg/i386/tcg-target.c.inc | 25 ++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
 #define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_roti_vec         have_avx512vl
 #define TCG_TARGET_HAS_rots_vec         0
-#define TCG_TARGET_HAS_rotv_vec         0
+#define TCG_TARGET_HAS_rotv_vec         have_avx512vl
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
 #define TCG_TARGET_HAS_shv_vec          have_avx2
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
 #define OPC_VPERMQ      (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
 #define OPC_VPERM2I128  (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPROLVD     (0x15 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPROLVQ     (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPRORVD     (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPRORVQ     (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSLLVW     (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSLLVD     (0x47 | P_EXT38 | P_DATA16)
 #define OPC_VPSLLVQ     (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     static int const umax_insn[4] = {
         OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
     };
+    static int const rotlv_insn[4] = {
+        OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
+    };
+    static int const rotrv_insn[4] = {
+        OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ
+    };
     static int const shlv_insn[4] = {
         OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
     };
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sarv_vec:
         insn = sarv_insn[vece];
         goto gen_simd;
+    case INDEX_op_rotlv_vec:
+        insn = rotlv_insn[vece];
+        goto gen_simd;
+    case INDEX_op_rotrv_vec:
+        insn = rotrv_insn[vece];
+        goto gen_simd;
     case INDEX_op_shls_vec:
         insn = shls_insn[vece];
         goto gen_simd;
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shlv_vec:
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
     case INDEX_op_shls_vec:
     case INDEX_op_shrs_vec:
     case INDEX_op_sars_vec:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
         return 0;
     case INDEX_op_rotlv_vec:
     case INDEX_op_rotrv_vec:
-        return have_avx2 && vece >= MO_32 ? -1 : 0;
+        switch (vece) {
+        case MO_32:
+        case MO_64:
+            return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
+        }
+        return 0;
 
     case INDEX_op_mul_vec:
         if (vece == MO_8) {
-- 
2.25.1

We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target-con-set.h |  1 +
 tcg/i386/tcg-target.opc.h     |  3 +++
 tcg/i386/tcg-target.c.inc     | 38 +++++++++++++++++++++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target-con-set.h
+++ b/tcg/i386/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rI)
 C_O1_I2(x, x, x)
 C_N1_I2(r, r, r)
 C_N1_I2(r, r, rW)
+C_O1_I3(x, 0, x, x)
 C_O1_I3(x, x, x, x)
 C_O1_I4(r, r, re, r, 0)
 C_O1_I4(r, r, r, ri, ri)
diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.opc.h
+++ b/tcg/i386/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@ DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
 DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
 DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
 DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_vpshldi_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_vpshldv_vec, 1, 3, 0, IMPLVEC)
+DEF(x86_vpshrdv_vec, 1, 3, 0, IMPLVEC)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_VPROLVQ     (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPRORVD     (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
 #define OPC_VPRORVQ     (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDW     (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDD     (0x71 | P_EXT3A | P_DATA16 | P_EVEX)
+#define OPC_VPSHLDQ     (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDVW    (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDVD    (0x71 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPSHLDVQ    (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHRDVW    (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHRDVD    (0x73 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPSHRDVQ    (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSLLVW     (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSLLVD     (0x47 | P_EXT38 | P_DATA16)
 #define OPC_VPSLLVQ     (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     static int const sars_insn[4] = {
         OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ
     };
+    static int const vpshldi_insn[4] = {
+        OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ
+    };
+    static int const vpshldv_insn[4] = {
+        OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ
+    };
+    static int const vpshrdv_insn[4] = {
+        OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ
+    };
     static int const abs_insn[4] = {
         /* TODO: AVX512 adds support for MO_64.  */
         OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_x86_packus_vec:
         insn = packus_insn[vece];
         goto gen_simd;
+    case INDEX_op_x86_vpshldv_vec:
+        insn = vpshldv_insn[vece];
+        a1 = a2;
+        a2 = args[3];
+        goto gen_simd;
+    case INDEX_op_x86_vpshrdv_vec:
+        insn = vpshrdv_insn[vece];
+        a1 = a2;
+        a2 = args[3];
+        goto gen_simd;
 #if TCG_TARGET_REG_BITS == 32
     case INDEX_op_dup2_vec:
         /* First merge the two 32-bit inputs to a single 64-bit element. */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         insn = OPC_VPERM2I128;
         sub = args[3];
         goto gen_simd_imm8;
+    case INDEX_op_x86_vpshldi_vec:
+        insn = vpshldi_insn[vece];
+        sub = args[3];
+        goto gen_simd_imm8;
     gen_simd_imm8:
+        tcg_debug_assert(insn != OPC_UD2);
         if (type == TCG_TYPE_V256) {
             insn |= P_VEXL;
         }
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_x86_vperm2i128_vec:
     case INDEX_op_x86_punpckl_vec:
     case INDEX_op_x86_punpckh_vec:
+    case INDEX_op_x86_vpshldi_vec:
 #if TCG_TARGET_REG_BITS == 32
     case INDEX_op_dup2_vec:
 #endif
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_x86_psrldq_vec:
         return C_O1_I1(x, x);
 
+    case INDEX_op_x86_vpshldv_vec:
+    case INDEX_op_x86_vpshrdv_vec:
+        return C_O1_I3(x, 0, x, x);
+
     case INDEX_op_x86_vpblendvb_vec:
         return C_O1_I3(x, x, x, x);
 
-- 
2.25.1

While there are no specific 16-bit rotate instructions, there
are double-word shifts, which can perform the same operation.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_rotlv_vec:
     case INDEX_op_rotrv_vec:
         switch (vece) {
+        case MO_16:
+            return have_avx512vbmi2 ? -1 : 0;
         case MO_32:
         case MO_64:
             return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotli(TCGType type, unsigned vece,
         return;
     }
 
+    if (have_avx512vbmi2) {
+        vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece,
+                  tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm);
+        return;
+    }
+
     t = tcg_temp_new_vec(type);
     tcg_gen_shli_vec(vece, t, v1, imm);
     tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotls(TCGType type, unsigned vece,
 static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
                             TCGv_vec v1, TCGv_vec sh, bool right)
 {
-    TCGv_vec t = tcg_temp_new_vec(type);
+    TCGv_vec t;
 
+    if (have_avx512vbmi2) {
+        vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec,
+                  type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(sh));
+        return;
+    }
+
+    t = tcg_temp_new_vec(type);
     tcg_gen_dupi_vec(vece, t, 8 << vece);
     tcg_gen_sub_vec(vece, t, t, sh);
     if (right) {
-- 
2.25.1

Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V;
expand 16-bit scalar rotate with VPSHLDV.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++----------------
 1 file changed, 29 insertions(+), 20 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotli(TCGType type, unsigned vece,
     tcg_temp_free_vec(t);
 }
 
-static void expand_vec_rotls(TCGType type, unsigned vece,
-                             TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
-{
-    TCGv_i32 rsh;
-    TCGv_vec t;
-
-    tcg_debug_assert(vece != MO_8);
-
-    t = tcg_temp_new_vec(type);
-    rsh = tcg_temp_new_i32();
-
-    tcg_gen_neg_i32(rsh, lsh);
-    tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
-    tcg_gen_shls_vec(vece, t, v1, lsh);
-    tcg_gen_shrs_vec(vece, v0, v1, rsh);
-    tcg_gen_or_vec(vece, v0, v0, t);
-    tcg_temp_free_vec(t);
-    tcg_temp_free_i32(rsh);
-}
-
 static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
                             TCGv_vec v1, TCGv_vec sh, bool right)
 {
@@ -XXX,XX +XXX,XX @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
     tcg_temp_free_vec(t);
 }
 
+static void expand_vec_rotls(TCGType type, unsigned vece,
+                             TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
+{
+    TCGv_vec t = tcg_temp_new_vec(type);
+
+    tcg_debug_assert(vece != MO_8);
+
+    if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) {
+        tcg_gen_dup_i32_vec(vece, t, lsh);
+        if (vece >= MO_32) {
+            tcg_gen_rotlv_vec(vece, v0, v1, t);
+        } else {
+            expand_vec_rotv(type, vece, v0, v1, t, false);
+        }
+    } else {
+        TCGv_i32 rsh = tcg_temp_new_i32();
+
+        tcg_gen_neg_i32(rsh, lsh);
+        tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
+        tcg_gen_shls_vec(vece, t, v1, lsh);
+        tcg_gen_shrs_vec(vece, v0, v1, rsh);
+        tcg_gen_or_vec(vece, v0, v0, t);
+
+        tcg_temp_free_i32(rsh);
+    }
+
+    tcg_temp_free_vec(t);
+}
+
 static void expand_vec_mul(TCGType type, unsigned vece,
                            TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
 {
-- 
2.25.1

AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_PABSB       (0x1c | P_EXT38 | P_DATA16)
 #define OPC_PABSW       (0x1d | P_EXT38 | P_DATA16)
 #define OPC_PABSD       (0x1e | P_EXT38 | P_DATA16)
+#define OPC_VPABSQ      (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_PACKSSDW    (0x6b | P_EXT | P_DATA16)
 #define OPC_PACKSSWB    (0x63 | P_EXT | P_DATA16)
 #define OPC_PACKUSDW    (0x2b | P_EXT38 | P_DATA16)
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_PMAXSB      (0x3c | P_EXT38 | P_DATA16)
 #define OPC_PMAXSW      (0xee | P_EXT | P_DATA16)
 #define OPC_PMAXSD      (0x3d | P_EXT38 | P_DATA16)
+#define OPC_VPMAXSQ     (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_PMAXUB      (0xde | P_EXT | P_DATA16)
 #define OPC_PMAXUW      (0x3e | P_EXT38 | P_DATA16)
 #define OPC_PMAXUD      (0x3f | P_EXT38 | P_DATA16)
+#define OPC_VPMAXUQ     (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_PMINSB      (0x38 | P_EXT38 | P_DATA16)
 #define OPC_PMINSW      (0xea | P_EXT | P_DATA16)
 #define OPC_PMINSD      (0x39 | P_EXT38 | P_DATA16)
+#define OPC_VPMINSQ     (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_PMINUB      (0xda | P_EXT | P_DATA16)
 #define OPC_PMINUW      (0x3a | P_EXT38 | P_DATA16)
 #define OPC_PMINUD      (0x3b | P_EXT38 | P_DATA16)
+#define OPC_VPMINUQ     (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_PMOVSXBW    (0x20 | P_EXT38 | P_DATA16)
 #define OPC_PMOVSXWD    (0x23 | P_EXT38 | P_DATA16)
 #define OPC_PMOVSXDQ    (0x25 | P_EXT38 | P_DATA16)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
     };
     static int const smin_insn[4] = {
-        OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2
+        OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ
     };
     static int const smax_insn[4] = {
-        OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2
+        OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ
     };
     static int const umin_insn[4] = {
-        OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2
+        OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ
     };
     static int const umax_insn[4] = {
-        OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
+        OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ
     };
     static int const rotlv_insn[4] = {
         OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ
     };
     static int const abs_insn[4] = {
-        /* TODO: AVX512 adds support for MO_64.  */
-        OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
+        OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ
     };
 
     TCGType type = vecl + TCG_TYPE_V64;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_umin_vec:
     case INDEX_op_umax_vec:
     case INDEX_op_abs_vec:
-        return vece <= MO_32;
+        return vece <= MO_32 || have_avx512vl;
 
     default:
         return 0;
-- 
2.25.1

AVX512DQ has VPMULLQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

AVX512VL has a general ternary logic operation, VPTERNLOGQ,
which can implement NOT, ORC, NAND, NOR, EQV.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.h     | 10 +++++-----
 tcg/i386/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_movbe;
 #define TCG_TARGET_HAS_v256             have_avx2
 
 #define TCG_TARGET_HAS_andc_vec         1
-#define TCG_TARGET_HAS_orc_vec          0
-#define TCG_TARGET_HAS_nand_vec         0
-#define TCG_TARGET_HAS_nor_vec          0
-#define TCG_TARGET_HAS_eqv_vec          0
-#define TCG_TARGET_HAS_not_vec          0
+#define TCG_TARGET_HAS_orc_vec          have_avx512vl
+#define TCG_TARGET_HAS_nand_vec         have_avx512vl
+#define TCG_TARGET_HAS_nor_vec          have_avx512vl
+#define TCG_TARGET_HAS_eqv_vec          have_avx512vl
+#define TCG_TARGET_HAS_not_vec          have_avx512vl
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_roti_vec         have_avx512vl
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 #define OPC_VPSRLVW     (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VPSRLVD     (0x45 | P_EXT38 | P_DATA16)
 #define OPC_VPSRLVQ     (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
+#define OPC_VPTERNLOGQ  (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
 #define OPC_VZEROUPPER  (0x77 | P_EXT)
 #define OPC_XCHG_ax_r32	(0x90)
 
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         insn = vpshldi_insn[vece];
         sub = args[3];
         goto gen_simd_imm8;
+
+    case INDEX_op_not_vec:
+        insn = OPC_VPTERNLOGQ;
+        a2 = a1;
+        sub = 0x33; /* !B */
+        goto gen_simd_imm8;
+    case INDEX_op_nor_vec:
+        insn = OPC_VPTERNLOGQ;
+        sub = 0x11; /* norCB */
+        goto gen_simd_imm8;
+    case INDEX_op_nand_vec:
+        insn = OPC_VPTERNLOGQ;
+        sub = 0x77; /* nandCB */
+        goto gen_simd_imm8;
+    case INDEX_op_eqv_vec:
+        insn = OPC_VPTERNLOGQ;
+        sub = 0x99; /* xnorCB */
+        goto gen_simd_imm8;
+    case INDEX_op_orc_vec:
+        insn = OPC_VPTERNLOGQ;
+        sub = 0xdd; /* orB!C */
+        goto gen_simd_imm8;
+
     gen_simd_imm8:
         tcg_debug_assert(insn != OPC_UD2);
         if (type == TCG_TYPE_V256) {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_or_vec:
     case INDEX_op_xor_vec:
     case INDEX_op_andc_vec:
+    case INDEX_op_orc_vec:
+    case INDEX_op_nand_vec:
+    case INDEX_op_nor_vec:
+    case INDEX_op_eqv_vec:
     case INDEX_op_ssadd_vec:
     case INDEX_op_usadd_vec:
     case INDEX_op_sssub_vec:
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_abs_vec:
     case INDEX_op_dup_vec:
+    case INDEX_op_not_vec:
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_or_vec:
     case INDEX_op_xor_vec:
     case INDEX_op_andc_vec:
+    case INDEX_op_orc_vec:
+    case INDEX_op_nand_vec:
+    case INDEX_op_nor_vec:
+    case INDEX_op_eqv_vec:
+    case INDEX_op_not_vec:
         return 1;
     case INDEX_op_cmp_vec:
     case INDEX_op_cmpsel_vec:
-- 
2.25.1

The general ternary logic operation can implement BITSEL.
Funnel the 4-operand operation into three variants of the
3-operand instruction, depending on input operand overlap.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.h     |  2 +-
 tcg/i386/tcg-target.c.inc | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

Define as 0 for all tcg hosts.  Put this in a separate header,
because we'll want this in places that do not ordinarily have
access to all of tcg/tcg.h.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target-sa32.h     | 1 +
 tcg/arm/tcg-target-sa32.h         | 1 +
 tcg/i386/tcg-target-sa32.h        | 1 +
 tcg/loongarch64/tcg-target-sa32.h | 1 +
 tcg/mips/tcg-target-sa32.h        | 1 +
 tcg/ppc/tcg-target-sa32.h         | 1 +
 tcg/riscv/tcg-target-sa32.h       | 1 +
 tcg/s390x/tcg-target-sa32.h       | 1 +
 tcg/sparc/tcg-target-sa32.h       | 1 +
 tcg/tci/tcg-target-sa32.h         | 1 +
 tcg/tcg.c                         | 4 ++++
 11 files changed, 14 insertions(+)
 create mode 100644 tcg/aarch64/tcg-target-sa32.h
 create mode 100644 tcg/arm/tcg-target-sa32.h
 create mode 100644 tcg/i386/tcg-target-sa32.h
 create mode 100644 tcg/loongarch64/tcg-target-sa32.h
 create mode 100644 tcg/mips/tcg-target-sa32.h
 create mode 100644 tcg/ppc/tcg-target-sa32.h
 create mode 100644 tcg/riscv/tcg-target-sa32.h
 create mode 100644 tcg/s390x/tcg-target-sa32.h
 create mode 100644 tcg/sparc/tcg-target-sa32.h
 create mode 100644 tcg/tci/tcg-target-sa32.h

diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/aarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/arm/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/i386/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/loongarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/mips/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/ppc/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/s390x/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/sparc/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/tci/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/log.h"
 #include "tcg/tcg-ldst.h"
 #include "tcg-internal.h"
+#include "tcg-target-sa32.h"
+
+/* Sanity check for TCG_TARGET_SIGNED_ADDR32. */
+QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS == 32 && TCG_TARGET_SIGNED_ADDR32);
 
 #ifdef CONFIG_TCG_INTERPRETER
 #include <ffi.h>
-- 
2.25.1

Create a new function to combine a CPUTLBEntry addend
with the guest address to form a host address.

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
     return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
 }
 
+static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
+{
+    return tlb->addend + (uintptr_t)gaddr;
+}
+
 static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
                              size_t max_entries)
 {
@@ -XXX,XX +XXX,XX @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
 
     if ((addr & (TLB_INVALID_MASK | TLB_MMIO |
                  TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) {
-        addr &= TARGET_PAGE_MASK;
-        addr += tlb_entry->addend;
+        addr = g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK);
         if ((addr - start) < length) {
 #if TCG_OVERSIZED_GUEST
             tlb_entry->addr_write |= TLB_NOTDIRTY;
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
         return -1;
     }
 
-    p = (void *)((uintptr_t)addr + entry->addend);
+    p = (void *)g2h_tlbe(entry, addr);
     if (hostp) {
         *hostp = p;
     }
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     }
 
     /* Everything else is RAM. */
-    *phost = (void *)((uintptr_t)addr + entry->addend);
+    *phost = (void *)g2h_tlbe(entry, addr);
     return flags;
 }
 
@@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
             data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
         } else {
             data->is_io = false;
-            data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
+            data->v.ram.hostaddr = (void *)g2h_tlbe(tlbe, addr);
         }
         return true;
     } else {
@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
         goto stop_the_world;
     }
 
-    hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
+    hostaddr = (void *)g2h_tlbe(tlbe, addr);
 
     if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
         notdirty_write(env_cpu(env), addr, size,
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
                             access_type, op ^ (need_swap * MO_BSWAP));
         }
 
-        haddr = (void *)((uintptr_t)addr + entry->addend);
+        haddr = (void *)g2h_tlbe(entry, addr);
 
         /*
          * Keep these two load_memop separate to ensure that the compiler
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
         return res & MAKE_64BIT_MASK(0, size * 8);
     }
 
-    haddr = (void *)((uintptr_t)addr + entry->addend);
+    haddr = (void *)g2h_tlbe(entry, addr);
     return load_memop(haddr, op);
 }
 
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
             notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
         }
 
-        haddr = (void *)((uintptr_t)addr + entry->addend);
+        haddr = (void *)g2h_tlbe(entry, addr);
 
         /*
          * Keep these two store_memop separate to ensure that the compiler
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
         return;
     }
 
-    haddr = (void *)((uintptr_t)addr + entry->addend);
+    haddr = (void *)g2h_tlbe(entry, addr);
     store_memop(haddr, val, op);
 }
 
-- 
2.25.1

When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
allow the 32-bit guest address to be sign extended within the
64-bit host register instead of zero extended.

This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
which naturally sign-extend 32-bit values, in contrast to x86_64
and AArch64 which zero-extend them.

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/plugin-memory.h"
 #endif
 #include "tcg/tcg-ldst.h"
+#include "tcg-target-sa32.h"
 
 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
 /* #define DEBUG_TLB */
@@ -XXX,XX +XXX,XX @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
 
 static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
 {
+    if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+        return tlb->addend + (int32_t)gaddr;
+    }
     return tlb->addend + (uintptr_t)gaddr;
 }
 
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
     desc->iotlb[index].attrs = attrs;
 
     /* Now calculate the new entry */
-    tn.addend = addend - vaddr_page;
+
+    if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+        tn.addend = addend - (int32_t)vaddr_page;
+    } else {
+        tn.addend = addend - vaddr_page;
+    }
+
     if (prot & PAGE_READ) {
         tn.addr_read = address;
         if (wp_flags & BP_MEM_READ) {
-- 
2.25.1

While the host may prefer to treat 32-bit addresses as signed,
there are edge cases of guests that cannot be implemented with
addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive.

Therefore, default to guest_base_signed_addr32 false, and allow
probe_guest_base to determine whether it is possible to set it
to true.  A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will
have to cope with either setting for user-only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h  | 16 ++++++++++++++++
 include/exec/cpu_ldst.h |  3 ++-
 bsd-user/main.c         |  4 ++++
 linux-user/main.c       |  3 +++
 4 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -XXX,XX +XXX,XX @@ static inline void tswap64s(uint64_t *s)
 
 #if defined(CONFIG_USER_ONLY)
 #include "exec/user/abitypes.h"
+#include "tcg-target-sa32.h"
 
 /* On some host systems the guest address space is reserved on the host.
  * This allows the guest address space to be offset to a convenient location.
@@ -XXX,XX +XXX,XX @@ extern uintptr_t guest_base;
 extern bool have_guest_base;
 extern unsigned long reserved_va;
 
+#if TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32
+extern bool guest_base_signed_addr32;
+#else
+#define guest_base_signed_addr32  false
+#endif
+
+static inline void set_guest_base_signed_addr32(void)
+{
+#ifdef guest_base_signed_addr32
+    qemu_build_not_reached();
+#else
+    guest_base_signed_addr32 = true;
+#endif
+}
+
 /*
  * Limit the guest addresses as best we can.
  *
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -XXX,XX +XXX,XX @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)
 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
 static inline void *g2h_untagged(abi_ptr x)
 {
-    return (void *)((uintptr_t)(x) + guest_base);
+    uintptr_t hx = guest_base_signed_addr32 ? (int32_t)x : (uintptr_t)x;
+    return (void *)(guest_base + hx);
 }
 
 static inline void *g2h(CPUState *cs, abi_ptr x)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index XXXXXXX..XXXXXXX 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -XXX,XX +XXX,XX @@
 int singlestep;
 uintptr_t guest_base;
 bool have_guest_base;
+#ifndef guest_base_signed_addr32
+bool guest_base_signed_addr32;
+#endif
+
 /*
  * When running 32-on-64 we should make sure we can fit all of the possible
  * guest address space into a contiguous chunk of virtual host memory.
diff --git a/linux-user/main.c b/linux-user/main.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -XXX,XX +XXX,XX @@ static const char *seed_optarg;
 unsigned long mmap_min_addr;
 uintptr_t guest_base;
 bool have_guest_base;
+#ifndef guest_base_signed_addr32
+bool guest_base_signed_addr32;
+#endif
 
 /*
  * Used to implement backwards-compatibility for the `-strace`, and
-- 
2.25.1

When using reserved_va, which is the default for a 64-bit host
and a 32-bit guest, set guest_base_signed_addr32 if requested
by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h |  4 ---
 linux-user/elfload.c   | 62 ++++++++++++++++++++++++++++++++++--------
 2 files changed, 50 insertions(+), 16 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -XXX,XX +XXX,XX @@ extern const TargetPageBits target_page;
 #define PAGE_RESET     0x0040
 /* For linux-user, indicates that the page is MAP_ANON. */
 #define PAGE_ANON      0x0080
-
-#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
-/* FIXME: Code that sets/uses this is broken and needs to go away.  */
 #define PAGE_RESERVED  0x0100
-#endif
 /* Target-specific bits that will be used via page_get_flags().  */
 #define PAGE_TARGET_1  0x0200
 #define PAGE_TARGET_2  0x0400
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -XXX,XX +XXX,XX @@ static void pgb_dynamic(const char *image_name, long align)
 static void pgb_reserved_va(const char *image_name, abi_ulong guest_loaddr,
                             abi_ulong guest_hiaddr, long align)
 {
-    int flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE;
+    int flags = (MAP_ANONYMOUS | MAP_PRIVATE |
+                 MAP_NORESERVE | MAP_FIXED_NOREPLACE);
+    unsigned long local_rva = reserved_va;
+    bool protect_wrap = false;
     void *addr, *test;
 
-    if (guest_hiaddr > reserved_va) {
+    if (guest_hiaddr > local_rva) {
         error_report("%s: requires more than reserved virtual "
                      "address space (0x%" PRIx64 " > 0x%lx)",
-                     image_name, (uint64_t)guest_hiaddr, reserved_va);
+                     image_name, (uint64_t)guest_hiaddr, local_rva);
         exit(EXIT_FAILURE);
     }
 
-    /* Widen the "image" to the entire reserved address space. */
-    pgb_static(image_name, 0, reserved_va, align);
+    if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+        if (guest_loaddr < 0x80000000u && guest_hiaddr > 0x80000000u) {
+            /*
+             * The executable itself wraps on signed addresses.
+             * Without per-page translation, we must keep the
+             * guest address 0x7fff_ffff adjacent to 0x8000_0000
+             * consecutive in host memory: unsigned addresses.
+             */
+        } else {
+            set_guest_base_signed_addr32();
+            if (local_rva <= 0x80000000u) {
+                /* No guest addresses are "negative": win! */
+            } else {
+                /* Begin by allocating the entire address space. */
+                local_rva = 0xfffffffful + 1;
+                protect_wrap = true;
+            }
+        }
+    }
 
-    /* osdep.h defines this as 0 if it's missing */
-    flags |= MAP_FIXED_NOREPLACE;
+    /* Widen the "image" to the entire reserved address space. */
+    pgb_static(image_name, 0, local_rva, align);
+    assert(guest_base != 0);
 
     /* Reserve the memory on the host. */
-    assert(guest_base != 0);
     test = g2h_untagged(0);
-    addr = mmap(test, reserved_va, PROT_NONE, flags, -1, 0);
+    addr = mmap(test, local_rva, PROT_NONE, flags, -1, 0);
     if (addr == MAP_FAILED || addr != test) {
+        /*
+         * If protect_wrap, we could try again with the original reserved_va
+         * setting, but the edge case of low ulimit vm setting on a 64-bit
+         * host is probably useless.
+         */
         error_report("Unable to reserve 0x%lx bytes of virtual address "
-                     "space at %p (%s) for use as guest address space (check your"
-                     "virtual memory ulimit setting, min_mmap_addr or reserve less "
-                     "using -R option)", reserved_va, test, strerror(errno));
+                     "space at %p (%s) for use as guest address space "
+                     "(check your virtual memory ulimit setting, "
+                     "min_mmap_addr or reserve less using -R option)",
+                     local_rva, test, strerror(errno));
         exit(EXIT_FAILURE);
     }
 
+    if (protect_wrap) {
+        /*
+         * Prevent the page just before 0x80000000 from being allocated.
+         * This prevents a single guest object/allocation from crossing
+         * the signed wrap, and thus being discontiguous in host memory.
+         */
+        page_set_flags(0x7fffffff & TARGET_PAGE_MASK, 0x80000000u,
+                       PAGE_RESERVED);
+        /* Adjust guest_base so that 0 is in the middle of the reservation. */
+        guest_base += 0x80000000ul;
+    }
+
     qemu_log_mask(CPU_LOG_PAGE, "%s: base @ %p for %lu bytes\n",
                   __func__, addr, reserved_va);
 }
-- 
2.25.1

AArch64 has both sign and zero-extending addressing modes, which
means that either treatment of guest addresses is equally efficient.
Enabling this for AArch64 gives us testing of the feature in CI.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target-sa32.h |  8 +++-
 tcg/aarch64/tcg-target.c.inc  | 81 ++++++++++++++++++++++++-----------
 2 files changed, 64 insertions(+), 25 deletions(-)

diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target-sa32.h
+++ b/tcg/aarch64/tcg-target-sa32.h
@@ -1 +1,7 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+/*
+ * AArch64 has both SXTW and UXTW addressing modes, which means that
+ * it is agnostic to how guest addresses should be represented.
+ * Because aarch64 is more common than the other hosts that will
+ * want to use this feature, enable it for continuous testing.
+ */
+#define TCG_TARGET_SIGNED_ADDR32 1
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     LDST_LD_S_W = 3,  /* load and sign-extend into Wt */
 } AArch64LdstType;
 
+/*
+ * See aarch64/instrs/extendreg/DecodeRegExtend
+ * But note that option<1> == 0 is UNDEFINED for LDR/STR.
+ */
+typedef enum {
+    LDST_EXT_UXTW = 2,  /* zero-extend from uint32_t */
+    LDST_EXT_UXTX = 3,  /* zero-extend from uint64_t (i.e. no extension) */
+    LDST_EXT_SXTW = 6,  /* sign-extend from int32_t */
+} AArch64LdstExt;
+
 /* We encode the format of the insn into the beginning of the name, so that
    we can have the preprocessor help "typecheck" the insn vs the output
    function.  Arm didn't provide us with nice names for the formats, so we
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
 }
 
 static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
-                              TCGReg rd, TCGReg base, TCGType ext,
+                              TCGReg rd, TCGReg base, AArch64LdstExt option,
                               TCGReg regoff)
 {
     /* Note the AArch64Insn constants above are for C3.3.12.  Adjust.  */
     tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
-              0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
+              option << 13 | base << 5 | (rd & 0x1f));
 }
 
 static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
 
     /* Worst-case scenario, move offset to temp register, use reg offset.  */
     tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
-    tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
+    tcg_out_ldst_r(s, insn, rd, rn, LDST_EXT_UXTX, TCG_REG_TMP);
 }
 
 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 
 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
                                    TCGReg data_r, TCGReg addr_r,
-                                   TCGType otype, TCGReg off_r)
+                                   AArch64LdstExt option, TCGReg off_r)
 {
     switch (memop & MO_SSIZE) {
     case MO_UB:
-        tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, option, off_r);
         break;
     case MO_SB:
         tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
-                       data_r, addr_r, otype, off_r);
+                       data_r, addr_r, option, off_r);
         break;
     case MO_UW:
-        tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, option, off_r);
         break;
     case MO_SW:
         tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
-                       data_r, addr_r, otype, off_r);
+                       data_r, addr_r, option, off_r);
         break;
     case MO_UL:
-        tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, option, off_r);
         break;
     case MO_SL:
-        tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, option, off_r);
         break;
     case MO_UQ:
-        tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, option, off_r);
         break;
     default:
         tcg_abort();
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
 
 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
                                    TCGReg data_r, TCGReg addr_r,
-                                   TCGType otype, TCGReg off_r)
+                                   AArch64LdstExt option, TCGReg off_r)
 {
     switch (memop & MO_SIZE) {
     case MO_8:
-        tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, option, off_r);
         break;
     case MO_16:
-        tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, option, off_r);
         break;
     case MO_32:
-        tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, option, off_r);
         break;
     case MO_64:
-        tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
+        tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, option, off_r);
         break;
     default:
         tcg_abort();
     }
 }
 
+/*
+ * Bits for the option field of LDR/STR (register),
+ * for application to a guest address.
+ */
+static AArch64LdstExt ldst_ext_option(void)
+{
+#ifdef CONFIG_USER_ONLY
+    bool signed_addr32 = guest_base_signed_addr32;
+#else
+    bool signed_addr32 = TCG_TARGET_SIGNED_ADDR32;
+#endif
+
+    if (TARGET_LONG_BITS == 64) {
+        return LDST_EXT_UXTX;
+    } else if (signed_addr32) {
+        return LDST_EXT_SXTW;
+    } else {
+        return LDST_EXT_UXTW;
+    }
+}
+
 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
                             MemOpIdx oi, TCGType ext)
 {
     MemOp memop = get_memop(oi);
-    const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+    AArch64LdstExt option = ldst_ext_option();
 
     /* Byte swapping is left to middle-end expansion. */
     tcg_debug_assert((memop & MO_BSWAP) == 0);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
 
     tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
     tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
-                           TCG_REG_X1, otype, addr_reg);
+                           TCG_REG_X1, option, addr_reg);
     add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
                         s->code_ptr, label_ptr);
 #else /* !CONFIG_SOFTMMU */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
     }
     if (USE_GUEST_BASE) {
         tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
-                               TCG_REG_GUEST_BASE, otype, addr_reg);
+                               TCG_REG_GUEST_BASE, option, addr_reg);
     } else {
+        /* This case is always a 64-bit guest with no extension. */
         tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
-                               addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
+                               addr_reg, LDST_EXT_UXTX, TCG_REG_XZR);
     }
 #endif /* CONFIG_SOFTMMU */
 }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
                             MemOpIdx oi)
 {
     MemOp memop = get_memop(oi);
-    const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+    AArch64LdstExt option = ldst_ext_option();
 
     /* Byte swapping is left to middle-end expansion. */
     tcg_debug_assert((memop & MO_BSWAP) == 0);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
 
     tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
     tcg_out_qemu_st_direct(s, memop, data_reg,
-                           TCG_REG_X1, otype, addr_reg);
+                           TCG_REG_X1, option, addr_reg);
     add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
                         data_reg, addr_reg, s->code_ptr, label_ptr);
 #else /* !CONFIG_SOFTMMU */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
     }
     if (USE_GUEST_BASE) {
         tcg_out_qemu_st_direct(s, memop, data_reg,
-                               TCG_REG_GUEST_BASE, otype, addr_reg);
+                               TCG_REG_GUEST_BASE, option, addr_reg);
     } else {
+        /* This case is always a 64-bit guest with no extension. */
         tcg_out_qemu_st_direct(s, memop, data_reg,
-                               addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
+                               addr_reg, LDST_EXT_UXTX, TCG_REG_XZR);
     }
 #endif /* CONFIG_SOFTMMU */
 }
-- 
2.25.1

All 32-bit mips operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/mips/tcg-target-sa32.h |  8 ++++++++
 tcg/mips/tcg-target.c.inc  | 10 ++--------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target-sa32.h
+++ b/tcg/mips/tcg-target-sa32.h
@@ -1 +1,9 @@
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#ifdef __mips64
+#define TCG_TARGET_SIGNED_ADDR32 1
+#else
 #define TCG_TARGET_SIGNED_ADDR32 0
+#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
                      TCG_TMP0, TCG_TMP3, cmp_off);
     }
 
-    /* Zero extend a 32-bit guest address for a 64-bit host. */
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-        tcg_out_ext32u(s, base, addrl);
-        addrl = base;
-    }
-
     /*
      * Mask the page bits, keeping the alignment bits to compare against.
      * For unaligned accesses, compare against the end of the access to
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, base, addr_regl);
         addr_regl = base;
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, base, addr_regl);
         addr_regl = base;
     }
-- 
2.25.1

All RV64 32-bit operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target-sa32.h | 6 +++++-
 tcg/riscv/tcg-target.c.inc  | 8 ++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target-sa32.h
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -1 +1,5 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#define TCG_TARGET_SIGNED_ADDR32  (__riscv_xlen == 64)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
     tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
 
     /* TLB Hit - translate address using addend.  */
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-        tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
-        addrl = TCG_REG_TMP0;
-    }
     tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
 }
 
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, base, addr_regl);
         addr_regl = base;
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, base, addr_regl);
         addr_regl = base;
     }
-- 
2.25.1

All 32-bit LoongArch operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Cc: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target-sa32.h |  2 +-
 tcg/loongarch64/tcg-target.c.inc  | 15 ++++++---------
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/loongarch64/tcg-target-sa32.h
+++ b/tcg/loongarch64/tcg-target-sa32.h
@@ -1 +1 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+#define TCG_TARGET_SIGNED_ADDR32 1
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
     return tcg_out_fail_alignment(s, l);
 }
 
-#endif /* CONFIG_SOFTMMU */
-
 /*
  * `ext32u` the address register into the temp register given,
  * if target is 32-bit, no-op otherwise.
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s,
                                           TCGReg addr, TCGReg tmp)
 {
-    if (TARGET_LONG_BITS == 32) {
+    if (TARGET_LONG_BITS == 32 && !guest_base_signed_addr32) {
         tcg_out_ext32u(s, tmp, addr);
         return tmp;
     }
     return addr;
 }
+#endif /* CONFIG_SOFTMMU */
 
 static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj,
                                    TCGReg rk, MemOp opc, TCGType type)
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
     tcg_insn_unit *label_ptr[1];
 #else
     unsigned a_bits;
-#endif
     TCGReg base;
+#endif
 
     data_regl = *args++;
     addr_regl = *args++;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
 
 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1);
-    base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
-    tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type);
+    tcg_out_qemu_ld_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc, type);
     add_qemu_ldst_label(s, 1, oi, type,
                         data_regl, addr_regl,
                         s->code_ptr, label_ptr);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
     tcg_insn_unit *label_ptr[1];
 #else
     unsigned a_bits;
-#endif
     TCGReg base;
+#endif
 
     data_regl = *args++;
     addr_regl = *args++;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
 
 #if defined(CONFIG_SOFTMMU)
     tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0);
-    base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
-    tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc);
+    tcg_out_qemu_st_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc);
     add_qemu_ldst_label(s, 0, oi,
                         0, /* type param is unused for stores */
                         data_regl, addr_regl,
-- 
2.25.1