The following changes since commit 3e08b2b9cb64bff2b73fa9128c0e49bfcde0dd40:

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200121' into staging (2020-01-21 15:29:25 +0000)

https://github.com/rth7680/qemu.git tags/pull-tcg-20200121

for you to fetch changes up to 75fa376cdab5e5db2c7fdd107358e16f95503ac6:

scripts/git.orderfile: Display decodetree before C source (2020-01-21 15:26:09 -1000)

Remove another limit to NB_MMU_MODES.

Fix compilation using uclibc.

Fix defaulting of -accel parameters.

Tidy cputlb basic routines.

Adjust git.orderfile for decodetree.

Carlos Santos (1):

util/cacheinfo: fix crash when compiling with uClibc

Philippe Mathieu-Daudé (1):

scripts/git.orderfile: Display decodetree before C source

From: Philippe Mathieu-Daudé <philmd@redhat.com>

scripts/git.orderfile | 3 +++

1 file changed, 3 insertions(+)

diff --git a/scripts/git.orderfile b/scripts/git.orderfile

--- a/scripts/git.orderfile

+++ b/scripts/git.orderfile

@@ -XXX,XX +XXX,XX @@ qga/*.json

# headers

*.h

+# decoding tree specification

+*.decode

+

# code

*.c

2.20.1

There is only one caller for tlb_table_flush_by_mmuidx. Place

the result at the earlier line number, due to an expected user

in the near future.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

accel/tcg/cputlb.c | 19 +++++++------------

1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)

-static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx)

+static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)

{

tlb_mmu_resize_locked(env, mmu_idx);

- memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));

env_tlb(env)->d[mmu_idx].n_used_entries = 0;

+ env_tlb(env)->d[mmu_idx].large_page_addr = -1;

+ env_tlb(env)->d[mmu_idx].large_page_mask = -1;

+ env_tlb(env)->d[mmu_idx].vindex = 0;

+ memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));

+ memset(env_tlb(env)->d[mmu_idx].vtable, -1,

+ sizeof(env_tlb(env)->d[0].vtable));

}

static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)

@@ -XXX,XX +XXX,XX @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide)

*pelide = elide;

}

-static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)

- tlb_table_flush_by_mmuidx(env, mmu_idx);

- env_tlb(env)->d[mmu_idx].large_page_addr = -1;

- env_tlb(env)->d[mmu_idx].large_page_mask = -1;

- env_tlb(env)->d[mmu_idx].vindex = 0;

- memset(env_tlb(env)->d[mmu_idx].vtable, -1,

- sizeof(env_tlb(env)->d[0].vtable));

static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)

CPUArchState *env = cpu->env_ptr;

2.20.1

By choosing "tcg:kvm" when kvm is not enabled, we generate

an incorrect warning: "invalid accelerator kvm".

vl.c | 21 +++++++++++++--------

1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/vl.c b/vl.c

--- a/vl.c

+++ b/vl.c

@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)

if (accel == NULL) {

/* Select the default accelerator */

- if (!accel_find("tcg") && !accel_find("kvm")) {

- error_report("No accelerator selected and"

- " no default accelerator available");

- exit(1);

- } else {

- int pnlen = strlen(progname);

- if (pnlen >= 3 && g_str_equal(&progname[pnlen - 3], "kvm")) {

+ bool have_tcg = accel_find("tcg");

+ bool have_kvm = accel_find("kvm");

+

+ if (have_tcg && have_kvm) {

+ if (g_str_has_suffix(progname, "kvm")) {

/* If the program name ends with "kvm", we prefer KVM */

accel = "kvm:tcg";

} else {

accel = "tcg:kvm";

}

+ } else if (have_kvm) {

+ accel = "kvm";

+ } else if (have_tcg) {

+ accel = "tcg";

+ } else {

+ error_report("No accelerator selected and"

+ " no default accelerator available");

+ exit(1);

}

-

accel_list = g_strsplit(accel, ":", 0);

for (tmp = accel_list; *tmp; tmp++) {

2.20.1

The result of g_strsplit is never NULL.

vl.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vl.c b/vl.c

--- a/vl.c

+++ b/vl.c

@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)

accel_list = g_strsplit(accel, ":", 0);

- for (tmp = accel_list; tmp && *tmp; tmp++) {

+ for (tmp = accel_list; *tmp; tmp++) {

/*

* Filter invalid accelerators here, to prevent obscenities

* such as "-machine accel=tcg,,thread=single".

2.20.1

No functional change, but the smaller expressions make

the code easier to read.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

accel/tcg/cputlb.c | 35 +++++++++++++++++------------------

1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)

/**

* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary

- * @env: CPU that owns the TLB

- * @mmu_idx: MMU index of the TLB

+ * @desc: The CPUTLBDesc portion of the TLB

+ * @fast: The CPUTLBDescFast portion of the same TLB

*

* Called with tlb_lock_held.

*

@@ -XXX,XX +XXX,XX @@ static void tlb_dyn_init(CPUArchState *env)

* high), since otherwise we are likely to have a significant amount of

* conflict misses.

*/

-static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)

+static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)

{

- CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];

- size_t old_size = tlb_n_entries(&env_tlb(env)->f[mmu_idx]);

+ size_t old_size = tlb_n_entries(fast);

size_t rate;

size_t new_size = old_size;

int64_t now = get_clock_realtime();

@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)

* If the allocations fail, try smaller sizes. We just freed some

* memory, so going back to half of new_size has a good chance of working.

@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)

* allocations to fail though, so we progressively reduce the allocation

* size, aborting if we cannot even allocate the smallest TLB we support.

- while (env_tlb(env)->f[mmu_idx].table == NULL ||

- env_tlb(env)->d[mmu_idx].iotlb == NULL) {

+ while (fast->table == NULL || desc->iotlb == NULL) {

if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {

error_report("%s: %s", __func__, strerror(errno));

abort();

}

new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS);

- env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;

+ fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;

- g_free(env_tlb(env)->f[mmu_idx].table);

- g_free(env_tlb(env)->d[mmu_idx].iotlb);

- env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);

- env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);

+ g_free(fast->table);

+ g_free(desc->iotlb);

+ fast->table = g_try_new(CPUTLBEntry, new_size);

+ desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);

2.20.1

In target/arm we will shortly have "too many" mmu_idx.

The current minimum barrier is caused by the way in which

tlb_flush_page_by_mmuidx is coded.

We can remove this limitation by allocating memory for

consumption by the worker. Let us assume that this is

the unlikely case, as will be the case for the majority

of targets which have so far satisfied the BUILD_BUG_ON,

and only allocate memory when necessary.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

accel/tcg/cputlb.c | 167 +++++++++++++++++++++++++++++++++++----------

1 file changed, 132 insertions(+), 35 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,

-/* As we are going to hijack the bottom bits of the page address for a

- * mmuidx bit mask we need to fail to build if we can't do that

+/**

+ * tlb_flush_page_by_mmuidx_async_0:

+ * @cpu: cpu on which to flush

+ * @addr: page of virtual address to flush

+ * @idxmap: set of mmu_idx to flush

+ *

+ * Helper for tlb_flush_page_by_mmuidx and friends, flush one page

+ * at @addr from the tlbs indicated by @idxmap from @cpu.

*/

-QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN);

-

-static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,

- run_on_cpu_data data)

+static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,

+ target_ulong addr,

+ uint16_t idxmap)

CPUArchState *env = cpu->env_ptr;

- target_ulong addr_and_mmuidx = (target_ulong) data.target_ptr;

- target_ulong addr = addr_and_mmuidx & TARGET_PAGE_MASK;

- unsigned long mmu_idx_bitmap = addr_and_mmuidx & ALL_MMUIDX_BITS;

int mmu_idx;

assert_cpu_is_self(cpu);

- tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n",

- addr, mmu_idx_bitmap);

+ tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%x\n", addr, idxmap);

qemu_spin_lock(&env_tlb(env)->c.lock);

for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {

- if (test_bit(mmu_idx, &mmu_idx_bitmap)) {

+ if ((idxmap >> mmu_idx) & 1) {

tlb_flush_page_locked(env, mmu_idx, addr);

}

}

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,

tb_flush_jmp_cache(cpu, addr);

}

+/**

+ * tlb_flush_page_by_mmuidx_async_1:

+ * @cpu: cpu on which to flush

+ * @data: encoded addr + idxmap

+ *

+ * Helper for tlb_flush_page_by_mmuidx and friends, called through

+ * async_run_on_cpu. The idxmap parameter is encoded in the page

+ * offset of the target_ptr field. This limits the set of mmu_idx

+ * that can be passed via this method.

+ */

+static void tlb_flush_page_by_mmuidx_async_1(CPUState *cpu,

+ run_on_cpu_data data)

+{

+ target_ulong addr_and_idxmap = (target_ulong) data.target_ptr;

+ target_ulong addr = addr_and_idxmap & TARGET_PAGE_MASK;

+ uint16_t idxmap = addr_and_idxmap & ~TARGET_PAGE_MASK;

+

+ tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap);

+}

+

+typedef struct {

+ target_ulong addr;

+ uint16_t idxmap;

+} TLBFlushPageByMMUIdxData;

+

+/**

+ * tlb_flush_page_by_mmuidx_async_2:

+ * @cpu: cpu on which to flush

+ * @data: allocated addr + idxmap

+ *

+ * Helper for tlb_flush_page_by_mmuidx and friends, called through

+ * async_run_on_cpu. The addr+idxmap parameters are stored in a

+ * TLBFlushPageByMMUIdxData structure that has been allocated

+ * specifically for this helper. Free the structure when done.

+ */

+static void tlb_flush_page_by_mmuidx_async_2(CPUState *cpu,

+ run_on_cpu_data data)

+{

+ TLBFlushPageByMMUIdxData *d = data.host_ptr;

+

+ tlb_flush_page_by_mmuidx_async_0(cpu, d->addr, d->idxmap);

+ g_free(d);

+}

+

void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap)

{

- target_ulong addr_and_mmu_idx;

-

tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%" PRIx16 "\n", addr, idxmap);

/* This should already be page aligned */

- addr_and_mmu_idx = addr & TARGET_PAGE_MASK;

- addr_and_mmu_idx |= idxmap;

+ addr &= TARGET_PAGE_MASK;

- if (!qemu_cpu_is_self(cpu)) {

- async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work,

- RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));

+ if (qemu_cpu_is_self(cpu)) {

+ tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap);

+ } else if (idxmap < TARGET_PAGE_SIZE) {

+ /*

+ * Most targets have only a few mmu_idx. In the case where

+ * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid

+ * allocating memory for this operation.

+ */

+ async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_1,

+ RUN_ON_CPU_TARGET_PTR(addr | idxmap));

} else {

- tlb_flush_page_by_mmuidx_async_work(

- cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx));

+ TLBFlushPageByMMUIdxData *d = g_new(TLBFlushPageByMMUIdxData, 1);

+

+ /* Otherwise allocate a structure, freed by the worker. */

+ d->addr = addr;

+ d->idxmap = idxmap;

+ async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_2,

+ RUN_ON_CPU_HOST_PTR(d));

2.20.1

The accel_list and tmp variables are only used when manufacturing

-machine accel, options based on -accel.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>

vl.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/vl.c b/vl.c

--- a/vl.c

+++ b/vl.c

@@ -XXX,XX +XXX,XX @@ static int do_configure_accelerator(void *opaque, QemuOpts *opts, Error **errp)

static void configure_accelerators(const char *progname)

{

const char *accel;

- char **accel_list, **tmp;

bool init_failed = false;

qemu_opts_foreach(qemu_find_opts("icount"),

@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)

accel = qemu_opt_get(qemu_get_machine_opts(), "accel");

if (QTAILQ_EMPTY(&qemu_accel_opts.head)) {

+ char **accel_list, **tmp;