The following changes since commit 3e08b2b9cb64bff2b73fa9128c0e49bfcde0dd40:

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200121' into staging (2020-01-21 15:29:25 +0000)

https://github.com/rth7680/qemu.git tags/pull-tcg-20200121

for you to fetch changes up to 75fa376cdab5e5db2c7fdd107358e16f95503ac6:

scripts/git.orderfile: Display decodetree before C source (2020-01-21 15:26:09 -1000)

Remove another limit to NB_MMU_MODES.

Fix compilation using uclibc.

Fix defaulting of -accel parameters.

Tidy cputlb basic routines.

Adjust git.orderfile for decodetree.

Carlos Santos (1):

util/cacheinfo: fix crash when compiling with uClibc

Philippe Mathieu-Daudé (1):

scripts/git.orderfile: Display decodetree before C source

cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN

vl: Remove unused variable in configure_accelerators

vl: Reduce scope of variables in configure_accelerators

vl: Remove useless test in configure_accelerators

vl: Only choose enabled accelerators in configure_accelerators

cputlb: Merge tlb_table_flush_by_mmuidx into tlb_flush_one_mmuidx_locked

cputlb: Make tlb_n_entries private to cputlb.c

cputlb: Pass CPUTLBDescFast to tlb_n_entries and sizeof_tlb

cputlb: Hoist tlb portions in tlb_mmu_resize_locked

cputlb: Hoist tlb portions in tlb_flush_one_mmuidx_locked

cputlb: Split out tlb_mmu_flush_locked

cputlb: Partially merge tlb_dyn_init into tlb_init

cputlb: Initialize tlbs as flushed

cputlb: Hoist timestamp outside of loops over tlbs

include/exec/cpu_ldst.h | 5 -

accel/tcg/cputlb.c | 287 +++++++++++++++++++++++++++++++++---------------

util/cacheinfo.c | 10 +-

vl.c | 27 +++--

scripts/git.orderfile | 3 +

5 files changed, 223 insertions(+), 109 deletions(-)

Do not call get_clock_realtime() in tlb_mmu_resize_locked,

but hoist outside of any loop over a set of tlbs. This is

only two (indirect) callers, tlb_flush_by_mmuidx_async_work

and tlb_flush_page_locked, so not onerous.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

accel/tcg/cputlb.c | 14 ++++++++------

1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,

* high), since otherwise we are likely to have a significant amount of

* conflict misses.

*/

-static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)

+static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,

+ int64_t now)

size_t old_size = tlb_n_entries(fast);

size_t rate;

size_t new_size = old_size;

- int64_t now = get_clock_realtime();

int64_t window_len_ms = 100;

int64_t window_len_ns = window_len_ms * 1000 * 1000;

bool window_expired = now > desc->window_begin_ns + window_len_ns;

@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)

memset(desc->vtable, -1, sizeof(desc->vtable));

}

-static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)

+static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx,

+ int64_t now)

{

CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];

CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];

- tlb_mmu_resize_locked(desc, fast);

+ tlb_mmu_resize_locked(desc, fast, now);

tlb_mmu_flush_locked(desc, fast);

}

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)

CPUArchState *env = cpu->env_ptr;

uint16_t asked = data.host_int;

uint16_t all_dirty, work, to_clean;

+ int64_t now = get_clock_realtime();

assert_cpu_is_self(cpu);

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)

for (work = to_clean; work != 0; work &= work - 1) {

int mmu_idx = ctz32(work);

- tlb_flush_one_mmuidx_locked(env, mmu_idx);

+ tlb_flush_one_mmuidx_locked(env, mmu_idx, now);

qemu_spin_unlock(&env_tlb(env)->c.lock);

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,

tlb_debug("forcing full flush midx %d ("

TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",

midx, lp_addr, lp_mask);

- tlb_flush_one_mmuidx_locked(env, midx);

+ tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime());

} else {

if (tlb_flush_entry_locked(tlb_entry(env, midx, page), page)) {

tlb_n_used_entries_dec(env, midx);

2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

To avoid scrolling each instruction when reviewing tcg

helpers written for the decodetree script, display the

.decode files (similar to header declarations) before

the C source (implementation of previous declarations).

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-Id: <20191230082856.30556-1-philmd@redhat.com>

scripts/git.orderfile | 3 +++

1 file changed, 3 insertions(+)

diff --git a/scripts/git.orderfile b/scripts/git.orderfile

--- a/scripts/git.orderfile

+++ b/scripts/git.orderfile

@@ -XXX,XX +XXX,XX @@ qga/*.json

# headers

*.h

+# decoding tree specification

+*.decode

+

# code

*.c

2.20.1

The result of g_strsplit is never NULL.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed by: Aleksandar Markovic <amarkovic@wavecomp.com>

vl.c | 2 +-

diff --git a/vl.c b/vl.c

--- a/vl.c

+++ b/vl.c

@@ -XXX,XX +XXX,XX @@ static void configure_accelerators(const char *progname)

accel_list = g_strsplit(accel, ":", 0);

- for (tmp = accel_list; tmp && *tmp; tmp++) {

+ for (tmp = accel_list; *tmp; tmp++) {

/*

* Filter invalid accelerators here, to prevent obscenities

* such as "-machine accel=tcg,,thread=single".

2.20.1

There's little point in leaving these data structures half initialized,

and relying on a flush to be done during reset.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

accel/tcg/cputlb.c | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)

fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;

fast->table = g_new(CPUTLBEntry, n_entries);

desc->iotlb = g_new(CPUIOTLBEntry, n_entries);

+ tlb_mmu_flush_locked(desc, fast);

}

static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)

@@ -XXX,XX +XXX,XX @@ void tlb_init(CPUState *cpu)

qemu_spin_init(&env_tlb(env)->c.lock);

- /* Ensure that cpu_reset performs a full flush. */

- env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;

+ /* All tlbs are initialized flushed. */

+ env_tlb(env)->c.dirty = 0;

for (i = 0; i < NB_MMU_MODES; i++) {

tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);

2.20.1

No functional change, but the smaller expressions make

the code easier to read.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

accel/tcg/cputlb.c | 19 ++++++++++---------

1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)

static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)

{

- tlb_mmu_resize_locked(&env_tlb(env)->d[mmu_idx], &env_tlb(env)->f[mmu_idx]);

- env_tlb(env)->d[mmu_idx].n_used_entries = 0;

- env_tlb(env)->d[mmu_idx].large_page_addr = -1;

- env_tlb(env)->d[mmu_idx].large_page_mask = -1;

- env_tlb(env)->d[mmu_idx].vindex = 0;

- memset(env_tlb(env)->f[mmu_idx].table, -1,

- sizeof_tlb(&env_tlb(env)->f[mmu_idx]));

- memset(env_tlb(env)->d[mmu_idx].vtable, -1,

- sizeof(env_tlb(env)->d[0].vtable));

+ CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];

+ CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx];

+

+ tlb_mmu_resize_locked(desc, fast);

+ desc->n_used_entries = 0;

+ desc->large_page_addr = -1;

+ desc->large_page_mask = -1;

+ desc->vindex = 0;

+ memset(fast->table, -1, sizeof_tlb(fast));

+ memset(desc->vtable, -1, sizeof(desc->vtable));

}

static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)

2.20.1

Merge into the only caller, but at the same time split

out tlb_mmu_init to initialize a single tlb entry.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

accel/tcg/cputlb.c | 33 ++++++++++++++++-----------------

1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,

desc->window_max_entries = max_entries;

-static void tlb_dyn_init(CPUArchState *env)

-{

- int i;

-

- for (i = 0; i < NB_MMU_MODES; i++) {

- CPUTLBDesc *desc = &env_tlb(env)->d[i];

- size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;

-

- tlb_window_reset(desc, get_clock_realtime(), 0);

- desc->n_used_entries = 0;

- env_tlb(env)->f[i].mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;

- env_tlb(env)->f[i].table = g_new(CPUTLBEntry, n_entries);

- env_tlb(env)->d[i].iotlb = g_new(CPUIOTLBEntry, n_entries);

- }

-}

-

/**

* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary

* @desc: The CPUTLBDesc portion of the TLB

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)

tlb_mmu_flush_locked(desc, fast);

}

+static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)

+ size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;

+

+ tlb_window_reset(desc, now, 0);

+ desc->n_used_entries = 0;

+ fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;

+ fast->table = g_new(CPUTLBEntry, n_entries);

+ desc->iotlb = g_new(CPUIOTLBEntry, n_entries);

static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)

{

env_tlb(env)->d[mmu_idx].n_used_entries++;

@@ -XXX,XX +XXX,XX @@ static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx)

void tlb_init(CPUState *cpu)

{

CPUArchState *env = cpu->env_ptr;

+ int64_t now = get_clock_realtime();

+ int i;

qemu_spin_init(&env_tlb(env)->c.lock);

/* Ensure that cpu_reset performs a full flush. */

env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;

- tlb_dyn_init(env);

+ for (i = 0; i < NB_MMU_MODES; i++) {

+ tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now);

+ }

}

/* flush_all_helper: run fn across all cpus

2.20.1

In target/arm we will shortly have "too many" mmu_idx.

The current minimum barrier is caused by the way in which

tlb_flush_page_by_mmuidx is coded.

We can remove this limitation by allocating memory for

consumption by the worker. Let us assume that this is

the unlikely case, as will be the case for the majority

of targets which have so far satisfied the BUILD_BUG_ON,

and only allocate memory when necessary.

accel/tcg/cputlb.c | 167 +++++++++++++++++++++++++++++++++++----------

1 file changed, 132 insertions(+), 35 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_locked(CPUArchState *env, int midx,

-/* As we are going to hijack the bottom bits of the page address for a

- * mmuidx bit mask we need to fail to build if we can't do that

+/**

+ * tlb_flush_page_by_mmuidx_async_0:

+ * @cpu: cpu on which to flush

+ * @addr: page of virtual address to flush

+ * @idxmap: set of mmu_idx to flush

+ *

+ * Helper for tlb_flush_page_by_mmuidx and friends, flush one page

+ * at @addr from the tlbs indicated by @idxmap from @cpu.

*/

-QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN);

-

-static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,

- run_on_cpu_data data)

+static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,

+ target_ulong addr,

+ uint16_t idxmap)

{

CPUArchState *env = cpu->env_ptr;

- target_ulong addr_and_mmuidx = (target_ulong) data.target_ptr;

- target_ulong addr = addr_and_mmuidx & TARGET_PAGE_MASK;

- unsigned long mmu_idx_bitmap = addr_and_mmuidx & ALL_MMUIDX_BITS;

int mmu_idx;

assert_cpu_is_self(cpu);

- tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n",

- addr, mmu_idx_bitmap);

+ tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%x\n", addr, idxmap);

qemu_spin_lock(&env_tlb(env)->c.lock);

for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {

- if (test_bit(mmu_idx, &mmu_idx_bitmap)) {

+ if ((idxmap >> mmu_idx) & 1) {

tlb_flush_page_locked(env, mmu_idx, addr);

@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,

tb_flush_jmp_cache(cpu, addr);

}

+/**

+ * tlb_flush_page_by_mmuidx_async_1:

+ * @cpu: cpu on which to flush

+ * @data: encoded addr + idxmap