[v1] riscv: Fix defination of csr operations

[PATCH] riscv: Fix defination of csr operations

jiangzhiying@ict.ac.cn posted 1 patch 4 years, 3 months ago

Diff against v1
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200119105245.5860-1-jiangzhiying@ict.ac.cn

Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>

target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

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[PATCH] riscv: Fix defination of csr operations

Posted by jiangzhiying@ict.ac.cn 4 years, 3 months ago

From: Ian Jiang <ianjiang.ict@gmail.com>

There is a mistake in defining CSR operations for pmpcfg registers.
This patch fixes the bug.

Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..e07b5267be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_SATP] =                { smode, read_satp,        write_satp        },
 
     /* Physical Memory Protection */
-    [CSR_PMPCFG0  ... CSR_PMPADDR9] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
+    [CSR_PMPCFG0  ... CSR_PMPCFG3] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
     [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },
 
     /* Performance Counters */
-- 
2.17.1

Re: [PATCH] riscv: Fix defination of csr operations

Posted by Alistair Francis 4 years, 3 months ago

On Sun, Jan 19, 2020 at 11:55 PM <jiangzhiying@ict.ac.cn> wrote:
>
> From: Ian Jiang <ianjiang.ict@gmail.com>
>
> There is a mistake in defining CSR operations for pmpcfg registers.
> This patch fixes the bug.
>
> Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>

Looks good! Thanks for the patch.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index da02f9f0b1..e07b5267be 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_SATP] =                { smode, read_satp,        write_satp        },
>
>      /* Physical Memory Protection */
> -    [CSR_PMPCFG0  ... CSR_PMPADDR9] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
> +    [CSR_PMPCFG0  ... CSR_PMPCFG3] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
>      [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },
>
>      /* Performance Counters */
> --
> 2.17.1
>
>