1
Latest arm queue, a mixed bag of features and bug fixes.
1
A last small test of bug fixes before rc1.
2
2
3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:
6
The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:
7
7
8
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (2020-01-17 12:13:17 +0000)
8
Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200117-1
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717
13
13
14
for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:
14
for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:
15
15
16
target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +0000)
16
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
Add model of the Netduino Plus 2 board
19
target-arm queue:
20
Some allwinner-a10 code cleanup
20
* hw/arm/sbsa-ref: set 'slots' property of xhci
21
New test cases for cubieboard
21
* linux-user: Remove pointless NULL check in clock_adjtime handling
22
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
22
* ptw: Fix S1_ptw_translate() debug path
23
i.MX: add an emulation for RNGC device
23
* ptw: Account for FEAT_RME when applying {N}SW, SA bits
24
target/arm: adjust program counter for wfi exception in AArch32
24
* accel/tcg: Zero-pad PC in TCG CPU exec trace lines
25
arm/gicv3: update virtual irq state after IAR register read
25
* hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
26
Set IL bit correctly for syndrome information for data aborts
27
26
28
----------------------------------------------------------------
27
----------------------------------------------------------------
29
Alistair Francis (4):
28
Peter Maydell (5):
30
hw/misc: Add the STM32F4xx Sysconfig device
29
linux-user: Remove pointless NULL check in clock_adjtime handling
31
hw/misc: Add the STM32F4xx EXTI device
30
target/arm/ptw.c: Add comments to S1Translate struct fields
32
hw/arm: Add the STM32F4xx SoC
31
target/arm: Fix S1_ptw_translate() debug path
33
hw/arm: Add the Netduino Plus 2
32
target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
33
accel/tcg: Zero-pad PC in TCG CPU exec trace lines
34
34
35
Jeff Kubascik (3):
35
Tong Ho (1):
36
target/arm: adjust program counter for wfi exception in AArch32
36
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
37
arm/gicv3: update virtual irq state after IAR register read
38
target/arm: Return correct IL bit in merge_syn_data_abort
39
37
40
Martin Kaiser (1):
38
Yuquan Wang (1):
41
i.MX: add an emulation for RNGC
39
hw/arm/sbsa-ref: set 'slots' property of xhci
42
40
43
Masahiro Yamada (1):
41
accel/tcg/cpu-exec.c | 4 +--
44
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
42
accel/tcg/translate-all.c | 2 +-
45
43
hw/arm/sbsa-ref.c | 1 +
46
Philippe Mathieu-Daudé (5):
44
hw/nvram/xlnx-efuse.c | 11 ++++--
47
tests/boot_linux_console: Add initrd test for the CubieBoard
45
linux-user/syscall.c | 12 +++----
48
tests/boot_linux_console: Add a SD card test for the CubieBoard
46
target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------
49
hw/arm/allwinner-a10: Move SoC definitions out of header
47
6 files changed, 98 insertions(+), 22 deletions(-)
50
hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
51
hw/arm/allwinner-a10: Remove local qemu_irq variables
52
53
Richard Henderson (1):
54
target/arm: Set ISSIs16Bit in make_issinfo
55
56
hw/arm/Makefile.objs | 2 +
57
hw/misc/Makefile.objs | 3 +
58
include/hw/arm/allwinner-a10.h | 7 -
59
include/hw/arm/fsl-imx25.h | 5 +
60
include/hw/arm/stm32f405_soc.h | 73 ++++++++
61
include/hw/misc/imx_rngc.h | 35 ++++
62
include/hw/misc/stm32f4xx_exti.h | 60 +++++++
63
include/hw/misc/stm32f4xx_syscfg.h | 61 +++++++
64
hw/arm/allwinner-a10.c | 39 +++--
65
hw/arm/fsl-imx25.c | 11 ++
66
hw/arm/netduinoplus2.c | 52 ++++++
67
hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++
68
hw/intc/arm_gicv3_cpuif.c | 3 +
69
hw/misc/imx_rngc.c | 278 ++++++++++++++++++++++++++++++
70
hw/misc/stm32f4xx_exti.c | 188 ++++++++++++++++++++
71
hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++
72
target/arm/arm-semi.c | 5 +-
73
target/arm/op_helper.c | 7 +-
74
target/arm/tlb_helper.c | 2 +-
75
target/arm/translate.c | 3 +
76
MAINTAINERS | 14 ++
77
default-configs/arm-softmmu.mak | 1 +
78
hw/arm/Kconfig | 10 ++
79
hw/misc/Kconfig | 6 +
80
hw/misc/trace-events | 11 ++
81
tests/acceptance/boot_linux_console.py | 85 ++++++++++
82
26 files changed, 1405 insertions(+), 29 deletions(-)
83
create mode 100644 include/hw/arm/stm32f405_soc.h
84
create mode 100644 include/hw/misc/imx_rngc.h
85
create mode 100644 include/hw/misc/stm32f4xx_exti.h
86
create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
87
create mode 100644 hw/arm/netduinoplus2.c
88
create mode 100644 hw/arm/stm32f405_soc.c
89
create mode 100644 hw/misc/imx_rngc.c
90
create mode 100644 hw/misc/stm32f4xx_exti.c
91
create mode 100644 hw/misc/stm32f4xx_syscfg.c
92
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
2
2
3
During the conversion to decodetree, the setting of
3
This extends the slots of xhci to 64, since the default xhci_sysbus
4
ISSIs16Bit got lost. This causes the guest os to
4
just supports one slot.
5
incorrectly adjust trapping memory operations.
6
5
7
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn>
8
Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
7
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
9
Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
11
Message-id: 20200117004618.2742-3-richard.henderson@linaro.org
10
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
target/arm/translate.c | 3 +++
14
hw/arm/sbsa-ref.c | 1 +
16
1 file changed, 3 insertions(+)
15
1 file changed, 1 insertion(+)
17
16
18
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate.c
19
--- a/hw/arm/sbsa-ref.c
21
+++ b/target/arm/translate.c
20
+++ b/hw/arm/sbsa-ref.c
22
@@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
21
@@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms)
23
/* ISS not valid if writeback */
22
hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
24
if (p && !w) {
23
int irq = sbsa_ref_irqmap[SBSA_XHCI];
25
ret = rd;
24
DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
26
+ if (s->base.pc_next - s->pc_curr == 2) {
25
+ qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
27
+ ret |= ISSIs16Bit;
26
28
+ }
27
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29
} else {
28
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
30
ret = ISSInvalid;
31
}
32
--
29
--
33
2.20.1
30
2.34.1
34
35
diff view generated by jsdifflib
1
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
1
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
2
the address of the local variable htx. This means it can never be
3
NULL, but later in the code we check it for NULL anyway. Coverity
4
complains about this (CID 1507683) because the NULL check comes after
5
a call to clock_adjtime() that assumes it is non-NULL.
2
6
3
The IL bit is set for 32-bit instructions, thus passing false
7
Since phtx is always &htx, and is used only in three places, it's not
4
with the is_16bit parameter to syn_data_abort_with_iss() makes
8
really necessary. Remove it, bringing the code structure in to line
5
a syn mask that always has the IL bit set.
9
with that for TARGET_NR_clock_adjtime64, which already uses a simple
10
'&htx' when it wants a pointer to 'htx'.
6
11
7
Pass is_16bit as true to make the initial syn mask have IL=0,
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
so that the final IL value comes from or'ing template_syn.
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org
16
---
17
linux-user/syscall.c | 12 +++++-------
18
1 file changed, 5 insertions(+), 7 deletions(-)
9
19
10
Cc: qemu-stable@nongnu.org
20
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
11
Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts")
12
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200117004618.2742-2-richard.henderson@linaro.org
15
[rth: Extracted this as a self-contained bug fix from a larger patch]
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/tlb_helper.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
24
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/tlb_helper.c
22
--- a/linux-user/syscall.c
26
+++ b/target/arm/tlb_helper.c
23
+++ b/linux-user/syscall.c
27
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
24
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,
28
syn = syn_data_abort_with_iss(same_el,
25
#if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME)
29
0, 0, 0, 0, 0,
26
case TARGET_NR_clock_adjtime:
30
ea, 0, s1ptw, is_write, fsc,
27
{
31
- false);
28
- struct timex htx, *phtx = &htx;
32
+ true);
29
+ struct timex htx;
33
/* Merge the runtime syndrome with the template syndrome. */
30
34
syn |= template_syn;
31
- if (target_to_host_timex(phtx, arg2) != 0) {
35
}
32
+ if (target_to_host_timex(&htx, arg2) != 0) {
33
return -TARGET_EFAULT;
34
}
35
- ret = get_errno(clock_adjtime(arg1, phtx));
36
- if (!is_error(ret) && phtx) {
37
- if (host_to_target_timex(arg2, phtx) != 0) {
38
- return -TARGET_EFAULT;
39
- }
40
+ ret = get_errno(clock_adjtime(arg1, &htx));
41
+ if (!is_error(ret) && host_to_target_timex(arg2, &htx)) {
42
+ return -TARGET_EFAULT;
43
}
44
}
45
return ret;
36
--
46
--
37
2.20.1
47
2.34.1
38
48
39
49
diff view generated by jsdifflib
1
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
1
Add comments to the in_* fields in the S1Translate struct
2
that explain what they're doing.
2
3
3
The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
register activates the highest priority pending interrupt and provides its
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
6
Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org
6
state - this change makes sure the virtual irq state is updated.
7
---
8
target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++
9
1 file changed, 40 insertions(+)
7
10
8
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
11
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/intc/arm_gicv3_cpuif.c | 3 +++
14
1 file changed, 3 insertions(+)
15
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_cpuif.c
13
--- a/target/arm/ptw.c
19
+++ b/hw/intc/arm_gicv3_cpuif.c
14
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
15
@@ -XXX,XX +XXX,XX @@
21
16
#endif
22
trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
17
23
gicv3_redist_affid(cs), intid);
18
typedef struct S1Translate {
24
+
19
+ /*
25
+ gicv3_cpuif_virt_update(cs);
20
+ * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk.
26
+
21
+ * Together with in_space, specifies the architectural translation regime.
27
return intid;
22
+ */
28
}
23
ARMMMUIdx in_mmu_idx;
29
24
+ /*
25
+ * in_ptw_idx: specifies which mmuidx to use for the actual
26
+ * page table descriptor load operations. This will be one of the
27
+ * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes.
28
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
29
+ * this field is updated accordingly.
30
+ */
31
ARMMMUIdx in_ptw_idx;
32
+ /*
33
+ * in_space: the security space for this walk. This plus
34
+ * the in_mmu_idx specify the architectural translation regime.
35
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
36
+ * this field is updated accordingly.
37
+ *
38
+ * Note that the security space for the in_ptw_idx may be different
39
+ * from that for the in_mmu_idx. We do not need to explicitly track
40
+ * the in_ptw_idx security space because:
41
+ * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
42
+ * itself specifies the security space
43
+ * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
44
+ * space used for ptw reads is the same as that of the security
45
+ * space of the stage 1 translation for all cases except where
46
+ * stage 1 is Secure; in that case the only possibilities for
47
+ * the ptw read are Secure and NonSecure, and the in_ptw_idx
48
+ * value being Stage2 vs Stage2_S distinguishes those.
49
+ */
50
ARMSecuritySpace in_space;
51
+ /*
52
+ * in_secure: whether the translation regime is a Secure one.
53
+ * This is always equal to arm_space_is_secure(in_space).
54
+ * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
55
+ * this field is updated accordingly.
56
+ */
57
bool in_secure;
58
+ /*
59
+ * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
60
+ * accesses will not update the guest page table access flags
61
+ * and will not change the state of the softmmu TLBs.
62
+ */
63
bool in_debug;
64
/*
65
* If this is stage 2 of a stage 1+2 page table walk, then this must
30
--
66
--
31
2.20.1
67
2.34.1
32
33
diff view generated by jsdifflib
1
From: Martin Kaiser <martin@kaiser.cx>
1
In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate()
2
so that the debug-access "call get_phys_addr_*" codepath is used both
3
when S1 is doing ptw reads from stage 2 and when it is doing ptw
4
reads from physical memory. However, we didn't update the
5
calculation of s2ptw->in_space and s2ptw->in_secure to account for
6
the "ptw reads from physical memory" case. This meant that debug
7
accesses when in Secure state broke.
2
8
3
Add an emulation for the RNGC random number generator and the compatible
9
Create a new function S2_security_space() which returns the
4
RNGB variant. These peripherals are included (at least) in imx25 and
10
correct security space to use for the ptw load, and use it to
5
imx35 chipsets.
11
determine the correct .in_secure and .in_space fields for the
12
stage 2 lookup for the ptw load.
6
13
7
The emulation supports the initial self test, reseeding the prng and
14
Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
reading random numbers.
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
16
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org
19
Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate")
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
21
---
14
hw/misc/Makefile.objs | 1 +
22
target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++-----
15
include/hw/arm/fsl-imx25.h | 5 +
23
1 file changed, 32 insertions(+), 5 deletions(-)
16
include/hw/misc/imx_rngc.h | 35 +++++
17
hw/arm/fsl-imx25.c | 11 ++
18
hw/misc/imx_rngc.c | 278 +++++++++++++++++++++++++++++++++++++
19
5 files changed, 330 insertions(+)
20
create mode 100644 include/hw/misc/imx_rngc.h
21
create mode 100644 hw/misc/imx_rngc.c
22
24
23
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
25
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
24
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/misc/Makefile.objs
27
--- a/target/arm/ptw.c
26
+++ b/hw/misc/Makefile.objs
28
+++ b/target/arm/ptw.c
27
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o
29
@@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
28
common-obj-$(CONFIG_IMX) += imx2_wdt.o
30
}
29
common-obj-$(CONFIG_IMX) += imx7_snvs.o
31
}
30
common-obj-$(CONFIG_IMX) += imx7_gpr.o
32
31
+common-obj-$(CONFIG_IMX) += imx_rngc.o
33
+static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space,
32
common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
34
+ ARMMMUIdx s2_mmu_idx)
33
common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
34
common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o
35
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/hw/arm/fsl-imx25.h
38
+++ b/include/hw/arm/fsl-imx25.h
39
@@ -XXX,XX +XXX,XX @@
40
#include "hw/timer/imx_gpt.h"
41
#include "hw/timer/imx_epit.h"
42
#include "hw/net/imx_fec.h"
43
+#include "hw/misc/imx_rngc.h"
44
#include "hw/i2c/imx_i2c.h"
45
#include "hw/gpio/imx_gpio.h"
46
#include "exec/memory.h"
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
IMXGPTState gpt[FSL_IMX25_NUM_GPTS];
49
IMXEPITState epit[FSL_IMX25_NUM_EPITS];
50
IMXFECState fec;
51
+ IMXRNGCState rngc;
52
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
53
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
54
MemoryRegion rom[2];
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
56
#define FSL_IMX25_GPIO4_SIZE 0x4000
57
#define FSL_IMX25_GPIO3_ADDR 0x53FA4000
58
#define FSL_IMX25_GPIO3_SIZE 0x4000
59
+#define FSL_IMX25_RNGC_ADDR 0x53FB0000
60
+#define FSL_IMX25_RNGC_SIZE 0x4000
61
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
62
#define FSL_IMX25_GPIO1_SIZE 0x4000
63
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
64
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
65
#define FSL_IMX25_EPIT1_IRQ 28
66
#define FSL_IMX25_EPIT2_IRQ 27
67
#define FSL_IMX25_FEC_IRQ 57
68
+#define FSL_IMX25_RNGC_IRQ 22
69
#define FSL_IMX25_I2C1_IRQ 3
70
#define FSL_IMX25_I2C2_IRQ 4
71
#define FSL_IMX25_I2C3_IRQ 10
72
diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h
73
new file mode 100644
74
index XXXXXXX..XXXXXXX
75
--- /dev/null
76
+++ b/include/hw/misc/imx_rngc.h
77
@@ -XXX,XX +XXX,XX @@
78
+/*
79
+ * Freescale i.MX RNGC emulation
80
+ *
81
+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
82
+ *
83
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
84
+ * See the COPYING file in the top-level directory.
85
+ */
86
+
87
+#ifndef IMX_RNGC_H
88
+#define IMX_RNGC_H
89
+
90
+#include "hw/sysbus.h"
91
+
92
+#define TYPE_IMX_RNGC "imx.rngc"
93
+#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC)
94
+
95
+typedef struct IMXRNGCState {
96
+ /*< private >*/
97
+ SysBusDevice parent_obj;
98
+
99
+ /*< public >*/
100
+ MemoryRegion iomem;
101
+
102
+ uint8_t op_self_test;
103
+ uint8_t op_seed;
104
+ uint8_t mask;
105
+ bool auto_seed;
106
+
107
+ QEMUBH *self_test_bh;
108
+ QEMUBH *seed_bh;
109
+ qemu_irq irq;
110
+} IMXRNGCState;
111
+
112
+#endif /* IMX_RNGC_H */
113
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/hw/arm/fsl-imx25.c
116
+++ b/hw/arm/fsl-imx25.c
117
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
118
119
sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
120
121
+ sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
122
+ TYPE_IMX_RNGC);
123
+
124
for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
125
sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
126
TYPE_IMX_I2C);
127
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
128
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
129
qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
130
131
+ object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
132
+ if (err) {
133
+ error_propagate(errp, err);
134
+ return;
135
+ }
136
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
137
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
138
+ qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
139
140
/* Initialize all I2C */
141
for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
142
diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c
143
new file mode 100644
144
index XXXXXXX..XXXXXXX
145
--- /dev/null
146
+++ b/hw/misc/imx_rngc.c
147
@@ -XXX,XX +XXX,XX @@
148
+/*
149
+ * Freescale i.MX RNGC emulation
150
+ *
151
+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
152
+ *
153
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
154
+ * See the COPYING file in the top-level directory.
155
+ *
156
+ * This driver provides the minimum functionality to initialize and seed
157
+ * an rngc and to read random numbers. The rngb that is found in imx25
158
+ * chipsets is also supported.
159
+ */
160
+
161
+#include "qemu/osdep.h"
162
+#include "qemu/main-loop.h"
163
+#include "qemu/module.h"
164
+#include "qemu/log.h"
165
+#include "qemu/guest-random.h"
166
+#include "hw/irq.h"
167
+#include "hw/misc/imx_rngc.h"
168
+#include "migration/vmstate.h"
169
+
170
+#define RNGC_NAME "i.MX RNGC"
171
+
172
+#define RNGC_VER_ID 0x00
173
+#define RNGC_COMMAND 0x04
174
+#define RNGC_CONTROL 0x08
175
+#define RNGC_STATUS 0x0C
176
+#define RNGC_FIFO 0x14
177
+
178
+/* These version info are reported by the rngb in an imx258 chip. */
179
+#define RNG_TYPE_RNGB 0x1
180
+#define V_MAJ 0x2
181
+#define V_MIN 0x40
182
+
183
+#define RNGC_CMD_BIT_SW_RST 0x40
184
+#define RNGC_CMD_BIT_CLR_ERR 0x20
185
+#define RNGC_CMD_BIT_CLR_INT 0x10
186
+#define RNGC_CMD_BIT_SEED 0x02
187
+#define RNGC_CMD_BIT_SELF_TEST 0x01
188
+
189
+#define RNGC_CTRL_BIT_MASK_ERR 0x40
190
+#define RNGC_CTRL_BIT_MASK_DONE 0x20
191
+#define RNGC_CTRL_BIT_AUTO_SEED 0x10
192
+
193
+/* the current status for self-test and seed operations */
194
+#define OP_IDLE 0
195
+#define OP_RUN 1
196
+#define OP_DONE 2
197
+
198
+static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size)
199
+{
35
+{
200
+ IMXRNGCState *s = IMX_RNGC(opaque);
36
+ /*
201
+ uint64_t val = 0;
37
+ * Return the security space to use for stage 2 when doing
202
+
38
+ * the S1 page table descriptor load.
203
+ switch (offset) {
39
+ */
204
+ case RNGC_VER_ID:
40
+ if (regime_is_stage2(s2_mmu_idx)) {
205
+ val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN;
41
+ /*
206
+ break;
42
+ * The security space for ptw reads is almost always the same
207
+
43
+ * as that of the security space of the stage 1 translation.
208
+ case RNGC_COMMAND:
44
+ * The only exception is when stage 1 is Secure; in that case
209
+ if (s->op_seed == OP_RUN) {
45
+ * the ptw read might be to the Secure or the NonSecure space
210
+ val |= RNGC_CMD_BIT_SEED;
46
+ * (but never Realm or Root), and the s2_mmu_idx tells us which.
47
+ * Root translations are always single-stage.
48
+ */
49
+ if (s1_space == ARMSS_Secure) {
50
+ return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S);
51
+ } else {
52
+ assert(s2_mmu_idx != ARMMMUIdx_Stage2_S);
53
+ assert(s1_space != ARMSS_Root);
54
+ return s1_space;
211
+ }
55
+ }
212
+ if (s->op_self_test == OP_RUN) {
56
+ } else {
213
+ val |= RNGC_CMD_BIT_SELF_TEST;
57
+ /* ptw loads are from phys: the mmu idx itself says which space */
214
+ }
58
+ return arm_phys_to_space(s2_mmu_idx);
215
+ break;
216
+
217
+ case RNGC_CONTROL:
218
+ /*
219
+ * The CTL_ACC and VERIF_MODE bits are not supported yet.
220
+ * They read as 0.
221
+ */
222
+ val |= s->mask;
223
+ if (s->auto_seed) {
224
+ val |= RNGC_CTRL_BIT_AUTO_SEED;
225
+ }
226
+ /*
227
+ * We don't have an internal fifo like the real hardware.
228
+ * There's no need for strategy to handle fifo underflows.
229
+ * We return the FIFO_UFLOW_RESPONSE bits as 0.
230
+ */
231
+ break;
232
+
233
+ case RNGC_STATUS:
234
+ /*
235
+ * We never report any statistics test or self-test errors or any
236
+ * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0.
237
+ */
238
+
239
+ /*
240
+ * We don't have an internal fifo, see above. Therefore, we
241
+ * report back the default fifo size (5 32-bit words) and
242
+ * indicate that our fifo is always full.
243
+ */
244
+ val |= 5 << 12 | 5 << 8;
245
+
246
+ /* We always have a new seed available. */
247
+ val |= 1 << 6;
248
+
249
+ if (s->op_seed == OP_DONE) {
250
+ val |= 1 << 5;
251
+ }
252
+ if (s->op_self_test == OP_DONE) {
253
+ val |= 1 << 4;
254
+ }
255
+ if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) {
256
+ /*
257
+ * We're busy if self-test is running or if we're
258
+ * seeding the prng.
259
+ */
260
+ val |= 1 << 1;
261
+ } else {
262
+ /*
263
+ * We're ready to provide secure random numbers whenever
264
+ * we're not busy.
265
+ */
266
+ val |= 1;
267
+ }
268
+ break;
269
+
270
+ case RNGC_FIFO:
271
+ qemu_guest_getrandom_nofail(&val, sizeof(val));
272
+ break;
273
+ }
274
+
275
+ return val;
276
+}
277
+
278
+static void imx_rngc_do_reset(IMXRNGCState *s)
279
+{
280
+ s->op_self_test = OP_IDLE;
281
+ s->op_seed = OP_IDLE;
282
+ s->mask = 0;
283
+ s->auto_seed = false;
284
+}
285
+
286
+static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value,
287
+ unsigned size)
288
+{
289
+ IMXRNGCState *s = IMX_RNGC(opaque);
290
+
291
+ switch (offset) {
292
+ case RNGC_COMMAND:
293
+ if (value & RNGC_CMD_BIT_SW_RST) {
294
+ imx_rngc_do_reset(s);
295
+ }
296
+
297
+ /*
298
+ * For now, both CLR_ERR and CLR_INT clear the interrupt. We
299
+ * don't report any errors yet.
300
+ */
301
+ if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) {
302
+ qemu_irq_lower(s->irq);
303
+ }
304
+
305
+ if (value & RNGC_CMD_BIT_SEED) {
306
+ s->op_seed = OP_RUN;
307
+ qemu_bh_schedule(s->seed_bh);
308
+ }
309
+
310
+ if (value & RNGC_CMD_BIT_SELF_TEST) {
311
+ s->op_self_test = OP_RUN;
312
+ qemu_bh_schedule(s->self_test_bh);
313
+ }
314
+ break;
315
+
316
+ case RNGC_CONTROL:
317
+ /*
318
+ * The CTL_ACC and VERIF_MODE bits are not supported yet.
319
+ * We ignore them if they're set by the caller.
320
+ */
321
+
322
+ if (value & RNGC_CTRL_BIT_MASK_ERR) {
323
+ s->mask |= RNGC_CTRL_BIT_MASK_ERR;
324
+ } else {
325
+ s->mask &= ~RNGC_CTRL_BIT_MASK_ERR;
326
+ }
327
+
328
+ if (value & RNGC_CTRL_BIT_MASK_DONE) {
329
+ s->mask |= RNGC_CTRL_BIT_MASK_DONE;
330
+ } else {
331
+ s->mask &= ~RNGC_CTRL_BIT_MASK_DONE;
332
+ }
333
+
334
+ if (value & RNGC_CTRL_BIT_AUTO_SEED) {
335
+ s->auto_seed = true;
336
+ } else {
337
+ s->auto_seed = false;
338
+ }
339
+ break;
340
+ }
59
+ }
341
+}
60
+}
342
+
61
+
343
+static const MemoryRegionOps imx_rngc_ops = {
62
/* Translate a S1 pagetable walk through S2 if needed. */
344
+ .read = imx_rngc_read,
63
static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
345
+ .write = imx_rngc_write,
64
hwaddr addr, ARMMMUFaultInfo *fi)
346
+ .endianness = DEVICE_NATIVE_ENDIAN,
65
{
347
+};
66
- ARMSecuritySpace space = ptw->in_space;
348
+
67
bool is_secure = ptw->in_secure;
349
+static void imx_rngc_self_test(void *opaque)
68
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
350
+{
69
ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
351
+ IMXRNGCState *s = IMX_RNGC(opaque);
70
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
352
+
71
* From gdbstub, do not use softmmu so that we don't modify the
353
+ s->op_self_test = OP_DONE;
72
* state of the cpu at all, including softmmu tlb contents.
354
+ if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
73
*/
355
+ qemu_irq_raise(s->irq);
74
+ ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx);
356
+ }
75
S1Translate s2ptw = {
357
+}
76
.in_mmu_idx = s2_mmu_idx,
358
+
77
.in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
359
+static void imx_rngc_seed(void *opaque)
78
- .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
360
+{
79
- .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
361
+ IMXRNGCState *s = IMX_RNGC(opaque);
80
- : space == ARMSS_Realm ? ARMSS_Realm
362
+
81
- : ARMSS_NonSecure),
363
+ s->op_seed = OP_DONE;
82
+ .in_secure = arm_space_is_secure(s2_space),
364
+ if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
83
+ .in_space = s2_space,
365
+ qemu_irq_raise(s->irq);
84
.in_debug = true,
366
+ }
85
};
367
+}
86
GetPhysAddrResult s2 = { };
368
+
369
+static void imx_rngc_realize(DeviceState *dev, Error **errp)
370
+{
371
+ IMXRNGCState *s = IMX_RNGC(dev);
372
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
373
+
374
+ memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s,
375
+ TYPE_IMX_RNGC, 0x1000);
376
+ sysbus_init_mmio(sbd, &s->iomem);
377
+
378
+ sysbus_init_irq(sbd, &s->irq);
379
+ s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s);
380
+ s->seed_bh = qemu_bh_new(imx_rngc_seed, s);
381
+}
382
+
383
+static void imx_rngc_reset(DeviceState *dev)
384
+{
385
+ IMXRNGCState *s = IMX_RNGC(dev);
386
+
387
+ imx_rngc_do_reset(s);
388
+}
389
+
390
+static const VMStateDescription vmstate_imx_rngc = {
391
+ .name = RNGC_NAME,
392
+ .version_id = 1,
393
+ .minimum_version_id = 1,
394
+ .fields = (VMStateField[]) {
395
+ VMSTATE_UINT8(op_self_test, IMXRNGCState),
396
+ VMSTATE_UINT8(op_seed, IMXRNGCState),
397
+ VMSTATE_UINT8(mask, IMXRNGCState),
398
+ VMSTATE_BOOL(auto_seed, IMXRNGCState),
399
+ VMSTATE_END_OF_LIST()
400
+ }
401
+};
402
+
403
+static void imx_rngc_class_init(ObjectClass *klass, void *data)
404
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
407
+ dc->realize = imx_rngc_realize;
408
+ dc->reset = imx_rngc_reset;
409
+ dc->desc = RNGC_NAME,
410
+ dc->vmsd = &vmstate_imx_rngc;
411
+}
412
+
413
+static const TypeInfo imx_rngc_info = {
414
+ .name = TYPE_IMX_RNGC,
415
+ .parent = TYPE_SYS_BUS_DEVICE,
416
+ .instance_size = sizeof(IMXRNGCState),
417
+ .class_init = imx_rngc_class_init,
418
+};
419
+
420
+static void imx_rngc_register_types(void)
421
+{
422
+ type_register_static(&imx_rngc_info);
423
+}
424
+
425
+type_init(imx_rngc_register_types)
426
--
87
--
427
2.20.1
88
2.34.1
428
429
diff view generated by jsdifflib
1
From: Alistair Francis <alistair@alistair23.me>
1
In get_phys_addr_twostage() the code that applies the effects of
2
VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
3
Now we also have f.attrs.space for FEAT_RME, we need to keep the two
4
in sync.
2
5
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
6
These bits only have an effect for Secure space translations, not
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
for Root, so use the input in_space field to determine whether to
5
Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me
8
apply them rather than the input is_secure. This doesn't actually
9
make a difference because Root translations are never two-stage,
10
but it's a little clearer.
11
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org
7
---
15
---
8
hw/misc/Makefile.objs | 1 +
16
target/arm/ptw.c | 13 ++++++++-----
9
include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++++++
17
1 file changed, 8 insertions(+), 5 deletions(-)
10
hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++++++++++++
11
default-configs/arm-softmmu.mak | 1 +
12
hw/arm/Kconfig | 9 ++
13
hw/misc/Kconfig | 3 +
14
hw/misc/trace-events | 6 +
15
7 files changed, 252 insertions(+)
16
create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
17
create mode 100644 hw/misc/stm32f4xx_syscfg.c
18
18
19
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
19
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/Makefile.objs
21
--- a/target/arm/ptw.c
22
+++ b/hw/misc/Makefile.objs
22
+++ b/target/arm/ptw.c
23
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
23
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
24
common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
24
hwaddr ipa;
25
common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
25
int s1_prot, s1_lgpgsz;
26
common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
26
bool is_secure = ptw->in_secure;
27
+common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
27
+ ARMSecuritySpace in_space = ptw->in_space;
28
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
28
bool ret, ipa_secure;
29
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
29
ARMCacheAttrs cacheattrs1;
30
obj-$(CONFIG_MIPS_ITU) += mips_itu.o
30
ARMSecuritySpace ipa_space;
31
diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
32
new file mode 100644
32
* Check if IPA translates to secure or non-secure PA space.
33
index XXXXXXX..XXXXXXX
33
* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
34
--- /dev/null
34
*/
35
+++ b/include/hw/misc/stm32f4xx_syscfg.h
35
- result->f.attrs.secure =
36
@@ -XXX,XX +XXX,XX @@
36
- (is_secure
37
+/*
37
- && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
38
+ * STM32F4xx SYSCFG
38
- && (ipa_secure
39
+ *
39
- || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
40
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
40
+ if (in_space == ARMSS_Secure) {
41
+ *
41
+ result->f.attrs.secure =
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
42
+ !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
43
+ * of this software and associated documentation files (the "Software"), to deal
43
+ && (ipa_secure
44
+ * in the Software without restriction, including without limitation the rights
44
+ || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)));
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
45
+ result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#ifndef HW_STM_SYSCFG_H
62
+#define HW_STM_SYSCFG_H
63
+
64
+#include "hw/sysbus.h"
65
+#include "hw/hw.h"
66
+
67
+#define SYSCFG_MEMRMP 0x00
68
+#define SYSCFG_PMC 0x04
69
+#define SYSCFG_EXTICR1 0x08
70
+#define SYSCFG_EXTICR2 0x0C
71
+#define SYSCFG_EXTICR3 0x10
72
+#define SYSCFG_EXTICR4 0x14
73
+#define SYSCFG_CMPCR 0x20
74
+
75
+#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
76
+#define STM32F4XX_SYSCFG(obj) \
77
+ OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG)
78
+
79
+#define SYSCFG_NUM_EXTICR 4
80
+
81
+typedef struct {
82
+ /* <private> */
83
+ SysBusDevice parent_obj;
84
+
85
+ /* <public> */
86
+ MemoryRegion mmio;
87
+
88
+ uint32_t syscfg_memrmp;
89
+ uint32_t syscfg_pmc;
90
+ uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];
91
+ uint32_t syscfg_cmpcr;
92
+
93
+ qemu_irq irq;
94
+ qemu_irq gpio_out[16];
95
+} STM32F4xxSyscfgState;
96
+
97
+#endif
98
diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c
99
new file mode 100644
100
index XXXXXXX..XXXXXXX
101
--- /dev/null
102
+++ b/hw/misc/stm32f4xx_syscfg.c
103
@@ -XXX,XX +XXX,XX @@
104
+/*
105
+ * STM32F4xx SYSCFG
106
+ *
107
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
108
+ *
109
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
110
+ * of this software and associated documentation files (the "Software"), to deal
111
+ * in the Software without restriction, including without limitation the rights
112
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
113
+ * copies of the Software, and to permit persons to whom the Software is
114
+ * furnished to do so, subject to the following conditions:
115
+ *
116
+ * The above copyright notice and this permission notice shall be included in
117
+ * all copies or substantial portions of the Software.
118
+ *
119
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
120
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
121
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
122
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
123
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
124
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
125
+ * THE SOFTWARE.
126
+ */
127
+
128
+#include "qemu/osdep.h"
129
+#include "qemu/log.h"
130
+#include "trace.h"
131
+#include "hw/irq.h"
132
+#include "migration/vmstate.h"
133
+#include "hw/misc/stm32f4xx_syscfg.h"
134
+
135
+static void stm32f4xx_syscfg_reset(DeviceState *dev)
136
+{
137
+ STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);
138
+
139
+ s->syscfg_memrmp = 0x00000000;
140
+ s->syscfg_pmc = 0x00000000;
141
+ s->syscfg_exticr[0] = 0x00000000;
142
+ s->syscfg_exticr[1] = 0x00000000;
143
+ s->syscfg_exticr[2] = 0x00000000;
144
+ s->syscfg_exticr[3] = 0x00000000;
145
+ s->syscfg_cmpcr = 0x00000000;
146
+}
147
+
148
+static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)
149
+{
150
+ STM32F4xxSyscfgState *s = opaque;
151
+ int icrreg = irq / 4;
152
+ int startbit = (irq & 3) * 4;
153
+ uint8_t config = config = irq / 16;
154
+
155
+ trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);
156
+
157
+ g_assert(icrreg < SYSCFG_NUM_EXTICR);
158
+
159
+ if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
160
+ qemu_set_irq(s->gpio_out[irq], level);
161
+ trace_stm32f4xx_pulse_exti(irq);
162
+ }
163
+}
164
+
165
+static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,
166
+ unsigned int size)
167
+{
168
+ STM32F4xxSyscfgState *s = opaque;
169
+
170
+ trace_stm32f4xx_syscfg_read(addr);
171
+
172
+ switch (addr) {
173
+ case SYSCFG_MEMRMP:
174
+ return s->syscfg_memrmp;
175
+ case SYSCFG_PMC:
176
+ return s->syscfg_pmc;
177
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
178
+ return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];
179
+ case SYSCFG_CMPCR:
180
+ return s->syscfg_cmpcr;
181
+ default:
182
+ qemu_log_mask(LOG_GUEST_ERROR,
183
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
184
+ return 0;
185
+ }
46
+ }
186
+}
47
187
+
48
return false;
188
+static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,
49
}
189
+ uint64_t val64, unsigned int size)
190
+{
191
+ STM32F4xxSyscfgState *s = opaque;
192
+ uint32_t value = val64;
193
+
194
+ trace_stm32f4xx_syscfg_write(value, addr);
195
+
196
+ switch (addr) {
197
+ case SYSCFG_MEMRMP:
198
+ qemu_log_mask(LOG_UNIMP,
199
+ "%s: Changing the memory mapping isn't supported " \
200
+ "in QEMU\n", __func__);
201
+ return;
202
+ case SYSCFG_PMC:
203
+ qemu_log_mask(LOG_UNIMP,
204
+ "%s: Changing the memory mapping isn't supported " \
205
+ "in QEMU\n", __func__);
206
+ return;
207
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
208
+ s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);
209
+ return;
210
+ case SYSCFG_CMPCR:
211
+ s->syscfg_cmpcr = value;
212
+ return;
213
+ default:
214
+ qemu_log_mask(LOG_GUEST_ERROR,
215
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
216
+ }
217
+}
218
+
219
+static const MemoryRegionOps stm32f4xx_syscfg_ops = {
220
+ .read = stm32f4xx_syscfg_read,
221
+ .write = stm32f4xx_syscfg_write,
222
+ .endianness = DEVICE_NATIVE_ENDIAN,
223
+};
224
+
225
+static void stm32f4xx_syscfg_init(Object *obj)
226
+{
227
+ STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);
228
+
229
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
230
+
231
+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,
232
+ TYPE_STM32F4XX_SYSCFG, 0x400);
233
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
234
+
235
+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);
236
+ qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
237
+}
238
+
239
+static const VMStateDescription vmstate_stm32f4xx_syscfg = {
240
+ .name = TYPE_STM32F4XX_SYSCFG,
241
+ .version_id = 1,
242
+ .minimum_version_id = 1,
243
+ .fields = (VMStateField[]) {
244
+ VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),
245
+ VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),
246
+ VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,
247
+ SYSCFG_NUM_EXTICR),
248
+ VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),
249
+ VMSTATE_END_OF_LIST()
250
+ }
251
+};
252
+
253
+static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)
254
+{
255
+ DeviceClass *dc = DEVICE_CLASS(klass);
256
+
257
+ dc->reset = stm32f4xx_syscfg_reset;
258
+ dc->vmsd = &vmstate_stm32f4xx_syscfg;
259
+}
260
+
261
+static const TypeInfo stm32f4xx_syscfg_info = {
262
+ .name = TYPE_STM32F4XX_SYSCFG,
263
+ .parent = TYPE_SYS_BUS_DEVICE,
264
+ .instance_size = sizeof(STM32F4xxSyscfgState),
265
+ .instance_init = stm32f4xx_syscfg_init,
266
+ .class_init = stm32f4xx_syscfg_class_init,
267
+};
268
+
269
+static void stm32f4xx_syscfg_register_types(void)
270
+{
271
+ type_register_static(&stm32f4xx_syscfg_info);
272
+}
273
+
274
+type_init(stm32f4xx_syscfg_register_types)
275
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
276
index XXXXXXX..XXXXXXX 100644
277
--- a/default-configs/arm-softmmu.mak
278
+++ b/default-configs/arm-softmmu.mak
279
@@ -XXX,XX +XXX,XX @@ CONFIG_Z2=y
280
CONFIG_COLLIE=y
281
CONFIG_ASPEED_SOC=y
282
CONFIG_NETDUINO2=y
283
+CONFIG_NETDUINOPLUS2=y
284
CONFIG_MPS2=y
285
CONFIG_RASPI=y
286
CONFIG_DIGIC=y
287
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/arm/Kconfig
290
+++ b/hw/arm/Kconfig
291
@@ -XXX,XX +XXX,XX @@ config NETDUINO2
292
bool
293
select STM32F205_SOC
294
295
+config NETDUINOPLUS2
296
+ bool
297
+ select STM32F405_SOC
298
+
299
config NSERIES
300
bool
301
select OMAP
302
@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC
303
select STM32F2XX_ADC
304
select STM32F2XX_SPI
305
306
+config STM32F405_SOC
307
+ bool
308
+ select ARM_V7M
309
+ select STM32F4XX_SYSCFG
310
+
311
config XLNX_ZYNQMP_ARM
312
bool
313
select AHCI
314
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
315
index XXXXXXX..XXXXXXX 100644
316
--- a/hw/misc/Kconfig
317
+++ b/hw/misc/Kconfig
318
@@ -XXX,XX +XXX,XX @@ config IMX
319
config STM32F2XX_SYSCFG
320
bool
321
322
+config STM32F4XX_SYSCFG
323
+ bool
324
+
325
config MIPS_ITU
326
bool
327
328
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
329
index XXXXXXX..XXXXXXX 100644
330
--- a/hw/misc/trace-events
331
+++ b/hw/misc/trace-events
332
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
333
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
334
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
335
336
+# stm32f4xx_syscfg
337
+stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
338
+stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
339
+stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
340
+stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
341
+
342
# tz-mpc.c
343
tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
344
tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
345
--
50
--
346
2.20.1
51
2.34.1
347
348
diff view generated by jsdifflib
Deleted patch
1
From: Alistair Francis <alistair@alistair23.me>
2
1
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: ef941d59fd8658589d34ed432e1d6dfdcf7fb1d0.1576658572.git.alistair@alistair23.me
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/misc/Makefile.objs | 1 +
10
include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++
11
hw/misc/stm32f4xx_exti.c | 188 +++++++++++++++++++++++++++++++
12
hw/arm/Kconfig | 1 +
13
hw/misc/Kconfig | 3 +
14
hw/misc/trace-events | 5 +
15
6 files changed, 258 insertions(+)
16
create mode 100644 include/hw/misc/stm32f4xx_exti.h
17
create mode 100644 hw/misc/stm32f4xx_exti.c
18
19
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/Makefile.objs
22
+++ b/hw/misc/Makefile.objs
23
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
24
common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
25
common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
26
common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
27
+common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o
28
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
29
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
30
obj-$(CONFIG_MIPS_ITU) += mips_itu.o
31
diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h
32
new file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- /dev/null
35
+++ b/include/hw/misc/stm32f4xx_exti.h
36
@@ -XXX,XX +XXX,XX @@
37
+/*
38
+ * STM32F4XX EXTI
39
+ *
40
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
41
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
43
+ * of this software and associated documentation files (the "Software"), to deal
44
+ * in the Software without restriction, including without limitation the rights
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#ifndef HW_STM_EXTI_H
62
+#define HW_STM_EXTI_H
63
+
64
+#include "hw/sysbus.h"
65
+#include "hw/hw.h"
66
+
67
+#define EXTI_IMR 0x00
68
+#define EXTI_EMR 0x04
69
+#define EXTI_RTSR 0x08
70
+#define EXTI_FTSR 0x0C
71
+#define EXTI_SWIER 0x10
72
+#define EXTI_PR 0x14
73
+
74
+#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"
75
+#define STM32F4XX_EXTI(obj) \
76
+ OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI)
77
+
78
+#define NUM_GPIO_EVENT_IN_LINES 16
79
+#define NUM_INTERRUPT_OUT_LINES 16
80
+
81
+typedef struct {
82
+ SysBusDevice parent_obj;
83
+
84
+ MemoryRegion mmio;
85
+
86
+ uint32_t exti_imr;
87
+ uint32_t exti_emr;
88
+ uint32_t exti_rtsr;
89
+ uint32_t exti_ftsr;
90
+ uint32_t exti_swier;
91
+ uint32_t exti_pr;
92
+
93
+ qemu_irq irq[NUM_INTERRUPT_OUT_LINES];
94
+} STM32F4xxExtiState;
95
+
96
+#endif
97
diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c
98
new file mode 100644
99
index XXXXXXX..XXXXXXX
100
--- /dev/null
101
+++ b/hw/misc/stm32f4xx_exti.c
102
@@ -XXX,XX +XXX,XX @@
103
+/*
104
+ * STM32F4XX EXTI
105
+ *
106
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
107
+ *
108
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
109
+ * of this software and associated documentation files (the "Software"), to deal
110
+ * in the Software without restriction, including without limitation the rights
111
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
112
+ * copies of the Software, and to permit persons to whom the Software is
113
+ * furnished to do so, subject to the following conditions:
114
+ *
115
+ * The above copyright notice and this permission notice shall be included in
116
+ * all copies or substantial portions of the Software.
117
+ *
118
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
119
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
120
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
121
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
122
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
123
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
124
+ * THE SOFTWARE.
125
+ */
126
+
127
+#include "qemu/osdep.h"
128
+#include "qemu/log.h"
129
+#include "trace.h"
130
+#include "hw/irq.h"
131
+#include "migration/vmstate.h"
132
+#include "hw/misc/stm32f4xx_exti.h"
133
+
134
+static void stm32f4xx_exti_reset(DeviceState *dev)
135
+{
136
+ STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);
137
+
138
+ s->exti_imr = 0x00000000;
139
+ s->exti_emr = 0x00000000;
140
+ s->exti_rtsr = 0x00000000;
141
+ s->exti_ftsr = 0x00000000;
142
+ s->exti_swier = 0x00000000;
143
+ s->exti_pr = 0x00000000;
144
+}
145
+
146
+static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)
147
+{
148
+ STM32F4xxExtiState *s = opaque;
149
+
150
+ trace_stm32f4xx_exti_set_irq(irq, level);
151
+
152
+ if (((1 << irq) & s->exti_rtsr) && level) {
153
+ /* Rising Edge */
154
+ s->exti_pr |= 1 << irq;
155
+ }
156
+
157
+ if (((1 << irq) & s->exti_ftsr) && !level) {
158
+ /* Falling Edge */
159
+ s->exti_pr |= 1 << irq;
160
+ }
161
+
162
+ if (!((1 << irq) & s->exti_imr)) {
163
+ /* Interrupt is masked */
164
+ return;
165
+ }
166
+ qemu_irq_pulse(s->irq[irq]);
167
+}
168
+
169
+static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,
170
+ unsigned int size)
171
+{
172
+ STM32F4xxExtiState *s = opaque;
173
+
174
+ trace_stm32f4xx_exti_read(addr);
175
+
176
+ switch (addr) {
177
+ case EXTI_IMR:
178
+ return s->exti_imr;
179
+ case EXTI_EMR:
180
+ return s->exti_emr;
181
+ case EXTI_RTSR:
182
+ return s->exti_rtsr;
183
+ case EXTI_FTSR:
184
+ return s->exti_ftsr;
185
+ case EXTI_SWIER:
186
+ return s->exti_swier;
187
+ case EXTI_PR:
188
+ return s->exti_pr;
189
+ default:
190
+ qemu_log_mask(LOG_GUEST_ERROR,
191
+ "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);
192
+ return 0;
193
+ }
194
+ return 0;
195
+}
196
+
197
+static void stm32f4xx_exti_write(void *opaque, hwaddr addr,
198
+ uint64_t val64, unsigned int size)
199
+{
200
+ STM32F4xxExtiState *s = opaque;
201
+ uint32_t value = (uint32_t) val64;
202
+
203
+ trace_stm32f4xx_exti_write(addr, value);
204
+
205
+ switch (addr) {
206
+ case EXTI_IMR:
207
+ s->exti_imr = value;
208
+ return;
209
+ case EXTI_EMR:
210
+ s->exti_emr = value;
211
+ return;
212
+ case EXTI_RTSR:
213
+ s->exti_rtsr = value;
214
+ return;
215
+ case EXTI_FTSR:
216
+ s->exti_ftsr = value;
217
+ return;
218
+ case EXTI_SWIER:
219
+ s->exti_swier = value;
220
+ return;
221
+ case EXTI_PR:
222
+ /* This bit is cleared by writing a 1 to it */
223
+ s->exti_pr &= ~value;
224
+ return;
225
+ default:
226
+ qemu_log_mask(LOG_GUEST_ERROR,
227
+ "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);
228
+ }
229
+}
230
+
231
+static const MemoryRegionOps stm32f4xx_exti_ops = {
232
+ .read = stm32f4xx_exti_read,
233
+ .write = stm32f4xx_exti_write,
234
+ .endianness = DEVICE_NATIVE_ENDIAN,
235
+};
236
+
237
+static void stm32f4xx_exti_init(Object *obj)
238
+{
239
+ STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);
240
+ int i;
241
+
242
+ for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {
243
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
244
+ }
245
+
246
+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,
247
+ TYPE_STM32F4XX_EXTI, 0x400);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
249
+
250
+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,
251
+ NUM_GPIO_EVENT_IN_LINES);
252
+}
253
+
254
+static const VMStateDescription vmstate_stm32f4xx_exti = {
255
+ .name = TYPE_STM32F4XX_EXTI,
256
+ .version_id = 1,
257
+ .minimum_version_id = 1,
258
+ .fields = (VMStateField[]) {
259
+ VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),
260
+ VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),
261
+ VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),
262
+ VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),
263
+ VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),
264
+ VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),
265
+ VMSTATE_END_OF_LIST()
266
+ }
267
+};
268
+
269
+static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)
270
+{
271
+ DeviceClass *dc = DEVICE_CLASS(klass);
272
+
273
+ dc->reset = stm32f4xx_exti_reset;
274
+ dc->vmsd = &vmstate_stm32f4xx_exti;
275
+}
276
+
277
+static const TypeInfo stm32f4xx_exti_info = {
278
+ .name = TYPE_STM32F4XX_EXTI,
279
+ .parent = TYPE_SYS_BUS_DEVICE,
280
+ .instance_size = sizeof(STM32F4xxExtiState),
281
+ .instance_init = stm32f4xx_exti_init,
282
+ .class_init = stm32f4xx_exti_class_init,
283
+};
284
+
285
+static void stm32f4xx_exti_register_types(void)
286
+{
287
+ type_register_static(&stm32f4xx_exti_info);
288
+}
289
+
290
+type_init(stm32f4xx_exti_register_types)
291
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
292
index XXXXXXX..XXXXXXX 100644
293
--- a/hw/arm/Kconfig
294
+++ b/hw/arm/Kconfig
295
@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
296
bool
297
select ARM_V7M
298
select STM32F4XX_SYSCFG
299
+ select STM32F4XX_EXTI
300
301
config XLNX_ZYNQMP_ARM
302
bool
303
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
304
index XXXXXXX..XXXXXXX 100644
305
--- a/hw/misc/Kconfig
306
+++ b/hw/misc/Kconfig
307
@@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG
308
config STM32F4XX_SYSCFG
309
bool
310
311
+config STM32F4XX_EXTI
312
+ bool
313
+
314
config MIPS_ITU
315
bool
316
317
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
318
index XXXXXXX..XXXXXXX 100644
319
--- a/hw/misc/trace-events
320
+++ b/hw/misc/trace-events
321
@@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
322
stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
323
stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
324
325
+# stm32f4xx_exti
326
+stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
327
+stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
328
+stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
329
+
330
# tz-mpc.c
331
tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
332
tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
333
--
334
2.20.1
335
336
diff view generated by jsdifflib
Deleted patch
1
From: Alistair Francis <alistair@alistair23.me>
2
1
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/Makefile.objs | 1 +
9
include/hw/arm/stm32f405_soc.h | 73 ++++++++
10
hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++
11
MAINTAINERS | 8 +
12
4 files changed, 384 insertions(+)
13
create mode 100644 include/hw/arm/stm32f405_soc.h
14
create mode 100644 hw/arm/stm32f405_soc.c
15
16
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Makefile.objs
19
+++ b/hw/arm/Makefile.objs
20
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STRONGARM) += strongarm.o
21
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
22
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
23
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
24
+obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
25
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
26
obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
27
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
28
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
29
new file mode 100644
30
index XXXXXXX..XXXXXXX
31
--- /dev/null
32
+++ b/include/hw/arm/stm32f405_soc.h
33
@@ -XXX,XX +XXX,XX @@
34
+/*
35
+ * STM32F405 SoC
36
+ *
37
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
38
+ *
39
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
40
+ * of this software and associated documentation files (the "Software"), to deal
41
+ * in the Software without restriction, including without limitation the rights
42
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
43
+ * copies of the Software, and to permit persons to whom the Software is
44
+ * furnished to do so, subject to the following conditions:
45
+ *
46
+ * The above copyright notice and this permission notice shall be included in
47
+ * all copies or substantial portions of the Software.
48
+ *
49
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
50
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
51
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
52
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
53
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
54
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
55
+ * THE SOFTWARE.
56
+ */
57
+
58
+#ifndef HW_ARM_STM32F405_SOC_H
59
+#define HW_ARM_STM32F405_SOC_H
60
+
61
+#include "hw/misc/stm32f4xx_syscfg.h"
62
+#include "hw/timer/stm32f2xx_timer.h"
63
+#include "hw/char/stm32f2xx_usart.h"
64
+#include "hw/adc/stm32f2xx_adc.h"
65
+#include "hw/misc/stm32f4xx_exti.h"
66
+#include "hw/or-irq.h"
67
+#include "hw/ssi/stm32f2xx_spi.h"
68
+#include "hw/arm/armv7m.h"
69
+
70
+#define TYPE_STM32F405_SOC "stm32f405-soc"
71
+#define STM32F405_SOC(obj) \
72
+ OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
73
+
74
+#define STM_NUM_USARTS 7
75
+#define STM_NUM_TIMERS 4
76
+#define STM_NUM_ADCS 6
77
+#define STM_NUM_SPIS 6
78
+
79
+#define FLASH_BASE_ADDRESS 0x08000000
80
+#define FLASH_SIZE (1024 * 1024)
81
+#define SRAM_BASE_ADDRESS 0x20000000
82
+#define SRAM_SIZE (192 * 1024)
83
+
84
+typedef struct STM32F405State {
85
+ /*< private >*/
86
+ SysBusDevice parent_obj;
87
+ /*< public >*/
88
+
89
+ char *cpu_type;
90
+
91
+ ARMv7MState armv7m;
92
+
93
+ STM32F4xxSyscfgState syscfg;
94
+ STM32F4xxExtiState exti;
95
+ STM32F2XXUsartState usart[STM_NUM_USARTS];
96
+ STM32F2XXTimerState timer[STM_NUM_TIMERS];
97
+ qemu_or_irq adc_irqs;
98
+ STM32F2XXADCState adc[STM_NUM_ADCS];
99
+ STM32F2XXSPIState spi[STM_NUM_SPIS];
100
+
101
+ MemoryRegion sram;
102
+ MemoryRegion flash;
103
+ MemoryRegion flash_alias;
104
+} STM32F405State;
105
+
106
+#endif
107
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
108
new file mode 100644
109
index XXXXXXX..XXXXXXX
110
--- /dev/null
111
+++ b/hw/arm/stm32f405_soc.c
112
@@ -XXX,XX +XXX,XX @@
113
+/*
114
+ * STM32F405 SoC
115
+ *
116
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
117
+ *
118
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
119
+ * of this software and associated documentation files (the "Software"), to deal
120
+ * in the Software without restriction, including without limitation the rights
121
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
122
+ * copies of the Software, and to permit persons to whom the Software is
123
+ * furnished to do so, subject to the following conditions:
124
+ *
125
+ * The above copyright notice and this permission notice shall be included in
126
+ * all copies or substantial portions of the Software.
127
+ *
128
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
129
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
130
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
131
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
132
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
133
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
134
+ * THE SOFTWARE.
135
+ */
136
+
137
+#include "qemu/osdep.h"
138
+#include "qapi/error.h"
139
+#include "qemu-common.h"
140
+#include "exec/address-spaces.h"
141
+#include "sysemu/sysemu.h"
142
+#include "hw/arm/stm32f405_soc.h"
143
+#include "hw/misc/unimp.h"
144
+
145
+#define SYSCFG_ADD 0x40013800
146
+static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
147
+ 0x40004C00, 0x40005000, 0x40011400,
148
+ 0x40007800, 0x40007C00 };
149
+/* At the moment only Timer 2 to 5 are modelled */
150
+static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
151
+ 0x40000800, 0x40000C00 };
152
+#define ADC_ADDR 0x40012000
153
+static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
154
+ 0x40013400, 0x40015000, 0x40015400 };
155
+#define EXTI_ADDR 0x40013C00
156
+
157
+#define SYSCFG_IRQ 71
158
+static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
159
+static const int timer_irq[] = { 28, 29, 30, 50 };
160
+#define ADC_IRQ 18
161
+static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };
162
+static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
163
+ 40, 40, 40, 40, 40} ;
164
+
165
+
166
+static void stm32f405_soc_initfn(Object *obj)
167
+{
168
+ STM32F405State *s = STM32F405_SOC(obj);
169
+ int i;
170
+
171
+ sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
172
+ TYPE_ARMV7M);
173
+
174
+ sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
175
+ TYPE_STM32F4XX_SYSCFG);
176
+
177
+ for (i = 0; i < STM_NUM_USARTS; i++) {
178
+ sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
179
+ sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
180
+ }
181
+
182
+ for (i = 0; i < STM_NUM_TIMERS; i++) {
183
+ sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
184
+ sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
185
+ }
186
+
187
+ for (i = 0; i < STM_NUM_ADCS; i++) {
188
+ sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
189
+ TYPE_STM32F2XX_ADC);
190
+ }
191
+
192
+ for (i = 0; i < STM_NUM_SPIS; i++) {
193
+ sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
194
+ TYPE_STM32F2XX_SPI);
195
+ }
196
+
197
+ sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
198
+ TYPE_STM32F4XX_EXTI);
199
+}
200
+
201
+static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
202
+{
203
+ STM32F405State *s = STM32F405_SOC(dev_soc);
204
+ MemoryRegion *system_memory = get_system_memory();
205
+ DeviceState *dev, *armv7m;
206
+ SysBusDevice *busdev;
207
+ Error *err = NULL;
208
+ int i;
209
+
210
+ memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE,
211
+ &err);
212
+ if (err != NULL) {
213
+ error_propagate(errp, err);
214
+ return;
215
+ }
216
+ memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias",
217
+ &s->flash, 0, FLASH_SIZE);
218
+
219
+ memory_region_set_readonly(&s->flash, true);
220
+ memory_region_set_readonly(&s->flash_alias, true);
221
+
222
+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
223
+ memory_region_add_subregion(system_memory, 0, &s->flash_alias);
224
+
225
+ memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
226
+ &err);
227
+ if (err != NULL) {
228
+ error_propagate(errp, err);
229
+ return;
230
+ }
231
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
232
+
233
+ armv7m = DEVICE(&s->armv7m);
234
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
235
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
236
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
237
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
238
+ "memory", &error_abort);
239
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
240
+ if (err != NULL) {
241
+ error_propagate(errp, err);
242
+ return;
243
+ }
244
+
245
+ /* System configuration controller */
246
+ dev = DEVICE(&s->syscfg);
247
+ object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
248
+ if (err != NULL) {
249
+ error_propagate(errp, err);
250
+ return;
251
+ }
252
+ busdev = SYS_BUS_DEVICE(dev);
253
+ sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
254
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
255
+
256
+ /* Attach UART (uses USART registers) and USART controllers */
257
+ for (i = 0; i < STM_NUM_USARTS; i++) {
258
+ dev = DEVICE(&(s->usart[i]));
259
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
260
+ object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
261
+ if (err != NULL) {
262
+ error_propagate(errp, err);
263
+ return;
264
+ }
265
+ busdev = SYS_BUS_DEVICE(dev);
266
+ sysbus_mmio_map(busdev, 0, usart_addr[i]);
267
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
268
+ }
269
+
270
+ /* Timer 2 to 5 */
271
+ for (i = 0; i < STM_NUM_TIMERS; i++) {
272
+ dev = DEVICE(&(s->timer[i]));
273
+ qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
274
+ object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
275
+ if (err != NULL) {
276
+ error_propagate(errp, err);
277
+ return;
278
+ }
279
+ busdev = SYS_BUS_DEVICE(dev);
280
+ sysbus_mmio_map(busdev, 0, timer_addr[i]);
281
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
282
+ }
283
+
284
+ /* ADC device, the IRQs are ORed together */
285
+ object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
286
+ sizeof(s->adc_irqs), TYPE_OR_IRQ,
287
+ &err, NULL);
288
+ if (err != NULL) {
289
+ error_propagate(errp, err);
290
+ return;
291
+ }
292
+ object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
293
+ "num-lines", &err);
294
+ object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
295
+ if (err != NULL) {
296
+ error_propagate(errp, err);
297
+ return;
298
+ }
299
+ qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
300
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
301
+
302
+ dev = DEVICE(&(s->adc[i]));
303
+ object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
304
+ if (err != NULL) {
305
+ error_propagate(errp, err);
306
+ return;
307
+ }
308
+ busdev = SYS_BUS_DEVICE(dev);
309
+ sysbus_mmio_map(busdev, 0, ADC_ADDR);
310
+ sysbus_connect_irq(busdev, 0,
311
+ qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
312
+
313
+ /* SPI devices */
314
+ for (i = 0; i < STM_NUM_SPIS; i++) {
315
+ dev = DEVICE(&(s->spi[i]));
316
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
317
+ if (err != NULL) {
318
+ error_propagate(errp, err);
319
+ return;
320
+ }
321
+ busdev = SYS_BUS_DEVICE(dev);
322
+ sysbus_mmio_map(busdev, 0, spi_addr[i]);
323
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
324
+ }
325
+
326
+ /* EXTI device */
327
+ dev = DEVICE(&s->exti);
328
+ object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
329
+ if (err != NULL) {
330
+ error_propagate(errp, err);
331
+ return;
332
+ }
333
+ busdev = SYS_BUS_DEVICE(dev);
334
+ sysbus_mmio_map(busdev, 0, EXTI_ADDR);
335
+ for (i = 0; i < 16; i++) {
336
+ sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
337
+ }
338
+ for (i = 0; i < 16; i++) {
339
+ qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
340
+ }
341
+
342
+ create_unimplemented_device("timer[7]", 0x40001400, 0x400);
343
+ create_unimplemented_device("timer[12]", 0x40001800, 0x400);
344
+ create_unimplemented_device("timer[6]", 0x40001000, 0x400);
345
+ create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
346
+ create_unimplemented_device("timer[14]", 0x40002000, 0x400);
347
+ create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
348
+ create_unimplemented_device("WWDG", 0x40002C00, 0x400);
349
+ create_unimplemented_device("IWDG", 0x40003000, 0x400);
350
+ create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
351
+ create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
352
+ create_unimplemented_device("I2C1", 0x40005400, 0x400);
353
+ create_unimplemented_device("I2C2", 0x40005800, 0x400);
354
+ create_unimplemented_device("I2C3", 0x40005C00, 0x400);
355
+ create_unimplemented_device("CAN1", 0x40006400, 0x400);
356
+ create_unimplemented_device("CAN2", 0x40006800, 0x400);
357
+ create_unimplemented_device("PWR", 0x40007000, 0x400);
358
+ create_unimplemented_device("DAC", 0x40007400, 0x400);
359
+ create_unimplemented_device("timer[1]", 0x40010000, 0x400);
360
+ create_unimplemented_device("timer[8]", 0x40010400, 0x400);
361
+ create_unimplemented_device("SDIO", 0x40012C00, 0x400);
362
+ create_unimplemented_device("timer[9]", 0x40014000, 0x400);
363
+ create_unimplemented_device("timer[10]", 0x40014400, 0x400);
364
+ create_unimplemented_device("timer[11]", 0x40014800, 0x400);
365
+ create_unimplemented_device("GPIOA", 0x40020000, 0x400);
366
+ create_unimplemented_device("GPIOB", 0x40020400, 0x400);
367
+ create_unimplemented_device("GPIOC", 0x40020800, 0x400);
368
+ create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
369
+ create_unimplemented_device("GPIOE", 0x40021000, 0x400);
370
+ create_unimplemented_device("GPIOF", 0x40021400, 0x400);
371
+ create_unimplemented_device("GPIOG", 0x40021800, 0x400);
372
+ create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
373
+ create_unimplemented_device("GPIOI", 0x40022000, 0x400);
374
+ create_unimplemented_device("CRC", 0x40023000, 0x400);
375
+ create_unimplemented_device("RCC", 0x40023800, 0x400);
376
+ create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
377
+ create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
378
+ create_unimplemented_device("DMA1", 0x40026000, 0x400);
379
+ create_unimplemented_device("DMA2", 0x40026400, 0x400);
380
+ create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
381
+ create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
382
+ create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
383
+ create_unimplemented_device("DCMI", 0x50050000, 0x400);
384
+ create_unimplemented_device("RNG", 0x50060800, 0x400);
385
+}
386
+
387
+static Property stm32f405_soc_properties[] = {
388
+ DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
389
+ DEFINE_PROP_END_OF_LIST(),
390
+};
391
+
392
+static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
393
+{
394
+ DeviceClass *dc = DEVICE_CLASS(klass);
395
+
396
+ dc->realize = stm32f405_soc_realize;
397
+ dc->props = stm32f405_soc_properties;
398
+ /* No vmstate or reset required: device has no internal state */
399
+}
400
+
401
+static const TypeInfo stm32f405_soc_info = {
402
+ .name = TYPE_STM32F405_SOC,
403
+ .parent = TYPE_SYS_BUS_DEVICE,
404
+ .instance_size = sizeof(STM32F405State),
405
+ .instance_init = stm32f405_soc_initfn,
406
+ .class_init = stm32f405_soc_class_init,
407
+};
408
+
409
+static void stm32f405_soc_types(void)
410
+{
411
+ type_register_static(&stm32f405_soc_info);
412
+}
413
+
414
+type_init(stm32f405_soc_types)
415
diff --git a/MAINTAINERS b/MAINTAINERS
416
index XXXXXXX..XXXXXXX 100644
417
--- a/MAINTAINERS
418
+++ b/MAINTAINERS
419
@@ -XXX,XX +XXX,XX @@ F: hw/adc/*
420
F: hw/ssi/stm32f2xx_spi.c
421
F: include/hw/*/stm32*.h
422
423
+STM32F405
424
+M: Alistair Francis <alistair@alistair23.me>
425
+M: Peter Maydell <peter.maydell@linaro.org>
426
+S: Maintained
427
+F: hw/arm/stm32f405_soc.c
428
+F: hw/misc/stm32f4xx_syscfg.c
429
+F: hw/misc/stm32f4xx_exti.c
430
+
431
Netduino 2
432
M: Alistair Francis <alistair@alistair23.me>
433
M: Peter Maydell <peter.maydell@linaro.org>
434
--
435
2.20.1
436
437
diff view generated by jsdifflib
Deleted patch
1
From: Alistair Francis <alistair@alistair23.me>
2
1
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: dad8d8d47f7625913e35e27a1c00f603a6b08f9a.1576658572.git.alistair@alistair23.me
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/Makefile.objs | 1 +
9
hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++
10
MAINTAINERS | 6 +++++
11
3 files changed, 59 insertions(+)
12
create mode 100644 hw/arm/netduinoplus2.c
13
14
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Makefile.objs
17
+++ b/hw/arm/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o
19
obj-$(CONFIG_MICROBIT) += microbit.o
20
obj-$(CONFIG_MUSICPAL) += musicpal.o
21
obj-$(CONFIG_NETDUINO2) += netduino2.o
22
+obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o
23
obj-$(CONFIG_NSERIES) += nseries.o
24
obj-$(CONFIG_SX1) += omap_sx1.o
25
obj-$(CONFIG_CHEETAH) += palm.o
26
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
27
new file mode 100644
28
index XXXXXXX..XXXXXXX
29
--- /dev/null
30
+++ b/hw/arm/netduinoplus2.c
31
@@ -XXX,XX +XXX,XX @@
32
+/*
33
+ * Netduino Plus 2 Machine Model
34
+ *
35
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
36
+ *
37
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
38
+ * of this software and associated documentation files (the "Software"), to deal
39
+ * in the Software without restriction, including without limitation the rights
40
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
41
+ * copies of the Software, and to permit persons to whom the Software is
42
+ * furnished to do so, subject to the following conditions:
43
+ *
44
+ * The above copyright notice and this permission notice shall be included in
45
+ * all copies or substantial portions of the Software.
46
+ *
47
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
51
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
52
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
53
+ * THE SOFTWARE.
54
+ */
55
+
56
+#include "qemu/osdep.h"
57
+#include "qapi/error.h"
58
+#include "hw/boards.h"
59
+#include "hw/qdev-properties.h"
60
+#include "qemu/error-report.h"
61
+#include "hw/arm/stm32f405_soc.h"
62
+#include "hw/arm/boot.h"
63
+
64
+static void netduinoplus2_init(MachineState *machine)
65
+{
66
+ DeviceState *dev;
67
+
68
+ dev = qdev_create(NULL, TYPE_STM32F405_SOC);
69
+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
70
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
71
+
72
+ armv7m_load_kernel(ARM_CPU(first_cpu),
73
+ machine->kernel_filename,
74
+ FLASH_SIZE);
75
+}
76
+
77
+static void netduinoplus2_machine_init(MachineClass *mc)
78
+{
79
+ mc->desc = "Netduino Plus 2 Machine";
80
+ mc->init = netduinoplus2_init;
81
+}
82
+
83
+DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
84
diff --git a/MAINTAINERS b/MAINTAINERS
85
index XXXXXXX..XXXXXXX 100644
86
--- a/MAINTAINERS
87
+++ b/MAINTAINERS
88
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
89
S: Maintained
90
F: hw/arm/netduino2.c
91
92
+Netduino Plus 2
93
+M: Alistair Francis <alistair@alistair23.me>
94
+M: Peter Maydell <peter.maydell@linaro.org>
95
+S: Maintained
96
+F: hw/arm/netduinoplus2.c
97
+
98
SmartFusion2
99
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
100
M: Peter Maydell <peter.maydell@linaro.org>
101
--
102
2.20.1
103
104
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
This test boots a Linux kernel on a CubieBoard and verify
4
the serial output is working.
5
6
The kernel image and DeviceTree blob are built by the Armbian
7
project (based on Debian):
8
https://docs.armbian.com/Developer-Guide_Build-Preparation/
9
10
The cpio image used comes from the linux-build-test project:
11
https://github.com/groeck/linux-build-test
12
13
If ARM is a target being built, "make check-acceptance" will
14
automatically include this test by the use of the "arch:arm" tags.
15
16
Alternatively, this test can be run using:
17
18
$ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
19
console: Uncompressing Linux... done, booting the kernel.
20
console: Booting Linux on physical CPU 0x0
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=50c5387d
23
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
24
console: OF: fdt: Machine model: Cubietech Cubieboard
25
[...]
26
console: Boot successful.
27
console: cat /proc/cpuinfo
28
console: / # cat /proc/cpuinfo
29
console: processor : 0
30
console: model name : ARMv7 Processor rev 0 (v7l)
31
console: BogoMIPS : 832.51
32
[...]
33
console: Hardware : Allwinner sun4i/sun5i Families
34
console: Revision : 0000
35
console: Serial : 0000000000000000
36
console: cat /proc/iomem
37
console: / # cat /proc/iomem
38
console: 01c00000-01c0002f : system-control@1c00000
39
console: 01c02000-01c02fff : dma-controller@1c02000
40
console: 01c05000-01c05fff : spi@1c05000
41
console: 01c0b080-01c0b093 : mdio@1c0b080
42
console: 01c0c000-01c0cfff : lcd-controller@1c0c000
43
console: 01c0d000-01c0dfff : lcd-controller@1c0d000
44
console: 01c0f000-01c0ffff : mmc@1c0f000
45
[...]
46
PASS (54.35 s)
47
48
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
49
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
50
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
51
Message-id: 20191230110953.25496-2-f4bug@amsat.org
52
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
53
---
54
tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++
55
1 file changed, 41 insertions(+)
56
57
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
58
index XXXXXXX..XXXXXXX 100644
59
--- a/tests/acceptance/boot_linux_console.py
60
+++ b/tests/acceptance/boot_linux_console.py
61
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
62
self.wait_for_console_pattern('Boot successful.')
63
# TODO user command, for now the uart is stuck
64
65
+ def test_arm_cubieboard_initrd(self):
66
+ """
67
+ :avocado: tags=arch:arm
68
+ :avocado: tags=machine:cubieboard
69
+ """
70
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
71
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
72
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
73
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
74
+ kernel_path = self.extract_from_deb(deb_path,
75
+ '/boot/vmlinuz-4.20.7-sunxi')
76
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
77
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
78
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
79
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
80
+ 'arm/rootfs-armv5.cpio.gz')
81
+ initrd_hash = '2b50f1873e113523967806f4da2afe385462ff9b'
82
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
83
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
84
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
85
+
86
+ self.vm.set_console()
87
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
88
+ 'console=ttyS0,115200 '
89
+ 'usbcore.nousb '
90
+ 'panic=-1 noreboot')
91
+ self.vm.add_args('-kernel', kernel_path,
92
+ '-dtb', dtb_path,
93
+ '-initrd', initrd_path,
94
+ '-append', kernel_command_line,
95
+ '-no-reboot')
96
+ self.vm.launch()
97
+ self.wait_for_console_pattern('Boot successful.')
98
+
99
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
100
+ 'Allwinner sun4i/sun5i')
101
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
102
+ 'system-control@1c00000')
103
+ exec_command_and_wait_for_pattern(self, 'reboot',
104
+ 'reboot: Restarting system')
105
+
106
def test_s390x_s390_ccw_virtio(self):
107
"""
108
:avocado: tags=arch:s390x
109
--
110
2.20.1
111
112
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The kernel image and DeviceTree blob are built by the Armbian
4
project (based on Debian):
5
https://docs.armbian.com/Developer-Guide_Build-Preparation/
6
7
The cpio image used comes from the linux-build-test project:
8
https://github.com/groeck/linux-build-test
9
10
If ARM is a target being built, "make check-acceptance" will
11
automatically include this test by the use of the "arch:arm" tags.
12
13
Alternatively, this test can be run using:
14
15
$ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
16
console: Uncompressing Linux... done, booting the kernel.
17
console: Booting Linux on physical CPU 0x0
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
19
[...]
20
console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4
21
console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit
22
console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps 0x1 impl platform mode
23
console: ahci-sunxi 1c18000.sata: flags: ncq only
24
console: scsi host0: ahci-sunxi
25
console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 27
26
console: of_cfs_init
27
console: of_cfs_init: OK
28
console: vcc3v0: disabling
29
console: vcc5v0: disabling
30
console: usb1-vbus: disabling
31
console: usb2-vbus: disabling
32
console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
33
console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100
34
console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32)
35
console: ata1.00: applying bridge limits
36
console: ata1.00: configured for UDMA/100
37
console: scsi 0:0:0:0: Direct-Access ATA QEMU HARDDISK 2.5+ PQ: 0 ANSI: 5
38
console: sd 0:0:0:0: Attached scsi generic sg0 type 0
39
console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB)
40
console: sd 0:0:0:0: [sda] Write Protect is off
41
console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
42
console: sd 0:0:0:0: [sda] Attached SCSI disk
43
console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem
44
console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null)
45
console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0.
46
[...]
47
console: cat /proc/partitions
48
console: / # cat /proc/partitions
49
console: major minor #blocks name
50
console: 1 0 4096 ram0
51
console: 1 1 4096 ram1
52
console: 1 2 4096 ram2
53
console: 1 3 4096 ram3
54
console: 8 0 20480 sda
55
console: reboot
56
console: / # reboot
57
[...]
58
console: sd 0:0:0:0: [sda] Synchronizing SCSI cache
59
console: reboot: Restarting system
60
PASS (48.39 s)
61
62
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
63
Message-id: 20191230110953.25496-3-f4bug@amsat.org
64
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
65
---
66
tests/acceptance/boot_linux_console.py | 44 ++++++++++++++++++++++++++
67
1 file changed, 44 insertions(+)
68
69
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tests/acceptance/boot_linux_console.py
72
+++ b/tests/acceptance/boot_linux_console.py
73
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
74
exec_command_and_wait_for_pattern(self, 'reboot',
75
'reboot: Restarting system')
76
77
+ def test_arm_cubieboard_sata(self):
78
+ """
79
+ :avocado: tags=arch:arm
80
+ :avocado: tags=machine:cubieboard
81
+ """
82
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
83
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
84
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
85
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
86
+ kernel_path = self.extract_from_deb(deb_path,
87
+ '/boot/vmlinuz-4.20.7-sunxi')
88
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
89
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
90
+ rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
91
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
92
+ 'arm/rootfs-armv5.ext2.gz')
93
+ rootfs_hash = '093e89d2b4d982234bf528bc9fb2f2f17a9d1f93'
94
+ rootfs_path_gz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
95
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
96
+ archive.gzip_uncompress(rootfs_path_gz, rootfs_path)
97
+
98
+ self.vm.set_console()
99
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
100
+ 'console=ttyS0,115200 '
101
+ 'usbcore.nousb '
102
+ 'root=/dev/sda ro '
103
+ 'panic=-1 noreboot')
104
+ self.vm.add_args('-kernel', kernel_path,
105
+ '-dtb', dtb_path,
106
+ '-drive', 'if=none,format=raw,id=disk0,file='
107
+ + rootfs_path,
108
+ '-device', 'ide-hd,bus=ide.0,drive=disk0',
109
+ '-append', kernel_command_line,
110
+ '-no-reboot')
111
+ self.vm.launch()
112
+ self.wait_for_console_pattern('Boot successful.')
113
+
114
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
115
+ 'Allwinner sun4i/sun5i')
116
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
117
+ 'sda')
118
+ exec_command_and_wait_for_pattern(self, 'reboot',
119
+ 'reboot: Restarting system')
120
+
121
def test_s390x_s390_ccw_virtio(self):
122
"""
123
:avocado: tags=arch:s390x
124
--
125
2.20.1
126
127
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
These definitions are specific to the A10 SoC and don't need
4
to be exported to the different Allwinner peripherals.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20191230110953.25496-4-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-a10.h | 6 ------
12
hw/arm/allwinner-a10.c | 6 ++++++
13
2 files changed, 6 insertions(+), 6 deletions(-)
14
15
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-a10.h
18
+++ b/include/hw/arm/allwinner-a10.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "target/arm/cpu.h"
21
22
23
-#define AW_A10_PIC_REG_BASE 0x01c20400
24
-#define AW_A10_PIT_REG_BASE 0x01c20c00
25
-#define AW_A10_UART0_REG_BASE 0x01c28000
26
-#define AW_A10_EMAC_BASE 0x01c0b000
27
-#define AW_A10_SATA_BASE 0x01c18000
28
-
29
#define AW_A10_SDRAM_BASE 0x40000000
30
31
#define TYPE_AW_A10 "allwinner-a10"
32
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/allwinner-a10.c
35
+++ b/hw/arm/allwinner-a10.c
36
@@ -XXX,XX +XXX,XX @@
37
#include "hw/misc/unimp.h"
38
#include "sysemu/sysemu.h"
39
40
+#define AW_A10_PIC_REG_BASE 0x01c20400
41
+#define AW_A10_PIT_REG_BASE 0x01c20c00
42
+#define AW_A10_UART0_REG_BASE 0x01c28000
43
+#define AW_A10_EMAC_BASE 0x01c0b000
44
+#define AW_A10_SATA_BASE 0x01c18000
45
+
46
static void aw_a10_init(Object *obj)
47
{
48
AwA10State *s = AW_A10(obj);
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
By calling qdev_pass_gpios() we don't need to hold a copy of the
4
IRQs from the INTC into the SoC state.
5
Instead of filling an array of qemu_irq and passing it around, we
6
can now directly call qdev_get_gpio_in() on the SoC.
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20191230110953.25496-5-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/allwinner-a10.h | 1 -
14
hw/arm/allwinner-a10.c | 24 +++++++++++-------------
15
2 files changed, 11 insertions(+), 14 deletions(-)
16
17
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/allwinner-a10.h
20
+++ b/include/hw/arm/allwinner-a10.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
22
/*< public >*/
23
24
ARMCPU cpu;
25
- qemu_irq irq[AW_A10_PIC_INT_NR];
26
AwA10PITState timer;
27
AwA10PICState intc;
28
AwEmacState emac;
29
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/allwinner-a10.c
32
+++ b/hw/arm/allwinner-a10.c
33
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
34
{
35
AwA10State *s = AW_A10(dev);
36
SysBusDevice *sysbusdev;
37
- uint8_t i;
38
qemu_irq fiq, irq;
39
Error *err = NULL;
40
41
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
42
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
43
sysbus_connect_irq(sysbusdev, 0, irq);
44
sysbus_connect_irq(sysbusdev, 1, fiq);
45
- for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
46
- s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
47
- }
48
+ qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
49
50
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
51
if (err != NULL) {
52
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
53
}
54
sysbusdev = SYS_BUS_DEVICE(&s->timer);
55
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
56
- sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
57
- sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
58
- sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
59
- sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
60
- sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
61
- sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
62
+ sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
63
+ sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
64
+ sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
65
+ sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
66
+ sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
67
+ sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
68
69
memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
70
&error_fatal);
71
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
72
}
73
sysbusdev = SYS_BUS_DEVICE(&s->emac);
74
sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
75
- sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
76
+ sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
77
78
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
79
if (err) {
80
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
81
return;
82
}
83
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
84
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
85
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
86
87
/* FIXME use a qdev chardev prop instead of serial_hd() */
88
- serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
89
+ serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
90
+ qdev_get_gpio_in(dev, 1),
91
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
92
}
93
94
--
95
2.20.1
96
97
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
We won't reuse the CPU IRQ/FIQ variables. Simplify by calling
4
qdev_get_gpio_in() in place.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20191230110953.25496-6-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/allwinner-a10.c | 9 ++++-----
12
1 file changed, 4 insertions(+), 5 deletions(-)
13
14
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/allwinner-a10.c
17
+++ b/hw/arm/allwinner-a10.c
18
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
19
{
20
AwA10State *s = AW_A10(dev);
21
SysBusDevice *sysbusdev;
22
- qemu_irq fiq, irq;
23
Error *err = NULL;
24
25
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
26
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
27
error_propagate(errp, err);
28
return;
29
}
30
- irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
31
- fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
32
33
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
34
if (err != NULL) {
35
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
36
}
37
sysbusdev = SYS_BUS_DEVICE(&s->intc);
38
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
39
- sysbus_connect_irq(sysbusdev, 0, irq);
40
- sysbus_connect_irq(sysbusdev, 1, fiq);
41
+ sysbus_connect_irq(sysbusdev, 0,
42
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
43
+ sysbus_connect_irq(sysbusdev, 1,
44
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
45
qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
46
47
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
1
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
1
In commit f0a08b0913befbd we changed the type of the PC from
2
target_ulong to vaddr. In doing so we inadvertently dropped the
3
zero-padding on the PC in trace lines (the second item inside the []
4
in these lines). They used to look like this on AArch64, for
5
instance:
2
6
3
The wfi instruction can be configured to be trapped by a higher exception
7
Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000]
4
level, such as the EL2 hypervisor. When the instruction is trapped, the
5
program counter should contain the address of the wfi instruction that
6
caused the exception. The program counter is adjusted for this in the wfi op
7
helper function.
8
8
9
However, this correction is done to env->pc, which only applies to AArch64
9
and now they look like this:
10
mode. For AArch32, the program counter is stored in env->regs[15]. This
10
Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000]
11
adds an if-else statement to modify the correct program counter location
12
based on the the current CPU mode.
13
11
14
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
12
and if the PC happens to be somewhere low like 0x5000
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
then the field is shown as /5000/.
14
15
This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier,
16
depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64
17
with no width specifier.
18
19
Restore the zero-padding by adding an 016 width specifier to
20
this tracing and a couple of others that were similarly recently
21
changed to use VADDR_PRIx without a width specifier.
22
23
We can't unfortunately restore the "32-bit guests are padded to
24
8 hex digits and 64-bit guests to 16 hex digits" behaviour so
25
easily.
26
27
Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr")
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
30
Reviewed-by: Anton Johansson <anjo@rev.ng>
31
Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
17
---
32
---
18
target/arm/op_helper.c | 7 ++++++-
33
accel/tcg/cpu-exec.c | 4 ++--
19
1 file changed, 6 insertions(+), 1 deletion(-)
34
accel/tcg/translate-all.c | 2 +-
35
2 files changed, 3 insertions(+), 3 deletions(-)
20
36
21
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
22
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/op_helper.c
39
--- a/accel/tcg/cpu-exec.c
24
+++ b/target/arm/op_helper.c
40
+++ b/accel/tcg/cpu-exec.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
41
@@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu,
26
}
42
if (qemu_log_in_addr_range(pc)) {
27
43
qemu_log_mask(CPU_LOG_EXEC,
28
if (target_el) {
44
"Trace %d: %p [%08" PRIx64
29
- env->pc -= insn_len;
45
- "/%" VADDR_PRIx "/%08x/%08x] %s\n",
30
+ if (env->aarch64) {
46
+ "/%016" VADDR_PRIx "/%08x/%08x] %s\n",
31
+ env->pc -= insn_len;
47
cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
32
+ } else {
48
tb->flags, tb->cflags, lookup_symbol(pc));
33
+ env->regs[15] -= insn_len;
49
34
+ }
50
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
35
+
51
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
36
raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
52
vaddr pc = log_pc(cpu, last_tb);
37
target_el);
53
if (qemu_log_in_addr_range(pc)) {
54
- qemu_log("Stopped execution of TB chain before %p [%"
55
+ qemu_log("Stopped execution of TB chain before %p [%016"
56
VADDR_PRIx "] %s\n",
57
last_tb->tc.ptr, pc, lookup_symbol(pc));
58
}
59
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/accel/tcg/translate-all.c
62
+++ b/accel/tcg/translate-all.c
63
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
64
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
65
vaddr pc = log_pc(cpu, tb);
66
if (qemu_log_in_addr_range(pc)) {
67
- qemu_log("cpu_io_recompile: rewound execution of TB to %"
68
+ qemu_log("cpu_io_recompile: rewound execution of TB to %016"
69
VADDR_PRIx "\n", pc);
70
}
38
}
71
}
39
--
72
--
40
2.20.1
73
2.34.1
41
74
42
75
diff view generated by jsdifflib
1
From: Masahiro Yamada <masahiroy@kernel.org>
1
From: Tong Ho <tong.ho@amd.com>
2
2
3
According to the specification "Semihosting for AArch32 and Aarch64",
3
Add a check in the bit-set operation to write the backstore
4
the SYS_OPEN operation should return:
4
only if the affected bit is 0 before.
5
5
6
- A nonzero handle if the call is successful
6
With this in place, there will be no need for callers to
7
- -1 if the call is not successful
7
do the checking in order to avoid unnecessary writes.
8
8
9
So, it should never return 0.
9
Signed-off-by: Tong Ho <tong.ho@amd.com>
10
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting
11
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
12
code hand out its own file descriptors"), the guest fd matched to the
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
host fd. It returned a nonzero handle on success since the fd 0 is
14
already used for stdin.
15
16
Now that the guest fd is the index of guestfd_array, it starts from 0.
17
18
I noticed this issue particularly because Trusted Firmware-A built with
19
PLAT=qemu is no longer working. Its io_semihosting driver only handles
20
a positive return value as a valid filehandle.
21
22
Basically, there are two ways to fix this:
23
24
- Use (guestfd - 1) as the index of guestfs_arrary. We need to insert
25
increment/decrement to convert the guestfd and the array index back
26
and forth.
27
28
- Keep using guestfd as the index of guestfs_array. The first entry
29
of guestfs_array is left unused.
30
31
I thought the latter is simpler. We end up with wasting a small piece
32
of memory for the unused first entry of guestfd_array, but this is
33
probably not a big deal.
34
35
Fixes: 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting code hand out its own file descriptors")
36
Cc: qemu-stable@nongnu.org
37
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20200109041228.10131-1-masahiroy@kernel.org
40
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
41
---
14
---
42
target/arm/arm-semi.c | 5 +++--
15
hw/nvram/xlnx-efuse.c | 11 +++++++++--
43
1 file changed, 3 insertions(+), 2 deletions(-)
16
1 file changed, 9 insertions(+), 2 deletions(-)
44
17
45
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
18
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
46
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/arm-semi.c
20
--- a/hw/nvram/xlnx-efuse.c
48
+++ b/target/arm/arm-semi.c
21
+++ b/hw/nvram/xlnx-efuse.c
49
@@ -XXX,XX +XXX,XX @@ static int alloc_guestfd(void)
22
@@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
50
guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD));
23
24
bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
25
{
26
+ uint32_t set, *row;
27
+
28
if (efuse_ro_bits_find(s, bit)) {
29
g_autofree char *path = object_get_canonical_path(OBJECT(s));
30
31
@@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
32
return false;
51
}
33
}
52
34
53
- for (i = 0; i < guestfd_array->len; i++) {
35
- s->fuse32[bit / 32] |= 1 << (bit % 32);
54
+ /* SYS_OPEN should return nonzero handle on success. Start guestfd from 1 */
36
- efuse_bdrv_sync(s, bit);
55
+ for (i = 1; i < guestfd_array->len; i++) {
37
+ /* Avoid back-end write unless there is a real update */
56
GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i);
38
+ row = &s->fuse32[bit / 32];
57
39
+ set = 1 << (bit % 32);
58
if (gf->type == GuestFDUnused) {
40
+ if (!(set & *row)) {
59
@@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd)
41
+ *row |= set;
60
return NULL;
42
+ efuse_bdrv_sync(s, bit);
61
}
43
+ }
62
44
return true;
63
- if (guestfd < 0 || guestfd >= guestfd_array->len) {
45
}
64
+ if (guestfd <= 0 || guestfd >= guestfd_array->len) {
65
return NULL;
66
}
67
46
68
--
47
--
69
2.20.1
48
2.34.1
70
49
71
50
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