1 | Latest arm queue, a mixed bag of features and bug fixes. | 1 | The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9: |
---|---|---|---|
2 | 2 | ||
3 | thanks | 3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000) |
4 | -- PMM | ||
5 | |||
6 | The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e: | ||
7 | |||
8 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (2020-01-17 12:13:17 +0000) | ||
9 | 4 | ||
10 | are available in the Git repository at: | 5 | are available in the Git repository at: |
11 | 6 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200117-1 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216 |
13 | 8 | ||
14 | for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9: | 9 | for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8: |
15 | 10 | ||
16 | target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +0000) | 11 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000) |
17 | 12 | ||
18 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
19 | Add model of the Netduino Plus 2 board | 14 | target-arm queue: |
20 | Some allwinner-a10 code cleanup | 15 | * Some mostly M-profile-related code cleanups |
21 | New test cases for cubieboard | 16 | * avocado: Retire the boot_linux.py AArch64 TCG tests |
22 | target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle | 17 | * hw/arm/smmuv3: Add GBPA register |
23 | i.MX: add an emulation for RNGC device | 18 | * arm/virt: don't try to spell out the accelerator |
24 | target/arm: adjust program counter for wfi exception in AArch32 | 19 | * hw/arm: Attach PSPI module to NPCM7XX SoC |
25 | arm/gicv3: update virtual irq state after IAR register read | 20 | * Some cleanup/refactoring patches aiming towards |
26 | Set IL bit correctly for syndrome information for data aborts | 21 | allowing building Arm targets without CONFIG_TCG |
27 | 22 | ||
28 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
29 | Alistair Francis (4): | 24 | Alex Bennée (1): |
30 | hw/misc: Add the STM32F4xx Sysconfig device | 25 | tests/avocado: retire the Aarch64 TCG tests from boot_linux.py |
31 | hw/misc: Add the STM32F4xx EXTI device | ||
32 | hw/arm: Add the STM32F4xx SoC | ||
33 | hw/arm: Add the Netduino Plus 2 | ||
34 | 26 | ||
35 | Jeff Kubascik (3): | 27 | Claudio Fontana (3): |
36 | target/arm: adjust program counter for wfi exception in AArch32 | 28 | target/arm: rename handle_semihosting to tcg_handle_semihosting |
37 | arm/gicv3: update virtual irq state after IAR register read | 29 | target/arm: wrap psci call with tcg_enabled |
38 | target/arm: Return correct IL bit in merge_syn_data_abort | 30 | target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() |
39 | 31 | ||
40 | Martin Kaiser (1): | 32 | Cornelia Huck (1): |
41 | i.MX: add an emulation for RNGC | 33 | arm/virt: don't try to spell out the accelerator |
42 | 34 | ||
43 | Masahiro Yamada (1): | 35 | Fabiano Rosas (7): |
44 | target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle | 36 | target/arm: Move PC alignment check |
37 | target/arm: Move cpregs code out of cpu.h | ||
38 | tests/avocado: Skip tests that require a missing accelerator | ||
39 | tests/avocado: Tag TCG tests with accel:tcg | ||
40 | target/arm: Use "max" as default cpu for the virt machine with KVM | ||
41 | tests/qtest: arm-cpu-features: Match tests to required accelerators | ||
42 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG | ||
45 | 43 | ||
46 | Philippe Mathieu-Daudé (5): | 44 | Hao Wu (3): |
47 | tests/boot_linux_console: Add initrd test for the CubieBoard | 45 | MAINTAINERS: Add myself to maintainers and remove Havard |
48 | tests/boot_linux_console: Add a SD card test for the CubieBoard | 46 | hw/ssi: Add Nuvoton PSPI Module |
49 | hw/arm/allwinner-a10: Move SoC definitions out of header | 47 | hw/arm: Attach PSPI module to NPCM7XX SoC |
50 | hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios() | ||
51 | hw/arm/allwinner-a10: Remove local qemu_irq variables | ||
52 | 48 | ||
53 | Richard Henderson (1): | 49 | Jean-Philippe Brucker (2): |
54 | target/arm: Set ISSIs16Bit in make_issinfo | 50 | hw/arm/smmu-common: Support 64-bit addresses |
51 | hw/arm/smmu-common: Fix TTB1 handling | ||
55 | 52 | ||
56 | hw/arm/Makefile.objs | 2 + | 53 | Mostafa Saleh (1): |
57 | hw/misc/Makefile.objs | 3 + | 54 | hw/arm/smmuv3: Add GBPA register |
58 | include/hw/arm/allwinner-a10.h | 7 - | ||
59 | include/hw/arm/fsl-imx25.h | 5 + | ||
60 | include/hw/arm/stm32f405_soc.h | 73 ++++++++ | ||
61 | include/hw/misc/imx_rngc.h | 35 ++++ | ||
62 | include/hw/misc/stm32f4xx_exti.h | 60 +++++++ | ||
63 | include/hw/misc/stm32f4xx_syscfg.h | 61 +++++++ | ||
64 | hw/arm/allwinner-a10.c | 39 +++-- | ||
65 | hw/arm/fsl-imx25.c | 11 ++ | ||
66 | hw/arm/netduinoplus2.c | 52 ++++++ | ||
67 | hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++ | ||
68 | hw/intc/arm_gicv3_cpuif.c | 3 + | ||
69 | hw/misc/imx_rngc.c | 278 ++++++++++++++++++++++++++++++ | ||
70 | hw/misc/stm32f4xx_exti.c | 188 ++++++++++++++++++++ | ||
71 | hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++ | ||
72 | target/arm/arm-semi.c | 5 +- | ||
73 | target/arm/op_helper.c | 7 +- | ||
74 | target/arm/tlb_helper.c | 2 +- | ||
75 | target/arm/translate.c | 3 + | ||
76 | MAINTAINERS | 14 ++ | ||
77 | default-configs/arm-softmmu.mak | 1 + | ||
78 | hw/arm/Kconfig | 10 ++ | ||
79 | hw/misc/Kconfig | 6 + | ||
80 | hw/misc/trace-events | 11 ++ | ||
81 | tests/acceptance/boot_linux_console.py | 85 ++++++++++ | ||
82 | 26 files changed, 1405 insertions(+), 29 deletions(-) | ||
83 | create mode 100644 include/hw/arm/stm32f405_soc.h | ||
84 | create mode 100644 include/hw/misc/imx_rngc.h | ||
85 | create mode 100644 include/hw/misc/stm32f4xx_exti.h | ||
86 | create mode 100644 include/hw/misc/stm32f4xx_syscfg.h | ||
87 | create mode 100644 hw/arm/netduinoplus2.c | ||
88 | create mode 100644 hw/arm/stm32f405_soc.c | ||
89 | create mode 100644 hw/misc/imx_rngc.c | ||
90 | create mode 100644 hw/misc/stm32f4xx_exti.c | ||
91 | create mode 100644 hw/misc/stm32f4xx_syscfg.c | ||
92 | 55 | ||
56 | Philippe Mathieu-Daudé (12): | ||
57 | hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro | ||
58 | target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation | ||
59 | target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope | ||
60 | target/arm: Constify ID_PFR1 on user emulation | ||
61 | target/arm: Convert CPUARMState::eabi to boolean | ||
62 | target/arm: Avoid resetting CPUARMState::eabi field | ||
63 | target/arm: Restrict CPUARMState::gicv3state to sysemu | ||
64 | target/arm: Restrict CPUARMState::arm_boot_info to sysemu | ||
65 | target/arm: Restrict CPUARMState::nvic to sysemu | ||
66 | target/arm: Store CPUARMState::nvic as NVICState* | ||
67 | target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' | ||
68 | hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency | ||
69 | |||
70 | MAINTAINERS | 8 +- | ||
71 | docs/system/arm/nuvoton.rst | 2 +- | ||
72 | hw/arm/smmuv3-internal.h | 7 + | ||
73 | include/hw/arm/npcm7xx.h | 2 + | ||
74 | include/hw/arm/smmu-common.h | 2 - | ||
75 | include/hw/arm/smmuv3.h | 1 + | ||
76 | include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++- | ||
77 | include/hw/ssi/npcm_pspi.h | 53 ++++++++ | ||
78 | linux-user/user-internals.h | 2 +- | ||
79 | target/arm/cpregs.h | 98 ++++++++++++++ | ||
80 | target/arm/cpu.h | 228 ++------------------------------- | ||
81 | target/arm/internals.h | 14 -- | ||
82 | hw/arm/npcm7xx.c | 25 +++- | ||
83 | hw/arm/smmu-common.c | 4 +- | ||
84 | hw/arm/smmuv3.c | 43 ++++++- | ||
85 | hw/arm/virt.c | 10 +- | ||
86 | hw/intc/armv7m_nvic.c | 38 ++---- | ||
87 | hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++ | ||
88 | linux-user/arm/cpu_loop.c | 4 +- | ||
89 | target/arm/cpu.c | 5 +- | ||
90 | target/arm/cpu_tcg.c | 3 + | ||
91 | target/arm/helper.c | 31 +++-- | ||
92 | target/arm/m_helper.c | 86 +++++++------ | ||
93 | target/arm/machine.c | 18 +-- | ||
94 | tests/qtest/arm-cpu-features.c | 28 ++-- | ||
95 | hw/arm/Kconfig | 1 + | ||
96 | hw/ssi/meson.build | 2 +- | ||
97 | hw/ssi/trace-events | 5 + | ||
98 | tests/avocado/avocado_qemu/__init__.py | 4 + | ||
99 | tests/avocado/boot_linux.py | 48 ++----- | ||
100 | tests/avocado/boot_linux_console.py | 1 + | ||
101 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++- | ||
102 | tests/avocado/reverse_debugging.py | 8 ++ | ||
103 | tests/qtest/meson.build | 4 +- | ||
104 | 34 files changed, 798 insertions(+), 399 deletions(-) | ||
105 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
106 | create mode 100644 hw/ssi/npcm_pspi.c | ||
107 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, | ||
4 | similarly to automatic conversion from commit 8063396bf3 | ||
5 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-2-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/intc/armv7m_nvic.h | 5 +---- | ||
13 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/intc/armv7m_nvic.h | ||
18 | +++ b/include/hw/intc/armv7m_nvic.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "qom/object.h" | ||
21 | |||
22 | #define TYPE_NVIC "armv7m_nvic" | ||
23 | - | ||
24 | -typedef struct NVICState NVICState; | ||
25 | -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, | ||
26 | - TYPE_NVIC) | ||
27 | +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) | ||
28 | |||
29 | /* Highest permitted number of exceptions (architectural limit) */ | ||
30 | #define NVIC_MAX_VECTORS 512 | ||
31 | -- | ||
32 | 2.34.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230206223502.25122-3-philmd@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | target/arm/m_helper.c | 11 ++++++++--- | ||
10 | 1 file changed, 8 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/m_helper.c | ||
15 | +++ b/target/arm/m_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
17 | return 0; | ||
18 | } | ||
19 | |||
20 | -#else | ||
21 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
22 | +{ | ||
23 | + return ARMMMUIdx_MUser; | ||
24 | +} | ||
25 | + | ||
26 | +#else /* !CONFIG_USER_ONLY */ | ||
27 | |||
28 | /* | ||
29 | * What kind of stack write are we doing? This affects how exceptions | ||
30 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
31 | return tt_resp; | ||
32 | } | ||
33 | |||
34 | -#endif /* !CONFIG_USER_ONLY */ | ||
35 | - | ||
36 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
37 | bool secstate, bool priv, bool negpri) | ||
38 | { | ||
39 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
40 | |||
41 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
42 | } | ||
43 | + | ||
44 | +#endif /* !CONFIG_USER_ONLY */ | ||
45 | -- | ||
46 | 2.34.1 | ||
47 | |||
48 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair@alistair23.me> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Alistair Francis <alistair@alistair23.me> | 3 | arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | are only used for system emulation in m_helper.c. |
5 | Message-id: 1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me | 5 | Move the definitions to avoid prototype forward declarations. |
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-4-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | hw/arm/Makefile.objs | 1 + | 12 | target/arm/internals.h | 14 -------- |
9 | include/hw/arm/stm32f405_soc.h | 73 ++++++++ | 13 | target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- |
10 | hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++ | 14 | 2 files changed, 37 insertions(+), 51 deletions(-) |
11 | MAINTAINERS | 8 + | ||
12 | 4 files changed, 384 insertions(+) | ||
13 | create mode 100644 include/hw/arm/stm32f405_soc.h | ||
14 | create mode 100644 hw/arm/stm32f405_soc.c | ||
15 | 15 | ||
16 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/Makefile.objs | 18 | --- a/target/arm/internals.h |
19 | +++ b/hw/arm/Makefile.objs | 19 | +++ b/target/arm/internals.h |
20 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STRONGARM) += strongarm.o | 20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
21 | obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o | 21 | |
22 | obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o | 22 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
23 | obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o | 23 | |
24 | +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o | 24 | -/* |
25 | obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o | 25 | - * Return the MMU index for a v7M CPU with all relevant information |
26 | obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o | 26 | - * manually specified. |
27 | obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o | 27 | - */ |
28 | diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h | 28 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
29 | new file mode 100644 | 29 | - bool secstate, bool priv, bool negpri); |
30 | index XXXXXXX..XXXXXXX | 30 | - |
31 | --- /dev/null | 31 | -/* |
32 | +++ b/include/hw/arm/stm32f405_soc.h | 32 | - * Return the MMU index for a v7M CPU in the specified security and |
33 | @@ -XXX,XX +XXX,XX @@ | 33 | - * privilege state. |
34 | +/* | 34 | - */ |
35 | + * STM32F405 SoC | 35 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
36 | + * | 36 | - bool secstate, bool priv); |
37 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | 37 | - |
38 | + * | 38 | /* Return the MMU index for a v7M CPU in the specified security state */ |
39 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 39 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); |
40 | + * of this software and associated documentation files (the "Software"), to deal | 40 | |
41 | + * in the Software without restriction, including without limitation the rights | 41 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
42 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 42 | index XXXXXXX..XXXXXXX 100644 |
43 | + * copies of the Software, and to permit persons to whom the Software is | 43 | --- a/target/arm/m_helper.c |
44 | + * furnished to do so, subject to the following conditions: | 44 | +++ b/target/arm/m_helper.c |
45 | + * | 45 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
46 | + * The above copyright notice and this permission notice shall be included in | 46 | |
47 | + * all copies or substantial portions of the Software. | 47 | #else /* !CONFIG_USER_ONLY */ |
48 | + * | 48 | |
49 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 49 | +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
50 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 50 | + bool secstate, bool priv, bool negpri) |
51 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 51 | +{ |
52 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 52 | + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; |
53 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
54 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
55 | + * THE SOFTWARE. | ||
56 | + */ | ||
57 | + | 53 | + |
58 | +#ifndef HW_ARM_STM32F405_SOC_H | 54 | + if (priv) { |
59 | +#define HW_ARM_STM32F405_SOC_H | 55 | + mmu_idx |= ARM_MMU_IDX_M_PRIV; |
60 | + | ||
61 | +#include "hw/misc/stm32f4xx_syscfg.h" | ||
62 | +#include "hw/timer/stm32f2xx_timer.h" | ||
63 | +#include "hw/char/stm32f2xx_usart.h" | ||
64 | +#include "hw/adc/stm32f2xx_adc.h" | ||
65 | +#include "hw/misc/stm32f4xx_exti.h" | ||
66 | +#include "hw/or-irq.h" | ||
67 | +#include "hw/ssi/stm32f2xx_spi.h" | ||
68 | +#include "hw/arm/armv7m.h" | ||
69 | + | ||
70 | +#define TYPE_STM32F405_SOC "stm32f405-soc" | ||
71 | +#define STM32F405_SOC(obj) \ | ||
72 | + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) | ||
73 | + | ||
74 | +#define STM_NUM_USARTS 7 | ||
75 | +#define STM_NUM_TIMERS 4 | ||
76 | +#define STM_NUM_ADCS 6 | ||
77 | +#define STM_NUM_SPIS 6 | ||
78 | + | ||
79 | +#define FLASH_BASE_ADDRESS 0x08000000 | ||
80 | +#define FLASH_SIZE (1024 * 1024) | ||
81 | +#define SRAM_BASE_ADDRESS 0x20000000 | ||
82 | +#define SRAM_SIZE (192 * 1024) | ||
83 | + | ||
84 | +typedef struct STM32F405State { | ||
85 | + /*< private >*/ | ||
86 | + SysBusDevice parent_obj; | ||
87 | + /*< public >*/ | ||
88 | + | ||
89 | + char *cpu_type; | ||
90 | + | ||
91 | + ARMv7MState armv7m; | ||
92 | + | ||
93 | + STM32F4xxSyscfgState syscfg; | ||
94 | + STM32F4xxExtiState exti; | ||
95 | + STM32F2XXUsartState usart[STM_NUM_USARTS]; | ||
96 | + STM32F2XXTimerState timer[STM_NUM_TIMERS]; | ||
97 | + qemu_or_irq adc_irqs; | ||
98 | + STM32F2XXADCState adc[STM_NUM_ADCS]; | ||
99 | + STM32F2XXSPIState spi[STM_NUM_SPIS]; | ||
100 | + | ||
101 | + MemoryRegion sram; | ||
102 | + MemoryRegion flash; | ||
103 | + MemoryRegion flash_alias; | ||
104 | +} STM32F405State; | ||
105 | + | ||
106 | +#endif | ||
107 | diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c | ||
108 | new file mode 100644 | ||
109 | index XXXXXXX..XXXXXXX | ||
110 | --- /dev/null | ||
111 | +++ b/hw/arm/stm32f405_soc.c | ||
112 | @@ -XXX,XX +XXX,XX @@ | ||
113 | +/* | ||
114 | + * STM32F405 SoC | ||
115 | + * | ||
116 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | ||
117 | + * | ||
118 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
119 | + * of this software and associated documentation files (the "Software"), to deal | ||
120 | + * in the Software without restriction, including without limitation the rights | ||
121 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
122 | + * copies of the Software, and to permit persons to whom the Software is | ||
123 | + * furnished to do so, subject to the following conditions: | ||
124 | + * | ||
125 | + * The above copyright notice and this permission notice shall be included in | ||
126 | + * all copies or substantial portions of the Software. | ||
127 | + * | ||
128 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
129 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
130 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
131 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
132 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
133 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
134 | + * THE SOFTWARE. | ||
135 | + */ | ||
136 | + | ||
137 | +#include "qemu/osdep.h" | ||
138 | +#include "qapi/error.h" | ||
139 | +#include "qemu-common.h" | ||
140 | +#include "exec/address-spaces.h" | ||
141 | +#include "sysemu/sysemu.h" | ||
142 | +#include "hw/arm/stm32f405_soc.h" | ||
143 | +#include "hw/misc/unimp.h" | ||
144 | + | ||
145 | +#define SYSCFG_ADD 0x40013800 | ||
146 | +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, | ||
147 | + 0x40004C00, 0x40005000, 0x40011400, | ||
148 | + 0x40007800, 0x40007C00 }; | ||
149 | +/* At the moment only Timer 2 to 5 are modelled */ | ||
150 | +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, | ||
151 | + 0x40000800, 0x40000C00 }; | ||
152 | +#define ADC_ADDR 0x40012000 | ||
153 | +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, | ||
154 | + 0x40013400, 0x40015000, 0x40015400 }; | ||
155 | +#define EXTI_ADDR 0x40013C00 | ||
156 | + | ||
157 | +#define SYSCFG_IRQ 71 | ||
158 | +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; | ||
159 | +static const int timer_irq[] = { 28, 29, 30, 50 }; | ||
160 | +#define ADC_IRQ 18 | ||
161 | +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; | ||
162 | +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, | ||
163 | + 40, 40, 40, 40, 40} ; | ||
164 | + | ||
165 | + | ||
166 | +static void stm32f405_soc_initfn(Object *obj) | ||
167 | +{ | ||
168 | + STM32F405State *s = STM32F405_SOC(obj); | ||
169 | + int i; | ||
170 | + | ||
171 | + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), | ||
172 | + TYPE_ARMV7M); | ||
173 | + | ||
174 | + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), | ||
175 | + TYPE_STM32F4XX_SYSCFG); | ||
176 | + | ||
177 | + for (i = 0; i < STM_NUM_USARTS; i++) { | ||
178 | + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], | ||
179 | + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); | ||
180 | + } | 56 | + } |
181 | + | 57 | + |
182 | + for (i = 0; i < STM_NUM_TIMERS; i++) { | 58 | + if (negpri) { |
183 | + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], | 59 | + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; |
184 | + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); | ||
185 | + } | 60 | + } |
186 | + | 61 | + |
187 | + for (i = 0; i < STM_NUM_ADCS; i++) { | 62 | + if (secstate) { |
188 | + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), | 63 | + mmu_idx |= ARM_MMU_IDX_M_S; |
189 | + TYPE_STM32F2XX_ADC); | ||
190 | + } | 64 | + } |
191 | + | 65 | + |
192 | + for (i = 0; i < STM_NUM_SPIS; i++) { | 66 | + return mmu_idx; |
193 | + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), | ||
194 | + TYPE_STM32F2XX_SPI); | ||
195 | + } | ||
196 | + | ||
197 | + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), | ||
198 | + TYPE_STM32F4XX_EXTI); | ||
199 | +} | 67 | +} |
200 | + | 68 | + |
201 | +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) | 69 | +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
70 | + bool secstate, bool priv) | ||
202 | +{ | 71 | +{ |
203 | + STM32F405State *s = STM32F405_SOC(dev_soc); | 72 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); |
204 | + MemoryRegion *system_memory = get_system_memory(); | ||
205 | + DeviceState *dev, *armv7m; | ||
206 | + SysBusDevice *busdev; | ||
207 | + Error *err = NULL; | ||
208 | + int i; | ||
209 | + | 73 | + |
210 | + memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE, | 74 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); |
211 | + &err); | ||
212 | + if (err != NULL) { | ||
213 | + error_propagate(errp, err); | ||
214 | + return; | ||
215 | + } | ||
216 | + memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias", | ||
217 | + &s->flash, 0, FLASH_SIZE); | ||
218 | + | ||
219 | + memory_region_set_readonly(&s->flash, true); | ||
220 | + memory_region_set_readonly(&s->flash_alias, true); | ||
221 | + | ||
222 | + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); | ||
223 | + memory_region_add_subregion(system_memory, 0, &s->flash_alias); | ||
224 | + | ||
225 | + memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, | ||
226 | + &err); | ||
227 | + if (err != NULL) { | ||
228 | + error_propagate(errp, err); | ||
229 | + return; | ||
230 | + } | ||
231 | + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); | ||
232 | + | ||
233 | + armv7m = DEVICE(&s->armv7m); | ||
234 | + qdev_prop_set_uint32(armv7m, "num-irq", 96); | ||
235 | + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); | ||
236 | + qdev_prop_set_bit(armv7m, "enable-bitband", true); | ||
237 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory), | ||
238 | + "memory", &error_abort); | ||
239 | + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | ||
240 | + if (err != NULL) { | ||
241 | + error_propagate(errp, err); | ||
242 | + return; | ||
243 | + } | ||
244 | + | ||
245 | + /* System configuration controller */ | ||
246 | + dev = DEVICE(&s->syscfg); | ||
247 | + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); | ||
248 | + if (err != NULL) { | ||
249 | + error_propagate(errp, err); | ||
250 | + return; | ||
251 | + } | ||
252 | + busdev = SYS_BUS_DEVICE(dev); | ||
253 | + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); | ||
254 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); | ||
255 | + | ||
256 | + /* Attach UART (uses USART registers) and USART controllers */ | ||
257 | + for (i = 0; i < STM_NUM_USARTS; i++) { | ||
258 | + dev = DEVICE(&(s->usart[i])); | ||
259 | + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); | ||
260 | + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); | ||
261 | + if (err != NULL) { | ||
262 | + error_propagate(errp, err); | ||
263 | + return; | ||
264 | + } | ||
265 | + busdev = SYS_BUS_DEVICE(dev); | ||
266 | + sysbus_mmio_map(busdev, 0, usart_addr[i]); | ||
267 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); | ||
268 | + } | ||
269 | + | ||
270 | + /* Timer 2 to 5 */ | ||
271 | + for (i = 0; i < STM_NUM_TIMERS; i++) { | ||
272 | + dev = DEVICE(&(s->timer[i])); | ||
273 | + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); | ||
274 | + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); | ||
275 | + if (err != NULL) { | ||
276 | + error_propagate(errp, err); | ||
277 | + return; | ||
278 | + } | ||
279 | + busdev = SYS_BUS_DEVICE(dev); | ||
280 | + sysbus_mmio_map(busdev, 0, timer_addr[i]); | ||
281 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); | ||
282 | + } | ||
283 | + | ||
284 | + /* ADC device, the IRQs are ORed together */ | ||
285 | + object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs, | ||
286 | + sizeof(s->adc_irqs), TYPE_OR_IRQ, | ||
287 | + &err, NULL); | ||
288 | + if (err != NULL) { | ||
289 | + error_propagate(errp, err); | ||
290 | + return; | ||
291 | + } | ||
292 | + object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS, | ||
293 | + "num-lines", &err); | ||
294 | + object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err); | ||
295 | + if (err != NULL) { | ||
296 | + error_propagate(errp, err); | ||
297 | + return; | ||
298 | + } | ||
299 | + qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, | ||
300 | + qdev_get_gpio_in(armv7m, ADC_IRQ)); | ||
301 | + | ||
302 | + dev = DEVICE(&(s->adc[i])); | ||
303 | + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); | ||
304 | + if (err != NULL) { | ||
305 | + error_propagate(errp, err); | ||
306 | + return; | ||
307 | + } | ||
308 | + busdev = SYS_BUS_DEVICE(dev); | ||
309 | + sysbus_mmio_map(busdev, 0, ADC_ADDR); | ||
310 | + sysbus_connect_irq(busdev, 0, | ||
311 | + qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); | ||
312 | + | ||
313 | + /* SPI devices */ | ||
314 | + for (i = 0; i < STM_NUM_SPIS; i++) { | ||
315 | + dev = DEVICE(&(s->spi[i])); | ||
316 | + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); | ||
317 | + if (err != NULL) { | ||
318 | + error_propagate(errp, err); | ||
319 | + return; | ||
320 | + } | ||
321 | + busdev = SYS_BUS_DEVICE(dev); | ||
322 | + sysbus_mmio_map(busdev, 0, spi_addr[i]); | ||
323 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); | ||
324 | + } | ||
325 | + | ||
326 | + /* EXTI device */ | ||
327 | + dev = DEVICE(&s->exti); | ||
328 | + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); | ||
329 | + if (err != NULL) { | ||
330 | + error_propagate(errp, err); | ||
331 | + return; | ||
332 | + } | ||
333 | + busdev = SYS_BUS_DEVICE(dev); | ||
334 | + sysbus_mmio_map(busdev, 0, EXTI_ADDR); | ||
335 | + for (i = 0; i < 16; i++) { | ||
336 | + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); | ||
337 | + } | ||
338 | + for (i = 0; i < 16; i++) { | ||
339 | + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); | ||
340 | + } | ||
341 | + | ||
342 | + create_unimplemented_device("timer[7]", 0x40001400, 0x400); | ||
343 | + create_unimplemented_device("timer[12]", 0x40001800, 0x400); | ||
344 | + create_unimplemented_device("timer[6]", 0x40001000, 0x400); | ||
345 | + create_unimplemented_device("timer[13]", 0x40001C00, 0x400); | ||
346 | + create_unimplemented_device("timer[14]", 0x40002000, 0x400); | ||
347 | + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400); | ||
348 | + create_unimplemented_device("WWDG", 0x40002C00, 0x400); | ||
349 | + create_unimplemented_device("IWDG", 0x40003000, 0x400); | ||
350 | + create_unimplemented_device("I2S2ext", 0x40003000, 0x400); | ||
351 | + create_unimplemented_device("I2S3ext", 0x40004000, 0x400); | ||
352 | + create_unimplemented_device("I2C1", 0x40005400, 0x400); | ||
353 | + create_unimplemented_device("I2C2", 0x40005800, 0x400); | ||
354 | + create_unimplemented_device("I2C3", 0x40005C00, 0x400); | ||
355 | + create_unimplemented_device("CAN1", 0x40006400, 0x400); | ||
356 | + create_unimplemented_device("CAN2", 0x40006800, 0x400); | ||
357 | + create_unimplemented_device("PWR", 0x40007000, 0x400); | ||
358 | + create_unimplemented_device("DAC", 0x40007400, 0x400); | ||
359 | + create_unimplemented_device("timer[1]", 0x40010000, 0x400); | ||
360 | + create_unimplemented_device("timer[8]", 0x40010400, 0x400); | ||
361 | + create_unimplemented_device("SDIO", 0x40012C00, 0x400); | ||
362 | + create_unimplemented_device("timer[9]", 0x40014000, 0x400); | ||
363 | + create_unimplemented_device("timer[10]", 0x40014400, 0x400); | ||
364 | + create_unimplemented_device("timer[11]", 0x40014800, 0x400); | ||
365 | + create_unimplemented_device("GPIOA", 0x40020000, 0x400); | ||
366 | + create_unimplemented_device("GPIOB", 0x40020400, 0x400); | ||
367 | + create_unimplemented_device("GPIOC", 0x40020800, 0x400); | ||
368 | + create_unimplemented_device("GPIOD", 0x40020C00, 0x400); | ||
369 | + create_unimplemented_device("GPIOE", 0x40021000, 0x400); | ||
370 | + create_unimplemented_device("GPIOF", 0x40021400, 0x400); | ||
371 | + create_unimplemented_device("GPIOG", 0x40021800, 0x400); | ||
372 | + create_unimplemented_device("GPIOH", 0x40021C00, 0x400); | ||
373 | + create_unimplemented_device("GPIOI", 0x40022000, 0x400); | ||
374 | + create_unimplemented_device("CRC", 0x40023000, 0x400); | ||
375 | + create_unimplemented_device("RCC", 0x40023800, 0x400); | ||
376 | + create_unimplemented_device("Flash Int", 0x40023C00, 0x400); | ||
377 | + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400); | ||
378 | + create_unimplemented_device("DMA1", 0x40026000, 0x400); | ||
379 | + create_unimplemented_device("DMA2", 0x40026400, 0x400); | ||
380 | + create_unimplemented_device("Ethernet", 0x40028000, 0x1400); | ||
381 | + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000); | ||
382 | + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000); | ||
383 | + create_unimplemented_device("DCMI", 0x50050000, 0x400); | ||
384 | + create_unimplemented_device("RNG", 0x50060800, 0x400); | ||
385 | +} | 75 | +} |
386 | + | 76 | + |
387 | +static Property stm32f405_soc_properties[] = { | 77 | +/* Return the MMU index for a v7M CPU in the specified security state */ |
388 | + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), | 78 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
389 | + DEFINE_PROP_END_OF_LIST(), | 79 | +{ |
390 | +}; | 80 | + bool priv = arm_v7m_is_handler_mode(env) || |
81 | + !(env->v7m.control[secstate] & 1); | ||
391 | + | 82 | + |
392 | +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) | 83 | + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
393 | +{ | ||
394 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
395 | + | ||
396 | + dc->realize = stm32f405_soc_realize; | ||
397 | + dc->props = stm32f405_soc_properties; | ||
398 | + /* No vmstate or reset required: device has no internal state */ | ||
399 | +} | 84 | +} |
400 | + | 85 | + |
401 | +static const TypeInfo stm32f405_soc_info = { | 86 | /* |
402 | + .name = TYPE_STM32F405_SOC, | 87 | * What kind of stack write are we doing? This affects how exceptions |
403 | + .parent = TYPE_SYS_BUS_DEVICE, | 88 | * generated during the stacking are treated. |
404 | + .instance_size = sizeof(STM32F405State), | 89 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
405 | + .instance_init = stm32f405_soc_initfn, | 90 | return tt_resp; |
406 | + .class_init = stm32f405_soc_class_init, | 91 | } |
407 | +}; | 92 | |
408 | + | 93 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
409 | +static void stm32f405_soc_types(void) | 94 | - bool secstate, bool priv, bool negpri) |
410 | +{ | 95 | -{ |
411 | + type_register_static(&stm32f405_soc_info); | 96 | - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; |
412 | +} | 97 | - |
413 | + | 98 | - if (priv) { |
414 | +type_init(stm32f405_soc_types) | 99 | - mmu_idx |= ARM_MMU_IDX_M_PRIV; |
415 | diff --git a/MAINTAINERS b/MAINTAINERS | 100 | - } |
416 | index XXXXXXX..XXXXXXX 100644 | 101 | - |
417 | --- a/MAINTAINERS | 102 | - if (negpri) { |
418 | +++ b/MAINTAINERS | 103 | - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; |
419 | @@ -XXX,XX +XXX,XX @@ F: hw/adc/* | 104 | - } |
420 | F: hw/ssi/stm32f2xx_spi.c | 105 | - |
421 | F: include/hw/*/stm32*.h | 106 | - if (secstate) { |
422 | 107 | - mmu_idx |= ARM_MMU_IDX_M_S; | |
423 | +STM32F405 | 108 | - } |
424 | +M: Alistair Francis <alistair@alistair23.me> | 109 | - |
425 | +M: Peter Maydell <peter.maydell@linaro.org> | 110 | - return mmu_idx; |
426 | +S: Maintained | 111 | -} |
427 | +F: hw/arm/stm32f405_soc.c | 112 | - |
428 | +F: hw/misc/stm32f4xx_syscfg.c | 113 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
429 | +F: hw/misc/stm32f4xx_exti.c | 114 | - bool secstate, bool priv) |
430 | + | 115 | -{ |
431 | Netduino 2 | 116 | - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); |
432 | M: Alistair Francis <alistair@alistair23.me> | 117 | - |
433 | M: Peter Maydell <peter.maydell@linaro.org> | 118 | - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); |
119 | -} | ||
120 | - | ||
121 | -/* Return the MMU index for a v7M CPU in the specified security state */ | ||
122 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
123 | -{ | ||
124 | - bool priv = arm_v7m_is_handler_mode(env) || | ||
125 | - !(env->v7m.control[secstate] & 1); | ||
126 | - | ||
127 | - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
128 | -} | ||
129 | - | ||
130 | #endif /* !CONFIG_USER_ONLY */ | ||
434 | -- | 131 | -- |
435 | 2.20.1 | 132 | 2.34.1 |
436 | 133 | ||
437 | 134 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Message-id: 20230206223502.25122-5-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper.c | 12 ++++++++++-- | ||
9 | 1 file changed, 10 insertions(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/helper.c | ||
14 | +++ b/target/arm/helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
16 | } | ||
17 | } | ||
18 | |||
19 | +#ifndef CONFIG_USER_ONLY | ||
20 | /* | ||
21 | * We don't know until after realize whether there's a GICv3 | ||
22 | * attached, and that is what registers the gicv3 sysregs. | ||
23 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
24 | return pfr1; | ||
25 | } | ||
26 | |||
27 | -#ifndef CONFIG_USER_ONLY | ||
28 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
29 | { | ||
30 | ARMCPU *cpu = env_archcpu(env); | ||
31 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
32 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | ||
33 | .access = PL1_R, .type = ARM_CP_NO_RAW, | ||
34 | .accessfn = access_aa32_tid3, | ||
35 | +#ifdef CONFIG_USER_ONLY | ||
36 | + .type = ARM_CP_CONST, | ||
37 | + .resetvalue = cpu->isar.id_pfr1, | ||
38 | +#else | ||
39 | + .type = ARM_CP_NO_RAW, | ||
40 | + .accessfn = access_aa32_tid3, | ||
41 | .readfn = id_pfr1_read, | ||
42 | - .writefn = arm_cp_write_ignore }, | ||
43 | + .writefn = arm_cp_write_ignore | ||
44 | +#endif | ||
45 | + }, | ||
46 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
48 | .access = PL1_R, .type = ARM_CP_CONST, | ||
49 | -- | ||
50 | 2.34.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230206223502.25122-6-philmd@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | linux-user/user-internals.h | 2 +- | ||
10 | target/arm/cpu.h | 2 +- | ||
11 | linux-user/arm/cpu_loop.c | 4 ++-- | ||
12 | 3 files changed, 4 insertions(+), 4 deletions(-) | ||
13 | |||
14 | diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/linux-user/user-internals.h | ||
17 | +++ b/linux-user/user-internals.h | ||
18 | @@ -XXX,XX +XXX,XX @@ void print_termios(void *arg); | ||
19 | #ifdef TARGET_ARM | ||
20 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) | ||
21 | { | ||
22 | - return cpu_env->eabi == 1; | ||
23 | + return cpu_env->eabi; | ||
24 | } | ||
25 | #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) | ||
26 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } | ||
27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/cpu.h | ||
30 | +++ b/target/arm/cpu.h | ||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
32 | |||
33 | #if defined(CONFIG_USER_ONLY) | ||
34 | /* For usermode syscall translation. */ | ||
35 | - int eabi; | ||
36 | + bool eabi; | ||
37 | #endif | ||
38 | |||
39 | struct CPUBreakpoint *cpu_breakpoint[16]; | ||
40 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/linux-user/arm/cpu_loop.c | ||
43 | +++ b/linux-user/arm/cpu_loop.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
45 | break; | ||
46 | case EXCP_SWI: | ||
47 | { | ||
48 | - env->eabi = 1; | ||
49 | + env->eabi = true; | ||
50 | /* system call */ | ||
51 | if (env->thumb) { | ||
52 | /* Thumb is always EABI style with syscall number in r7 */ | ||
53 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
54 | * > 0xfffff and are handled below as out-of-range. | ||
55 | */ | ||
56 | n ^= ARM_SYSCALL_BASE; | ||
57 | - env->eabi = 0; | ||
58 | + env->eabi = false; | ||
59 | } | ||
60 | } | ||
61 | |||
62 | -- | ||
63 | 2.34.1 | ||
64 | |||
65 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We won't reuse the CPU IRQ/FIQ variables. Simplify by calling | 3 | Although the 'eabi' field is only used in user emulation where |
4 | qdev_get_gpio_in() in place. | 4 | CPU reset doesn't occur, it doesn't belong to the area to reset. |
5 | Move it after the 'end_reset_fields' for consistency. | ||
5 | 6 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20191230110953.25496-6-f4bug@amsat.org | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20230206223502.25122-7-philmd@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | 11 | --- |
11 | hw/arm/allwinner-a10.c | 9 ++++----- | 12 | target/arm/cpu.h | 9 ++++----- |
12 | 1 file changed, 4 insertions(+), 5 deletions(-) | 13 | 1 file changed, 4 insertions(+), 5 deletions(-) |
13 | 14 | ||
14 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/allwinner-a10.c | 17 | --- a/target/arm/cpu.h |
17 | +++ b/hw/arm/allwinner-a10.c | 18 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
19 | { | 20 | ARMVectorReg zarray[ARM_MAX_VQ * 16]; |
20 | AwA10State *s = AW_A10(dev); | 21 | #endif |
21 | SysBusDevice *sysbusdev; | 22 | |
22 | - qemu_irq fiq, irq; | 23 | -#if defined(CONFIG_USER_ONLY) |
23 | Error *err = NULL; | 24 | - /* For usermode syscall translation. */ |
24 | 25 | - bool eabi; | |
25 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | 26 | -#endif |
26 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 27 | - |
27 | error_propagate(errp, err); | 28 | struct CPUBreakpoint *cpu_breakpoint[16]; |
28 | return; | 29 | struct CPUWatchpoint *cpu_watchpoint[16]; |
29 | } | 30 | |
30 | - irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ); | 31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
31 | - fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ); | 32 | const struct arm_boot_info *boot_info; |
32 | 33 | /* Store GICv3CPUState to access from this struct */ | |
33 | object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); | 34 | void *gicv3state; |
34 | if (err != NULL) { | 35 | +#if defined(CONFIG_USER_ONLY) |
35 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 36 | + /* For usermode syscall translation. */ |
36 | } | 37 | + bool eabi; |
37 | sysbusdev = SYS_BUS_DEVICE(&s->intc); | 38 | +#endif /* CONFIG_USER_ONLY */ |
38 | sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); | 39 | |
39 | - sysbus_connect_irq(sysbusdev, 0, irq); | 40 | #ifdef TARGET_TAGGED_ADDRESSES |
40 | - sysbus_connect_irq(sysbusdev, 1, fiq); | 41 | /* Linux syscall tagged address support */ |
41 | + sysbus_connect_irq(sysbusdev, 0, | ||
42 | + qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); | ||
43 | + sysbus_connect_irq(sysbusdev, 1, | ||
44 | + qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); | ||
45 | qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); | ||
46 | |||
47 | object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); | ||
48 | -- | 42 | -- |
49 | 2.20.1 | 43 | 2.34.1 |
50 | 44 | ||
51 | 45 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Message-id: 20230206223502.25122-8-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 3 ++- | ||
9 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
16 | |||
17 | void *nvic; | ||
18 | const struct arm_boot_info *boot_info; | ||
19 | +#if !defined(CONFIG_USER_ONLY) | ||
20 | /* Store GICv3CPUState to access from this struct */ | ||
21 | void *gicv3state; | ||
22 | -#if defined(CONFIG_USER_ONLY) | ||
23 | +#else /* CONFIG_USER_ONLY */ | ||
24 | /* For usermode syscall translation. */ | ||
25 | bool eabi; | ||
26 | #endif /* CONFIG_USER_ONLY */ | ||
27 | -- | ||
28 | 2.34.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | During the conversion to decodetree, the setting of | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | ISSIs16Bit got lost. This causes the guest os to | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | incorrectly adjust trapping memory operations. | 5 | Message-id: 20230206223502.25122-9-philmd@linaro.org |
6 | |||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)") | ||
9 | Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20200117004618.2742-3-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 7 | --- |
15 | target/arm/translate.c | 3 +++ | 8 | target/arm/cpu.h | 2 +- |
16 | 1 file changed, 3 insertions(+) | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
17 | 10 | ||
18 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
19 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/translate.c | 13 | --- a/target/arm/cpu.h |
21 | +++ b/target/arm/translate.c | 14 | +++ b/target/arm/cpu.h |
22 | @@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
23 | /* ISS not valid if writeback */ | 16 | } sau; |
24 | if (p && !w) { | 17 | |
25 | ret = rd; | 18 | void *nvic; |
26 | + if (s->base.pc_next - s->pc_curr == 2) { | 19 | - const struct arm_boot_info *boot_info; |
27 | + ret |= ISSIs16Bit; | 20 | #if !defined(CONFIG_USER_ONLY) |
28 | + } | 21 | + const struct arm_boot_info *boot_info; |
29 | } else { | 22 | /* Store GICv3CPUState to access from this struct */ |
30 | ret = ISSInvalid; | 23 | void *gicv3state; |
31 | } | 24 | #else /* CONFIG_USER_ONLY */ |
32 | -- | 25 | -- |
33 | 2.20.1 | 26 | 2.34.1 |
34 | 27 | ||
35 | 28 | diff view generated by jsdifflib |
1 | From: Jeff Kubascik <jeff.kubascik@dornerworks.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The IL bit is set for 32-bit instructions, thus passing false | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | with the is_16bit parameter to syn_data_abort_with_iss() makes | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | a syn mask that always has the IL bit set. | 5 | Message-id: 20230206223502.25122-10-philmd@linaro.org |
6 | |||
7 | Pass is_16bit as true to make the initial syn mask have IL=0, | ||
8 | so that the final IL value comes from or'ing template_syn. | ||
9 | |||
10 | Cc: qemu-stable@nongnu.org | ||
11 | Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts") | ||
12 | Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20200117004618.2742-2-richard.henderson@linaro.org | ||
15 | [rth: Extracted this as a self-contained bug fix from a larger patch] | ||
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 7 | --- |
20 | target/arm/tlb_helper.c | 2 +- | 8 | target/arm/cpu.h | 2 +- |
21 | 1 file changed, 1 insertion(+), 1 deletion(-) | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
22 | 10 | ||
23 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
24 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/tlb_helper.c | 13 | --- a/target/arm/cpu.h |
26 | +++ b/target/arm/tlb_helper.c | 14 | +++ b/target/arm/cpu.h |
27 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
28 | syn = syn_data_abort_with_iss(same_el, | 16 | uint32_t ctrl; |
29 | 0, 0, 0, 0, 0, | 17 | } sau; |
30 | ea, 0, s1ptw, is_write, fsc, | 18 | |
31 | - false); | 19 | - void *nvic; |
32 | + true); | 20 | #if !defined(CONFIG_USER_ONLY) |
33 | /* Merge the runtime syndrome with the template syndrome. */ | 21 | + void *nvic; |
34 | syn |= template_syn; | 22 | const struct arm_boot_info *boot_info; |
35 | } | 23 | /* Store GICv3CPUState to access from this struct */ |
24 | void *gicv3state; | ||
36 | -- | 25 | -- |
37 | 2.20.1 | 26 | 2.34.1 |
38 | 27 | ||
39 | 28 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | |
2 | |||
3 | There is no point in using a void pointer to access the NVIC. | ||
4 | Use the real type to avoid casting it while debugging. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230206223502.25122-11-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- | ||
12 | hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- | ||
13 | target/arm/cpu.c | 1 + | ||
14 | target/arm/m_helper.c | 2 +- | ||
15 | 4 files changed, 39 insertions(+), 48 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags { | ||
22 | |||
23 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | ||
24 | |||
25 | +typedef struct NVICState NVICState; | ||
26 | + | ||
27 | typedef struct CPUArchState { | ||
28 | /* Regs for current mode. */ | ||
29 | uint32_t regs[16]; | ||
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
31 | } sau; | ||
32 | |||
33 | #if !defined(CONFIG_USER_ONLY) | ||
34 | - void *nvic; | ||
35 | + NVICState *nvic; | ||
36 | const struct arm_boot_info *boot_info; | ||
37 | /* Store GICv3CPUState to access from this struct */ | ||
38 | void *gicv3state; | ||
39 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
40 | |||
41 | /* Interface between CPU and Interrupt controller. */ | ||
42 | #ifndef CONFIG_USER_ONLY | ||
43 | -bool armv7m_nvic_can_take_pending_exception(void *opaque); | ||
44 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
45 | #else | ||
46 | -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
47 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
48 | { | ||
49 | return true; | ||
50 | } | ||
51 | #endif | ||
52 | /** | ||
53 | * armv7m_nvic_set_pending: mark the specified exception as pending | ||
54 | - * @opaque: the NVIC | ||
55 | + * @s: the NVIC | ||
56 | * @irq: the exception number to mark pending | ||
57 | * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | * version of a banked exception, true for the secure version of a banked | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
60 | * if @secure is true and @irq does not specify one of the fixed set | ||
61 | * of architecturally banked exceptions. | ||
62 | */ | ||
63 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
64 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
65 | /** | ||
66 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
67 | - * @opaque: the NVIC | ||
68 | + * @s: the NVIC | ||
69 | * @irq: the exception number to mark pending | ||
70 | * @secure: false for non-banked exceptions or for the nonsecure | ||
71 | * version of a banked exception, true for the secure version of a banked | ||
72 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
73 | * exceptions (exceptions generated in the course of trying to take | ||
74 | * a different exception). | ||
75 | */ | ||
76 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
77 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
78 | /** | ||
79 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
80 | - * @opaque: the NVIC | ||
81 | + * @s: the NVIC | ||
82 | * @irq: the exception number to mark pending | ||
83 | * @secure: false for non-banked exceptions or for the nonsecure | ||
84 | * version of a banked exception, true for the secure version of a banked | ||
85 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
86 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
87 | * generated in the course of lazy stacking of FP registers. | ||
88 | */ | ||
89 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
90 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
91 | /** | ||
92 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
93 | * exception, and whether it targets Secure state | ||
94 | - * @opaque: the NVIC | ||
95 | + * @s: the NVIC | ||
96 | * @pirq: set to pending exception number | ||
97 | * @ptargets_secure: set to whether pending exception targets Secure | ||
98 | * | ||
99 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
100 | * to true if the current highest priority pending exception should | ||
101 | * be taken to Secure state, false for NS. | ||
102 | */ | ||
103 | -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | ||
104 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
105 | bool *ptargets_secure); | ||
106 | /** | ||
107 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
108 | - * @opaque: the NVIC | ||
109 | + * @s: the NVIC | ||
110 | * | ||
111 | * Move the current highest priority pending exception from the pending | ||
112 | * state to the active state, and update v7m.exception to indicate that | ||
113 | * it is the exception currently being handled. | ||
114 | */ | ||
115 | -void armv7m_nvic_acknowledge_irq(void *opaque); | ||
116 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
117 | /** | ||
118 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
119 | - * @opaque: the NVIC | ||
120 | + * @s: the NVIC | ||
121 | * @irq: the exception number to complete | ||
122 | * @secure: true if this exception was secure | ||
123 | * | ||
124 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
125 | * 0 if there is still an irq active after this one was completed | ||
126 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
127 | */ | ||
128 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
129 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
130 | /** | ||
131 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
132 | - * @opaque: the NVIC | ||
133 | + * @s: the NVIC | ||
134 | * @irq: the exception number to mark pending | ||
135 | * @secure: false for non-banked exceptions or for the nonsecure | ||
136 | * version of a banked exception, true for the secure version of a banked | ||
137 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
138 | * interrupt the current execution priority. This controls whether the | ||
139 | * RDY bit for it in the FPCCR is set. | ||
140 | */ | ||
141 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | ||
142 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
143 | /** | ||
144 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
145 | - * @opaque: the NVIC | ||
146 | + * @s: the NVIC | ||
147 | * | ||
148 | * Returns: the raw execution priority as defined by the v8M architecture. | ||
149 | * This is the execution priority minus the effects of AIRCR.PRIS, | ||
150 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
151 | * (v8M ARM ARM I_PKLD.) | ||
152 | */ | ||
153 | -int armv7m_nvic_raw_execution_priority(void *opaque); | ||
154 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
155 | /** | ||
156 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
157 | * priority is negative for the specified security state. | ||
158 | - * @opaque: the NVIC | ||
159 | + * @s: the NVIC | ||
160 | * @secure: the security state to test | ||
161 | * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
162 | */ | ||
163 | #ifndef CONFIG_USER_ONLY | ||
164 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | ||
165 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
166 | #else | ||
167 | -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
168 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
169 | { | ||
170 | return false; | ||
171 | } | ||
172 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
173 | index XXXXXXX..XXXXXXX 100644 | ||
174 | --- a/hw/intc/armv7m_nvic.c | ||
175 | +++ b/hw/intc/armv7m_nvic.c | ||
176 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
177 | return MIN(running, s->exception_prio); | ||
178 | } | ||
179 | |||
180 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
181 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
182 | { | ||
183 | /* Return true if the requested execution priority is negative | ||
184 | * for the specified security state, ie that security state | ||
185 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
186 | * mean we don't allow FAULTMASK_NS to actually make the execution | ||
187 | * priority negative). Compare pseudocode IsReqExcPriNeg(). | ||
188 | */ | ||
189 | - NVICState *s = opaque; | ||
190 | - | ||
191 | if (s->cpu->env.v7m.faultmask[secure]) { | ||
192 | return true; | ||
193 | } | ||
194 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
195 | return false; | ||
196 | } | ||
197 | |||
198 | -bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
199 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
200 | { | ||
201 | - NVICState *s = opaque; | ||
202 | - | ||
203 | return nvic_exec_prio(s) > nvic_pending_prio(s); | ||
204 | } | ||
205 | |||
206 | -int armv7m_nvic_raw_execution_priority(void *opaque) | ||
207 | +int armv7m_nvic_raw_execution_priority(NVICState *s) | ||
208 | { | ||
209 | - NVICState *s = opaque; | ||
210 | - | ||
211 | return s->exception_prio; | ||
212 | } | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s) | ||
215 | * if @secure is true and @irq does not specify one of the fixed set | ||
216 | * of architecturally banked exceptions. | ||
217 | */ | ||
218 | -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | ||
219 | +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) | ||
220 | { | ||
221 | - NVICState *s = (NVICState *)opaque; | ||
222 | VecInfo *vec; | ||
223 | |||
224 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
225 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, | ||
226 | } | ||
227 | } | ||
228 | |||
229 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) | ||
230 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) | ||
231 | { | ||
232 | - do_armv7m_nvic_set_pending(opaque, irq, secure, false); | ||
233 | + do_armv7m_nvic_set_pending(s, irq, secure, false); | ||
234 | } | ||
235 | |||
236 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | ||
237 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) | ||
238 | { | ||
239 | - do_armv7m_nvic_set_pending(opaque, irq, secure, true); | ||
240 | + do_armv7m_nvic_set_pending(s, irq, secure, true); | ||
241 | } | ||
242 | |||
243 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
244 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
245 | { | ||
246 | /* | ||
247 | * Pend an exception during lazy FP stacking. This differs | ||
248 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
249 | * whether we should escalate depends on the saved context | ||
250 | * in the FPCCR register, not on the current state of the CPU/NVIC. | ||
251 | */ | ||
252 | - NVICState *s = (NVICState *)opaque; | ||
253 | bool banked = exc_is_banked(irq); | ||
254 | VecInfo *vec; | ||
255 | bool targets_secure; | ||
256 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
257 | } | ||
258 | |||
259 | /* Make pending IRQ active. */ | ||
260 | -void armv7m_nvic_acknowledge_irq(void *opaque) | ||
261 | +void armv7m_nvic_acknowledge_irq(NVICState *s) | ||
262 | { | ||
263 | - NVICState *s = (NVICState *)opaque; | ||
264 | CPUARMState *env = &s->cpu->env; | ||
265 | const int pending = s->vectpending; | ||
266 | const int running = nvic_exec_prio(s); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s) | ||
268 | exc_targets_secure(s, s->vectpending); | ||
269 | } | ||
270 | |||
271 | -void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
272 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, | ||
273 | int *pirq, bool *ptargets_secure) | ||
274 | { | ||
275 | - NVICState *s = (NVICState *)opaque; | ||
276 | const int pending = s->vectpending; | ||
277 | bool targets_secure; | ||
278 | |||
279 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
280 | *pirq = pending; | ||
281 | } | ||
282 | |||
283 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
284 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) | ||
285 | { | ||
286 | - NVICState *s = (NVICState *)opaque; | ||
287 | VecInfo *vec = NULL; | ||
288 | int ret = 0; | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
295 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) | ||
296 | { | ||
297 | /* | ||
298 | * Return whether an exception is "ready", i.e. it is enabled and is | ||
299 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
300 | * for non-banked exceptions secure is always false; for banked exceptions | ||
301 | * it indicates which of the exceptions is required. | ||
302 | */ | ||
303 | - NVICState *s = (NVICState *)opaque; | ||
304 | bool banked = exc_is_banked(irq); | ||
305 | VecInfo *vec; | ||
306 | int running = nvic_exec_prio(s); | ||
307 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
308 | index XXXXXXX..XXXXXXX 100644 | ||
309 | --- a/target/arm/cpu.c | ||
310 | +++ b/target/arm/cpu.c | ||
311 | @@ -XXX,XX +XXX,XX @@ | ||
312 | #if !defined(CONFIG_USER_ONLY) | ||
313 | #include "hw/loader.h" | ||
314 | #include "hw/boards.h" | ||
315 | +#include "hw/intc/armv7m_nvic.h" | ||
316 | #endif | ||
317 | #include "sysemu/tcg.h" | ||
318 | #include "sysemu/qtest.h" | ||
319 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
320 | index XXXXXXX..XXXXXXX 100644 | ||
321 | --- a/target/arm/m_helper.c | ||
322 | +++ b/target/arm/m_helper.c | ||
323 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, | ||
324 | * that we will need later in order to do lazy FP reg stacking. | ||
325 | */ | ||
326 | bool is_secure = env->v7m.secure; | ||
327 | - void *nvic = env->nvic; | ||
328 | + NVICState *nvic = env->nvic; | ||
329 | /* | ||
330 | * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits | ||
331 | * are banked and we want to update the bit in the bank for the | ||
332 | -- | ||
333 | 2.34.1 | ||
334 | |||
335 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | |
2 | |||
3 | While dozens of files include "cpu.h", only 3 files require | ||
4 | these NVIC helper declarations. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20230206223502.25122-12-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ | ||
12 | target/arm/cpu.h | 123 ---------------------------------- | ||
13 | target/arm/cpu.c | 4 +- | ||
14 | target/arm/cpu_tcg.c | 3 + | ||
15 | target/arm/m_helper.c | 3 + | ||
16 | 5 files changed, 132 insertions(+), 124 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/intc/armv7m_nvic.h | ||
21 | +++ b/include/hw/intc/armv7m_nvic.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct NVICState { | ||
23 | qemu_irq sysresetreq; | ||
24 | }; | ||
25 | |||
26 | +/* Interface between CPU and Interrupt controller. */ | ||
27 | +/** | ||
28 | + * armv7m_nvic_set_pending: mark the specified exception as pending | ||
29 | + * @s: the NVIC | ||
30 | + * @irq: the exception number to mark pending | ||
31 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
32 | + * version of a banked exception, true for the secure version of a banked | ||
33 | + * exception. | ||
34 | + * | ||
35 | + * Marks the specified exception as pending. Note that we will assert() | ||
36 | + * if @secure is true and @irq does not specify one of the fixed set | ||
37 | + * of architecturally banked exceptions. | ||
38 | + */ | ||
39 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
40 | +/** | ||
41 | + * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
42 | + * @s: the NVIC | ||
43 | + * @irq: the exception number to mark pending | ||
44 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
45 | + * version of a banked exception, true for the secure version of a banked | ||
46 | + * exception. | ||
47 | + * | ||
48 | + * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
49 | + * exceptions (exceptions generated in the course of trying to take | ||
50 | + * a different exception). | ||
51 | + */ | ||
52 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
53 | +/** | ||
54 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
55 | + * @s: the NVIC | ||
56 | + * @irq: the exception number to mark pending | ||
57 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | + * version of a banked exception, true for the secure version of a banked | ||
59 | + * exception. | ||
60 | + * | ||
61 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
62 | + * generated in the course of lazy stacking of FP registers. | ||
63 | + */ | ||
64 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
65 | +/** | ||
66 | + * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
67 | + * exception, and whether it targets Secure state | ||
68 | + * @s: the NVIC | ||
69 | + * @pirq: set to pending exception number | ||
70 | + * @ptargets_secure: set to whether pending exception targets Secure | ||
71 | + * | ||
72 | + * This function writes the number of the highest priority pending | ||
73 | + * exception (the one which would be made active by | ||
74 | + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
75 | + * to true if the current highest priority pending exception should | ||
76 | + * be taken to Secure state, false for NS. | ||
77 | + */ | ||
78 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
79 | + bool *ptargets_secure); | ||
80 | +/** | ||
81 | + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
82 | + * @s: the NVIC | ||
83 | + * | ||
84 | + * Move the current highest priority pending exception from the pending | ||
85 | + * state to the active state, and update v7m.exception to indicate that | ||
86 | + * it is the exception currently being handled. | ||
87 | + */ | ||
88 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
89 | +/** | ||
90 | + * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
91 | + * @s: the NVIC | ||
92 | + * @irq: the exception number to complete | ||
93 | + * @secure: true if this exception was secure | ||
94 | + * | ||
95 | + * Returns: -1 if the irq was not active | ||
96 | + * 1 if completing this irq brought us back to base (no active irqs) | ||
97 | + * 0 if there is still an irq active after this one was completed | ||
98 | + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
99 | + */ | ||
100 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
101 | +/** | ||
102 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
103 | + * @s: the NVIC | ||
104 | + * @irq: the exception number to mark pending | ||
105 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
106 | + * version of a banked exception, true for the secure version of a banked | ||
107 | + * exception. | ||
108 | + * | ||
109 | + * Return whether an exception is "ready", i.e. whether the exception is | ||
110 | + * enabled and is configured at a priority which would allow it to | ||
111 | + * interrupt the current execution priority. This controls whether the | ||
112 | + * RDY bit for it in the FPCCR is set. | ||
113 | + */ | ||
114 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
115 | +/** | ||
116 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
117 | + * @s: the NVIC | ||
118 | + * | ||
119 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
120 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
121 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
122 | + * (v8M ARM ARM I_PKLD.) | ||
123 | + */ | ||
124 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
125 | +/** | ||
126 | + * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
127 | + * priority is negative for the specified security state. | ||
128 | + * @s: the NVIC | ||
129 | + * @secure: the security state to test | ||
130 | + * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
131 | + */ | ||
132 | +#ifndef CONFIG_USER_ONLY | ||
133 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
134 | +#else | ||
135 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
136 | +{ | ||
137 | + return false; | ||
138 | +} | ||
139 | +#endif | ||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
142 | +#else | ||
143 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
144 | +{ | ||
145 | + return true; | ||
146 | +} | ||
147 | +#endif | ||
148 | + | ||
149 | #endif | ||
150 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/cpu.h | ||
153 | +++ b/target/arm/cpu.h | ||
154 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
155 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
156 | uint32_t cur_el, bool secure); | ||
157 | |||
158 | -/* Interface between CPU and Interrupt controller. */ | ||
159 | -#ifndef CONFIG_USER_ONLY | ||
160 | -bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
161 | -#else | ||
162 | -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
163 | -{ | ||
164 | - return true; | ||
165 | -} | ||
166 | -#endif | ||
167 | -/** | ||
168 | - * armv7m_nvic_set_pending: mark the specified exception as pending | ||
169 | - * @s: the NVIC | ||
170 | - * @irq: the exception number to mark pending | ||
171 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
172 | - * version of a banked exception, true for the secure version of a banked | ||
173 | - * exception. | ||
174 | - * | ||
175 | - * Marks the specified exception as pending. Note that we will assert() | ||
176 | - * if @secure is true and @irq does not specify one of the fixed set | ||
177 | - * of architecturally banked exceptions. | ||
178 | - */ | ||
179 | -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
180 | -/** | ||
181 | - * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
182 | - * @s: the NVIC | ||
183 | - * @irq: the exception number to mark pending | ||
184 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
185 | - * version of a banked exception, true for the secure version of a banked | ||
186 | - * exception. | ||
187 | - * | ||
188 | - * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
189 | - * exceptions (exceptions generated in the course of trying to take | ||
190 | - * a different exception). | ||
191 | - */ | ||
192 | -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
193 | -/** | ||
194 | - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
195 | - * @s: the NVIC | ||
196 | - * @irq: the exception number to mark pending | ||
197 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
198 | - * version of a banked exception, true for the secure version of a banked | ||
199 | - * exception. | ||
200 | - * | ||
201 | - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
202 | - * generated in the course of lazy stacking of FP registers. | ||
203 | - */ | ||
204 | -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
205 | -/** | ||
206 | - * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
207 | - * exception, and whether it targets Secure state | ||
208 | - * @s: the NVIC | ||
209 | - * @pirq: set to pending exception number | ||
210 | - * @ptargets_secure: set to whether pending exception targets Secure | ||
211 | - * | ||
212 | - * This function writes the number of the highest priority pending | ||
213 | - * exception (the one which would be made active by | ||
214 | - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
215 | - * to true if the current highest priority pending exception should | ||
216 | - * be taken to Secure state, false for NS. | ||
217 | - */ | ||
218 | -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
219 | - bool *ptargets_secure); | ||
220 | -/** | ||
221 | - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
222 | - * @s: the NVIC | ||
223 | - * | ||
224 | - * Move the current highest priority pending exception from the pending | ||
225 | - * state to the active state, and update v7m.exception to indicate that | ||
226 | - * it is the exception currently being handled. | ||
227 | - */ | ||
228 | -void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
229 | -/** | ||
230 | - * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
231 | - * @s: the NVIC | ||
232 | - * @irq: the exception number to complete | ||
233 | - * @secure: true if this exception was secure | ||
234 | - * | ||
235 | - * Returns: -1 if the irq was not active | ||
236 | - * 1 if completing this irq brought us back to base (no active irqs) | ||
237 | - * 0 if there is still an irq active after this one was completed | ||
238 | - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
239 | - */ | ||
240 | -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
241 | -/** | ||
242 | - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
243 | - * @s: the NVIC | ||
244 | - * @irq: the exception number to mark pending | ||
245 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
246 | - * version of a banked exception, true for the secure version of a banked | ||
247 | - * exception. | ||
248 | - * | ||
249 | - * Return whether an exception is "ready", i.e. whether the exception is | ||
250 | - * enabled and is configured at a priority which would allow it to | ||
251 | - * interrupt the current execution priority. This controls whether the | ||
252 | - * RDY bit for it in the FPCCR is set. | ||
253 | - */ | ||
254 | -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
255 | -/** | ||
256 | - * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
257 | - * @s: the NVIC | ||
258 | - * | ||
259 | - * Returns: the raw execution priority as defined by the v8M architecture. | ||
260 | - * This is the execution priority minus the effects of AIRCR.PRIS, | ||
261 | - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
262 | - * (v8M ARM ARM I_PKLD.) | ||
263 | - */ | ||
264 | -int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
265 | -/** | ||
266 | - * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
267 | - * priority is negative for the specified security state. | ||
268 | - * @s: the NVIC | ||
269 | - * @secure: the security state to test | ||
270 | - * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
271 | - */ | ||
272 | -#ifndef CONFIG_USER_ONLY | ||
273 | -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
274 | -#else | ||
275 | -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
276 | -{ | ||
277 | - return false; | ||
278 | -} | ||
279 | -#endif | ||
280 | - | ||
281 | /* Interface for defining coprocessor registers. | ||
282 | * Registers are defined in tables of arm_cp_reginfo structs | ||
283 | * which are passed to define_arm_cp_regs(). | ||
284 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/target/arm/cpu.c | ||
287 | +++ b/target/arm/cpu.c | ||
288 | @@ -XXX,XX +XXX,XX @@ | ||
289 | #if !defined(CONFIG_USER_ONLY) | ||
290 | #include "hw/loader.h" | ||
291 | #include "hw/boards.h" | ||
292 | +#ifdef CONFIG_TCG | ||
293 | #include "hw/intc/armv7m_nvic.h" | ||
294 | -#endif | ||
295 | +#endif /* CONFIG_TCG */ | ||
296 | +#endif /* !CONFIG_USER_ONLY */ | ||
297 | #include "sysemu/tcg.h" | ||
298 | #include "sysemu/qtest.h" | ||
299 | #include "sysemu/hw_accel.h" | ||
300 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
301 | index XXXXXXX..XXXXXXX 100644 | ||
302 | --- a/target/arm/cpu_tcg.c | ||
303 | +++ b/target/arm/cpu_tcg.c | ||
304 | @@ -XXX,XX +XXX,XX @@ | ||
305 | #include "hw/boards.h" | ||
306 | #endif | ||
307 | #include "cpregs.h" | ||
308 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) | ||
309 | +#include "hw/intc/armv7m_nvic.h" | ||
310 | +#endif | ||
311 | |||
312 | |||
313 | /* Share AArch32 -cpu max features with AArch64. */ | ||
314 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/m_helper.c | ||
317 | +++ b/target/arm/m_helper.c | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | #include "exec/cpu_ldst.h" | ||
320 | #include "semihosting/common-semi.h" | ||
321 | #endif | ||
322 | +#if !defined(CONFIG_USER_ONLY) | ||
323 | +#include "hw/intc/armv7m_nvic.h" | ||
324 | +#endif | ||
325 | |||
326 | static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
327 | uint32_t reg, uint32_t val) | ||
328 | -- | ||
329 | 2.34.1 | ||
330 | |||
331 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Alex Bennée <alex.bennee@linaro.org> | |
2 | |||
3 | The two TCG tests for GICv2 and GICv3 are very heavy weight distros | ||
4 | that take a long time to boot up, especially for an --enable-debug | ||
5 | build. The total code coverage they give is: | ||
6 | |||
7 | Overall coverage rate: | ||
8 | lines......: 11.2% (59584 of 530123 lines) | ||
9 | functions..: 15.0% (7436 of 49443 functions) | ||
10 | branches...: 6.3% (19273 of 303933 branches) | ||
11 | |||
12 | We already get pretty close to that with the machine_aarch64_virt | ||
13 | tests which only does one full boot (~120s vs ~600s) of alpine. We | ||
14 | expand the kernel+initrd boot (~8s) to test both GICs and also add an | ||
15 | RNG device and a block device to generate a few IRQs and exercise the | ||
16 | storage layer. With that we get to a coverage of: | ||
17 | |||
18 | Overall coverage rate: | ||
19 | lines......: 11.0% (58121 of 530123 lines) | ||
20 | functions..: 14.9% (7343 of 49443 functions) | ||
21 | branches...: 6.0% (18269 of 303933 branches) | ||
22 | |||
23 | which I feel is close enough given the massive time saving. If we want | ||
24 | to target any more sub-systems we can use lighter weight more directed | ||
25 | tests. | ||
26 | |||
27 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
29 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org | ||
31 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | --- | ||
34 | tests/avocado/boot_linux.py | 48 ++++---------------- | ||
35 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- | ||
36 | 2 files changed, 65 insertions(+), 46 deletions(-) | ||
37 | |||
38 | diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/tests/avocado/boot_linux.py | ||
41 | +++ b/tests/avocado/boot_linux.py | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self): | ||
43 | self.launch_and_wait(set_up_ssh_connection=False) | ||
44 | |||
45 | |||
46 | -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very | ||
47 | -# heavyweight. There are lighter weight distros which we use in the | ||
48 | -# machine_aarch64_virt.py tests. | ||
49 | +# For Aarch64 we only boot KVM tests in CI as booting the current | ||
50 | +# Fedora OS in TCG tests is very heavyweight. There are lighter weight | ||
51 | +# distros which we use in the machine_aarch64_virt.py tests. | ||
52 | class BootLinuxAarch64(LinuxTest): | ||
53 | """ | ||
54 | :avocado: tags=arch:aarch64 | ||
55 | :avocado: tags=machine:virt | ||
56 | - :avocado: tags=machine:gic-version=2 | ||
57 | """ | ||
58 | timeout = 720 | ||
59 | |||
60 | - def add_common_args(self): | ||
61 | - self.vm.add_args('-bios', | ||
62 | - os.path.join(BUILD_DIR, 'pc-bios', | ||
63 | - 'edk2-aarch64-code.fd')) | ||
64 | - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
65 | - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
66 | - | ||
67 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
68 | - def test_fedora_cloud_tcg_gicv2(self): | ||
69 | - """ | ||
70 | - :avocado: tags=accel:tcg | ||
71 | - :avocado: tags=cpu:max | ||
72 | - :avocado: tags=device:gicv2 | ||
73 | - """ | ||
74 | - self.require_accelerator("tcg") | ||
75 | - self.vm.add_args("-accel", "tcg") | ||
76 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
77 | - self.vm.add_args("-machine", "virt,gic-version=2") | ||
78 | - self.add_common_args() | ||
79 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
80 | - | ||
81 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
82 | - def test_fedora_cloud_tcg_gicv3(self): | ||
83 | - """ | ||
84 | - :avocado: tags=accel:tcg | ||
85 | - :avocado: tags=cpu:max | ||
86 | - :avocado: tags=device:gicv3 | ||
87 | - """ | ||
88 | - self.require_accelerator("tcg") | ||
89 | - self.vm.add_args("-accel", "tcg") | ||
90 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
91 | - self.vm.add_args("-machine", "virt,gic-version=3") | ||
92 | - self.add_common_args() | ||
93 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
94 | - | ||
95 | def test_virt_kvm(self): | ||
96 | """ | ||
97 | :avocado: tags=accel:kvm | ||
98 | @@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self): | ||
99 | self.require_accelerator("kvm") | ||
100 | self.vm.add_args("-accel", "kvm") | ||
101 | self.vm.add_args("-machine", "virt,gic-version=host") | ||
102 | - self.add_common_args() | ||
103 | + self.vm.add_args('-bios', | ||
104 | + os.path.join(BUILD_DIR, 'pc-bios', | ||
105 | + 'edk2-aarch64-code.fd')) | ||
106 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
107 | + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
108 | self.launch_and_wait(set_up_ssh_connection=False) | ||
109 | |||
110 | |||
111 | diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/tests/avocado/machine_aarch64_virt.py | ||
114 | +++ b/tests/avocado/machine_aarch64_virt.py | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | |||
117 | import time | ||
118 | import os | ||
119 | +import logging | ||
120 | |||
121 | from avocado_qemu import QemuSystemTest | ||
122 | from avocado_qemu import wait_for_console_pattern | ||
123 | from avocado_qemu import exec_command | ||
124 | from avocado_qemu import BUILD_DIR | ||
125 | +from avocado.utils import process | ||
126 | +from avocado.utils.path import find_command | ||
127 | |||
128 | class Aarch64VirtMachine(QemuSystemTest): | ||
129 | KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' | ||
130 | @@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self): | ||
131 | self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') | ||
132 | |||
133 | |||
134 | - def test_aarch64_virt(self): | ||
135 | + def common_aarch64_virt(self, machine): | ||
136 | """ | ||
137 | - :avocado: tags=arch:aarch64 | ||
138 | - :avocado: tags=machine:virt | ||
139 | - :avocado: tags=accel:tcg | ||
140 | - :avocado: tags=cpu:max | ||
141 | + Common code to launch basic virt machine with kernel+initrd | ||
142 | + and a scratch disk. | ||
143 | """ | ||
144 | + logger = logging.getLogger('aarch64_virt') | ||
145 | + | ||
146 | kernel_url = ('https://fileserver.linaro.org/s/' | ||
147 | 'z6B2ARM7DQT3HWN/download') | ||
148 | - | ||
149 | kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' | ||
150 | kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self): | ||
153 | 'console=ttyAMA0') | ||
154 | self.require_accelerator("tcg") | ||
155 | self.vm.add_args('-cpu', 'max,pauth-impdef=on', | ||
156 | + '-machine', machine, | ||
157 | '-accel', 'tcg', | ||
158 | '-kernel', kernel_path, | ||
159 | '-append', kernel_command_line) | ||
160 | + | ||
161 | + # A RNG offers an easy way to generate a few IRQs | ||
162 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
163 | + self.vm.add_args('-object', | ||
164 | + 'rng-random,id=rng0,filename=/dev/urandom') | ||
165 | + | ||
166 | + # Also add a scratch block device | ||
167 | + logger.info('creating scratch qcow2 image') | ||
168 | + image_path = os.path.join(self.workdir, 'scratch.qcow2') | ||
169 | + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') | ||
170 | + if not os.path.exists(qemu_img): | ||
171 | + qemu_img = find_command('qemu-img', False) | ||
172 | + if qemu_img is False: | ||
173 | + self.cancel('Could not find "qemu-img", which is required to ' | ||
174 | + 'create the temporary qcow2 image') | ||
175 | + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) | ||
176 | + process.run(cmd) | ||
177 | + | ||
178 | + # Add the device | ||
179 | + self.vm.add_args('-blockdev', | ||
180 | + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") | ||
181 | + self.vm.add_args('-device', | ||
182 | + 'virtio-blk-device,drive=scratch') | ||
183 | + | ||
184 | self.vm.launch() | ||
185 | self.wait_for_console_pattern('Welcome to Buildroot') | ||
186 | time.sleep(0.1) | ||
187 | exec_command(self, 'root') | ||
188 | time.sleep(0.1) | ||
189 | + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') | ||
190 | + time.sleep(0.1) | ||
191 | + exec_command(self, 'md5sum /dev/vda') | ||
192 | + time.sleep(0.1) | ||
193 | + exec_command(self, 'cat /proc/interrupts') | ||
194 | + time.sleep(0.1) | ||
195 | exec_command(self, 'cat /proc/self/maps') | ||
196 | time.sleep(0.1) | ||
197 | + | ||
198 | + def test_aarch64_virt_gicv3(self): | ||
199 | + """ | ||
200 | + :avocado: tags=arch:aarch64 | ||
201 | + :avocado: tags=machine:virt | ||
202 | + :avocado: tags=accel:tcg | ||
203 | + :avocado: tags=cpu:max | ||
204 | + """ | ||
205 | + self.common_aarch64_virt("virt,gic_version=3") | ||
206 | + | ||
207 | + def test_aarch64_virt_gicv2(self): | ||
208 | + """ | ||
209 | + :avocado: tags=arch:aarch64 | ||
210 | + :avocado: tags=machine:virt | ||
211 | + :avocado: tags=accel:tcg | ||
212 | + :avocado: tags=cpu:max | ||
213 | + """ | ||
214 | + self.common_aarch64_virt("virt,gic-version=2") | ||
215 | -- | ||
216 | 2.34.1 | ||
217 | |||
218 | diff view generated by jsdifflib |
1 | From: Martin Kaiser <martin@kaiser.cx> | 1 | From: Mostafa Saleh <smostafa@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Add an emulation for the RNGC random number generator and the compatible | 3 | GBPA register can be used to globally abort all |
4 | RNGB variant. These peripherals are included (at least) in imx25 and | 4 | transactions. |
5 | imx35 chipsets. | ||
6 | 5 | ||
7 | The emulation supports the initial self test, reseeding the prng and | 6 | It is described in the SMMU manual in "6.3.14 SMMU_GBPA". |
8 | reading random numbers. | 7 | ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to |
8 | be zero(Do not abort incoming transactions). | ||
9 | 9 | ||
10 | Signed-off-by: Martin Kaiser <martin@kaiser.cx> | 10 | Other fields have default values of Use Incoming. |
11 | |||
12 | If UPDATE is not set, the write is ignored. This is the only permitted | ||
13 | behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) | ||
14 | |||
15 | As this patch adds a new state to the SMMU (GBPA), it is added | ||
16 | in a new subsection for forward migration compatibility. | ||
17 | GBPA is only migrated if its value is different from the reset value. | ||
18 | It does this to be backward migration compatible if SW didn't write | ||
19 | the register. | ||
20 | |||
21 | Signed-off-by: Mostafa Saleh <smostafa@google.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Message-id: 20230214094009.2445653-1-smostafa@google.com | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 27 | --- |
14 | hw/misc/Makefile.objs | 1 + | 28 | hw/arm/smmuv3-internal.h | 7 +++++++ |
15 | include/hw/arm/fsl-imx25.h | 5 + | 29 | include/hw/arm/smmuv3.h | 1 + |
16 | include/hw/misc/imx_rngc.h | 35 +++++ | 30 | hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- |
17 | hw/arm/fsl-imx25.c | 11 ++ | 31 | 3 files changed, 50 insertions(+), 1 deletion(-) |
18 | hw/misc/imx_rngc.c | 278 +++++++++++++++++++++++++++++++++++++ | ||
19 | 5 files changed, 330 insertions(+) | ||
20 | create mode 100644 include/hw/misc/imx_rngc.h | ||
21 | create mode 100644 hw/misc/imx_rngc.c | ||
22 | 32 | ||
23 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 33 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h |
24 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/misc/Makefile.objs | 35 | --- a/hw/arm/smmuv3-internal.h |
26 | +++ b/hw/misc/Makefile.objs | 36 | +++ b/hw/arm/smmuv3-internal.h |
27 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o | 37 | @@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24) |
28 | common-obj-$(CONFIG_IMX) += imx2_wdt.o | 38 | REG32(CR1, 0x28) |
29 | common-obj-$(CONFIG_IMX) += imx7_snvs.o | 39 | REG32(CR2, 0x2c) |
30 | common-obj-$(CONFIG_IMX) += imx7_gpr.o | 40 | REG32(STATUSR, 0x40) |
31 | +common-obj-$(CONFIG_IMX) += imx_rngc.o | 41 | +REG32(GBPA, 0x44) |
32 | common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o | 42 | + FIELD(GBPA, ABORT, 20, 1) |
33 | common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o | 43 | + FIELD(GBPA, UPDATE, 31, 1) |
34 | common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o | 44 | + |
35 | diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h | 45 | +/* Use incoming. */ |
46 | +#define SMMU_GBPA_RESET_VAL 0x1000 | ||
47 | + | ||
48 | REG32(IRQ_CTRL, 0x50) | ||
49 | FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) | ||
50 | FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) | ||
51 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/include/hw/arm/fsl-imx25.h | 53 | --- a/include/hw/arm/smmuv3.h |
38 | +++ b/include/hw/arm/fsl-imx25.h | 54 | +++ b/include/hw/arm/smmuv3.h |
39 | @@ -XXX,XX +XXX,XX @@ | 55 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { |
40 | #include "hw/timer/imx_gpt.h" | 56 | uint32_t cr[3]; |
41 | #include "hw/timer/imx_epit.h" | 57 | uint32_t cr0ack; |
42 | #include "hw/net/imx_fec.h" | 58 | uint32_t statusr; |
43 | +#include "hw/misc/imx_rngc.h" | 59 | + uint32_t gbpa; |
44 | #include "hw/i2c/imx_i2c.h" | 60 | uint32_t irq_ctrl; |
45 | #include "hw/gpio/imx_gpio.h" | 61 | uint32_t gerror; |
46 | #include "exec/memory.h" | 62 | uint32_t gerrorn; |
47 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | 63 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
48 | IMXGPTState gpt[FSL_IMX25_NUM_GPTS]; | 64 | index XXXXXXX..XXXXXXX 100644 |
49 | IMXEPITState epit[FSL_IMX25_NUM_EPITS]; | 65 | --- a/hw/arm/smmuv3.c |
50 | IMXFECState fec; | 66 | +++ b/hw/arm/smmuv3.c |
51 | + IMXRNGCState rngc; | 67 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) |
52 | IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; | 68 | s->gerror = 0; |
53 | IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; | 69 | s->gerrorn = 0; |
54 | MemoryRegion rom[2]; | 70 | s->statusr = 0; |
55 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | 71 | + s->gbpa = SMMU_GBPA_RESET_VAL; |
56 | #define FSL_IMX25_GPIO4_SIZE 0x4000 | 72 | } |
57 | #define FSL_IMX25_GPIO3_ADDR 0x53FA4000 | 73 | |
58 | #define FSL_IMX25_GPIO3_SIZE 0x4000 | 74 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, |
59 | +#define FSL_IMX25_RNGC_ADDR 0x53FB0000 | 75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, |
60 | +#define FSL_IMX25_RNGC_SIZE 0x4000 | 76 | qemu_mutex_lock(&s->mutex); |
61 | #define FSL_IMX25_GPIO1_ADDR 0x53FCC000 | 77 | |
62 | #define FSL_IMX25_GPIO1_SIZE 0x4000 | 78 | if (!smmu_enabled(s)) { |
63 | #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 | 79 | - status = SMMU_TRANS_DISABLE; |
64 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State { | 80 | + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { |
65 | #define FSL_IMX25_EPIT1_IRQ 28 | 81 | + status = SMMU_TRANS_ABORT; |
66 | #define FSL_IMX25_EPIT2_IRQ 27 | 82 | + } else { |
67 | #define FSL_IMX25_FEC_IRQ 57 | 83 | + status = SMMU_TRANS_DISABLE; |
68 | +#define FSL_IMX25_RNGC_IRQ 22 | 84 | + } |
69 | #define FSL_IMX25_I2C1_IRQ 3 | 85 | goto epilogue; |
70 | #define FSL_IMX25_I2C2_IRQ 4 | 86 | } |
71 | #define FSL_IMX25_I2C3_IRQ 10 | 87 | |
72 | diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h | 88 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, |
73 | new file mode 100644 | 89 | case A_GERROR_IRQ_CFG2: |
74 | index XXXXXXX..XXXXXXX | 90 | s->gerror_irq_cfg2 = data; |
75 | --- /dev/null | 91 | return MEMTX_OK; |
76 | +++ b/include/hw/misc/imx_rngc.h | 92 | + case A_GBPA: |
77 | @@ -XXX,XX +XXX,XX @@ | 93 | + /* |
78 | +/* | 94 | + * If UPDATE is not set, the write is ignored. This is the only |
79 | + * Freescale i.MX RNGC emulation | 95 | + * permitted behavior in SMMUv3.2 and later. |
80 | + * | 96 | + */ |
81 | + * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx> | 97 | + if (data & R_GBPA_UPDATE_MASK) { |
82 | + * | 98 | + /* Ignore update bit as write is synchronous. */ |
83 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 99 | + s->gbpa = data & ~R_GBPA_UPDATE_MASK; |
84 | + * See the COPYING file in the top-level directory. | 100 | + } |
85 | + */ | 101 | + return MEMTX_OK; |
102 | case A_STRTAB_BASE: /* 64b */ | ||
103 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | ||
104 | return MEMTX_OK; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | ||
106 | case A_STATUSR: | ||
107 | *data = s->statusr; | ||
108 | return MEMTX_OK; | ||
109 | + case A_GBPA: | ||
110 | + *data = s->gbpa; | ||
111 | + return MEMTX_OK; | ||
112 | case A_IRQ_CTRL: | ||
113 | case A_IRQ_CTRL_ACK: | ||
114 | *data = s->irq_ctrl; | ||
115 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = { | ||
116 | }, | ||
117 | }; | ||
118 | |||
119 | +static bool smmuv3_gbpa_needed(void *opaque) | ||
120 | +{ | ||
121 | + SMMUv3State *s = opaque; | ||
86 | + | 122 | + |
87 | +#ifndef IMX_RNGC_H | 123 | + /* Only migrate GBPA if it has different reset value. */ |
88 | +#define IMX_RNGC_H | 124 | + return s->gbpa != SMMU_GBPA_RESET_VAL; |
89 | + | ||
90 | +#include "hw/sysbus.h" | ||
91 | + | ||
92 | +#define TYPE_IMX_RNGC "imx.rngc" | ||
93 | +#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC) | ||
94 | + | ||
95 | +typedef struct IMXRNGCState { | ||
96 | + /*< private >*/ | ||
97 | + SysBusDevice parent_obj; | ||
98 | + | ||
99 | + /*< public >*/ | ||
100 | + MemoryRegion iomem; | ||
101 | + | ||
102 | + uint8_t op_self_test; | ||
103 | + uint8_t op_seed; | ||
104 | + uint8_t mask; | ||
105 | + bool auto_seed; | ||
106 | + | ||
107 | + QEMUBH *self_test_bh; | ||
108 | + QEMUBH *seed_bh; | ||
109 | + qemu_irq irq; | ||
110 | +} IMXRNGCState; | ||
111 | + | ||
112 | +#endif /* IMX_RNGC_H */ | ||
113 | diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c | ||
114 | index XXXXXXX..XXXXXXX 100644 | ||
115 | --- a/hw/arm/fsl-imx25.c | ||
116 | +++ b/hw/arm/fsl-imx25.c | ||
117 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj) | ||
118 | |||
119 | sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC); | ||
120 | |||
121 | + sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc), | ||
122 | + TYPE_IMX_RNGC); | ||
123 | + | ||
124 | for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { | ||
125 | sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), | ||
126 | TYPE_IMX_I2C); | ||
127 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) | ||
128 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, | ||
129 | qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); | ||
130 | |||
131 | + object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err); | ||
132 | + if (err) { | ||
133 | + error_propagate(errp, err); | ||
134 | + return; | ||
135 | + } | ||
136 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); | ||
137 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, | ||
138 | + qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); | ||
139 | |||
140 | /* Initialize all I2C */ | ||
141 | for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { | ||
142 | diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c | ||
143 | new file mode 100644 | ||
144 | index XXXXXXX..XXXXXXX | ||
145 | --- /dev/null | ||
146 | +++ b/hw/misc/imx_rngc.c | ||
147 | @@ -XXX,XX +XXX,XX @@ | ||
148 | +/* | ||
149 | + * Freescale i.MX RNGC emulation | ||
150 | + * | ||
151 | + * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx> | ||
152 | + * | ||
153 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
154 | + * See the COPYING file in the top-level directory. | ||
155 | + * | ||
156 | + * This driver provides the minimum functionality to initialize and seed | ||
157 | + * an rngc and to read random numbers. The rngb that is found in imx25 | ||
158 | + * chipsets is also supported. | ||
159 | + */ | ||
160 | + | ||
161 | +#include "qemu/osdep.h" | ||
162 | +#include "qemu/main-loop.h" | ||
163 | +#include "qemu/module.h" | ||
164 | +#include "qemu/log.h" | ||
165 | +#include "qemu/guest-random.h" | ||
166 | +#include "hw/irq.h" | ||
167 | +#include "hw/misc/imx_rngc.h" | ||
168 | +#include "migration/vmstate.h" | ||
169 | + | ||
170 | +#define RNGC_NAME "i.MX RNGC" | ||
171 | + | ||
172 | +#define RNGC_VER_ID 0x00 | ||
173 | +#define RNGC_COMMAND 0x04 | ||
174 | +#define RNGC_CONTROL 0x08 | ||
175 | +#define RNGC_STATUS 0x0C | ||
176 | +#define RNGC_FIFO 0x14 | ||
177 | + | ||
178 | +/* These version info are reported by the rngb in an imx258 chip. */ | ||
179 | +#define RNG_TYPE_RNGB 0x1 | ||
180 | +#define V_MAJ 0x2 | ||
181 | +#define V_MIN 0x40 | ||
182 | + | ||
183 | +#define RNGC_CMD_BIT_SW_RST 0x40 | ||
184 | +#define RNGC_CMD_BIT_CLR_ERR 0x20 | ||
185 | +#define RNGC_CMD_BIT_CLR_INT 0x10 | ||
186 | +#define RNGC_CMD_BIT_SEED 0x02 | ||
187 | +#define RNGC_CMD_BIT_SELF_TEST 0x01 | ||
188 | + | ||
189 | +#define RNGC_CTRL_BIT_MASK_ERR 0x40 | ||
190 | +#define RNGC_CTRL_BIT_MASK_DONE 0x20 | ||
191 | +#define RNGC_CTRL_BIT_AUTO_SEED 0x10 | ||
192 | + | ||
193 | +/* the current status for self-test and seed operations */ | ||
194 | +#define OP_IDLE 0 | ||
195 | +#define OP_RUN 1 | ||
196 | +#define OP_DONE 2 | ||
197 | + | ||
198 | +static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size) | ||
199 | +{ | ||
200 | + IMXRNGCState *s = IMX_RNGC(opaque); | ||
201 | + uint64_t val = 0; | ||
202 | + | ||
203 | + switch (offset) { | ||
204 | + case RNGC_VER_ID: | ||
205 | + val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN; | ||
206 | + break; | ||
207 | + | ||
208 | + case RNGC_COMMAND: | ||
209 | + if (s->op_seed == OP_RUN) { | ||
210 | + val |= RNGC_CMD_BIT_SEED; | ||
211 | + } | ||
212 | + if (s->op_self_test == OP_RUN) { | ||
213 | + val |= RNGC_CMD_BIT_SELF_TEST; | ||
214 | + } | ||
215 | + break; | ||
216 | + | ||
217 | + case RNGC_CONTROL: | ||
218 | + /* | ||
219 | + * The CTL_ACC and VERIF_MODE bits are not supported yet. | ||
220 | + * They read as 0. | ||
221 | + */ | ||
222 | + val |= s->mask; | ||
223 | + if (s->auto_seed) { | ||
224 | + val |= RNGC_CTRL_BIT_AUTO_SEED; | ||
225 | + } | ||
226 | + /* | ||
227 | + * We don't have an internal fifo like the real hardware. | ||
228 | + * There's no need for strategy to handle fifo underflows. | ||
229 | + * We return the FIFO_UFLOW_RESPONSE bits as 0. | ||
230 | + */ | ||
231 | + break; | ||
232 | + | ||
233 | + case RNGC_STATUS: | ||
234 | + /* | ||
235 | + * We never report any statistics test or self-test errors or any | ||
236 | + * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0. | ||
237 | + */ | ||
238 | + | ||
239 | + /* | ||
240 | + * We don't have an internal fifo, see above. Therefore, we | ||
241 | + * report back the default fifo size (5 32-bit words) and | ||
242 | + * indicate that our fifo is always full. | ||
243 | + */ | ||
244 | + val |= 5 << 12 | 5 << 8; | ||
245 | + | ||
246 | + /* We always have a new seed available. */ | ||
247 | + val |= 1 << 6; | ||
248 | + | ||
249 | + if (s->op_seed == OP_DONE) { | ||
250 | + val |= 1 << 5; | ||
251 | + } | ||
252 | + if (s->op_self_test == OP_DONE) { | ||
253 | + val |= 1 << 4; | ||
254 | + } | ||
255 | + if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) { | ||
256 | + /* | ||
257 | + * We're busy if self-test is running or if we're | ||
258 | + * seeding the prng. | ||
259 | + */ | ||
260 | + val |= 1 << 1; | ||
261 | + } else { | ||
262 | + /* | ||
263 | + * We're ready to provide secure random numbers whenever | ||
264 | + * we're not busy. | ||
265 | + */ | ||
266 | + val |= 1; | ||
267 | + } | ||
268 | + break; | ||
269 | + | ||
270 | + case RNGC_FIFO: | ||
271 | + qemu_guest_getrandom_nofail(&val, sizeof(val)); | ||
272 | + break; | ||
273 | + } | ||
274 | + | ||
275 | + return val; | ||
276 | +} | 125 | +} |
277 | + | 126 | + |
278 | +static void imx_rngc_do_reset(IMXRNGCState *s) | 127 | +static const VMStateDescription vmstate_gbpa = { |
279 | +{ | 128 | + .name = "smmuv3/gbpa", |
280 | + s->op_self_test = OP_IDLE; | ||
281 | + s->op_seed = OP_IDLE; | ||
282 | + s->mask = 0; | ||
283 | + s->auto_seed = false; | ||
284 | +} | ||
285 | + | ||
286 | +static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value, | ||
287 | + unsigned size) | ||
288 | +{ | ||
289 | + IMXRNGCState *s = IMX_RNGC(opaque); | ||
290 | + | ||
291 | + switch (offset) { | ||
292 | + case RNGC_COMMAND: | ||
293 | + if (value & RNGC_CMD_BIT_SW_RST) { | ||
294 | + imx_rngc_do_reset(s); | ||
295 | + } | ||
296 | + | ||
297 | + /* | ||
298 | + * For now, both CLR_ERR and CLR_INT clear the interrupt. We | ||
299 | + * don't report any errors yet. | ||
300 | + */ | ||
301 | + if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) { | ||
302 | + qemu_irq_lower(s->irq); | ||
303 | + } | ||
304 | + | ||
305 | + if (value & RNGC_CMD_BIT_SEED) { | ||
306 | + s->op_seed = OP_RUN; | ||
307 | + qemu_bh_schedule(s->seed_bh); | ||
308 | + } | ||
309 | + | ||
310 | + if (value & RNGC_CMD_BIT_SELF_TEST) { | ||
311 | + s->op_self_test = OP_RUN; | ||
312 | + qemu_bh_schedule(s->self_test_bh); | ||
313 | + } | ||
314 | + break; | ||
315 | + | ||
316 | + case RNGC_CONTROL: | ||
317 | + /* | ||
318 | + * The CTL_ACC and VERIF_MODE bits are not supported yet. | ||
319 | + * We ignore them if they're set by the caller. | ||
320 | + */ | ||
321 | + | ||
322 | + if (value & RNGC_CTRL_BIT_MASK_ERR) { | ||
323 | + s->mask |= RNGC_CTRL_BIT_MASK_ERR; | ||
324 | + } else { | ||
325 | + s->mask &= ~RNGC_CTRL_BIT_MASK_ERR; | ||
326 | + } | ||
327 | + | ||
328 | + if (value & RNGC_CTRL_BIT_MASK_DONE) { | ||
329 | + s->mask |= RNGC_CTRL_BIT_MASK_DONE; | ||
330 | + } else { | ||
331 | + s->mask &= ~RNGC_CTRL_BIT_MASK_DONE; | ||
332 | + } | ||
333 | + | ||
334 | + if (value & RNGC_CTRL_BIT_AUTO_SEED) { | ||
335 | + s->auto_seed = true; | ||
336 | + } else { | ||
337 | + s->auto_seed = false; | ||
338 | + } | ||
339 | + break; | ||
340 | + } | ||
341 | +} | ||
342 | + | ||
343 | +static const MemoryRegionOps imx_rngc_ops = { | ||
344 | + .read = imx_rngc_read, | ||
345 | + .write = imx_rngc_write, | ||
346 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
347 | +}; | ||
348 | + | ||
349 | +static void imx_rngc_self_test(void *opaque) | ||
350 | +{ | ||
351 | + IMXRNGCState *s = IMX_RNGC(opaque); | ||
352 | + | ||
353 | + s->op_self_test = OP_DONE; | ||
354 | + if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) { | ||
355 | + qemu_irq_raise(s->irq); | ||
356 | + } | ||
357 | +} | ||
358 | + | ||
359 | +static void imx_rngc_seed(void *opaque) | ||
360 | +{ | ||
361 | + IMXRNGCState *s = IMX_RNGC(opaque); | ||
362 | + | ||
363 | + s->op_seed = OP_DONE; | ||
364 | + if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) { | ||
365 | + qemu_irq_raise(s->irq); | ||
366 | + } | ||
367 | +} | ||
368 | + | ||
369 | +static void imx_rngc_realize(DeviceState *dev, Error **errp) | ||
370 | +{ | ||
371 | + IMXRNGCState *s = IMX_RNGC(dev); | ||
372 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
373 | + | ||
374 | + memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s, | ||
375 | + TYPE_IMX_RNGC, 0x1000); | ||
376 | + sysbus_init_mmio(sbd, &s->iomem); | ||
377 | + | ||
378 | + sysbus_init_irq(sbd, &s->irq); | ||
379 | + s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s); | ||
380 | + s->seed_bh = qemu_bh_new(imx_rngc_seed, s); | ||
381 | +} | ||
382 | + | ||
383 | +static void imx_rngc_reset(DeviceState *dev) | ||
384 | +{ | ||
385 | + IMXRNGCState *s = IMX_RNGC(dev); | ||
386 | + | ||
387 | + imx_rngc_do_reset(s); | ||
388 | +} | ||
389 | + | ||
390 | +static const VMStateDescription vmstate_imx_rngc = { | ||
391 | + .name = RNGC_NAME, | ||
392 | + .version_id = 1, | 129 | + .version_id = 1, |
393 | + .minimum_version_id = 1, | 130 | + .minimum_version_id = 1, |
131 | + .needed = smmuv3_gbpa_needed, | ||
394 | + .fields = (VMStateField[]) { | 132 | + .fields = (VMStateField[]) { |
395 | + VMSTATE_UINT8(op_self_test, IMXRNGCState), | 133 | + VMSTATE_UINT32(gbpa, SMMUv3State), |
396 | + VMSTATE_UINT8(op_seed, IMXRNGCState), | ||
397 | + VMSTATE_UINT8(mask, IMXRNGCState), | ||
398 | + VMSTATE_BOOL(auto_seed, IMXRNGCState), | ||
399 | + VMSTATE_END_OF_LIST() | 134 | + VMSTATE_END_OF_LIST() |
400 | + } | 135 | + } |
401 | +}; | 136 | +}; |
402 | + | 137 | + |
403 | +static void imx_rngc_class_init(ObjectClass *klass, void *data) | 138 | static const VMStateDescription vmstate_smmuv3 = { |
404 | +{ | 139 | .name = "smmuv3", |
405 | + DeviceClass *dc = DEVICE_CLASS(klass); | 140 | .version_id = 1, |
406 | + | 141 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = { |
407 | + dc->realize = imx_rngc_realize; | 142 | |
408 | + dc->reset = imx_rngc_reset; | 143 | VMSTATE_END_OF_LIST(), |
409 | + dc->desc = RNGC_NAME, | 144 | }, |
410 | + dc->vmsd = &vmstate_imx_rngc; | 145 | + .subsections = (const VMStateDescription * []) { |
411 | +} | 146 | + &vmstate_gbpa, |
412 | + | 147 | + NULL |
413 | +static const TypeInfo imx_rngc_info = { | 148 | + } |
414 | + .name = TYPE_IMX_RNGC, | 149 | }; |
415 | + .parent = TYPE_SYS_BUS_DEVICE, | 150 | |
416 | + .instance_size = sizeof(IMXRNGCState), | 151 | static void smmuv3_instance_init(Object *obj) |
417 | + .class_init = imx_rngc_class_init, | ||
418 | +}; | ||
419 | + | ||
420 | +static void imx_rngc_register_types(void) | ||
421 | +{ | ||
422 | + type_register_static(&imx_rngc_info); | ||
423 | +} | ||
424 | + | ||
425 | +type_init(imx_rngc_register_types) | ||
426 | -- | 152 | -- |
427 | 2.20.1 | 153 | 2.34.1 |
428 | |||
429 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair@alistair23.me> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Alistair Francis <alistair@alistair23.me> | 3 | Since commit acc0b8b05a when running the ZynqMP ZCU102 board with |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | a QEMU configured using --without-default-devices, we get: |
5 | Message-id: ef941d59fd8658589d34ed432e1d6dfdcf7fb1d0.1576658572.git.alistair@alistair23.me | 5 | |
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 6 | $ qemu-system-aarch64 -M xlnx-zcu102 |
7 | qemu-system-aarch64: missing object type 'usb_dwc3' | ||
8 | Abort trap: 6 | ||
9 | |||
10 | Fix by adding the missing Kconfig dependency. | ||
11 | |||
12 | Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230216092327.2203-1-philmd@linaro.org | ||
15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 17 | --- |
9 | hw/misc/Makefile.objs | 1 + | 18 | hw/arm/Kconfig | 1 + |
10 | include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++ | 19 | 1 file changed, 1 insertion(+) |
11 | hw/misc/stm32f4xx_exti.c | 188 +++++++++++++++++++++++++++++++ | ||
12 | hw/arm/Kconfig | 1 + | ||
13 | hw/misc/Kconfig | 3 + | ||
14 | hw/misc/trace-events | 5 + | ||
15 | 6 files changed, 258 insertions(+) | ||
16 | create mode 100644 include/hw/misc/stm32f4xx_exti.h | ||
17 | create mode 100644 hw/misc/stm32f4xx_exti.c | ||
18 | 20 | ||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/misc/Makefile.objs | ||
22 | +++ b/hw/misc/Makefile.objs | ||
23 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o | ||
24 | common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o | ||
25 | common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | ||
26 | common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o | ||
27 | +common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o | ||
28 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | ||
29 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | ||
30 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | ||
31 | diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h | ||
32 | new file mode 100644 | ||
33 | index XXXXXXX..XXXXXXX | ||
34 | --- /dev/null | ||
35 | +++ b/include/hw/misc/stm32f4xx_exti.h | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | +/* | ||
38 | + * STM32F4XX EXTI | ||
39 | + * | ||
40 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | ||
41 | + * | ||
42 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
43 | + * of this software and associated documentation files (the "Software"), to deal | ||
44 | + * in the Software without restriction, including without limitation the rights | ||
45 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
46 | + * copies of the Software, and to permit persons to whom the Software is | ||
47 | + * furnished to do so, subject to the following conditions: | ||
48 | + * | ||
49 | + * The above copyright notice and this permission notice shall be included in | ||
50 | + * all copies or substantial portions of the Software. | ||
51 | + * | ||
52 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
53 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
54 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
55 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
56 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
57 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
58 | + * THE SOFTWARE. | ||
59 | + */ | ||
60 | + | ||
61 | +#ifndef HW_STM_EXTI_H | ||
62 | +#define HW_STM_EXTI_H | ||
63 | + | ||
64 | +#include "hw/sysbus.h" | ||
65 | +#include "hw/hw.h" | ||
66 | + | ||
67 | +#define EXTI_IMR 0x00 | ||
68 | +#define EXTI_EMR 0x04 | ||
69 | +#define EXTI_RTSR 0x08 | ||
70 | +#define EXTI_FTSR 0x0C | ||
71 | +#define EXTI_SWIER 0x10 | ||
72 | +#define EXTI_PR 0x14 | ||
73 | + | ||
74 | +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti" | ||
75 | +#define STM32F4XX_EXTI(obj) \ | ||
76 | + OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI) | ||
77 | + | ||
78 | +#define NUM_GPIO_EVENT_IN_LINES 16 | ||
79 | +#define NUM_INTERRUPT_OUT_LINES 16 | ||
80 | + | ||
81 | +typedef struct { | ||
82 | + SysBusDevice parent_obj; | ||
83 | + | ||
84 | + MemoryRegion mmio; | ||
85 | + | ||
86 | + uint32_t exti_imr; | ||
87 | + uint32_t exti_emr; | ||
88 | + uint32_t exti_rtsr; | ||
89 | + uint32_t exti_ftsr; | ||
90 | + uint32_t exti_swier; | ||
91 | + uint32_t exti_pr; | ||
92 | + | ||
93 | + qemu_irq irq[NUM_INTERRUPT_OUT_LINES]; | ||
94 | +} STM32F4xxExtiState; | ||
95 | + | ||
96 | +#endif | ||
97 | diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c | ||
98 | new file mode 100644 | ||
99 | index XXXXXXX..XXXXXXX | ||
100 | --- /dev/null | ||
101 | +++ b/hw/misc/stm32f4xx_exti.c | ||
102 | @@ -XXX,XX +XXX,XX @@ | ||
103 | +/* | ||
104 | + * STM32F4XX EXTI | ||
105 | + * | ||
106 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | ||
107 | + * | ||
108 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
109 | + * of this software and associated documentation files (the "Software"), to deal | ||
110 | + * in the Software without restriction, including without limitation the rights | ||
111 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
112 | + * copies of the Software, and to permit persons to whom the Software is | ||
113 | + * furnished to do so, subject to the following conditions: | ||
114 | + * | ||
115 | + * The above copyright notice and this permission notice shall be included in | ||
116 | + * all copies or substantial portions of the Software. | ||
117 | + * | ||
118 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
119 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
120 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
121 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
122 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
123 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
124 | + * THE SOFTWARE. | ||
125 | + */ | ||
126 | + | ||
127 | +#include "qemu/osdep.h" | ||
128 | +#include "qemu/log.h" | ||
129 | +#include "trace.h" | ||
130 | +#include "hw/irq.h" | ||
131 | +#include "migration/vmstate.h" | ||
132 | +#include "hw/misc/stm32f4xx_exti.h" | ||
133 | + | ||
134 | +static void stm32f4xx_exti_reset(DeviceState *dev) | ||
135 | +{ | ||
136 | + STM32F4xxExtiState *s = STM32F4XX_EXTI(dev); | ||
137 | + | ||
138 | + s->exti_imr = 0x00000000; | ||
139 | + s->exti_emr = 0x00000000; | ||
140 | + s->exti_rtsr = 0x00000000; | ||
141 | + s->exti_ftsr = 0x00000000; | ||
142 | + s->exti_swier = 0x00000000; | ||
143 | + s->exti_pr = 0x00000000; | ||
144 | +} | ||
145 | + | ||
146 | +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) | ||
147 | +{ | ||
148 | + STM32F4xxExtiState *s = opaque; | ||
149 | + | ||
150 | + trace_stm32f4xx_exti_set_irq(irq, level); | ||
151 | + | ||
152 | + if (((1 << irq) & s->exti_rtsr) && level) { | ||
153 | + /* Rising Edge */ | ||
154 | + s->exti_pr |= 1 << irq; | ||
155 | + } | ||
156 | + | ||
157 | + if (((1 << irq) & s->exti_ftsr) && !level) { | ||
158 | + /* Falling Edge */ | ||
159 | + s->exti_pr |= 1 << irq; | ||
160 | + } | ||
161 | + | ||
162 | + if (!((1 << irq) & s->exti_imr)) { | ||
163 | + /* Interrupt is masked */ | ||
164 | + return; | ||
165 | + } | ||
166 | + qemu_irq_pulse(s->irq[irq]); | ||
167 | +} | ||
168 | + | ||
169 | +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr, | ||
170 | + unsigned int size) | ||
171 | +{ | ||
172 | + STM32F4xxExtiState *s = opaque; | ||
173 | + | ||
174 | + trace_stm32f4xx_exti_read(addr); | ||
175 | + | ||
176 | + switch (addr) { | ||
177 | + case EXTI_IMR: | ||
178 | + return s->exti_imr; | ||
179 | + case EXTI_EMR: | ||
180 | + return s->exti_emr; | ||
181 | + case EXTI_RTSR: | ||
182 | + return s->exti_rtsr; | ||
183 | + case EXTI_FTSR: | ||
184 | + return s->exti_ftsr; | ||
185 | + case EXTI_SWIER: | ||
186 | + return s->exti_swier; | ||
187 | + case EXTI_PR: | ||
188 | + return s->exti_pr; | ||
189 | + default: | ||
190 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
191 | + "STM32F4XX_exti_read: Bad offset %x\n", (int)addr); | ||
192 | + return 0; | ||
193 | + } | ||
194 | + return 0; | ||
195 | +} | ||
196 | + | ||
197 | +static void stm32f4xx_exti_write(void *opaque, hwaddr addr, | ||
198 | + uint64_t val64, unsigned int size) | ||
199 | +{ | ||
200 | + STM32F4xxExtiState *s = opaque; | ||
201 | + uint32_t value = (uint32_t) val64; | ||
202 | + | ||
203 | + trace_stm32f4xx_exti_write(addr, value); | ||
204 | + | ||
205 | + switch (addr) { | ||
206 | + case EXTI_IMR: | ||
207 | + s->exti_imr = value; | ||
208 | + return; | ||
209 | + case EXTI_EMR: | ||
210 | + s->exti_emr = value; | ||
211 | + return; | ||
212 | + case EXTI_RTSR: | ||
213 | + s->exti_rtsr = value; | ||
214 | + return; | ||
215 | + case EXTI_FTSR: | ||
216 | + s->exti_ftsr = value; | ||
217 | + return; | ||
218 | + case EXTI_SWIER: | ||
219 | + s->exti_swier = value; | ||
220 | + return; | ||
221 | + case EXTI_PR: | ||
222 | + /* This bit is cleared by writing a 1 to it */ | ||
223 | + s->exti_pr &= ~value; | ||
224 | + return; | ||
225 | + default: | ||
226 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
227 | + "STM32F4XX_exti_write: Bad offset %x\n", (int)addr); | ||
228 | + } | ||
229 | +} | ||
230 | + | ||
231 | +static const MemoryRegionOps stm32f4xx_exti_ops = { | ||
232 | + .read = stm32f4xx_exti_read, | ||
233 | + .write = stm32f4xx_exti_write, | ||
234 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
235 | +}; | ||
236 | + | ||
237 | +static void stm32f4xx_exti_init(Object *obj) | ||
238 | +{ | ||
239 | + STM32F4xxExtiState *s = STM32F4XX_EXTI(obj); | ||
240 | + int i; | ||
241 | + | ||
242 | + for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) { | ||
243 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); | ||
244 | + } | ||
245 | + | ||
246 | + memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, | ||
247 | + TYPE_STM32F4XX_EXTI, 0x400); | ||
248 | + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
249 | + | ||
250 | + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq, | ||
251 | + NUM_GPIO_EVENT_IN_LINES); | ||
252 | +} | ||
253 | + | ||
254 | +static const VMStateDescription vmstate_stm32f4xx_exti = { | ||
255 | + .name = TYPE_STM32F4XX_EXTI, | ||
256 | + .version_id = 1, | ||
257 | + .minimum_version_id = 1, | ||
258 | + .fields = (VMStateField[]) { | ||
259 | + VMSTATE_UINT32(exti_imr, STM32F4xxExtiState), | ||
260 | + VMSTATE_UINT32(exti_emr, STM32F4xxExtiState), | ||
261 | + VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState), | ||
262 | + VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState), | ||
263 | + VMSTATE_UINT32(exti_swier, STM32F4xxExtiState), | ||
264 | + VMSTATE_UINT32(exti_pr, STM32F4xxExtiState), | ||
265 | + VMSTATE_END_OF_LIST() | ||
266 | + } | ||
267 | +}; | ||
268 | + | ||
269 | +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) | ||
270 | +{ | ||
271 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
272 | + | ||
273 | + dc->reset = stm32f4xx_exti_reset; | ||
274 | + dc->vmsd = &vmstate_stm32f4xx_exti; | ||
275 | +} | ||
276 | + | ||
277 | +static const TypeInfo stm32f4xx_exti_info = { | ||
278 | + .name = TYPE_STM32F4XX_EXTI, | ||
279 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
280 | + .instance_size = sizeof(STM32F4xxExtiState), | ||
281 | + .instance_init = stm32f4xx_exti_init, | ||
282 | + .class_init = stm32f4xx_exti_class_init, | ||
283 | +}; | ||
284 | + | ||
285 | +static void stm32f4xx_exti_register_types(void) | ||
286 | +{ | ||
287 | + type_register_static(&stm32f4xx_exti_info); | ||
288 | +} | ||
289 | + | ||
290 | +type_init(stm32f4xx_exti_register_types) | ||
291 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 21 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
292 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
293 | --- a/hw/arm/Kconfig | 23 | --- a/hw/arm/Kconfig |
294 | +++ b/hw/arm/Kconfig | 24 | +++ b/hw/arm/Kconfig |
295 | @@ -XXX,XX +XXX,XX @@ config STM32F405_SOC | 25 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM |
26 | select XLNX_CSU_DMA | ||
27 | select XLNX_ZYNQMP | ||
28 | select XLNX_ZDMA | ||
29 | + select USB_DWC3 | ||
30 | |||
31 | config XLNX_VERSAL | ||
296 | bool | 32 | bool |
297 | select ARM_V7M | ||
298 | select STM32F4XX_SYSCFG | ||
299 | + select STM32F4XX_EXTI | ||
300 | |||
301 | config XLNX_ZYNQMP_ARM | ||
302 | bool | ||
303 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
304 | index XXXXXXX..XXXXXXX 100644 | ||
305 | --- a/hw/misc/Kconfig | ||
306 | +++ b/hw/misc/Kconfig | ||
307 | @@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG | ||
308 | config STM32F4XX_SYSCFG | ||
309 | bool | ||
310 | |||
311 | +config STM32F4XX_EXTI | ||
312 | + bool | ||
313 | + | ||
314 | config MIPS_ITU | ||
315 | bool | ||
316 | |||
317 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
318 | index XXXXXXX..XXXXXXX 100644 | ||
319 | --- a/hw/misc/trace-events | ||
320 | +++ b/hw/misc/trace-events | ||
321 | @@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" | ||
322 | stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " | ||
323 | stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | ||
324 | |||
325 | +# stm32f4xx_exti | ||
326 | +stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" | ||
327 | +stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " | ||
328 | +stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | ||
329 | + | ||
330 | # tz-mpc.c | ||
331 | tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
332 | tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
333 | -- | 33 | -- |
334 | 2.20.1 | 34 | 2.34.1 |
335 | 35 | ||
336 | 36 | diff view generated by jsdifflib |
1 | From: Masahiro Yamada <masahiroy@kernel.org> | 1 | From: Cornelia Huck <cohuck@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | According to the specification "Semihosting for AArch32 and Aarch64", | 3 | Just use current_accel_name() directly. |
4 | the SYS_OPEN operation should return: | ||
5 | 4 | ||
6 | - A nonzero handle if the call is successful | 5 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> |
7 | - -1 if the call is not successful | 6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | |||
9 | So, it should never return 0. | ||
10 | |||
11 | Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting | ||
12 | code hand out its own file descriptors"), the guest fd matched to the | ||
13 | host fd. It returned a nonzero handle on success since the fd 0 is | ||
14 | already used for stdin. | ||
15 | |||
16 | Now that the guest fd is the index of guestfd_array, it starts from 0. | ||
17 | |||
18 | I noticed this issue particularly because Trusted Firmware-A built with | ||
19 | PLAT=qemu is no longer working. Its io_semihosting driver only handles | ||
20 | a positive return value as a valid filehandle. | ||
21 | |||
22 | Basically, there are two ways to fix this: | ||
23 | |||
24 | - Use (guestfd - 1) as the index of guestfs_arrary. We need to insert | ||
25 | increment/decrement to convert the guestfd and the array index back | ||
26 | and forth. | ||
27 | |||
28 | - Keep using guestfd as the index of guestfs_array. The first entry | ||
29 | of guestfs_array is left unused. | ||
30 | |||
31 | I thought the latter is simpler. We end up with wasting a small piece | ||
32 | of memory for the unused first entry of guestfd_array, but this is | ||
33 | probably not a big deal. | ||
34 | |||
35 | Fixes: 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting code hand out its own file descriptors") | ||
36 | Cc: qemu-stable@nongnu.org | ||
37 | Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> | ||
38 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
39 | Message-id: 20200109041228.10131-1-masahiroy@kernel.org | ||
40 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
41 | --- | 9 | --- |
42 | target/arm/arm-semi.c | 5 +++-- | 10 | hw/arm/virt.c | 6 +++--- |
43 | 1 file changed, 3 insertions(+), 2 deletions(-) | 11 | 1 file changed, 3 insertions(+), 3 deletions(-) |
44 | 12 | ||
45 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 13 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
46 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/target/arm/arm-semi.c | 15 | --- a/hw/arm/virt.c |
48 | +++ b/target/arm/arm-semi.c | 16 | +++ b/hw/arm/virt.c |
49 | @@ -XXX,XX +XXX,XX @@ static int alloc_guestfd(void) | 17 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
50 | guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD)); | 18 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { |
19 | error_report("mach-virt: %s does not support providing " | ||
20 | "Security extensions (TrustZone) to the guest CPU", | ||
21 | - kvm_enabled() ? "KVM" : "HVF"); | ||
22 | + current_accel_name()); | ||
23 | exit(1); | ||
51 | } | 24 | } |
52 | 25 | ||
53 | - for (i = 0; i < guestfd_array->len; i++) { | 26 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { |
54 | + /* SYS_OPEN should return nonzero handle on success. Start guestfd from 1 */ | 27 | error_report("mach-virt: %s does not support providing " |
55 | + for (i = 1; i < guestfd_array->len; i++) { | 28 | "Virtualization extensions to the guest CPU", |
56 | GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i); | 29 | - kvm_enabled() ? "KVM" : "HVF"); |
57 | 30 | + current_accel_name()); | |
58 | if (gf->type == GuestFDUnused) { | 31 | exit(1); |
59 | @@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd) | ||
60 | return NULL; | ||
61 | } | 32 | } |
62 | 33 | ||
63 | - if (guestfd < 0 || guestfd >= guestfd_array->len) { | 34 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { |
64 | + if (guestfd <= 0 || guestfd >= guestfd_array->len) { | 35 | error_report("mach-virt: %s does not support providing " |
65 | return NULL; | 36 | "MTE to the guest CPU", |
37 | - kvm_enabled() ? "KVM" : "HVF"); | ||
38 | + current_accel_name()); | ||
39 | exit(1); | ||
66 | } | 40 | } |
67 | 41 | ||
68 | -- | 42 | -- |
69 | 2.20.1 | 43 | 2.34.1 |
70 | |||
71 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair@alistair23.me> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Alistair Francis <alistair@alistair23.me> | 3 | Havard is no longer working on the Nuvoton systems for a while |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | and won't be able to do any work on it in the future. So I'll |
5 | Message-id: dad8d8d47f7625913e35e27a1c00f603a6b08f9a.1576658572.git.alistair@alistair23.me | 5 | take over maintaining the Nuvoton system from him. |
6 | |||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Acked-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
10 | Message-id: 20230208235433.3989937-2-wuhaotsh@google.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | hw/arm/Makefile.objs | 1 + | 13 | MAINTAINERS | 2 +- |
9 | hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++ | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | MAINTAINERS | 6 +++++ | ||
11 | 3 files changed, 59 insertions(+) | ||
12 | create mode 100644 hw/arm/netduinoplus2.c | ||
13 | 15 | ||
14 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/Makefile.objs | ||
17 | +++ b/hw/arm/Makefile.objs | ||
18 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o | ||
19 | obj-$(CONFIG_MICROBIT) += microbit.o | ||
20 | obj-$(CONFIG_MUSICPAL) += musicpal.o | ||
21 | obj-$(CONFIG_NETDUINO2) += netduino2.o | ||
22 | +obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o | ||
23 | obj-$(CONFIG_NSERIES) += nseries.o | ||
24 | obj-$(CONFIG_SX1) += omap_sx1.o | ||
25 | obj-$(CONFIG_CHEETAH) += palm.o | ||
26 | diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c | ||
27 | new file mode 100644 | ||
28 | index XXXXXXX..XXXXXXX | ||
29 | --- /dev/null | ||
30 | +++ b/hw/arm/netduinoplus2.c | ||
31 | @@ -XXX,XX +XXX,XX @@ | ||
32 | +/* | ||
33 | + * Netduino Plus 2 Machine Model | ||
34 | + * | ||
35 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | ||
36 | + * | ||
37 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
38 | + * of this software and associated documentation files (the "Software"), to deal | ||
39 | + * in the Software without restriction, including without limitation the rights | ||
40 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
41 | + * copies of the Software, and to permit persons to whom the Software is | ||
42 | + * furnished to do so, subject to the following conditions: | ||
43 | + * | ||
44 | + * The above copyright notice and this permission notice shall be included in | ||
45 | + * all copies or substantial portions of the Software. | ||
46 | + * | ||
47 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
48 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
49 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
50 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
51 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
52 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
53 | + * THE SOFTWARE. | ||
54 | + */ | ||
55 | + | ||
56 | +#include "qemu/osdep.h" | ||
57 | +#include "qapi/error.h" | ||
58 | +#include "hw/boards.h" | ||
59 | +#include "hw/qdev-properties.h" | ||
60 | +#include "qemu/error-report.h" | ||
61 | +#include "hw/arm/stm32f405_soc.h" | ||
62 | +#include "hw/arm/boot.h" | ||
63 | + | ||
64 | +static void netduinoplus2_init(MachineState *machine) | ||
65 | +{ | ||
66 | + DeviceState *dev; | ||
67 | + | ||
68 | + dev = qdev_create(NULL, TYPE_STM32F405_SOC); | ||
69 | + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); | ||
70 | + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); | ||
71 | + | ||
72 | + armv7m_load_kernel(ARM_CPU(first_cpu), | ||
73 | + machine->kernel_filename, | ||
74 | + FLASH_SIZE); | ||
75 | +} | ||
76 | + | ||
77 | +static void netduinoplus2_machine_init(MachineClass *mc) | ||
78 | +{ | ||
79 | + mc->desc = "Netduino Plus 2 Machine"; | ||
80 | + mc->init = netduinoplus2_init; | ||
81 | +} | ||
82 | + | ||
83 | +DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) | ||
84 | diff --git a/MAINTAINERS b/MAINTAINERS | 16 | diff --git a/MAINTAINERS b/MAINTAINERS |
85 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
86 | --- a/MAINTAINERS | 18 | --- a/MAINTAINERS |
87 | +++ b/MAINTAINERS | 19 | +++ b/MAINTAINERS |
88 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | 20 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h |
89 | S: Maintained | 21 | F: docs/system/arm/musicpal.rst |
90 | F: hw/arm/netduino2.c | 22 | |
91 | 23 | Nuvoton NPCM7xx | |
92 | +Netduino Plus 2 | 24 | -M: Havard Skinnemoen <hskinnemoen@google.com> |
93 | +M: Alistair Francis <alistair@alistair23.me> | 25 | M: Tyrone Ting <kfting@nuvoton.com> |
94 | +M: Peter Maydell <peter.maydell@linaro.org> | 26 | +M: Hao Wu <wuhaotsh@google.com> |
95 | +S: Maintained | 27 | L: qemu-arm@nongnu.org |
96 | +F: hw/arm/netduinoplus2.c | 28 | S: Supported |
97 | + | 29 | F: hw/*/npcm7xx* |
98 | SmartFusion2 | ||
99 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
100 | M: Peter Maydell <peter.maydell@linaro.org> | ||
101 | -- | 30 | -- |
102 | 2.20.1 | 31 | 2.34.1 |
103 | |||
104 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair@alistair23.me> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Alistair Francis <alistair@alistair23.me> | 3 | Nuvoton's PSPI is a general purpose SPI module which enables |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | connections to SPI-based peripheral devices. |
5 | Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me | 5 | |
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
7 | Reviewed-by: Chris Rauer <crauer@google.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
9 | Message-id: 20230208235433.3989937-3-wuhaotsh@google.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | hw/misc/Makefile.objs | 1 + | 12 | MAINTAINERS | 6 +- |
9 | include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++++++ | 13 | include/hw/ssi/npcm_pspi.h | 53 +++++++++ |
10 | hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++++++++++++ | 14 | hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ |
11 | default-configs/arm-softmmu.mak | 1 + | 15 | hw/ssi/meson.build | 2 +- |
12 | hw/arm/Kconfig | 9 ++ | 16 | hw/ssi/trace-events | 5 + |
13 | hw/misc/Kconfig | 3 + | 17 | 5 files changed, 283 insertions(+), 4 deletions(-) |
14 | hw/misc/trace-events | 6 + | 18 | create mode 100644 include/hw/ssi/npcm_pspi.h |
15 | 7 files changed, 252 insertions(+) | 19 | create mode 100644 hw/ssi/npcm_pspi.c |
16 | create mode 100644 include/hw/misc/stm32f4xx_syscfg.h | ||
17 | create mode 100644 hw/misc/stm32f4xx_syscfg.c | ||
18 | 20 | ||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 21 | diff --git a/MAINTAINERS b/MAINTAINERS |
20 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/Makefile.objs | 23 | --- a/MAINTAINERS |
22 | +++ b/hw/misc/Makefile.objs | 24 | +++ b/MAINTAINERS |
23 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o | 25 | @@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com> |
24 | common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o | 26 | M: Hao Wu <wuhaotsh@google.com> |
25 | common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o | 27 | L: qemu-arm@nongnu.org |
26 | common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | 28 | S: Supported |
27 | +common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o | 29 | -F: hw/*/npcm7xx* |
28 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | 30 | -F: include/hw/*/npcm7xx* |
29 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | 31 | -F: tests/qtest/npcm7xx* |
30 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 32 | +F: hw/*/npcm* |
31 | diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h | 33 | +F: include/hw/*/npcm* |
34 | +F: tests/qtest/npcm* | ||
35 | F: pc-bios/npcm7xx_bootrom.bin | ||
36 | F: roms/vbootrom | ||
37 | F: docs/system/arm/nuvoton.rst | ||
38 | diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h | ||
32 | new file mode 100644 | 39 | new file mode 100644 |
33 | index XXXXXXX..XXXXXXX | 40 | index XXXXXXX..XXXXXXX |
34 | --- /dev/null | 41 | --- /dev/null |
35 | +++ b/include/hw/misc/stm32f4xx_syscfg.h | 42 | +++ b/include/hw/ssi/npcm_pspi.h |
36 | @@ -XXX,XX +XXX,XX @@ | 43 | @@ -XXX,XX +XXX,XX @@ |
37 | +/* | 44 | +/* |
38 | + * STM32F4xx SYSCFG | 45 | + * Nuvoton Peripheral SPI Module |
39 | + * | 46 | + * |
40 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | 47 | + * Copyright 2023 Google LLC |
41 | + * | 48 | + * |
42 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 49 | + * This program is free software; you can redistribute it and/or modify it |
43 | + * of this software and associated documentation files (the "Software"), to deal | 50 | + * under the terms of the GNU General Public License as published by the |
44 | + * in the Software without restriction, including without limitation the rights | 51 | + * Free Software Foundation; either version 2 of the License, or |
45 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 52 | + * (at your option) any later version. |
46 | + * copies of the Software, and to permit persons to whom the Software is | 53 | + * |
47 | + * furnished to do so, subject to the following conditions: | 54 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
48 | + * | 55 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
49 | + * The above copyright notice and this permission notice shall be included in | 56 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
50 | + * all copies or substantial portions of the Software. | 57 | + * for more details. |
51 | + * | ||
52 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
53 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
54 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
55 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
56 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
57 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
58 | + * THE SOFTWARE. | ||
59 | + */ | 58 | + */ |
60 | + | 59 | +#ifndef NPCM_PSPI_H |
61 | +#ifndef HW_STM_SYSCFG_H | 60 | +#define NPCM_PSPI_H |
62 | +#define HW_STM_SYSCFG_H | 61 | + |
63 | + | 62 | +#include "hw/ssi/ssi.h" |
64 | +#include "hw/sysbus.h" | 63 | +#include "hw/sysbus.h" |
65 | +#include "hw/hw.h" | 64 | + |
66 | + | 65 | +/* |
67 | +#define SYSCFG_MEMRMP 0x00 | 66 | + * Number of registers in our device state structure. Don't change this without |
68 | +#define SYSCFG_PMC 0x04 | 67 | + * incrementing the version_id in the vmstate. |
69 | +#define SYSCFG_EXTICR1 0x08 | 68 | + */ |
70 | +#define SYSCFG_EXTICR2 0x0C | 69 | +#define NPCM_PSPI_NR_REGS 3 |
71 | +#define SYSCFG_EXTICR3 0x10 | 70 | + |
72 | +#define SYSCFG_EXTICR4 0x14 | 71 | +/** |
73 | +#define SYSCFG_CMPCR 0x20 | 72 | + * NPCMPSPIState - Device state for one Flash Interface Unit. |
74 | + | 73 | + * @parent: System bus device. |
75 | +#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg" | 74 | + * @mmio: Memory region for register access. |
76 | +#define STM32F4XX_SYSCFG(obj) \ | 75 | + * @spi: The SPI bus mastered by this controller. |
77 | + OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG) | 76 | + * @regs: Register contents. |
78 | + | 77 | + * @irq: The interrupt request queue for this module. |
79 | +#define SYSCFG_NUM_EXTICR 4 | 78 | + * |
80 | + | 79 | + * Each PSPI has a shared bank of registers, and controls up to four chip |
81 | +typedef struct { | 80 | + * selects. Each chip select has a dedicated memory region which may be used to |
82 | + /* <private> */ | 81 | + * read and write the flash connected to that chip select as if it were memory. |
83 | + SysBusDevice parent_obj; | 82 | + */ |
84 | + | 83 | +typedef struct NPCMPSPIState { |
85 | + /* <public> */ | 84 | + SysBusDevice parent; |
85 | + | ||
86 | + MemoryRegion mmio; | 86 | + MemoryRegion mmio; |
87 | + | 87 | + |
88 | + uint32_t syscfg_memrmp; | 88 | + SSIBus *spi; |
89 | + uint32_t syscfg_pmc; | 89 | + uint16_t regs[NPCM_PSPI_NR_REGS]; |
90 | + uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR]; | ||
91 | + uint32_t syscfg_cmpcr; | ||
92 | + | ||
93 | + qemu_irq irq; | 90 | + qemu_irq irq; |
94 | + qemu_irq gpio_out[16]; | 91 | +} NPCMPSPIState; |
95 | +} STM32F4xxSyscfgState; | 92 | + |
96 | + | 93 | +#define TYPE_NPCM_PSPI "npcm-pspi" |
97 | +#endif | 94 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) |
98 | diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c | 95 | + |
96 | +#endif /* NPCM_PSPI_H */ | ||
97 | diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c | ||
99 | new file mode 100644 | 98 | new file mode 100644 |
100 | index XXXXXXX..XXXXXXX | 99 | index XXXXXXX..XXXXXXX |
101 | --- /dev/null | 100 | --- /dev/null |
102 | +++ b/hw/misc/stm32f4xx_syscfg.c | 101 | +++ b/hw/ssi/npcm_pspi.c |
103 | @@ -XXX,XX +XXX,XX @@ | 102 | @@ -XXX,XX +XXX,XX @@ |
104 | +/* | 103 | +/* |
105 | + * STM32F4xx SYSCFG | 104 | + * Nuvoton NPCM Peripheral SPI Module (PSPI) |
106 | + * | 105 | + * |
107 | + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | 106 | + * Copyright 2023 Google LLC |
108 | + * | 107 | + * |
109 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 108 | + * This program is free software; you can redistribute it and/or modify it |
110 | + * of this software and associated documentation files (the "Software"), to deal | 109 | + * under the terms of the GNU General Public License as published by the |
111 | + * in the Software without restriction, including without limitation the rights | 110 | + * Free Software Foundation; either version 2 of the License, or |
112 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 111 | + * (at your option) any later version. |
113 | + * copies of the Software, and to permit persons to whom the Software is | 112 | + * |
114 | + * furnished to do so, subject to the following conditions: | 113 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
115 | + * | 114 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
116 | + * The above copyright notice and this permission notice shall be included in | 115 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
117 | + * all copies or substantial portions of the Software. | 116 | + * for more details. |
118 | + * | ||
119 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
120 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
121 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
122 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
123 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
124 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
125 | + * THE SOFTWARE. | ||
126 | + */ | 117 | + */ |
127 | + | 118 | + |
128 | +#include "qemu/osdep.h" | 119 | +#include "qemu/osdep.h" |
120 | + | ||
121 | +#include "hw/irq.h" | ||
122 | +#include "hw/registerfields.h" | ||
123 | +#include "hw/ssi/npcm_pspi.h" | ||
124 | +#include "migration/vmstate.h" | ||
125 | +#include "qapi/error.h" | ||
126 | +#include "qemu/error-report.h" | ||
129 | +#include "qemu/log.h" | 127 | +#include "qemu/log.h" |
128 | +#include "qemu/module.h" | ||
129 | +#include "qemu/units.h" | ||
130 | + | ||
130 | +#include "trace.h" | 131 | +#include "trace.h" |
131 | +#include "hw/irq.h" | 132 | + |
132 | +#include "migration/vmstate.h" | 133 | +REG16(PSPI_DATA, 0x0) |
133 | +#include "hw/misc/stm32f4xx_syscfg.h" | 134 | +REG16(PSPI_CTL1, 0x2) |
134 | + | 135 | + FIELD(PSPI_CTL1, SPIEN, 0, 1) |
135 | +static void stm32f4xx_syscfg_reset(DeviceState *dev) | 136 | + FIELD(PSPI_CTL1, MOD, 2, 1) |
136 | +{ | 137 | + FIELD(PSPI_CTL1, EIR, 5, 1) |
137 | + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev); | 138 | + FIELD(PSPI_CTL1, EIW, 6, 1) |
138 | + | 139 | + FIELD(PSPI_CTL1, SCM, 7, 1) |
139 | + s->syscfg_memrmp = 0x00000000; | 140 | + FIELD(PSPI_CTL1, SCIDL, 8, 1) |
140 | + s->syscfg_pmc = 0x00000000; | 141 | + FIELD(PSPI_CTL1, SCDV, 9, 7) |
141 | + s->syscfg_exticr[0] = 0x00000000; | 142 | +REG16(PSPI_STAT, 0x4) |
142 | + s->syscfg_exticr[1] = 0x00000000; | 143 | + FIELD(PSPI_STAT, BSY, 0, 1) |
143 | + s->syscfg_exticr[2] = 0x00000000; | 144 | + FIELD(PSPI_STAT, RBF, 1, 1) |
144 | + s->syscfg_exticr[3] = 0x00000000; | 145 | + |
145 | + s->syscfg_cmpcr = 0x00000000; | 146 | +static void npcm_pspi_update_irq(NPCMPSPIState *s) |
146 | +} | 147 | +{ |
147 | + | 148 | + int level = 0; |
148 | +static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level) | 149 | + |
149 | +{ | 150 | + /* Only fire IRQ when the module is enabled. */ |
150 | + STM32F4xxSyscfgState *s = opaque; | 151 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { |
151 | + int icrreg = irq / 4; | 152 | + /* Update interrupt as BSY is cleared. */ |
152 | + int startbit = (irq & 3) * 4; | 153 | + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && |
153 | + uint8_t config = config = irq / 16; | 154 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { |
154 | + | 155 | + level = 1; |
155 | + trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level); | 156 | + } |
156 | + | 157 | + |
157 | + g_assert(icrreg < SYSCFG_NUM_EXTICR); | 158 | + /* Update interrupt as RBF is set. */ |
158 | + | 159 | + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && |
159 | + if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) { | 160 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { |
160 | + qemu_set_irq(s->gpio_out[irq], level); | 161 | + level = 1; |
161 | + trace_stm32f4xx_pulse_exti(irq); | 162 | + } |
162 | + } | 163 | + } |
163 | +} | 164 | + qemu_set_irq(s->irq, level); |
164 | + | 165 | +} |
165 | +static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr, | 166 | + |
166 | + unsigned int size) | 167 | +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) |
167 | +{ | 168 | +{ |
168 | + STM32F4xxSyscfgState *s = opaque; | 169 | + uint16_t value = s->regs[R_PSPI_DATA]; |
169 | + | 170 | + |
170 | + trace_stm32f4xx_syscfg_read(addr); | 171 | + /* Clear stat bits as the value are read out. */ |
172 | + s->regs[R_PSPI_STAT] = 0; | ||
173 | + | ||
174 | + return value; | ||
175 | +} | ||
176 | + | ||
177 | +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) | ||
178 | +{ | ||
179 | + uint16_t value = 0; | ||
180 | + | ||
181 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { | ||
182 | + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; | ||
183 | + } | ||
184 | + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); | ||
185 | + s->regs[R_PSPI_DATA] = value; | ||
186 | + | ||
187 | + /* Mark data as available */ | ||
188 | + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; | ||
189 | +} | ||
190 | + | ||
191 | +/* Control register read handler. */ | ||
192 | +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, | ||
193 | + unsigned int size) | ||
194 | +{ | ||
195 | + NPCMPSPIState *s = opaque; | ||
196 | + uint16_t value; | ||
171 | + | 197 | + |
172 | + switch (addr) { | 198 | + switch (addr) { |
173 | + case SYSCFG_MEMRMP: | 199 | + case A_PSPI_DATA: |
174 | + return s->syscfg_memrmp; | 200 | + value = npcm_pspi_read_data(s); |
175 | + case SYSCFG_PMC: | 201 | + break; |
176 | + return s->syscfg_pmc; | 202 | + |
177 | + case SYSCFG_EXTICR1...SYSCFG_EXTICR4: | 203 | + case A_PSPI_CTL1: |
178 | + return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4]; | 204 | + value = s->regs[R_PSPI_CTL1]; |
179 | + case SYSCFG_CMPCR: | 205 | + break; |
180 | + return s->syscfg_cmpcr; | 206 | + |
207 | + case A_PSPI_STAT: | ||
208 | + value = s->regs[R_PSPI_STAT]; | ||
209 | + break; | ||
210 | + | ||
181 | + default: | 211 | + default: |
182 | + qemu_log_mask(LOG_GUEST_ERROR, | 212 | + qemu_log_mask(LOG_GUEST_ERROR, |
183 | + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); | 213 | + "%s: write to invalid offset 0x%" PRIx64 "\n", |
214 | + DEVICE(s)->canonical_path, addr); | ||
184 | + return 0; | 215 | + return 0; |
185 | + } | 216 | + } |
186 | +} | 217 | + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); |
187 | + | 218 | + npcm_pspi_update_irq(s); |
188 | +static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr, | 219 | + |
189 | + uint64_t val64, unsigned int size) | 220 | + return value; |
190 | +{ | 221 | +} |
191 | + STM32F4xxSyscfgState *s = opaque; | 222 | + |
192 | + uint32_t value = val64; | 223 | +/* Control register write handler. */ |
193 | + | 224 | +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, |
194 | + trace_stm32f4xx_syscfg_write(value, addr); | 225 | + unsigned int size) |
226 | +{ | ||
227 | + NPCMPSPIState *s = opaque; | ||
228 | + uint16_t value = v; | ||
229 | + | ||
230 | + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); | ||
195 | + | 231 | + |
196 | + switch (addr) { | 232 | + switch (addr) { |
197 | + case SYSCFG_MEMRMP: | 233 | + case A_PSPI_DATA: |
198 | + qemu_log_mask(LOG_UNIMP, | 234 | + npcm_pspi_write_data(s, value); |
199 | + "%s: Changing the memory mapping isn't supported " \ | 235 | + break; |
200 | + "in QEMU\n", __func__); | 236 | + |
201 | + return; | 237 | + case A_PSPI_CTL1: |
202 | + case SYSCFG_PMC: | 238 | + s->regs[R_PSPI_CTL1] = value; |
203 | + qemu_log_mask(LOG_UNIMP, | 239 | + break; |
204 | + "%s: Changing the memory mapping isn't supported " \ | 240 | + |
205 | + "in QEMU\n", __func__); | 241 | + case A_PSPI_STAT: |
206 | + return; | 242 | + qemu_log_mask(LOG_GUEST_ERROR, |
207 | + case SYSCFG_EXTICR1...SYSCFG_EXTICR4: | 243 | + "%s: write to read-only register PSPI_STAT: 0x%08" |
208 | + s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF); | 244 | + PRIx64 "\n", DEVICE(s)->canonical_path, v); |
209 | + return; | 245 | + break; |
210 | + case SYSCFG_CMPCR: | 246 | + |
211 | + s->syscfg_cmpcr = value; | ||
212 | + return; | ||
213 | + default: | 247 | + default: |
214 | + qemu_log_mask(LOG_GUEST_ERROR, | 248 | + qemu_log_mask(LOG_GUEST_ERROR, |
215 | + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); | 249 | + "%s: write to invalid offset 0x%" PRIx64 "\n", |
250 | + DEVICE(s)->canonical_path, addr); | ||
251 | + return; | ||
216 | + } | 252 | + } |
217 | +} | 253 | + npcm_pspi_update_irq(s); |
218 | + | 254 | +} |
219 | +static const MemoryRegionOps stm32f4xx_syscfg_ops = { | 255 | + |
220 | + .read = stm32f4xx_syscfg_read, | 256 | +static const MemoryRegionOps npcm_pspi_ctrl_ops = { |
221 | + .write = stm32f4xx_syscfg_write, | 257 | + .read = npcm_pspi_ctrl_read, |
222 | + .endianness = DEVICE_NATIVE_ENDIAN, | 258 | + .write = npcm_pspi_ctrl_write, |
259 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
260 | + .valid = { | ||
261 | + .min_access_size = 1, | ||
262 | + .max_access_size = 2, | ||
263 | + .unaligned = false, | ||
264 | + }, | ||
265 | + .impl = { | ||
266 | + .min_access_size = 2, | ||
267 | + .max_access_size = 2, | ||
268 | + .unaligned = false, | ||
269 | + }, | ||
223 | +}; | 270 | +}; |
224 | + | 271 | + |
225 | +static void stm32f4xx_syscfg_init(Object *obj) | 272 | +static void npcm_pspi_enter_reset(Object *obj, ResetType type) |
226 | +{ | 273 | +{ |
227 | + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj); | 274 | + NPCMPSPIState *s = NPCM_PSPI(obj); |
228 | + | 275 | + |
229 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | 276 | + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); |
230 | + | 277 | + memset(s->regs, 0, sizeof(s->regs)); |
231 | + memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s, | 278 | +} |
232 | + TYPE_STM32F4XX_SYSCFG, 0x400); | 279 | + |
233 | + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | 280 | +static void npcm_pspi_realize(DeviceState *dev, Error **errp) |
234 | + | 281 | +{ |
235 | + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9); | 282 | + NPCMPSPIState *s = NPCM_PSPI(dev); |
236 | + qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16); | 283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
237 | +} | 284 | + Object *obj = OBJECT(dev); |
238 | + | 285 | + |
239 | +static const VMStateDescription vmstate_stm32f4xx_syscfg = { | 286 | + s->spi = ssi_create_bus(dev, "pspi"); |
240 | + .name = TYPE_STM32F4XX_SYSCFG, | 287 | + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, |
241 | + .version_id = 1, | 288 | + "mmio", 4 * KiB); |
242 | + .minimum_version_id = 1, | 289 | + sysbus_init_mmio(sbd, &s->mmio); |
290 | + sysbus_init_irq(sbd, &s->irq); | ||
291 | +} | ||
292 | + | ||
293 | +static const VMStateDescription vmstate_npcm_pspi = { | ||
294 | + .name = "npcm-pspi", | ||
295 | + .version_id = 0, | ||
296 | + .minimum_version_id = 0, | ||
243 | + .fields = (VMStateField[]) { | 297 | + .fields = (VMStateField[]) { |
244 | + VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState), | 298 | + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), |
245 | + VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState), | 299 | + VMSTATE_END_OF_LIST(), |
246 | + VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState, | 300 | + }, |
247 | + SYSCFG_NUM_EXTICR), | ||
248 | + VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState), | ||
249 | + VMSTATE_END_OF_LIST() | ||
250 | + } | ||
251 | +}; | 301 | +}; |
252 | + | 302 | + |
253 | +static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data) | 303 | + |
254 | +{ | 304 | +static void npcm_pspi_class_init(ObjectClass *klass, void *data) |
305 | +{ | ||
306 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
255 | + DeviceClass *dc = DEVICE_CLASS(klass); | 307 | + DeviceClass *dc = DEVICE_CLASS(klass); |
256 | + | 308 | + |
257 | + dc->reset = stm32f4xx_syscfg_reset; | 309 | + dc->desc = "NPCM Peripheral SPI Module"; |
258 | + dc->vmsd = &vmstate_stm32f4xx_syscfg; | 310 | + dc->realize = npcm_pspi_realize; |
259 | +} | 311 | + dc->vmsd = &vmstate_npcm_pspi; |
260 | + | 312 | + rc->phases.enter = npcm_pspi_enter_reset; |
261 | +static const TypeInfo stm32f4xx_syscfg_info = { | 313 | +} |
262 | + .name = TYPE_STM32F4XX_SYSCFG, | 314 | + |
263 | + .parent = TYPE_SYS_BUS_DEVICE, | 315 | +static const TypeInfo npcm_pspi_types[] = { |
264 | + .instance_size = sizeof(STM32F4xxSyscfgState), | 316 | + { |
265 | + .instance_init = stm32f4xx_syscfg_init, | 317 | + .name = TYPE_NPCM_PSPI, |
266 | + .class_init = stm32f4xx_syscfg_class_init, | 318 | + .parent = TYPE_SYS_BUS_DEVICE, |
319 | + .instance_size = sizeof(NPCMPSPIState), | ||
320 | + .class_init = npcm_pspi_class_init, | ||
321 | + }, | ||
267 | +}; | 322 | +}; |
268 | + | 323 | +DEFINE_TYPES(npcm_pspi_types); |
269 | +static void stm32f4xx_syscfg_register_types(void) | 324 | diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build |
270 | +{ | ||
271 | + type_register_static(&stm32f4xx_syscfg_info); | ||
272 | +} | ||
273 | + | ||
274 | +type_init(stm32f4xx_syscfg_register_types) | ||
275 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
276 | index XXXXXXX..XXXXXXX 100644 | 325 | index XXXXXXX..XXXXXXX 100644 |
277 | --- a/default-configs/arm-softmmu.mak | 326 | --- a/hw/ssi/meson.build |
278 | +++ b/default-configs/arm-softmmu.mak | 327 | +++ b/hw/ssi/meson.build |
279 | @@ -XXX,XX +XXX,XX @@ CONFIG_Z2=y | 328 | @@ -XXX,XX +XXX,XX @@ |
280 | CONFIG_COLLIE=y | 329 | softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) |
281 | CONFIG_ASPEED_SOC=y | 330 | softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) |
282 | CONFIG_NETDUINO2=y | 331 | -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) |
283 | +CONFIG_NETDUINOPLUS2=y | 332 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) |
284 | CONFIG_MPS2=y | 333 | softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) |
285 | CONFIG_RASPI=y | 334 | softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) |
286 | CONFIG_DIGIC=y | 335 | softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) |
287 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 336 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events |
288 | index XXXXXXX..XXXXXXX 100644 | 337 | index XXXXXXX..XXXXXXX 100644 |
289 | --- a/hw/arm/Kconfig | 338 | --- a/hw/ssi/trace-events |
290 | +++ b/hw/arm/Kconfig | 339 | +++ b/hw/ssi/trace-events |
291 | @@ -XXX,XX +XXX,XX @@ config NETDUINO2 | 340 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: |
292 | bool | 341 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 |
293 | select STM32F205_SOC | 342 | npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 |
294 | 343 | ||
295 | +config NETDUINOPLUS2 | 344 | +# npcm_pspi.c |
296 | + bool | 345 | +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" |
297 | + select STM32F405_SOC | 346 | +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 |
298 | + | 347 | +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 |
299 | config NSERIES | 348 | + |
300 | bool | 349 | # ibex_spi_host.c |
301 | select OMAP | 350 | |
302 | @@ -XXX,XX +XXX,XX @@ config STM32F205_SOC | 351 | ibex_spi_host_reset(const char *msg) "%s" |
303 | select STM32F2XX_ADC | ||
304 | select STM32F2XX_SPI | ||
305 | |||
306 | +config STM32F405_SOC | ||
307 | + bool | ||
308 | + select ARM_V7M | ||
309 | + select STM32F4XX_SYSCFG | ||
310 | + | ||
311 | config XLNX_ZYNQMP_ARM | ||
312 | bool | ||
313 | select AHCI | ||
314 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/hw/misc/Kconfig | ||
317 | +++ b/hw/misc/Kconfig | ||
318 | @@ -XXX,XX +XXX,XX @@ config IMX | ||
319 | config STM32F2XX_SYSCFG | ||
320 | bool | ||
321 | |||
322 | +config STM32F4XX_SYSCFG | ||
323 | + bool | ||
324 | + | ||
325 | config MIPS_ITU | ||
326 | bool | ||
327 | |||
328 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
329 | index XXXXXXX..XXXXXXX 100644 | ||
330 | --- a/hw/misc/trace-events | ||
331 | +++ b/hw/misc/trace-events | ||
332 | @@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int" | ||
333 | mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 | ||
334 | mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" | ||
335 | |||
336 | +# stm32f4xx_syscfg | ||
337 | +stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" | ||
338 | +stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" | ||
339 | +stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " | ||
340 | +stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | ||
341 | + | ||
342 | # tz-mpc.c | ||
343 | tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
344 | tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
345 | -- | 352 | -- |
346 | 2.20.1 | 353 | 2.34.1 |
347 | |||
348 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
1 | 2 | ||
3 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
4 | Reviewed-by: Titus Rwantare <titusr@google.com> | ||
5 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
6 | Message-id: 20230208235433.3989937-4-wuhaotsh@google.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | docs/system/arm/nuvoton.rst | 2 +- | ||
10 | include/hw/arm/npcm7xx.h | 2 ++ | ||
11 | hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- | ||
12 | 3 files changed, 26 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/docs/system/arm/nuvoton.rst | ||
17 | +++ b/docs/system/arm/nuvoton.rst | ||
18 | @@ -XXX,XX +XXX,XX @@ Supported devices | ||
19 | * SMBus controller (SMBF) | ||
20 | * Ethernet controller (EMC) | ||
21 | * Tachometer | ||
22 | + * Peripheral SPI controller (PSPI) | ||
23 | |||
24 | Missing devices | ||
25 | --------------- | ||
26 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
27 | |||
28 | * Ethernet controller (GMAC) | ||
29 | * USB device (USBD) | ||
30 | - * Peripheral SPI controller (PSPI) | ||
31 | * SD/MMC host | ||
32 | * PECI interface | ||
33 | * PCI and PCIe root complex and bridges | ||
34 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/npcm7xx.h | ||
37 | +++ b/include/hw/arm/npcm7xx.h | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #include "hw/nvram/npcm7xx_otp.h" | ||
40 | #include "hw/timer/npcm7xx_timer.h" | ||
41 | #include "hw/ssi/npcm7xx_fiu.h" | ||
42 | +#include "hw/ssi/npcm_pspi.h" | ||
43 | #include "hw/usb/hcd-ehci.h" | ||
44 | #include "hw/usb/hcd-ohci.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxState { | ||
47 | NPCM7xxFIUState fiu[2]; | ||
48 | NPCM7xxEMCState emc[2]; | ||
49 | NPCM7xxSDHCIState mmc; | ||
50 | + NPCMPSPIState pspi[2]; | ||
51 | }; | ||
52 | |||
53 | #define TYPE_NPCM7XX "npcm7xx" | ||
54 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/arm/npcm7xx.c | ||
57 | +++ b/hw/arm/npcm7xx.c | ||
58 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | ||
59 | NPCM7XX_EMC1RX_IRQ = 15, | ||
60 | NPCM7XX_EMC1TX_IRQ, | ||
61 | NPCM7XX_MMC_IRQ = 26, | ||
62 | + NPCM7XX_PSPI2_IRQ = 28, | ||
63 | + NPCM7XX_PSPI1_IRQ = 31, | ||
64 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ | ||
65 | NPCM7XX_TIMER1_IRQ, | ||
66 | NPCM7XX_TIMER2_IRQ, | ||
67 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = { | ||
68 | 0xf0826000, | ||
69 | }; | ||
70 | |||
71 | +/* Register base address for each PSPI Module */ | ||
72 | +static const hwaddr npcm7xx_pspi_addr[] = { | ||
73 | + 0xf0200000, | ||
74 | + 0xf0201000, | ||
75 | +}; | ||
76 | + | ||
77 | static const struct { | ||
78 | hwaddr regs_addr; | ||
79 | uint32_t unconnected_pins; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
81 | object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); | ||
82 | } | ||
83 | |||
84 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
85 | + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); | ||
86 | + } | ||
87 | + | ||
88 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); | ||
89 | } | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
92 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, | ||
93 | npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); | ||
94 | |||
95 | + /* PSPI */ | ||
96 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); | ||
97 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
98 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); | ||
99 | + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; | ||
100 | + | ||
101 | + sysbus_realize(sbd, &error_abort); | ||
102 | + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); | ||
103 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); | ||
104 | + } | ||
105 | + | ||
106 | create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); | ||
107 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | ||
108 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | ||
109 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
110 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); | ||
111 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | ||
112 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | ||
113 | - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); | ||
114 | - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); | ||
115 | create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); | ||
116 | create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); | ||
117 | create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); | ||
118 | -- | ||
119 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
1 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set. Ensure the IOMMU region covers all 64 bits. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/smmu-common.h | 2 -- | ||
13 | hw/arm/smmu-common.c | 2 +- | ||
14 | 2 files changed, 1 insertion(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/smmu-common.h | ||
19 | +++ b/include/hw/arm/smmu-common.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #define SMMU_PCI_DEVFN_MAX 256 | ||
22 | #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) | ||
23 | |||
24 | -#define SMMU_MAX_VA_BITS 48 | ||
25 | - | ||
26 | /* | ||
27 | * Page table walk error types | ||
28 | */ | ||
29 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/smmu-common.c | ||
32 | +++ b/hw/arm/smmu-common.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | ||
34 | |||
35 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), | ||
36 | s->mrtypename, | ||
37 | - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); | ||
38 | + OBJECT(s), name, UINT64_MAX); | ||
39 | address_space_init(&sdev->as, | ||
40 | MEMORY_REGION(&sdev->iommu), name); | ||
41 | trace_smmu_add_mr(name); | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
1 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set (except for the top byte when TBI is enabled). Fix | ||
5 | the TTB1 check. | ||
6 | |||
7 | Reported-by: Ola Hugosson <ola.hugosson@arm.com> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/smmu-common.c | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/smmu-common.c | ||
20 | +++ b/hw/arm/smmu-common.c | ||
21 | @@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) | ||
22 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | ||
23 | return &cfg->tt[0]; | ||
24 | } else if (cfg->tt[1].tsz && | ||
25 | - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { | ||
26 | + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { | ||
27 | /* there is a ttbr1 region and we are in it (high bits all one) */ | ||
28 | return &cfg->tt[1]; | ||
29 | } else if (!cfg->tt[0].tsz) { | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | By calling qdev_pass_gpios() we don't need to hold a copy of the | 3 | make it clearer from the name that this is a tcg-only function. |
4 | IRQs from the INTC into the SoC state. | ||
5 | Instead of filling an array of qemu_irq and passing it around, we | ||
6 | can now directly call qdev_get_gpio_in() on the SoC. | ||
7 | 4 | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
9 | Message-id: 20191230110953.25496-5-f4bug@amsat.org | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | 11 | --- |
13 | include/hw/arm/allwinner-a10.h | 1 - | 12 | target/arm/helper.c | 4 ++-- |
14 | hw/arm/allwinner-a10.c | 24 +++++++++++------------- | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
15 | 2 files changed, 11 insertions(+), 14 deletions(-) | ||
16 | 14 | ||
17 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/allwinner-a10.h | 17 | --- a/target/arm/helper.c |
20 | +++ b/include/hw/arm/allwinner-a10.h | 18 | +++ b/target/arm/helper.c |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct AwA10State { | 19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
22 | /*< public >*/ | 20 | * trapped to the hypervisor in KVM. |
23 | 21 | */ | |
24 | ARMCPU cpu; | 22 | #ifdef CONFIG_TCG |
25 | - qemu_irq irq[AW_A10_PIC_INT_NR]; | 23 | -static void handle_semihosting(CPUState *cs) |
26 | AwA10PITState timer; | 24 | +static void tcg_handle_semihosting(CPUState *cs) |
27 | AwA10PICState intc; | ||
28 | AwEmacState emac; | ||
29 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/allwinner-a10.c | ||
32 | +++ b/hw/arm/allwinner-a10.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | ||
34 | { | 25 | { |
35 | AwA10State *s = AW_A10(dev); | 26 | ARMCPU *cpu = ARM_CPU(cs); |
36 | SysBusDevice *sysbusdev; | 27 | CPUARMState *env = &cpu->env; |
37 | - uint8_t i; | 28 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) |
38 | qemu_irq fiq, irq; | 29 | */ |
39 | Error *err = NULL; | 30 | #ifdef CONFIG_TCG |
40 | 31 | if (cs->exception_index == EXCP_SEMIHOST) { | |
41 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 32 | - handle_semihosting(cs); |
42 | sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); | 33 | + tcg_handle_semihosting(cs); |
43 | sysbus_connect_irq(sysbusdev, 0, irq); | ||
44 | sysbus_connect_irq(sysbusdev, 1, fiq); | ||
45 | - for (i = 0; i < AW_A10_PIC_INT_NR; i++) { | ||
46 | - s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i); | ||
47 | - } | ||
48 | + qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); | ||
49 | |||
50 | object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); | ||
51 | if (err != NULL) { | ||
52 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | ||
53 | } | ||
54 | sysbusdev = SYS_BUS_DEVICE(&s->timer); | ||
55 | sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); | ||
56 | - sysbus_connect_irq(sysbusdev, 0, s->irq[22]); | ||
57 | - sysbus_connect_irq(sysbusdev, 1, s->irq[23]); | ||
58 | - sysbus_connect_irq(sysbusdev, 2, s->irq[24]); | ||
59 | - sysbus_connect_irq(sysbusdev, 3, s->irq[25]); | ||
60 | - sysbus_connect_irq(sysbusdev, 4, s->irq[67]); | ||
61 | - sysbus_connect_irq(sysbusdev, 5, s->irq[68]); | ||
62 | + sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); | ||
63 | + sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); | ||
64 | + sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); | ||
65 | + sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); | ||
66 | + sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); | ||
67 | + sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); | ||
68 | |||
69 | memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, | ||
70 | &error_fatal); | ||
71 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | ||
72 | } | ||
73 | sysbusdev = SYS_BUS_DEVICE(&s->emac); | ||
74 | sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); | ||
75 | - sysbus_connect_irq(sysbusdev, 0, s->irq[55]); | ||
76 | + sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); | ||
77 | |||
78 | object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); | ||
79 | if (err) { | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | ||
81 | return; | 34 | return; |
82 | } | 35 | } |
83 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); | 36 | #endif |
84 | - sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); | ||
85 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); | ||
86 | |||
87 | /* FIXME use a qdev chardev prop instead of serial_hd() */ | ||
88 | - serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], | ||
89 | + serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, | ||
90 | + qdev_get_gpio_in(dev, 1), | ||
91 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); | ||
92 | } | ||
93 | |||
94 | -- | 37 | -- |
95 | 2.20.1 | 38 | 2.34.1 |
96 | 39 | ||
97 | 40 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | These definitions are specific to the A10 SoC and don't need | 3 | for "all" builds (tcg + kvm), we want to avoid doing |
4 | to be exported to the different Allwinner peripherals. | 4 | the psci check if tcg is built-in, but not enabled. |
5 | 5 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
7 | Message-id: 20191230110953.25496-4-f4bug@amsat.org | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | 11 | --- |
11 | include/hw/arm/allwinner-a10.h | 6 ------ | 12 | target/arm/helper.c | 3 ++- |
12 | hw/arm/allwinner-a10.c | 6 ++++++ | 13 | 1 file changed, 2 insertions(+), 1 deletion(-) |
13 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
14 | 14 | ||
15 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/allwinner-a10.h | 17 | --- a/target/arm/helper.c |
18 | +++ b/include/hw/arm/allwinner-a10.h | 18 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
20 | #include "target/arm/cpu.h" | 20 | #include "hw/irq.h" |
21 | 21 | #include "sysemu/cpu-timers.h" | |
22 | 22 | #include "sysemu/kvm.h" | |
23 | -#define AW_A10_PIC_REG_BASE 0x01c20400 | 23 | +#include "sysemu/tcg.h" |
24 | -#define AW_A10_PIT_REG_BASE 0x01c20c00 | 24 | #include "qapi/qapi-commands-machine-target.h" |
25 | -#define AW_A10_UART0_REG_BASE 0x01c28000 | 25 | #include "qapi/error.h" |
26 | -#define AW_A10_EMAC_BASE 0x01c0b000 | 26 | #include "qemu/guest-random.h" |
27 | -#define AW_A10_SATA_BASE 0x01c18000 | 27 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) |
28 | - | 28 | env->exception.syndrome); |
29 | #define AW_A10_SDRAM_BASE 0x40000000 | 29 | } |
30 | 30 | ||
31 | #define TYPE_AW_A10 "allwinner-a10" | 31 | - if (arm_is_psci_call(cpu, cs->exception_index)) { |
32 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | 32 | + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { |
33 | index XXXXXXX..XXXXXXX 100644 | 33 | arm_handle_psci_call(cpu); |
34 | --- a/hw/arm/allwinner-a10.c | 34 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); |
35 | +++ b/hw/arm/allwinner-a10.c | 35 | return; |
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #include "hw/misc/unimp.h" | ||
38 | #include "sysemu/sysemu.h" | ||
39 | |||
40 | +#define AW_A10_PIC_REG_BASE 0x01c20400 | ||
41 | +#define AW_A10_PIT_REG_BASE 0x01c20c00 | ||
42 | +#define AW_A10_UART0_REG_BASE 0x01c28000 | ||
43 | +#define AW_A10_EMAC_BASE 0x01c0b000 | ||
44 | +#define AW_A10_SATA_BASE 0x01c18000 | ||
45 | + | ||
46 | static void aw_a10_init(Object *obj) | ||
47 | { | ||
48 | AwA10State *s = AW_A10(obj); | ||
49 | -- | 36 | -- |
50 | 2.20.1 | 37 | 2.34.1 |
51 | 38 | ||
52 | 39 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | The kernel image and DeviceTree blob are built by the Armbian | 3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
4 | project (based on Debian): | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | https://docs.armbian.com/Developer-Guide_Build-Preparation/ | 5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 | 6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
7 | The cpio image used comes from the linux-build-test project: | ||
8 | https://github.com/groeck/linux-build-test | ||
9 | |||
10 | If ARM is a target being built, "make check-acceptance" will | ||
11 | automatically include this test by the use of the "arch:arm" tags. | ||
12 | |||
13 | Alternatively, this test can be run using: | ||
14 | |||
15 | $ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py | ||
16 | console: Uncompressing Linux... done, booting the kernel. | ||
17 | console: Booting Linux on physical CPU 0x0 | ||
18 | console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 | ||
19 | [...] | ||
20 | console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4 | ||
21 | console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit | ||
22 | console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps 0x1 impl platform mode | ||
23 | console: ahci-sunxi 1c18000.sata: flags: ncq only | ||
24 | console: scsi host0: ahci-sunxi | ||
25 | console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 27 | ||
26 | console: of_cfs_init | ||
27 | console: of_cfs_init: OK | ||
28 | console: vcc3v0: disabling | ||
29 | console: vcc5v0: disabling | ||
30 | console: usb1-vbus: disabling | ||
31 | console: usb2-vbus: disabling | ||
32 | console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) | ||
33 | console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100 | ||
34 | console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32) | ||
35 | console: ata1.00: applying bridge limits | ||
36 | console: ata1.00: configured for UDMA/100 | ||
37 | console: scsi 0:0:0:0: Direct-Access ATA QEMU HARDDISK 2.5+ PQ: 0 ANSI: 5 | ||
38 | console: sd 0:0:0:0: Attached scsi generic sg0 type 0 | ||
39 | console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB) | ||
40 | console: sd 0:0:0:0: [sda] Write Protect is off | ||
41 | console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA | ||
42 | console: sd 0:0:0:0: [sda] Attached SCSI disk | ||
43 | console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem | ||
44 | console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null) | ||
45 | console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0. | ||
46 | [...] | ||
47 | console: cat /proc/partitions | ||
48 | console: / # cat /proc/partitions | ||
49 | console: major minor #blocks name | ||
50 | console: 1 0 4096 ram0 | ||
51 | console: 1 1 4096 ram1 | ||
52 | console: 1 2 4096 ram2 | ||
53 | console: 1 3 4096 ram3 | ||
54 | console: 8 0 20480 sda | ||
55 | console: reboot | ||
56 | console: / # reboot | ||
57 | [...] | ||
58 | console: sd 0:0:0:0: [sda] Synchronizing SCSI cache | ||
59 | console: reboot: Restarting system | ||
60 | PASS (48.39 s) | ||
61 | |||
62 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
63 | Message-id: 20191230110953.25496-3-f4bug@amsat.org | ||
64 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
65 | --- | 8 | --- |
66 | tests/acceptance/boot_linux_console.py | 44 ++++++++++++++++++++++++++ | 9 | target/arm/helper.c | 12 +++++++----- |
67 | 1 file changed, 44 insertions(+) | 10 | 1 file changed, 7 insertions(+), 5 deletions(-) |
68 | 11 | ||
69 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
70 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
71 | --- a/tests/acceptance/boot_linux_console.py | 14 | --- a/target/arm/helper.c |
72 | +++ b/tests/acceptance/boot_linux_console.py | 15 | +++ b/target/arm/helper.c |
73 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | 16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
74 | exec_command_and_wait_for_pattern(self, 'reboot', | 17 | unsigned int cur_el = arm_current_el(env); |
75 | 'reboot: Restarting system') | 18 | int rt; |
76 | 19 | ||
77 | + def test_arm_cubieboard_sata(self): | 20 | - /* |
78 | + """ | 21 | - * Note that new_el can never be 0. If cur_el is 0, then |
79 | + :avocado: tags=arch:arm | 22 | - * el0_a64 is is_a64(), else el0_a64 is ignored. |
80 | + :avocado: tags=machine:cubieboard | 23 | - */ |
81 | + """ | 24 | - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
82 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | 25 | + if (tcg_enabled()) { |
83 | + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') | 26 | + /* |
84 | + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' | 27 | + * Note that new_el can never be 0. If cur_el is 0, then |
85 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | 28 | + * el0_a64 is is_a64(), else el0_a64 is ignored. |
86 | + kernel_path = self.extract_from_deb(deb_path, | 29 | + */ |
87 | + '/boot/vmlinuz-4.20.7-sunxi') | 30 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
88 | + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb' | 31 | + } |
89 | + dtb_path = self.extract_from_deb(deb_path, dtb_path) | 32 | |
90 | + rootfs_url = ('https://github.com/groeck/linux-build-test/raw/' | 33 | if (cur_el < new_el) { |
91 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | 34 | /* |
92 | + 'arm/rootfs-armv5.ext2.gz') | ||
93 | + rootfs_hash = '093e89d2b4d982234bf528bc9fb2f2f17a9d1f93' | ||
94 | + rootfs_path_gz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash) | ||
95 | + rootfs_path = os.path.join(self.workdir, 'rootfs.cpio') | ||
96 | + archive.gzip_uncompress(rootfs_path_gz, rootfs_path) | ||
97 | + | ||
98 | + self.vm.set_console() | ||
99 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | ||
100 | + 'console=ttyS0,115200 ' | ||
101 | + 'usbcore.nousb ' | ||
102 | + 'root=/dev/sda ro ' | ||
103 | + 'panic=-1 noreboot') | ||
104 | + self.vm.add_args('-kernel', kernel_path, | ||
105 | + '-dtb', dtb_path, | ||
106 | + '-drive', 'if=none,format=raw,id=disk0,file=' | ||
107 | + + rootfs_path, | ||
108 | + '-device', 'ide-hd,bus=ide.0,drive=disk0', | ||
109 | + '-append', kernel_command_line, | ||
110 | + '-no-reboot') | ||
111 | + self.vm.launch() | ||
112 | + self.wait_for_console_pattern('Boot successful.') | ||
113 | + | ||
114 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | ||
115 | + 'Allwinner sun4i/sun5i') | ||
116 | + exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', | ||
117 | + 'sda') | ||
118 | + exec_command_and_wait_for_pattern(self, 'reboot', | ||
119 | + 'reboot: Restarting system') | ||
120 | + | ||
121 | def test_s390x_s390_ccw_virtio(self): | ||
122 | """ | ||
123 | :avocado: tags=arch:s390x | ||
124 | -- | 35 | -- |
125 | 2.20.1 | 36 | 2.34.1 |
126 | 37 | ||
127 | 38 | diff view generated by jsdifflib |
1 | From: Jeff Kubascik <jeff.kubascik@dornerworks.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | The wfi instruction can be configured to be trapped by a higher exception | 3 | Move this earlier to make the next patch diff cleaner. While here |
4 | level, such as the EL2 hypervisor. When the instruction is trapped, the | 4 | update the comment slightly to not give the impression that the |
5 | program counter should contain the address of the wfi instruction that | 5 | misalignment affects only TCG. |
6 | caused the exception. The program counter is adjusted for this in the wfi op | ||
7 | helper function. | ||
8 | 6 | ||
9 | However, this correction is done to env->pc, which only applies to AArch64 | ||
10 | mode. For AArch32, the program counter is stored in env->regs[15]. This | ||
11 | adds an if-else statement to modify the correct program counter location | ||
12 | based on the the current CPU mode. | ||
13 | |||
14 | Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com> | ||
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 12 | --- |
18 | target/arm/op_helper.c | 7 ++++++- | 13 | target/arm/machine.c | 18 +++++++++--------- |
19 | 1 file changed, 6 insertions(+), 1 deletion(-) | 14 | 1 file changed, 9 insertions(+), 9 deletions(-) |
20 | 15 | ||
21 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | 16 | diff --git a/target/arm/machine.c b/target/arm/machine.c |
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/op_helper.c | 18 | --- a/target/arm/machine.c |
24 | +++ b/target/arm/op_helper.c | 19 | +++ b/target/arm/machine.c |
25 | @@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) | 20 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
21 | } | ||
26 | } | 22 | } |
27 | 23 | ||
28 | if (target_el) { | 24 | + /* |
29 | - env->pc -= insn_len; | 25 | + * Misaligned thumb pc is architecturally impossible. Fail the |
30 | + if (env->aarch64) { | 26 | + * incoming migration. For TCG it would trigger the assert in |
31 | + env->pc -= insn_len; | 27 | + * thumb_tr_translate_insn(). |
32 | + } else { | 28 | + */ |
33 | + env->regs[15] -= insn_len; | 29 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { |
34 | + } | 30 | + return -1; |
31 | + } | ||
35 | + | 32 | + |
36 | raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2), | 33 | hw_breakpoint_update_all(cpu); |
37 | target_el); | 34 | hw_watchpoint_update_all(cpu); |
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | ||
37 | } | ||
38 | } | ||
39 | |||
40 | - /* | ||
41 | - * Misaligned thumb pc is architecturally impossible. | ||
42 | - * We have an assert in thumb_tr_translate_insn to verify this. | ||
43 | - * Fail an incoming migrate to avoid this assert. | ||
44 | - */ | ||
45 | - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
46 | - return -1; | ||
47 | - } | ||
48 | - | ||
49 | if (!kvm_enabled()) { | ||
50 | pmu_op_finish(&cpu->env); | ||
38 | } | 51 | } |
39 | -- | 52 | -- |
40 | 2.20.1 | 53 | 2.34.1 |
41 | 54 | ||
42 | 55 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Fabiano Rosas <farosas@suse.de> | |
2 | |||
3 | Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have | ||
4 | a cpregs.h header which is more suitable for this code. | ||
5 | |||
6 | Code moved verbatim. | ||
7 | |||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ | ||
15 | target/arm/cpu.h | 91 ----------------------------------------- | ||
16 | 2 files changed, 98 insertions(+), 91 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpregs.h | ||
21 | +++ b/target/arm/cpregs.h | ||
22 | @@ -XXX,XX +XXX,XX @@ enum { | ||
23 | ARM_CP_SME = 1 << 19, | ||
24 | }; | ||
25 | |||
26 | +/* | ||
27 | + * Interface for defining coprocessor registers. | ||
28 | + * Registers are defined in tables of arm_cp_reginfo structs | ||
29 | + * which are passed to define_arm_cp_regs(). | ||
30 | + */ | ||
31 | + | ||
32 | +/* | ||
33 | + * When looking up a coprocessor register we look for it | ||
34 | + * via an integer which encodes all of: | ||
35 | + * coprocessor number | ||
36 | + * Crn, Crm, opc1, opc2 fields | ||
37 | + * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
38 | + * or via MRRC/MCRR?) | ||
39 | + * non-secure/secure bank (AArch32 only) | ||
40 | + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
41 | + * (In this case crn and opc2 should be zero.) | ||
42 | + * For AArch64, there is no 32/64 bit size distinction; | ||
43 | + * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
44 | + * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
45 | + * to be easy to convert to and from the KVM encodings, and also | ||
46 | + * so that the hashtable can contain both AArch32 and AArch64 | ||
47 | + * registers (to allow for interprocessing where we might run | ||
48 | + * 32 bit code on a 64 bit core). | ||
49 | + */ | ||
50 | +/* | ||
51 | + * This bit is private to our hashtable cpreg; in KVM register | ||
52 | + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
53 | + * in the upper bits of the 64 bit ID. | ||
54 | + */ | ||
55 | +#define CP_REG_AA64_SHIFT 28 | ||
56 | +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
57 | + | ||
58 | +/* | ||
59 | + * To enable banking of coprocessor registers depending on ns-bit we | ||
60 | + * add a bit to distinguish between secure and non-secure cpregs in the | ||
61 | + * hashtable. | ||
62 | + */ | ||
63 | +#define CP_REG_NS_SHIFT 29 | ||
64 | +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
65 | + | ||
66 | +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
67 | + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
68 | + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
69 | + | ||
70 | +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
71 | + (CP_REG_AA64_MASK | \ | ||
72 | + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
73 | + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
74 | + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
75 | + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
76 | + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
77 | + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
78 | + | ||
79 | +/* | ||
80 | + * Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
81 | + * version used as a key for the coprocessor register hashtable | ||
82 | + */ | ||
83 | +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
84 | +{ | ||
85 | + uint32_t cpregid = kvmid; | ||
86 | + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
87 | + cpregid |= CP_REG_AA64_MASK; | ||
88 | + } else { | ||
89 | + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
90 | + cpregid |= (1 << 15); | ||
91 | + } | ||
92 | + | ||
93 | + /* | ||
94 | + * KVM is always non-secure so add the NS flag on AArch32 register | ||
95 | + * entries. | ||
96 | + */ | ||
97 | + cpregid |= 1 << CP_REG_NS_SHIFT; | ||
98 | + } | ||
99 | + return cpregid; | ||
100 | +} | ||
101 | + | ||
102 | +/* | ||
103 | + * Convert a truncated 32 bit hashtable key into the full | ||
104 | + * 64 bit KVM register ID. | ||
105 | + */ | ||
106 | +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
107 | +{ | ||
108 | + uint64_t kvmid; | ||
109 | + | ||
110 | + if (cpregid & CP_REG_AA64_MASK) { | ||
111 | + kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
112 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
113 | + } else { | ||
114 | + kvmid = cpregid & ~(1 << 15); | ||
115 | + if (cpregid & (1 << 15)) { | ||
116 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
117 | + } else { | ||
118 | + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
119 | + } | ||
120 | + } | ||
121 | + return kvmid; | ||
122 | +} | ||
123 | + | ||
124 | /* | ||
125 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
126 | * the AArch32 and AArch64 execution states this register is visible in. | ||
127 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/cpu.h | ||
130 | +++ b/target/arm/cpu.h | ||
131 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
132 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
133 | uint32_t cur_el, bool secure); | ||
134 | |||
135 | -/* Interface for defining coprocessor registers. | ||
136 | - * Registers are defined in tables of arm_cp_reginfo structs | ||
137 | - * which are passed to define_arm_cp_regs(). | ||
138 | - */ | ||
139 | - | ||
140 | -/* When looking up a coprocessor register we look for it | ||
141 | - * via an integer which encodes all of: | ||
142 | - * coprocessor number | ||
143 | - * Crn, Crm, opc1, opc2 fields | ||
144 | - * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
145 | - * or via MRRC/MCRR?) | ||
146 | - * non-secure/secure bank (AArch32 only) | ||
147 | - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
148 | - * (In this case crn and opc2 should be zero.) | ||
149 | - * For AArch64, there is no 32/64 bit size distinction; | ||
150 | - * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
151 | - * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
152 | - * to be easy to convert to and from the KVM encodings, and also | ||
153 | - * so that the hashtable can contain both AArch32 and AArch64 | ||
154 | - * registers (to allow for interprocessing where we might run | ||
155 | - * 32 bit code on a 64 bit core). | ||
156 | - */ | ||
157 | -/* This bit is private to our hashtable cpreg; in KVM register | ||
158 | - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
159 | - * in the upper bits of the 64 bit ID. | ||
160 | - */ | ||
161 | -#define CP_REG_AA64_SHIFT 28 | ||
162 | -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
163 | - | ||
164 | -/* To enable banking of coprocessor registers depending on ns-bit we | ||
165 | - * add a bit to distinguish between secure and non-secure cpregs in the | ||
166 | - * hashtable. | ||
167 | - */ | ||
168 | -#define CP_REG_NS_SHIFT 29 | ||
169 | -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
170 | - | ||
171 | -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
172 | - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
173 | - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
174 | - | ||
175 | -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
176 | - (CP_REG_AA64_MASK | \ | ||
177 | - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
178 | - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
179 | - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
180 | - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
181 | - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
182 | - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
183 | - | ||
184 | -/* Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
185 | - * version used as a key for the coprocessor register hashtable | ||
186 | - */ | ||
187 | -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
188 | -{ | ||
189 | - uint32_t cpregid = kvmid; | ||
190 | - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
191 | - cpregid |= CP_REG_AA64_MASK; | ||
192 | - } else { | ||
193 | - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
194 | - cpregid |= (1 << 15); | ||
195 | - } | ||
196 | - | ||
197 | - /* KVM is always non-secure so add the NS flag on AArch32 register | ||
198 | - * entries. | ||
199 | - */ | ||
200 | - cpregid |= 1 << CP_REG_NS_SHIFT; | ||
201 | - } | ||
202 | - return cpregid; | ||
203 | -} | ||
204 | - | ||
205 | -/* Convert a truncated 32 bit hashtable key into the full | ||
206 | - * 64 bit KVM register ID. | ||
207 | - */ | ||
208 | -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
209 | -{ | ||
210 | - uint64_t kvmid; | ||
211 | - | ||
212 | - if (cpregid & CP_REG_AA64_MASK) { | ||
213 | - kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
214 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
215 | - } else { | ||
216 | - kvmid = cpregid & ~(1 << 15); | ||
217 | - if (cpregid & (1 << 15)) { | ||
218 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
219 | - } else { | ||
220 | - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
221 | - } | ||
222 | - } | ||
223 | - return kvmid; | ||
224 | -} | ||
225 | - | ||
226 | /* Return the highest implemented Exception Level */ | ||
227 | static inline int arm_highest_el(CPUARMState *env) | ||
228 | { | ||
229 | -- | ||
230 | 2.34.1 | ||
231 | |||
232 | diff view generated by jsdifflib |
1 | From: Jeff Kubascik <jeff.kubascik@dornerworks.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the | 3 | If a test was tagged with the "accel" tag and the specified |
4 | register activates the highest priority pending interrupt and provides its | 4 | accelerator it not present in the qemu binary, cancel the test. |
5 | interrupt ID. Activating an interrupt can change the CPU's virtual interrupt | ||
6 | state - this change makes sure the virtual irq state is updated. | ||
7 | 5 | ||
8 | Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com> | 6 | We can now write tests without explicit calls to require_accelerator, |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | just the tag is enough. |
10 | Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com | 8 | |
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | hw/intc/arm_gicv3_cpuif.c | 3 +++ | 14 | tests/avocado/avocado_qemu/__init__.py | 4 ++++ |
14 | 1 file changed, 3 insertions(+) | 15 | 1 file changed, 4 insertions(+) |
15 | 16 | ||
16 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | 17 | diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/intc/arm_gicv3_cpuif.c | 19 | --- a/tests/avocado/avocado_qemu/__init__.py |
19 | +++ b/hw/intc/arm_gicv3_cpuif.c | 20 | +++ b/tests/avocado/avocado_qemu/__init__.py |
20 | @@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) | 21 | @@ -XXX,XX +XXX,XX @@ def setUp(self): |
21 | 22 | ||
22 | trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, | 23 | super().setUp('qemu-system-') |
23 | gicv3_redist_affid(cs), intid); | 24 | |
25 | + accel_required = self._get_unique_tag_val('accel') | ||
26 | + if accel_required: | ||
27 | + self.require_accelerator(accel_required) | ||
24 | + | 28 | + |
25 | + gicv3_cpuif_virt_update(cs); | 29 | self.machine = self.params.get('machine', |
26 | + | 30 | default=self._get_unique_tag_val('machine')) |
27 | return intid; | ||
28 | } | ||
29 | 31 | ||
30 | -- | 32 | -- |
31 | 2.20.1 | 33 | 2.34.1 |
32 | 34 | ||
33 | 35 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | This test boots a Linux kernel on a CubieBoard and verify | 3 | This allows the test to be skipped when TCG is not present in the QEMU |
4 | the serial output is working. | 4 | binary. |
5 | 5 | ||
6 | The kernel image and DeviceTree blob are built by the Armbian | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
7 | project (based on Debian): | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | https://docs.armbian.com/Developer-Guide_Build-Preparation/ | 8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | |||
10 | The cpio image used comes from the linux-build-test project: | ||
11 | https://github.com/groeck/linux-build-test | ||
12 | |||
13 | If ARM is a target being built, "make check-acceptance" will | ||
14 | automatically include this test by the use of the "arch:arm" tags. | ||
15 | |||
16 | Alternatively, this test can be run using: | ||
17 | |||
18 | $ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py | ||
19 | console: Uncompressing Linux... done, booting the kernel. | ||
20 | console: Booting Linux on physical CPU 0x0 | ||
21 | console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019 | ||
22 | console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=50c5387d | ||
23 | console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache | ||
24 | console: OF: fdt: Machine model: Cubietech Cubieboard | ||
25 | [...] | ||
26 | console: Boot successful. | ||
27 | console: cat /proc/cpuinfo | ||
28 | console: / # cat /proc/cpuinfo | ||
29 | console: processor : 0 | ||
30 | console: model name : ARMv7 Processor rev 0 (v7l) | ||
31 | console: BogoMIPS : 832.51 | ||
32 | [...] | ||
33 | console: Hardware : Allwinner sun4i/sun5i Families | ||
34 | console: Revision : 0000 | ||
35 | console: Serial : 0000000000000000 | ||
36 | console: cat /proc/iomem | ||
37 | console: / # cat /proc/iomem | ||
38 | console: 01c00000-01c0002f : system-control@1c00000 | ||
39 | console: 01c02000-01c02fff : dma-controller@1c02000 | ||
40 | console: 01c05000-01c05fff : spi@1c05000 | ||
41 | console: 01c0b080-01c0b093 : mdio@1c0b080 | ||
42 | console: 01c0c000-01c0cfff : lcd-controller@1c0c000 | ||
43 | console: 01c0d000-01c0dfff : lcd-controller@1c0d000 | ||
44 | console: 01c0f000-01c0ffff : mmc@1c0f000 | ||
45 | [...] | ||
46 | PASS (54.35 s) | ||
47 | |||
48 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
49 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
50 | Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
51 | Message-id: 20191230110953.25496-2-f4bug@amsat.org | ||
52 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
53 | --- | 10 | --- |
54 | tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++ | 11 | tests/avocado/boot_linux_console.py | 1 + |
55 | 1 file changed, 41 insertions(+) | 12 | tests/avocado/reverse_debugging.py | 8 ++++++++ |
13 | 2 files changed, 9 insertions(+) | ||
56 | 14 | ||
57 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | 15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py |
58 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
59 | --- a/tests/acceptance/boot_linux_console.py | 17 | --- a/tests/avocado/boot_linux_console.py |
60 | +++ b/tests/acceptance/boot_linux_console.py | 18 | +++ b/tests/avocado/boot_linux_console.py |
61 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): | 19 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self): |
62 | self.wait_for_console_pattern('Boot successful.') | 20 | |
63 | # TODO user command, for now the uart is stuck | 21 | def test_aarch64_raspi3_atf(self): |
64 | 22 | """ | |
65 | + def test_arm_cubieboard_initrd(self): | 23 | + :avocado: tags=accel:tcg |
66 | + """ | 24 | :avocado: tags=arch:aarch64 |
67 | + :avocado: tags=arch:arm | 25 | :avocado: tags=machine:raspi3b |
68 | + :avocado: tags=machine:cubieboard | 26 | :avocado: tags=cpu:cortex-a53 |
69 | + """ | 27 | diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py |
70 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | 28 | index XXXXXXX..XXXXXXX 100644 |
71 | + 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb') | 29 | --- a/tests/avocado/reverse_debugging.py |
72 | + deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315' | 30 | +++ b/tests/avocado/reverse_debugging.py |
73 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | 31 | @@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None): |
74 | + kernel_path = self.extract_from_deb(deb_path, | 32 | vm.shutdown() |
75 | + '/boot/vmlinuz-4.20.7-sunxi') | 33 | |
76 | + dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb' | 34 | class ReverseDebugging_X86_64(ReverseDebugging): |
77 | + dtb_path = self.extract_from_deb(deb_path, dtb_path) | 35 | + """ |
78 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | 36 | + :avocado: tags=accel:tcg |
79 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | 37 | + """ |
80 | + 'arm/rootfs-armv5.cpio.gz') | ||
81 | + initrd_hash = '2b50f1873e113523967806f4da2afe385462ff9b' | ||
82 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) | ||
83 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') | ||
84 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) | ||
85 | + | 38 | + |
86 | + self.vm.set_console() | 39 | REG_PC = 0x10 |
87 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | 40 | REG_CS = 0x12 |
88 | + 'console=ttyS0,115200 ' | 41 | def get_pc(self, g): |
89 | + 'usbcore.nousb ' | 42 | @@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self): |
90 | + 'panic=-1 noreboot') | 43 | self.reverse_debugging() |
91 | + self.vm.add_args('-kernel', kernel_path, | 44 | |
92 | + '-dtb', dtb_path, | 45 | class ReverseDebugging_AArch64(ReverseDebugging): |
93 | + '-initrd', initrd_path, | 46 | + """ |
94 | + '-append', kernel_command_line, | 47 | + :avocado: tags=accel:tcg |
95 | + '-no-reboot') | 48 | + """ |
96 | + self.vm.launch() | ||
97 | + self.wait_for_console_pattern('Boot successful.') | ||
98 | + | 49 | + |
99 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | 50 | REG_PC = 32 |
100 | + 'Allwinner sun4i/sun5i') | 51 | |
101 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | 52 | # unidentified gitlab timeout problem |
102 | + 'system-control@1c00000') | ||
103 | + exec_command_and_wait_for_pattern(self, 'reboot', | ||
104 | + 'reboot: Restarting system') | ||
105 | + | ||
106 | def test_s390x_s390_ccw_virtio(self): | ||
107 | """ | ||
108 | :avocado: tags=arch:s390x | ||
109 | -- | 53 | -- |
110 | 2.20.1 | 54 | 2.34.1 |
111 | 55 | ||
112 | 56 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a | ||
4 | KVM-only build the 'max' cpu. | ||
5 | |||
6 | Note that we cannot use 'host' here because the qtests can run without | ||
7 | any other accelerator (than qtest) and 'host' depends on KVM being | ||
8 | enabled. | ||
9 | |||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/arm/virt.c | 4 ++++ | ||
16 | 1 file changed, 4 insertions(+) | ||
17 | |||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/arm/virt.c | ||
21 | +++ b/hw/arm/virt.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
23 | mc->minimum_page_bits = 12; | ||
24 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; | ||
25 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | ||
26 | +#ifdef CONFIG_TCG | ||
27 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | ||
28 | +#else | ||
29 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); | ||
30 | +#endif | ||
31 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; | ||
32 | mc->kvm_type = virt_kvm_type; | ||
33 | assert(!mc->get_hotplug_handler); | ||
34 | -- | ||
35 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- | ||
9 | 1 file changed, 18 insertions(+), 10 deletions(-) | ||
10 | |||
11 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tests/qtest/arm-cpu-features.c | ||
14 | +++ b/tests/qtest/arm-cpu-features.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #define SVE_MAX_VQ 16 | ||
17 | |||
18 | #define MACHINE "-machine virt,gic-version=max -accel tcg " | ||
19 | -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " | ||
20 | +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " | ||
21 | #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ | ||
22 | " 'arguments': { 'type': 'full', " | ||
23 | #define QUERY_TAIL "}}" | ||
24 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | ||
25 | { | ||
26 | g_test_init(&argc, &argv, NULL); | ||
27 | |||
28 | - qtest_add_data_func("/arm/query-cpu-model-expansion", | ||
29 | - NULL, test_query_cpu_model_expansion); | ||
30 | + if (qtest_has_accel("tcg")) { | ||
31 | + qtest_add_data_func("/arm/query-cpu-model-expansion", | ||
32 | + NULL, test_query_cpu_model_expansion); | ||
33 | + } | ||
34 | + | ||
35 | + if (!g_str_equal(qtest_get_arch(), "aarch64")) { | ||
36 | + goto out; | ||
37 | + } | ||
38 | |||
39 | /* | ||
40 | * For now we only run KVM specific tests with AArch64 QEMU in | ||
41 | * order avoid attempting to run an AArch32 QEMU with KVM on | ||
42 | * AArch64 hosts. That won't work and isn't easy to detect. | ||
43 | */ | ||
44 | - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { | ||
45 | + if (qtest_has_accel("kvm")) { | ||
46 | /* | ||
47 | * This tests target the 'host' CPU type, so register it only if | ||
48 | * KVM is available. | ||
49 | */ | ||
50 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", | ||
51 | NULL, test_query_cpu_model_expansion_kvm); | ||
52 | - } | ||
53 | |||
54 | - if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
55 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
56 | - NULL, sve_tests_sve_max_vq_8); | ||
57 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
58 | - NULL, sve_tests_sve_off); | ||
59 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", | ||
60 | NULL, sve_tests_sve_off_kvm); | ||
61 | } | ||
62 | |||
63 | + if (qtest_has_accel("tcg")) { | ||
64 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
65 | + NULL, sve_tests_sve_max_vq_8); | ||
66 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
67 | + NULL, sve_tests_sve_off); | ||
68 | + } | ||
69 | + | ||
70 | +out: | ||
71 | return g_test_run(); | ||
72 | } | ||
73 | -- | ||
74 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | These tests set -accel tcg, so restrict them to when TCG is present. | ||
4 | |||
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
6 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | tests/qtest/meson.build | 4 ++-- | ||
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/tests/qtest/meson.build | ||
16 | +++ b/tests/qtest/meson.build | ||
17 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ | ||
18 | # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional | ||
19 | qtests_aarch64 = \ | ||
20 | (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ | ||
21 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ | ||
22 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ | ||
23 | + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ | ||
24 | + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ | ||
25 | (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ | ||
26 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ | ||
27 | ['arm-cpu-features', | ||
28 | -- | ||
29 | 2.34.1 | diff view generated by jsdifflib |