[PULL 00/15] target-arm queue
[PULL 00/24] target-arm queue
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Latest arm queue, a mixed bag of features and bug fixes.
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The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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thanks
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
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-- PMM
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The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:
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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (2020-01-17 12:13:17 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200117-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
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target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +0000)
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target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Add model of the Netduino Plus 2 board
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target-arm queue:
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Some allwinner-a10 code cleanup
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* more MVE instructions
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New test cases for cubieboard
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* hw/gpio/gpio_pwr: use shutdown function for reboot
22
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
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* target/arm: Check NaN mode before silencing NaN
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i.MX: add an emulation for RNGC device
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* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
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target/arm: adjust program counter for wfi exception in AArch32
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* hw/arm: Add basic power management to raspi.
25
arm/gicv3: update virtual irq state after IAR register read
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* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
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Set IL bit correctly for syndrome information for data aborts
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alistair Francis (4):
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Joe Komlodi (1):
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hw/misc: Add the STM32F4xx Sysconfig device
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target/arm: Check NaN mode before silencing NaN
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hw/misc: Add the STM32F4xx EXTI device
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hw/arm: Add the STM32F4xx SoC
33
hw/arm: Add the Netduino Plus 2
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35
Jeff Kubascik (3):
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Maxim Uvarov (1):
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target/arm: adjust program counter for wfi exception in AArch32
27
hw/gpio/gpio_pwr: use shutdown function for reboot
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arm/gicv3: update virtual irq state after IAR register read
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target/arm: Return correct IL bit in merge_syn_data_abort
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40
Martin Kaiser (1):
29
Nolan Leake (1):
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i.MX: add an emulation for RNGC
30
hw/arm: Add basic power management to raspi.
42
31
43
Masahiro Yamada (1):
32
Patrick Venture (2):
44
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
33
docs/system/arm: Add quanta-q7l1-bmc reference
34
docs/system/arm: Add quanta-gbs-bmc reference
45
35
46
Philippe Mathieu-Daudé (5):
36
Peter Maydell (18):
47
tests/boot_linux_console: Add initrd test for the CubieBoard
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
48
tests/boot_linux_console: Add a SD card test for the CubieBoard
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
49
hw/arm/allwinner-a10: Move SoC definitions out of header
39
target/arm: Make asimd_imm_const() public
50
hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
40
target/arm: Use asimd_imm_const for A64 decode
51
hw/arm/allwinner-a10: Remove local qemu_irq variables
41
target/arm: Use dup_const() instead of bitfield_replicate()
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target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
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target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
52
55
53
Richard Henderson (1):
56
Philippe Mathieu-Daudé (1):
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target/arm: Set ISSIs16Bit in make_issinfo
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tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
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58
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hw/arm/Makefile.objs | 2 +
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docs/system/arm/aspeed.rst | 1 +
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hw/misc/Makefile.objs | 3 +
60
docs/system/arm/nuvoton.rst | 5 +-
58
include/hw/arm/allwinner-a10.h | 7 -
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
59
include/hw/arm/fsl-imx25.h | 5 +
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
60
include/hw/arm/stm32f405_soc.h | 73 ++++++++
63
target/arm/helper-mve.h | 108 +++++++
61
include/hw/misc/imx_rngc.h | 35 ++++
64
target/arm/translate.h | 41 +++
62
include/hw/misc/stm32f4xx_exti.h | 60 +++++++
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target/arm/mve.decode | 177 ++++++++++-
63
include/hw/misc/stm32f4xx_syscfg.h | 61 +++++++
66
target/arm/t32.decode | 71 ++++-
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hw/arm/allwinner-a10.c | 39 +++--
67
hw/arm/bcm2835_peripherals.c | 13 +-
65
hw/arm/fsl-imx25.c | 11 ++
68
hw/gpio/gpio_pwr.c | 2 +-
66
hw/arm/netduinoplus2.c | 52 ++++++
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
67
hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++
70
target/arm/helper-a64.c | 12 +-
68
hw/intc/arm_gicv3_cpuif.c | 3 +
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
69
hw/misc/imx_rngc.c | 278 ++++++++++++++++++++++++++++++
72
target/arm/translate-a64.c | 86 +-----
70
hw/misc/stm32f4xx_exti.c | 188 ++++++++++++++++++++
73
target/arm/translate-mve.c | 261 +++++++++++++++-
71
hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++
74
target/arm/translate-neon.c | 81 -----
72
target/arm/arm-semi.c | 5 +-
75
target/arm/translate.c | 327 +++++++++++++++++++-
73
target/arm/op_helper.c | 7 +-
76
target/arm/vfp_helper.c | 24 +-
74
target/arm/tlb_helper.c | 2 +-
77
hw/misc/meson.build | 1 +
75
target/arm/translate.c | 3 +
78
tests/acceptance/boot_linux_console.py | 43 +++
76
MAINTAINERS | 14 ++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
77
default-configs/arm-softmmu.mak | 1 +
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
78
hw/arm/Kconfig | 10 ++
81
create mode 100644 hw/misc/bcm2835_powermgt.c
79
hw/misc/Kconfig | 6 +
80
hw/misc/trace-events | 11 ++
81
tests/acceptance/boot_linux_console.py | 85 ++++++++++
82
26 files changed, 1405 insertions(+), 29 deletions(-)
83
create mode 100644 include/hw/arm/stm32f405_soc.h
84
create mode 100644 include/hw/misc/imx_rngc.h
85
create mode 100644 include/hw/misc/stm32f4xx_exti.h
86
create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
87
create mode 100644 hw/arm/netduinoplus2.c
88
create mode 100644 hw/arm/stm32f405_soc.c
89
create mode 100644 hw/misc/imx_rngc.c
90
create mode 100644 hw/misc/stm32f4xx_exti.c
91
create mode 100644 hw/misc/stm32f4xx_syscfg.c
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diff view generated by jsdifflib
New patch
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Patrick Venture <venture@google.com>
1
2
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
entry.
5
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20210615192848.1065297-2-venture@google.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ etc.
19
AST2400 SoC based machines :
20
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
23
24
AST2500 SoC based machines :
25
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[PULL 10/15] target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Masahiro Yamada <masahiroy@kernel.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
According to the specification "Semihosting for AArch32 and Aarch64",
3
Add line item reference to quanta-gbs-bmc machine.
4
the SYS_OPEN operation should return:
5
4
6
- A nonzero handle if the call is successful
5
Signed-off-by: Patrick Venture <venture@google.com>
7
- -1 if the call is not successful
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
7
Message-id: 20210615192848.1065297-3-venture@google.com
9
So, it should never return 0.
8
[PMM: fixed underline Sphinx warning]
10
11
Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting
12
code hand out its own file descriptors"), the guest fd matched to the
13
host fd. It returned a nonzero handle on success since the fd 0 is
14
already used for stdin.
15
16
Now that the guest fd is the index of guestfd_array, it starts from 0.
17
18
I noticed this issue particularly because Trusted Firmware-A built with
19
PLAT=qemu is no longer working. Its io_semihosting driver only handles
20
a positive return value as a valid filehandle.
21
22
Basically, there are two ways to fix this:
23
24
- Use (guestfd - 1) as the index of guestfs_arrary. We need to insert
25
increment/decrement to convert the guestfd and the array index back
26
and forth.
27
28
- Keep using guestfd as the index of guestfs_array. The first entry
29
of guestfs_array is left unused.
30
31
I thought the latter is simpler. We end up with wasting a small piece
32
of memory for the unused first entry of guestfd_array, but this is
33
probably not a big deal.
34
35
Fixes: 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting code hand out its own file descriptors")
36
Cc: qemu-stable@nongnu.org
37
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20200109041228.10131-1-masahiroy@kernel.org
40
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
41
---
10
---
42
target/arm/arm-semi.c | 5 +++--
11
docs/system/arm/nuvoton.rst | 5 +++--
43
1 file changed, 3 insertions(+), 2 deletions(-)
12
1 file changed, 3 insertions(+), 2 deletions(-)
44
13
45
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
46
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/arm-semi.c
16
--- a/docs/system/arm/nuvoton.rst
48
+++ b/target/arm/arm-semi.c
17
+++ b/docs/system/arm/nuvoton.rst
49
@@ -XXX,XX +XXX,XX @@ static int alloc_guestfd(void)
18
@@ -XXX,XX +XXX,XX @@
50
guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD));
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
51
}
20
-=====================================================
52
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
53
- for (i = 0; i < guestfd_array->len; i++) {
22
+================================================================
54
+ /* SYS_OPEN should return nonzero handle on success. Start guestfd from 1 */
23
55
+ for (i = 1; i < guestfd_array->len; i++) {
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
56
GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i);
25
designed to be used as Baseboard Management Controllers (BMCs) in various
57
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
58
if (gf->type == GuestFDUnused) {
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
59
@@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd)
28
Hyperscale applications. The following machines are based on this chip :
60
return NULL;
29
61
}
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
62
31
- ``quanta-gsj`` Quanta GSJ server BMC
63
- if (guestfd < 0 || guestfd >= guestfd_array->len) {
32
64
+ if (guestfd <= 0 || guestfd >= guestfd_array->len) {
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
65
return NULL;
66
}
67
68
--
34
--
69
2.20.1
35
2.20.1
70
36
71
37
diff view generated by jsdifflib
[PULL 11/15] i.MX: add an emulation for RNGC
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Martin Kaiser <martin@kaiser.cx>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
Add an emulation for the RNGC random number generator and the compatible
3
This is just enough to make reboot and poweroff work. Works for
4
RNGB variant. These peripherals are included (at least) in imx25 and
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
imx35 chipsets.
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
6
do what linux does for reset.
7
The emulation supports the initial self test, reseeding the prng and
7
8
reading random numbers.
8
The watchdog timer functionality is not yet implemented.
9
9
10
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
18
---
14
hw/misc/Makefile.objs | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
15
include/hw/arm/fsl-imx25.h | 5 +
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
16
include/hw/misc/imx_rngc.h | 35 +++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
17
hw/arm/fsl-imx25.c | 11 ++
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
18
hw/misc/imx_rngc.c | 278 +++++++++++++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
19
5 files changed, 330 insertions(+)
24
5 files changed, 204 insertions(+), 2 deletions(-)
20
create mode 100644 include/hw/misc/imx_rngc.h
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
21
create mode 100644 hw/misc/imx_rngc.c
26
create mode 100644 hw/misc/bcm2835_powermgt.c
22
27
23
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
24
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/misc/Makefile.objs
30
--- a/include/hw/arm/bcm2835_peripherals.h
26
+++ b/hw/misc/Makefile.objs
31
+++ b/include/hw/arm/bcm2835_peripherals.h
27
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o
28
common-obj-$(CONFIG_IMX) += imx2_wdt.o
29
common-obj-$(CONFIG_IMX) += imx7_snvs.o
30
common-obj-$(CONFIG_IMX) += imx7_gpr.o
31
+common-obj-$(CONFIG_IMX) += imx_rngc.o
32
common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
33
common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
34
common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o
35
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/hw/arm/fsl-imx25.h
38
+++ b/include/hw/arm/fsl-imx25.h
39
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
40
#include "hw/timer/imx_gpt.h"
33
#include "hw/misc/bcm2835_mphi.h"
41
#include "hw/timer/imx_epit.h"
34
#include "hw/misc/bcm2835_thermal.h"
42
#include "hw/net/imx_fec.h"
35
#include "hw/misc/bcm2835_cprman.h"
43
+#include "hw/misc/imx_rngc.h"
36
+#include "hw/misc/bcm2835_powermgt.h"
44
#include "hw/i2c/imx_i2c.h"
37
#include "hw/sd/sdhci.h"
45
#include "hw/gpio/imx_gpio.h"
38
#include "hw/sd/bcm2835_sdhost.h"
46
#include "exec/memory.h"
39
#include "hw/gpio/bcm2835_gpio.h"
47
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
48
IMXGPTState gpt[FSL_IMX25_NUM_GPTS];
41
BCM2835MphiState mphi;
49
IMXEPITState epit[FSL_IMX25_NUM_EPITS];
42
UnimplementedDeviceState txp;
50
IMXFECState fec;
43
UnimplementedDeviceState armtmr;
51
+ IMXRNGCState rngc;
44
- UnimplementedDeviceState powermgt;
52
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
45
+ BCM2835PowerMgtState powermgt;
53
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
46
BCM2835CprmanState cprman;
54
MemoryRegion rom[2];
47
PL011State uart0;
55
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
48
BCM2835AuxState aux;
56
#define FSL_IMX25_GPIO4_SIZE 0x4000
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
57
#define FSL_IMX25_GPIO3_ADDR 0x53FA4000
58
#define FSL_IMX25_GPIO3_SIZE 0x4000
59
+#define FSL_IMX25_RNGC_ADDR 0x53FB0000
60
+#define FSL_IMX25_RNGC_SIZE 0x4000
61
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
62
#define FSL_IMX25_GPIO1_SIZE 0x4000
63
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
64
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
65
#define FSL_IMX25_EPIT1_IRQ 28
66
#define FSL_IMX25_EPIT2_IRQ 27
67
#define FSL_IMX25_FEC_IRQ 57
68
+#define FSL_IMX25_RNGC_IRQ 22
69
#define FSL_IMX25_I2C1_IRQ 3
70
#define FSL_IMX25_I2C2_IRQ 4
71
#define FSL_IMX25_I2C3_IRQ 10
72
diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h
73
new file mode 100644
50
new file mode 100644
74
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
75
--- /dev/null
52
--- /dev/null
76
+++ b/include/hw/misc/imx_rngc.h
53
+++ b/include/hw/misc/bcm2835_powermgt.h
77
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
78
+/*
55
+/*
79
+ * Freescale i.MX RNGC emulation
56
+ * BCM2835 Power Management emulation
80
+ *
57
+ *
81
+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
82
+ *
60
+ *
83
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
84
+ * See the COPYING file in the top-level directory.
62
+ * See the COPYING file in the top-level directory.
85
+ */
63
+ */
86
+
64
+
87
+#ifndef IMX_RNGC_H
65
+#ifndef BCM2835_POWERMGT_H
88
+#define IMX_RNGC_H
66
+#define BCM2835_POWERMGT_H
89
+
67
+
90
+#include "hw/sysbus.h"
68
+#include "hw/sysbus.h"
91
+
69
+#include "qom/object.h"
92
+#define TYPE_IMX_RNGC "imx.rngc"
70
+
93
+#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC)
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
94
+
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
95
+typedef struct IMXRNGCState {
73
+
96
+ /*< private >*/
74
+struct BCM2835PowerMgtState {
97
+ SysBusDevice parent_obj;
75
+ SysBusDevice busdev;
98
+
76
+ MemoryRegion iomem;
99
+ /*< public >*/
77
+
100
+ MemoryRegion iomem;
78
+ uint32_t rstc;
101
+
79
+ uint32_t rsts;
102
+ uint8_t op_self_test;
80
+ uint32_t wdog;
103
+ uint8_t op_seed;
81
+};
104
+ uint8_t mask;
82
+
105
+ bool auto_seed;
83
+#endif
106
+
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
107
+ QEMUBH *self_test_bh;
108
+ QEMUBH *seed_bh;
109
+ qemu_irq irq;
110
+} IMXRNGCState;
111
+
112
+#endif /* IMX_RNGC_H */
113
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
114
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
115
--- a/hw/arm/fsl-imx25.c
86
--- a/hw/arm/bcm2835_peripherals.c
116
+++ b/hw/arm/fsl-imx25.c
87
+++ b/hw/arm/bcm2835_peripherals.c
117
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
118
89
119
sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
120
91
OBJECT(&s->gpu_bus_mr));
121
+ sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
92
+
122
+ TYPE_IMX_RNGC);
93
+ /* Power Management */
123
+
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
124
for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
95
+ TYPE_BCM2835_POWERMGT);
125
sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
96
}
126
TYPE_IMX_I2C);
97
127
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
128
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
129
qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
130
101
INTERRUPT_USB));
131
+ object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
102
132
+ if (err) {
103
+ /* Power Management */
133
+ error_propagate(errp, err);
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
134
+ return;
105
+ return;
135
+ }
106
+ }
136
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
107
+
137
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
138
+ qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
139
110
+
140
/* Initialize all I2C */
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
141
for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
142
diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
143
new file mode 100644
118
new file mode 100644
144
index XXXXXXX..XXXXXXX
119
index XXXXXXX..XXXXXXX
145
--- /dev/null
120
--- /dev/null
146
+++ b/hw/misc/imx_rngc.c
121
+++ b/hw/misc/bcm2835_powermgt.c
147
@@ -XXX,XX +XXX,XX @@
122
@@ -XXX,XX +XXX,XX @@
148
+/*
123
+/*
149
+ * Freescale i.MX RNGC emulation
124
+ * BCM2835 Power Management emulation
150
+ *
125
+ *
151
+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
152
+ *
128
+ *
153
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
154
+ * See the COPYING file in the top-level directory.
130
+ * See the COPYING file in the top-level directory.
155
+ *
156
+ * This driver provides the minimum functionality to initialize and seed
157
+ * an rngc and to read random numbers. The rngb that is found in imx25
158
+ * chipsets is also supported.
159
+ */
131
+ */
160
+
132
+
161
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
162
+#include "qemu/main-loop.h"
134
+#include "qemu/log.h"
163
+#include "qemu/module.h"
135
+#include "qemu/module.h"
164
+#include "qemu/log.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
165
+#include "qemu/guest-random.h"
166
+#include "hw/irq.h"
167
+#include "hw/misc/imx_rngc.h"
168
+#include "migration/vmstate.h"
137
+#include "migration/vmstate.h"
169
+
138
+#include "sysemu/runstate.h"
170
+#define RNGC_NAME "i.MX RNGC"
139
+
171
+
140
+#define PASSWORD 0x5a000000
172
+#define RNGC_VER_ID 0x00
141
+#define PASSWORD_MASK 0xff000000
173
+#define RNGC_COMMAND 0x04
142
+
174
+#define RNGC_CONTROL 0x08
143
+#define R_RSTC 0x1c
175
+#define RNGC_STATUS 0x0C
144
+#define V_RSTC_RESET 0x20
176
+#define RNGC_FIFO 0x14
145
+#define R_RSTS 0x20
177
+
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
178
+/* These version info are reported by the rngb in an imx258 chip. */
147
+#define R_WDOG 0x24
179
+#define RNG_TYPE_RNGB 0x1
148
+
180
+#define V_MAJ 0x2
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
181
+#define V_MIN 0x40
150
+ unsigned size)
182
+
151
+{
183
+#define RNGC_CMD_BIT_SW_RST 0x40
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
184
+#define RNGC_CMD_BIT_CLR_ERR 0x20
153
+ uint32_t res = 0;
185
+#define RNGC_CMD_BIT_CLR_INT 0x10
186
+#define RNGC_CMD_BIT_SEED 0x02
187
+#define RNGC_CMD_BIT_SELF_TEST 0x01
188
+
189
+#define RNGC_CTRL_BIT_MASK_ERR 0x40
190
+#define RNGC_CTRL_BIT_MASK_DONE 0x20
191
+#define RNGC_CTRL_BIT_AUTO_SEED 0x10
192
+
193
+/* the current status for self-test and seed operations */
194
+#define OP_IDLE 0
195
+#define OP_RUN 1
196
+#define OP_DONE 2
197
+
198
+static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size)
199
+{
200
+ IMXRNGCState *s = IMX_RNGC(opaque);
201
+ uint64_t val = 0;
202
+
154
+
203
+ switch (offset) {
155
+ switch (offset) {
204
+ case RNGC_VER_ID:
156
+ case R_RSTC:
205
+ val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN;
157
+ res = s->rstc;
206
+ break;
158
+ break;
207
+
159
+ case R_RSTS:
208
+ case RNGC_COMMAND:
160
+ res = s->rsts;
209
+ if (s->op_seed == OP_RUN) {
161
+ break;
210
+ val |= RNGC_CMD_BIT_SEED;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
191
+
192
+ switch (offset) {
193
+ case R_RSTC:
194
+ s->rstc = value;
195
+ if (value & V_RSTC_RESET) {
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
198
+ } else {
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200
+ }
211
+ }
201
+ }
212
+ if (s->op_self_test == OP_RUN) {
202
+ break;
213
+ val |= RNGC_CMD_BIT_SELF_TEST;
203
+ case R_RSTS:
214
+ }
204
+ qemu_log_mask(LOG_UNIMP,
215
+ break;
205
+ "bcm2835_powermgt_write: RSTS\n");
216
+
206
+ s->rsts = value;
217
+ case RNGC_CONTROL:
207
+ break;
218
+ /*
208
+ case R_WDOG:
219
+ * The CTL_ACC and VERIF_MODE bits are not supported yet.
209
+ qemu_log_mask(LOG_UNIMP,
220
+ * They read as 0.
210
+ "bcm2835_powermgt_write: WDOG\n");
221
+ */
211
+ s->wdog = value;
222
+ val |= s->mask;
212
+ break;
223
+ if (s->auto_seed) {
213
+
224
+ val |= RNGC_CTRL_BIT_AUTO_SEED;
214
+ default:
225
+ }
215
+ qemu_log_mask(LOG_UNIMP,
226
+ /*
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
227
+ * We don't have an internal fifo like the real hardware.
217
+ "\n", offset);
228
+ * There's no need for strategy to handle fifo underflows.
218
+ break;
229
+ * We return the FIFO_UFLOW_RESPONSE bits as 0.
219
+ }
230
+ */
220
+}
231
+ break;
221
+
232
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
233
+ case RNGC_STATUS:
223
+ .read = bcm2835_powermgt_read,
234
+ /*
224
+ .write = bcm2835_powermgt_write,
235
+ * We never report any statistics test or self-test errors or any
236
+ * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0.
237
+ */
238
+
239
+ /*
240
+ * We don't have an internal fifo, see above. Therefore, we
241
+ * report back the default fifo size (5 32-bit words) and
242
+ * indicate that our fifo is always full.
243
+ */
244
+ val |= 5 << 12 | 5 << 8;
245
+
246
+ /* We always have a new seed available. */
247
+ val |= 1 << 6;
248
+
249
+ if (s->op_seed == OP_DONE) {
250
+ val |= 1 << 5;
251
+ }
252
+ if (s->op_self_test == OP_DONE) {
253
+ val |= 1 << 4;
254
+ }
255
+ if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) {
256
+ /*
257
+ * We're busy if self-test is running or if we're
258
+ * seeding the prng.
259
+ */
260
+ val |= 1 << 1;
261
+ } else {
262
+ /*
263
+ * We're ready to provide secure random numbers whenever
264
+ * we're not busy.
265
+ */
266
+ val |= 1;
267
+ }
268
+ break;
269
+
270
+ case RNGC_FIFO:
271
+ qemu_guest_getrandom_nofail(&val, sizeof(val));
272
+ break;
273
+ }
274
+
275
+ return val;
276
+}
277
+
278
+static void imx_rngc_do_reset(IMXRNGCState *s)
279
+{
280
+ s->op_self_test = OP_IDLE;
281
+ s->op_seed = OP_IDLE;
282
+ s->mask = 0;
283
+ s->auto_seed = false;
284
+}
285
+
286
+static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value,
287
+ unsigned size)
288
+{
289
+ IMXRNGCState *s = IMX_RNGC(opaque);
290
+
291
+ switch (offset) {
292
+ case RNGC_COMMAND:
293
+ if (value & RNGC_CMD_BIT_SW_RST) {
294
+ imx_rngc_do_reset(s);
295
+ }
296
+
297
+ /*
298
+ * For now, both CLR_ERR and CLR_INT clear the interrupt. We
299
+ * don't report any errors yet.
300
+ */
301
+ if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) {
302
+ qemu_irq_lower(s->irq);
303
+ }
304
+
305
+ if (value & RNGC_CMD_BIT_SEED) {
306
+ s->op_seed = OP_RUN;
307
+ qemu_bh_schedule(s->seed_bh);
308
+ }
309
+
310
+ if (value & RNGC_CMD_BIT_SELF_TEST) {
311
+ s->op_self_test = OP_RUN;
312
+ qemu_bh_schedule(s->self_test_bh);
313
+ }
314
+ break;
315
+
316
+ case RNGC_CONTROL:
317
+ /*
318
+ * The CTL_ACC and VERIF_MODE bits are not supported yet.
319
+ * We ignore them if they're set by the caller.
320
+ */
321
+
322
+ if (value & RNGC_CTRL_BIT_MASK_ERR) {
323
+ s->mask |= RNGC_CTRL_BIT_MASK_ERR;
324
+ } else {
325
+ s->mask &= ~RNGC_CTRL_BIT_MASK_ERR;
326
+ }
327
+
328
+ if (value & RNGC_CTRL_BIT_MASK_DONE) {
329
+ s->mask |= RNGC_CTRL_BIT_MASK_DONE;
330
+ } else {
331
+ s->mask &= ~RNGC_CTRL_BIT_MASK_DONE;
332
+ }
333
+
334
+ if (value & RNGC_CTRL_BIT_AUTO_SEED) {
335
+ s->auto_seed = true;
336
+ } else {
337
+ s->auto_seed = false;
338
+ }
339
+ break;
340
+ }
341
+}
342
+
343
+static const MemoryRegionOps imx_rngc_ops = {
344
+ .read = imx_rngc_read,
345
+ .write = imx_rngc_write,
346
+ .endianness = DEVICE_NATIVE_ENDIAN,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
347
+};
226
+ .impl.min_access_size = 4,
348
+
227
+ .impl.max_access_size = 4,
349
+static void imx_rngc_self_test(void *opaque)
228
+};
350
+{
229
+
351
+ IMXRNGCState *s = IMX_RNGC(opaque);
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
352
+
231
+ .name = TYPE_BCM2835_POWERMGT,
353
+ s->op_self_test = OP_DONE;
354
+ if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
355
+ qemu_irq_raise(s->irq);
356
+ }
357
+}
358
+
359
+static void imx_rngc_seed(void *opaque)
360
+{
361
+ IMXRNGCState *s = IMX_RNGC(opaque);
362
+
363
+ s->op_seed = OP_DONE;
364
+ if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
365
+ qemu_irq_raise(s->irq);
366
+ }
367
+}
368
+
369
+static void imx_rngc_realize(DeviceState *dev, Error **errp)
370
+{
371
+ IMXRNGCState *s = IMX_RNGC(dev);
372
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
373
+
374
+ memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s,
375
+ TYPE_IMX_RNGC, 0x1000);
376
+ sysbus_init_mmio(sbd, &s->iomem);
377
+
378
+ sysbus_init_irq(sbd, &s->irq);
379
+ s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s);
380
+ s->seed_bh = qemu_bh_new(imx_rngc_seed, s);
381
+}
382
+
383
+static void imx_rngc_reset(DeviceState *dev)
384
+{
385
+ IMXRNGCState *s = IMX_RNGC(dev);
386
+
387
+ imx_rngc_do_reset(s);
388
+}
389
+
390
+static const VMStateDescription vmstate_imx_rngc = {
391
+ .name = RNGC_NAME,
392
+ .version_id = 1,
232
+ .version_id = 1,
393
+ .minimum_version_id = 1,
233
+ .minimum_version_id = 1,
394
+ .fields = (VMStateField[]) {
234
+ .fields = (VMStateField[]) {
395
+ VMSTATE_UINT8(op_self_test, IMXRNGCState),
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
396
+ VMSTATE_UINT8(op_seed, IMXRNGCState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
397
+ VMSTATE_UINT8(mask, IMXRNGCState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
398
+ VMSTATE_BOOL(auto_seed, IMXRNGCState),
399
+ VMSTATE_END_OF_LIST()
238
+ VMSTATE_END_OF_LIST()
400
+ }
239
+ }
401
+};
240
+};
402
+
241
+
403
+static void imx_rngc_class_init(ObjectClass *klass, void *data)
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
404
+{
262
+{
405
+ DeviceClass *dc = DEVICE_CLASS(klass);
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
406
+
264
+
407
+ dc->realize = imx_rngc_realize;
265
+ dc->reset = bcm2835_powermgt_reset;
408
+ dc->reset = imx_rngc_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
409
+ dc->desc = RNGC_NAME,
267
+}
410
+ dc->vmsd = &vmstate_imx_rngc;
268
+
411
+}
269
+static TypeInfo bcm2835_powermgt_info = {
412
+
270
+ .name = TYPE_BCM2835_POWERMGT,
413
+static const TypeInfo imx_rngc_info = {
414
+ .name = TYPE_IMX_RNGC,
415
+ .parent = TYPE_SYS_BUS_DEVICE,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
416
+ .instance_size = sizeof(IMXRNGCState),
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
417
+ .class_init = imx_rngc_class_init,
273
+ .class_init = bcm2835_powermgt_class_init,
418
+};
274
+ .instance_init = bcm2835_powermgt_init,
419
+
275
+};
420
+static void imx_rngc_register_types(void)
276
+
421
+{
277
+static void bcm2835_powermgt_register_types(void)
422
+ type_register_static(&imx_rngc_info);
278
+{
423
+}
279
+ type_register_static(&bcm2835_powermgt_info);
424
+
280
+}
425
+type_init(imx_rngc_register_types)
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
426
--
295
--
427
2.20.1
296
2.20.1
428
297
429
298
diff view generated by jsdifflib
[PULL 05/15] tests/boot_linux_console: Add initrd test for the CubieBoard
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This test boots a Linux kernel on a CubieBoard and verify
3
Add a test booting and quickly shutdown a raspi2 machine,
4
the serial output is working.
4
to test the power management model:
5
5
6
The kernel image and DeviceTree blob are built by the Armbian
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
project (based on Debian):
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
https://docs.armbian.com/Developer-Guide_Build-Preparation/
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
The cpio image used comes from the linux-build-test project:
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
https://github.com/groeck/linux-build-test
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
If ARM is a target being built, "make check-acceptance" will
13
...
14
automatically include this test by the use of the "arch:arm" tags.
15
16
Alternatively, this test can be run using:
17
18
$ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
19
console: Uncompressing Linux... done, booting the kernel.
20
console: Booting Linux on physical CPU 0x0
21
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
22
console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=50c5387d
23
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
24
console: OF: fdt: Machine model: Cubietech Cubieboard
25
[...]
26
console: Boot successful.
14
console: Boot successful.
27
console: cat /proc/cpuinfo
15
console: cat /proc/cpuinfo
28
console: / # cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
29
console: processor : 0
17
...
30
console: model name : ARMv7 Processor rev 0 (v7l)
18
console: processor : 3
31
console: BogoMIPS : 832.51
19
console: model name : ARMv7 Processor rev 5 (v7l)
32
[...]
20
console: BogoMIPS : 125.00
33
console: Hardware : Allwinner sun4i/sun5i Families
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
34
console: Revision : 0000
28
console: Revision : 0000
35
console: Serial : 0000000000000000
29
console: Serial : 0000000000000000
36
console: cat /proc/iomem
30
console: cat /proc/iomem
37
console: / # cat /proc/iomem
31
console: / # cat /proc/iomem
38
console: 01c00000-01c0002f : system-control@1c00000
32
console: 00000000-3bffffff : System RAM
39
console: 01c02000-01c02fff : dma-controller@1c02000
33
console: 00008000-00afffff : Kernel code
40
console: 01c05000-01c05fff : spi@1c05000
34
console: 00c00000-00d468ef : Kernel data
41
console: 01c0b080-01c0b093 : mdio@1c0b080
35
console: 3f006000-3f006fff : dwc_otg
42
console: 01c0c000-01c0cfff : lcd-controller@1c0c000
36
console: 3f007000-3f007eff : /soc/dma@7e007000
43
console: 01c0d000-01c0dfff : lcd-controller@1c0d000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
44
console: 01c0f000-01c0ffff : mmc@1c0f000
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
45
[...]
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
46
PASS (54.35 s)
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
47
44
48
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
49
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
50
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
51
Message-id: 20191230110953.25496-2-f4bug@amsat.org
52
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
53
---
49
---
54
tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
55
1 file changed, 41 insertions(+)
51
1 file changed, 43 insertions(+)
56
52
57
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
58
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
59
--- a/tests/acceptance/boot_linux_console.py
55
--- a/tests/acceptance/boot_linux_console.py
60
+++ b/tests/acceptance/boot_linux_console.py
56
+++ b/tests/acceptance/boot_linux_console.py
61
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
57
@@ -XXX,XX +XXX,XX @@
62
self.wait_for_console_pattern('Boot successful.')
58
from avocado import skip
63
# TODO user command, for now the uart is stuck
59
from avocado import skipUnless
64
60
from avocado_qemu import Test
65
+ def test_arm_cubieboard_initrd(self):
61
+from avocado_qemu import exec_command
62
from avocado_qemu import exec_command_and_wait_for_pattern
63
from avocado_qemu import interrupt_interactive_console_until_pattern
64
from avocado_qemu import wait_for_console_pattern
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
66
"""
67
self.do_test_arm_raspi2(0)
68
69
+ def test_arm_raspi2_initrd(self):
66
+ """
70
+ """
67
+ :avocado: tags=arch:arm
71
+ :avocado: tags=arch:arm
68
+ :avocado: tags=machine:cubieboard
72
+ :avocado: tags=machine:raspi2
69
+ """
73
+ """
70
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
71
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
75
+ 'pool/main/r/raspberrypi-firmware/'
72
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
73
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
74
+ kernel_path = self.extract_from_deb(deb_path,
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
75
+ '/boot/vmlinuz-4.20.7-sunxi')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
76
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
81
+
77
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
78
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
79
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
80
+ 'arm/rootfs-armv5.cpio.gz')
84
+ 'arm/rootfs-armv7a.cpio.gz')
81
+ initrd_hash = '2b50f1873e113523967806f4da2afe385462ff9b'
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
82
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
83
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
84
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
85
+
89
+
86
+ self.vm.set_console()
90
+ self.vm.set_console()
87
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
88
+ 'console=ttyS0,115200 '
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
89
+ 'usbcore.nousb '
93
+ 'panic=-1 noreboot ' +
90
+ 'panic=-1 noreboot')
94
+ 'dwc_otg.fiq_fsm_enable=0')
91
+ self.vm.add_args('-kernel', kernel_path,
95
+ self.vm.add_args('-kernel', kernel_path,
92
+ '-dtb', dtb_path,
96
+ '-dtb', dtb_path,
93
+ '-initrd', initrd_path,
97
+ '-initrd', initrd_path,
94
+ '-append', kernel_command_line,
98
+ '-append', kernel_command_line,
95
+ '-no-reboot')
99
+ '-no-reboot')
96
+ self.vm.launch()
100
+ self.vm.launch()
97
+ self.wait_for_console_pattern('Boot successful.')
101
+ self.wait_for_console_pattern('Boot successful.')
98
+
102
+
99
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
100
+ 'Allwinner sun4i/sun5i')
104
+ 'BCM2835')
101
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
102
+ 'system-control@1c00000')
106
+ '/soc/cprman@7e101000')
103
+ exec_command_and_wait_for_pattern(self, 'reboot',
107
+ exec_command(self, 'halt')
104
+ 'reboot: Restarting system')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
105
+
110
+
106
def test_s390x_s390_ccw_virtio(self):
111
def test_arm_exynos4210_initrd(self):
107
"""
112
"""
108
:avocado: tags=arch:s390x
113
:avocado: tags=arch:arm
109
--
114
--
110
2.20.1
115
2.20.1
111
116
112
117
diff view generated by jsdifflib
[PULL 06/15] tests/boot_linux_console: Add a SD card test for the CubieBoard
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
The kernel image and DeviceTree blob are built by the Armbian
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
project (based on Debian):
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
https://docs.armbian.com/Developer-Guide_Build-Preparation/
5
assert due to fpst->default_nan_mode being set.
6
6
7
The cpio image used comes from the linux-build-test project:
7
To avoid this, we check to see what NaN mode we're running in before we call
8
https://github.com/groeck/linux-build-test
8
floatxx_silence_nan().
9
9
10
If ARM is a target being built, "make check-acceptance" will
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
automatically include this test by the use of the "arch:arm" tags.
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
13
Alternatively, this test can be run using:
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
15
$ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
16
console: Uncompressing Linux... done, booting the kernel.
17
console: Booting Linux on physical CPU 0x0
18
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
19
[...]
20
console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4
21
console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit
22
console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps 0x1 impl platform mode
23
console: ahci-sunxi 1c18000.sata: flags: ncq only
24
console: scsi host0: ahci-sunxi
25
console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 27
26
console: of_cfs_init
27
console: of_cfs_init: OK
28
console: vcc3v0: disabling
29
console: vcc5v0: disabling
30
console: usb1-vbus: disabling
31
console: usb2-vbus: disabling
32
console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
33
console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100
34
console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32)
35
console: ata1.00: applying bridge limits
36
console: ata1.00: configured for UDMA/100
37
console: scsi 0:0:0:0: Direct-Access ATA QEMU HARDDISK 2.5+ PQ: 0 ANSI: 5
38
console: sd 0:0:0:0: Attached scsi generic sg0 type 0
39
console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB)
40
console: sd 0:0:0:0: [sda] Write Protect is off
41
console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
42
console: sd 0:0:0:0: [sda] Attached SCSI disk
43
console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem
44
console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null)
45
console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0.
46
[...]
47
console: cat /proc/partitions
48
console: / # cat /proc/partitions
49
console: major minor #blocks name
50
console: 1 0 4096 ram0
51
console: 1 1 4096 ram1
52
console: 1 2 4096 ram2
53
console: 1 3 4096 ram3
54
console: 8 0 20480 sda
55
console: reboot
56
console: / # reboot
57
[...]
58
console: sd 0:0:0:0: [sda] Synchronizing SCSI cache
59
console: reboot: Restarting system
60
PASS (48.39 s)
61
62
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
63
Message-id: 20191230110953.25496-3-f4bug@amsat.org
64
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
65
---
15
---
66
tests/acceptance/boot_linux_console.py | 44 ++++++++++++++++++++++++++
16
target/arm/helper-a64.c | 12 +++++++++---
67
1 file changed, 44 insertions(+)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
68
19
69
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
70
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
71
--- a/tests/acceptance/boot_linux_console.py
22
--- a/target/arm/helper-a64.c
72
+++ b/tests/acceptance/boot_linux_console.py
23
+++ b/target/arm/helper-a64.c
73
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
74
exec_command_and_wait_for_pattern(self, 'reboot',
25
float16 nan = a;
75
'reboot: Restarting system')
26
if (float16_is_signaling_nan(a, fpst)) {
76
27
float_raise(float_flag_invalid, fpst);
77
+ def test_arm_cubieboard_sata(self):
28
- nan = float16_silence_nan(a, fpst);
78
+ """
29
+ if (!fpst->default_nan_mode) {
79
+ :avocado: tags=arch:arm
30
+ nan = float16_silence_nan(a, fpst);
80
+ :avocado: tags=machine:cubieboard
31
+ }
81
+ """
32
}
82
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
33
if (fpst->default_nan_mode) {
83
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
34
nan = float16_default_nan(fpst);
84
+ deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
85
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
36
float32 nan = a;
86
+ kernel_path = self.extract_from_deb(deb_path,
37
if (float32_is_signaling_nan(a, fpst)) {
87
+ '/boot/vmlinuz-4.20.7-sunxi')
38
float_raise(float_flag_invalid, fpst);
88
+ dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
39
- nan = float32_silence_nan(a, fpst);
89
+ dtb_path = self.extract_from_deb(deb_path, dtb_path)
40
+ if (!fpst->default_nan_mode) {
90
+ rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
41
+ nan = float32_silence_nan(a, fpst);
91
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
42
+ }
92
+ 'arm/rootfs-armv5.ext2.gz')
43
}
93
+ rootfs_hash = '093e89d2b4d982234bf528bc9fb2f2f17a9d1f93'
44
if (fpst->default_nan_mode) {
94
+ rootfs_path_gz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
45
nan = float32_default_nan(fpst);
95
+ rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
96
+ archive.gzip_uncompress(rootfs_path_gz, rootfs_path)
47
float64 nan = a;
97
+
48
if (float64_is_signaling_nan(a, fpst)) {
98
+ self.vm.set_console()
49
float_raise(float_flag_invalid, fpst);
99
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
50
- nan = float64_silence_nan(a, fpst);
100
+ 'console=ttyS0,115200 '
51
+ if (!fpst->default_nan_mode) {
101
+ 'usbcore.nousb '
52
+ nan = float64_silence_nan(a, fpst);
102
+ 'root=/dev/sda ro '
53
+ }
103
+ 'panic=-1 noreboot')
54
}
104
+ self.vm.add_args('-kernel', kernel_path,
55
if (fpst->default_nan_mode) {
105
+ '-dtb', dtb_path,
56
nan = float64_default_nan(fpst);
106
+ '-drive', 'if=none,format=raw,id=disk0,file='
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
107
+ + rootfs_path,
58
index XXXXXXX..XXXXXXX 100644
108
+ '-device', 'ide-hd,bus=ide.0,drive=disk0',
59
--- a/target/arm/vfp_helper.c
109
+ '-append', kernel_command_line,
60
+++ b/target/arm/vfp_helper.c
110
+ '-no-reboot')
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
111
+ self.vm.launch()
62
float16 nan = f16;
112
+ self.wait_for_console_pattern('Boot successful.')
63
if (float16_is_signaling_nan(f16, fpst)) {
113
+
64
float_raise(float_flag_invalid, fpst);
114
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
65
- nan = float16_silence_nan(f16, fpst);
115
+ 'Allwinner sun4i/sun5i')
66
+ if (!fpst->default_nan_mode) {
116
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
67
+ nan = float16_silence_nan(f16, fpst);
117
+ 'sda')
68
+ }
118
+ exec_command_and_wait_for_pattern(self, 'reboot',
69
}
119
+ 'reboot: Restarting system')
70
if (fpst->default_nan_mode) {
120
+
71
nan = float16_default_nan(fpst);
121
def test_s390x_s390_ccw_virtio(self):
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
122
"""
73
float32 nan = f32;
123
:avocado: tags=arch:s390x
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
124
--
127
--
125
2.20.1
128
2.20.1
126
129
127
130
diff view generated by jsdifflib
[PULL 13/15] arm/gicv3: update virtual irq state after IAR register read
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
register activates the highest priority pending interrupt and provides its
4
function has to be used for machine shutdown. Otherwise we cause
5
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
state - this change makes sure the virtual irq state is updated.
7
6
8
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
hw/intc/arm_gicv3_cpuif.c | 3 +++
13
hw/gpio/gpio_pwr.c | 2 +-
14
1 file changed, 3 insertions(+)
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
15
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_cpuif.c
18
--- a/hw/gpio/gpio_pwr.c
19
+++ b/hw/intc/arm_gicv3_cpuif.c
19
+++ b/hw/gpio/gpio_pwr.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
21
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
22
trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
22
{
23
gicv3_redist_affid(cs), intid);
23
if (level) {
24
+
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
25
+ gicv3_cpuif_virt_update(cs);
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
26
+
26
}
27
return intid;
28
}
27
}
29
28
30
--
29
--
31
2.20.1
30
2.20.1
32
31
33
32
diff view generated by jsdifflib
New patch
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
9
---
10
target/arm/translate-mve.c | 17 +++++++++--------
11
1 file changed, 9 insertions(+), 8 deletions(-)
12
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-mve.c
16
+++ b/target/arm/translate-mve.c
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
18
}
19
}
20
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
23
+ unsigned msize)
24
{
25
TCGv_i32 addr;
26
uint32_t offset;
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
28
return true;
29
}
30
31
- offset = a->imm << a->size;
32
+ offset = a->imm << msize;
33
if (!a->a) {
34
offset = -offset;
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
42
}
43
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
65
--
66
2.20.1
67
68
diff view generated by jsdifflib
[PULL 12/15] target/arm: adjust program counter for wfi exception in AArch32
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
The wfi instruction can be configured to be trapped by a higher exception
10
In particular, fixing the second of these allows us to recast
4
level, such as the EL2 hypervisor. When the instruction is trapped, the
11
the implementation to avoid 128-bit arithmetic entirely.
5
program counter should contain the address of the wfi instruction that
6
caused the exception. The program counter is adjusted for this in the wfi op
7
helper function.
8
12
9
However, this correction is done to env->pc, which only applies to AArch64
13
Since the element size here is always 4, we can also drop the
10
mode. For AArch32, the program counter is stored in env->regs[15]. This
14
parameterization of ESIZE to make the code a little more readable.
11
adds an if-else statement to modify the correct program counter location
12
based on the the current CPU mode.
13
15
14
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
17
---
20
---
18
target/arm/op_helper.c | 7 ++++++-
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
19
1 file changed, 6 insertions(+), 1 deletion(-)
22
1 file changed, 21 insertions(+), 17 deletions(-)
20
23
21
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
22
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/op_helper.c
26
--- a/target/arm/mve_helper.c
24
+++ b/target/arm/op_helper.c
27
+++ b/target/arm/mve_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
28
@@ -XXX,XX +XXX,XX @@
29
*/
30
31
#include "qemu/osdep.h"
32
-#include "qemu/int128.h"
33
#include "cpu.h"
34
#include "internals.h"
35
#include "vec_internal.h"
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
38
39
/*
40
- * Rounding multiply add long dual accumulate high: we must keep
41
- * a 72-bit internal accumulator value and return the top 64 bits.
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
43
+ * this is implemented with a 72-bit internal accumulator value of which
44
+ * the top 64 bits are returned. We optimize this to avoid having to
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
46
+ * is squashed back into 64-bits after each beat.
47
*/
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
51
void *vm, uint64_t a) \
52
{ \
53
uint16_t mask = mve_element_mask(env); \
54
unsigned e; \
55
TYPE *n = vn, *m = vm; \
56
- Int128 acc = int128_lshift(TO128(a), 8); \
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
59
if (mask & 1) { \
60
+ LTYPE mul; \
61
if (e & 1) { \
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
63
- m[H##ESIZE(e)])); \
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
65
+ if (SUB) { \
66
+ mul = -mul; \
67
+ } \
68
} else { \
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
70
- m[H##ESIZE(e)])); \
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
72
} \
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
75
+ a += mul; \
76
} \
77
} \
78
mve_advance_vpt(env); \
79
- return int128_getlo(int128_rshift(acc, 8)); \
80
+ return a; \
26
}
81
}
27
82
28
if (target_el) {
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
29
- env->pc -= insn_len;
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
30
+ if (env->aarch64) {
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
31
+ env->pc -= insn_len;
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
32
+ } else {
87
33
+ env->regs[15] -= insn_len;
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
34
+ }
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
35
+
90
36
raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
37
target_el);
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
38
}
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
95
96
/* Vector add across vector */
97
#define DO_VADDV(OP, ESIZE, TYPE) \
39
--
98
--
40
2.20.1
99
2.20.1
41
100
42
101
diff view generated by jsdifflib
New patch
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 16 ++++++++++
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
14
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
18
+++ b/target/arm/translate.h
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
20
return opc | s->be_data;
21
}
22
23
+/**
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
25
+ *
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
49
-{
50
- /*
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
109
-}
110
-
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
112
GVecGen2iFn *fn)
113
{
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
119
a64_translate_init();
120
}
121
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
123
+{
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
125
+ switch (cmode) {
126
+ case 0: case 1:
127
+ /* no-op */
128
+ break;
129
+ case 2: case 3:
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
181
{
182
--
183
2.20.1
184
185
diff view generated by jsdifflib
[PULL 09/15] hw/arm/allwinner-a10: Remove local qemu_irq variables
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
We won't reuse the CPU IRQ/FIQ variables. Simplify by calling
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
qdev_get_gpio_in() in place.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 3 +-
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
5
14
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
7
Message-id: 20191230110953.25496-6-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/allwinner-a10.c | 9 ++++-----
12
1 file changed, 4 insertions(+), 5 deletions(-)
13
14
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/allwinner-a10.c
17
--- a/target/arm/translate.h
17
+++ b/hw/arm/allwinner-a10.c
18
+++ b/target/arm/translate.h
18
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
20
* VMVN and VBIC (when cmode < 14 && op == 1).
21
*
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
23
- * callers must catch this.
24
+ * callers must catch this; we return the 64-bit constant value defined
25
+ * for AArch64.
26
*
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
19
{
34
{
20
AwA10State *s = AW_A10(dev);
35
int rd = extract32(insn, 0, 5);
21
SysBusDevice *sysbusdev;
36
int cmode = extract32(insn, 12, 4);
22
- qemu_irq fiq, irq;
37
- int cmode_3_1 = extract32(cmode, 1, 3);
23
Error *err = NULL;
38
- int cmode_0 = extract32(cmode, 0, 1);
24
39
int o2 = extract32(insn, 11, 1);
25
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
26
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
41
bool is_neg = extract32(insn, 29, 1);
27
error_propagate(errp, err);
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
28
return;
43
return;
29
}
44
}
30
- irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
45
31
- fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
46
- /* See AdvSIMDExpandImm() in ARM ARM */
32
47
- switch (cmode_3_1) {
33
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
34
if (err != NULL) {
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
35
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
36
}
130
}
37
sysbusdev = SYS_BUS_DEVICE(&s->intc);
131
38
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
39
- sysbus_connect_irq(sysbusdev, 0, irq);
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
40
- sysbus_connect_irq(sysbusdev, 1, fiq);
134
index XXXXXXX..XXXXXXX 100644
41
+ sysbus_connect_irq(sysbusdev, 0,
135
--- a/target/arm/translate.c
42
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
136
+++ b/target/arm/translate.c
43
+ sysbus_connect_irq(sysbusdev, 1,
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
44
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
138
case 14:
45
qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
139
if (op) {
46
140
/*
47
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
141
- * This is the only case where the top and bottom 32 bits
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
48
--
168
--
49
2.20.1
169
2.20.1
50
170
51
171
diff view generated by jsdifflib
[PULL 14/15] target/arm: Return correct IL bit in merge_syn_data_abort
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
2
3
3
The IL bit is set for 32-bit instructions, thus passing false
4
(We can't replace the other use of bitfield_replicate() in this file,
4
with the is_16bit parameter to syn_data_abort_with_iss() makes
5
in logic_imm_decode_wmask(), because that location needs to handle 2
5
a syn mask that always has the IL bit set.
6
and 4 bit elements, which dup_const() cannot.)
6
7
7
Pass is_16bit as true to make the initial syn mask have IL=0,
8
so that the final IL value comes from or'ing template_syn.
9
10
Cc: qemu-stable@nongnu.org
11
Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts")
12
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200117004618.2742-2-richard.henderson@linaro.org
15
[rth: Extracted this as a self-contained bug fix from a larger patch]
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
19
---
11
---
20
target/arm/tlb_helper.c | 2 +-
12
target/arm/translate-a64.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
22
14
23
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/tlb_helper.c
17
--- a/target/arm/translate-a64.c
26
+++ b/target/arm/tlb_helper.c
18
+++ b/target/arm/translate-a64.c
27
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
28
syn = syn_data_abort_with_iss(same_el,
20
/* FMOV (vector, immediate) - half-precision */
29
0, 0, 0, 0, 0,
21
imm = vfp_expand_imm(MO_16, abcdefgh);
30
ea, 0, s1ptw, is_write, fsc,
22
/* now duplicate across the lanes */
31
- false);
23
- imm = bitfield_replicate(imm, 16);
32
+ true);
24
+ imm = dup_const(MO_16, imm);
33
/* Merge the runtime syndrome with the template syndrome. */
25
} else {
34
syn |= template_syn;
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
35
}
27
}
36
--
28
--
37
2.20.1
29
2.20.1
38
30
39
31
diff view generated by jsdifflib
New patch
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
15
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/mve.decode
31
+++ b/target/arm/mve.decode
32
@@ -XXX,XX +XXX,XX @@
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
34
%size_28 28:1 !function=plus_1
35
36
+# 1imm format immediate
37
+%imm_28_16_0 28:1 16:3 0:4
38
+
39
&vldr_vstr rn qd imm p a w size l u
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
93
+ }
94
+
95
+#define DO_MOVI(N, I) (I)
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
98
+
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
122
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
124
+{
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
135
+ }
136
+
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
138
+
139
+ qd = mve_qreg_ptr(a->qd);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
144
+}
145
+
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
147
+{
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
168
+ }
169
+ return do_1imm(s, a, fn);
170
+}
171
--
172
2.20.1
173
174
diff view generated by jsdifflib
New patch
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
and VQSHLU.
3
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
10
---
11
target/arm/helper-mve.h | 16 +++++++++++
12
target/arm/mve.decode | 23 +++++++++++++++
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
15
4 files changed, 147 insertions(+)
16
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
224
--
225
2.20.1
226
227
diff view generated by jsdifflib
[PULL 08/15] hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
By calling qdev_pass_gpios() we don't need to hold a copy of the
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
IRQs from the INTC into the SoC state.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Instead of filling an array of qemu_irq and passing it around, we
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
6
can now directly call qdev_get_gpio_in() on the SoC.
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
7
17
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
Message-id: 20191230110953.25496-5-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/allwinner-a10.h | 1 -
14
hw/arm/allwinner-a10.c | 24 +++++++++++-------------
15
2 files changed, 11 insertions(+), 14 deletions(-)
16
17
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/allwinner-a10.h
20
--- a/target/arm/helper-mve.h
20
+++ b/include/hw/arm/allwinner-a10.h
21
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
22
/*< public >*/
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
24
ARMCPU cpu;
25
25
- qemu_irq irq[AW_A10_PIC_INT_NR];
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
AwA10PITState timer;
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
AwA10PICState intc;
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
AwEmacState emac;
29
+
29
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/allwinner-a10.c
47
--- a/target/arm/translate.h
32
+++ b/hw/arm/allwinner-a10.c
48
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
50
return x * 2 + 1;
51
}
52
53
+static inline int rsub_64(DisasContext *s, int x)
54
+{
55
+ return 64 - x;
56
+}
57
+
58
+static inline int rsub_32(DisasContext *s, int x)
59
+{
60
+ return 32 - x;
61
+}
62
+
63
+static inline int rsub_16(DisasContext *s, int x)
64
+{
65
+ return 16 - x;
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
34
{
74
{
35
AwA10State *s = AW_A10(dev);
75
return (dc->features & (1ULL << feature)) != 0;
36
SysBusDevice *sysbusdev;
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
37
- uint8_t i;
77
index XXXXXXX..XXXXXXX 100644
38
qemu_irq fiq, irq;
78
--- a/target/arm/mve.decode
39
Error *err = NULL;
79
+++ b/target/arm/mve.decode
40
80
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
42
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
43
sysbus_connect_irq(sysbusdev, 0, irq);
83
44
sysbus_connect_irq(sysbusdev, 1, fiq);
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
45
- for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
85
+%rshift_i5 16:5 !function=rsub_32
46
- s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
86
+%rshift_i4 16:4 !function=rsub_16
47
- }
87
+%rshift_i3 16:3 !function=rsub_8
48
+ qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
88
+
49
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
50
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
90
+ size=0 shift=%rshift_i3
51
if (err != NULL) {
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
52
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
92
+ size=1 shift=%rshift_i4
53
}
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
54
sysbusdev = SYS_BUS_DEVICE(&s->timer);
94
+ size=2 shift=%rshift_i5
55
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
95
+
56
- sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
96
# Vector loads and stores
57
- sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
97
58
- sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
98
# Widening loads and narrowing stores:
59
- sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
60
- sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
61
- sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
62
+ sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
63
+ sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
103
+
64
+ sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
65
+ sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
66
+ sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
67
+ sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
107
+
68
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
69
memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
70
&error_fatal);
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
71
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
111
+
72
}
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
73
sysbusdev = SYS_BUS_DEVICE(&s->emac);
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
74
sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
75
- sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
115
+
76
+ sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
77
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
78
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
79
if (err) {
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
80
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
120
index XXXXXXX..XXXXXXX 100644
81
return;
121
--- a/target/arm/mve_helper.c
82
}
122
+++ b/target/arm/mve_helper.c
83
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
84
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
85
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
86
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
87
/* FIXME use a qdev chardev prop instead of serial_hd() */
127
+#define DO_2SHIFT_S(OP, FN) \
88
- serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
89
+ serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
90
+ qdev_get_gpio_in(dev, 1),
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
91
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
92
}
163
}
93
164
165
-static inline int rsub_64(DisasContext *s, int x)
166
-{
167
- return 64 - x;
168
-}
169
-
170
-static inline int rsub_32(DisasContext *s, int x)
171
-{
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
94
--
186
--
95
2.20.1
187
2.20.1
96
188
97
189
diff view generated by jsdifflib
[PULL 04/15] hw/arm: Add the Netduino Plus 2
[PULL 15/24] target/arm: Implement MVE VSHLL
1
From: Alistair Francis <alistair@alistair23.me>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: dad8d8d47f7625913e35e27a1c00f603a6b08f9a.1576658572.git.alistair@alistair23.me
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
7
---
9
---
8
hw/arm/Makefile.objs | 1 +
10
target/arm/helper-mve.h | 9 +++++++
9
hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
10
MAINTAINERS | 6 +++++
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
11
3 files changed, 59 insertions(+)
13
target/arm/translate-mve.c | 15 +++++++++++
12
create mode 100644 hw/arm/netduinoplus2.c
14
4 files changed, 105 insertions(+), 4 deletions(-)
13
15
14
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Makefile.objs
18
--- a/target/arm/helper-mve.h
17
+++ b/hw/arm/Makefile.objs
19
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
obj-$(CONFIG_MICROBIT) += microbit.o
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
obj-$(CONFIG_MUSICPAL) += musicpal.o
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
obj-$(CONFIG_NETDUINO2) += netduino2.o
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o
24
+
23
obj-$(CONFIG_NSERIES) += nseries.o
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
obj-$(CONFIG_SX1) += omap_sx1.o
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
obj-$(CONFIG_CHEETAH) += palm.o
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
new file mode 100644
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
index XXXXXXX..XXXXXXX
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
--- /dev/null
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+++ b/hw/arm/netduinoplus2.c
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
31
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
32
+/*
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
33
+ * Netduino Plus 2 Machine Model
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
34
+ *
40
35
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
36
+ *
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
37
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
43
+# VSHLL encoding T2 where shift == esize
38
+ * of this software and associated documentation files (the "Software"), to deal
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
39
+ * in the Software without restriction, including without limitation the rights
45
+ qd=%qd qm=%qm size=0 shift=8
40
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
41
+ * copies of the Software, and to permit persons to whom the Software is
47
+ qd=%qd qm=%qm size=1 shift=16
42
+ * furnished to do so, subject to the following conditions:
43
+ *
44
+ * The above copyright notice and this permission notice shall be included in
45
+ * all copies or substantial portions of the Software.
46
+ *
47
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
51
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
52
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
53
+ * THE SOFTWARE.
54
+ */
55
+
48
+
56
+#include "qemu/osdep.h"
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
57
+#include "qapi/error.h"
50
%rshift_i5 16:5 !function=rsub_32
58
+#include "hw/boards.h"
51
%rshift_i4 16:4 !function=rsub_16
59
+#include "hw/qdev-properties.h"
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
60
+#include "qemu/error-report.h"
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
61
+#include "hw/arm/stm32f405_soc.h"
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
62
+#include "hw/arm/boot.h"
55
63
+
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
64
+static void netduinoplus2_init(MachineState *machine)
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
59
+# overlaps what would be size=0b11 VMULH/VRMULH
65
+{
60
+{
66
+ DeviceState *dev;
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
67
+
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
68
+ dev = qdev_create(NULL, TYPE_STM32F405_SOC);
63
69
+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
70
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
71
+
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
72
+ armv7m_load_kernel(ARM_CPU(first_cpu),
73
+ machine->kernel_filename,
74
+ FLASH_SIZE);
75
+}
67
+}
76
+
68
+
77
+static void netduinoplus2_machine_init(MachineClass *mc)
78
+{
69
+{
79
+ mc->desc = "Netduino Plus 2 Machine";
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
80
+ mc->init = netduinoplus2_init;
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
81
+}
74
+}
82
+
75
+
83
+DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
76
+{
84
diff --git a/MAINTAINERS b/MAINTAINERS
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
79
+
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
81
+}
82
+
83
+{
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
86
+
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
96
+
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
85
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
86
--- a/MAINTAINERS
111
--- a/target/arm/mve_helper.c
87
+++ b/MAINTAINERS
112
+++ b/target/arm/mve_helper.c
88
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
89
S: Maintained
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
90
F: hw/arm/netduino2.c
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
91
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
92
+Netduino Plus 2
93
+M: Alistair Francis <alistair@alistair23.me>
94
+M: Peter Maydell <peter.maydell@linaro.org>
95
+S: Maintained
96
+F: hw/arm/netduinoplus2.c
97
+
117
+
98
SmartFusion2
118
+/*
99
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
100
M: Peter Maydell <peter.maydell@linaro.org>
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
139
+ }
140
+
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
101
--
172
--
102
2.20.1
173
2.20.1
103
174
104
175
diff view generated by jsdifflib
New patch
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 8 ++++++++
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
13
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper-mve.h
17
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/mve.decode
33
+++ b/target/arm/mve.decode
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
+
39
+# Shift-and-insert
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
114
--
115
2.20.1
116
117
diff view generated by jsdifflib
[PULL 02/15] hw/misc: Add the STM32F4xx EXTI device
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
From: Alistair Francis <alistair@alistair23.me>
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
2
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
3
do_urshr() is borrowed from sve_helper.c.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
5
Message-id: ef941d59fd8658589d34ed432e1d6dfdcf7fb1d0.1576658572.git.alistair@alistair23.me
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
8
---
8
---
9
hw/misc/Makefile.objs | 1 +
9
target/arm/helper-mve.h | 10 ++++++++++
10
include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++
10
target/arm/mve.decode | 11 +++++++++++
11
hw/misc/stm32f4xx_exti.c | 188 +++++++++++++++++++++++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
hw/arm/Kconfig | 1 +
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
hw/misc/Kconfig | 3 +
13
4 files changed, 76 insertions(+)
14
hw/misc/trace-events | 5 +
15
6 files changed, 258 insertions(+)
16
create mode 100644 include/hw/misc/stm32f4xx_exti.h
17
create mode 100644 hw/misc/stm32f4xx_exti.c
18
14
19
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/Makefile.objs
17
--- a/target/arm/helper-mve.h
22
+++ b/hw/misc/Makefile.objs
18
+++ b/target/arm/helper-mve.h
23
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o
23
+
28
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
obj-$(CONFIG_MIPS_ITU) += mips_itu.o
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
new file mode 100644
28
+
33
index XXXXXXX..XXXXXXX
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
--- /dev/null
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+++ b/include/hw/misc/stm32f4xx_exti.h
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
@@ -XXX,XX +XXX,XX @@
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
37
+/*
61
+/*
38
+ * STM32F4XX EXTI
62
+ * Narrowing right shifts, taking a double sized input, shifting it
39
+ *
63
+ * and putting the result in either the top or bottom half of the output.
40
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
41
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
43
+ * of this software and associated documentation files (the "Software"), to deal
44
+ * in the Software without restriction, including without limitation the rights
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
65
+ */
60
+
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
61
+#ifndef HW_STM_EXTI_H
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
62
+#define HW_STM_EXTI_H
68
+ void *vm, uint32_t shift) \
63
+
69
+ { \
64
+#include "hw/sysbus.h"
70
+ LTYPE *m = vm; \
65
+#include "hw/hw.h"
71
+ TYPE *d = vd; \
66
+
72
+ uint16_t mask = mve_element_mask(env); \
67
+#define EXTI_IMR 0x00
73
+ unsigned le; \
68
+#define EXTI_EMR 0x04
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
69
+#define EXTI_RTSR 0x08
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
70
+#define EXTI_FTSR 0x0C
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
71
+#define EXTI_SWIER 0x10
77
+ } \
72
+#define EXTI_PR 0x14
78
+ mve_advance_vpt(env); \
73
+
74
+#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"
75
+#define STM32F4XX_EXTI(obj) \
76
+ OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI)
77
+
78
+#define NUM_GPIO_EVENT_IN_LINES 16
79
+#define NUM_INTERRUPT_OUT_LINES 16
80
+
81
+typedef struct {
82
+ SysBusDevice parent_obj;
83
+
84
+ MemoryRegion mmio;
85
+
86
+ uint32_t exti_imr;
87
+ uint32_t exti_emr;
88
+ uint32_t exti_rtsr;
89
+ uint32_t exti_ftsr;
90
+ uint32_t exti_swier;
91
+ uint32_t exti_pr;
92
+
93
+ qemu_irq irq[NUM_INTERRUPT_OUT_LINES];
94
+} STM32F4xxExtiState;
95
+
96
+#endif
97
diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c
98
new file mode 100644
99
index XXXXXXX..XXXXXXX
100
--- /dev/null
101
+++ b/hw/misc/stm32f4xx_exti.c
102
@@ -XXX,XX +XXX,XX @@
103
+/*
104
+ * STM32F4XX EXTI
105
+ *
106
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
107
+ *
108
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
109
+ * of this software and associated documentation files (the "Software"), to deal
110
+ * in the Software without restriction, including without limitation the rights
111
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
112
+ * copies of the Software, and to permit persons to whom the Software is
113
+ * furnished to do so, subject to the following conditions:
114
+ *
115
+ * The above copyright notice and this permission notice shall be included in
116
+ * all copies or substantial portions of the Software.
117
+ *
118
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
119
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
120
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
121
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
122
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
123
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
124
+ * THE SOFTWARE.
125
+ */
126
+
127
+#include "qemu/osdep.h"
128
+#include "qemu/log.h"
129
+#include "trace.h"
130
+#include "hw/irq.h"
131
+#include "migration/vmstate.h"
132
+#include "hw/misc/stm32f4xx_exti.h"
133
+
134
+static void stm32f4xx_exti_reset(DeviceState *dev)
135
+{
136
+ STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);
137
+
138
+ s->exti_imr = 0x00000000;
139
+ s->exti_emr = 0x00000000;
140
+ s->exti_rtsr = 0x00000000;
141
+ s->exti_ftsr = 0x00000000;
142
+ s->exti_swier = 0x00000000;
143
+ s->exti_pr = 0x00000000;
144
+}
145
+
146
+static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)
147
+{
148
+ STM32F4xxExtiState *s = opaque;
149
+
150
+ trace_stm32f4xx_exti_set_irq(irq, level);
151
+
152
+ if (((1 << irq) & s->exti_rtsr) && level) {
153
+ /* Rising Edge */
154
+ s->exti_pr |= 1 << irq;
155
+ }
79
+ }
156
+
80
+
157
+ if (((1 << irq) & s->exti_ftsr) && !level) {
81
+#define DO_VSHRN_ALL(OP, FN) \
158
+ /* Falling Edge */
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
159
+ s->exti_pr |= 1 << irq;
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
160
+ }
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
161
+
86
+
162
+ if (!((1 << irq) & s->exti_imr)) {
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
163
+ /* Interrupt is masked */
164
+ return;
165
+ }
166
+ qemu_irq_pulse(s->irq[irq]);
167
+}
168
+
169
+static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,
170
+ unsigned int size)
171
+{
88
+{
172
+ STM32F4xxExtiState *s = opaque;
89
+ if (likely(sh < 64)) {
173
+
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
174
+ trace_stm32f4xx_exti_read(addr);
91
+ } else if (sh == 64) {
175
+
92
+ return x >> 63;
176
+ switch (addr) {
93
+ } else {
177
+ case EXTI_IMR:
178
+ return s->exti_imr;
179
+ case EXTI_EMR:
180
+ return s->exti_emr;
181
+ case EXTI_RTSR:
182
+ return s->exti_rtsr;
183
+ case EXTI_FTSR:
184
+ return s->exti_ftsr;
185
+ case EXTI_SWIER:
186
+ return s->exti_swier;
187
+ case EXTI_PR:
188
+ return s->exti_pr;
189
+ default:
190
+ qemu_log_mask(LOG_GUEST_ERROR,
191
+ "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);
192
+ return 0;
94
+ return 0;
193
+ }
194
+ return 0;
195
+}
196
+
197
+static void stm32f4xx_exti_write(void *opaque, hwaddr addr,
198
+ uint64_t val64, unsigned int size)
199
+{
200
+ STM32F4xxExtiState *s = opaque;
201
+ uint32_t value = (uint32_t) val64;
202
+
203
+ trace_stm32f4xx_exti_write(addr, value);
204
+
205
+ switch (addr) {
206
+ case EXTI_IMR:
207
+ s->exti_imr = value;
208
+ return;
209
+ case EXTI_EMR:
210
+ s->exti_emr = value;
211
+ return;
212
+ case EXTI_RTSR:
213
+ s->exti_rtsr = value;
214
+ return;
215
+ case EXTI_FTSR:
216
+ s->exti_ftsr = value;
217
+ return;
218
+ case EXTI_SWIER:
219
+ s->exti_swier = value;
220
+ return;
221
+ case EXTI_PR:
222
+ /* This bit is cleared by writing a 1 to it */
223
+ s->exti_pr &= ~value;
224
+ return;
225
+ default:
226
+ qemu_log_mask(LOG_GUEST_ERROR,
227
+ "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);
228
+ }
95
+ }
229
+}
96
+}
230
+
97
+
231
+static const MemoryRegionOps stm32f4xx_exti_ops = {
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
232
+ .read = stm32f4xx_exti_read,
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
233
+ .write = stm32f4xx_exti_write,
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
234
+ .endianness = DEVICE_NATIVE_ENDIAN,
101
index XXXXXXX..XXXXXXX 100644
235
+};
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
236
+
108
+
237
+static void stm32f4xx_exti_init(Object *obj)
109
+#define DO_2SHIFT_N(INSN, FN) \
238
+{
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
239
+ STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);
111
+ { \
240
+ int i;
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
241
+
113
+ gen_helper_mve_##FN##b, \
242
+ for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {
114
+ gen_helper_mve_##FN##h, \
243
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
244
+ }
117
+ }
245
+
118
+
246
+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
247
+ TYPE_STM32F4XX_EXTI, 0x400);
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
249
+
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
250
+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,
251
+ NUM_GPIO_EVENT_IN_LINES);
252
+}
253
+
254
+static const VMStateDescription vmstate_stm32f4xx_exti = {
255
+ .name = TYPE_STM32F4XX_EXTI,
256
+ .version_id = 1,
257
+ .minimum_version_id = 1,
258
+ .fields = (VMStateField[]) {
259
+ VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),
260
+ VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),
261
+ VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),
262
+ VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),
263
+ VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),
264
+ VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),
265
+ VMSTATE_END_OF_LIST()
266
+ }
267
+};
268
+
269
+static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)
270
+{
271
+ DeviceClass *dc = DEVICE_CLASS(klass);
272
+
273
+ dc->reset = stm32f4xx_exti_reset;
274
+ dc->vmsd = &vmstate_stm32f4xx_exti;
275
+}
276
+
277
+static const TypeInfo stm32f4xx_exti_info = {
278
+ .name = TYPE_STM32F4XX_EXTI,
279
+ .parent = TYPE_SYS_BUS_DEVICE,
280
+ .instance_size = sizeof(STM32F4xxExtiState),
281
+ .instance_init = stm32f4xx_exti_init,
282
+ .class_init = stm32f4xx_exti_class_init,
283
+};
284
+
285
+static void stm32f4xx_exti_register_types(void)
286
+{
287
+ type_register_static(&stm32f4xx_exti_info);
288
+}
289
+
290
+type_init(stm32f4xx_exti_register_types)
291
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
292
index XXXXXXX..XXXXXXX 100644
293
--- a/hw/arm/Kconfig
294
+++ b/hw/arm/Kconfig
295
@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
296
bool
297
select ARM_V7M
298
select STM32F4XX_SYSCFG
299
+ select STM32F4XX_EXTI
300
301
config XLNX_ZYNQMP_ARM
302
bool
303
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
304
index XXXXXXX..XXXXXXX 100644
305
--- a/hw/misc/Kconfig
306
+++ b/hw/misc/Kconfig
307
@@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG
308
config STM32F4XX_SYSCFG
309
bool
310
311
+config STM32F4XX_EXTI
312
+ bool
313
+
314
config MIPS_ITU
315
bool
316
317
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
318
index XXXXXXX..XXXXXXX 100644
319
--- a/hw/misc/trace-events
320
+++ b/hw/misc/trace-events
321
@@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
322
stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
323
stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
324
325
+# stm32f4xx_exti
326
+stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
327
+stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
328
+stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
329
+
330
# tz-mpc.c
331
tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
332
tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
333
--
123
--
334
2.20.1
124
2.20.1
335
125
336
126
diff view generated by jsdifflib
[PULL 01/15] hw/misc: Add the STM32F4xx Sysconfig device
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
From: Alistair Francis <alistair@alistair23.me>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
3
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
do_srshr() is borrowed from sve_helper.c.
5
Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
7
---
9
---
8
hw/misc/Makefile.objs | 1 +
10
target/arm/helper-mve.h | 30 +++++++++++
9
include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++++++
11
target/arm/mve.decode | 28 ++++++++++
10
hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++++++++++++
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
11
default-configs/arm-softmmu.mak | 1 +
13
target/arm/translate-mve.c | 12 +++++
12
hw/arm/Kconfig | 9 ++
14
4 files changed, 174 insertions(+)
13
hw/misc/Kconfig | 3 +
15
14
hw/misc/trace-events | 6 +
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
7 files changed, 252 insertions(+)
17
index XXXXXXX..XXXXXXX 100644
16
create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
18
--- a/target/arm/helper-mve.h
17
create mode 100644 hw/misc/stm32f4xx_syscfg.c
19
+++ b/target/arm/helper-mve.h
18
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
index XXXXXXX..XXXXXXX 100644
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
--- a/hw/misc/Makefile.objs
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+++ b/hw/misc/Makefile.objs
24
+
23
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
29
+
28
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
obj-$(CONFIG_MIPS_ITU) += mips_itu.o
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
new file mode 100644
34
+
33
index XXXXXXX..XXXXXXX
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
--- /dev/null
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+++ b/include/hw/misc/stm32f4xx_syscfg.h
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
@@ -XXX,XX +XXX,XX @@
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+/*
39
+
38
+ * STM32F4xx SYSCFG
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+ *
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+ *
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
44
+
43
+ * of this software and associated documentation files (the "Software"), to deal
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+ * in the Software without restriction, including without limitation the rights
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+ * copies of the Software, and to permit persons to whom the Software is
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+ * furnished to do so, subject to the following conditions:
49
+
48
+ *
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+ * The above copyright notice and this permission notice shall be included in
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
50
+ * all copies or substantial portions of the Software.
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+ *
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
55
index XXXXXXX..XXXXXXX 100644
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
56
--- a/target/arm/mve.decode
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
57
+++ b/target/arm/mve.decode
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
58
+ * THE SOFTWARE.
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
59
+ */
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
60
+
62
+
61
+#ifndef HW_STM_SYSCFG_H
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
62
+#define HW_STM_SYSCFG_H
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
63
+
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
64
+#include "hw/sysbus.h"
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
65
+#include "hw/hw.h"
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
66
+
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
67
+#define SYSCFG_MEMRMP 0x00
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
68
+#define SYSCFG_PMC 0x04
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
69
+#define SYSCFG_EXTICR1 0x08
71
+
70
+#define SYSCFG_EXTICR2 0x0C
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
71
+#define SYSCFG_EXTICR3 0x10
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
72
+#define SYSCFG_EXTICR4 0x14
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
73
+#define SYSCFG_CMPCR 0x20
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
74
+
76
+
75
+#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
76
+#define STM32F4XX_SYSCFG(obj) \
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
77
+ OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG)
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
78
+
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
79
+#define SYSCFG_NUM_EXTICR 4
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
80
+
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
81
+typedef struct {
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
82
+ /* <private> */
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
83
+ SysBusDevice parent_obj;
85
+
84
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
85
+ /* <public> */
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
86
+ MemoryRegion mmio;
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
87
+
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
88
+ uint32_t syscfg_memrmp;
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
89
+ uint32_t syscfg_pmc;
91
index XXXXXXX..XXXXXXX 100644
90
+ uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];
92
--- a/target/arm/mve_helper.c
91
+ uint32_t syscfg_cmpcr;
93
+++ b/target/arm/mve_helper.c
92
+
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
93
+ qemu_irq irq;
95
}
94
+ qemu_irq gpio_out[16];
96
}
95
+} STM32F4xxSyscfgState;
97
96
+
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
97
+#endif
98
diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c
99
new file mode 100644
100
index XXXXXXX..XXXXXXX
101
--- /dev/null
102
+++ b/hw/misc/stm32f4xx_syscfg.c
103
@@ -XXX,XX +XXX,XX @@
104
+/*
105
+ * STM32F4xx SYSCFG
106
+ *
107
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
108
+ *
109
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
110
+ * of this software and associated documentation files (the "Software"), to deal
111
+ * in the Software without restriction, including without limitation the rights
112
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
113
+ * copies of the Software, and to permit persons to whom the Software is
114
+ * furnished to do so, subject to the following conditions:
115
+ *
116
+ * The above copyright notice and this permission notice shall be included in
117
+ * all copies or substantial portions of the Software.
118
+ *
119
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
120
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
121
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
122
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
123
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
124
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
125
+ * THE SOFTWARE.
126
+ */
127
+
128
+#include "qemu/osdep.h"
129
+#include "qemu/log.h"
130
+#include "trace.h"
131
+#include "hw/irq.h"
132
+#include "migration/vmstate.h"
133
+#include "hw/misc/stm32f4xx_syscfg.h"
134
+
135
+static void stm32f4xx_syscfg_reset(DeviceState *dev)
136
+{
99
+{
137
+ STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);
100
+ if (likely(sh < 64)) {
138
+
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
139
+ s->syscfg_memrmp = 0x00000000;
102
+ } else {
140
+ s->syscfg_pmc = 0x00000000;
103
+ /* Rounding the sign bit always produces 0. */
141
+ s->syscfg_exticr[0] = 0x00000000;
142
+ s->syscfg_exticr[1] = 0x00000000;
143
+ s->syscfg_exticr[2] = 0x00000000;
144
+ s->syscfg_exticr[3] = 0x00000000;
145
+ s->syscfg_cmpcr = 0x00000000;
146
+}
147
+
148
+static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)
149
+{
150
+ STM32F4xxSyscfgState *s = opaque;
151
+ int icrreg = irq / 4;
152
+ int startbit = (irq & 3) * 4;
153
+ uint8_t config = config = irq / 16;
154
+
155
+ trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);
156
+
157
+ g_assert(icrreg < SYSCFG_NUM_EXTICR);
158
+
159
+ if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
160
+ qemu_set_irq(s->gpio_out[irq], level);
161
+ trace_stm32f4xx_pulse_exti(irq);
162
+ }
163
+}
164
+
165
+static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,
166
+ unsigned int size)
167
+{
168
+ STM32F4xxSyscfgState *s = opaque;
169
+
170
+ trace_stm32f4xx_syscfg_read(addr);
171
+
172
+ switch (addr) {
173
+ case SYSCFG_MEMRMP:
174
+ return s->syscfg_memrmp;
175
+ case SYSCFG_PMC:
176
+ return s->syscfg_pmc;
177
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
178
+ return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];
179
+ case SYSCFG_CMPCR:
180
+ return s->syscfg_cmpcr;
181
+ default:
182
+ qemu_log_mask(LOG_GUEST_ERROR,
183
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
184
+ return 0;
104
+ return 0;
185
+ }
105
+ }
186
+}
106
+}
187
+
107
+
188
+static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,
108
DO_VSHRN_ALL(vshrn, DO_SHR)
189
+ uint64_t val64, unsigned int size)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
190
+{
113
+{
191
+ STM32F4xxSyscfgState *s = opaque;
114
+ if (val > max) {
192
+ uint32_t value = val64;
115
+ *satp = true;
193
+
116
+ return max;
194
+ trace_stm32f4xx_syscfg_write(value, addr);
117
+ } else if (val < min) {
195
+
118
+ *satp = true;
196
+ switch (addr) {
119
+ return min;
197
+ case SYSCFG_MEMRMP:
120
+ } else {
198
+ qemu_log_mask(LOG_UNIMP,
121
+ return val;
199
+ "%s: Changing the memory mapping isn't supported " \
200
+ "in QEMU\n", __func__);
201
+ return;
202
+ case SYSCFG_PMC:
203
+ qemu_log_mask(LOG_UNIMP,
204
+ "%s: Changing the memory mapping isn't supported " \
205
+ "in QEMU\n", __func__);
206
+ return;
207
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
208
+ s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);
209
+ return;
210
+ case SYSCFG_CMPCR:
211
+ s->syscfg_cmpcr = value;
212
+ return;
213
+ default:
214
+ qemu_log_mask(LOG_GUEST_ERROR,
215
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
216
+ }
122
+ }
217
+}
123
+}
218
+
124
+
219
+static const MemoryRegionOps stm32f4xx_syscfg_ops = {
125
+/* Saturating narrowing right shifts */
220
+ .read = stm32f4xx_syscfg_read,
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
221
+ .write = stm32f4xx_syscfg_write,
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
222
+ .endianness = DEVICE_NATIVE_ENDIAN,
128
+ void *vm, uint32_t shift) \
223
+};
129
+ { \
224
+
130
+ LTYPE *m = vm; \
225
+static void stm32f4xx_syscfg_init(Object *obj)
131
+ TYPE *d = vd; \
226
+{
132
+ uint16_t mask = mve_element_mask(env); \
227
+ STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);
133
+ bool qc = false; \
228
+
134
+ unsigned le; \
229
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
230
+
136
+ bool sat = false; \
231
+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
232
+ TYPE_STM32F4XX_SYSCFG, 0x400);
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
233
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
234
+
140
+ } \
235
+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);
141
+ if (qc) { \
236
+ qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
142
+ env->vfp.qc[0] = qc; \
237
+}
143
+ } \
238
+
144
+ mve_advance_vpt(env); \
239
+static const VMStateDescription vmstate_stm32f4xx_syscfg = {
240
+ .name = TYPE_STM32F4XX_SYSCFG,
241
+ .version_id = 1,
242
+ .minimum_version_id = 1,
243
+ .fields = (VMStateField[]) {
244
+ VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),
245
+ VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),
246
+ VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,
247
+ SYSCFG_NUM_EXTICR),
248
+ VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),
249
+ VMSTATE_END_OF_LIST()
250
+ }
145
+ }
251
+};
146
+
252
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
253
+static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
254
+{
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
255
+ DeviceClass *dc = DEVICE_CLASS(klass);
150
+
256
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
257
+ dc->reset = stm32f4xx_syscfg_reset;
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
258
+ dc->vmsd = &vmstate_stm32f4xx_syscfg;
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
259
+}
154
+
260
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
261
+static const TypeInfo stm32f4xx_syscfg_info = {
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
262
+ .name = TYPE_STM32F4XX_SYSCFG,
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
263
+ .parent = TYPE_SYS_BUS_DEVICE,
158
+
264
+ .instance_size = sizeof(STM32F4xxSyscfgState),
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
265
+ .instance_init = stm32f4xx_syscfg_init,
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
266
+ .class_init = stm32f4xx_syscfg_class_init,
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
267
+};
162
+
268
+
163
+#define DO_SHRN_SB(N, M, SATP) \
269
+static void stm32f4xx_syscfg_register_types(void)
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
270
+{
165
+#define DO_SHRN_UB(N, M, SATP) \
271
+ type_register_static(&stm32f4xx_syscfg_info);
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
272
+}
167
+#define DO_SHRUN_B(N, M, SATP) \
273
+
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
274
+type_init(stm32f4xx_syscfg_register_types)
169
+
275
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
170
+#define DO_SHRN_SH(N, M, SATP) \
276
index XXXXXXX..XXXXXXX 100644
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
277
--- a/default-configs/arm-softmmu.mak
172
+#define DO_SHRN_UH(N, M, SATP) \
278
+++ b/default-configs/arm-softmmu.mak
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
279
@@ -XXX,XX +XXX,XX @@ CONFIG_Z2=y
174
+#define DO_SHRUN_H(N, M, SATP) \
280
CONFIG_COLLIE=y
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
281
CONFIG_ASPEED_SOC=y
176
+
282
CONFIG_NETDUINO2=y
177
+#define DO_RSHRN_SB(N, M, SATP) \
283
+CONFIG_NETDUINOPLUS2=y
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
284
CONFIG_MPS2=y
179
+#define DO_RSHRN_UB(N, M, SATP) \
285
CONFIG_RASPI=y
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
286
CONFIG_DIGIC=y
181
+#define DO_RSHRUN_B(N, M, SATP) \
287
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
288
index XXXXXXX..XXXXXXX 100644
183
+
289
--- a/hw/arm/Kconfig
184
+#define DO_RSHRN_SH(N, M, SATP) \
290
+++ b/hw/arm/Kconfig
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
291
@@ -XXX,XX +XXX,XX @@ config NETDUINO2
186
+#define DO_RSHRN_UH(N, M, SATP) \
292
bool
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
293
select STM32F205_SOC
188
+#define DO_RSHRUN_H(N, M, SATP) \
294
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
295
+config NETDUINOPLUS2
190
+
296
+ bool
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
297
+ select STM32F405_SOC
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
298
+
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
299
config NSERIES
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
300
bool
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
301
select OMAP
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
302
@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC
197
+
303
select STM32F2XX_ADC
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
304
select STM32F2XX_SPI
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
305
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
306
+config STM32F405_SOC
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
307
+ bool
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
308
+ select ARM_V7M
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
309
+ select STM32F4XX_SYSCFG
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
310
+
205
index XXXXXXX..XXXXXXX 100644
311
config XLNX_ZYNQMP_ARM
206
--- a/target/arm/translate-mve.c
312
bool
207
+++ b/target/arm/translate-mve.c
313
select AHCI
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
314
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
209
DO_2SHIFT_N(VSHRNT, vshrnt)
315
index XXXXXXX..XXXXXXX 100644
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
316
--- a/hw/misc/Kconfig
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
317
+++ b/hw/misc/Kconfig
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
318
@@ -XXX,XX +XXX,XX @@ config IMX
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
319
config STM32F2XX_SYSCFG
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
320
bool
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
321
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
322
+config STM32F4XX_SYSCFG
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
323
+ bool
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
324
+
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
325
config MIPS_ITU
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
326
bool
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
327
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
328
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
329
index XXXXXXX..XXXXXXX 100644
330
--- a/hw/misc/trace-events
331
+++ b/hw/misc/trace-events
332
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
333
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
334
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
335
336
+# stm32f4xx_syscfg
337
+stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
338
+stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
339
+stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
340
+stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
341
+
342
# tz-mpc.c
343
tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
344
tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
345
--
224
--
346
2.20.1
225
2.20.1
347
226
348
227
diff view generated by jsdifflib
New patch
[PULL 19/24] target/arm: Implement MVE VSHLC
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 2 ++
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
14
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/mve.decode
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
33
+
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
119
--
120
2.20.1
121
122
diff view generated by jsdifflib
New patch
[PULL 20/24] target/arm: Implement MVE VADDLV
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 3 ++
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
82
}
83
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
85
+{
86
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
95
+
96
+ if (!dc_isar_feature(aa32_mve, s)) {
97
+ return false;
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
108
+ }
109
+
110
+ /*
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
145
+}
146
+
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
148
{
149
TCGv_ptr qd;
150
--
151
2.20.1
152
153
diff view generated by jsdifflib
New patch
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
1
The MVE extension to v8.1M includes some new shift instructions which
2
sit entirely within the non-coprocessor part of the encoding space
3
and which operate only on general-purpose registers. They take up
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
with Rm == 13 or 15.
6
7
Implement the long shifts by immediate, which perform shifts on a
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
an immediate shift count between 1 and 32.
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
27
---
28
target/arm/helper-mve.h | 3 ++
29
target/arm/translate.h | 1 +
30
target/arm/t32.decode | 28 +++++++++++++
31
target/arm/mve_helper.c | 10 +++++
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
33
5 files changed, 132 insertions(+)
34
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
38
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
83
{
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
133
return true;
134
}
135
136
+/*
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
229
--
230
2.20.1
231
232
diff view generated by jsdifflib
[PULL 07/15] hw/arm/allwinner-a10: Move SoC definitions out of header
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE long shifts by register, which perform shifts on a
2
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
These definitions are specific to the A10 SoC and don't need
3
the shift count in another general-purpose register, which might be
4
to be exported to the different Allwinner peripherals.
4
either positive or negative.
5
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
Message-id: 20191230110953.25496-4-f4bug@amsat.org
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
10
---
15
---
11
include/hw/arm/allwinner-a10.h | 6 ------
16
target/arm/helper-mve.h | 6 +++
12
hw/arm/allwinner-a10.c | 6 ++++++
17
target/arm/translate.h | 1 +
13
2 files changed, 6 insertions(+), 6 deletions(-)
18
target/arm/t32.decode | 16 +++++--
14
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
15
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
16
index XXXXXXX..XXXXXXX 100644
21
5 files changed, 182 insertions(+), 3 deletions(-)
17
--- a/include/hw/arm/allwinner-a10.h
22
18
+++ b/include/hw/arm/allwinner-a10.h
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-mve.h
26
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
30
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
19
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@
20
#include "target/arm/cpu.h"
56
&mcrr !extern cp opc1 crm rt rt2
21
57
22
58
&mve_shl_ri rdalo rdahi shim
23
-#define AW_A10_PIC_REG_BASE 0x01c20400
59
+&mve_shl_rr rdalo rdahi rm
24
-#define AW_A10_PIT_REG_BASE 0x01c20c00
60
25
-#define AW_A10_UART0_REG_BASE 0x01c28000
61
# rdahi: bits [3:1] from insn, bit 0 is 1
26
-#define AW_A10_EMAC_BASE 0x01c0b000
62
# rdalo: bits [3:1] from insn, bit 0 is 0
27
-#define AW_A10_SATA_BASE 0x01c18000
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
28
-
99
-
29
#define AW_A10_SDRAM_BASE 0x40000000
100
# Data-processing (register-shifted register)
30
101
31
#define TYPE_AW_A10 "allwinner-a10"
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
32
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
33
index XXXXXXX..XXXXXXX 100644
104
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/allwinner-a10.c
105
--- a/target/arm/mve_helper.c
35
+++ b/hw/arm/allwinner-a10.c
106
+++ b/target/arm/mve_helper.c
36
@@ -XXX,XX +XXX,XX @@
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
37
#include "hw/misc/unimp.h"
108
return rdm;
38
#include "sysemu/sysemu.h"
109
}
39
110
40
+#define AW_A10_PIC_REG_BASE 0x01c20400
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
41
+#define AW_A10_PIT_REG_BASE 0x01c20c00
112
+{
42
+#define AW_A10_UART0_REG_BASE 0x01c28000
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
43
+#define AW_A10_EMAC_BASE 0x01c0b000
114
+}
44
+#define AW_A10_SATA_BASE 0x01c18000
115
+
45
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
46
static void aw_a10_init(Object *obj)
117
+{
47
{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
48
AwA10State *s = AW_A10(obj);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
49
--
291
--
50
2.20.1
292
2.20.1
51
293
52
294
diff view generated by jsdifflib
[PULL 15/15] target/arm: Set ISSIs16Bit in make_issinfo
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE shifts by immediate, which perform shifts
2
2
on a single general-purpose register.
3
During the conversion to decodetree, the setting of
3
4
ISSIs16Bit got lost. This causes the guest os to
4
These patterns overlap with the long-shift-by-immediates,
5
incorrectly adjust trapping memory operations.
5
so we have to rearrange the grouping a little here.
6
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
9
Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200117004618.2742-3-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
14
---
10
---
15
target/arm/translate.c | 3 +++
11
target/arm/helper-mve.h | 3 ++
16
1 file changed, 3 insertions(+)
12
target/arm/translate.h | 1 +
17
13
target/arm/t32.decode | 31 ++++++++++++++-----
14
target/arm/mve_helper.c | 10 ++++++
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
16
5 files changed, 104 insertions(+), 9 deletions(-)
17
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
21
+++ b/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
45
@@ -XXX,XX +XXX,XX @@
46
47
&mve_shl_ri rdalo rdahi shim
48
&mve_shl_rr rdalo rdahi rm
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
105
}
106
+
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
108
+{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
110
+}
111
+
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
113
+{
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
115
+}
18
diff --git a/target/arm/translate.c b/target/arm/translate.c
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
117
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate.c
118
--- a/target/arm/translate.c
21
+++ b/target/arm/translate.c
119
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
23
/* ISS not valid if writeback */
121
24
if (p && !w) {
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
25
ret = rd;
123
{
26
+ if (s->base.pc_next - s->pc_curr == 2) {
124
- TCGv_i32 t = tcg_temp_new_i32();
27
+ ret |= ISSIs16Bit;
125
+ TCGv_i32 t;
28
+ }
126
29
} else {
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
30
ret = ISSInvalid;
128
+ if (sh == 32) {
31
}
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
154
}
155
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
157
+{
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
32
--
211
--
33
2.20.1
212
2.20.1
34
213
35
214
diff view generated by jsdifflib
[PULL 03/15] hw/arm: Add the STM32F4xx SoC
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Alistair Francis <alistair@alistair23.me>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
Signed-off-by: Alistair Francis <alistair@alistair23.me>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
7
---
7
---
8
hw/arm/Makefile.objs | 1 +
8
target/arm/helper-mve.h | 2 ++
9
include/hw/arm/stm32f405_soc.h | 73 ++++++++
9
target/arm/translate.h | 1 +
10
hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++
10
target/arm/t32.decode | 18 ++++++++++++++----
11
MAINTAINERS | 8 +
11
target/arm/mve_helper.c | 10 ++++++++++
12
4 files changed, 384 insertions(+)
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
create mode 100644 include/hw/arm/stm32f405_soc.h
13
5 files changed, 57 insertions(+), 4 deletions(-)
14
create mode 100644 hw/arm/stm32f405_soc.c
15
14
16
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Makefile.objs
17
--- a/target/arm/helper-mve.h
19
+++ b/hw/arm/Makefile.objs
18
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STRONGARM) += strongarm.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
21
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
20
22
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
23
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
24
+obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
25
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
26
obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
27
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
26
index XXXXXXX..XXXXXXX 100644
28
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
27
--- a/target/arm/translate.h
29
new file mode 100644
28
+++ b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
31
--- /dev/null
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
32
+++ b/include/hw/arm/stm32f405_soc.h
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
33
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
34
+/*
42
&mve_shl_ri rdalo rdahi shim
35
+ * STM32F405 SoC
43
&mve_shl_rr rdalo rdahi rm
36
+ *
44
&mve_sh_ri rda shim
37
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
45
+&mve_sh_rr rda rm
38
+ *
46
39
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
47
# rdahi: bits [3:1] from insn, bit 0 is 1
40
+ * of this software and associated documentation files (the "Software"), to deal
48
# rdalo: bits [3:1] from insn, bit 0 is 0
41
+ * in the Software without restriction, including without limitation the rights
42
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
43
+ * copies of the Software, and to permit persons to whom the Software is
44
+ * furnished to do so, subject to the following conditions:
45
+ *
46
+ * The above copyright notice and this permission notice shall be included in
47
+ * all copies or substantial portions of the Software.
48
+ *
49
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
50
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
51
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
52
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
53
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
54
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
55
+ * THE SOFTWARE.
56
+ */
57
+
58
+#ifndef HW_ARM_STM32F405_SOC_H
59
+#define HW_ARM_STM32F405_SOC_H
60
+
61
+#include "hw/misc/stm32f4xx_syscfg.h"
62
+#include "hw/timer/stm32f2xx_timer.h"
63
+#include "hw/char/stm32f2xx_usart.h"
64
+#include "hw/adc/stm32f2xx_adc.h"
65
+#include "hw/misc/stm32f4xx_exti.h"
66
+#include "hw/or-irq.h"
67
+#include "hw/ssi/stm32f2xx_spi.h"
68
+#include "hw/arm/armv7m.h"
69
+
70
+#define TYPE_STM32F405_SOC "stm32f405-soc"
71
+#define STM32F405_SOC(obj) \
72
+ OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
73
+
74
+#define STM_NUM_USARTS 7
75
+#define STM_NUM_TIMERS 4
76
+#define STM_NUM_ADCS 6
77
+#define STM_NUM_SPIS 6
78
+
79
+#define FLASH_BASE_ADDRESS 0x08000000
80
+#define FLASH_SIZE (1024 * 1024)
81
+#define SRAM_BASE_ADDRESS 0x20000000
82
+#define SRAM_SIZE (192 * 1024)
83
+
84
+typedef struct STM32F405State {
85
+ /*< private >*/
86
+ SysBusDevice parent_obj;
87
+ /*< public >*/
88
+
89
+ char *cpu_type;
90
+
91
+ ARMv7MState armv7m;
92
+
93
+ STM32F4xxSyscfgState syscfg;
94
+ STM32F4xxExtiState exti;
95
+ STM32F2XXUsartState usart[STM_NUM_USARTS];
96
+ STM32F2XXTimerState timer[STM_NUM_TIMERS];
97
+ qemu_or_irq adc_irqs;
98
+ STM32F2XXADCState adc[STM_NUM_ADCS];
99
+ STM32F2XXSPIState spi[STM_NUM_SPIS];
100
+
101
+ MemoryRegion sram;
102
+ MemoryRegion flash;
103
+ MemoryRegion flash_alias;
104
+} STM32F405State;
105
+
106
+#endif
107
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
108
new file mode 100644
109
index XXXXXXX..XXXXXXX
110
--- /dev/null
111
+++ b/hw/arm/stm32f405_soc.c
112
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@
113
+/*
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
114
+ * STM32F405 SoC
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
115
+ *
52
&mve_sh_ri shim=%imm5_12_6
116
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
117
+ *
54
118
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
55
{
119
+ * of this software and associated documentation files (the "Software"), to deal
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
120
+ * in the Software without restriction, including without limitation the rights
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
121
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
122
+ * copies of the Software, and to permit persons to whom the Software is
59
}
123
+ * furnished to do so, subject to the following conditions:
60
124
+ *
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
125
+ * The above copyright notice and this permission notice shall be included in
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
126
+ * all copies or substantial portions of the Software.
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
127
+ *
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
128
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
65
+ {
129
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
130
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
131
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
132
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
133
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
134
+ * THE SOFTWARE.
135
+ */
136
+
137
+#include "qemu/osdep.h"
138
+#include "qapi/error.h"
139
+#include "qemu-common.h"
140
+#include "exec/address-spaces.h"
141
+#include "sysemu/sysemu.h"
142
+#include "hw/arm/stm32f405_soc.h"
143
+#include "hw/misc/unimp.h"
144
+
145
+#define SYSCFG_ADD 0x40013800
146
+static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
147
+ 0x40004C00, 0x40005000, 0x40011400,
148
+ 0x40007800, 0x40007C00 };
149
+/* At the moment only Timer 2 to 5 are modelled */
150
+static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
151
+ 0x40000800, 0x40000C00 };
152
+#define ADC_ADDR 0x40012000
153
+static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
154
+ 0x40013400, 0x40015000, 0x40015400 };
155
+#define EXTI_ADDR 0x40013C00
156
+
157
+#define SYSCFG_IRQ 71
158
+static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
159
+static const int timer_irq[] = { 28, 29, 30, 50 };
160
+#define ADC_IRQ 18
161
+static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };
162
+static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
163
+ 40, 40, 40, 40, 40} ;
164
+
165
+
166
+static void stm32f405_soc_initfn(Object *obj)
167
+{
168
+ STM32F405State *s = STM32F405_SOC(obj);
169
+ int i;
170
+
171
+ sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
172
+ TYPE_ARMV7M);
173
+
174
+ sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
175
+ TYPE_STM32F4XX_SYSCFG);
176
+
177
+ for (i = 0; i < STM_NUM_USARTS; i++) {
178
+ sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
179
+ sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
180
+ }
69
+ }
181
+
70
+
182
+ for (i = 0; i < STM_NUM_TIMERS; i++) {
71
+ {
183
+ sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
184
+ sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
185
+ }
75
+ }
186
+
76
+
187
+ for (i = 0; i < STM_NUM_ADCS; i++) {
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
188
+ sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
189
+ TYPE_STM32F2XX_ADC);
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
92
+}
93
+
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
95
+{
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
97
+}
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate.c
101
+++ b/target/arm/translate.c
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
190
+ }
119
+ }
191
+
120
+
192
+ for (i = 0; i < STM_NUM_SPIS; i++) {
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
193
+ sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
194
+ TYPE_STM32F2XX_SPI);
123
+ return true;
195
+ }
196
+
197
+ sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
198
+ TYPE_STM32F4XX_EXTI);
199
+}
124
+}
200
+
125
+
201
+static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
202
+{
127
+{
203
+ STM32F405State *s = STM32F405_SOC(dev_soc);
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
204
+ MemoryRegion *system_memory = get_system_memory();
205
+ DeviceState *dev, *armv7m;
206
+ SysBusDevice *busdev;
207
+ Error *err = NULL;
208
+ int i;
209
+
210
+ memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE,
211
+ &err);
212
+ if (err != NULL) {
213
+ error_propagate(errp, err);
214
+ return;
215
+ }
216
+ memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias",
217
+ &s->flash, 0, FLASH_SIZE);
218
+
219
+ memory_region_set_readonly(&s->flash, true);
220
+ memory_region_set_readonly(&s->flash_alias, true);
221
+
222
+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
223
+ memory_region_add_subregion(system_memory, 0, &s->flash_alias);
224
+
225
+ memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
226
+ &err);
227
+ if (err != NULL) {
228
+ error_propagate(errp, err);
229
+ return;
230
+ }
231
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
232
+
233
+ armv7m = DEVICE(&s->armv7m);
234
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
235
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
236
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
237
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
238
+ "memory", &error_abort);
239
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
240
+ if (err != NULL) {
241
+ error_propagate(errp, err);
242
+ return;
243
+ }
244
+
245
+ /* System configuration controller */
246
+ dev = DEVICE(&s->syscfg);
247
+ object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
248
+ if (err != NULL) {
249
+ error_propagate(errp, err);
250
+ return;
251
+ }
252
+ busdev = SYS_BUS_DEVICE(dev);
253
+ sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
254
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
255
+
256
+ /* Attach UART (uses USART registers) and USART controllers */
257
+ for (i = 0; i < STM_NUM_USARTS; i++) {
258
+ dev = DEVICE(&(s->usart[i]));
259
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
260
+ object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
261
+ if (err != NULL) {
262
+ error_propagate(errp, err);
263
+ return;
264
+ }
265
+ busdev = SYS_BUS_DEVICE(dev);
266
+ sysbus_mmio_map(busdev, 0, usart_addr[i]);
267
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
268
+ }
269
+
270
+ /* Timer 2 to 5 */
271
+ for (i = 0; i < STM_NUM_TIMERS; i++) {
272
+ dev = DEVICE(&(s->timer[i]));
273
+ qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
274
+ object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
275
+ if (err != NULL) {
276
+ error_propagate(errp, err);
277
+ return;
278
+ }
279
+ busdev = SYS_BUS_DEVICE(dev);
280
+ sysbus_mmio_map(busdev, 0, timer_addr[i]);
281
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
282
+ }
283
+
284
+ /* ADC device, the IRQs are ORed together */
285
+ object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
286
+ sizeof(s->adc_irqs), TYPE_OR_IRQ,
287
+ &err, NULL);
288
+ if (err != NULL) {
289
+ error_propagate(errp, err);
290
+ return;
291
+ }
292
+ object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
293
+ "num-lines", &err);
294
+ object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
295
+ if (err != NULL) {
296
+ error_propagate(errp, err);
297
+ return;
298
+ }
299
+ qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
300
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
301
+
302
+ dev = DEVICE(&(s->adc[i]));
303
+ object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
304
+ if (err != NULL) {
305
+ error_propagate(errp, err);
306
+ return;
307
+ }
308
+ busdev = SYS_BUS_DEVICE(dev);
309
+ sysbus_mmio_map(busdev, 0, ADC_ADDR);
310
+ sysbus_connect_irq(busdev, 0,
311
+ qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
312
+
313
+ /* SPI devices */
314
+ for (i = 0; i < STM_NUM_SPIS; i++) {
315
+ dev = DEVICE(&(s->spi[i]));
316
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
317
+ if (err != NULL) {
318
+ error_propagate(errp, err);
319
+ return;
320
+ }
321
+ busdev = SYS_BUS_DEVICE(dev);
322
+ sysbus_mmio_map(busdev, 0, spi_addr[i]);
323
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
324
+ }
325
+
326
+ /* EXTI device */
327
+ dev = DEVICE(&s->exti);
328
+ object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
329
+ if (err != NULL) {
330
+ error_propagate(errp, err);
331
+ return;
332
+ }
333
+ busdev = SYS_BUS_DEVICE(dev);
334
+ sysbus_mmio_map(busdev, 0, EXTI_ADDR);
335
+ for (i = 0; i < 16; i++) {
336
+ sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
337
+ }
338
+ for (i = 0; i < 16; i++) {
339
+ qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
340
+ }
341
+
342
+ create_unimplemented_device("timer[7]", 0x40001400, 0x400);
343
+ create_unimplemented_device("timer[12]", 0x40001800, 0x400);
344
+ create_unimplemented_device("timer[6]", 0x40001000, 0x400);
345
+ create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
346
+ create_unimplemented_device("timer[14]", 0x40002000, 0x400);
347
+ create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
348
+ create_unimplemented_device("WWDG", 0x40002C00, 0x400);
349
+ create_unimplemented_device("IWDG", 0x40003000, 0x400);
350
+ create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
351
+ create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
352
+ create_unimplemented_device("I2C1", 0x40005400, 0x400);
353
+ create_unimplemented_device("I2C2", 0x40005800, 0x400);
354
+ create_unimplemented_device("I2C3", 0x40005C00, 0x400);
355
+ create_unimplemented_device("CAN1", 0x40006400, 0x400);
356
+ create_unimplemented_device("CAN2", 0x40006800, 0x400);
357
+ create_unimplemented_device("PWR", 0x40007000, 0x400);
358
+ create_unimplemented_device("DAC", 0x40007400, 0x400);
359
+ create_unimplemented_device("timer[1]", 0x40010000, 0x400);
360
+ create_unimplemented_device("timer[8]", 0x40010400, 0x400);
361
+ create_unimplemented_device("SDIO", 0x40012C00, 0x400);
362
+ create_unimplemented_device("timer[9]", 0x40014000, 0x400);
363
+ create_unimplemented_device("timer[10]", 0x40014400, 0x400);
364
+ create_unimplemented_device("timer[11]", 0x40014800, 0x400);
365
+ create_unimplemented_device("GPIOA", 0x40020000, 0x400);
366
+ create_unimplemented_device("GPIOB", 0x40020400, 0x400);
367
+ create_unimplemented_device("GPIOC", 0x40020800, 0x400);
368
+ create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
369
+ create_unimplemented_device("GPIOE", 0x40021000, 0x400);
370
+ create_unimplemented_device("GPIOF", 0x40021400, 0x400);
371
+ create_unimplemented_device("GPIOG", 0x40021800, 0x400);
372
+ create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
373
+ create_unimplemented_device("GPIOI", 0x40022000, 0x400);
374
+ create_unimplemented_device("CRC", 0x40023000, 0x400);
375
+ create_unimplemented_device("RCC", 0x40023800, 0x400);
376
+ create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
377
+ create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
378
+ create_unimplemented_device("DMA1", 0x40026000, 0x400);
379
+ create_unimplemented_device("DMA2", 0x40026400, 0x400);
380
+ create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
381
+ create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
382
+ create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
383
+ create_unimplemented_device("DCMI", 0x50050000, 0x400);
384
+ create_unimplemented_device("RNG", 0x50060800, 0x400);
385
+}
129
+}
386
+
130
+
387
+static Property stm32f405_soc_properties[] = {
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
388
+ DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
389
+ DEFINE_PROP_END_OF_LIST(),
390
+};
391
+
392
+static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
393
+{
132
+{
394
+ DeviceClass *dc = DEVICE_CLASS(klass);
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
395
+
396
+ dc->realize = stm32f405_soc_realize;
397
+ dc->props = stm32f405_soc_properties;
398
+ /* No vmstate or reset required: device has no internal state */
399
+}
134
+}
400
+
135
+
401
+static const TypeInfo stm32f405_soc_info = {
136
/*
402
+ .name = TYPE_STM32F405_SOC,
137
* Multiply and multiply accumulate
403
+ .parent = TYPE_SYS_BUS_DEVICE,
138
*/
404
+ .instance_size = sizeof(STM32F405State),
405
+ .instance_init = stm32f405_soc_initfn,
406
+ .class_init = stm32f405_soc_class_init,
407
+};
408
+
409
+static void stm32f405_soc_types(void)
410
+{
411
+ type_register_static(&stm32f405_soc_info);
412
+}
413
+
414
+type_init(stm32f405_soc_types)
415
diff --git a/MAINTAINERS b/MAINTAINERS
416
index XXXXXXX..XXXXXXX 100644
417
--- a/MAINTAINERS
418
+++ b/MAINTAINERS
419
@@ -XXX,XX +XXX,XX @@ F: hw/adc/*
420
F: hw/ssi/stm32f2xx_spi.c
421
F: include/hw/*/stm32*.h
422
423
+STM32F405
424
+M: Alistair Francis <alistair@alistair23.me>
425
+M: Peter Maydell <peter.maydell@linaro.org>
426
+S: Maintained
427
+F: hw/arm/stm32f405_soc.c
428
+F: hw/misc/stm32f4xx_syscfg.c
429
+F: hw/misc/stm32f4xx_exti.c
430
+
431
Netduino 2
432
M: Alistair Francis <alistair@alistair23.me>
433
M: Peter Maydell <peter.maydell@linaro.org>
434
--
139
--
435
2.20.1
140
2.20.1
436
141
437
142
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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