From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/misc/Makefile.objs | 1 +

include/hw/misc/stm32f4xx_syscfg.h | 61 ++++++++++

hw/misc/stm32f4xx_syscfg.c | 171 +++++++++++++++++++++++++++++

default-configs/arm-softmmu.mak | 1 +

hw/arm/Kconfig | 9 ++

hw/misc/Kconfig | 3 +

hw/misc/trace-events | 6 +

7 files changed, 252 insertions(+)

create mode 100644 include/hw/misc/stm32f4xx_syscfg.h

create mode 100644 hw/misc/stm32f4xx_syscfg.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o

common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o

common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o

common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o

+common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o

obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o

obj-$(CONFIG_MIPS_CPS) += mips_cpc.o

obj-$(CONFIG_MIPS_ITU) += mips_itu.o

diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/stm32f4xx_syscfg.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F4xx SYSCFG

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#ifndef HW_STM_SYSCFG_H

+#define HW_STM_SYSCFG_H

+

+#include "hw/sysbus.h"

+#include "hw/hw.h"

+

+#define SYSCFG_MEMRMP 0x00

+#define SYSCFG_PMC 0x04

+#define SYSCFG_EXTICR1 0x08

+#define SYSCFG_EXTICR2 0x0C

+#define SYSCFG_EXTICR3 0x10

+#define SYSCFG_EXTICR4 0x14

+#define SYSCFG_CMPCR 0x20

+

+#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"

+#define STM32F4XX_SYSCFG(obj) \

+ OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG)

+

+#define SYSCFG_NUM_EXTICR 4

+

+typedef struct {

+ /* <private> */

+ SysBusDevice parent_obj;

+

+ /* <public> */

+ MemoryRegion mmio;

+

+ uint32_t syscfg_memrmp;

+ uint32_t syscfg_pmc;

+ uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];

+ uint32_t syscfg_cmpcr;

+

+ qemu_irq irq;

+ qemu_irq gpio_out[16];

+} STM32F4xxSyscfgState;

+

+#endif

diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/stm32f4xx_syscfg.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F4xx SYSCFG

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "trace.h"

+#include "hw/irq.h"

+#include "migration/vmstate.h"

+#include "hw/misc/stm32f4xx_syscfg.h"

+

+static void stm32f4xx_syscfg_reset(DeviceState *dev)

+{

+ STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);

+

+ s->syscfg_memrmp = 0x00000000;

+ s->syscfg_pmc = 0x00000000;

+ s->syscfg_exticr[0] = 0x00000000;

+ s->syscfg_exticr[1] = 0x00000000;

+ s->syscfg_exticr[2] = 0x00000000;

+ s->syscfg_exticr[3] = 0x00000000;

+ s->syscfg_cmpcr = 0x00000000;

+}

+

+static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)

+{

+ STM32F4xxSyscfgState *s = opaque;

+ int icrreg = irq / 4;

+ int startbit = (irq & 3) * 4;

+ uint8_t config = config = irq / 16;

+

+ trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);

+

+ g_assert(icrreg < SYSCFG_NUM_EXTICR);

+

+ if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {

+ qemu_set_irq(s->gpio_out[irq], level);

+ trace_stm32f4xx_pulse_exti(irq);

+ }

+}

+

+static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,

+ unsigned int size)

+{

+ STM32F4xxSyscfgState *s = opaque;

+

+ trace_stm32f4xx_syscfg_read(addr);

+

+ switch (addr) {

+ case SYSCFG_MEMRMP:

+ return s->syscfg_memrmp;

+ case SYSCFG_PMC:

+ return s->syscfg_pmc;

+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:

+ return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];

+ case SYSCFG_CMPCR:

+ return s->syscfg_cmpcr;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);

+ return 0;

+ }

+}

+

+static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,

+ uint64_t val64, unsigned int size)

+{

+ STM32F4xxSyscfgState *s = opaque;

+ uint32_t value = val64;

+

+ trace_stm32f4xx_syscfg_write(value, addr);

+

+ switch (addr) {

+ case SYSCFG_MEMRMP:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Changing the memory mapping isn't supported " \

+ "in QEMU\n", __func__);

+ return;

+ case SYSCFG_PMC:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Changing the memory mapping isn't supported " \

+ "in QEMU\n", __func__);

+ return;

+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:

+ s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);

+ return;

+ case SYSCFG_CMPCR:

+ s->syscfg_cmpcr = value;

+ return;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);

+ }

+}

+

+static const MemoryRegionOps stm32f4xx_syscfg_ops = {

+ .read = stm32f4xx_syscfg_read,

+ .write = stm32f4xx_syscfg_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+};

+

+static void stm32f4xx_syscfg_init(Object *obj)

+{

+ STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);

+

+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

+

+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,

+ TYPE_STM32F4XX_SYSCFG, 0x400);

+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

+

+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);

+ qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);

+}

+

+static const VMStateDescription vmstate_stm32f4xx_syscfg = {

+ .name = TYPE_STM32F4XX_SYSCFG,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),

+ VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),

+ VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,

+ SYSCFG_NUM_EXTICR),

+ VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = stm32f4xx_syscfg_reset;

+ dc->vmsd = &vmstate_stm32f4xx_syscfg;

+}

+

+static const TypeInfo stm32f4xx_syscfg_info = {

+ .name = TYPE_STM32F4XX_SYSCFG,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(STM32F4xxSyscfgState),

+ .instance_init = stm32f4xx_syscfg_init,

+ .class_init = stm32f4xx_syscfg_class_init,

+};

+

+static void stm32f4xx_syscfg_register_types(void)

+{

+ type_register_static(&stm32f4xx_syscfg_info);

+}

+

+type_init(stm32f4xx_syscfg_register_types)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak

index XXXXXXX..XXXXXXX 100644

--- a/default-configs/arm-softmmu.mak

+++ b/default-configs/arm-softmmu.mak

@@ -XXX,XX +XXX,XX @@ CONFIG_Z2=y

CONFIG_COLLIE=y

CONFIG_ASPEED_SOC=y

CONFIG_NETDUINO2=y

+CONFIG_NETDUINOPLUS2=y

CONFIG_MPS2=y

CONFIG_RASPI=y

CONFIG_DIGIC=y

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config NETDUINO2

bool

select STM32F205_SOC

+config NETDUINOPLUS2

+ bool

+ select STM32F405_SOC

+

config NSERIES

bool

select OMAP

@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC

select STM32F2XX_ADC

select STM32F2XX_SPI

+config STM32F405_SOC

+ bool

+ select ARM_V7M

+ select STM32F4XX_SYSCFG

+

config XLNX_ZYNQMP_ARM

bool

select AHCI

diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/Kconfig

+++ b/hw/misc/Kconfig

@@ -XXX,XX +XXX,XX @@ config IMX

config STM32F2XX_SYSCFG

bool

+config STM32F4XX_SYSCFG

+ bool

+

config MIPS_ITU

bool

diff --git a/hw/misc/trace-events b/hw/misc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/trace-events

+++ b/hw/misc/trace-events

@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"

mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64

mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"

+# stm32f4xx_syscfg

+stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"

+stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"

+stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "

+stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""

+

# tz-mpc.c

tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"

tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"

--

2.20.1

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: ef941d59fd8658589d34ed432e1d6dfdcf7fb1d0.1576658572.git.alistair@alistair23.me

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/misc/Makefile.objs | 1 +

include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++

hw/misc/stm32f4xx_exti.c | 188 +++++++++++++++++++++++++++++++

hw/arm/Kconfig | 1 +

hw/misc/Kconfig | 3 +

hw/misc/trace-events | 5 +

6 files changed, 258 insertions(+)

create mode 100644 include/hw/misc/stm32f4xx_exti.h

create mode 100644 hw/misc/stm32f4xx_exti.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o

common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o

common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o

common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o

+common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o

obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o

obj-$(CONFIG_MIPS_CPS) += mips_cpc.o

obj-$(CONFIG_MIPS_ITU) += mips_itu.o

diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/stm32f4xx_exti.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F4XX EXTI

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#ifndef HW_STM_EXTI_H

+#define HW_STM_EXTI_H

+

+#include "hw/sysbus.h"

+#include "hw/hw.h"

+

+#define EXTI_IMR 0x00

+#define EXTI_EMR 0x04

+#define EXTI_RTSR 0x08

+#define EXTI_FTSR 0x0C

+#define EXTI_SWIER 0x10

+#define EXTI_PR 0x14

+

+#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"

+#define STM32F4XX_EXTI(obj) \

+ OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI)

+

+#define NUM_GPIO_EVENT_IN_LINES 16

+#define NUM_INTERRUPT_OUT_LINES 16

+

+typedef struct {

+ SysBusDevice parent_obj;

+

+ MemoryRegion mmio;

+

+ uint32_t exti_imr;

+ uint32_t exti_emr;

+ uint32_t exti_rtsr;

+ uint32_t exti_ftsr;

+ uint32_t exti_swier;

+ uint32_t exti_pr;

+

+ qemu_irq irq[NUM_INTERRUPT_OUT_LINES];

+} STM32F4xxExtiState;

+

+#endif

diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/stm32f4xx_exti.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F4XX EXTI

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "trace.h"

+#include "hw/irq.h"

+#include "migration/vmstate.h"

+#include "hw/misc/stm32f4xx_exti.h"

+

+static void stm32f4xx_exti_reset(DeviceState *dev)

+{

+ STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);

+

+ s->exti_imr = 0x00000000;

+ s->exti_emr = 0x00000000;

+ s->exti_rtsr = 0x00000000;

+ s->exti_ftsr = 0x00000000;

+ s->exti_swier = 0x00000000;

+ s->exti_pr = 0x00000000;

+}

+

+static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)

+{

+ STM32F4xxExtiState *s = opaque;

+

+ trace_stm32f4xx_exti_set_irq(irq, level);

+

+ if (((1 << irq) & s->exti_rtsr) && level) {

+ /* Rising Edge */

+ s->exti_pr |= 1 << irq;

+ }

+

+ if (((1 << irq) & s->exti_ftsr) && !level) {

+ /* Falling Edge */

+ s->exti_pr |= 1 << irq;

+ }

+

+ if (!((1 << irq) & s->exti_imr)) {

+ /* Interrupt is masked */

+ return;

+ }

+ qemu_irq_pulse(s->irq[irq]);

+}

+

+static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,

+ unsigned int size)

+{

+ STM32F4xxExtiState *s = opaque;

+

+ trace_stm32f4xx_exti_read(addr);

+

+ switch (addr) {

+ case EXTI_IMR:

+ return s->exti_imr;

+ case EXTI_EMR:

+ return s->exti_emr;

+ case EXTI_RTSR:

+ return s->exti_rtsr;

+ case EXTI_FTSR:

+ return s->exti_ftsr;

+ case EXTI_SWIER:

+ return s->exti_swier;

+ case EXTI_PR:

+ return s->exti_pr;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);

+ return 0;

+ }

+ return 0;

+}

+

+static void stm32f4xx_exti_write(void *opaque, hwaddr addr,

+ uint64_t val64, unsigned int size)

+{

+ STM32F4xxExtiState *s = opaque;

+ uint32_t value = (uint32_t) val64;

+

+ trace_stm32f4xx_exti_write(addr, value);

+

+ switch (addr) {

+ case EXTI_IMR:

+ s->exti_imr = value;

+ return;

+ case EXTI_EMR:

+ s->exti_emr = value;

+ return;

+ case EXTI_RTSR:

+ s->exti_rtsr = value;

+ return;

+ case EXTI_FTSR:

+ s->exti_ftsr = value;

+ return;

+ case EXTI_SWIER:

+ s->exti_swier = value;

+ return;

+ case EXTI_PR:

+ /* This bit is cleared by writing a 1 to it */

+ s->exti_pr &= ~value;

+ return;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);

+ }

+}

+

+static const MemoryRegionOps stm32f4xx_exti_ops = {

+ .read = stm32f4xx_exti_read,

+ .write = stm32f4xx_exti_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+};

+

+static void stm32f4xx_exti_init(Object *obj)

+{

+ STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);

+ int i;

+

+ for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {

+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);

+ }

+

+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,

+ TYPE_STM32F4XX_EXTI, 0x400);

+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

+

+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,

+ NUM_GPIO_EVENT_IN_LINES);

+}

+

+static const VMStateDescription vmstate_stm32f4xx_exti = {

+ .name = TYPE_STM32F4XX_EXTI,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = stm32f4xx_exti_reset;

+ dc->vmsd = &vmstate_stm32f4xx_exti;

+}

+

+static const TypeInfo stm32f4xx_exti_info = {

+ .name = TYPE_STM32F4XX_EXTI,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(STM32F4xxExtiState),

+ .instance_init = stm32f4xx_exti_init,

+ .class_init = stm32f4xx_exti_class_init,

+};

+

+static void stm32f4xx_exti_register_types(void)

+{

+ type_register_static(&stm32f4xx_exti_info);

+}

+

+type_init(stm32f4xx_exti_register_types)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC

bool

select ARM_V7M

select STM32F4XX_SYSCFG

+ select STM32F4XX_EXTI

config XLNX_ZYNQMP_ARM

bool

diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/Kconfig

+++ b/hw/misc/Kconfig

@@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG

config STM32F4XX_SYSCFG

bool

+config STM32F4XX_EXTI

+ bool

+

config MIPS_ITU

bool

diff --git a/hw/misc/trace-events b/hw/misc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/trace-events

+++ b/hw/misc/trace-events

@@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"

stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "

stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""

+# stm32f4xx_exti

+stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"

+stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "

+stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""

+

# tz-mpc.c

tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"

tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"

--

2.20.1

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/Makefile.objs | 1 +

include/hw/arm/stm32f405_soc.h | 73 ++++++++

hw/arm/stm32f405_soc.c | 302 +++++++++++++++++++++++++++++++++

MAINTAINERS | 8 +

4 files changed, 384 insertions(+)

create mode 100644 include/hw/arm/stm32f405_soc.h

create mode 100644 hw/arm/stm32f405_soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STRONGARM) += strongarm.o

obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o

obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o

obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o

+obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o

obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o

obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o

obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o

diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/arm/stm32f405_soc.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F405 SoC

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#ifndef HW_ARM_STM32F405_SOC_H

+#define HW_ARM_STM32F405_SOC_H

+

+#include "hw/misc/stm32f4xx_syscfg.h"

+#include "hw/timer/stm32f2xx_timer.h"

+#include "hw/char/stm32f2xx_usart.h"

+#include "hw/adc/stm32f2xx_adc.h"

+#include "hw/misc/stm32f4xx_exti.h"

+#include "hw/or-irq.h"

+#include "hw/ssi/stm32f2xx_spi.h"

+#include "hw/arm/armv7m.h"

+

+#define TYPE_STM32F405_SOC "stm32f405-soc"

+#define STM32F405_SOC(obj) \

+ OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)

+

+#define STM_NUM_USARTS 7

+#define STM_NUM_TIMERS 4

+#define STM_NUM_ADCS 6

+#define STM_NUM_SPIS 6

+

+#define FLASH_BASE_ADDRESS 0x08000000

+#define FLASH_SIZE (1024 * 1024)

+#define SRAM_BASE_ADDRESS 0x20000000

+#define SRAM_SIZE (192 * 1024)

+

+typedef struct STM32F405State {

+ /*< private >*/

+ SysBusDevice parent_obj;

+ /*< public >*/

+

+ char *cpu_type;

+

+ ARMv7MState armv7m;

+

+ STM32F4xxSyscfgState syscfg;

+ STM32F4xxExtiState exti;

+ STM32F2XXUsartState usart[STM_NUM_USARTS];

+ STM32F2XXTimerState timer[STM_NUM_TIMERS];

+ qemu_or_irq adc_irqs;

+ STM32F2XXADCState adc[STM_NUM_ADCS];

+ STM32F2XXSPIState spi[STM_NUM_SPIS];

+

+ MemoryRegion sram;

+ MemoryRegion flash;

+ MemoryRegion flash_alias;

+} STM32F405State;

+

+#endif

diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/stm32f405_soc.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F405 SoC

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu-common.h"

+#include "exec/address-spaces.h"

+#include "sysemu/sysemu.h"

+#include "hw/arm/stm32f405_soc.h"

+#include "hw/misc/unimp.h"

+

+#define SYSCFG_ADD 0x40013800

+static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,

+ 0x40004C00, 0x40005000, 0x40011400,

+ 0x40007800, 0x40007C00 };

+/* At the moment only Timer 2 to 5 are modelled */

+static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,

+ 0x40000800, 0x40000C00 };

+#define ADC_ADDR 0x40012000

+static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,

+ 0x40013400, 0x40015000, 0x40015400 };

+#define EXTI_ADDR 0x40013C00

+

+#define SYSCFG_IRQ 71

+static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };

+static const int timer_irq[] = { 28, 29, 30, 50 };

+#define ADC_IRQ 18

+static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };

+static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,

+ 40, 40, 40, 40, 40} ;

+

+

+static void stm32f405_soc_initfn(Object *obj)

+{

+ STM32F405State *s = STM32F405_SOC(obj);

+ int i;

+

+ sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),

+ TYPE_ARMV7M);

+

+ sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),

+ TYPE_STM32F4XX_SYSCFG);

+

+ for (i = 0; i < STM_NUM_USARTS; i++) {

+ sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],

+ sizeof(s->usart[i]), TYPE_STM32F2XX_USART);

+ }

+

+ for (i = 0; i < STM_NUM_TIMERS; i++) {

+ sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],

+ sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);

+ }

+

+ for (i = 0; i < STM_NUM_ADCS; i++) {

+ sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),

+ TYPE_STM32F2XX_ADC);

+ }

+

+ for (i = 0; i < STM_NUM_SPIS; i++) {

+ sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),

+ TYPE_STM32F2XX_SPI);

+ }

+

+ sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),

+ TYPE_STM32F4XX_EXTI);

+}

+

+static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)

+{

+ STM32F405State *s = STM32F405_SOC(dev_soc);

+ MemoryRegion *system_memory = get_system_memory();

+ DeviceState *dev, *armv7m;

+ SysBusDevice *busdev;

+ Error *err = NULL;

+ int i;

+

+ memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE,

+ &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias",

+ &s->flash, 0, FLASH_SIZE);

+

+ memory_region_set_readonly(&s->flash, true);

+ memory_region_set_readonly(&s->flash_alias, true);

+

+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);

+ memory_region_add_subregion(system_memory, 0, &s->flash_alias);

+

+ memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,

+ &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);

+

+ armv7m = DEVICE(&s->armv7m);

+ qdev_prop_set_uint32(armv7m, "num-irq", 96);

+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);

+ qdev_prop_set_bit(armv7m, "enable-bitband", true);

+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),

+ "memory", &error_abort);

+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+

+ /* System configuration controller */

+ dev = DEVICE(&s->syscfg);

+ object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, SYSCFG_ADD);

+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));

+

+ /* Attach UART (uses USART registers) and USART controllers */

+ for (i = 0; i < STM_NUM_USARTS; i++) {

+ dev = DEVICE(&(s->usart[i]));

+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));

+ object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, usart_addr[i]);

+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));

+ }

+

+ /* Timer 2 to 5 */

+ for (i = 0; i < STM_NUM_TIMERS; i++) {

+ dev = DEVICE(&(s->timer[i]));

+ qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);

+ object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, timer_addr[i]);

+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));

+ }

+

+ /* ADC device, the IRQs are ORed together */

+ object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,

+ sizeof(s->adc_irqs), TYPE_OR_IRQ,

+ &err, NULL);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,

+ "num-lines", &err);

+ object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,

+ qdev_get_gpio_in(armv7m, ADC_IRQ));

+

+ dev = DEVICE(&(s->adc[i]));

+ object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, ADC_ADDR);

+ sysbus_connect_irq(busdev, 0,

+ qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));

+

+ /* SPI devices */

+ for (i = 0; i < STM_NUM_SPIS; i++) {

+ dev = DEVICE(&(s->spi[i]));

+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, spi_addr[i]);

+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));

+ }

+

+ /* EXTI device */

+ dev = DEVICE(&s->exti);

+ object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, EXTI_ADDR);

+ for (i = 0; i < 16; i++) {

+ sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));

+ }

+ for (i = 0; i < 16; i++) {

+ qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));

+ }

+

+ create_unimplemented_device("timer[7]", 0x40001400, 0x400);

+ create_unimplemented_device("timer[12]", 0x40001800, 0x400);

+ create_unimplemented_device("timer[6]", 0x40001000, 0x400);

+ create_unimplemented_device("timer[13]", 0x40001C00, 0x400);

+ create_unimplemented_device("timer[14]", 0x40002000, 0x400);

+ create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);

+ create_unimplemented_device("WWDG", 0x40002C00, 0x400);

+ create_unimplemented_device("IWDG", 0x40003000, 0x400);

+ create_unimplemented_device("I2S2ext", 0x40003000, 0x400);

+ create_unimplemented_device("I2S3ext", 0x40004000, 0x400);

+ create_unimplemented_device("I2C1", 0x40005400, 0x400);

+ create_unimplemented_device("I2C2", 0x40005800, 0x400);

+ create_unimplemented_device("I2C3", 0x40005C00, 0x400);

+ create_unimplemented_device("CAN1", 0x40006400, 0x400);

+ create_unimplemented_device("CAN2", 0x40006800, 0x400);

+ create_unimplemented_device("PWR", 0x40007000, 0x400);

+ create_unimplemented_device("DAC", 0x40007400, 0x400);

+ create_unimplemented_device("timer[1]", 0x40010000, 0x400);

+ create_unimplemented_device("timer[8]", 0x40010400, 0x400);

+ create_unimplemented_device("SDIO", 0x40012C00, 0x400);

+ create_unimplemented_device("timer[9]", 0x40014000, 0x400);

+ create_unimplemented_device("timer[10]", 0x40014400, 0x400);

+ create_unimplemented_device("timer[11]", 0x40014800, 0x400);

+ create_unimplemented_device("GPIOA", 0x40020000, 0x400);

+ create_unimplemented_device("GPIOB", 0x40020400, 0x400);

+ create_unimplemented_device("GPIOC", 0x40020800, 0x400);

+ create_unimplemented_device("GPIOD", 0x40020C00, 0x400);

+ create_unimplemented_device("GPIOE", 0x40021000, 0x400);

+ create_unimplemented_device("GPIOF", 0x40021400, 0x400);

+ create_unimplemented_device("GPIOG", 0x40021800, 0x400);

+ create_unimplemented_device("GPIOH", 0x40021C00, 0x400);

+ create_unimplemented_device("GPIOI", 0x40022000, 0x400);

+ create_unimplemented_device("CRC", 0x40023000, 0x400);

+ create_unimplemented_device("RCC", 0x40023800, 0x400);

+ create_unimplemented_device("Flash Int", 0x40023C00, 0x400);

+ create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);

+ create_unimplemented_device("DMA1", 0x40026000, 0x400);

+ create_unimplemented_device("DMA2", 0x40026400, 0x400);

+ create_unimplemented_device("Ethernet", 0x40028000, 0x1400);

+ create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);

+ create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);

+ create_unimplemented_device("DCMI", 0x50050000, 0x400);

+ create_unimplemented_device("RNG", 0x50060800, 0x400);

+}

+

+static Property stm32f405_soc_properties[] = {

+ DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void stm32f405_soc_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->realize = stm32f405_soc_realize;

+ dc->props = stm32f405_soc_properties;

+ /* No vmstate or reset required: device has no internal state */

+}

+

+static const TypeInfo stm32f405_soc_info = {

+ .name = TYPE_STM32F405_SOC,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(STM32F405State),

+ .instance_init = stm32f405_soc_initfn,

+ .class_init = stm32f405_soc_class_init,

+};

+

+static void stm32f405_soc_types(void)

+{

+ type_register_static(&stm32f405_soc_info);

+}

+

+type_init(stm32f405_soc_types)

diff --git a/MAINTAINERS b/MAINTAINERS

index XXXXXXX..XXXXXXX 100644

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F: hw/adc/*

F: hw/ssi/stm32f2xx_spi.c

F: include/hw/*/stm32*.h

+STM32F405

+M: Alistair Francis <alistair@alistair23.me>

+M: Peter Maydell <peter.maydell@linaro.org>

+S: Maintained

+F: hw/arm/stm32f405_soc.c

+F: hw/misc/stm32f4xx_syscfg.c

+F: hw/misc/stm32f4xx_exti.c

+

Netduino 2

M: Alistair Francis <alistair@alistair23.me>

M: Peter Maydell <peter.maydell@linaro.org>

--

2.20.1

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: dad8d8d47f7625913e35e27a1c00f603a6b08f9a.1576658572.git.alistair@alistair23.me

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/Makefile.objs | 1 +

hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++

MAINTAINERS | 6 +++++

3 files changed, 59 insertions(+)

create mode 100644 hw/arm/netduinoplus2.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o

obj-$(CONFIG_MICROBIT) += microbit.o

obj-$(CONFIG_MUSICPAL) += musicpal.o

obj-$(CONFIG_NETDUINO2) += netduino2.o

+obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o

obj-$(CONFIG_NSERIES) += nseries.o

obj-$(CONFIG_SX1) += omap_sx1.o

obj-$(CONFIG_CHEETAH) += palm.o

diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/netduinoplus2.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Netduino Plus 2 Machine Model

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "hw/boards.h"

+#include "hw/qdev-properties.h"

+#include "qemu/error-report.h"

+#include "hw/arm/stm32f405_soc.h"

+#include "hw/arm/boot.h"

+

+static void netduinoplus2_init(MachineState *machine)

+{

+ DeviceState *dev;

+

+ dev = qdev_create(NULL, TYPE_STM32F405_SOC);

+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));

+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);

+

+ armv7m_load_kernel(ARM_CPU(first_cpu),

+ machine->kernel_filename,

+ FLASH_SIZE);

+}