Latest arm queue, a mixed bag of features and bug fixes.

The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (2020-01-17 12:13:17 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200117-1

for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:

target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +0000)

Add model of the Netduino Plus 2 board

Some allwinner-a10 code cleanup

New test cases for cubieboard

target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle

i.MX: add an emulation for RNGC device

target/arm: adjust program counter for wfi exception in AArch32

arm/gicv3: update virtual irq state after IAR register read

Set IL bit correctly for syndrome information for data aborts

Alistair Francis (4):

hw/misc: Add the STM32F4xx Sysconfig device

hw/misc: Add the STM32F4xx EXTI device

hw/arm: Add the STM32F4xx SoC

hw/arm: Add the Netduino Plus 2

Jeff Kubascik (3):

target/arm: adjust program counter for wfi exception in AArch32

arm/gicv3: update virtual irq state after IAR register read

target/arm: Return correct IL bit in merge_syn_data_abort

Martin Kaiser (1):

i.MX: add an emulation for RNGC

Masahiro Yamada (1):

target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle

Philippe Mathieu-Daudé (5):

tests/boot_linux_console: Add initrd test for the CubieBoard

tests/boot_linux_console: Add a SD card test for the CubieBoard

hw/arm/allwinner-a10: Move SoC definitions out of header

hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()

hw/arm/allwinner-a10: Remove local qemu_irq variables

Richard Henderson (1):

target/arm: Set ISSIs16Bit in make_issinfo

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>

hw/misc/Makefile.objs | 1 +

include/hw/misc/stm32f4xx_exti.h | 60 ++++++++++

hw/misc/stm32f4xx_exti.c | 188 +++++++++++++++++++++++++++++++

hw/arm/Kconfig | 1 +

hw/misc/Kconfig | 3 +

hw/misc/trace-events | 5 +

6 files changed, 258 insertions(+)

create mode 100644 include/hw/misc/stm32f4xx_exti.h

create mode 100644 hw/misc/stm32f4xx_exti.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o

common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o

common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o

common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o

+common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o

obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o

obj-$(CONFIG_MIPS_CPS) += mips_cpc.o

obj-$(CONFIG_MIPS_ITU) += mips_itu.o

diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/stm32f4xx_exti.h

@@ -XXX,XX +XXX,XX @@

+ * STM32F4XX EXTI

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+

+#ifndef HW_STM_EXTI_H

+#define HW_STM_EXTI_H

+

+#include "hw/sysbus.h"

+#include "hw/hw.h"

+

+#define EXTI_IMR 0x00

+#define EXTI_EMR 0x04

+#define EXTI_RTSR 0x08

+#define EXTI_FTSR 0x0C

+#define EXTI_SWIER 0x10

+#define EXTI_PR 0x14

+

+#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"

+#define STM32F4XX_EXTI(obj) \

+ OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI)

+

+#define NUM_GPIO_EVENT_IN_LINES 16

+#define NUM_INTERRUPT_OUT_LINES 16

+

+typedef struct {

+ SysBusDevice parent_obj;

+

+ MemoryRegion mmio;

+

+ uint32_t exti_imr;

+ uint32_t exti_emr;

+ uint32_t exti_rtsr;

+ uint32_t exti_ftsr;

+ uint32_t exti_swier;

+ uint32_t exti_pr;

+

+ qemu_irq irq[NUM_INTERRUPT_OUT_LINES];

+} STM32F4xxExtiState;

+

+#endif

diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/stm32f4xx_exti.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F4XX EXTI

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "trace.h"

+#include "hw/irq.h"

+#include "migration/vmstate.h"

+#include "hw/misc/stm32f4xx_exti.h"

+

+static void stm32f4xx_exti_reset(DeviceState *dev)

+ STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);

+

+ s->exti_imr = 0x00000000;

+ s->exti_emr = 0x00000000;

+ s->exti_rtsr = 0x00000000;

+ s->exti_ftsr = 0x00000000;

+ s->exti_swier = 0x00000000;

+ s->exti_pr = 0x00000000;

+static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)

+{

+ STM32F4xxExtiState *s = opaque;

+

+ trace_stm32f4xx_exti_set_irq(irq, level);

+

+ if (((1 << irq) & s->exti_rtsr) && level) {

+ /* Rising Edge */

+ s->exti_pr |= 1 << irq;

+ }

+

+ if (((1 << irq) & s->exti_ftsr) && !level) {

+ /* Falling Edge */

+ s->exti_pr |= 1 << irq;

+ }

+

+ if (!((1 << irq) & s->exti_imr)) {

+ /* Interrupt is masked */

+ return;

+ }

+ qemu_irq_pulse(s->irq[irq]);

+}

+

+static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,

+ unsigned int size)

+{

+ STM32F4xxExtiState *s = opaque;

+

+ trace_stm32f4xx_exti_read(addr);

+

+ switch (addr) {

+ case EXTI_IMR:

+ return s->exti_imr;

+ case EXTI_EMR:

+ return s->exti_emr;

+ case EXTI_RTSR:

+ return s->exti_rtsr;

+ case EXTI_FTSR:

+ return s->exti_ftsr;

+ case EXTI_SWIER:

+ return s->exti_swier;

+ case EXTI_PR:

+ return s->exti_pr;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);

+ return 0;

+ }

+ return 0;

+}

+

+static void stm32f4xx_exti_write(void *opaque, hwaddr addr,

+ uint64_t val64, unsigned int size)

+{

+ STM32F4xxExtiState *s = opaque;

+ uint32_t value = (uint32_t) val64;

+

+ trace_stm32f4xx_exti_write(addr, value);

+

+ switch (addr) {

+ case EXTI_IMR:

+ s->exti_imr = value;

+ return;

+ case EXTI_EMR:

+ s->exti_emr = value;

+ return;

+ case EXTI_RTSR:

+ s->exti_rtsr = value;

+ return;

+ case EXTI_FTSR:

+ s->exti_ftsr = value;

+ return;

+ case EXTI_SWIER:

+ s->exti_swier = value;

+ return;

+ case EXTI_PR:

+ /* This bit is cleared by writing a 1 to it */

+ s->exti_pr &= ~value;

+ return;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);

+ }

+}

+

+static const MemoryRegionOps stm32f4xx_exti_ops = {

+ .read = stm32f4xx_exti_read,

+ .write = stm32f4xx_exti_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+};

+

+static void stm32f4xx_exti_init(Object *obj)

+{

+ STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);

+ int i;

+

+ for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {

+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);

+ }

+

+ memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,

+ TYPE_STM32F4XX_EXTI, 0x400);

+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

+

+ qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,

+ NUM_GPIO_EVENT_IN_LINES);

+}

+

+static const VMStateDescription vmstate_stm32f4xx_exti = {

+ .name = TYPE_STM32F4XX_EXTI,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),

+ VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = stm32f4xx_exti_reset;

+ dc->vmsd = &vmstate_stm32f4xx_exti;

+}

+

+static const TypeInfo stm32f4xx_exti_info = {

+ .name = TYPE_STM32F4XX_EXTI,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(STM32F4xxExtiState),

+ .instance_init = stm32f4xx_exti_init,

+ .class_init = stm32f4xx_exti_class_init,

+};

+

+static void stm32f4xx_exti_register_types(void)

+{

+ type_register_static(&stm32f4xx_exti_info);

+}

+

+type_init(stm32f4xx_exti_register_types)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC

bool

select ARM_V7M

select STM32F4XX_SYSCFG

+ select STM32F4XX_EXTI

config XLNX_ZYNQMP_ARM

bool

diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig

--- a/hw/misc/Kconfig

+++ b/hw/misc/Kconfig

@@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG

config STM32F4XX_SYSCFG

bool

+config STM32F4XX_EXTI

+ bool

+

config MIPS_ITU

bool

diff --git a/hw/misc/trace-events b/hw/misc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/trace-events

+++ b/hw/misc/trace-events

@@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"

stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "

stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""

+# stm32f4xx_exti

+stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"

+stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "

+stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""

+

# tz-mpc.c

tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"

tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>

hw/arm/Makefile.objs | 1 +

hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++

MAINTAINERS | 6 +++++

3 files changed, 59 insertions(+)

create mode 100644 hw/arm/netduinoplus2.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o

obj-$(CONFIG_MICROBIT) += microbit.o

obj-$(CONFIG_MUSICPAL) += musicpal.o

obj-$(CONFIG_NETDUINO2) += netduino2.o

+obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o

obj-$(CONFIG_NSERIES) += nseries.o

obj-$(CONFIG_SX1) += omap_sx1.o

obj-$(CONFIG_CHEETAH) += palm.o

diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/netduinoplus2.c

@@ -XXX,XX +XXX,XX @@

+ * Netduino Plus 2 Machine Model

+ *

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "hw/boards.h"

+#include "hw/qdev-properties.h"

+#include "qemu/error-report.h"

+#include "hw/arm/stm32f405_soc.h"

+#include "hw/arm/boot.h"

+

+static void netduinoplus2_init(MachineState *machine)

+ DeviceState *dev;

+

+ dev = qdev_create(NULL, TYPE_STM32F405_SOC);

+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));

+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);

+

+ armv7m_load_kernel(ARM_CPU(first_cpu),

+ machine->kernel_filename,

+ FLASH_SIZE);

+static void netduinoplus2_machine_init(MachineClass *mc)

+{

+ mc->desc = "Netduino Plus 2 Machine";

+ mc->init = netduinoplus2_init;

+}

+

+DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)

diff --git a/MAINTAINERS b/MAINTAINERS

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>

S: Maintained

F: hw/arm/netduino2.c

+Netduino Plus 2

+M: Alistair Francis <alistair@alistair23.me>

+M: Peter Maydell <peter.maydell@linaro.org>

+S: Maintained

+F: hw/arm/netduinoplus2.c

+

SmartFusion2

M: Subbaraya Sundeep <sundeep.lkml@gmail.com>

M: Peter Maydell <peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By calling qdev_pass_gpios() we don't need to hold a copy of the

IRQs from the INTC into the SoC state.

Instead of filling an array of qemu_irq and passing it around, we

can now directly call qdev_get_gpio_in() on the SoC.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20191230110953.25496-5-f4bug@amsat.org

include/hw/arm/allwinner-a10.h | 1 -

hw/arm/allwinner-a10.c | 24 +++++++++++-------------

2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h

--- a/include/hw/arm/allwinner-a10.h

+++ b/include/hw/arm/allwinner-a10.h

@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {

/*< public >*/

ARMCPU cpu;

- qemu_irq irq[AW_A10_PIC_INT_NR];

AwA10PITState timer;

AwA10PICState intc;

AwEmacState emac;

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/allwinner-a10.c

+++ b/hw/arm/allwinner-a10.c

@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)

AwA10State *s = AW_A10(dev);

SysBusDevice *sysbusdev;

- uint8_t i;

qemu_irq fiq, irq;

Error *err = NULL;

@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)

sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);

sysbus_connect_irq(sysbusdev, 0, irq);

sysbus_connect_irq(sysbusdev, 1, fiq);

- for (i = 0; i < AW_A10_PIC_INT_NR; i++) {

- s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);

- }

+ qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);

object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);

if (err != NULL) {

@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)

From: Martin Kaiser <martin@kaiser.cx>

Add an emulation for the RNGC random number generator and the compatible

RNGB variant. These peripherals are included (at least) in imx25 and

imx35 chipsets.

The emulation supports the initial self test, reseeding the prng and

reading random numbers.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>

hw/misc/Makefile.objs | 1 +

include/hw/arm/fsl-imx25.h | 5 +

include/hw/misc/imx_rngc.h | 35 +++++

hw/arm/fsl-imx25.c | 11 ++

hw/misc/imx_rngc.c | 278 +++++++++++++++++++++++++++++++++++++

5 files changed, 330 insertions(+)

create mode 100644 include/hw/misc/imx_rngc.h

create mode 100644 hw/misc/imx_rngc.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o

common-obj-$(CONFIG_IMX) += imx2_wdt.o

common-obj-$(CONFIG_IMX) += imx7_snvs.o

common-obj-$(CONFIG_IMX) += imx7_gpr.o

+common-obj-$(CONFIG_IMX) += imx_rngc.o

common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o

common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o

common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o

diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/fsl-imx25.h

+++ b/include/hw/arm/fsl-imx25.h

@@ -XXX,XX +XXX,XX @@

#include "hw/timer/imx_gpt.h"

#include "hw/timer/imx_epit.h"

#include "hw/net/imx_fec.h"

+#include "hw/misc/imx_rngc.h"

#include "hw/i2c/imx_i2c.h"

#include "hw/gpio/imx_gpio.h"

#include "exec/memory.h"

@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {

IMXGPTState gpt[FSL_IMX25_NUM_GPTS];

IMXEPITState epit[FSL_IMX25_NUM_EPITS];

IMXFECState fec;

+ IMXRNGCState rngc;

IMXI2CState i2c[FSL_IMX25_NUM_I2CS];

IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];

MemoryRegion rom[2];

@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {

#define FSL_IMX25_GPIO4_SIZE 0x4000

#define FSL_IMX25_GPIO3_ADDR 0x53FA4000

#define FSL_IMX25_GPIO3_SIZE 0x4000

+#define FSL_IMX25_RNGC_ADDR 0x53FB0000

+#define FSL_IMX25_RNGC_SIZE 0x4000

#define FSL_IMX25_GPIO1_ADDR 0x53FCC000

#define FSL_IMX25_GPIO1_SIZE 0x4000

#define FSL_IMX25_GPIO2_ADDR 0x53FD0000

@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {

#define FSL_IMX25_EPIT1_IRQ 28

#define FSL_IMX25_EPIT2_IRQ 27

#define FSL_IMX25_FEC_IRQ 57

+#define FSL_IMX25_RNGC_IRQ 22

#define FSL_IMX25_I2C1_IRQ 3

#define FSL_IMX25_I2C2_IRQ 4

#define FSL_IMX25_I2C3_IRQ 10

diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/imx_rngc.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Freescale i.MX RNGC emulation

+ *

+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#ifndef IMX_RNGC_H

+#define IMX_RNGC_H

+

+#include "hw/sysbus.h"

+

+#define TYPE_IMX_RNGC "imx.rngc"

+#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC)

+

+typedef struct IMXRNGCState {

+ /*< private >*/

+ SysBusDevice parent_obj;

+

+ /*< public >*/

+ MemoryRegion iomem;

+

+ uint8_t op_self_test;

+ uint8_t op_seed;

+ uint8_t mask;

+ bool auto_seed;

+

+ QEMUBH *self_test_bh;

+ QEMUBH *seed_bh;

+ qemu_irq irq;

+} IMXRNGCState;

+

+#endif /* IMX_RNGC_H */

diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/fsl-imx25.c

+++ b/hw/arm/fsl-imx25.c

@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)

sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);

+ sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),

+ TYPE_IMX_RNGC);

+

for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {

sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),

TYPE_IMX_I2C);

@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)

sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,

qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));

+ object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,

+ qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));

/* Initialize all I2C */

for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {

diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/imx_rngc.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Freescale i.MX RNGC emulation

+ *

+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ *

+ * This driver provides the minimum functionality to initialize and seed

+ * an rngc and to read random numbers. The rngb that is found in imx25

+ * chipsets is also supported.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/main-loop.h"

+#include "qemu/module.h"

+#include "qemu/log.h"

+#include "qemu/guest-random.h"

+#include "hw/irq.h"

+#include "hw/misc/imx_rngc.h"

+#include "migration/vmstate.h"

+

+#define RNGC_NAME "i.MX RNGC"

+

+#define RNGC_VER_ID 0x00

+#define RNGC_COMMAND 0x04

+#define RNGC_CONTROL 0x08

+#define RNGC_STATUS 0x0C

+#define RNGC_FIFO 0x14

+

+/* These version info are reported by the rngb in an imx258 chip. */

+#define RNG_TYPE_RNGB 0x1

+#define V_MAJ 0x2

+#define V_MIN 0x40

+

+#define RNGC_CMD_BIT_SW_RST 0x40

+#define RNGC_CMD_BIT_CLR_ERR 0x20

+#define RNGC_CMD_BIT_CLR_INT 0x10

+#define RNGC_CMD_BIT_SEED 0x02

+#define RNGC_CMD_BIT_SELF_TEST 0x01

+

+#define RNGC_CTRL_BIT_MASK_ERR 0x40

+#define RNGC_CTRL_BIT_MASK_DONE 0x20

+#define RNGC_CTRL_BIT_AUTO_SEED 0x10

+

+/* the current status for self-test and seed operations */

+#define OP_IDLE 0

+#define OP_RUN 1

+#define OP_DONE 2

+

+static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size)

+ IMXRNGCState *s = IMX_RNGC(opaque);

+ uint64_t val = 0;

+

+ switch (offset) {

+ case RNGC_VER_ID:

+ val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN;

+

+ case RNGC_COMMAND:

+ if (s->op_seed == OP_RUN) {

+ val |= RNGC_CMD_BIT_SEED;

+ }

+ if (s->op_self_test == OP_RUN) {

+ val |= RNGC_CMD_BIT_SELF_TEST;

+ }

+ break;

+

+ case RNGC_CONTROL:

+ /*

+ * The CTL_ACC and VERIF_MODE bits are not supported yet.

+ * They read as 0.

+ */

+ val |= s->mask;

+ if (s->auto_seed) {

+ val |= RNGC_CTRL_BIT_AUTO_SEED;

+ }

+ /*

+ * We don't have an internal fifo like the real hardware.

+ * There's no need for strategy to handle fifo underflows.

+ * We return the FIFO_UFLOW_RESPONSE bits as 0.

+ */

+ break;

+

+ case RNGC_STATUS:

+ /*

+ * We never report any statistics test or self-test errors or any

+ * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0.

+ */

+

+ /*

+ * We don't have an internal fifo, see above. Therefore, we

+ * report back the default fifo size (5 32-bit words) and

+ * indicate that our fifo is always full.

+ */

+ val |= 5 << 12 | 5 << 8;

+

+ /* We always have a new seed available. */

+ val |= 1 << 6;

+

+ if (s->op_seed == OP_DONE) {

+ val |= 1 << 5;

+ }

+ if (s->op_self_test == OP_DONE) {

+ val |= 1 << 4;

+ }

+ if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) {

+ /*

+ * We're busy if self-test is running or if we're

+ * seeding the prng.

+ */

+ val |= 1 << 1;

+ } else {

+ /*

+ * We're ready to provide secure random numbers whenever

+ * we're not busy.

+ */

+ val |= 1;

+ }

+ break;

+

+ case RNGC_FIFO:

+ qemu_guest_getrandom_nofail(&val, sizeof(val));

+ break;

+ }

+

+ return val;

+}

+

+static void imx_rngc_do_reset(IMXRNGCState *s)

+{

+ s->op_self_test = OP_IDLE;

+ s->op_seed = OP_IDLE;

+ s->mask = 0;

+ s->auto_seed = false;

+}

+

+static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value,

+ unsigned size)

+{

+ IMXRNGCState *s = IMX_RNGC(opaque);

+

+ switch (offset) {

+ case RNGC_COMMAND:

+ if (value & RNGC_CMD_BIT_SW_RST) {

+ imx_rngc_do_reset(s);

+ }

+

+ /*

+ * For now, both CLR_ERR and CLR_INT clear the interrupt. We

+ * don't report any errors yet.

+ */

+ if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) {

+ qemu_irq_lower(s->irq);

+ }

+

+ if (value & RNGC_CMD_BIT_SEED) {

+ s->op_seed = OP_RUN;

+ qemu_bh_schedule(s->seed_bh);

+ }

+

+ if (value & RNGC_CMD_BIT_SELF_TEST) {

+ s->op_self_test = OP_RUN;

+ qemu_bh_schedule(s->self_test_bh);

+ }

+ break;

+

+ case RNGC_CONTROL:

+ /*

+ * The CTL_ACC and VERIF_MODE bits are not supported yet.

+ * We ignore them if they're set by the caller.

+ */

+

+ if (value & RNGC_CTRL_BIT_MASK_ERR) {

+ s->mask |= RNGC_CTRL_BIT_MASK_ERR;

+ } else {

+ s->mask &= ~RNGC_CTRL_BIT_MASK_ERR;

+ }

+

+ if (value & RNGC_CTRL_BIT_MASK_DONE) {

+ s->mask |= RNGC_CTRL_BIT_MASK_DONE;

+ } else {

+ s->mask &= ~RNGC_CTRL_BIT_MASK_DONE;

+ }

+

+ if (value & RNGC_CTRL_BIT_AUTO_SEED) {

+ s->auto_seed = true;

+ } else {

+ s->auto_seed = false;

+ }

+ break;

+static const MemoryRegionOps imx_rngc_ops = {

+ .read = imx_rngc_read,

+ .write = imx_rngc_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+};

+

+static void imx_rngc_self_test(void *opaque)

+ IMXRNGCState *s = IMX_RNGC(opaque);

+

+ s->op_self_test = OP_DONE;

+ if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {

+ qemu_irq_raise(s->irq);

+static void imx_rngc_seed(void *opaque)

+{

+ IMXRNGCState *s = IMX_RNGC(opaque);

+

+ s->op_seed = OP_DONE;

+ if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {

+ qemu_irq_raise(s->irq);

+ }

+}

+

+static void imx_rngc_realize(DeviceState *dev, Error **errp)

+{

+ IMXRNGCState *s = IMX_RNGC(dev);

+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

+

+ memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s,

+ TYPE_IMX_RNGC, 0x1000);

+ sysbus_init_mmio(sbd, &s->iomem);

+

+ sysbus_init_irq(sbd, &s->irq);

+ s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s);

+ s->seed_bh = qemu_bh_new(imx_rngc_seed, s);

+}

+

+static void imx_rngc_reset(DeviceState *dev)

+{

+ IMXRNGCState *s = IMX_RNGC(dev);

+

+ imx_rngc_do_reset(s);

+}

+

+static const VMStateDescription vmstate_imx_rngc = {

+ .name = RNGC_NAME,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT8(op_self_test, IMXRNGCState),

+ VMSTATE_UINT8(op_seed, IMXRNGCState),

+ VMSTATE_UINT8(mask, IMXRNGCState),

+ VMSTATE_BOOL(auto_seed, IMXRNGCState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void imx_rngc_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);