[PATCH] target/m68k: Allow movec only on 68010+

BALATON Zoltan posted 1 patch 1 week ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200114202226.E859E745702@zero.eik.bme.hu
Maintainers: Laurent Vivier <laurent@vivier.eu>
target/m68k/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] target/m68k: Allow movec only on 68010+

Posted by BALATON Zoltan 1 week ago
The movec opcode does not exist on 68000 and should raise an
exception. Fix the feature mask to only allow movec on newer 68k CPUs.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 target/m68k/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index fcdb7bc8e4..f19da064c8 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5988,7 +5988,7 @@ void register_m68k_insns (CPUM68KState *env)
     BASE(stop,      4e72, ffff);
     BASE(rte,       4e73, ffff);
     INSN(cf_movec,  4e7b, ffff, CF_ISA_A);
-    INSN(m68k_movec, 4e7a, fffe, M68000);
+    INSN(m68k_movec, 4e7a, fffe, FPU);
 #endif
     BASE(nop,       4e71, ffff);
     INSN(rtd,       4e74, ffff, RTD);
-- 
2.13.7


Re: [PATCH] target/m68k: Allow movec only on 68010+

Posted by Laurent Vivier 1 week ago
Le 14/01/2020 à 21:13, BALATON Zoltan a écrit :
> The movec opcode does not exist on 68000 and should raise an
> exception. Fix the feature mask to only allow movec on newer 68k CPUs.
> 
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>  target/m68k/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index fcdb7bc8e4..f19da064c8 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -5988,7 +5988,7 @@ void register_m68k_insns (CPUM68KState *env)
>      BASE(stop,      4e72, ffff);
>      BASE(rte,       4e73, ffff);
>      INSN(cf_movec,  4e7b, ffff, CF_ISA_A);
> -    INSN(m68k_movec, 4e7a, fffe, M68000);
> +    INSN(m68k_movec, 4e7a, fffe, FPU);
>  #endif
>      BASE(nop,       4e71, ffff);
>      INSN(rtd,       4e74, ffff, RTD);
> 

Good point. But as movec is not related to FPU I don't think this is the
good flag to use.

Lucien has sent a patch to fix this issue last year:

  [5/6] MOVEC insn. doesnt generate exception if wrong CR is accessed
  https://patchwork.kernel.org/patch/10997467/

it needs a rework (M680x0 feature flags are now specific to each CPU, so
the table cannot be set to the older one, 68010, and 68060 is missing)
but I think it's a better approach.

Thanks,
Laurent