[PULL 0/4] target-arm queue
[PULL 0/6] target-arm queue
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Arm patches for rc3 : just a handful of bug fixes.
1
Hi; here's a target-arm pull for rc2. Four arm-related fixes,
2
and a couple of bug fixes for other areas of the codebase
3
that seemed like they'd fallen through the cracks.
2
4
3
thanks
5
thanks
4
-- PMM
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-- PMM
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7
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The following changes since commit ccb86f079a9e4d94918086a9df18c1844347aff8:
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9
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The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
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Merge tag 'pull-nbd-2023-07-28' of https://repo.or.cz/qemu/ericb into staging (2023-07-28 09:56:57 -0700)
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230731
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for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
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for you to fetch changes up to 108e8180c6b0c315711aa54e914030a313505c17:
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target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
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gdbstub: Fix client Ctrl-C handling (2023-07-31 14:57:32 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
21
target-arm queue:
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* handle FTYPE flag correctly in v7M exception return
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* Don't build AArch64 decodetree files for qemu-system-arm
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for v7M CPUs with an FPU (v8M CPUs were already correct)
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* Fix TCG assert in v8.1M CSEL etc
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* versal: Add the CRP as unimplemented
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* Fix MemOp for STGP
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* Fix ISR_EL1 tracking when executing at EL2
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* gdbstub: Fix client Ctrl-C handling
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* Honor HCR_EL2.TID3 trapping requirements
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* kvm: Fix crash due to access uninitialized kvm_state
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* elf2dmp: Don't abandon when Prcb is set to 0
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28
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----------------------------------------------------------------
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----------------------------------------------------------------
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Edgar E. Iglesias (1):
30
Akihiko Odaki (1):
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hw/arm: versal: Add the CRP as unimplemented
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elf2dmp: Don't abandon when Prcb is set to 0
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32
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Jean-Hugues Deschênes (1):
33
Gavin Shan (1):
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target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
34
kvm: Fix crash due to access uninitialized kvm_state
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35
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Marc Zyngier (2):
36
Nicholas Piggin (1):
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target/arm: Fix ISR_EL1 tracking when executing at EL2
37
gdbstub: Fix client Ctrl-C handling
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
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38
38
include/hw/arm/xlnx-versal.h | 3 ++
39
Peter Maydell (2):
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hw/arm/xlnx-versal.c | 2 ++
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target/arm: Avoid writing to constant TCGv in trans_CSEL()
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target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
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target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm
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target/arm/m_helper.c | 7 ++--
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4 files changed, 89 insertions(+), 6 deletions(-)
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42
43
Richard Henderson (1):
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target/arm: Fix MemOp for STGP
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46
accel/kvm/kvm-all.c | 2 +-
47
contrib/elf2dmp/main.c | 5 +++++
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gdbstub/gdbstub.c | 13 +++++++++++--
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target/arm/tcg/translate-a64.c | 21 ++++++++++++++++++---
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target/arm/tcg/translate.c | 15 ++++++++-------
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target/arm/tcg/meson.build | 10 +++++++---
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6 files changed, 50 insertions(+), 16 deletions(-)
diff view generated by jsdifflib
[PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements
[PULL 1/6] target/arm: Fix MemOp for STGP
1
From: Marc Zyngier <maz@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
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2
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
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When converting to decodetree, the code to rebuild mop for the pair
4
registers traps to EL2, and QEMU has so far ignored this requirement.
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only made it into trans_STP and not into trans_STGP.
5
5
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1790
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while the hypervisor doesn't want to expose the feature to its guest.
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Fixes: 8c212eb6594 ("target/arm: Convert load/store-pair to decodetree")
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To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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case), and masks out the unsupported feature.
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Message-id: 20230726165416.309624-1-richard.henderson@linaro.org
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QEMU not honoring the trap request means that the guest observes
12
that the feature is present in the HW, starts using it, and dies
13
a horrible death when KVM injects an UNDEF, because the feature
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*really* isn't supported.
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Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
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Note that this change does not include trapping of the MVFR
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registers from AArch32 (they are accessed via the VMRS
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instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
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Signed-off-by: Marc Zyngier <maz@kernel.org>
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Tested-by: Will Deacon <will@kernel.org>
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Message-id: 20191123115618.29230-1-maz@kernel.org
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[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
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changed names of access functions to include _tid3]
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
12
---
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target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
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target/arm/tcg/translate-a64.c | 21 ++++++++++++++++++---
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1 file changed, 76 insertions(+)
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1 file changed, 18 insertions(+), 3 deletions(-)
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15
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/helper.c
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--- a/target/arm/tcg/translate-a64.c
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+++ b/target/arm/helper.c
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+++ b/target/arm/tcg/translate-a64.c
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
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@@ -XXX,XX +XXX,XX @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
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REGINFO_SENTINEL
21
MemOp mop;
40
};
22
TCGv_i128 tmp;
41
23
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
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+ /* STGP only comes in one size. */
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+ bool isread)
25
+ tcg_debug_assert(a->sz == MO_64);
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+{
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+
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
27
if (!dc_isar_feature(aa64_mte_insn_reg, s)) {
46
+ return CP_ACCESS_TRAP_EL2;
28
return false;
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}
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@@ -XXX,XX +XXX,XX @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
31
gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
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}
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- mop = finalize_memop(s, a->sz);
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- clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, mop);
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+ mop = finalize_memop(s, MO_64);
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+ clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << MO_64, mop);
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tcg_rt = cpu_reg(s, a->rt);
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tcg_rt2 = cpu_reg(s, a->rt2);
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42
- assert(a->sz == 3);
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+ /*
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+ * STGP is defined as two 8-byte memory operations and one tag operation.
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+ * We implement it as one single 16-byte memory operation for convenience.
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+ * Rebuild mop as for STP.
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+ * TODO: The atomicity with LSE2 is stronger than required.
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+ * Need a form of MO_ATOM_WITHIN16_PAIR that never requires
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+ * 16-byte atomicity.
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+ */
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+ mop = MO_128;
52
+ if (s->align_mem) {
53
+ mop |= MO_ALIGN_8;
47
+ }
54
+ }
48
+
55
+ mop = finalize_memop_pair(s, mop);
49
+ return CP_ACCESS_OK;
56
50
+}
57
tmp = tcg_temp_new_i128();
51
+
58
if (s->be_data == MO_LE) {
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ return access_aa64_tid3(env, ri, isread);
57
+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
61
+
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void register_cp_regs_for_features(ARMCPU *cpu)
63
{
64
/* Register all the coprocessor registers based on feature bits */
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@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_pfr0 },
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/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
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* the value of the GIC field until after we define these regs.
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@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
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{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_NO_RAW,
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+ .accessfn = access_aa32_tid3,
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.readfn = id_pfr1_read,
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.writefn = arm_cp_write_ignore },
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{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_dfr0 },
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{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_afr0 },
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{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr0 },
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{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr1 },
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr2 },
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{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
107
.access = PL1_R, .type = ARM_CP_CONST,
108
+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr3 },
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST,
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+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
118
+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
132
.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
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.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
59
--
358
2.20.1
60
2.34.1
359
360
diff view generated by jsdifflib
New patch
[PULL 2/6] elf2dmp: Don't abandon when Prcb is set to 0
1
From: Akihiko Odaki <akihiko.odaki@daynix.com>
1
2
3
Prcb may be set to 0 for some CPUs if the dump was taken before they
4
start. The dump may still contain valuable information for started CPUs
5
so don't abandon conversion in such a case.
6
7
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
8
Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
9
Message-id: 20230611033434.14659-1-akihiko.odaki@daynix.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
contrib/elf2dmp/main.c | 5 +++++
13
1 file changed, 5 insertions(+)
14
15
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/contrib/elf2dmp/main.c
18
+++ b/contrib/elf2dmp/main.c
19
@@ -XXX,XX +XXX,XX @@ static int fill_context(KDDEBUGGER_DATA64 *kdbg,
20
return 1;
21
}
22
23
+ if (!Prcb) {
24
+ eprintf("Context for CPU #%d is missing\n", i);
25
+ continue;
26
+ }
27
+
28
if (va_space_rw(vs, Prcb + kdbg->OffsetPrcbContext,
29
&Context, sizeof(Context), 0)) {
30
eprintf("Failed to read CPU #%d ContextFrame location\n", i);
31
--
32
2.34.1
diff view generated by jsdifflib
New patch
[PULL 3/6] target/arm: Avoid writing to constant TCGv in trans_CSEL()
1
In commit 0b188ea05acb5 we changed the implementation of
2
trans_CSEL() to use tcg_constant_i32(). However, this change
3
was incorrect, because the implementation of the function
4
sets up the TCGv_i32 rn and rm to be either zero or else
5
a TCG temp created in load_reg(), and these TCG temps are
6
then in both cases written to by the emitted TCG ops.
7
The result is that we hit a TCG assertion:
1
8
9
qemu-system-arm: ../../tcg/tcg.c:4455: tcg_reg_alloc_mov: Assertion `!temp_readonly(ots)' failed.
10
11
(or on a non-debug build, just produce a garbage result)
12
13
Adjust the code so that rn and rm are always writeable
14
temporaries whether the instruction is using the special
15
case "0" or a normal register as input.
16
17
Cc: qemu-stable@nongnu.org
18
Fixes: 0b188ea05acb5 ("target/arm: Use tcg_constant in trans_CSEL")
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20230727103906.2641264-1-peter.maydell@linaro.org
22
---
23
target/arm/tcg/translate.c | 15 ++++++++-------
24
1 file changed, 8 insertions(+), 7 deletions(-)
25
26
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/tcg/translate.c
29
+++ b/target/arm/tcg/translate.c
30
@@ -XXX,XX +XXX,XX @@ static bool trans_IT(DisasContext *s, arg_IT *a)
31
/* v8.1M CSEL/CSINC/CSNEG/CSINV */
32
static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
33
{
34
- TCGv_i32 rn, rm, zero;
35
+ TCGv_i32 rn, rm;
36
DisasCompare c;
37
38
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
39
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
40
}
41
42
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
43
- zero = tcg_constant_i32(0);
44
+ rn = tcg_temp_new_i32();
45
+ rm = tcg_temp_new_i32();
46
if (a->rn == 15) {
47
- rn = zero;
48
+ tcg_gen_movi_i32(rn, 0);
49
} else {
50
- rn = load_reg(s, a->rn);
51
+ load_reg_var(s, rn, a->rn);
52
}
53
if (a->rm == 15) {
54
- rm = zero;
55
+ tcg_gen_movi_i32(rm, 0);
56
} else {
57
- rm = load_reg(s, a->rm);
58
+ load_reg_var(s, rm, a->rm);
59
}
60
61
switch (a->op) {
62
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
63
}
64
65
arm_test_cc(&c, a->fcond);
66
- tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
67
+ tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm);
68
69
store_reg(s, a->rd, rn);
70
return true;
71
--
72
2.34.1
diff view generated by jsdifflib
[PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
[PULL 4/6] target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
Currently we list all the Arm decodetree files together and add them
2
unconditionally to arm_ss. This means we build them for both
3
qemu-system-aarch64 and qemu-system-arm. However, some of them are
4
AArch64-specific, so there is no need to build them for
5
qemu-system-arm. (Meson is smart enough to notice that the generated
6
.c.inc file is not used by any objects that go into qemu-system-arm,
7
so we only unnecessarily run decodetree, not anything more
8
heavyweight like a recompile or relink, but it's still unnecessary
9
work.)
2
10
3
Add the CRP as unimplemented thus avoiding bus errors when
11
Split gen into gen_a32 and gen_a64, and only add gen_a64 for
4
guests access these registers.
12
TARGET_AARCH64 compiles.
5
13
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
Message-id: 20230718104628.1137734-1-peter.maydell@linaro.org
11
---
17
---
12
include/hw/arm/xlnx-versal.h | 3 +++
18
target/arm/tcg/meson.build | 10 +++++++---
13
hw/arm/xlnx-versal.c | 2 ++
19
1 file changed, 7 insertions(+), 3 deletions(-)
14
2 files changed, 5 insertions(+)
15
20
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
21
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
23
--- a/target/arm/tcg/meson.build
19
+++ b/include/hw/arm/xlnx-versal.h
24
+++ b/target/arm/tcg/meson.build
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
25
@@ -XXX,XX +XXX,XX @@
21
#define MM_IOU_SCNTRS_SIZE 0x10000
26
-gen = [
22
#define MM_FPD_CRF 0xfd1a0000U
27
+gen_a64 = [
23
#define MM_FPD_CRF_SIZE 0x140000
28
+ decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']),
29
decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
30
decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
31
decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
32
+]
24
+
33
+
25
+#define MM_PMC_CRP 0xf1260000U
34
+gen_a32 = [
26
+#define MM_PMC_CRP_SIZE 0x10000
35
decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
27
#endif
36
decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
37
decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
29
index XXXXXXX..XXXXXXX 100644
38
@@ -XXX,XX +XXX,XX @@ gen = [
30
--- a/hw/arm/xlnx-versal.c
39
decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
31
+++ b/hw/arm/xlnx-versal.c
40
decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
41
decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
33
MM_CRL, MM_CRL_SIZE);
42
- decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']),
34
versal_unimp_area(s, "crf", &s->mr_ps,
43
]
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
44
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
45
-arm_ss.add(gen)
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
46
+arm_ss.add(gen_a32)
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
47
+arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
48
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
49
arm_ss.add(files(
50
'cpu32.c',
41
--
51
--
42
2.20.1
52
2.34.1
43
53
44
54
diff view generated by jsdifflib
[PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2
[PULL 5/6] kvm: Fix crash due to access uninitialized kvm_state
1
From: Marc Zyngier <maz@kernel.org>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
3
Runs into core dump on arm64 and the backtrace extracted from the
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
4
core dump is shown as below. It's caused by accessing uninitialized
5
SError interrupts.
5
@kvm_state in kvm_flush_coalesced_mmio_buffer() due to commit 176d073029
6
("hw/arm/virt: Use machine_memory_devices_init()"), where the machine's
7
memory region is added earlier than before.
6
8
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
9
main
8
bits, and ignores the current exception level. This means a hypervisor
10
qemu_init
9
trying to look at its own interrupt state actually sees the guest
11
configure_accelerators
10
state, which is unexpected and breaks KVM as of Linux 5.3.
12
qemu_opts_foreach
13
do_configure_accelerator
14
accel_init_machine
15
kvm_init
16
virt_kvm_type
17
virt_set_memmap
18
machine_memory_devices_init
19
memory_region_add_subregion
20
memory_region_add_subregion_common
21
memory_region_update_container_subregions
22
memory_region_transaction_begin
23
qemu_flush_coalesced_mmio_buffer
24
kvm_flush_coalesced_mmio_buffer
11
25
12
Instead, check for the running EL and return the physical bits
26
Fix it by bailing early in kvm_flush_coalesced_mmio_buffer() on the
13
if not running in a virtualized context.
27
uninitialized @kvm_state. With this applied, no crash is observed on
28
arm64.
14
29
15
Fixes: 636540e9c40b
30
Fixes: 176d073029 ("hw/arm/virt: Use machine_memory_devices_init()")
16
Cc: qemu-stable@nongnu.org
31
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reported-by: Quentin Perret <qperret@google.com>
32
Reviewed-by: David Hildenbrand <david@redhat.com>
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
19
Message-id: 20191122135833.28953-1-maz@kernel.org
34
Message-id: 20230731125946.2038742-1-gshan@redhat.com
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
36
---
24
target/arm/helper.c | 7 +++++--
37
accel/kvm/kvm-all.c | 2 +-
25
1 file changed, 5 insertions(+), 2 deletions(-)
38
1 file changed, 1 insertion(+), 1 deletion(-)
26
39
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
28
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
42
--- a/accel/kvm/kvm-all.c
30
+++ b/target/arm/helper.c
43
+++ b/accel/kvm/kvm-all.c
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
44
@@ -XXX,XX +XXX,XX @@ void kvm_flush_coalesced_mmio_buffer(void)
32
CPUState *cs = env_cpu(env);
45
{
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
46
KVMState *s = kvm_state;
34
uint64_t ret = 0;
47
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
48
- if (s->coalesced_flush_in_progress) {
36
+ (!arm_is_secure_below_el3(env) ||
49
+ if (!s || s->coalesced_flush_in_progress) {
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
50
return;
38
39
- if (hcr_el2 & HCR_IMO) {
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
42
ret |= CPSR_I;
43
}
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
45
}
46
}
51
}
47
52
48
- if (hcr_el2 & HCR_FMO) {
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
51
ret |= CPSR_F;
52
}
53
--
53
--
54
2.20.1
54
2.34.1
55
55
56
56
diff view generated by jsdifflib
[PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
[PULL 6/6] gdbstub: Fix client Ctrl-C handling
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
From: Nicholas Piggin <npiggin@gmail.com>
2
2
3
According to the PushStack() pseudocode in the armv7m RM,
3
The gdb remote protocol has a special interrupt character (0x03) that is
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
4
transmitted outside the regular packet processing, and represents a
5
an FPU is present. Current implementation is doing it for
5
Ctrl-C pressed in the client. Despite not being a regular packet, it
6
armv8, but not for armv7. This patch makes the existing
6
does expect a regular stop response if the stub successfully stops the
7
logic applicable to both code paths.
7
running program.
8
8
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
9
See: https://sourceware.org/gdb/onlinedocs/gdb/Interrupts.html
10
11
Inhibiting the stop reply packet can lead to gdb client hang. So permit
12
a stop response when receiving a character from gdb that stops the vm.
13
Additionally, add a warning if that was not a 0x03 character, because
14
the gdb session is likely to end up getting confused if this happens.
15
16
Cc: qemu-stable@nongnu.org
17
Fixes: 758370052fb ("gdbstub: only send stop-reply packets when allowed to")
18
Reported-by: Frederic Barrat <fbarrat@linux.ibm.com>
19
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
20
Tested-by: Joel Stanley <joel@jms.id.au>
21
Message-id: 20230711085903.304496-1-npiggin@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
24
---
13
target/arm/m_helper.c | 7 +++----
25
gdbstub/gdbstub.c | 13 +++++++++++--
14
1 file changed, 3 insertions(+), 4 deletions(-)
26
1 file changed, 11 insertions(+), 2 deletions(-)
15
27
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
28
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
17
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
30
--- a/gdbstub/gdbstub.c
19
+++ b/target/arm/m_helper.c
31
+++ b/gdbstub/gdbstub.c
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
32
@@ -XXX,XX +XXX,XX @@ void gdb_read_byte(uint8_t ch)
21
if (env->v7m.secure) {
33
return;
22
lr |= R_V7M_EXCRET_S_MASK;
23
}
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
26
- }
27
} else {
28
lr = R_V7M_EXCRET_RES1_MASK |
29
R_V7M_EXCRET_S_MASK |
30
R_V7M_EXCRET_DCRS_MASK |
31
- R_V7M_EXCRET_FTYPE_MASK |
32
R_V7M_EXCRET_ES_MASK;
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
35
}
36
}
34
}
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
35
if (runstate_is_running()) {
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
36
- /* when the CPU is running, we cannot do anything except stop
39
+ }
37
- it when receiving a char */
40
if (!arm_v7m_is_handler_mode(env)) {
38
+ /*
41
lr |= R_V7M_EXCRET_MODE_MASK;
39
+ * When the CPU is running, we cannot do anything except stop
42
}
40
+ * it when receiving a char. This is expected on a Ctrl-C in the
41
+ * gdb client. Because we are in all-stop mode, gdb sends a
42
+ * 0x03 byte which is not a usual packet, so we handle it specially
43
+ * here, but it does expect a stop reply.
44
+ */
45
+ if (ch != 0x03) {
46
+ warn_report("gdbstub: client sent packet while target running\n");
47
+ }
48
+ gdbserver_state.allow_stop_reply = true;
49
vm_stop(RUN_STATE_PAUSED);
50
} else
51
#endif
43
--
52
--
44
2.20.1
53
2.34.1
45
46
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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