1
Arm patches for rc3 : just a handful of bug fixes.
1
target-arm queue: just bugfixes, mostly mine.
2
2
3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:
6
7
7
The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
8
Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)
8
9
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725
14
13
15
for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
14
for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:
16
15
17
target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
16
tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
20
* tests/decode: Suppress "error: " string for expected-failure tests
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
21
* ui/curses: For curses display, recognize a few more control keys
23
* versal: Add the CRP as unimplemented
22
* target/arm: Special case M-profile in debug_helper.c code
24
* Fix ISR_EL1 tracking when executing at EL2
23
* scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
25
* Honor HCR_EL2.TID3 trapping requirements
24
* hw/arm/smmu: Handle big-endian hosts correctly
26
25
27
----------------------------------------------------------------
26
----------------------------------------------------------------
28
Edgar E. Iglesias (1):
27
Peter Maydell (4):
29
hw/arm: versal: Add the CRP as unimplemented
28
hw/arm/smmu: Handle big-endian hosts correctly
29
scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
30
target/arm: Special case M-profile in debug_helper.c code
31
tests/decode: Suppress "error: " string for expected-failure tests
30
32
31
Jean-Hugues Deschênes (1):
33
Sean Estabrooks (1):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
34
For curses display, recognize a few more control keys
33
35
34
Marc Zyngier (2):
36
ui/curses_keys.h | 6 ++++++
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
37
hw/arm/smmu-common.c | 3 +--
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
38
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
37
39
target/arm/debug_helper.c | 18 ++++++++++++------
38
include/hw/arm/xlnx-versal.h | 3 ++
40
scripts/decodetree.py | 6 +++++-
39
hw/arm/xlnx-versal.c | 2 ++
41
scripts/git-submodule.sh | 2 +-
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
42
6 files changed, 56 insertions(+), 18 deletions(-)
41
target/arm/m_helper.c | 7 ++--
42
4 files changed, 89 insertions(+), 6 deletions(-)
43
diff view generated by jsdifflib
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
The implementation of the SMMUv3 has multiple places where it reads a
2
data structure from the guest and directly operates on it without
3
doing a guest-to-host endianness conversion. Since all SMMU data
4
structures are little-endian, this means that the SMMU doesn't work
5
on a big-endian host. In particular, this causes the Avocado test
6
machine_aarch64_virt.py:Aarch64VirtMachine.test_alpine_virt_tcg_gic_max
7
to fail on an s390x host.
2
8
3
According to the PushStack() pseudocode in the armv7m RM,
9
Add appropriate byte-swapping on reads and writes of guest in-memory
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
10
data structures so that the device works correctly on big-endian
5
an FPU is present. Current implementation is doing it for
11
hosts.
6
armv8, but not for armv7. This patch makes the existing
7
logic applicable to both code paths.
8
12
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
13
As part of this we constrain queue_read() to operate only on Cmd
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
structs and queue_write() on Evt structs, because in practice these
15
are the only data structures the two functions are used with, and we
16
need to know what the data structure is to be able to byte-swap its
17
parts correctly.
18
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Tested-by: Thomas Huth <thuth@redhat.com>
21
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
Reviewed-by: Eric Auger <eric.auger@redhat.com>
23
Message-id: 20230717132641.764660-1-peter.maydell@linaro.org
24
Cc: qemu-stable@nongnu.org
12
---
25
---
13
target/arm/m_helper.c | 7 +++----
26
hw/arm/smmu-common.c | 3 +--
14
1 file changed, 3 insertions(+), 4 deletions(-)
27
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
28
2 files changed, 32 insertions(+), 10 deletions(-)
15
29
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
30
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
17
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
32
--- a/hw/arm/smmu-common.c
19
+++ b/target/arm/m_helper.c
33
+++ b/hw/arm/smmu-common.c
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
34
@@ -XXX,XX +XXX,XX @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
21
if (env->v7m.secure) {
35
dma_addr_t addr = baseaddr + index * sizeof(*pte);
22
lr |= R_V7M_EXCRET_S_MASK;
36
37
/* TODO: guarantee 64-bit single-copy atomicity */
38
- ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte),
39
- MEMTXATTRS_UNSPECIFIED);
40
+ ret = ldq_le_dma(&address_space_memory, addr, pte, MEMTXATTRS_UNSPECIFIED);
41
42
if (ret != MEMTX_OK) {
43
info->type = SMMU_PTW_ERR_WALK_EABT;
44
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/smmuv3.c
47
+++ b/hw/arm/smmuv3.c
48
@@ -XXX,XX +XXX,XX @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
49
trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
50
}
51
52
-static inline MemTxResult queue_read(SMMUQueue *q, void *data)
53
+static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd)
54
{
55
dma_addr_t addr = Q_CONS_ENTRY(q);
56
+ MemTxResult ret;
57
+ int i;
58
59
- return dma_memory_read(&address_space_memory, addr, data, q->entry_size,
60
- MEMTXATTRS_UNSPECIFIED);
61
+ ret = dma_memory_read(&address_space_memory, addr, cmd, sizeof(Cmd),
62
+ MEMTXATTRS_UNSPECIFIED);
63
+ if (ret != MEMTX_OK) {
64
+ return ret;
65
+ }
66
+ for (i = 0; i < ARRAY_SIZE(cmd->word); i++) {
67
+ le32_to_cpus(&cmd->word[i]);
68
+ }
69
+ return ret;
70
}
71
72
-static MemTxResult queue_write(SMMUQueue *q, void *data)
73
+static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in)
74
{
75
dma_addr_t addr = Q_PROD_ENTRY(q);
76
MemTxResult ret;
77
+ Evt evt = *evt_in;
78
+ int i;
79
80
- ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size,
81
+ for (i = 0; i < ARRAY_SIZE(evt.word); i++) {
82
+ cpu_to_le32s(&evt.word[i]);
83
+ }
84
+ ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt),
85
MEMTXATTRS_UNSPECIFIED);
86
if (ret != MEMTX_OK) {
87
return ret;
88
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
89
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
90
SMMUEventInfo *event)
91
{
92
- int ret;
93
+ int ret, i;
94
95
trace_smmuv3_get_ste(addr);
96
/* TODO: guarantee 64-bit single-copy atomicity */
97
@@ -XXX,XX +XXX,XX @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
98
event->u.f_ste_fetch.addr = addr;
99
return -EINVAL;
100
}
101
+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
102
+ le32_to_cpus(&buf->word[i]);
103
+ }
104
return 0;
105
106
}
107
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
108
CD *buf, SMMUEventInfo *event)
109
{
110
dma_addr_t addr = STE_CTXPTR(ste);
111
- int ret;
112
+ int ret, i;
113
114
trace_smmuv3_get_cd(addr);
115
/* TODO: guarantee 64-bit single-copy atomicity */
116
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
117
event->u.f_ste_fetch.addr = addr;
118
return -EINVAL;
119
}
120
+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
121
+ le32_to_cpus(&buf->word[i]);
122
+ }
123
return 0;
124
}
125
126
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
127
return -EINVAL;
128
}
129
if (s->features & SMMU_FEATURE_2LVL_STE) {
130
- int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
131
+ int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i;
132
dma_addr_t l1ptr, l2ptr;
133
STEDesc l1std;
134
135
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
136
event->u.f_ste_fetch.addr = l1ptr;
137
return -EINVAL;
23
}
138
}
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
139
+ for (i = 0; i < ARRAY_SIZE(l1std.word); i++) {
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
140
+ le32_to_cpus(&l1std.word[i]);
26
- }
141
+ }
27
} else {
142
28
lr = R_V7M_EXCRET_RES1_MASK |
143
span = L1STD_SPAN(&l1std);
29
R_V7M_EXCRET_S_MASK |
144
30
R_V7M_EXCRET_DCRS_MASK |
31
- R_V7M_EXCRET_FTYPE_MASK |
32
R_V7M_EXCRET_ES_MASK;
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
35
}
36
}
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
39
+ }
40
if (!arm_v7m_is_handler_mode(env)) {
41
lr |= R_V7M_EXCRET_MODE_MASK;
42
}
43
--
145
--
44
2.20.1
146
2.34.1
45
147
46
148
diff view generated by jsdifflib
1
From: Marc Zyngier <maz@kernel.org>
1
The POSIX definition of the 'read' utility requires that you
2
specify the variable name to set; omitting the name and
3
having it default to 'REPLY' is a bashism. If your system
4
sh is dash, then it will print an error message during build:
2
5
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
6
qemu/pc-bios/s390-ccw/../../scripts/git-submodule.sh: 106: read: arg count
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
5
SError interrupts.
6
7
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
8
Specify the variable name explicitly.
8
bits, and ignores the current exception level. This means a hypervisor
9
trying to look at its own interrupt state actually sees the guest
10
state, which is unexpected and breaks KVM as of Linux 5.3.
11
9
12
Instead, check for the running EL and return the physical bits
10
Fixes: fdb8fd8cb915647b ("git-submodule: allow partial update of .git-submodule-status")
13
if not running in a virtualized context.
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20230720153038.1587196-1-peter.maydell@linaro.org
15
---
16
scripts/git-submodule.sh | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
14
18
15
Fixes: 636540e9c40b
19
diff --git a/scripts/git-submodule.sh b/scripts/git-submodule.sh
16
Cc: qemu-stable@nongnu.org
20
index XXXXXXX..XXXXXXX 100755
17
Reported-by: Quentin Perret <qperret@google.com>
21
--- a/scripts/git-submodule.sh
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
22
+++ b/scripts/git-submodule.sh
19
Message-id: 20191122135833.28953-1-maz@kernel.org
23
@@ -XXX,XX +XXX,XX @@ update)
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
check_updated $module || echo Updated "$module"
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
25
done
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
23
---
27
- (while read -r; do
24
target/arm/helper.c | 7 +++++--
28
+ (while read -r REPLY; do
25
1 file changed, 5 insertions(+), 2 deletions(-)
29
for module in $modules; do
26
30
case $REPLY in
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
*" $module "*) continue 2 ;;
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
32
CPUState *cs = env_cpu(env);
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
34
uint64_t ret = 0;
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
36
+ (!arm_is_secure_below_el3(env) ||
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
38
39
- if (hcr_el2 & HCR_IMO) {
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
42
ret |= CPSR_I;
43
}
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
45
}
46
}
47
48
- if (hcr_el2 & HCR_FMO) {
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
51
ret |= CPSR_F;
52
}
53
--
32
--
54
2.20.1
33
2.34.1
55
34
56
35
diff view generated by jsdifflib
New patch
1
A lot of the code called from helper_exception_bkpt_insn() is written
2
assuming A-profile, but we will also call this helper on M-profile
3
CPUs when they execute a BKPT insn. This used to work by accident,
4
but recent changes mean that we will hit an assert when some of this
5
code calls down into lower level functions that end up calling
6
arm_security_space_below_el3(), arm_el_is_aa64(), and other functions
7
that now explicitly assert that the guest CPU is not M-profile.
1
8
9
Handle M-profile directly to avoid the assertions:
10
* in arm_debug_target_el(), M-profile debug exceptions always
11
go to EL1
12
* in arm_debug_exception_fsr(), M-profile always uses the short
13
format FSR (compare commit d7fe699be54b2, though in this case
14
the code in arm_v7m_cpu_do_interrupt() does not need to
15
look at the FSR value at all)
16
17
Cc: qemu-stable@nongnu.org
18
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1775
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20230721143239.1753066-1-peter.maydell@linaro.org
22
---
23
target/arm/debug_helper.c | 18 ++++++++++++------
24
1 file changed, 12 insertions(+), 6 deletions(-)
25
26
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/debug_helper.c
29
+++ b/target/arm/debug_helper.c
30
@@ -XXX,XX +XXX,XX @@ static int arm_debug_target_el(CPUARMState *env)
31
bool secure = arm_is_secure(env);
32
bool route_to_el2 = false;
33
34
+ if (arm_feature(env, ARM_FEATURE_M)) {
35
+ return 1;
36
+ }
37
+
38
if (arm_is_el2_enabled(env)) {
39
route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
40
env->cp15.mdcr_el2 & MDCR_TDE;
41
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
42
{
43
ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
44
int target_el = arm_debug_target_el(env);
45
- bool using_lpae = false;
46
+ bool using_lpae;
47
48
- if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
49
+ if (arm_feature(env, ARM_FEATURE_M)) {
50
+ using_lpae = false;
51
+ } else if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
52
using_lpae = true;
53
} else if (arm_feature(env, ARM_FEATURE_PMSA) &&
54
arm_feature(env, ARM_FEATURE_V8)) {
55
using_lpae = true;
56
+ } else if (arm_feature(env, ARM_FEATURE_LPAE) &&
57
+ (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
58
+ using_lpae = true;
59
} else {
60
- if (arm_feature(env, ARM_FEATURE_LPAE) &&
61
- (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
62
- using_lpae = true;
63
- }
64
+ using_lpae = false;
65
}
66
67
if (using_lpae) {
68
--
69
2.34.1
diff view generated by jsdifflib
1
From: Marc Zyngier <maz@kernel.org>
1
From: Sean Estabrooks <sean.estabrooks@gmail.com>
2
2
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
3
The curses display handles most control-X keys, and translates
4
registers traps to EL2, and QEMU has so far ignored this requirement.
4
them into their corresponding keycode. Here we recognize
5
a few that are missing, Ctrl-@ (null), Ctrl-\ (backslash),
6
Ctrl-] (right bracket), Ctrl-^ (caret), Ctrl-_ (underscore).
5
7
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
8
Signed-off-by: Sean Estabrooks <sean.estabrooks@gmail.com>
7
while the hypervisor doesn't want to expose the feature to its guest.
9
Message-id: CAHyVn3Bh9CRgDuOmf7G7Ngwamu8d4cVozAcB2i4ymnnggBXNmg@mail.gmail.com
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
9
case), and masks out the unsupported feature.
10
11
QEMU not honoring the trap request means that the guest observes
12
that the feature is present in the HW, starts using it, and dies
13
a horrible death when KVM injects an UNDEF, because the feature
14
*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
17
18
Note that this change does not include trapping of the MVFR
19
registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
23
Signed-off-by: Marc Zyngier <maz@kernel.org>
24
Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
26
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
12
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
13
ui/curses_keys.h | 6 ++++++
32
1 file changed, 76 insertions(+)
14
1 file changed, 6 insertions(+)
33
15
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/ui/curses_keys.h b/ui/curses_keys.h
35
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
18
--- a/ui/curses_keys.h
37
+++ b/target/arm/helper.c
19
+++ b/ui/curses_keys.h
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
20
@@ -XXX,XX +XXX,XX @@ static const int _curses2keycode[CURSES_CHARS] = {
39
REGINFO_SENTINEL
21
['N' - '@'] = 49 | CNTRL, /* Control + n */
22
/* Control + m collides with the keycode for Enter */
23
24
+ ['@' - '@'] = 3 | CNTRL, /* Control + @ */
25
+ /* Control + [ collides with the keycode for Escape */
26
+ ['\\' - '@'] = 43 | CNTRL, /* Control + Backslash */
27
+ [']' - '@'] = 27 | CNTRL, /* Control + ] */
28
+ ['^' - '@'] = 7 | CNTRL, /* Control + ^ */
29
+ ['_' - '@'] = 12 | CNTRL, /* Control + Underscore */
40
};
30
};
41
31
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
32
static const int _curseskey2keycode[CURSES_KEYS] = {
43
+ bool isread)
44
+{
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
46
+ return CP_ACCESS_TRAP_EL2;
47
+ }
48
+
49
+ return CP_ACCESS_OK;
50
+}
51
+
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ return access_aa64_tid3(env, ri, isread);
57
+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
61
+
62
void register_cp_regs_for_features(ARMCPU *cpu)
63
{
64
/* Register all the coprocessor registers based on feature bits */
65
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
68
.access = PL1_R, .type = ARM_CP_CONST,
69
+ .accessfn = access_aa32_tid3,
70
.resetvalue = cpu->id_pfr0 },
71
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
72
* the value of the GIC field until after we define these regs.
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
76
.access = PL1_R, .type = ARM_CP_NO_RAW,
77
+ .accessfn = access_aa32_tid3,
78
.readfn = id_pfr1_read,
79
.writefn = arm_cp_write_ignore },
80
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
81
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
82
.access = PL1_R, .type = ARM_CP_CONST,
83
+ .accessfn = access_aa32_tid3,
84
.resetvalue = cpu->id_dfr0 },
85
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
86
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
87
.access = PL1_R, .type = ARM_CP_CONST,
88
+ .accessfn = access_aa32_tid3,
89
.resetvalue = cpu->id_afr0 },
90
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
91
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
92
.access = PL1_R, .type = ARM_CP_CONST,
93
+ .accessfn = access_aa32_tid3,
94
.resetvalue = cpu->id_mmfr0 },
95
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
96
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
97
.access = PL1_R, .type = ARM_CP_CONST,
98
+ .accessfn = access_aa32_tid3,
99
.resetvalue = cpu->id_mmfr1 },
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
102
.access = PL1_R, .type = ARM_CP_CONST,
103
+ .accessfn = access_aa32_tid3,
104
.resetvalue = cpu->id_mmfr2 },
105
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
107
.access = PL1_R, .type = ARM_CP_CONST,
108
+ .accessfn = access_aa32_tid3,
109
.resetvalue = cpu->id_mmfr3 },
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_CONST,
113
+ .accessfn = access_aa32_tid3,
114
.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
118
+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
132
.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
134
.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
139
.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
33
--
358
2.20.1
34
2.34.1
359
360
diff view generated by jsdifflib
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From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
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The "expected failure" tests for decodetree result in the
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error messages from decodetree ending up in logs and in
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V=1 output:
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Add the CRP as unimplemented thus avoiding bus errors when
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>>> MALLOC_PERTURB_=226 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/pyvenv/bin/python3 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/scripts/decodetree.py --output-null --test-for-error /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode
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guests access these registers.
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――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― ✀ ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
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/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode:5: error: duplicate argument "a"
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―――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
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1/44 qemu:decodetree / err_argset1 OK 0.05s
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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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This then produces false positives when scanning the
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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logfiles for strings like "error: ".
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Reviewed-by: Luc Michel <luc.michel@greensocs.com>
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Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
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For the expected-failure tests, make decodetree print
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"detected:" instead of "error:".
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20230720131521.1325905-1-peter.maydell@linaro.org
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---
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---
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include/hw/arm/xlnx-versal.h | 3 +++
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scripts/decodetree.py | 6 +++++-
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hw/arm/xlnx-versal.c | 2 ++
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1 file changed, 5 insertions(+), 1 deletion(-)
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2 files changed, 5 insertions(+)
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diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
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diff --git a/scripts/decodetree.py b/scripts/decodetree.py
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/include/hw/arm/xlnx-versal.h
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--- a/scripts/decodetree.py
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+++ b/include/hw/arm/xlnx-versal.h
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+++ b/scripts/decodetree.py
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@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
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@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
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#define MM_IOU_SCNTRS_SIZE 0x10000
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global output_file
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#define MM_FPD_CRF 0xfd1a0000U
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global output_fd
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#define MM_FPD_CRF_SIZE 0x140000
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+
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+ # For the test suite expected-errors case, don't print the
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+#define MM_PMC_CRP 0xf1260000U
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+ # string "error: ", so they don't turn up as false positives
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+#define MM_PMC_CRP_SIZE 0x10000
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+ # if you grep the meson logs for strings like that.
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#endif
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+ end = 'error: ' if not testforerror else 'detected: '
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diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
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prefix = ''
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index XXXXXXX..XXXXXXX 100644
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if file:
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--- a/hw/arm/xlnx-versal.c
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prefix += f'{file}:'
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+++ b/hw/arm/xlnx-versal.c
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@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
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@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
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prefix += f'{lineno}:'
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MM_CRL, MM_CRL_SIZE);
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if prefix:
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versal_unimp_area(s, "crf", &s->mr_ps,
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prefix += ' '
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MM_FPD_CRF, MM_FPD_CRF_SIZE);
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- print(prefix, end='error: ', file=sys.stderr)
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+ versal_unimp_area(s, "crp", &s->mr_ps,
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+ print(prefix, end=end, file=sys.stderr)
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+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
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print(*args, file=sys.stderr)
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versal_unimp_area(s, "iou-scntr", &s->mr_ps,
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MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
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if output_file and output_fd:
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versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
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--
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--
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2.20.1
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2.34.1
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