[PULL 0/4] target-arm queue
[PULL 00/25] target-arm queue
1
Arm patches for rc3 : just a handful of bug fixes.
1
The following changes since commit b11728dc3ae67ddedf34b7a4f318170e7092803c:
2
2
3
thanks
3
Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging (2023-02-26 20:14:46 +0000)
4
-- PMM
5
6
7
The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
8
9
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
10
4
11
are available in the Git repository at:
5
are available in the Git repository at:
12
6
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
7
https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20230227
14
8
15
for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
9
for you to fetch changes up to e844f0c5d0bd2c4d8d3c1622eb2a88586c9c4677:
16
10
17
target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
11
hw: Replace qemu_or_irq typedef by OrIRQState (2023-02-27 13:27:05 +0000)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
15
* Various code cleanups
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
16
* More refactoring working towards allowing a build
23
* versal: Add the CRP as unimplemented
17
without CONFIG_TCG
24
* Fix ISR_EL1 tracking when executing at EL2
25
* Honor HCR_EL2.TID3 trapping requirements
26
18
27
----------------------------------------------------------------
19
----------------------------------------------------------------
28
Edgar E. Iglesias (1):
20
Claudio Fontana (2):
29
hw/arm: versal: Add the CRP as unimplemented
21
target/arm: move helpers to tcg/
22
target/arm: Move psci.c into the tcg directory
30
23
31
Jean-Hugues Deschênes (1):
24
Fabiano Rosas (9):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
25
target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
26
target/arm: Wrap TCG-only code in debug_helper.c
27
target/arm: move translate modules to tcg/
28
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
29
target/arm: Move hflags code into the tcg directory
30
target/arm: Move regime_using_lpae_format into internal.h
31
target/arm: Don't access TCG code when debugging with KVM
32
cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
33
tests/avocado: add machine:none tag to version.py
33
34
34
Marc Zyngier (2):
35
Philippe Mathieu-Daudé (13):
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
36
hw/gpio/max7310: Simplify max7310_realize()
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
37
hw/char/pl011: Un-inline pl011_create()
38
hw/char/pl011: Open-code pl011_luminary_create()
39
hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
40
hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
41
hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
42
hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
43
hw/intc/armv7m_nvic: Use QOM cast CPU() macro
44
hw/arm/musicpal: Remove unused dummy MemoryRegion
45
iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
46
hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
47
hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
48
hw: Replace qemu_or_irq typedef by OrIRQState
37
49
38
include/hw/arm/xlnx-versal.h | 3 ++
50
Thomas Huth (1):
39
hw/arm/xlnx-versal.c | 2 ++
51
include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
41
target/arm/m_helper.c | 7 ++--
42
4 files changed, 89 insertions(+), 6 deletions(-)
43
52
53
MAINTAINERS | 1 +
54
include/exec/cpu-defs.h | 6 +
55
include/hw/arm/allwinner-a10.h | 2 -
56
include/hw/arm/armsse.h | 6 +-
57
include/hw/arm/bcm2835_peripherals.h | 2 +-
58
include/hw/arm/exynos4210.h | 4 +-
59
include/hw/arm/stm32f205_soc.h | 2 +-
60
include/hw/arm/stm32f405_soc.h | 2 +-
61
include/hw/arm/xlnx-versal.h | 6 +-
62
include/hw/arm/xlnx-zynqmp.h | 2 +-
63
include/hw/char/cmsdk-apb-uart.h | 34 ---
64
include/hw/char/pl011.h | 36 +--
65
include/hw/char/xilinx_uartlite.h | 22 +-
66
include/hw/or-irq.h | 5 +-
67
include/hw/timer/cmsdk-apb-timer.h | 1 -
68
target/arm/internals.h | 23 +-
69
target/arm/{ => tcg}/translate-a64.h | 0
70
target/arm/{ => tcg}/translate.h | 0
71
target/arm/{ => tcg}/vec_internal.h | 0
72
target/arm/{ => tcg}/a32-uncond.decode | 0
73
target/arm/{ => tcg}/a32.decode | 0
74
target/arm/{ => tcg}/m-nocp.decode | 0
75
target/arm/{ => tcg}/mve.decode | 0
76
target/arm/{ => tcg}/neon-dp.decode | 0
77
target/arm/{ => tcg}/neon-ls.decode | 0
78
target/arm/{ => tcg}/neon-shared.decode | 0
79
target/arm/{ => tcg}/sme-fa64.decode | 0
80
target/arm/{ => tcg}/sme.decode | 0
81
target/arm/{ => tcg}/sve.decode | 0
82
target/arm/{ => tcg}/t16.decode | 0
83
target/arm/{ => tcg}/t32.decode | 0
84
target/arm/{ => tcg}/vfp-uncond.decode | 0
85
target/arm/{ => tcg}/vfp.decode | 0
86
hw/arm/allwinner-a10.c | 1 +
87
hw/arm/boot.c | 6 +-
88
hw/arm/exynos4210.c | 4 +-
89
hw/arm/mps2-tz.c | 2 +-
90
hw/arm/mps2.c | 41 ++-
91
hw/arm/musicpal.c | 4 -
92
hw/arm/stellaris.c | 11 +-
93
hw/char/pl011.c | 17 ++
94
hw/char/xilinx_uartlite.c | 4 +-
95
hw/core/irq.c | 9 +-
96
hw/core/or-irq.c | 18 +-
97
hw/gpio/max7310.c | 5 +-
98
hw/intc/armv7m_nvic.c | 26 +-
99
hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +-
100
hw/pci-host/raven.c | 2 +-
101
iothread.c | 4 -
102
target/arm/arm-powerctl.c | 7 +-
103
target/arm/cpu.c | 9 +-
104
target/arm/debug_helper.c | 490 ++++++++++++++++---------------
105
target/arm/helper.c | 411 +-------------------------
106
target/arm/machine.c | 12 +-
107
target/arm/ptw.c | 4 +
108
target/arm/tcg-stubs.c | 27 ++
109
target/arm/{ => tcg}/crypto_helper.c | 0
110
target/arm/{ => tcg}/helper-a64.c | 0
111
target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++
112
target/arm/{ => tcg}/iwmmxt_helper.c | 0
113
target/arm/{ => tcg}/m_helper.c | 0
114
target/arm/{ => tcg}/mte_helper.c | 0
115
target/arm/{ => tcg}/mve_helper.c | 0
116
target/arm/{ => tcg}/neon_helper.c | 0
117
target/arm/{ => tcg}/op_helper.c | 0
118
target/arm/{ => tcg}/pauth_helper.c | 0
119
target/arm/{ => tcg}/psci.c | 0
120
target/arm/{ => tcg}/sme_helper.c | 0
121
target/arm/{ => tcg}/sve_helper.c | 0
122
target/arm/{ => tcg}/tlb_helper.c | 18 --
123
target/arm/{ => tcg}/translate-a64.c | 0
124
target/arm/{ => tcg}/translate-m-nocp.c | 0
125
target/arm/{ => tcg}/translate-mve.c | 0
126
target/arm/{ => tcg}/translate-neon.c | 0
127
target/arm/{ => tcg}/translate-sme.c | 0
128
target/arm/{ => tcg}/translate-sve.c | 0
129
target/arm/{ => tcg}/translate-vfp.c | 0
130
target/arm/{ => tcg}/translate.c | 0
131
target/arm/{ => tcg}/vec_helper.c | 0
132
target/arm/meson.build | 46 +--
133
target/arm/tcg/meson.build | 50 ++++
134
tests/avocado/version.py | 1 +
135
82 files changed, 918 insertions(+), 875 deletions(-)
136
rename target/arm/{ => tcg}/translate-a64.h (100%)
137
rename target/arm/{ => tcg}/translate.h (100%)
138
rename target/arm/{ => tcg}/vec_internal.h (100%)
139
rename target/arm/{ => tcg}/a32-uncond.decode (100%)
140
rename target/arm/{ => tcg}/a32.decode (100%)
141
rename target/arm/{ => tcg}/m-nocp.decode (100%)
142
rename target/arm/{ => tcg}/mve.decode (100%)
143
rename target/arm/{ => tcg}/neon-dp.decode (100%)
144
rename target/arm/{ => tcg}/neon-ls.decode (100%)
145
rename target/arm/{ => tcg}/neon-shared.decode (100%)
146
rename target/arm/{ => tcg}/sme-fa64.decode (100%)
147
rename target/arm/{ => tcg}/sme.decode (100%)
148
rename target/arm/{ => tcg}/sve.decode (100%)
149
rename target/arm/{ => tcg}/t16.decode (100%)
150
rename target/arm/{ => tcg}/t32.decode (100%)
151
rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
152
rename target/arm/{ => tcg}/vfp.decode (100%)
153
create mode 100644 target/arm/tcg-stubs.c
154
rename target/arm/{ => tcg}/crypto_helper.c (100%)
155
rename target/arm/{ => tcg}/helper-a64.c (100%)
156
create mode 100644 target/arm/tcg/hflags.c
157
rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
158
rename target/arm/{ => tcg}/m_helper.c (100%)
159
rename target/arm/{ => tcg}/mte_helper.c (100%)
160
rename target/arm/{ => tcg}/mve_helper.c (100%)
161
rename target/arm/{ => tcg}/neon_helper.c (100%)
162
rename target/arm/{ => tcg}/op_helper.c (100%)
163
rename target/arm/{ => tcg}/pauth_helper.c (100%)
164
rename target/arm/{ => tcg}/psci.c (100%)
165
rename target/arm/{ => tcg}/sme_helper.c (100%)
166
rename target/arm/{ => tcg}/sve_helper.c (100%)
167
rename target/arm/{ => tcg}/tlb_helper.c (94%)
168
rename target/arm/{ => tcg}/translate-a64.c (100%)
169
rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
170
rename target/arm/{ => tcg}/translate-mve.c (100%)
171
rename target/arm/{ => tcg}/translate-neon.c (100%)
172
rename target/arm/{ => tcg}/translate-sme.c (100%)
173
rename target/arm/{ => tcg}/translate-sve.c (100%)
174
rename target/arm/{ => tcg}/translate-vfp.c (100%)
175
rename target/arm/{ => tcg}/translate.c (100%)
176
rename target/arm/{ => tcg}/vec_helper.c (100%)
177
create mode 100644 target/arm/tcg/meson.build
178
diff view generated by jsdifflib
New patch
[PULL 01/25] include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header
1
From: Thomas Huth <thuth@redhat.com>
1
2
3
pci_device.h is not needed at all in allwinner-a10.h, and serial.h
4
is only needed by the corresponding .c file.
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230215152233.210024-1-thuth@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-a10.h | 2 --
12
hw/arm/allwinner-a10.c | 1 +
13
2 files changed, 1 insertion(+), 2 deletions(-)
14
15
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-a10.h
18
+++ b/include/hw/arm/allwinner-a10.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef HW_ARM_ALLWINNER_A10_H
21
#define HW_ARM_ALLWINNER_A10_H
22
23
-#include "hw/char/serial.h"
24
#include "hw/arm/boot.h"
25
-#include "hw/pci/pci_device.h"
26
#include "hw/timer/allwinner-a10-pit.h"
27
#include "hw/intc/allwinner-a10-pic.h"
28
#include "hw/net/allwinner_emac.h"
29
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/allwinner-a10.c
32
+++ b/hw/arm/allwinner-a10.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qemu/osdep.h"
35
#include "qapi/error.h"
36
#include "qemu/module.h"
37
+#include "hw/char/serial.h"
38
#include "hw/sysbus.h"
39
#include "hw/arm/allwinner-a10.h"
40
#include "hw/misc/unimp.h"
41
--
42
2.34.1
43
44
diff view generated by jsdifflib
New patch
[PULL 02/25] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
This is in preparation for restricting compilation of some parts of
4
debug_helper.c to TCG only.
5
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.c | 6 ++++--
11
target/arm/debug_helper.c | 16 ++++++++++++----
12
target/arm/machine.c | 7 +++++--
13
3 files changed, 21 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.c
18
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
20
}
21
#endif
22
23
- hw_breakpoint_update_all(cpu);
24
- hw_watchpoint_update_all(cpu);
25
+ if (tcg_enabled()) {
26
+ hw_breakpoint_update_all(cpu);
27
+ hw_watchpoint_update_all(cpu);
28
+ }
29
arm_rebuild_hflags(env);
30
}
31
32
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/debug_helper.c
35
+++ b/target/arm/debug_helper.c
36
@@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
value &= ~3ULL;
38
39
raw_write(env, ri, value);
40
- hw_watchpoint_update(cpu, i);
41
+ if (tcg_enabled()) {
42
+ hw_watchpoint_update(cpu, i);
43
+ }
44
}
45
46
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
@@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
48
int i = ri->crm;
49
50
raw_write(env, ri, value);
51
- hw_watchpoint_update(cpu, i);
52
+ if (tcg_enabled()) {
53
+ hw_watchpoint_update(cpu, i);
54
+ }
55
}
56
57
void hw_breakpoint_update(ARMCPU *cpu, int n)
58
@@ -XXX,XX +XXX,XX @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
59
int i = ri->crm;
60
61
raw_write(env, ri, value);
62
- hw_breakpoint_update(cpu, i);
63
+ if (tcg_enabled()) {
64
+ hw_breakpoint_update(cpu, i);
65
+ }
66
}
67
68
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
69
@@ -XXX,XX +XXX,XX @@ static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
70
value = deposit64(value, 8, 1, extract64(value, 7, 1));
71
72
raw_write(env, ri, value);
73
- hw_breakpoint_update(cpu, i);
74
+ if (tcg_enabled()) {
75
+ hw_breakpoint_update(cpu, i);
76
+ }
77
}
78
79
void define_debug_regs(ARMCPU *cpu)
80
diff --git a/target/arm/machine.c b/target/arm/machine.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/machine.c
83
+++ b/target/arm/machine.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "cpu.h"
86
#include "qemu/error-report.h"
87
#include "sysemu/kvm.h"
88
+#include "sysemu/tcg.h"
89
#include "kvm_arm.h"
90
#include "internals.h"
91
#include "migration/cpu.h"
92
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
93
return -1;
94
}
95
96
- hw_breakpoint_update_all(cpu);
97
- hw_watchpoint_update_all(cpu);
98
+ if (tcg_enabled()) {
99
+ hw_breakpoint_update_all(cpu);
100
+ hw_watchpoint_update_all(cpu);
101
+ }
102
103
/*
104
* TCG gen_update_fp_context() relies on the invariant that
105
--
106
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/25] target/arm: Wrap TCG-only code in debug_helper.c
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
The next few patches will move helpers under CONFIG_TCG. We'd prefer
4
to keep the debug helpers and debug registers close together, so
5
rearrange the file a bit to be able to wrap the helpers with a TCG
6
ifdef.
7
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/debug_helper.c | 476 +++++++++++++++++++-------------------
13
1 file changed, 239 insertions(+), 237 deletions(-)
14
15
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/debug_helper.c
18
+++ b/target/arm/debug_helper.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "cpregs.h"
21
#include "exec/exec-all.h"
22
#include "exec/helper-proto.h"
23
+#include "sysemu/tcg.h"
24
25
-
26
+#ifdef CONFIG_TCG
27
/* Return the Exception Level targeted by debug exceptions. */
28
static int arm_debug_target_el(CPUARMState *env)
29
{
30
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
31
raise_exception_debug(env, EXCP_UDEF, syndrome);
32
}
33
34
+void hw_watchpoint_update(ARMCPU *cpu, int n)
35
+{
36
+ CPUARMState *env = &cpu->env;
37
+ vaddr len = 0;
38
+ vaddr wvr = env->cp15.dbgwvr[n];
39
+ uint64_t wcr = env->cp15.dbgwcr[n];
40
+ int mask;
41
+ int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
42
+
43
+ if (env->cpu_watchpoint[n]) {
44
+ cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
45
+ env->cpu_watchpoint[n] = NULL;
46
+ }
47
+
48
+ if (!FIELD_EX64(wcr, DBGWCR, E)) {
49
+ /* E bit clear : watchpoint disabled */
50
+ return;
51
+ }
52
+
53
+ switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
54
+ case 0:
55
+ /* LSC 00 is reserved and must behave as if the wp is disabled */
56
+ return;
57
+ case 1:
58
+ flags |= BP_MEM_READ;
59
+ break;
60
+ case 2:
61
+ flags |= BP_MEM_WRITE;
62
+ break;
63
+ case 3:
64
+ flags |= BP_MEM_ACCESS;
65
+ break;
66
+ }
67
+
68
+ /*
69
+ * Attempts to use both MASK and BAS fields simultaneously are
70
+ * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
71
+ * thus generating a watchpoint for every byte in the masked region.
72
+ */
73
+ mask = FIELD_EX64(wcr, DBGWCR, MASK);
74
+ if (mask == 1 || mask == 2) {
75
+ /*
76
+ * Reserved values of MASK; we must act as if the mask value was
77
+ * some non-reserved value, or as if the watchpoint were disabled.
78
+ * We choose the latter.
79
+ */
80
+ return;
81
+ } else if (mask) {
82
+ /* Watchpoint covers an aligned area up to 2GB in size */
83
+ len = 1ULL << mask;
84
+ /*
85
+ * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
86
+ * whether the watchpoint fires when the unmasked bits match; we opt
87
+ * to generate the exceptions.
88
+ */
89
+ wvr &= ~(len - 1);
90
+ } else {
91
+ /* Watchpoint covers bytes defined by the byte address select bits */
92
+ int bas = FIELD_EX64(wcr, DBGWCR, BAS);
93
+ int basstart;
94
+
95
+ if (extract64(wvr, 2, 1)) {
96
+ /*
97
+ * Deprecated case of an only 4-aligned address. BAS[7:4] are
98
+ * ignored, and BAS[3:0] define which bytes to watch.
99
+ */
100
+ bas &= 0xf;
101
+ }
102
+
103
+ if (bas == 0) {
104
+ /* This must act as if the watchpoint is disabled */
105
+ return;
106
+ }
107
+
108
+ /*
109
+ * The BAS bits are supposed to be programmed to indicate a contiguous
110
+ * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
111
+ * we fire for each byte in the word/doubleword addressed by the WVR.
112
+ * We choose to ignore any non-zero bits after the first range of 1s.
113
+ */
114
+ basstart = ctz32(bas);
115
+ len = cto32(bas >> basstart);
116
+ wvr += basstart;
117
+ }
118
+
119
+ cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
120
+ &env->cpu_watchpoint[n]);
121
+}
122
+
123
+void hw_watchpoint_update_all(ARMCPU *cpu)
124
+{
125
+ int i;
126
+ CPUARMState *env = &cpu->env;
127
+
128
+ /*
129
+ * Completely clear out existing QEMU watchpoints and our array, to
130
+ * avoid possible stale entries following migration load.
131
+ */
132
+ cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
133
+ memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
134
+
135
+ for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
136
+ hw_watchpoint_update(cpu, i);
137
+ }
138
+}
139
+
140
+void hw_breakpoint_update(ARMCPU *cpu, int n)
141
+{
142
+ CPUARMState *env = &cpu->env;
143
+ uint64_t bvr = env->cp15.dbgbvr[n];
144
+ uint64_t bcr = env->cp15.dbgbcr[n];
145
+ vaddr addr;
146
+ int bt;
147
+ int flags = BP_CPU;
148
+
149
+ if (env->cpu_breakpoint[n]) {
150
+ cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
151
+ env->cpu_breakpoint[n] = NULL;
152
+ }
153
+
154
+ if (!extract64(bcr, 0, 1)) {
155
+ /* E bit clear : watchpoint disabled */
156
+ return;
157
+ }
158
+
159
+ bt = extract64(bcr, 20, 4);
160
+
161
+ switch (bt) {
162
+ case 4: /* unlinked address mismatch (reserved if AArch64) */
163
+ case 5: /* linked address mismatch (reserved if AArch64) */
164
+ qemu_log_mask(LOG_UNIMP,
165
+ "arm: address mismatch breakpoint types not implemented\n");
166
+ return;
167
+ case 0: /* unlinked address match */
168
+ case 1: /* linked address match */
169
+ {
170
+ /*
171
+ * Bits [1:0] are RES0.
172
+ *
173
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
174
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
175
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
176
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
177
+ * whether the RESS bits are ignored when comparing an address.
178
+ * Therefore we are allowed to compare the entire register, which
179
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
180
+ *
181
+ * The BAS field is used to allow setting breakpoints on 16-bit
182
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
183
+ * a bp will fire if the addresses covered by the bp and the addresses
184
+ * covered by the insn overlap but the insn doesn't start at the
185
+ * start of the bp address range. We choose to require the insn and
186
+ * the bp to have the same address. The constraints on writing to
187
+ * BAS enforced in dbgbcr_write mean we have only four cases:
188
+ * 0b0000 => no breakpoint
189
+ * 0b0011 => breakpoint on addr
190
+ * 0b1100 => breakpoint on addr + 2
191
+ * 0b1111 => breakpoint on addr
192
+ * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
193
+ */
194
+ int bas = extract64(bcr, 5, 4);
195
+ addr = bvr & ~3ULL;
196
+ if (bas == 0) {
197
+ return;
198
+ }
199
+ if (bas == 0xc) {
200
+ addr += 2;
201
+ }
202
+ break;
203
+ }
204
+ case 2: /* unlinked context ID match */
205
+ case 8: /* unlinked VMID match (reserved if no EL2) */
206
+ case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
207
+ qemu_log_mask(LOG_UNIMP,
208
+ "arm: unlinked context breakpoint types not implemented\n");
209
+ return;
210
+ case 9: /* linked VMID match (reserved if no EL2) */
211
+ case 11: /* linked context ID and VMID match (reserved if no EL2) */
212
+ case 3: /* linked context ID match */
213
+ default:
214
+ /*
215
+ * We must generate no events for Linked context matches (unless
216
+ * they are linked to by some other bp/wp, which is handled in
217
+ * updates for the linking bp/wp). We choose to also generate no events
218
+ * for reserved values.
219
+ */
220
+ return;
221
+ }
222
+
223
+ cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
224
+}
225
+
226
+void hw_breakpoint_update_all(ARMCPU *cpu)
227
+{
228
+ int i;
229
+ CPUARMState *env = &cpu->env;
230
+
231
+ /*
232
+ * Completely clear out existing QEMU breakpoints and our array, to
233
+ * avoid possible stale entries following migration load.
234
+ */
235
+ cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
236
+ memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
237
+
238
+ for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
239
+ hw_breakpoint_update(cpu, i);
240
+ }
241
+}
242
+
243
+#if !defined(CONFIG_USER_ONLY)
244
+
245
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
246
+{
247
+ ARMCPU *cpu = ARM_CPU(cs);
248
+ CPUARMState *env = &cpu->env;
249
+
250
+ /*
251
+ * In BE32 system mode, target memory is stored byteswapped (on a
252
+ * little-endian host system), and by the time we reach here (via an
253
+ * opcode helper) the addresses of subword accesses have been adjusted
254
+ * to account for that, which means that watchpoints will not match.
255
+ * Undo the adjustment here.
256
+ */
257
+ if (arm_sctlr_b(env)) {
258
+ if (len == 1) {
259
+ addr ^= 3;
260
+ } else if (len == 2) {
261
+ addr ^= 2;
262
+ }
263
+ }
264
+
265
+ return addr;
266
+}
267
+
268
+#endif /* !CONFIG_USER_ONLY */
269
+#endif /* CONFIG_TCG */
270
+
271
/*
272
* Check for traps to "powerdown debug" registers, which are controlled
273
* by MDCR.TDOSA
274
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
275
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
276
};
277
278
-void hw_watchpoint_update(ARMCPU *cpu, int n)
279
-{
280
- CPUARMState *env = &cpu->env;
281
- vaddr len = 0;
282
- vaddr wvr = env->cp15.dbgwvr[n];
283
- uint64_t wcr = env->cp15.dbgwcr[n];
284
- int mask;
285
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
286
-
287
- if (env->cpu_watchpoint[n]) {
288
- cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
289
- env->cpu_watchpoint[n] = NULL;
290
- }
291
-
292
- if (!FIELD_EX64(wcr, DBGWCR, E)) {
293
- /* E bit clear : watchpoint disabled */
294
- return;
295
- }
296
-
297
- switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
298
- case 0:
299
- /* LSC 00 is reserved and must behave as if the wp is disabled */
300
- return;
301
- case 1:
302
- flags |= BP_MEM_READ;
303
- break;
304
- case 2:
305
- flags |= BP_MEM_WRITE;
306
- break;
307
- case 3:
308
- flags |= BP_MEM_ACCESS;
309
- break;
310
- }
311
-
312
- /*
313
- * Attempts to use both MASK and BAS fields simultaneously are
314
- * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
315
- * thus generating a watchpoint for every byte in the masked region.
316
- */
317
- mask = FIELD_EX64(wcr, DBGWCR, MASK);
318
- if (mask == 1 || mask == 2) {
319
- /*
320
- * Reserved values of MASK; we must act as if the mask value was
321
- * some non-reserved value, or as if the watchpoint were disabled.
322
- * We choose the latter.
323
- */
324
- return;
325
- } else if (mask) {
326
- /* Watchpoint covers an aligned area up to 2GB in size */
327
- len = 1ULL << mask;
328
- /*
329
- * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
330
- * whether the watchpoint fires when the unmasked bits match; we opt
331
- * to generate the exceptions.
332
- */
333
- wvr &= ~(len - 1);
334
- } else {
335
- /* Watchpoint covers bytes defined by the byte address select bits */
336
- int bas = FIELD_EX64(wcr, DBGWCR, BAS);
337
- int basstart;
338
-
339
- if (extract64(wvr, 2, 1)) {
340
- /*
341
- * Deprecated case of an only 4-aligned address. BAS[7:4] are
342
- * ignored, and BAS[3:0] define which bytes to watch.
343
- */
344
- bas &= 0xf;
345
- }
346
-
347
- if (bas == 0) {
348
- /* This must act as if the watchpoint is disabled */
349
- return;
350
- }
351
-
352
- /*
353
- * The BAS bits are supposed to be programmed to indicate a contiguous
354
- * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
355
- * we fire for each byte in the word/doubleword addressed by the WVR.
356
- * We choose to ignore any non-zero bits after the first range of 1s.
357
- */
358
- basstart = ctz32(bas);
359
- len = cto32(bas >> basstart);
360
- wvr += basstart;
361
- }
362
-
363
- cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
364
- &env->cpu_watchpoint[n]);
365
-}
366
-
367
-void hw_watchpoint_update_all(ARMCPU *cpu)
368
-{
369
- int i;
370
- CPUARMState *env = &cpu->env;
371
-
372
- /*
373
- * Completely clear out existing QEMU watchpoints and our array, to
374
- * avoid possible stale entries following migration load.
375
- */
376
- cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
377
- memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
378
-
379
- for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
380
- hw_watchpoint_update(cpu, i);
381
- }
382
-}
383
-
384
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
385
uint64_t value)
386
{
387
@@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
388
}
389
}
390
391
-void hw_breakpoint_update(ARMCPU *cpu, int n)
392
-{
393
- CPUARMState *env = &cpu->env;
394
- uint64_t bvr = env->cp15.dbgbvr[n];
395
- uint64_t bcr = env->cp15.dbgbcr[n];
396
- vaddr addr;
397
- int bt;
398
- int flags = BP_CPU;
399
-
400
- if (env->cpu_breakpoint[n]) {
401
- cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
402
- env->cpu_breakpoint[n] = NULL;
403
- }
404
-
405
- if (!extract64(bcr, 0, 1)) {
406
- /* E bit clear : watchpoint disabled */
407
- return;
408
- }
409
-
410
- bt = extract64(bcr, 20, 4);
411
-
412
- switch (bt) {
413
- case 4: /* unlinked address mismatch (reserved if AArch64) */
414
- case 5: /* linked address mismatch (reserved if AArch64) */
415
- qemu_log_mask(LOG_UNIMP,
416
- "arm: address mismatch breakpoint types not implemented\n");
417
- return;
418
- case 0: /* unlinked address match */
419
- case 1: /* linked address match */
420
- {
421
- /*
422
- * Bits [1:0] are RES0.
423
- *
424
- * It is IMPLEMENTATION DEFINED whether bits [63:49]
425
- * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
426
- * of the VA field ([48] or [52] for FEAT_LVA), or whether the
427
- * value is read as written. It is CONSTRAINED UNPREDICTABLE
428
- * whether the RESS bits are ignored when comparing an address.
429
- * Therefore we are allowed to compare the entire register, which
430
- * lets us avoid considering whether FEAT_LVA is actually enabled.
431
- *
432
- * The BAS field is used to allow setting breakpoints on 16-bit
433
- * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
434
- * a bp will fire if the addresses covered by the bp and the addresses
435
- * covered by the insn overlap but the insn doesn't start at the
436
- * start of the bp address range. We choose to require the insn and
437
- * the bp to have the same address. The constraints on writing to
438
- * BAS enforced in dbgbcr_write mean we have only four cases:
439
- * 0b0000 => no breakpoint
440
- * 0b0011 => breakpoint on addr
441
- * 0b1100 => breakpoint on addr + 2
442
- * 0b1111 => breakpoint on addr
443
- * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
444
- */
445
- int bas = extract64(bcr, 5, 4);
446
- addr = bvr & ~3ULL;
447
- if (bas == 0) {
448
- return;
449
- }
450
- if (bas == 0xc) {
451
- addr += 2;
452
- }
453
- break;
454
- }
455
- case 2: /* unlinked context ID match */
456
- case 8: /* unlinked VMID match (reserved if no EL2) */
457
- case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
458
- qemu_log_mask(LOG_UNIMP,
459
- "arm: unlinked context breakpoint types not implemented\n");
460
- return;
461
- case 9: /* linked VMID match (reserved if no EL2) */
462
- case 11: /* linked context ID and VMID match (reserved if no EL2) */
463
- case 3: /* linked context ID match */
464
- default:
465
- /*
466
- * We must generate no events for Linked context matches (unless
467
- * they are linked to by some other bp/wp, which is handled in
468
- * updates for the linking bp/wp). We choose to also generate no events
469
- * for reserved values.
470
- */
471
- return;
472
- }
473
-
474
- cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
475
-}
476
-
477
-void hw_breakpoint_update_all(ARMCPU *cpu)
478
-{
479
- int i;
480
- CPUARMState *env = &cpu->env;
481
-
482
- /*
483
- * Completely clear out existing QEMU breakpoints and our array, to
484
- * avoid possible stale entries following migration load.
485
- */
486
- cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
487
- memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
488
-
489
- for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
490
- hw_breakpoint_update(cpu, i);
491
- }
492
-}
493
-
494
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
495
uint64_t value)
496
{
497
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
498
g_free(dbgwcr_el1_name);
499
}
500
}
501
-
502
-#if !defined(CONFIG_USER_ONLY)
503
-
504
-vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
505
-{
506
- ARMCPU *cpu = ARM_CPU(cs);
507
- CPUARMState *env = &cpu->env;
508
-
509
- /*
510
- * In BE32 system mode, target memory is stored byteswapped (on a
511
- * little-endian host system), and by the time we reach here (via an
512
- * opcode helper) the addresses of subword accesses have been adjusted
513
- * to account for that, which means that watchpoints will not match.
514
- * Undo the adjustment here.
515
- */
516
- if (arm_sctlr_b(env)) {
517
- if (len == 1) {
518
- addr ^= 3;
519
- } else if (len == 2) {
520
- addr ^= 2;
521
- }
522
- }
523
-
524
- return addr;
525
-}
526
-
527
-#endif
528
--
529
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/25] target/arm: move translate modules to tcg/
1
1
From: Fabiano Rosas <farosas@suse.de>
2
3
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
4
code that is selected by CONFIG_TCG.
5
6
Signed-off-by: Claudio Fontana <cfontana@suse.de>
7
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
MAINTAINERS | 1 +
15
target/arm/{ => tcg}/translate-a64.h | 0
16
target/arm/{ => tcg}/translate.h | 0
17
target/arm/{ => tcg}/a32-uncond.decode | 0
18
target/arm/{ => tcg}/a32.decode | 0
19
target/arm/{ => tcg}/m-nocp.decode | 0
20
target/arm/{ => tcg}/mve.decode | 0
21
target/arm/{ => tcg}/neon-dp.decode | 0
22
target/arm/{ => tcg}/neon-ls.decode | 0
23
target/arm/{ => tcg}/neon-shared.decode | 0
24
target/arm/{ => tcg}/sme-fa64.decode | 0
25
target/arm/{ => tcg}/sme.decode | 0
26
target/arm/{ => tcg}/sve.decode | 0
27
target/arm/{ => tcg}/t16.decode | 0
28
target/arm/{ => tcg}/t32.decode | 0
29
target/arm/{ => tcg}/vfp-uncond.decode | 0
30
target/arm/{ => tcg}/vfp.decode | 0
31
target/arm/{ => tcg}/translate-a64.c | 0
32
target/arm/{ => tcg}/translate-m-nocp.c | 0
33
target/arm/{ => tcg}/translate-mve.c | 0
34
target/arm/{ => tcg}/translate-neon.c | 0
35
target/arm/{ => tcg}/translate-sme.c | 0
36
target/arm/{ => tcg}/translate-sve.c | 0
37
target/arm/{ => tcg}/translate-vfp.c | 0
38
target/arm/{ => tcg}/translate.c | 0
39
target/arm/meson.build | 30 +++---------------
40
target/arm/{ => tcg}/meson.build | 41 +------------------------
41
27 files changed, 6 insertions(+), 66 deletions(-)
42
rename target/arm/{ => tcg}/translate-a64.h (100%)
43
rename target/arm/{ => tcg}/translate.h (100%)
44
rename target/arm/{ => tcg}/a32-uncond.decode (100%)
45
rename target/arm/{ => tcg}/a32.decode (100%)
46
rename target/arm/{ => tcg}/m-nocp.decode (100%)
47
rename target/arm/{ => tcg}/mve.decode (100%)
48
rename target/arm/{ => tcg}/neon-dp.decode (100%)
49
rename target/arm/{ => tcg}/neon-ls.decode (100%)
50
rename target/arm/{ => tcg}/neon-shared.decode (100%)
51
rename target/arm/{ => tcg}/sme-fa64.decode (100%)
52
rename target/arm/{ => tcg}/sme.decode (100%)
53
rename target/arm/{ => tcg}/sve.decode (100%)
54
rename target/arm/{ => tcg}/t16.decode (100%)
55
rename target/arm/{ => tcg}/t32.decode (100%)
56
rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
57
rename target/arm/{ => tcg}/vfp.decode (100%)
58
rename target/arm/{ => tcg}/translate-a64.c (100%)
59
rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
60
rename target/arm/{ => tcg}/translate-mve.c (100%)
61
rename target/arm/{ => tcg}/translate-neon.c (100%)
62
rename target/arm/{ => tcg}/translate-sme.c (100%)
63
rename target/arm/{ => tcg}/translate-sve.c (100%)
64
rename target/arm/{ => tcg}/translate-vfp.c (100%)
65
rename target/arm/{ => tcg}/translate.c (100%)
66
copy target/arm/{ => tcg}/meson.build (64%)
67
68
diff --git a/MAINTAINERS b/MAINTAINERS
69
index XXXXXXX..XXXXXXX 100644
70
--- a/MAINTAINERS
71
+++ b/MAINTAINERS
72
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
73
L: qemu-arm@nongnu.org
74
S: Maintained
75
F: target/arm/
76
+F: target/arm/tcg/
77
F: tests/tcg/arm/
78
F: tests/tcg/aarch64/
79
F: tests/qtest/arm-cpu-features.c
80
diff --git a/target/arm/translate-a64.h b/target/arm/tcg/translate-a64.h
81
similarity index 100%
82
rename from target/arm/translate-a64.h
83
rename to target/arm/tcg/translate-a64.h
84
diff --git a/target/arm/translate.h b/target/arm/tcg/translate.h
85
similarity index 100%
86
rename from target/arm/translate.h
87
rename to target/arm/tcg/translate.h
88
diff --git a/target/arm/a32-uncond.decode b/target/arm/tcg/a32-uncond.decode
89
similarity index 100%
90
rename from target/arm/a32-uncond.decode
91
rename to target/arm/tcg/a32-uncond.decode
92
diff --git a/target/arm/a32.decode b/target/arm/tcg/a32.decode
93
similarity index 100%
94
rename from target/arm/a32.decode
95
rename to target/arm/tcg/a32.decode
96
diff --git a/target/arm/m-nocp.decode b/target/arm/tcg/m-nocp.decode
97
similarity index 100%
98
rename from target/arm/m-nocp.decode
99
rename to target/arm/tcg/m-nocp.decode
100
diff --git a/target/arm/mve.decode b/target/arm/tcg/mve.decode
101
similarity index 100%
102
rename from target/arm/mve.decode
103
rename to target/arm/tcg/mve.decode
104
diff --git a/target/arm/neon-dp.decode b/target/arm/tcg/neon-dp.decode
105
similarity index 100%
106
rename from target/arm/neon-dp.decode
107
rename to target/arm/tcg/neon-dp.decode
108
diff --git a/target/arm/neon-ls.decode b/target/arm/tcg/neon-ls.decode
109
similarity index 100%
110
rename from target/arm/neon-ls.decode
111
rename to target/arm/tcg/neon-ls.decode
112
diff --git a/target/arm/neon-shared.decode b/target/arm/tcg/neon-shared.decode
113
similarity index 100%
114
rename from target/arm/neon-shared.decode
115
rename to target/arm/tcg/neon-shared.decode
116
diff --git a/target/arm/sme-fa64.decode b/target/arm/tcg/sme-fa64.decode
117
similarity index 100%
118
rename from target/arm/sme-fa64.decode
119
rename to target/arm/tcg/sme-fa64.decode
120
diff --git a/target/arm/sme.decode b/target/arm/tcg/sme.decode
121
similarity index 100%
122
rename from target/arm/sme.decode
123
rename to target/arm/tcg/sme.decode
124
diff --git a/target/arm/sve.decode b/target/arm/tcg/sve.decode
125
similarity index 100%
126
rename from target/arm/sve.decode
127
rename to target/arm/tcg/sve.decode
128
diff --git a/target/arm/t16.decode b/target/arm/tcg/t16.decode
129
similarity index 100%
130
rename from target/arm/t16.decode
131
rename to target/arm/tcg/t16.decode
132
diff --git a/target/arm/t32.decode b/target/arm/tcg/t32.decode
133
similarity index 100%
134
rename from target/arm/t32.decode
135
rename to target/arm/tcg/t32.decode
136
diff --git a/target/arm/vfp-uncond.decode b/target/arm/tcg/vfp-uncond.decode
137
similarity index 100%
138
rename from target/arm/vfp-uncond.decode
139
rename to target/arm/tcg/vfp-uncond.decode
140
diff --git a/target/arm/vfp.decode b/target/arm/tcg/vfp.decode
141
similarity index 100%
142
rename from target/arm/vfp.decode
143
rename to target/arm/tcg/vfp.decode
144
diff --git a/target/arm/translate-a64.c b/target/arm/tcg/translate-a64.c
145
similarity index 100%
146
rename from target/arm/translate-a64.c
147
rename to target/arm/tcg/translate-a64.c
148
diff --git a/target/arm/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c
149
similarity index 100%
150
rename from target/arm/translate-m-nocp.c
151
rename to target/arm/tcg/translate-m-nocp.c
152
diff --git a/target/arm/translate-mve.c b/target/arm/tcg/translate-mve.c
153
similarity index 100%
154
rename from target/arm/translate-mve.c
155
rename to target/arm/tcg/translate-mve.c
156
diff --git a/target/arm/translate-neon.c b/target/arm/tcg/translate-neon.c
157
similarity index 100%
158
rename from target/arm/translate-neon.c
159
rename to target/arm/tcg/translate-neon.c
160
diff --git a/target/arm/translate-sme.c b/target/arm/tcg/translate-sme.c
161
similarity index 100%
162
rename from target/arm/translate-sme.c
163
rename to target/arm/tcg/translate-sme.c
164
diff --git a/target/arm/translate-sve.c b/target/arm/tcg/translate-sve.c
165
similarity index 100%
166
rename from target/arm/translate-sve.c
167
rename to target/arm/tcg/translate-sve.c
168
diff --git a/target/arm/translate-vfp.c b/target/arm/tcg/translate-vfp.c
169
similarity index 100%
170
rename from target/arm/translate-vfp.c
171
rename to target/arm/tcg/translate-vfp.c
172
diff --git a/target/arm/translate.c b/target/arm/tcg/translate.c
173
similarity index 100%
174
rename from target/arm/translate.c
175
rename to target/arm/tcg/translate.c
176
diff --git a/target/arm/meson.build b/target/arm/meson.build
177
index XXXXXXX..XXXXXXX 100644
178
--- a/target/arm/meson.build
179
+++ b/target/arm/meson.build
180
@@ -XXX,XX +XXX,XX @@
181
-gen = [
182
- decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
183
- decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
184
- decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
185
- decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
186
- decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
187
- decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
188
- decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
189
- decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'),
190
- decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
191
- decodetree.process('mve.decode', extra_args: '--decode=disas_mve'),
192
- decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
193
- decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
194
- decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
195
- decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
196
-]
197
-
198
arm_ss = ss.source_set()
199
-arm_ss.add(gen)
200
arm_ss.add(files(
201
'cpu.c',
202
'crypto_helper.c',
203
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
204
'neon_helper.c',
205
'op_helper.c',
206
'tlb_helper.c',
207
- 'translate.c',
208
- 'translate-m-nocp.c',
209
- 'translate-mve.c',
210
- 'translate-neon.c',
211
- 'translate-vfp.c',
212
'vec_helper.c',
213
'vfp_helper.c',
214
'cpu_tcg.c',
215
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
216
'pauth_helper.c',
217
'sve_helper.c',
218
'sme_helper.c',
219
- 'translate-a64.c',
220
- 'translate-sve.c',
221
- 'translate-sme.c',
222
))
223
224
arm_softmmu_ss = ss.source_set()
225
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
226
227
subdir('hvf')
228
229
+if 'CONFIG_TCG' in config_all
230
+ subdir('tcg')
231
+endif
232
+
233
target_arch += {'arm': arm_ss}
234
target_softmmu_arch += {'arm': arm_softmmu_ss}
235
diff --git a/target/arm/meson.build b/target/arm/tcg/meson.build
236
similarity index 64%
237
copy from target/arm/meson.build
238
copy to target/arm/tcg/meson.build
239
index XXXXXXX..XXXXXXX 100644
240
--- a/target/arm/meson.build
241
+++ b/target/arm/tcg/meson.build
242
@@ -XXX,XX +XXX,XX @@ gen = [
243
decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
244
]
245
246
-arm_ss = ss.source_set()
247
arm_ss.add(gen)
248
+
249
arm_ss.add(files(
250
- 'cpu.c',
251
- 'crypto_helper.c',
252
- 'debug_helper.c',
253
- 'gdbstub.c',
254
- 'helper.c',
255
- 'iwmmxt_helper.c',
256
- 'm_helper.c',
257
- 'mve_helper.c',
258
- 'neon_helper.c',
259
- 'op_helper.c',
260
- 'tlb_helper.c',
261
'translate.c',
262
'translate-m-nocp.c',
263
'translate-mve.c',
264
'translate-neon.c',
265
'translate-vfp.c',
266
- 'vec_helper.c',
267
- 'vfp_helper.c',
268
- 'cpu_tcg.c',
269
))
270
-arm_ss.add(zlib)
271
-
272
-arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
273
274
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
275
- 'cpu64.c',
276
- 'gdbstub64.c',
277
- 'helper-a64.c',
278
- 'mte_helper.c',
279
- 'pauth_helper.c',
280
- 'sve_helper.c',
281
- 'sme_helper.c',
282
'translate-a64.c',
283
'translate-sve.c',
284
'translate-sme.c',
285
))
286
-
287
-arm_softmmu_ss = ss.source_set()
288
-arm_softmmu_ss.add(files(
289
- 'arch_dump.c',
290
- 'arm-powerctl.c',
291
- 'machine.c',
292
- 'monitor.c',
293
- 'psci.c',
294
- 'ptw.c',
295
-))
296
-
297
-subdir('hvf')
298
-
299
-target_arch += {'arm': arm_ss}
300
-target_softmmu_arch += {'arm': arm_softmmu_ss}
301
--
302
2.34.1
303
304
diff view generated by jsdifflib
New patch
[PULL 05/25] target/arm: move helpers to tcg/
1
1
From: Claudio Fontana <cfontana@suse.de>
2
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
4
Signed-off-by: Fabiano Rosas <farosas@suse.de>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/{ => tcg}/vec_internal.h | 0
11
target/arm/tcg-stubs.c | 23 +++++++++++++++++++++++
12
target/arm/{ => tcg}/crypto_helper.c | 0
13
target/arm/{ => tcg}/helper-a64.c | 0
14
target/arm/{ => tcg}/iwmmxt_helper.c | 0
15
target/arm/{ => tcg}/m_helper.c | 0
16
target/arm/{ => tcg}/mte_helper.c | 0
17
target/arm/{ => tcg}/mve_helper.c | 0
18
target/arm/{ => tcg}/neon_helper.c | 0
19
target/arm/{ => tcg}/op_helper.c | 0
20
target/arm/{ => tcg}/pauth_helper.c | 0
21
target/arm/{ => tcg}/sme_helper.c | 0
22
target/arm/{ => tcg}/sve_helper.c | 0
23
target/arm/{ => tcg}/tlb_helper.c | 0
24
target/arm/{ => tcg}/vec_helper.c | 0
25
target/arm/meson.build | 15 ++-------------
26
target/arm/tcg/meson.build | 13 +++++++++++++
27
17 files changed, 38 insertions(+), 13 deletions(-)
28
rename target/arm/{ => tcg}/vec_internal.h (100%)
29
create mode 100644 target/arm/tcg-stubs.c
30
rename target/arm/{ => tcg}/crypto_helper.c (100%)
31
rename target/arm/{ => tcg}/helper-a64.c (100%)
32
rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
33
rename target/arm/{ => tcg}/m_helper.c (100%)
34
rename target/arm/{ => tcg}/mte_helper.c (100%)
35
rename target/arm/{ => tcg}/mve_helper.c (100%)
36
rename target/arm/{ => tcg}/neon_helper.c (100%)
37
rename target/arm/{ => tcg}/op_helper.c (100%)
38
rename target/arm/{ => tcg}/pauth_helper.c (100%)
39
rename target/arm/{ => tcg}/sme_helper.c (100%)
40
rename target/arm/{ => tcg}/sve_helper.c (100%)
41
rename target/arm/{ => tcg}/tlb_helper.c (100%)
42
rename target/arm/{ => tcg}/vec_helper.c (100%)
43
44
diff --git a/target/arm/vec_internal.h b/target/arm/tcg/vec_internal.h
45
similarity index 100%
46
rename from target/arm/vec_internal.h
47
rename to target/arm/tcg/vec_internal.h
48
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
49
new file mode 100644
50
index XXXXXXX..XXXXXXX
51
--- /dev/null
52
+++ b/target/arm/tcg-stubs.c
53
@@ -XXX,XX +XXX,XX @@
54
+/*
55
+ * QEMU ARM stubs for some TCG helper functions
56
+ *
57
+ * Copyright 2021 SUSE LLC
58
+ *
59
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
60
+ * See the COPYING file in the top-level directory.
61
+ */
62
+
63
+#include "qemu/osdep.h"
64
+#include "cpu.h"
65
+#include "internals.h"
66
+
67
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
68
+{
69
+ g_assert_not_reached();
70
+}
71
+
72
+void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
73
+ uint32_t target_el, uintptr_t ra)
74
+{
75
+ g_assert_not_reached();
76
+}
77
diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c
78
similarity index 100%
79
rename from target/arm/crypto_helper.c
80
rename to target/arm/tcg/crypto_helper.c
81
diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c
82
similarity index 100%
83
rename from target/arm/helper-a64.c
84
rename to target/arm/tcg/helper-a64.c
85
diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c
86
similarity index 100%
87
rename from target/arm/iwmmxt_helper.c
88
rename to target/arm/tcg/iwmmxt_helper.c
89
diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c
90
similarity index 100%
91
rename from target/arm/m_helper.c
92
rename to target/arm/tcg/m_helper.c
93
diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c
94
similarity index 100%
95
rename from target/arm/mte_helper.c
96
rename to target/arm/tcg/mte_helper.c
97
diff --git a/target/arm/mve_helper.c b/target/arm/tcg/mve_helper.c
98
similarity index 100%
99
rename from target/arm/mve_helper.c
100
rename to target/arm/tcg/mve_helper.c
101
diff --git a/target/arm/neon_helper.c b/target/arm/tcg/neon_helper.c
102
similarity index 100%
103
rename from target/arm/neon_helper.c
104
rename to target/arm/tcg/neon_helper.c
105
diff --git a/target/arm/op_helper.c b/target/arm/tcg/op_helper.c
106
similarity index 100%
107
rename from target/arm/op_helper.c
108
rename to target/arm/tcg/op_helper.c
109
diff --git a/target/arm/pauth_helper.c b/target/arm/tcg/pauth_helper.c
110
similarity index 100%
111
rename from target/arm/pauth_helper.c
112
rename to target/arm/tcg/pauth_helper.c
113
diff --git a/target/arm/sme_helper.c b/target/arm/tcg/sme_helper.c
114
similarity index 100%
115
rename from target/arm/sme_helper.c
116
rename to target/arm/tcg/sme_helper.c
117
diff --git a/target/arm/sve_helper.c b/target/arm/tcg/sve_helper.c
118
similarity index 100%
119
rename from target/arm/sve_helper.c
120
rename to target/arm/tcg/sve_helper.c
121
diff --git a/target/arm/tlb_helper.c b/target/arm/tcg/tlb_helper.c
122
similarity index 100%
123
rename from target/arm/tlb_helper.c
124
rename to target/arm/tcg/tlb_helper.c
125
diff --git a/target/arm/vec_helper.c b/target/arm/tcg/vec_helper.c
126
similarity index 100%
127
rename from target/arm/vec_helper.c
128
rename to target/arm/tcg/vec_helper.c
129
diff --git a/target/arm/meson.build b/target/arm/meson.build
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/meson.build
132
+++ b/target/arm/meson.build
133
@@ -XXX,XX +XXX,XX @@
134
arm_ss = ss.source_set()
135
arm_ss.add(files(
136
'cpu.c',
137
- 'crypto_helper.c',
138
'debug_helper.c',
139
'gdbstub.c',
140
'helper.c',
141
- 'iwmmxt_helper.c',
142
- 'm_helper.c',
143
- 'mve_helper.c',
144
- 'neon_helper.c',
145
- 'op_helper.c',
146
- 'tlb_helper.c',
147
- 'vec_helper.c',
148
'vfp_helper.c',
149
'cpu_tcg.c',
150
))
151
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: fil
152
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
153
'cpu64.c',
154
'gdbstub64.c',
155
- 'helper-a64.c',
156
- 'mte_helper.c',
157
- 'pauth_helper.c',
158
- 'sve_helper.c',
159
- 'sme_helper.c',
160
))
161
162
arm_softmmu_ss = ss.source_set()
163
@@ -XXX,XX +XXX,XX @@ subdir('hvf')
164
165
if 'CONFIG_TCG' in config_all
166
subdir('tcg')
167
+else
168
+ arm_ss.add(files('tcg-stubs.c'))
169
endif
170
171
target_arch += {'arm': arm_ss}
172
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
173
index XXXXXXX..XXXXXXX 100644
174
--- a/target/arm/tcg/meson.build
175
+++ b/target/arm/tcg/meson.build
176
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
177
'translate-mve.c',
178
'translate-neon.c',
179
'translate-vfp.c',
180
+ 'crypto_helper.c',
181
+ 'iwmmxt_helper.c',
182
+ 'm_helper.c',
183
+ 'mve_helper.c',
184
+ 'neon_helper.c',
185
+ 'op_helper.c',
186
+ 'tlb_helper.c',
187
+ 'vec_helper.c',
188
))
189
190
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
191
'translate-a64.c',
192
'translate-sve.c',
193
'translate-sme.c',
194
+ 'helper-a64.c',
195
+ 'mte_helper.c',
196
+ 'pauth_helper.c',
197
+ 'sme_helper.c',
198
+ 'sve_helper.c',
199
))
200
--
201
2.34.1
202
203
diff view generated by jsdifflib
New patch
[PULL 06/25] target/arm: Move psci.c into the tcg directory
1
From: Claudio Fontana <cfontana@suse.de>
1
2
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
4
Signed-off-by: Fabiano Rosas <farosas@suse.de>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/{ => tcg}/psci.c | 0
11
target/arm/meson.build | 1 -
12
target/arm/tcg/meson.build | 4 ++++
13
3 files changed, 4 insertions(+), 1 deletion(-)
14
rename target/arm/{ => tcg}/psci.c (100%)
15
16
diff --git a/target/arm/psci.c b/target/arm/tcg/psci.c
17
similarity index 100%
18
rename from target/arm/psci.c
19
rename to target/arm/tcg/psci.c
20
diff --git a/target/arm/meson.build b/target/arm/meson.build
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/meson.build
23
+++ b/target/arm/meson.build
24
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
25
'arm-powerctl.c',
26
'machine.c',
27
'monitor.c',
28
- 'psci.c',
29
'ptw.c',
30
))
31
32
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/meson.build
35
+++ b/target/arm/tcg/meson.build
36
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
37
'sme_helper.c',
38
'sve_helper.c',
39
))
40
+
41
+arm_softmmu_ss.add(files(
42
+ 'psci.c',
43
+))
44
--
45
2.34.1
46
47
diff view generated by jsdifflib
New patch
[PULL 07/25] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
1
1
From: Fabiano Rosas <farosas@suse.de>
2
3
This is in preparation to moving the hflags code into its own file
4
under the tcg/ directory.
5
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/boot.c | 6 +++++-
12
hw/intc/armv7m_nvic.c | 20 +++++++++++++-------
13
target/arm/arm-powerctl.c | 7 +++++--
14
target/arm/cpu.c | 3 ++-
15
target/arm/helper.c | 18 +++++++++++++-----
16
target/arm/machine.c | 5 ++++-
17
6 files changed, 42 insertions(+), 17 deletions(-)
18
19
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/boot.c
22
+++ b/hw/arm/boot.c
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/arm/boot.h"
25
#include "hw/arm/linux-boot-if.h"
26
#include "sysemu/kvm.h"
27
+#include "sysemu/tcg.h"
28
#include "sysemu/sysemu.h"
29
#include "sysemu/numa.h"
30
#include "hw/boards.h"
31
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
32
info->secondary_cpu_reset_hook(cpu, info);
33
}
34
}
35
- arm_rebuild_hflags(env);
36
+
37
+ if (tcg_enabled()) {
38
+ arm_rebuild_hflags(env);
39
+ }
40
}
41
}
42
43
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/armv7m_nvic.c
46
+++ b/hw/intc/armv7m_nvic.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "hw/intc/armv7m_nvic.h"
49
#include "hw/irq.h"
50
#include "hw/qdev-properties.h"
51
+#include "sysemu/tcg.h"
52
#include "sysemu/runstate.h"
53
#include "target/arm/cpu.h"
54
#include "exec/exec-all.h"
55
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
56
/* This is UNPREDICTABLE; treat as RAZ/WI */
57
58
exit_ok:
59
- /* Ensure any changes made are reflected in the cached hflags. */
60
- arm_rebuild_hflags(&s->cpu->env);
61
+ if (tcg_enabled()) {
62
+ /* Ensure any changes made are reflected in the cached hflags. */
63
+ arm_rebuild_hflags(&s->cpu->env);
64
+ }
65
return MEMTX_OK;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
69
}
70
}
71
72
- /*
73
- * We updated state that affects the CPU's MMUidx and thus its hflags;
74
- * and we can't guarantee that we run before the CPU reset function.
75
- */
76
- arm_rebuild_hflags(&s->cpu->env);
77
+ if (tcg_enabled()) {
78
+ /*
79
+ * We updated state that affects the CPU's MMUidx and thus its
80
+ * hflags; and we can't guarantee that we run before the CPU
81
+ * reset function.
82
+ */
83
+ arm_rebuild_hflags(&s->cpu->env);
84
+ }
85
}
86
87
static void nvic_systick_trigger(void *opaque, int n, int level)
88
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/arm-powerctl.c
91
+++ b/target/arm/arm-powerctl.c
92
@@ -XXX,XX +XXX,XX @@
93
#include "arm-powerctl.h"
94
#include "qemu/log.h"
95
#include "qemu/main-loop.h"
96
+#include "sysemu/tcg.h"
97
98
#ifndef DEBUG_ARM_POWERCTL
99
#define DEBUG_ARM_POWERCTL 0
100
@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
101
target_cpu->env.regs[0] = info->context_id;
102
}
103
104
- /* CP15 update requires rebuilding hflags */
105
- arm_rebuild_hflags(&target_cpu->env);
106
+ if (tcg_enabled()) {
107
+ /* CP15 update requires rebuilding hflags */
108
+ arm_rebuild_hflags(&target_cpu->env);
109
+ }
110
111
/* Start the new CPU at the requested address */
112
cpu_set_pc(target_cpu_state, info->entry);
113
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/cpu.c
116
+++ b/target/arm/cpu.c
117
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
118
if (tcg_enabled()) {
119
hw_breakpoint_update_all(cpu);
120
hw_watchpoint_update_all(cpu);
121
+
122
+ arm_rebuild_hflags(env);
123
}
124
- arm_rebuild_hflags(env);
125
}
126
127
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
128
diff --git a/target/arm/helper.c b/target/arm/helper.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/helper.c
131
+++ b/target/arm/helper.c
132
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
133
/* This may enable/disable the MMU, so do a TLB flush. */
134
tlb_flush(CPU(cpu));
135
136
- if (ri->type & ARM_CP_SUPPRESS_TB_END) {
137
+ if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) {
138
/*
139
* Normally we would always end the TB on an SCTLR write; see the
140
* comment in ARMCPRegInfo sctlr initialization below for why Xscale
141
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
142
memset(env->zarray, 0, sizeof(env->zarray));
143
}
144
145
- arm_rebuild_hflags(env);
146
+ if (tcg_enabled()) {
147
+ arm_rebuild_hflags(env);
148
+ }
149
}
150
151
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
152
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
153
}
154
mask &= ~CACHED_CPSR_BITS;
155
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
156
- if (rebuild_hflags) {
157
+ if (tcg_enabled() && rebuild_hflags) {
158
arm_rebuild_hflags(env);
159
}
160
}
161
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
162
env->regs[14] = env->regs[15] + offset;
163
}
164
env->regs[15] = newpc;
165
- arm_rebuild_hflags(env);
166
+
167
+ if (tcg_enabled()) {
168
+ arm_rebuild_hflags(env);
169
+ }
170
}
171
172
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
173
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
174
pstate_write(env, PSTATE_DAIF | new_mode);
175
env->aarch64 = true;
176
aarch64_restore_sp(env, new_el);
177
- helper_rebuild_hflags_a64(env, new_el);
178
+
179
+ if (tcg_enabled()) {
180
+ helper_rebuild_hflags_a64(env, new_el);
181
+ }
182
183
env->pc = addr;
184
185
diff --git a/target/arm/machine.c b/target/arm/machine.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/target/arm/machine.c
188
+++ b/target/arm/machine.c
189
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
190
if (!kvm_enabled()) {
191
pmu_op_finish(&cpu->env);
192
}
193
- arm_rebuild_hflags(&cpu->env);
194
+
195
+ if (tcg_enabled()) {
196
+ arm_rebuild_hflags(&cpu->env);
197
+ }
198
199
return 0;
200
}
201
--
202
2.34.1
203
204
diff view generated by jsdifflib
[PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2
[PULL 08/25] target/arm: Move hflags code into the tcg directory
1
From: Marc Zyngier <maz@kernel.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
3
The hflags are used only for TCG code, so introduce a new file
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
4
hflags.c to keep that code.
5
SError interrupts.
6
5
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
bits, and ignores the current exception level. This means a hypervisor
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
trying to look at its own interrupt state actually sees the guest
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
state, which is unexpected and breaks KVM as of Linux 5.3.
11
12
Instead, check for the running EL and return the physical bits
13
if not running in a virtualized context.
14
15
Fixes: 636540e9c40b
16
Cc: qemu-stable@nongnu.org
17
Reported-by: Quentin Perret <qperret@google.com>
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
19
Message-id: 20191122135833.28953-1-maz@kernel.org
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
10
---
24
target/arm/helper.c | 7 +++++--
11
target/arm/internals.h | 2 +
25
1 file changed, 5 insertions(+), 2 deletions(-)
12
target/arm/helper.c | 393 +-----------------------------------
13
target/arm/tcg-stubs.c | 4 +
14
target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++++++++++++++
15
target/arm/tcg/meson.build | 1 +
16
5 files changed, 411 insertions(+), 392 deletions(-)
17
create mode 100644 target/arm/tcg/hflags.c
26
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
24
25
int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
26
int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
27
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
28
29
/* Determine if allocation tags are available. */
30
static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
31
@@ -XXX,XX +XXX,XX @@ static inline bool arm_fgt_active(CPUARMState *env, int el)
32
(!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
33
}
34
35
+void assert_hflags_rebuild_correctly(CPUARMState *env);
36
#endif
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
39
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
40
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
41
@@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el)
32
CPUState *cs = env_cpu(env);
42
return 0;
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
43
}
34
uint64_t ret = 0;
44
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
45
-/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
36
+ (!arm_is_secure_below_el3(env) ||
46
-static bool sme_fa64(CPUARMState *env, int el)
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
47
-{
38
48
- if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
39
- if (hcr_el2 & HCR_IMO) {
49
- return false;
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
50
- }
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
51
-
42
ret |= CPSR_I;
52
- if (el <= 1 && !el_is_in_host(env, el)) {
43
}
53
- if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
54
- return false;
45
}
55
- }
56
- }
57
- if (el <= 2 && arm_is_el2_enabled(env)) {
58
- if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
59
- return false;
60
- }
61
- }
62
- if (arm_feature(env, ARM_FEATURE_EL3)) {
63
- if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
64
- return false;
65
- }
66
- }
67
-
68
- return true;
69
-}
70
-
71
/*
72
* Given that SVE is enabled, return the vector length for EL.
73
*/
74
@@ -XXX,XX +XXX,XX @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
46
}
75
}
47
76
}
48
- if (hcr_el2 & HCR_FMO) {
77
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
78
-static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
79
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
51
ret |= CPSR_F;
80
{
52
}
81
if (regime_has_2_ranges(mmu_idx)) {
82
return extract64(tcr, 57, 2);
83
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
84
return arm_mmu_idx_el(env, arm_current_el(env));
85
}
86
87
-static inline bool fgt_svc(CPUARMState *env, int el)
88
-{
89
- /*
90
- * Assuming fine-grained-traps are active, return true if we
91
- * should be trapping on SVC instructions. Only AArch64 can
92
- * trap on an SVC at EL1, but we don't need to special-case this
93
- * because if this is AArch32 EL1 then arm_fgt_active() is false.
94
- * We also know el is 0 or 1.
95
- */
96
- return el == 0 ?
97
- FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
98
- FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
99
-}
100
-
101
-static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
102
- ARMMMUIdx mmu_idx,
103
- CPUARMTBFlags flags)
104
-{
105
- DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
106
- DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
107
-
108
- if (arm_singlestep_active(env)) {
109
- DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
110
- }
111
-
112
- return flags;
113
-}
114
-
115
-static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
116
- ARMMMUIdx mmu_idx,
117
- CPUARMTBFlags flags)
118
-{
119
- bool sctlr_b = arm_sctlr_b(env);
120
-
121
- if (sctlr_b) {
122
- DP_TBFLAG_A32(flags, SCTLR__B, 1);
123
- }
124
- if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
125
- DP_TBFLAG_ANY(flags, BE_DATA, 1);
126
- }
127
- DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
128
-
129
- return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
130
-}
131
-
132
-static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
133
- ARMMMUIdx mmu_idx)
134
-{
135
- CPUARMTBFlags flags = {};
136
- uint32_t ccr = env->v7m.ccr[env->v7m.secure];
137
-
138
- /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
139
- if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
140
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
141
- }
142
-
143
- if (arm_v7m_is_handler_mode(env)) {
144
- DP_TBFLAG_M32(flags, HANDLER, 1);
145
- }
146
-
147
- /*
148
- * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
149
- * is suppressing them because the requested execution priority
150
- * is less than 0.
151
- */
152
- if (arm_feature(env, ARM_FEATURE_V8) &&
153
- !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
154
- (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
155
- DP_TBFLAG_M32(flags, STACKCHECK, 1);
156
- }
157
-
158
- if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
159
- DP_TBFLAG_M32(flags, SECURE, 1);
160
- }
161
-
162
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
163
-}
164
-
165
-static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
166
- ARMMMUIdx mmu_idx)
167
-{
168
- CPUARMTBFlags flags = {};
169
- int el = arm_current_el(env);
170
-
171
- if (arm_sctlr(env, el) & SCTLR_A) {
172
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
173
- }
174
-
175
- if (arm_el_is_aa64(env, 1)) {
176
- DP_TBFLAG_A32(flags, VFPEN, 1);
177
- }
178
-
179
- if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
180
- (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
181
- DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
182
- }
183
-
184
- if (arm_fgt_active(env, el)) {
185
- DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
186
- if (fgt_svc(env, el)) {
187
- DP_TBFLAG_ANY(flags, FGT_SVC, 1);
188
- }
189
- }
190
-
191
- if (env->uncached_cpsr & CPSR_IL) {
192
- DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
193
- }
194
-
195
- /*
196
- * The SME exception we are testing for is raised via
197
- * AArch64.CheckFPAdvSIMDEnabled(), as called from
198
- * AArch32.CheckAdvSIMDOrFPEnabled().
199
- */
200
- if (el == 0
201
- && FIELD_EX64(env->svcr, SVCR, SM)
202
- && (!arm_is_el2_enabled(env)
203
- || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
204
- && arm_el_is_aa64(env, 1)
205
- && !sme_fa64(env, el)) {
206
- DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
207
- }
208
-
209
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
210
-}
211
-
212
-static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
213
- ARMMMUIdx mmu_idx)
214
-{
215
- CPUARMTBFlags flags = {};
216
- ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
217
- uint64_t tcr = regime_tcr(env, mmu_idx);
218
- uint64_t sctlr;
219
- int tbii, tbid;
220
-
221
- DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
222
-
223
- /* Get control bits for tagged addresses. */
224
- tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
225
- tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
226
-
227
- DP_TBFLAG_A64(flags, TBII, tbii);
228
- DP_TBFLAG_A64(flags, TBID, tbid);
229
-
230
- if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
231
- int sve_el = sve_exception_el(env, el);
232
-
233
- /*
234
- * If either FP or SVE are disabled, translator does not need len.
235
- * If SVE EL > FP EL, FP exception has precedence, and translator
236
- * does not need SVE EL. Save potential re-translations by forcing
237
- * the unneeded data to zero.
238
- */
239
- if (fp_el != 0) {
240
- if (sve_el > fp_el) {
241
- sve_el = 0;
242
- }
243
- } else if (sve_el == 0) {
244
- DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
245
- }
246
- DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
247
- }
248
- if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
249
- int sme_el = sme_exception_el(env, el);
250
- bool sm = FIELD_EX64(env->svcr, SVCR, SM);
251
-
252
- DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
253
- if (sme_el == 0) {
254
- /* Similarly, do not compute SVL if SME is disabled. */
255
- int svl = sve_vqm1_for_el_sm(env, el, true);
256
- DP_TBFLAG_A64(flags, SVL, svl);
257
- if (sm) {
258
- /* If SVE is disabled, we will not have set VL above. */
259
- DP_TBFLAG_A64(flags, VL, svl);
260
- }
261
- }
262
- if (sm) {
263
- DP_TBFLAG_A64(flags, PSTATE_SM, 1);
264
- DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
265
- }
266
- DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
267
- }
268
-
269
- sctlr = regime_sctlr(env, stage1);
270
-
271
- if (sctlr & SCTLR_A) {
272
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
273
- }
274
-
275
- if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
276
- DP_TBFLAG_ANY(flags, BE_DATA, 1);
277
- }
278
-
279
- if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
280
- /*
281
- * In order to save space in flags, we record only whether
282
- * pauth is "inactive", meaning all insns are implemented as
283
- * a nop, or "active" when some action must be performed.
284
- * The decision of which action to take is left to a helper.
285
- */
286
- if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
287
- DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
288
- }
289
- }
290
-
291
- if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
292
- /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
293
- if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
294
- DP_TBFLAG_A64(flags, BT, 1);
295
- }
296
- }
297
-
298
- /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
299
- if (!(env->pstate & PSTATE_UAO)) {
300
- switch (mmu_idx) {
301
- case ARMMMUIdx_E10_1:
302
- case ARMMMUIdx_E10_1_PAN:
303
- /* TODO: ARMv8.3-NV */
304
- DP_TBFLAG_A64(flags, UNPRIV, 1);
305
- break;
306
- case ARMMMUIdx_E20_2:
307
- case ARMMMUIdx_E20_2_PAN:
308
- /*
309
- * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
310
- * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
311
- */
312
- if (env->cp15.hcr_el2 & HCR_TGE) {
313
- DP_TBFLAG_A64(flags, UNPRIV, 1);
314
- }
315
- break;
316
- default:
317
- break;
318
- }
319
- }
320
-
321
- if (env->pstate & PSTATE_IL) {
322
- DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
323
- }
324
-
325
- if (arm_fgt_active(env, el)) {
326
- DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
327
- if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
328
- DP_TBFLAG_A64(flags, FGT_ERET, 1);
329
- }
330
- if (fgt_svc(env, el)) {
331
- DP_TBFLAG_ANY(flags, FGT_SVC, 1);
332
- }
333
- }
334
-
335
- if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
336
- /*
337
- * Set MTE_ACTIVE if any access may be Checked, and leave clear
338
- * if all accesses must be Unchecked:
339
- * 1) If no TBI, then there are no tags in the address to check,
340
- * 2) If Tag Check Override, then all accesses are Unchecked,
341
- * 3) If Tag Check Fail == 0, then Checked access have no effect,
342
- * 4) If no Allocation Tag Access, then all accesses are Unchecked.
343
- */
344
- if (allocation_tag_access_enabled(env, el, sctlr)) {
345
- DP_TBFLAG_A64(flags, ATA, 1);
346
- if (tbid
347
- && !(env->pstate & PSTATE_TCO)
348
- && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
349
- DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
350
- }
351
- }
352
- /* And again for unprivileged accesses, if required. */
353
- if (EX_TBFLAG_A64(flags, UNPRIV)
354
- && tbid
355
- && !(env->pstate & PSTATE_TCO)
356
- && (sctlr & SCTLR_TCF0)
357
- && allocation_tag_access_enabled(env, 0, sctlr)) {
358
- DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
359
- }
360
- /* Cache TCMA as well as TBI. */
361
- DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
362
- }
363
-
364
- return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
365
-}
366
-
367
-static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
368
-{
369
- int el = arm_current_el(env);
370
- int fp_el = fp_exception_el(env, el);
371
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
372
-
373
- if (is_a64(env)) {
374
- return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
375
- } else if (arm_feature(env, ARM_FEATURE_M)) {
376
- return rebuild_hflags_m32(env, fp_el, mmu_idx);
377
- } else {
378
- return rebuild_hflags_a32(env, fp_el, mmu_idx);
379
- }
380
-}
381
-
382
-void arm_rebuild_hflags(CPUARMState *env)
383
-{
384
- env->hflags = rebuild_hflags_internal(env);
385
-}
386
-
387
-/*
388
- * If we have triggered a EL state change we can't rely on the
389
- * translator having passed it to us, we need to recompute.
390
- */
391
-void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
392
-{
393
- int el = arm_current_el(env);
394
- int fp_el = fp_exception_el(env, el);
395
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
396
-
397
- env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
398
-}
399
-
400
-void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
401
-{
402
- int fp_el = fp_exception_el(env, el);
403
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
404
-
405
- env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
406
-}
407
-
408
-/*
409
- * If we have triggered a EL state change we can't rely on the
410
- * translator having passed it to us, we need to recompute.
411
- */
412
-void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
413
-{
414
- int el = arm_current_el(env);
415
- int fp_el = fp_exception_el(env, el);
416
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
417
- env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
418
-}
419
-
420
-void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
421
-{
422
- int fp_el = fp_exception_el(env, el);
423
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
424
-
425
- env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
426
-}
427
-
428
-void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
429
-{
430
- int fp_el = fp_exception_el(env, el);
431
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
432
-
433
- env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
434
-}
435
-
436
-static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
437
-{
438
-#ifdef CONFIG_DEBUG_TCG
439
- CPUARMTBFlags c = env->hflags;
440
- CPUARMTBFlags r = rebuild_hflags_internal(env);
441
-
442
- if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
443
- fprintf(stderr, "TCG hflags mismatch "
444
- "(current:(0x%08x,0x" TARGET_FMT_lx ")"
445
- " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
446
- c.flags, c.flags2, r.flags, r.flags2);
447
- abort();
448
- }
449
-#endif
450
-}
451
-
452
static bool mve_no_pred(CPUARMState *env)
453
{
454
/*
455
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
456
index XXXXXXX..XXXXXXX 100644
457
--- a/target/arm/tcg-stubs.c
458
+++ b/target/arm/tcg-stubs.c
459
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
460
{
461
g_assert_not_reached();
462
}
463
+/* Temporarily while cpu_get_tb_cpu_state() is still in common code */
464
+void assert_hflags_rebuild_correctly(CPUARMState *env)
465
+{
466
+}
467
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
468
new file mode 100644
469
index XXXXXXX..XXXXXXX
470
--- /dev/null
471
+++ b/target/arm/tcg/hflags.c
472
@@ -XXX,XX +XXX,XX @@
473
+/*
474
+ * ARM hflags
475
+ *
476
+ * This code is licensed under the GNU GPL v2 or later.
477
+ *
478
+ * SPDX-License-Identifier: GPL-2.0-or-later
479
+ */
480
+#include "qemu/osdep.h"
481
+#include "cpu.h"
482
+#include "internals.h"
483
+#include "exec/helper-proto.h"
484
+#include "cpregs.h"
485
+
486
+static inline bool fgt_svc(CPUARMState *env, int el)
487
+{
488
+ /*
489
+ * Assuming fine-grained-traps are active, return true if we
490
+ * should be trapping on SVC instructions. Only AArch64 can
491
+ * trap on an SVC at EL1, but we don't need to special-case this
492
+ * because if this is AArch32 EL1 then arm_fgt_active() is false.
493
+ * We also know el is 0 or 1.
494
+ */
495
+ return el == 0 ?
496
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
497
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
498
+}
499
+
500
+static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
501
+ ARMMMUIdx mmu_idx,
502
+ CPUARMTBFlags flags)
503
+{
504
+ DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
505
+ DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
506
+
507
+ if (arm_singlestep_active(env)) {
508
+ DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
509
+ }
510
+
511
+ return flags;
512
+}
513
+
514
+static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
515
+ ARMMMUIdx mmu_idx,
516
+ CPUARMTBFlags flags)
517
+{
518
+ bool sctlr_b = arm_sctlr_b(env);
519
+
520
+ if (sctlr_b) {
521
+ DP_TBFLAG_A32(flags, SCTLR__B, 1);
522
+ }
523
+ if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
524
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
525
+ }
526
+ DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
527
+
528
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
529
+}
530
+
531
+static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
532
+ ARMMMUIdx mmu_idx)
533
+{
534
+ CPUARMTBFlags flags = {};
535
+ uint32_t ccr = env->v7m.ccr[env->v7m.secure];
536
+
537
+ /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
538
+ if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
539
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
540
+ }
541
+
542
+ if (arm_v7m_is_handler_mode(env)) {
543
+ DP_TBFLAG_M32(flags, HANDLER, 1);
544
+ }
545
+
546
+ /*
547
+ * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
548
+ * is suppressing them because the requested execution priority
549
+ * is less than 0.
550
+ */
551
+ if (arm_feature(env, ARM_FEATURE_V8) &&
552
+ !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
553
+ (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
554
+ DP_TBFLAG_M32(flags, STACKCHECK, 1);
555
+ }
556
+
557
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
558
+ DP_TBFLAG_M32(flags, SECURE, 1);
559
+ }
560
+
561
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
562
+}
563
+
564
+/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
565
+static bool sme_fa64(CPUARMState *env, int el)
566
+{
567
+ if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
568
+ return false;
569
+ }
570
+
571
+ if (el <= 1 && !el_is_in_host(env, el)) {
572
+ if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
573
+ return false;
574
+ }
575
+ }
576
+ if (el <= 2 && arm_is_el2_enabled(env)) {
577
+ if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
578
+ return false;
579
+ }
580
+ }
581
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
582
+ if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
583
+ return false;
584
+ }
585
+ }
586
+
587
+ return true;
588
+}
589
+
590
+static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
591
+ ARMMMUIdx mmu_idx)
592
+{
593
+ CPUARMTBFlags flags = {};
594
+ int el = arm_current_el(env);
595
+
596
+ if (arm_sctlr(env, el) & SCTLR_A) {
597
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
598
+ }
599
+
600
+ if (arm_el_is_aa64(env, 1)) {
601
+ DP_TBFLAG_A32(flags, VFPEN, 1);
602
+ }
603
+
604
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
605
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
606
+ DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
607
+ }
608
+
609
+ if (arm_fgt_active(env, el)) {
610
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
611
+ if (fgt_svc(env, el)) {
612
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
613
+ }
614
+ }
615
+
616
+ if (env->uncached_cpsr & CPSR_IL) {
617
+ DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
618
+ }
619
+
620
+ /*
621
+ * The SME exception we are testing for is raised via
622
+ * AArch64.CheckFPAdvSIMDEnabled(), as called from
623
+ * AArch32.CheckAdvSIMDOrFPEnabled().
624
+ */
625
+ if (el == 0
626
+ && FIELD_EX64(env->svcr, SVCR, SM)
627
+ && (!arm_is_el2_enabled(env)
628
+ || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
629
+ && arm_el_is_aa64(env, 1)
630
+ && !sme_fa64(env, el)) {
631
+ DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
632
+ }
633
+
634
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
635
+}
636
+
637
+static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
638
+ ARMMMUIdx mmu_idx)
639
+{
640
+ CPUARMTBFlags flags = {};
641
+ ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
642
+ uint64_t tcr = regime_tcr(env, mmu_idx);
643
+ uint64_t sctlr;
644
+ int tbii, tbid;
645
+
646
+ DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
647
+
648
+ /* Get control bits for tagged addresses. */
649
+ tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
650
+ tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
651
+
652
+ DP_TBFLAG_A64(flags, TBII, tbii);
653
+ DP_TBFLAG_A64(flags, TBID, tbid);
654
+
655
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
656
+ int sve_el = sve_exception_el(env, el);
657
+
658
+ /*
659
+ * If either FP or SVE are disabled, translator does not need len.
660
+ * If SVE EL > FP EL, FP exception has precedence, and translator
661
+ * does not need SVE EL. Save potential re-translations by forcing
662
+ * the unneeded data to zero.
663
+ */
664
+ if (fp_el != 0) {
665
+ if (sve_el > fp_el) {
666
+ sve_el = 0;
667
+ }
668
+ } else if (sve_el == 0) {
669
+ DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
670
+ }
671
+ DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
672
+ }
673
+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
674
+ int sme_el = sme_exception_el(env, el);
675
+ bool sm = FIELD_EX64(env->svcr, SVCR, SM);
676
+
677
+ DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
678
+ if (sme_el == 0) {
679
+ /* Similarly, do not compute SVL if SME is disabled. */
680
+ int svl = sve_vqm1_for_el_sm(env, el, true);
681
+ DP_TBFLAG_A64(flags, SVL, svl);
682
+ if (sm) {
683
+ /* If SVE is disabled, we will not have set VL above. */
684
+ DP_TBFLAG_A64(flags, VL, svl);
685
+ }
686
+ }
687
+ if (sm) {
688
+ DP_TBFLAG_A64(flags, PSTATE_SM, 1);
689
+ DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
690
+ }
691
+ DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
692
+ }
693
+
694
+ sctlr = regime_sctlr(env, stage1);
695
+
696
+ if (sctlr & SCTLR_A) {
697
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
698
+ }
699
+
700
+ if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
701
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
702
+ }
703
+
704
+ if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
705
+ /*
706
+ * In order to save space in flags, we record only whether
707
+ * pauth is "inactive", meaning all insns are implemented as
708
+ * a nop, or "active" when some action must be performed.
709
+ * The decision of which action to take is left to a helper.
710
+ */
711
+ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
712
+ DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
713
+ }
714
+ }
715
+
716
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
717
+ /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
718
+ if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
719
+ DP_TBFLAG_A64(flags, BT, 1);
720
+ }
721
+ }
722
+
723
+ /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
724
+ if (!(env->pstate & PSTATE_UAO)) {
725
+ switch (mmu_idx) {
726
+ case ARMMMUIdx_E10_1:
727
+ case ARMMMUIdx_E10_1_PAN:
728
+ /* TODO: ARMv8.3-NV */
729
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
730
+ break;
731
+ case ARMMMUIdx_E20_2:
732
+ case ARMMMUIdx_E20_2_PAN:
733
+ /*
734
+ * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
735
+ * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
736
+ */
737
+ if (env->cp15.hcr_el2 & HCR_TGE) {
738
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
739
+ }
740
+ break;
741
+ default:
742
+ break;
743
+ }
744
+ }
745
+
746
+ if (env->pstate & PSTATE_IL) {
747
+ DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
748
+ }
749
+
750
+ if (arm_fgt_active(env, el)) {
751
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
752
+ if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
753
+ DP_TBFLAG_A64(flags, FGT_ERET, 1);
754
+ }
755
+ if (fgt_svc(env, el)) {
756
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
757
+ }
758
+ }
759
+
760
+ if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
761
+ /*
762
+ * Set MTE_ACTIVE if any access may be Checked, and leave clear
763
+ * if all accesses must be Unchecked:
764
+ * 1) If no TBI, then there are no tags in the address to check,
765
+ * 2) If Tag Check Override, then all accesses are Unchecked,
766
+ * 3) If Tag Check Fail == 0, then Checked access have no effect,
767
+ * 4) If no Allocation Tag Access, then all accesses are Unchecked.
768
+ */
769
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
770
+ DP_TBFLAG_A64(flags, ATA, 1);
771
+ if (tbid
772
+ && !(env->pstate & PSTATE_TCO)
773
+ && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
774
+ DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
775
+ }
776
+ }
777
+ /* And again for unprivileged accesses, if required. */
778
+ if (EX_TBFLAG_A64(flags, UNPRIV)
779
+ && tbid
780
+ && !(env->pstate & PSTATE_TCO)
781
+ && (sctlr & SCTLR_TCF0)
782
+ && allocation_tag_access_enabled(env, 0, sctlr)) {
783
+ DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
784
+ }
785
+ /* Cache TCMA as well as TBI. */
786
+ DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
787
+ }
788
+
789
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
790
+}
791
+
792
+static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
793
+{
794
+ int el = arm_current_el(env);
795
+ int fp_el = fp_exception_el(env, el);
796
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
797
+
798
+ if (is_a64(env)) {
799
+ return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
800
+ } else if (arm_feature(env, ARM_FEATURE_M)) {
801
+ return rebuild_hflags_m32(env, fp_el, mmu_idx);
802
+ } else {
803
+ return rebuild_hflags_a32(env, fp_el, mmu_idx);
804
+ }
805
+}
806
+
807
+void arm_rebuild_hflags(CPUARMState *env)
808
+{
809
+ env->hflags = rebuild_hflags_internal(env);
810
+}
811
+
812
+/*
813
+ * If we have triggered a EL state change we can't rely on the
814
+ * translator having passed it to us, we need to recompute.
815
+ */
816
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
817
+{
818
+ int el = arm_current_el(env);
819
+ int fp_el = fp_exception_el(env, el);
820
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
821
+
822
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
823
+}
824
+
825
+void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
826
+{
827
+ int fp_el = fp_exception_el(env, el);
828
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
829
+
830
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
831
+}
832
+
833
+/*
834
+ * If we have triggered a EL state change we can't rely on the
835
+ * translator having passed it to us, we need to recompute.
836
+ */
837
+void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
838
+{
839
+ int el = arm_current_el(env);
840
+ int fp_el = fp_exception_el(env, el);
841
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
842
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
843
+}
844
+
845
+void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
846
+{
847
+ int fp_el = fp_exception_el(env, el);
848
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
849
+
850
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
851
+}
852
+
853
+void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
854
+{
855
+ int fp_el = fp_exception_el(env, el);
856
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
857
+
858
+ env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
859
+}
860
+
861
+void assert_hflags_rebuild_correctly(CPUARMState *env)
862
+{
863
+#ifdef CONFIG_DEBUG_TCG
864
+ CPUARMTBFlags c = env->hflags;
865
+ CPUARMTBFlags r = rebuild_hflags_internal(env);
866
+
867
+ if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
868
+ fprintf(stderr, "TCG hflags mismatch "
869
+ "(current:(0x%08x,0x" TARGET_FMT_lx ")"
870
+ " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
871
+ c.flags, c.flags2, r.flags, r.flags2);
872
+ abort();
873
+ }
874
+#endif
875
+}
876
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
877
index XXXXXXX..XXXXXXX 100644
878
--- a/target/arm/tcg/meson.build
879
+++ b/target/arm/tcg/meson.build
880
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
881
'translate-neon.c',
882
'translate-vfp.c',
883
'crypto_helper.c',
884
+ 'hflags.c',
885
'iwmmxt_helper.c',
886
'm_helper.c',
887
'mve_helper.c',
53
--
888
--
54
2.20.1
889
2.34.1
55
890
56
891
diff view generated by jsdifflib
New patch
[PULL 09/25] target/arm: Move regime_using_lpae_format into internal.h
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
This function is needed by common code (ptw.c), so move it along with
4
the other regime_* functions in internal.h. When we enable the build
5
without TCG, the tlb_helper.c file will not be present.
6
7
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 21 ++++++++++++++++++---
13
target/arm/tcg/tlb_helper.c | 18 ------------------
14
2 files changed, 18 insertions(+), 21 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
21
/* Return the MMU index for a v7M CPU in the specified security state */
22
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
23
24
-/* Return true if the translation regime is using LPAE format page tables */
25
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
26
-
27
/*
28
* Return true if the stage 1 translation regime is using LPAE
29
* format page tables
30
@@ -XXX,XX +XXX,XX @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
31
return env->cp15.tcr_el[regime_el(env, mmu_idx)];
32
}
33
34
+/* Return true if the translation regime is using LPAE format page tables */
35
+static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
36
+{
37
+ int el = regime_el(env, mmu_idx);
38
+ if (el == 2 || arm_el_is_aa64(env, el)) {
39
+ return true;
40
+ }
41
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
42
+ arm_feature(env, ARM_FEATURE_V8)) {
43
+ return true;
44
+ }
45
+ if (arm_feature(env, ARM_FEATURE_LPAE)
46
+ && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
47
+ return true;
48
+ }
49
+ return false;
50
+}
51
+
52
/**
53
* arm_num_brps: Return number of implemented breakpoints.
54
* Note that the ID register BRPS field is "number of bps - 1",
55
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/tcg/tlb_helper.c
58
+++ b/target/arm/tcg/tlb_helper.c
59
@@ -XXX,XX +XXX,XX @@
60
#include "exec/helper-proto.h"
61
62
63
-/* Return true if the translation regime is using LPAE format page tables */
64
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
65
-{
66
- int el = regime_el(env, mmu_idx);
67
- if (el == 2 || arm_el_is_aa64(env, el)) {
68
- return true;
69
- }
70
- if (arm_feature(env, ARM_FEATURE_PMSA) &&
71
- arm_feature(env, ARM_FEATURE_V8)) {
72
- return true;
73
- }
74
- if (arm_feature(env, ARM_FEATURE_LPAE)
75
- && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
76
- return true;
77
- }
78
- return false;
79
-}
80
-
81
/*
82
* Returns true if the stage 1 translation regime is using LPAE format page
83
* tables. Used when raising alignment exceptions, whose FSR changes depending
84
--
85
2.34.1
86
87
diff view generated by jsdifflib
New patch
[PULL 10/25] target/arm: Don't access TCG code when debugging with KVM
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
When TCG is disabled this part of the code should not be reachable, so
4
wrap it with an ifdef for now.
5
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 4 ++++
12
1 file changed, 4 insertions(+)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
19
ptw->out_host = NULL;
20
ptw->out_rw = false;
21
} else {
22
+#ifdef CONFIG_TCG
23
CPUTLBEntryFull *full;
24
int flags;
25
26
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
27
ptw->out_rw = full->prot & PAGE_WRITE;
28
pte_attrs = full->pte_attrs;
29
pte_secure = full->attrs.secure;
30
+#else
31
+ g_assert_not_reached();
32
+#endif
33
}
34
35
if (regime_is_stage2(s2_mmu_idx)) {
36
--
37
2.34.1
38
39
diff view generated by jsdifflib
New patch
[PULL 11/25] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
This struct has no dependencies on TCG code and it is being used in
4
target/arm/ptw.c to simplify the passing around of page table walk
5
results. Those routines can be reached by KVM code via the gdbstub
6
breakpoint code, so take the structure out of CONFIG_TCG to make it
7
visible when building with --disable-tcg.
8
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/exec/cpu-defs.h | 6 ++++++
16
1 file changed, 6 insertions(+)
17
18
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/exec/cpu-defs.h
21
+++ b/include/exec/cpu-defs.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry {
23
24
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
25
26
+
27
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
28
+
29
+#if !defined(CONFIG_USER_ONLY)
30
/*
31
* The full TLB entry, which is not accessed by generated TCG code,
32
* so the layout is not as critical as that of CPUTLBEntry. This is
33
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
34
TARGET_PAGE_ENTRY_EXTRA
35
#endif
36
} CPUTLBEntryFull;
37
+#endif /* !CONFIG_USER_ONLY */
38
39
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
40
/*
41
* Data elements that are per MMU mode, minus the bits accessed by
42
* the TCG fast path.
43
--
44
2.34.1
45
46
diff view generated by jsdifflib
New patch
[PULL 12/25] tests/avocado: add machine:none tag to version.py
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
This test currently fails when run on a host for which the QEMU target
4
has no default machine set:
5
6
ERROR| Output: qemu-system-aarch64: No machine specified, and there is
7
no default
8
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
tests/avocado/version.py | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/tests/avocado/version.py b/tests/avocado/version.py
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/avocado/version.py
19
+++ b/tests/avocado/version.py
20
@@ -XXX,XX +XXX,XX @@
21
class Version(QemuSystemTest):
22
"""
23
:avocado: tags=quick
24
+ :avocado: tags=machine:none
25
"""
26
def test_qmp_human_info_version(self):
27
self.vm.add_args('-nodefaults')
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
New patch
[PULL 13/25] hw/gpio/max7310: Simplify max7310_realize()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since &I2C_SLAVE(dev)->qdev == dev, no need to go back and
4
forth with QOM type casting. Directly use 'dev'.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230220115114.25237-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/gpio/max7310.c | 5 ++---
12
1 file changed, 2 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/gpio/max7310.c
17
+++ b/hw/gpio/max7310.c
18
@@ -XXX,XX +XXX,XX @@ static void max7310_gpio_set(void *opaque, int line, int level)
19
* but also accepts sequences that are not SMBus so return an I2C device. */
20
static void max7310_realize(DeviceState *dev, Error **errp)
21
{
22
- I2CSlave *i2c = I2C_SLAVE(dev);
23
MAX7310State *s = MAX7310(dev);
24
25
- qdev_init_gpio_in(&i2c->qdev, max7310_gpio_set, 8);
26
- qdev_init_gpio_out(&i2c->qdev, s->handler, 8);
27
+ qdev_init_gpio_in(dev, max7310_gpio_set, ARRAY_SIZE(s->handler));
28
+ qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler));
29
}
30
31
static void max7310_class_init(ObjectClass *klass, void *data)
32
--
33
2.34.1
34
35
diff view generated by jsdifflib
[PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements
[PULL 14/25] hw/char/pl011: Un-inline pl011_create()
1
From: Marc Zyngier <maz@kernel.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
3
pl011_create() is only used in DeviceRealize handlers,
4
registers traps to EL2, and QEMU has so far ignored this requirement.
4
not a hot-path. Inlining is not justified.
5
5
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
while the hypervisor doesn't want to expose the feature to its guest.
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
case), and masks out the unsupported feature.
9
Message-id: 20230220115114.25237-3-philmd@linaro.org
10
11
QEMU not honoring the trap request means that the guest observes
12
that the feature is present in the HW, starts using it, and dies
13
a horrible death when KVM injects an UNDEF, because the feature
14
*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
17
18
Note that this change does not include trapping of the MVFR
19
registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
23
Signed-off-by: Marc Zyngier <maz@kernel.org>
24
Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
26
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
11
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
12
include/hw/char/pl011.h | 19 +------------------
32
1 file changed, 76 insertions(+)
13
hw/char/pl011.c | 17 +++++++++++++++++
14
2 files changed, 18 insertions(+), 18 deletions(-)
33
15
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
35
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
18
--- a/include/hw/char/pl011.h
37
+++ b/target/arm/helper.c
19
+++ b/include/hw/char/pl011.h
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
20
@@ -XXX,XX +XXX,XX @@
39
REGINFO_SENTINEL
21
#ifndef HW_PL011_H
22
#define HW_PL011_H
23
24
-#include "hw/qdev-properties.h"
25
#include "hw/sysbus.h"
26
#include "chardev/char-fe.h"
27
-#include "qapi/error.h"
28
#include "qom/object.h"
29
30
#define TYPE_PL011 "pl011"
31
@@ -XXX,XX +XXX,XX @@ struct PL011State {
32
const unsigned char *id;
40
};
33
};
41
34
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
35
-static inline DeviceState *pl011_create(hwaddr addr,
43
+ bool isread)
36
- qemu_irq irq,
37
- Chardev *chr)
38
-{
39
- DeviceState *dev;
40
- SysBusDevice *s;
41
-
42
- dev = qdev_new("pl011");
43
- s = SYS_BUS_DEVICE(dev);
44
- qdev_prop_set_chr(dev, "chardev", chr);
45
- sysbus_realize_and_unref(s, &error_fatal);
46
- sysbus_mmio_map(s, 0, addr);
47
- sysbus_connect_irq(s, 0, irq);
48
-
49
- return dev;
50
-}
51
+DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
52
53
static inline DeviceState *pl011_luminary_create(hwaddr addr,
54
qemu_irq irq,
55
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/char/pl011.c
58
+++ b/hw/char/pl011.c
59
@@ -XXX,XX +XXX,XX @@
60
*/
61
62
#include "qemu/osdep.h"
63
+#include "qapi/error.h"
64
#include "hw/char/pl011.h"
65
#include "hw/irq.h"
66
#include "hw/sysbus.h"
67
#include "hw/qdev-clock.h"
68
+#include "hw/qdev-properties.h"
69
#include "hw/qdev-properties-system.h"
70
#include "migration/vmstate.h"
71
#include "chardev/char-fe.h"
72
@@ -XXX,XX +XXX,XX @@
73
#include "qemu/module.h"
74
#include "trace.h"
75
76
+DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
44
+{
77
+{
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
78
+ DeviceState *dev;
46
+ return CP_ACCESS_TRAP_EL2;
79
+ SysBusDevice *s;
47
+ }
48
+
80
+
49
+ return CP_ACCESS_OK;
81
+ dev = qdev_new("pl011");
82
+ s = SYS_BUS_DEVICE(dev);
83
+ qdev_prop_set_chr(dev, "chardev", chr);
84
+ sysbus_realize_and_unref(s, &error_fatal);
85
+ sysbus_mmio_map(s, 0, addr);
86
+ sysbus_connect_irq(s, 0, irq);
87
+
88
+ return dev;
50
+}
89
+}
51
+
90
+
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
91
#define PL011_INT_TX 0x20
53
+ bool isread)
92
#define PL011_INT_RX 0x10
54
+{
93
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ return access_aa64_tid3(env, ri, isread);
57
+ }
58
+
59
+ return CP_ACCESS_OK;
60
+}
61
+
62
void register_cp_regs_for_features(ARMCPU *cpu)
63
{
64
/* Register all the coprocessor registers based on feature bits */
65
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
68
.access = PL1_R, .type = ARM_CP_CONST,
69
+ .accessfn = access_aa32_tid3,
70
.resetvalue = cpu->id_pfr0 },
71
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
72
* the value of the GIC field until after we define these regs.
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
76
.access = PL1_R, .type = ARM_CP_NO_RAW,
77
+ .accessfn = access_aa32_tid3,
78
.readfn = id_pfr1_read,
79
.writefn = arm_cp_write_ignore },
80
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
81
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
82
.access = PL1_R, .type = ARM_CP_CONST,
83
+ .accessfn = access_aa32_tid3,
84
.resetvalue = cpu->id_dfr0 },
85
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
86
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
87
.access = PL1_R, .type = ARM_CP_CONST,
88
+ .accessfn = access_aa32_tid3,
89
.resetvalue = cpu->id_afr0 },
90
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
91
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
92
.access = PL1_R, .type = ARM_CP_CONST,
93
+ .accessfn = access_aa32_tid3,
94
.resetvalue = cpu->id_mmfr0 },
95
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
96
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
97
.access = PL1_R, .type = ARM_CP_CONST,
98
+ .accessfn = access_aa32_tid3,
99
.resetvalue = cpu->id_mmfr1 },
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
102
.access = PL1_R, .type = ARM_CP_CONST,
103
+ .accessfn = access_aa32_tid3,
104
.resetvalue = cpu->id_mmfr2 },
105
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
107
.access = PL1_R, .type = ARM_CP_CONST,
108
+ .accessfn = access_aa32_tid3,
109
.resetvalue = cpu->id_mmfr3 },
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
112
.access = PL1_R, .type = ARM_CP_CONST,
113
+ .accessfn = access_aa32_tid3,
114
.resetvalue = cpu->isar.id_isar0 },
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
117
.access = PL1_R, .type = ARM_CP_CONST,
118
+ .accessfn = access_aa32_tid3,
119
.resetvalue = cpu->isar.id_isar1 },
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
122
.access = PL1_R, .type = ARM_CP_CONST,
123
+ .accessfn = access_aa32_tid3,
124
.resetvalue = cpu->isar.id_isar2 },
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
127
.access = PL1_R, .type = ARM_CP_CONST,
128
+ .accessfn = access_aa32_tid3,
129
.resetvalue = cpu->isar.id_isar3 },
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
132
.access = PL1_R, .type = ARM_CP_CONST,
133
+ .accessfn = access_aa32_tid3,
134
.resetvalue = cpu->isar.id_isar4 },
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
137
.access = PL1_R, .type = ARM_CP_CONST,
138
+ .accessfn = access_aa32_tid3,
139
.resetvalue = cpu->isar.id_isar5 },
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
94
--
358
2.20.1
95
2.34.1
359
96
360
97
diff view generated by jsdifflib
New patch
[PULL 15/25] hw/char/pl011: Open-code pl011_luminary_create()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
pl011_luminary_create() is only used for the Stellaris board,
4
open-code it.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230220115114.25237-4-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/char/pl011.h | 17 -----------------
13
hw/arm/stellaris.c | 11 ++++++++---
14
2 files changed, 8 insertions(+), 20 deletions(-)
15
16
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/pl011.h
19
+++ b/include/hw/char/pl011.h
20
@@ -XXX,XX +XXX,XX @@ struct PL011State {
21
22
DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
23
24
-static inline DeviceState *pl011_luminary_create(hwaddr addr,
25
- qemu_irq irq,
26
- Chardev *chr)
27
-{
28
- DeviceState *dev;
29
- SysBusDevice *s;
30
-
31
- dev = qdev_new("pl011_luminary");
32
- s = SYS_BUS_DEVICE(dev);
33
- qdev_prop_set_chr(dev, "chardev", chr);
34
- sysbus_realize_and_unref(s, &error_fatal);
35
- sysbus_mmio_map(s, 0, addr);
36
- sysbus_connect_irq(s, 0, irq);
37
-
38
- return dev;
39
-}
40
-
41
#endif
42
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/stellaris.c
45
+++ b/hw/arm/stellaris.c
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
48
for (i = 0; i < 4; i++) {
49
if (board->dc2 & (1 << i)) {
50
- pl011_luminary_create(0x4000c000 + i * 0x1000,
51
- qdev_get_gpio_in(nvic, uart_irq[i]),
52
- serial_hd(i));
53
+ SysBusDevice *sbd;
54
+
55
+ dev = qdev_new("pl011_luminary");
56
+ sbd = SYS_BUS_DEVICE(dev);
57
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
58
+ sysbus_realize_and_unref(sbd, &error_fatal);
59
+ sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000);
60
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));
61
}
62
}
63
if (board->dc2 & (1 << 4)) {
64
--
65
2.34.1
66
67
diff view generated by jsdifflib
New patch
[PULL 16/25] hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230220115114.25237-5-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/char/xilinx_uartlite.h | 6 +++++-
10
hw/char/xilinx_uartlite.c | 4 +---
11
2 files changed, 6 insertions(+), 4 deletions(-)
12
13
diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/char/xilinx_uartlite.h
16
+++ b/include/hw/char/xilinx_uartlite.h
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/qdev-properties.h"
19
#include "hw/sysbus.h"
20
#include "qapi/error.h"
21
+#include "qom/object.h"
22
+
23
+#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
24
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
25
26
static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
27
qemu_irq irq,
28
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
29
DeviceState *dev;
30
SysBusDevice *s;
31
32
- dev = qdev_new("xlnx.xps-uartlite");
33
+ dev = qdev_new(TYPE_XILINX_UARTLITE);
34
s = SYS_BUS_DEVICE(dev);
35
qdev_prop_set_chr(dev, "chardev", chr);
36
sysbus_realize_and_unref(s, &error_fatal);
37
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/char/xilinx_uartlite.c
40
+++ b/hw/char/xilinx_uartlite.c
41
@@ -XXX,XX +XXX,XX @@
42
43
#include "qemu/osdep.h"
44
#include "qemu/log.h"
45
+#include "hw/char/xilinx_uartlite.h"
46
#include "hw/irq.h"
47
#include "hw/qdev-properties.h"
48
#include "hw/qdev-properties-system.h"
49
@@ -XXX,XX +XXX,XX @@
50
#define CONTROL_RST_RX 0x02
51
#define CONTROL_IE 0x10
52
53
-#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
54
-OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
55
-
56
struct XilinxUARTLite {
57
SysBusDevice parent_obj;
58
59
--
60
2.34.1
61
62
diff view generated by jsdifflib
New patch
[PULL 17/25] hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Open-code the single use of xilinx_uartlite_create().
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230220115114.25237-6-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/char/xilinx_uartlite.h | 20 --------------------
12
hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +++++--
13
2 files changed, 5 insertions(+), 22 deletions(-)
14
15
diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/char/xilinx_uartlite.h
18
+++ b/include/hw/char/xilinx_uartlite.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef XILINX_UARTLITE_H
21
#define XILINX_UARTLITE_H
22
23
-#include "hw/qdev-properties.h"
24
-#include "hw/sysbus.h"
25
-#include "qapi/error.h"
26
#include "qom/object.h"
27
28
#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
29
OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
30
31
-static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
32
- qemu_irq irq,
33
- Chardev *chr)
34
-{
35
- DeviceState *dev;
36
- SysBusDevice *s;
37
-
38
- dev = qdev_new(TYPE_XILINX_UARTLITE);
39
- s = SYS_BUS_DEVICE(dev);
40
- qdev_prop_set_chr(dev, "chardev", chr);
41
- sysbus_realize_and_unref(s, &error_fatal);
42
- sysbus_mmio_map(s, 0, addr);
43
- sysbus_connect_irq(s, 0, irq);
44
-
45
- return dev;
46
-}
47
-
48
#endif
49
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
52
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
53
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
54
irq[i] = qdev_get_gpio_in(dev, i);
55
}
56
57
- xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ],
58
- serial_hd(0));
59
+ dev = qdev_new(TYPE_XILINX_UARTLITE);
60
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
61
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
62
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
64
65
/* 2 timers at irq 2 @ 62 Mhz. */
66
dev = qdev_new("xlnx.xps-timer");
67
--
68
2.34.1
69
70
diff view generated by jsdifflib
[PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
[PULL 18/25] hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
According to the PushStack() pseudocode in the armv7m RM,
3
cmsdk_apb_uart_create() is only used twice in the same
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
4
file. Open-code it.
5
an FPU is present. Current implementation is doing it for
6
armv8, but not for armv7. This patch makes the existing
7
logic applicable to both code paths.
8
5
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230220115114.25237-7-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/m_helper.c | 7 +++----
11
include/hw/char/cmsdk-apb-uart.h | 34 --------------------------
14
1 file changed, 3 insertions(+), 4 deletions(-)
12
hw/arm/mps2.c | 41 +++++++++++++++++++++-----------
13
2 files changed, 27 insertions(+), 48 deletions(-)
15
14
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
15
diff --git a/include/hw/char/cmsdk-apb-uart.h b/include/hw/char/cmsdk-apb-uart.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
17
--- a/include/hw/char/cmsdk-apb-uart.h
19
+++ b/target/arm/m_helper.c
18
+++ b/include/hw/char/cmsdk-apb-uart.h
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
19
@@ -XXX,XX +XXX,XX @@
21
if (env->v7m.secure) {
20
#ifndef CMSDK_APB_UART_H
22
lr |= R_V7M_EXCRET_S_MASK;
21
#define CMSDK_APB_UART_H
22
23
-#include "hw/qdev-properties.h"
24
#include "hw/sysbus.h"
25
#include "chardev/char-fe.h"
26
-#include "qapi/error.h"
27
#include "qom/object.h"
28
29
#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
30
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBUART {
31
uint8_t rxbuf;
32
};
33
34
-/**
35
- * cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_UART
36
- * @addr: location in system memory to map registers
37
- * @chr: Chardev backend to connect UART to, or NULL if no backend
38
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
39
- */
40
-static inline DeviceState *cmsdk_apb_uart_create(hwaddr addr,
41
- qemu_irq txint,
42
- qemu_irq rxint,
43
- qemu_irq txovrint,
44
- qemu_irq rxovrint,
45
- qemu_irq uartint,
46
- Chardev *chr,
47
- uint32_t pclk_frq)
48
-{
49
- DeviceState *dev;
50
- SysBusDevice *s;
51
-
52
- dev = qdev_new(TYPE_CMSDK_APB_UART);
53
- s = SYS_BUS_DEVICE(dev);
54
- qdev_prop_set_chr(dev, "chardev", chr);
55
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
56
- sysbus_realize_and_unref(s, &error_fatal);
57
- sysbus_mmio_map(s, 0, addr);
58
- sysbus_connect_irq(s, 0, txint);
59
- sysbus_connect_irq(s, 1, rxint);
60
- sysbus_connect_irq(s, 2, txovrint);
61
- sysbus_connect_irq(s, 3, rxovrint);
62
- sysbus_connect_irq(s, 4, uartint);
63
- return dev;
64
-}
65
-
66
#endif
67
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/arm/mps2.c
70
+++ b/hw/arm/mps2.c
71
@@ -XXX,XX +XXX,XX @@
72
#include "hw/boards.h"
73
#include "exec/address-spaces.h"
74
#include "sysemu/sysemu.h"
75
+#include "hw/qdev-properties.h"
76
#include "hw/misc/unimp.h"
77
#include "hw/char/cmsdk-apb-uart.h"
78
#include "hw/timer/cmsdk-apb-timer.h"
79
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
80
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
81
82
for (i = 0; i < 5; i++) {
83
+ DeviceState *dev;
84
+ SysBusDevice *s;
85
+
86
static const hwaddr uartbase[] = {0x40004000, 0x40005000,
87
0x40006000, 0x40007000,
88
0x40009000};
89
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
90
rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
91
}
92
93
- cmsdk_apb_uart_create(uartbase[i],
94
- qdev_get_gpio_in(armv7m, uartirq[i] + 1),
95
- qdev_get_gpio_in(armv7m, uartirq[i]),
96
- txovrint, rxovrint,
97
- NULL,
98
- serial_hd(i), SYSCLK_FRQ);
99
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
100
+ s = SYS_BUS_DEVICE(dev);
101
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
102
+ qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
103
+ sysbus_realize_and_unref(s, &error_fatal);
104
+ sysbus_mmio_map(s, 0, uartbase[i]);
105
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1));
106
+ sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i]));
107
+ sysbus_connect_irq(s, 2, txovrint);
108
+ sysbus_connect_irq(s, 3, rxovrint);
23
}
109
}
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
110
break;
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
111
}
26
- }
112
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
27
} else {
113
0x4002c000, 0x4002d000,
28
lr = R_V7M_EXCRET_RES1_MASK |
114
0x4002e000};
29
R_V7M_EXCRET_S_MASK |
115
Object *txrx_orgate;
30
R_V7M_EXCRET_DCRS_MASK |
116
- DeviceState *txrx_orgate_dev;
31
- R_V7M_EXCRET_FTYPE_MASK |
117
+ DeviceState *txrx_orgate_dev, *dev;
32
R_V7M_EXCRET_ES_MASK;
118
+ SysBusDevice *s;
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
119
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
120
txrx_orgate = object_new(TYPE_OR_IRQ);
121
object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
122
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
123
txrx_orgate_dev = DEVICE(txrx_orgate);
124
qdev_connect_gpio_out(txrx_orgate_dev, 0,
125
qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
126
- cmsdk_apb_uart_create(uartbase[i],
127
- qdev_get_gpio_in(txrx_orgate_dev, 0),
128
- qdev_get_gpio_in(txrx_orgate_dev, 1),
129
- qdev_get_gpio_in(orgate_dev, i * 2),
130
- qdev_get_gpio_in(orgate_dev, i * 2 + 1),
131
- NULL,
132
- serial_hd(i), SYSCLK_FRQ);
133
+
134
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
135
+ s = SYS_BUS_DEVICE(dev);
136
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
137
+ qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
138
+ sysbus_realize_and_unref(s, &error_fatal);
139
+ sysbus_mmio_map(s, 0, uartbase[i]);
140
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0));
141
+ sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1));
142
+ sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
143
+ sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
35
}
144
}
36
}
145
break;
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
39
+ }
40
if (!arm_v7m_is_handler_mode(env)) {
41
lr |= R_V7M_EXCRET_MODE_MASK;
42
}
146
}
43
--
147
--
44
2.20.1
148
2.34.1
45
149
46
150
diff view generated by jsdifflib
New patch
[PULL 19/25] hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20230220115114.25237-8-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/timer/cmsdk-apb-timer.h | 1 -
9
1 file changed, 1 deletion(-)
10
11
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/timer/cmsdk-apb-timer.h
14
+++ b/include/hw/timer/cmsdk-apb-timer.h
15
@@ -XXX,XX +XXX,XX @@
16
#ifndef CMSDK_APB_TIMER_H
17
#define CMSDK_APB_TIMER_H
18
19
-#include "hw/qdev-properties.h"
20
#include "hw/sysbus.h"
21
#include "hw/ptimer.h"
22
#include "hw/clock.h"
23
--
24
2.34.1
25
26
diff view generated by jsdifflib
New patch
[PULL 20/25] hw/intc/armv7m_nvic: Use QOM cast CPU() macro
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Avoid accessing 'parent_obj' directly.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20230220115114.25237-9-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/intc/armv7m_nvic.c | 6 +++---
11
1 file changed, 3 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
16
+++ b/hw/intc/armv7m_nvic.c
17
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
18
* which saves having to have an extra argument is_terminal
19
* that we'd only use in one place.
20
*/
21
- cpu_abort(&s->cpu->parent_obj,
22
+ cpu_abort(CPU(s->cpu),
23
"Lockup: can't take terminal derived exception "
24
"(original exception priority %d)\n",
25
s->vectpending_prio);
26
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
27
* Lockup condition due to a guest bug. We don't model
28
* Lockup, so report via cpu_abort() instead.
29
*/
30
- cpu_abort(&s->cpu->parent_obj,
31
+ cpu_abort(CPU(s->cpu),
32
"Lockup: can't escalate %d to HardFault "
33
"(current priority %d)\n", irq, running);
34
}
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
36
* We want to escalate to HardFault but the context the
37
* FP state belongs to prevents the exception pre-empting.
38
*/
39
- cpu_abort(&s->cpu->parent_obj,
40
+ cpu_abort(CPU(s->cpu),
41
"Lockup: can't escalate to HardFault during "
42
"lazy FP register stacking\n");
43
}
44
--
45
2.34.1
46
47
diff view generated by jsdifflib
New patch
[PULL 21/25] hw/arm/musicpal: Remove unused dummy MemoryRegion
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
hw/arm/musicpal.c | 4 ----
8
1 file changed, 4 deletions(-)
9
10
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/musicpal.c
13
+++ b/hw/arm/musicpal.c
14
@@ -XXX,XX +XXX,XX @@ struct musicpal_key_state {
15
SysBusDevice parent_obj;
16
/*< public >*/
17
18
- MemoryRegion iomem;
19
uint32_t kbd_extended;
20
uint32_t pressed_keys;
21
qemu_irq out[8];
22
@@ -XXX,XX +XXX,XX @@ static void musicpal_key_init(Object *obj)
23
DeviceState *dev = DEVICE(sbd);
24
musicpal_key_state *s = MUSICPAL_KEY(dev);
25
26
- memory_region_init(&s->iomem, obj, "dummy", 0);
27
- sysbus_init_mmio(sbd, &s->iomem);
28
-
29
s->kbd_extended = 0;
30
s->pressed_keys = 0;
31
32
--
33
2.34.1
34
35
diff view generated by jsdifflib
New patch
[PULL 22/25] iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since commit be8d853766 ("iothread: add I/O thread object") we
4
never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(),
5
remove these definitions.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20230113200138.52869-2-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
iothread.c | 4 ----
14
1 file changed, 4 deletions(-)
15
16
diff --git a/iothread.c b/iothread.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/iothread.c
19
+++ b/iothread.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "qemu/rcu.h"
22
#include "qemu/main-loop.h"
23
24
-typedef ObjectClass IOThreadClass;
25
-
26
-DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD,
27
- TYPE_IOTHREAD)
28
29
#ifdef CONFIG_POSIX
30
/* Benchmark results from 2016 on NVMe SSD drives show max polling times around
31
--
32
2.34.1
33
34
diff view generated by jsdifflib
New patch
[PULL 23/25] hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
QOM *DECLARE* macros expect a typedef as first argument,
4
not a structure. Replace 'struct IRQState' by 'IRQState'
5
to avoid when modifying the macros:
6
7
../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a definition
8
DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
9
^
10
11
Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER.
12
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20230113200138.52869-3-philmd@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/core/irq.c | 9 ++++-----
20
1 file changed, 4 insertions(+), 5 deletions(-)
21
22
diff --git a/hw/core/irq.c b/hw/core/irq.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/core/irq.c
25
+++ b/hw/core/irq.c
26
@@ -XXX,XX +XXX,XX @@
27
#include "hw/irq.h"
28
#include "qom/object.h"
29
30
-DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
31
- TYPE_IRQ)
32
+OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ)
33
34
struct IRQState {
35
Object parent_obj;
36
@@ -XXX,XX +XXX,XX @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
37
38
qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
39
{
40
- struct IRQState *irq;
41
+ IRQState *irq;
42
43
irq = IRQ(object_new(TYPE_IRQ));
44
irq->handler = handler;
45
@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq)
46
47
static void qemu_notirq(void *opaque, int line, int level)
48
{
49
- struct IRQState *irq = opaque;
50
+ IRQState *irq = opaque;
51
52
irq->handler(irq->opaque, irq->n, !level);
53
}
54
@@ -XXX,XX +XXX,XX @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
55
static const TypeInfo irq_type_info = {
56
.name = TYPE_IRQ,
57
.parent = TYPE_OBJECT,
58
- .instance_size = sizeof(struct IRQState),
59
+ .instance_size = sizeof(IRQState),
60
};
61
62
static void irq_register_types(void)
63
--
64
2.34.1
65
66
diff view generated by jsdifflib
New patch
[PULL 24/25] hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Missed during automatic conversion from commit 8063396bf3
4
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20230113200138.52869-4-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/or-irq.h | 3 +--
13
1 file changed, 1 insertion(+), 2 deletions(-)
14
15
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/or-irq.h
18
+++ b/include/hw/or-irq.h
19
@@ -XXX,XX +XXX,XX @@
20
21
typedef struct OrIRQState qemu_or_irq;
22
23
-DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ,
24
- TYPE_OR_IRQ)
25
+OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ)
26
27
struct OrIRQState {
28
DeviceState parent_obj;
29
--
30
2.34.1
31
32
diff view generated by jsdifflib
[PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
[PULL 25/25] hw: Replace qemu_or_irq typedef by OrIRQState
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Add the CRP as unimplemented thus avoiding bus errors when
3
OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState
4
guests access these registers.
4
declaration for free. Besides, the QOM code style is to use
5
5
the structure name as typedef, and QEMU style is to use Camel
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Case, so rename qemu_or_irq as OrIRQState.
7
8
Mechanical change using:
9
10
$ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq)
11
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
15
Message-id: 20230113200138.52869-5-philmd@linaro.org
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
include/hw/arm/xlnx-versal.h | 3 +++
18
include/hw/arm/armsse.h | 6 +++---
13
hw/arm/xlnx-versal.c | 2 ++
19
include/hw/arm/bcm2835_peripherals.h | 2 +-
14
2 files changed, 5 insertions(+)
20
include/hw/arm/exynos4210.h | 4 ++--
15
21
include/hw/arm/stm32f205_soc.h | 2 +-
22
include/hw/arm/stm32f405_soc.h | 2 +-
23
include/hw/arm/xlnx-versal.h | 6 +++---
24
include/hw/arm/xlnx-zynqmp.h | 2 +-
25
include/hw/or-irq.h | 2 --
26
hw/arm/exynos4210.c | 4 ++--
27
hw/arm/mps2-tz.c | 2 +-
28
hw/core/or-irq.c | 18 +++++++++---------
29
hw/pci-host/raven.c | 2 +-
30
12 files changed, 25 insertions(+), 27 deletions(-)
31
32
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/armsse.h
35
+++ b/include/hw/arm/armsse.h
36
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
37
TZPPC apb_ppc[NUM_INTERNAL_PPCS];
38
TZMPC mpc[IOTS_NUM_MPC];
39
CMSDKAPBTimer timer[3];
40
- qemu_or_irq ppc_irq_orgate;
41
+ OrIRQState ppc_irq_orgate;
42
SplitIRQ sec_resp_splitter;
43
SplitIRQ ppc_irq_splitter[NUM_PPCS];
44
SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
45
- qemu_or_irq mpc_irq_orgate;
46
- qemu_or_irq nmi_orgate;
47
+ OrIRQState mpc_irq_orgate;
48
+ OrIRQState nmi_orgate;
49
50
SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS];
51
52
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/arm/bcm2835_peripherals.h
55
+++ b/include/hw/arm/bcm2835_peripherals.h
56
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
57
BCM2835AuxState aux;
58
BCM2835FBState fb;
59
BCM2835DMAState dma;
60
- qemu_or_irq orgated_dma_irq;
61
+ OrIRQState orgated_dma_irq;
62
BCM2835ICState ic;
63
BCM2835PropertyState property;
64
BCM2835RngState rng;
65
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/arm/exynos4210.h
68
+++ b/include/hw/arm/exynos4210.h
69
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
70
MemoryRegion boot_secondary;
71
MemoryRegion bootreg_mem;
72
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
73
- qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
74
- qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
75
+ OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA];
76
+ OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS];
77
A9MPPrivState a9mpcore;
78
Exynos4210GicState ext_gic;
79
Exynos4210CombinerState int_combiner;
80
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
81
index XXXXXXX..XXXXXXX 100644
82
--- a/include/hw/arm/stm32f205_soc.h
83
+++ b/include/hw/arm/stm32f205_soc.h
84
@@ -XXX,XX +XXX,XX @@ struct STM32F205State {
85
STM32F2XXADCState adc[STM_NUM_ADCS];
86
STM32F2XXSPIState spi[STM_NUM_SPIS];
87
88
- qemu_or_irq *adc_irqs;
89
+ OrIRQState *adc_irqs;
90
91
MemoryRegion sram;
92
MemoryRegion flash;
93
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
94
index XXXXXXX..XXXXXXX 100644
95
--- a/include/hw/arm/stm32f405_soc.h
96
+++ b/include/hw/arm/stm32f405_soc.h
97
@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
98
STM32F4xxExtiState exti;
99
STM32F2XXUsartState usart[STM_NUM_USARTS];
100
STM32F2XXTimerState timer[STM_NUM_TIMERS];
101
- qemu_or_irq adc_irqs;
102
+ OrIRQState adc_irqs;
103
STM32F2XXADCState adc[STM_NUM_ADCS];
104
STM32F2XXSPIState spi[STM_NUM_SPIS];
105
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
106
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
17
index XXXXXXX..XXXXXXX 100644
107
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
108
--- a/include/hw/arm/xlnx-versal.h
19
+++ b/include/hw/arm/xlnx-versal.h
109
+++ b/include/hw/arm/xlnx-versal.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
110
@@ -XXX,XX +XXX,XX @@ struct Versal {
21
#define MM_IOU_SCNTRS_SIZE 0x10000
111
} rpu;
22
#define MM_FPD_CRF 0xfd1a0000U
112
23
#define MM_FPD_CRF_SIZE 0x140000
113
struct {
24
+
114
- qemu_or_irq irq_orgate;
25
+#define MM_PMC_CRP 0xf1260000U
115
+ OrIRQState irq_orgate;
26
+#define MM_PMC_CRP_SIZE 0x10000
116
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
27
#endif
117
} xram;
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
118
29
index XXXXXXX..XXXXXXX 100644
119
@@ -XXX,XX +XXX,XX @@ struct Versal {
30
--- a/hw/arm/xlnx-versal.c
120
XlnxCSUDMA dma_src;
31
+++ b/hw/arm/xlnx-versal.c
121
XlnxCSUDMA dma_dst;
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
122
MemoryRegion linear_mr;
33
MM_CRL, MM_CRL_SIZE);
123
- qemu_or_irq irq_orgate;
34
versal_unimp_area(s, "crf", &s->mr_ps,
124
+ OrIRQState irq_orgate;
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
125
} ospi;
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
126
} iou;
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
127
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
128
@@ -XXX,XX +XXX,XX @@ struct Versal {
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
129
XlnxVersalEFuseCtrl efuse_ctrl;
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
130
XlnxVersalEFuseCache efuse_cache;
131
132
- qemu_or_irq apb_irq_orgate;
133
+ OrIRQState apb_irq_orgate;
134
} pmc;
135
136
struct {
137
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/xlnx-zynqmp.h
140
+++ b/include/hw/arm/xlnx-zynqmp.h
141
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
142
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
143
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
144
XlnxCSUDMA qspi_dma;
145
- qemu_or_irq qspi_irq_orgate;
146
+ OrIRQState qspi_irq_orgate;
147
XlnxZynqMPAPUCtrl apu_ctrl;
148
XlnxZynqMPCRF crf;
149
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
150
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/or-irq.h
153
+++ b/include/hw/or-irq.h
154
@@ -XXX,XX +XXX,XX @@
155
*/
156
#define MAX_OR_LINES 48
157
158
-typedef struct OrIRQState qemu_or_irq;
159
-
160
OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ)
161
162
struct OrIRQState {
163
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/arm/exynos4210.c
166
+++ b/hw/arm/exynos4210.c
167
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
168
return (0x9 << ARM_AFF1_SHIFT) | cpu;
169
}
170
171
-static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
172
+static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate,
173
qemu_irq irq, int nreq, int nevents, int width)
174
{
175
SysBusDevice *busdev;
176
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
177
178
for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
179
char *name = g_strdup_printf("pl330-irq-orgate%d", i);
180
- qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
181
+ OrIRQState *orgate = &s->pl330_irq_orgate[i];
182
183
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
184
g_free(name);
185
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/mps2-tz.c
188
+++ b/hw/arm/mps2-tz.c
189
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
190
TZMSC msc[4];
191
CMSDKAPBUART uart[6];
192
SplitIRQ sec_resp_splitter;
193
- qemu_or_irq uart_irq_orgate;
194
+ OrIRQState uart_irq_orgate;
195
DeviceState *lan9118;
196
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
197
Clock *sysclk;
198
diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
199
index XXXXXXX..XXXXXXX 100644
200
--- a/hw/core/or-irq.c
201
+++ b/hw/core/or-irq.c
202
@@ -XXX,XX +XXX,XX @@
203
204
static void or_irq_handler(void *opaque, int n, int level)
205
{
206
- qemu_or_irq *s = OR_IRQ(opaque);
207
+ OrIRQState *s = OR_IRQ(opaque);
208
int or_level = 0;
209
int i;
210
211
@@ -XXX,XX +XXX,XX @@ static void or_irq_handler(void *opaque, int n, int level)
212
213
static void or_irq_reset(DeviceState *dev)
214
{
215
- qemu_or_irq *s = OR_IRQ(dev);
216
+ OrIRQState *s = OR_IRQ(dev);
217
int i;
218
219
for (i = 0; i < MAX_OR_LINES; i++) {
220
@@ -XXX,XX +XXX,XX @@ static void or_irq_reset(DeviceState *dev)
221
222
static void or_irq_realize(DeviceState *dev, Error **errp)
223
{
224
- qemu_or_irq *s = OR_IRQ(dev);
225
+ OrIRQState *s = OR_IRQ(dev);
226
227
assert(s->num_lines <= MAX_OR_LINES);
228
229
@@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp)
230
231
static void or_irq_init(Object *obj)
232
{
233
- qemu_or_irq *s = OR_IRQ(obj);
234
+ OrIRQState *s = OR_IRQ(obj);
235
236
qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1);
237
}
238
@@ -XXX,XX +XXX,XX @@ static void or_irq_init(Object *obj)
239
240
static bool vmstate_extras_needed(void *opaque)
241
{
242
- qemu_or_irq *s = OR_IRQ(opaque);
243
+ OrIRQState *s = OR_IRQ(opaque);
244
245
return s->num_lines >= OLD_MAX_OR_LINES;
246
}
247
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq_extras = {
248
.minimum_version_id = 1,
249
.needed = vmstate_extras_needed,
250
.fields = (VMStateField[]) {
251
- VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0,
252
+ VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
253
vmstate_info_bool, bool),
254
VMSTATE_END_OF_LIST(),
255
},
256
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = {
257
.version_id = 1,
258
.minimum_version_id = 1,
259
.fields = (VMStateField[]) {
260
- VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES),
261
+ VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
262
VMSTATE_END_OF_LIST(),
263
},
264
.subsections = (const VMStateDescription*[]) {
265
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = {
266
};
267
268
static Property or_irq_properties[] = {
269
- DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1),
270
+ DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1),
271
DEFINE_PROP_END_OF_LIST(),
272
};
273
274
@@ -XXX,XX +XXX,XX @@ static void or_irq_class_init(ObjectClass *klass, void *data)
275
static const TypeInfo or_irq_type_info = {
276
.name = TYPE_OR_IRQ,
277
.parent = TYPE_DEVICE,
278
- .instance_size = sizeof(qemu_or_irq),
279
+ .instance_size = sizeof(OrIRQState),
280
.instance_init = or_irq_init,
281
.class_init = or_irq_class_init,
282
};
283
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/pci-host/raven.c
286
+++ b/hw/pci-host/raven.c
287
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
288
struct PRePPCIState {
289
PCIHostState parent_obj;
290
291
- qemu_or_irq *or_irq;
292
+ OrIRQState *or_irq;
293
qemu_irq pci_irqs[PCI_NUM_PINS];
294
PCIBus pci_bus;
295
AddressSpace pci_io_as;
41
--
296
--
42
2.20.1
297
2.34.1
43
298
44
299
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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