[PULL 0/4] target-arm queue
[PULL 00/39] target-arm queue
1
Arm patches for rc3 : just a handful of bug fixes.
1
Hi; this pullreq contains mainly a chunk of RTH's refactoring
2
of the Arm pagetable walk code, plus a series from me fixing
3
configure checkpatch warnings, and some old patches to various
4
files all over the tree getting rid of dynamic stack allocation.
2
5
3
thanks
6
thanks
4
-- PMM
7
-- PMM
5
8
9
The following changes since commit 6338c30111d596d955e6bc933a82184a0b910c43:
6
10
7
The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c:
11
Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-09-21 13:12:36 -0400)
8
9
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000)
10
12
11
are available in the Git repository at:
13
are available in the Git repository at:
12
14
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220922
14
16
15
for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317:
17
for you to fetch changes up to b3b5472db0ab7a53499441c1fe1dedec05b1e285:
16
18
17
target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000)
19
configure: Avoid use of 'local' as it is non-POSIX (2022-09-22 16:38:29 +0100)
18
20
19
----------------------------------------------------------------
21
----------------------------------------------------------------
20
target-arm queue:
22
target-arm queue:
21
* handle FTYPE flag correctly in v7M exception return
23
* hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
22
for v7M CPUs with an FPU (v8M CPUs were already correct)
24
* Fix alignment for Neon VLD4.32
23
* versal: Add the CRP as unimplemented
25
* Refactoring of page-table-walk code
24
* Fix ISR_EL1 tracking when executing at EL2
26
* hw/acpi: Add ospm_status hook implementation for acpi-ged
25
* Honor HCR_EL2.TID3 trapping requirements
27
* hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
28
* chardev/baum: avoid variable-length arrays
29
* io/channel-websock: avoid variable-length arrays
30
* hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
31
* hw/ppc/pnv: Avoid dynamic stack allocation
32
* hw/intc/xics: Avoid dynamic stack allocation
33
* hw/i386/multiboot: Avoid dynamic stack allocation
34
* hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
35
* ui/curses: Avoid dynamic stack allocation
36
* tests/unit/test-vmstate: Avoid dynamic stack allocation
37
* configure: fix various shellcheck-spotted issues and nits
26
38
27
----------------------------------------------------------------
39
----------------------------------------------------------------
28
Edgar E. Iglesias (1):
40
Anton Kochkov (1):
29
hw/arm: versal: Add the CRP as unimplemented
41
hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
30
42
31
Jean-Hugues Deschênes (1):
43
Clément Chigot (1):
32
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
44
target/arm: Fix alignment for VLD4.32
33
45
34
Marc Zyngier (2):
46
Keqian Zhu (1):
35
target/arm: Fix ISR_EL1 tracking when executing at EL2
47
hw/acpi: Add ospm_status hook implementation for acpi-ged
36
target/arm: Honor HCR_EL2.TID3 trapping requirements
37
48
38
include/hw/arm/xlnx-versal.h | 3 ++
49
Lucas Dietrich (1):
39
hw/arm/xlnx-versal.c | 2 ++
50
hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
40
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++--
41
target/arm/m_helper.c | 7 ++--
42
4 files changed, 89 insertions(+), 6 deletions(-)
43
51
52
Peter Maydell (7):
53
configure: Remove unused python_version variable
54
configure: Remove unused meson_args variable
55
configure: Add missing quoting for some easy cases
56
configure: Add './' on front of glob of */config-devices.mak.d
57
configure: Remove use of backtick `...` syntax
58
configure: Check mkdir result directly, not via $?
59
configure: Avoid use of 'local' as it is non-POSIX
60
61
Philippe Mathieu-Daudé (11):
62
chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
63
chardev/baum: Use definitions to avoid dynamic stack allocation
64
chardev/baum: Avoid dynamic stack allocation
65
io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
66
hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
67
hw/ppc/pnv: Avoid dynamic stack allocation
68
hw/intc/xics: Avoid dynamic stack allocation
69
hw/i386/multiboot: Avoid dynamic stack allocation
70
hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
71
ui/curses: Avoid dynamic stack allocation
72
tests/unit/test-vmstate: Avoid dynamic stack allocation
73
74
Richard Henderson (17):
75
target/arm: Create GetPhysAddrResult
76
target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
77
target/arm: Use GetPhysAddrResult in get_phys_addr_v6
78
target/arm: Use GetPhysAddrResult in get_phys_addr_v5
79
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
80
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
81
target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
82
target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
83
target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
84
target/arm: Add is_secure parameter to v8m_security_lookup
85
target/arm: Add secure parameter to pmsav8_mpu_lookup
86
target/arm: Add is_secure parameter to get_phys_addr_v5
87
target/arm: Add is_secure parameter to get_phys_addr_v6
88
target/arm: Add secure parameter to get_phys_addr_pmsav8
89
target/arm: Add is_secure parameter to pmsav7_use_background_region
90
target/arm: Add secure parameter to get_phys_addr_pmsav7
91
target/arm: Add is_secure parameter to get_phys_addr_pmsav5
92
93
configure | 82 +++++-----
94
target/arm/internals.h | 26 +--
95
chardev/baum.c | 22 ++-
96
hw/acpi/generic_event_device.c | 8 +
97
hw/i386/multiboot.c | 5 +-
98
hw/intc/xics.c | 2 +-
99
hw/net/can/xlnx-zynqmp-can.c | 32 ++--
100
hw/net/e1000e_core.c | 7 +-
101
hw/net/lan9118.c | 8 +
102
hw/ppc/pnv.c | 4 +-
103
hw/ppc/spapr.c | 8 +-
104
hw/ppc/spapr_pci_nvlink2.c | 2 +-
105
hw/usb/hcd-ohci.c | 7 +-
106
io/channel-websock.c | 2 +-
107
target/arm/helper.c | 27 ++-
108
target/arm/m_helper.c | 78 ++++-----
109
target/arm/ptw.c | 364 +++++++++++++++++++----------------------
110
target/arm/tlb_helper.c | 22 +--
111
target/arm/translate-neon.c | 6 +-
112
tests/unit/test-vmstate.c | 7 +-
113
ui/curses.c | 2 +-
114
21 files changed, 347 insertions(+), 374 deletions(-)
115
diff view generated by jsdifflib
New patch
[PULL 01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
1
From: Anton Kochkov <anton.kochkov@proton.me>
1
2
3
For consistency, function "update_rx_fifo()" should use the RX FIFO
4
register field names, not the TX FIFO ones, even if they refer to the
5
same bit positions in the register.
6
7
Signed-off-by: Anton Kochkov <anton.kochkov@proton.me>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Message-id: 20220817141754.2105981-1-anton.kochkov@proton.me
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123
11
[PMM: tweaked commit message]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/net/can/xlnx-zynqmp-can.c | 32 ++++++++++++++++----------------
15
1 file changed, 16 insertions(+), 16 deletions(-)
16
17
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/net/can/xlnx-zynqmp-can.c
20
+++ b/hw/net/can/xlnx-zynqmp-can.c
21
@@ -XXX,XX +XXX,XX @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
22
timestamp));
23
24
/* First 32 bit of the data. */
25
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
26
- R_TXFIFO_DATA1_DB3_LENGTH,
27
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT,
28
+ R_RXFIFO_DATA1_DB3_LENGTH,
29
frame->data[0]) |
30
- deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
31
- R_TXFIFO_DATA1_DB2_LENGTH,
32
+ deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT,
33
+ R_RXFIFO_DATA1_DB2_LENGTH,
34
frame->data[1]) |
35
- deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
36
- R_TXFIFO_DATA1_DB1_LENGTH,
37
+ deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT,
38
+ R_RXFIFO_DATA1_DB1_LENGTH,
39
frame->data[2]) |
40
- deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
41
- R_TXFIFO_DATA1_DB0_LENGTH,
42
+ deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT,
43
+ R_RXFIFO_DATA1_DB0_LENGTH,
44
frame->data[3]));
45
/* Last 32 bit of the data. */
46
- fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
47
- R_TXFIFO_DATA2_DB7_LENGTH,
48
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT,
49
+ R_RXFIFO_DATA2_DB7_LENGTH,
50
frame->data[4]) |
51
- deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
52
- R_TXFIFO_DATA2_DB6_LENGTH,
53
+ deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT,
54
+ R_RXFIFO_DATA2_DB6_LENGTH,
55
frame->data[5]) |
56
- deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
57
- R_TXFIFO_DATA2_DB5_LENGTH,
58
+ deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT,
59
+ R_RXFIFO_DATA2_DB5_LENGTH,
60
frame->data[6]) |
61
- deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
62
- R_TXFIFO_DATA2_DB4_LENGTH,
63
+ deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT,
64
+ R_RXFIFO_DATA2_DB4_LENGTH,
65
frame->data[7]));
66
67
ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
68
--
69
2.25.1
diff view generated by jsdifflib
New patch
[PULL 02/39] target/arm: Fix alignment for VLD4.32
1
From: Clément Chigot <chigot@adacore.com>
1
2
3
When requested, the alignment for VLD4.32 is 8 and not 16.
4
5
See ARM documentation about VLD4 encoding:
6
ebytes = 1 << UInt(size);
7
if size == '10' then
8
alignment = if a == '0' then 1 else 8;
9
else
10
alignment = if a == '0' then 1 else 4*ebytes;
11
12
Signed-off-by: Clément Chigot <chigot@adacore.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220914105058.2787404-1-chigot@adacore.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/translate-neon.c | 6 +++++-
18
1 file changed, 5 insertions(+), 1 deletion(-)
19
20
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-neon.c
23
+++ b/target/arm/translate-neon.c
24
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
25
case 3:
26
return false;
27
case 4:
28
- align = pow2_align(size + 2);
29
+ if (size == 2) {
30
+ align = pow2_align(3);
31
+ } else {
32
+ align = pow2_align(size + 2);
33
+ }
34
break;
35
default:
36
g_assert_not_reached();
37
--
38
2.25.1
39
40
diff view generated by jsdifflib
[PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements
[PULL 03/39] target/arm: Create GetPhysAddrResult
1
From: Marc Zyngier <maz@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
3
Combine 5 output pointer arguments from get_phys_addr
4
registers traps to EL2, and QEMU has so far ignored this requirement.
4
into a single struct. Adjust all callers.
5
5
6
This breaks (among other things) KVM guests that have PtrAuth enabled,
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
while the hypervisor doesn't want to expose the feature to its guest.
7
Message-id: 20220822152741.1617527-2-richard.henderson@linaro.org
8
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
9
case), and masks out the unsupported feature.
10
11
QEMU not honoring the trap request means that the guest observes
12
that the feature is present in the HW, starts using it, and dies
13
a horrible death when KVM injects an UNDEF, because the feature
14
*really* isn't supported.
15
16
Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.
17
18
Note that this change does not include trapping of the MVFR
19
registers from AArch32 (they are accessed via the VMRS
20
instruction and need to be handled in a different way).
21
22
Reported-by: Will Deacon <will@kernel.org>
23
Signed-off-by: Marc Zyngier <maz@kernel.org>
24
Tested-by: Will Deacon <will@kernel.org>
25
Message-id: 20191123115618.29230-1-maz@kernel.org
26
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
27
changed names of access functions to include _tid3]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
10
---
31
target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
11
target/arm/internals.h | 13 ++++-
32
1 file changed, 76 insertions(+)
12
target/arm/helper.c | 27 ++++-----
13
target/arm/m_helper.c | 52 ++++++-----------
14
target/arm/ptw.c | 120 +++++++++++++++++++++-------------------
15
target/arm/tlb_helper.c | 22 +++-----
16
5 files changed, 109 insertions(+), 125 deletions(-)
33
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
21
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
23
bool is_s2_format:1;
24
} ARMCacheAttrs;
25
26
+/* Fields that are valid upon success. */
27
+typedef struct GetPhysAddrResult {
28
+ hwaddr phys;
29
+ target_ulong page_size;
30
+ int prot;
31
+ MemTxAttrs attrs;
32
+ ARMCacheAttrs cacheattrs;
33
+} GetPhysAddrResult;
34
+
35
bool get_phys_addr(CPUARMState *env, target_ulong address,
36
MMUAccessType access_type, ARMMMUIdx mmu_idx,
37
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
38
- target_ulong *page_size,
39
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
40
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
41
__attribute__((nonnull));
42
43
void arm_log_exception(CPUState *cs);
34
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
35
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/helper.c
46
--- a/target/arm/helper.c
37
+++ b/target/arm/helper.c
47
+++ b/target/arm/helper.c
38
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = {
48
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
39
REGINFO_SENTINEL
49
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
40
};
50
MMUAccessType access_type, ARMMMUIdx mmu_idx)
41
51
{
42
+static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
52
- hwaddr phys_addr;
43
+ bool isread)
53
- target_ulong page_size;
44
+{
54
- int prot;
45
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
55
bool ret;
46
+ return CP_ACCESS_TRAP_EL2;
56
uint64_t par64;
47
+ }
57
bool format64 = false;
58
- MemTxAttrs attrs = {};
59
ARMMMUFaultInfo fi = {};
60
- ARMCacheAttrs cacheattrs = {};
61
+ GetPhysAddrResult res = {};
62
63
- ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
64
- &prot, &page_size, &fi, &cacheattrs);
65
+ ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
66
67
/*
68
* ATS operations only do S1 or S1+S2 translations, so we never
69
* have to deal with the ARMCacheAttrs format for S2 only.
70
*/
71
- assert(!cacheattrs.is_s2_format);
72
+ assert(!res.cacheattrs.is_s2_format);
73
74
if (ret) {
75
/*
76
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
77
/* Create a 64-bit PAR */
78
par64 = (1 << 11); /* LPAE bit always set */
79
if (!ret) {
80
- par64 |= phys_addr & ~0xfffULL;
81
- if (!attrs.secure) {
82
+ par64 |= res.phys & ~0xfffULL;
83
+ if (!res.attrs.secure) {
84
par64 |= (1 << 9); /* NS */
85
}
86
- par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
87
- par64 |= cacheattrs.shareability << 7; /* SH */
88
+ par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
89
+ par64 |= res.cacheattrs.shareability << 7; /* SH */
90
} else {
91
uint32_t fsr = arm_fi_to_lfsc(&fi);
92
93
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
94
*/
95
if (!ret) {
96
/* We do not set any attribute bits in the PAR */
97
- if (page_size == (1 << 24)
98
+ if (res.page_size == (1 << 24)
99
&& arm_feature(env, ARM_FEATURE_V7)) {
100
- par64 = (phys_addr & 0xff000000) | (1 << 1);
101
+ par64 = (res.phys & 0xff000000) | (1 << 1);
102
} else {
103
- par64 = phys_addr & 0xfffff000;
104
+ par64 = res.phys & 0xfffff000;
105
}
106
- if (!attrs.secure) {
107
+ if (!res.attrs.secure) {
108
par64 |= (1 << 9); /* NS */
109
}
110
} else {
111
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/m_helper.c
114
+++ b/target/arm/m_helper.c
115
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
116
{
117
CPUState *cs = CPU(cpu);
118
CPUARMState *env = &cpu->env;
119
- MemTxAttrs attrs = {};
120
MemTxResult txres;
121
- target_ulong page_size;
122
- hwaddr physaddr;
123
- int prot;
124
+ GetPhysAddrResult res = {};
125
ARMMMUFaultInfo fi = {};
126
- ARMCacheAttrs cacheattrs = {};
127
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
128
int exc;
129
bool exc_secure;
130
131
- if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr,
132
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
133
+ if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) {
134
/* MPU/SAU lookup failed */
135
if (fi.type == ARMFault_QEMU_SFault) {
136
if (mode == STACK_LAZYFP) {
137
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
138
}
139
goto pend_fault;
140
}
141
- address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value,
142
- attrs, &txres);
143
+ address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
144
+ res.attrs, &txres);
145
if (txres != MEMTX_OK) {
146
/* BusFault trying to write the data */
147
if (mode == STACK_LAZYFP) {
148
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
149
{
150
CPUState *cs = CPU(cpu);
151
CPUARMState *env = &cpu->env;
152
- MemTxAttrs attrs = {};
153
MemTxResult txres;
154
- target_ulong page_size;
155
- hwaddr physaddr;
156
- int prot;
157
+ GetPhysAddrResult res = {};
158
ARMMMUFaultInfo fi = {};
159
- ARMCacheAttrs cacheattrs = {};
160
bool secure = mmu_idx & ARM_MMU_IDX_M_S;
161
int exc;
162
bool exc_secure;
163
uint32_t value;
164
165
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
166
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
167
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
168
/* MPU/SAU lookup failed */
169
if (fi.type == ARMFault_QEMU_SFault) {
170
qemu_log_mask(CPU_LOG_INT,
171
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
172
goto pend_fault;
173
}
174
175
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
176
- attrs, &txres);
177
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
178
+ res.attrs, &txres);
179
if (txres != MEMTX_OK) {
180
/* BusFault trying to read the data */
181
qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
182
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
183
CPUState *cs = CPU(cpu);
184
CPUARMState *env = &cpu->env;
185
V8M_SAttributes sattrs = {};
186
- MemTxAttrs attrs = {};
187
+ GetPhysAddrResult res = {};
188
ARMMMUFaultInfo fi = {};
189
- ARMCacheAttrs cacheattrs = {};
190
MemTxResult txres;
191
- target_ulong page_size;
192
- hwaddr physaddr;
193
- int prot;
194
195
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
196
if (!sattrs.nsc || sattrs.ns) {
197
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
198
"...really SecureFault with SFSR.INVEP\n");
199
return false;
200
}
201
- if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr,
202
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
203
+ if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) {
204
/* the MPU lookup failed */
205
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
206
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
207
qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
208
return false;
209
}
210
- *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr,
211
- attrs, &txres);
212
+ *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
213
+ res.attrs, &txres);
214
if (txres != MEMTX_OK) {
215
env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
216
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
217
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
218
*/
219
CPUState *cs = CPU(cpu);
220
CPUARMState *env = &cpu->env;
221
- MemTxAttrs attrs = {};
222
MemTxResult txres;
223
- target_ulong page_size;
224
- hwaddr physaddr;
225
- int prot;
226
+ GetPhysAddrResult res = {};
227
ARMMMUFaultInfo fi = {};
228
- ARMCacheAttrs cacheattrs = {};
229
uint32_t value;
230
231
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
232
- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
233
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) {
234
/* MPU/SAU lookup failed */
235
if (fi.type == ARMFault_QEMU_SFault) {
236
qemu_log_mask(CPU_LOG_INT,
237
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
238
}
239
return false;
240
}
241
- value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
242
- attrs, &txres);
243
+ value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
244
+ res.attrs, &txres);
245
if (txres != MEMTX_OK) {
246
/* BusFault trying to read the data */
247
qemu_log_mask(CPU_LOG_INT,
248
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
249
index XXXXXXX..XXXXXXX 100644
250
--- a/target/arm/ptw.c
251
+++ b/target/arm/ptw.c
252
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
253
* @address: virtual address to get physical address for
254
* @access_type: 0 for read, 1 for write, 2 for execute
255
* @mmu_idx: MMU index indicating required translation regime
256
- * @phys_ptr: set to the physical address corresponding to the virtual address
257
- * @attrs: set to the memory transaction attributes to use
258
- * @prot: set to the permissions for the page containing phys_ptr
259
- * @page_size: set to the size of the page containing phys_ptr
260
+ * @result: set on translation success.
261
* @fi: set to fault info if the translation fails
262
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
263
*/
264
bool get_phys_addr(CPUARMState *env, target_ulong address,
265
MMUAccessType access_type, ARMMMUIdx mmu_idx,
266
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
267
- target_ulong *page_size,
268
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
269
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
270
{
271
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
272
273
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
274
*/
275
if (arm_feature(env, ARM_FEATURE_EL2)) {
276
hwaddr ipa;
277
- int s2_prot;
278
+ int s1_prot;
279
int ret;
280
bool ipa_secure;
281
- ARMCacheAttrs cacheattrs2 = {};
282
+ ARMCacheAttrs cacheattrs1;
283
ARMMMUIdx s2_mmu_idx;
284
bool is_el0;
285
286
- ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
287
- attrs, prot, page_size, fi, cacheattrs);
288
+ ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
289
+ result, fi);
290
291
/* If S1 fails or S2 is disabled, return early. */
292
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
293
- *phys_ptr = ipa;
294
return ret;
295
}
296
297
- ipa_secure = attrs->secure;
298
+ ipa = result->phys;
299
+ ipa_secure = result->attrs.secure;
300
if (arm_is_secure_below_el3(env)) {
301
if (ipa_secure) {
302
- attrs->secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
303
+ result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
304
} else {
305
- attrs->secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
306
+ result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
307
}
308
} else {
309
assert(!ipa_secure);
310
}
311
312
- s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
313
+ s2_mmu_idx = (result->attrs.secure
314
+ ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
315
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
316
317
- /* S1 is done. Now do S2 translation. */
318
+ /*
319
+ * S1 is done, now do S2 translation.
320
+ * Save the stage1 results so that we may merge
321
+ * prot and cacheattrs later.
322
+ */
323
+ s1_prot = result->prot;
324
+ cacheattrs1 = result->cacheattrs;
325
+ memset(result, 0, sizeof(*result));
48
+
326
+
49
+ return CP_ACCESS_OK;
327
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
50
+}
328
- phys_ptr, attrs, &s2_prot,
329
- page_size, fi, &cacheattrs2);
330
+ &result->phys, &result->attrs,
331
+ &result->prot, &result->page_size,
332
+ fi, &result->cacheattrs);
333
fi->s2addr = ipa;
51
+
334
+
52
+static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
335
/* Combine the S1 and S2 perms. */
53
+ bool isread)
336
- *prot &= s2_prot;
54
+{
337
+ result->prot &= s1_prot;
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
338
56
+ return access_aa64_tid3(env, ri, isread);
339
/* If S2 fails, return early. */
57
+ }
340
if (ret) {
58
+
341
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
59
+ return CP_ACCESS_OK;
342
* Outer Write-Back Read-Allocate Write-Allocate.
60
+}
343
* Do not overwrite Tagged within attrs.
61
+
344
*/
62
void register_cp_regs_for_features(ARMCPU *cpu)
345
- if (cacheattrs->attrs != 0xf0) {
346
- cacheattrs->attrs = 0xff;
347
+ if (cacheattrs1.attrs != 0xf0) {
348
+ cacheattrs1.attrs = 0xff;
349
}
350
- cacheattrs->shareability = 0;
351
+ cacheattrs1.shareability = 0;
352
}
353
- *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2);
354
+ result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
355
+ result->cacheattrs);
356
357
/* Check if IPA translates to secure or non-secure PA space. */
358
if (arm_is_secure_below_el3(env)) {
359
if (ipa_secure) {
360
- attrs->secure =
361
+ result->attrs.secure =
362
!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
363
} else {
364
- attrs->secure =
365
+ result->attrs.secure =
366
!((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
367
|| (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
368
}
369
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
370
* cannot upgrade an non-secure translation regime's attributes
371
* to secure.
372
*/
373
- attrs->secure = regime_is_secure(env, mmu_idx);
374
- attrs->user = regime_is_user(env, mmu_idx);
375
+ result->attrs.secure = regime_is_secure(env, mmu_idx);
376
+ result->attrs.user = regime_is_user(env, mmu_idx);
377
378
/*
379
* Fast Context Switch Extension. This doesn't exist at all in v8.
380
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
381
382
if (arm_feature(env, ARM_FEATURE_PMSA)) {
383
bool ret;
384
- *page_size = TARGET_PAGE_SIZE;
385
+ result->page_size = TARGET_PAGE_SIZE;
386
387
if (arm_feature(env, ARM_FEATURE_V8)) {
388
/* PMSAv8 */
389
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
390
- phys_ptr, attrs, prot, page_size, fi);
391
+ &result->phys, &result->attrs,
392
+ &result->prot, &result->page_size, fi);
393
} else if (arm_feature(env, ARM_FEATURE_V7)) {
394
/* PMSAv7 */
395
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
396
- phys_ptr, prot, page_size, fi);
397
+ &result->phys, &result->prot,
398
+ &result->page_size, fi);
399
} else {
400
/* Pre-v7 MPU */
401
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
402
- phys_ptr, prot, fi);
403
+ &result->phys, &result->prot, fi);
404
}
405
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
406
" mmu_idx %u -> %s (prot %c%c%c)\n",
407
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
408
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
409
(uint32_t)address, mmu_idx,
410
ret ? "Miss" : "Hit",
411
- *prot & PAGE_READ ? 'r' : '-',
412
- *prot & PAGE_WRITE ? 'w' : '-',
413
- *prot & PAGE_EXEC ? 'x' : '-');
414
+ result->prot & PAGE_READ ? 'r' : '-',
415
+ result->prot & PAGE_WRITE ? 'w' : '-',
416
+ result->prot & PAGE_EXEC ? 'x' : '-');
417
418
return ret;
419
}
420
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
421
address = extract64(address, 0, 52);
422
}
423
}
424
- *phys_ptr = address;
425
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
426
- *page_size = TARGET_PAGE_SIZE;
427
+ result->phys = address;
428
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
429
+ result->page_size = TARGET_PAGE_SIZE;
430
431
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
432
hcr = arm_hcr_el2_eff(env);
433
- cacheattrs->shareability = 0;
434
- cacheattrs->is_s2_format = false;
435
+ result->cacheattrs.shareability = 0;
436
+ result->cacheattrs.is_s2_format = false;
437
if (hcr & HCR_DC) {
438
if (hcr & HCR_DCT) {
439
memattr = 0xf0; /* Tagged, Normal, WB, RWA */
440
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
441
} else {
442
memattr = 0x44; /* Normal, NC, No */
443
}
444
- cacheattrs->shareability = 2; /* outer sharable */
445
+ result->cacheattrs.shareability = 2; /* outer sharable */
446
} else {
447
memattr = 0x00; /* Device, nGnRnE */
448
}
449
- cacheattrs->attrs = memattr;
450
+ result->cacheattrs.attrs = memattr;
451
return 0;
452
}
453
454
if (regime_using_lpae_format(env, mmu_idx)) {
455
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
456
- phys_ptr, attrs, prot, page_size,
457
- fi, cacheattrs);
458
+ &result->phys, &result->attrs,
459
+ &result->prot, &result->page_size,
460
+ fi, &result->cacheattrs);
461
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
462
return get_phys_addr_v6(env, address, access_type, mmu_idx,
463
- phys_ptr, attrs, prot, page_size, fi);
464
+ &result->phys, &result->attrs,
465
+ &result->prot, &result->page_size, fi);
466
} else {
467
return get_phys_addr_v5(env, address, access_type, mmu_idx,
468
- phys_ptr, prot, page_size, fi);
469
+ &result->phys, &result->prot,
470
+ &result->page_size, fi);
471
}
472
}
473
474
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
63
{
475
{
64
/* Register all the coprocessor registers based on feature bits */
476
ARMCPU *cpu = ARM_CPU(cs);
65
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
477
CPUARMState *env = &cpu->env;
66
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
478
- hwaddr phys_addr;
67
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
479
- target_ulong page_size;
68
.access = PL1_R, .type = ARM_CP_CONST,
480
- int prot;
69
+ .accessfn = access_aa32_tid3,
481
- bool ret;
70
.resetvalue = cpu->id_pfr0 },
482
+ GetPhysAddrResult res = {};
71
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
483
ARMMMUFaultInfo fi = {};
72
* the value of the GIC field until after we define these regs.
484
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
485
- ARMCacheAttrs cacheattrs = {};
74
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
486
+ bool ret;
75
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
487
76
.access = PL1_R, .type = ARM_CP_NO_RAW,
488
- *attrs = (MemTxAttrs) {};
77
+ .accessfn = access_aa32_tid3,
489
-
78
.readfn = id_pfr1_read,
490
- ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
79
.writefn = arm_cp_write_ignore },
491
- attrs, &prot, &page_size, &fi, &cacheattrs);
80
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
492
+ ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
81
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
493
+ *attrs = res.attrs;
82
.access = PL1_R, .type = ARM_CP_CONST,
494
83
+ .accessfn = access_aa32_tid3,
495
if (ret) {
84
.resetvalue = cpu->id_dfr0 },
496
return -1;
85
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
497
}
86
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
498
- return phys_addr;
87
.access = PL1_R, .type = ARM_CP_CONST,
499
+ return res.phys;
88
+ .accessfn = access_aa32_tid3,
500
}
89
.resetvalue = cpu->id_afr0 },
501
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
90
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
502
index XXXXXXX..XXXXXXX 100644
91
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
503
--- a/target/arm/tlb_helper.c
92
.access = PL1_R, .type = ARM_CP_CONST,
504
+++ b/target/arm/tlb_helper.c
93
+ .accessfn = access_aa32_tid3,
505
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
94
.resetvalue = cpu->id_mmfr0 },
506
{
95
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
507
ARMCPU *cpu = ARM_CPU(cs);
96
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
508
ARMMMUFaultInfo fi = {};
97
.access = PL1_R, .type = ARM_CP_CONST,
509
- hwaddr phys_addr;
98
+ .accessfn = access_aa32_tid3,
510
- target_ulong page_size;
99
.resetvalue = cpu->id_mmfr1 },
511
- int prot, ret;
100
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
512
- MemTxAttrs attrs = {};
101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
513
- ARMCacheAttrs cacheattrs = {};
102
.access = PL1_R, .type = ARM_CP_CONST,
514
+ GetPhysAddrResult res = {};
103
+ .accessfn = access_aa32_tid3,
515
+ int ret;
104
.resetvalue = cpu->id_mmfr2 },
516
105
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
517
/*
106
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
518
* Walk the page table and (if the mapping exists) add the page
107
.access = PL1_R, .type = ARM_CP_CONST,
519
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108
+ .accessfn = access_aa32_tid3,
520
*/
109
.resetvalue = cpu->id_mmfr3 },
521
ret = get_phys_addr(&cpu->env, address, access_type,
110
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
522
core_to_arm_mmu_idx(&cpu->env, mmu_idx),
111
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
523
- &phys_addr, &attrs, &prot, &page_size,
112
.access = PL1_R, .type = ARM_CP_CONST,
524
- &fi, &cacheattrs);
113
+ .accessfn = access_aa32_tid3,
525
+ &res, &fi);
114
.resetvalue = cpu->isar.id_isar0 },
526
if (likely(!ret)) {
115
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
527
/*
116
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
528
* Map a single [sub]page. Regions smaller than our declared
117
.access = PL1_R, .type = ARM_CP_CONST,
529
* target page size are handled specially, so for those we
118
+ .accessfn = access_aa32_tid3,
530
* pass in the exact addresses.
119
.resetvalue = cpu->isar.id_isar1 },
531
*/
120
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
532
- if (page_size >= TARGET_PAGE_SIZE) {
121
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
533
- phys_addr &= TARGET_PAGE_MASK;
122
.access = PL1_R, .type = ARM_CP_CONST,
534
+ if (res.page_size >= TARGET_PAGE_SIZE) {
123
+ .accessfn = access_aa32_tid3,
535
+ res.phys &= TARGET_PAGE_MASK;
124
.resetvalue = cpu->isar.id_isar2 },
536
address &= TARGET_PAGE_MASK;
125
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
537
}
126
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
538
/* Notice and record tagged memory. */
127
.access = PL1_R, .type = ARM_CP_CONST,
539
- if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
128
+ .accessfn = access_aa32_tid3,
540
- arm_tlb_mte_tagged(&attrs) = true;
129
.resetvalue = cpu->isar.id_isar3 },
541
+ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
130
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
542
+ arm_tlb_mte_tagged(&res.attrs) = true;
131
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
543
}
132
.access = PL1_R, .type = ARM_CP_CONST,
544
133
+ .accessfn = access_aa32_tid3,
545
- tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
134
.resetvalue = cpu->isar.id_isar4 },
546
- prot, mmu_idx, page_size);
135
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
547
+ tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
136
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
548
+ res.prot, mmu_idx, res.page_size);
137
.access = PL1_R, .type = ARM_CP_CONST,
549
return true;
138
+ .accessfn = access_aa32_tid3,
550
} else if (probe) {
139
.resetvalue = cpu->isar.id_isar5 },
551
return false;
140
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
141
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
142
.access = PL1_R, .type = ARM_CP_CONST,
143
+ .accessfn = access_aa32_tid3,
144
.resetvalue = cpu->id_mmfr4 },
145
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
146
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
147
.access = PL1_R, .type = ARM_CP_CONST,
148
+ .accessfn = access_aa32_tid3,
149
.resetvalue = cpu->isar.id_isar6 },
150
REGINFO_SENTINEL
151
};
152
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
153
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
154
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
155
.access = PL1_R, .type = ARM_CP_NO_RAW,
156
+ .accessfn = access_aa64_tid3,
157
.readfn = id_aa64pfr0_read,
158
.writefn = arm_cp_write_ignore },
159
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
160
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
161
.access = PL1_R, .type = ARM_CP_CONST,
162
+ .accessfn = access_aa64_tid3,
163
.resetvalue = cpu->isar.id_aa64pfr1},
164
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
165
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
166
.access = PL1_R, .type = ARM_CP_CONST,
167
+ .accessfn = access_aa64_tid3,
168
.resetvalue = 0 },
169
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
170
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
171
.access = PL1_R, .type = ARM_CP_CONST,
172
+ .accessfn = access_aa64_tid3,
173
.resetvalue = 0 },
174
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
175
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
176
.access = PL1_R, .type = ARM_CP_CONST,
177
+ .accessfn = access_aa64_tid3,
178
/* At present, only SVEver == 0 is defined anyway. */
179
.resetvalue = 0 },
180
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
181
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
182
.access = PL1_R, .type = ARM_CP_CONST,
183
+ .accessfn = access_aa64_tid3,
184
.resetvalue = 0 },
185
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
186
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
187
.access = PL1_R, .type = ARM_CP_CONST,
188
+ .accessfn = access_aa64_tid3,
189
.resetvalue = 0 },
190
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
191
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
192
.access = PL1_R, .type = ARM_CP_CONST,
193
+ .accessfn = access_aa64_tid3,
194
.resetvalue = 0 },
195
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
196
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
197
.access = PL1_R, .type = ARM_CP_CONST,
198
+ .accessfn = access_aa64_tid3,
199
.resetvalue = cpu->id_aa64dfr0 },
200
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
201
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
202
.access = PL1_R, .type = ARM_CP_CONST,
203
+ .accessfn = access_aa64_tid3,
204
.resetvalue = cpu->id_aa64dfr1 },
205
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
206
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
207
.access = PL1_R, .type = ARM_CP_CONST,
208
+ .accessfn = access_aa64_tid3,
209
.resetvalue = 0 },
210
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
211
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
212
.access = PL1_R, .type = ARM_CP_CONST,
213
+ .accessfn = access_aa64_tid3,
214
.resetvalue = 0 },
215
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
216
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
217
.access = PL1_R, .type = ARM_CP_CONST,
218
+ .accessfn = access_aa64_tid3,
219
.resetvalue = cpu->id_aa64afr0 },
220
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
221
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
222
.access = PL1_R, .type = ARM_CP_CONST,
223
+ .accessfn = access_aa64_tid3,
224
.resetvalue = cpu->id_aa64afr1 },
225
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
226
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
227
.access = PL1_R, .type = ARM_CP_CONST,
228
+ .accessfn = access_aa64_tid3,
229
.resetvalue = 0 },
230
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
231
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
232
.access = PL1_R, .type = ARM_CP_CONST,
233
+ .accessfn = access_aa64_tid3,
234
.resetvalue = 0 },
235
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
236
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
237
.access = PL1_R, .type = ARM_CP_CONST,
238
+ .accessfn = access_aa64_tid3,
239
.resetvalue = cpu->isar.id_aa64isar0 },
240
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
241
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
242
.access = PL1_R, .type = ARM_CP_CONST,
243
+ .accessfn = access_aa64_tid3,
244
.resetvalue = cpu->isar.id_aa64isar1 },
245
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
246
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
247
.access = PL1_R, .type = ARM_CP_CONST,
248
+ .accessfn = access_aa64_tid3,
249
.resetvalue = 0 },
250
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
251
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
252
.access = PL1_R, .type = ARM_CP_CONST,
253
+ .accessfn = access_aa64_tid3,
254
.resetvalue = 0 },
255
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
256
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
257
.access = PL1_R, .type = ARM_CP_CONST,
258
+ .accessfn = access_aa64_tid3,
259
.resetvalue = 0 },
260
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
261
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
262
.access = PL1_R, .type = ARM_CP_CONST,
263
+ .accessfn = access_aa64_tid3,
264
.resetvalue = 0 },
265
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
266
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
267
.access = PL1_R, .type = ARM_CP_CONST,
268
+ .accessfn = access_aa64_tid3,
269
.resetvalue = 0 },
270
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
271
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
272
.access = PL1_R, .type = ARM_CP_CONST,
273
+ .accessfn = access_aa64_tid3,
274
.resetvalue = 0 },
275
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
277
.access = PL1_R, .type = ARM_CP_CONST,
278
+ .accessfn = access_aa64_tid3,
279
.resetvalue = cpu->isar.id_aa64mmfr0 },
280
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
+ .accessfn = access_aa64_tid3,
284
.resetvalue = cpu->isar.id_aa64mmfr1 },
285
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
287
.access = PL1_R, .type = ARM_CP_CONST,
288
+ .accessfn = access_aa64_tid3,
289
.resetvalue = 0 },
290
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
291
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
292
.access = PL1_R, .type = ARM_CP_CONST,
293
+ .accessfn = access_aa64_tid3,
294
.resetvalue = 0 },
295
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
296
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
297
.access = PL1_R, .type = ARM_CP_CONST,
298
+ .accessfn = access_aa64_tid3,
299
.resetvalue = 0 },
300
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
301
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
302
.access = PL1_R, .type = ARM_CP_CONST,
303
+ .accessfn = access_aa64_tid3,
304
.resetvalue = 0 },
305
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
306
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
307
.access = PL1_R, .type = ARM_CP_CONST,
308
+ .accessfn = access_aa64_tid3,
309
.resetvalue = 0 },
310
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
311
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
312
.access = PL1_R, .type = ARM_CP_CONST,
313
+ .accessfn = access_aa64_tid3,
314
.resetvalue = 0 },
315
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
316
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
317
.access = PL1_R, .type = ARM_CP_CONST,
318
+ .accessfn = access_aa64_tid3,
319
.resetvalue = cpu->isar.mvfr0 },
320
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
321
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
322
.access = PL1_R, .type = ARM_CP_CONST,
323
+ .accessfn = access_aa64_tid3,
324
.resetvalue = cpu->isar.mvfr1 },
325
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
327
.access = PL1_R, .type = ARM_CP_CONST,
328
+ .accessfn = access_aa64_tid3,
329
.resetvalue = cpu->isar.mvfr2 },
330
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
331
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
332
.access = PL1_R, .type = ARM_CP_CONST,
333
+ .accessfn = access_aa64_tid3,
334
.resetvalue = 0 },
335
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
336
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
337
.access = PL1_R, .type = ARM_CP_CONST,
338
+ .accessfn = access_aa64_tid3,
339
.resetvalue = 0 },
340
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
341
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
342
.access = PL1_R, .type = ARM_CP_CONST,
343
+ .accessfn = access_aa64_tid3,
344
.resetvalue = 0 },
345
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
346
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
347
.access = PL1_R, .type = ARM_CP_CONST,
348
+ .accessfn = access_aa64_tid3,
349
.resetvalue = 0 },
350
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
351
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
352
.access = PL1_R, .type = ARM_CP_CONST,
353
+ .accessfn = access_aa64_tid3,
354
.resetvalue = 0 },
355
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
356
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
357
--
552
--
358
2.20.1
553
2.25.1
359
360
diff view generated by jsdifflib
New patch
[PULL 04/39] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-4-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/ptw.c | 69 ++++++++++++++++++------------------------------
10
1 file changed, 26 insertions(+), 43 deletions(-)
11
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
15
+++ b/target/arm/ptw.c
16
@@ -XXX,XX +XXX,XX @@
17
18
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- bool s1_is_el0, hwaddr *phys_ptr,
21
- MemTxAttrs *txattrs, int *prot,
22
- target_ulong *page_size_ptr,
23
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
24
+ bool s1_is_el0, GetPhysAddrResult *result,
25
+ ARMMMUFaultInfo *fi)
26
__attribute__((nonnull));
27
28
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
29
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
30
{
31
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
32
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
33
- target_ulong s2size;
34
- hwaddr s2pa;
35
- int s2prot;
36
- int ret;
37
ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
38
: ARMMMUIdx_Stage2;
39
- ARMCacheAttrs cacheattrs = {};
40
- MemTxAttrs txattrs = {};
41
+ GetPhysAddrResult s2 = {};
42
+ int ret;
43
44
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
45
- &s2pa, &txattrs, &s2prot, &s2size, fi,
46
- &cacheattrs);
47
+ &s2, fi);
48
if (ret) {
49
assert(fi->type != ARMFault_None);
50
fi->s2addr = addr;
51
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
52
return ~0;
53
}
54
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
55
- ptw_attrs_are_device(env, cacheattrs)) {
56
+ ptw_attrs_are_device(env, s2.cacheattrs)) {
57
/*
58
* PTW set and S1 walk touched S2 Device memory:
59
* generate Permission fault.
60
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
61
assert(!*is_secure);
62
}
63
64
- addr = s2pa;
65
+ addr = s2.phys;
66
}
67
return addr;
68
}
69
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
70
* table walk), must be true if this is stage 2 of a stage 1+2
71
* walk for an EL0 access. If @mmu_idx is anything else,
72
* @s1_is_el0 is ignored.
73
- * @phys_ptr: set to the physical address corresponding to the virtual address
74
- * @attrs: set to the memory transaction attributes to use
75
- * @prot: set to the permissions for the page containing phys_ptr
76
- * @page_size_ptr: set to the size of the page containing phys_ptr
77
+ * @result: set on translation success,
78
* @fi: set to fault info if the translation fails
79
- * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
80
*/
81
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
82
MMUAccessType access_type, ARMMMUIdx mmu_idx,
83
- bool s1_is_el0, hwaddr *phys_ptr,
84
- MemTxAttrs *txattrs, int *prot,
85
- target_ulong *page_size_ptr,
86
- ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
87
+ bool s1_is_el0, GetPhysAddrResult *result,
88
+ ARMMMUFaultInfo *fi)
89
{
90
ARMCPU *cpu = env_archcpu(env);
91
/* Read an LPAE long-descriptor translation table. */
92
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
93
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
94
ns = mmu_idx == ARMMMUIdx_Stage2;
95
xn = extract32(attrs, 11, 2);
96
- *prot = get_S2prot(env, ap, xn, s1_is_el0);
97
+ result->prot = get_S2prot(env, ap, xn, s1_is_el0);
98
} else {
99
ns = extract32(attrs, 3, 1);
100
xn = extract32(attrs, 12, 1);
101
pxn = extract32(attrs, 11, 1);
102
- *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
103
+ result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
104
}
105
106
fault_type = ARMFault_Permission;
107
- if (!(*prot & (1 << access_type))) {
108
+ if (!(result->prot & (1 << access_type))) {
109
goto do_fault;
110
}
111
112
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
113
* the CPU doesn't support TZ or this is a non-secure translation
114
* regime, because the attribute will already be non-secure.
115
*/
116
- txattrs->secure = false;
117
+ result->attrs.secure = false;
118
}
119
/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
120
if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
121
- arm_tlb_bti_gp(txattrs) = true;
122
+ arm_tlb_bti_gp(&result->attrs) = true;
123
}
124
125
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
126
- cacheattrs->is_s2_format = true;
127
- cacheattrs->attrs = extract32(attrs, 0, 4);
128
+ result->cacheattrs.is_s2_format = true;
129
+ result->cacheattrs.attrs = extract32(attrs, 0, 4);
130
} else {
131
/* Index into MAIR registers for cache attributes */
132
uint8_t attrindx = extract32(attrs, 0, 3);
133
uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
134
assert(attrindx <= 7);
135
- cacheattrs->is_s2_format = false;
136
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
137
+ result->cacheattrs.is_s2_format = false;
138
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
139
}
140
141
/*
142
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
143
* that case comes from TCR_ELx, which we extracted earlier.
144
*/
145
if (param.ds) {
146
- cacheattrs->shareability = param.sh;
147
+ result->cacheattrs.shareability = param.sh;
148
} else {
149
- cacheattrs->shareability = extract32(attrs, 6, 2);
150
+ result->cacheattrs.shareability = extract32(attrs, 6, 2);
151
}
152
153
- *phys_ptr = descaddr;
154
- *page_size_ptr = page_size;
155
+ result->phys = descaddr;
156
+ result->page_size = page_size;
157
return false;
158
159
do_fault:
160
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
161
cacheattrs1 = result->cacheattrs;
162
memset(result, 0, sizeof(*result));
163
164
- ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0,
165
- &result->phys, &result->attrs,
166
- &result->prot, &result->page_size,
167
- fi, &result->cacheattrs);
168
+ ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
169
+ is_el0, result, fi);
170
fi->s2addr = ipa;
171
172
/* Combine the S1 and S2 perms. */
173
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
174
175
if (regime_using_lpae_format(env, mmu_idx)) {
176
return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
177
- &result->phys, &result->attrs,
178
- &result->prot, &result->page_size,
179
- fi, &result->cacheattrs);
180
+ result, fi);
181
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
182
return get_phys_addr_v6(env, address, access_type, mmu_idx,
183
&result->phys, &result->attrs,
184
--
185
2.25.1
186
187
diff view generated by jsdifflib
New patch
[PULL 05/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v6
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-5-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/ptw.c | 30 ++++++++++++++----------------
10
1 file changed, 14 insertions(+), 16 deletions(-)
11
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
15
+++ b/target/arm/ptw.c
16
@@ -XXX,XX +XXX,XX @@ do_fault:
17
18
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
21
- target_ulong *page_size, ARMMMUFaultInfo *fi)
22
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
23
{
24
ARMCPU *cpu = env_archcpu(env);
25
int level = 1;
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
27
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
28
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
29
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
30
- *page_size = 0x1000000;
31
+ result->page_size = 0x1000000;
32
} else {
33
/* Section. */
34
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
35
- *page_size = 0x100000;
36
+ result->page_size = 0x100000;
37
}
38
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
39
xn = desc & (1 << 4);
40
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
41
case 1: /* 64k page. */
42
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
43
xn = desc & (1 << 15);
44
- *page_size = 0x10000;
45
+ result->page_size = 0x10000;
46
break;
47
case 2: case 3: /* 4k page. */
48
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
49
xn = desc & 1;
50
- *page_size = 0x1000;
51
+ result->page_size = 0x1000;
52
break;
53
default:
54
/* Never happens, but compiler isn't smart enough to tell. */
55
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
56
}
57
}
58
if (domain_prot == 3) {
59
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
60
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
61
} else {
62
if (pxn && !regime_is_user(env, mmu_idx)) {
63
xn = 1;
64
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
65
fi->type = ARMFault_AccessFlag;
66
goto do_fault;
67
}
68
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
69
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
70
} else {
71
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
72
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
73
}
74
- if (*prot && !xn) {
75
- *prot |= PAGE_EXEC;
76
+ if (result->prot && !xn) {
77
+ result->prot |= PAGE_EXEC;
78
}
79
- if (!(*prot & (1 << access_type))) {
80
+ if (!(result->prot & (1 << access_type))) {
81
/* Access permission fault. */
82
fi->type = ARMFault_Permission;
83
goto do_fault;
84
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
85
* the CPU doesn't support TZ or this is a non-secure translation
86
* regime, because the attribute will already be non-secure.
87
*/
88
- attrs->secure = false;
89
+ result->attrs.secure = false;
90
}
91
- *phys_ptr = phys_addr;
92
+ result->phys = phys_addr;
93
return false;
94
do_fault:
95
fi->domain = domain;
96
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
97
result, fi);
98
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
99
return get_phys_addr_v6(env, address, access_type, mmu_idx,
100
- &result->phys, &result->attrs,
101
- &result->prot, &result->page_size, fi);
102
+ result, fi);
103
} else {
104
return get_phys_addr_v5(env, address, access_type, mmu_idx,
105
&result->phys, &result->prot,
106
--
107
2.25.1
108
109
diff view generated by jsdifflib
New patch
[PULL 06/39] target/arm: Use GetPhysAddrResult in get_phys_addr_v5
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-6-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/ptw.c | 25 +++++++++++--------------
10
1 file changed, 11 insertions(+), 14 deletions(-)
11
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
15
+++ b/target/arm/ptw.c
16
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
17
18
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, int *prot,
21
- target_ulong *page_size,
22
- ARMMMUFaultInfo *fi)
23
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
24
{
25
int level = 1;
26
uint32_t table;
27
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
28
/* 1Mb section. */
29
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
30
ap = (desc >> 10) & 3;
31
- *page_size = 1024 * 1024;
32
+ result->page_size = 1024 * 1024;
33
} else {
34
/* Lookup l2 entry. */
35
if (type == 1) {
36
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
37
case 1: /* 64k page. */
38
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
39
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
40
- *page_size = 0x10000;
41
+ result->page_size = 0x10000;
42
break;
43
case 2: /* 4k page. */
44
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
45
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
46
- *page_size = 0x1000;
47
+ result->page_size = 0x1000;
48
break;
49
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
50
if (type == 1) {
51
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
52
if (arm_feature(env, ARM_FEATURE_XSCALE)
53
|| arm_feature(env, ARM_FEATURE_V6)) {
54
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
55
- *page_size = 0x1000;
56
+ result->page_size = 0x1000;
57
} else {
58
/*
59
* UNPREDICTABLE in ARMv5; we choose to take a
60
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
61
}
62
} else {
63
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
64
- *page_size = 0x400;
65
+ result->page_size = 0x400;
66
}
67
ap = (desc >> 4) & 3;
68
break;
69
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
70
g_assert_not_reached();
71
}
72
}
73
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
74
- *prot |= *prot ? PAGE_EXEC : 0;
75
- if (!(*prot & (1 << access_type))) {
76
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
77
+ result->prot |= result->prot ? PAGE_EXEC : 0;
78
+ if (!(result->prot & (1 << access_type))) {
79
/* Access permission fault. */
80
fi->type = ARMFault_Permission;
81
goto do_fault;
82
}
83
- *phys_ptr = phys_addr;
84
+ result->phys = phys_addr;
85
return false;
86
do_fault:
87
fi->domain = domain;
88
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
89
result, fi);
90
} else {
91
return get_phys_addr_v5(env, address, access_type, mmu_idx,
92
- &result->phys, &result->prot,
93
- &result->page_size, fi);
94
+ result, fi);
95
}
96
}
97
98
--
99
2.25.1
100
101
diff view generated by jsdifflib
New patch
[PULL 07/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-7-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/ptw.c | 24 ++++++++++++------------
10
1 file changed, 12 insertions(+), 12 deletions(-)
11
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
15
+++ b/target/arm/ptw.c
16
@@ -XXX,XX +XXX,XX @@ do_fault:
17
18
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, int *prot,
21
+ GetPhysAddrResult *result,
22
ARMMMUFaultInfo *fi)
23
{
24
int n;
25
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
26
27
if (regime_translation_disabled(env, mmu_idx)) {
28
/* MPU disabled. */
29
- *phys_ptr = address;
30
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
31
+ result->phys = address;
32
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
33
return false;
34
}
35
36
- *phys_ptr = address;
37
+ result->phys = address;
38
for (n = 7; n >= 0; n--) {
39
base = env->cp15.c6_region[n];
40
if ((base & 1) == 0) {
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
42
fi->level = 1;
43
return true;
44
}
45
- *prot = PAGE_READ | PAGE_WRITE;
46
+ result->prot = PAGE_READ | PAGE_WRITE;
47
break;
48
case 2:
49
- *prot = PAGE_READ;
50
+ result->prot = PAGE_READ;
51
if (!is_user) {
52
- *prot |= PAGE_WRITE;
53
+ result->prot |= PAGE_WRITE;
54
}
55
break;
56
case 3:
57
- *prot = PAGE_READ | PAGE_WRITE;
58
+ result->prot = PAGE_READ | PAGE_WRITE;
59
break;
60
case 5:
61
if (is_user) {
62
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
63
fi->level = 1;
64
return true;
65
}
66
- *prot = PAGE_READ;
67
+ result->prot = PAGE_READ;
68
break;
69
case 6:
70
- *prot = PAGE_READ;
71
+ result->prot = PAGE_READ;
72
break;
73
default:
74
/* Bad permission. */
75
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
76
fi->level = 1;
77
return true;
78
}
79
- *prot |= PAGE_EXEC;
80
+ result->prot |= PAGE_EXEC;
81
return false;
82
}
83
84
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
85
} else {
86
/* Pre-v7 MPU */
87
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
88
- &result->phys, &result->prot, fi);
89
+ result, fi);
90
}
91
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
92
" mmu_idx %u -> %s (prot %c%c%c)\n",
93
--
94
2.25.1
95
96
diff view generated by jsdifflib
New patch
[PULL 08/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-8-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/ptw.c | 36 +++++++++++++++++-------------------
10
1 file changed, 17 insertions(+), 19 deletions(-)
11
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/ptw.c
15
+++ b/target/arm/ptw.c
16
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
17
18
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
- hwaddr *phys_ptr, int *prot,
21
- target_ulong *page_size,
22
+ GetPhysAddrResult *result,
23
ARMMMUFaultInfo *fi)
24
{
25
ARMCPU *cpu = env_archcpu(env);
26
int n;
27
bool is_user = regime_is_user(env, mmu_idx);
28
29
- *phys_ptr = address;
30
- *page_size = TARGET_PAGE_SIZE;
31
- *prot = 0;
32
+ result->phys = address;
33
+ result->page_size = TARGET_PAGE_SIZE;
34
+ result->prot = 0;
35
36
if (regime_translation_disabled(env, mmu_idx) ||
37
m_is_ppb_region(env, address)) {
38
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
39
* which always does a direct read using address_space_ldl(), rather
40
* than going via this function, so we don't need to check that here.
41
*/
42
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
43
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
44
} else { /* MPU enabled */
45
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
46
/* region search */
47
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
48
if (ranges_overlap(base, rmask,
49
address & TARGET_PAGE_MASK,
50
TARGET_PAGE_SIZE)) {
51
- *page_size = 1;
52
+ result->page_size = 1;
53
}
54
continue;
55
}
56
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
57
continue;
58
}
59
if (rsize < TARGET_PAGE_BITS) {
60
- *page_size = 1 << rsize;
61
+ result->page_size = 1 << rsize;
62
}
63
break;
64
}
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
66
fi->type = ARMFault_Background;
67
return true;
68
}
69
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
70
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
71
} else { /* a MPU hit! */
72
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
73
uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
75
case 5:
76
break; /* no access */
77
case 3:
78
- *prot |= PAGE_WRITE;
79
+ result->prot |= PAGE_WRITE;
80
/* fall through */
81
case 2:
82
case 6:
83
- *prot |= PAGE_READ | PAGE_EXEC;
84
+ result->prot |= PAGE_READ | PAGE_EXEC;
85
break;
86
case 7:
87
/* for v7M, same as 6; for R profile a reserved value */
88
if (arm_feature(env, ARM_FEATURE_M)) {
89
- *prot |= PAGE_READ | PAGE_EXEC;
90
+ result->prot |= PAGE_READ | PAGE_EXEC;
91
break;
92
}
93
/* fall through */
94
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
95
case 1:
96
case 2:
97
case 3:
98
- *prot |= PAGE_WRITE;
99
+ result->prot |= PAGE_WRITE;
100
/* fall through */
101
case 5:
102
case 6:
103
- *prot |= PAGE_READ | PAGE_EXEC;
104
+ result->prot |= PAGE_READ | PAGE_EXEC;
105
break;
106
case 7:
107
/* for v7M, same as 6; for R profile a reserved value */
108
if (arm_feature(env, ARM_FEATURE_M)) {
109
- *prot |= PAGE_READ | PAGE_EXEC;
110
+ result->prot |= PAGE_READ | PAGE_EXEC;
111
break;
112
}
113
/* fall through */
114
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
115
116
/* execute never */
117
if (xn) {
118
- *prot &= ~PAGE_EXEC;
119
+ result->prot &= ~PAGE_EXEC;
120
}
121
}
122
}
123
124
fi->type = ARMFault_Permission;
125
fi->level = 1;
126
- return !(*prot & (1 << access_type));
127
+ return !(result->prot & (1 << access_type));
128
}
129
130
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
131
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
132
} else if (arm_feature(env, ARM_FEATURE_V7)) {
133
/* PMSAv7 */
134
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
135
- &result->phys, &result->prot,
136
- &result->page_size, fi);
137
+ result, fi);
138
} else {
139
/* Pre-v7 MPU */
140
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
141
--
142
2.25.1
143
144
diff view generated by jsdifflib
[PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2
[PULL 09/39] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8
1
From: Marc Zyngier <maz@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
SError interrupts.
5
Message-id: 20220822152741.1617527-9-richard.henderson@linaro.org
6
7
Unfortunately, QEMU's implementation only considers the HCR_EL2
8
bits, and ignores the current exception level. This means a hypervisor
9
trying to look at its own interrupt state actually sees the guest
10
state, which is unexpected and breaks KVM as of Linux 5.3.
11
12
Instead, check for the running EL and return the physical bits
13
if not running in a virtualized context.
14
15
Fixes: 636540e9c40b
16
Cc: qemu-stable@nongnu.org
17
Reported-by: Quentin Perret <qperret@google.com>
18
Signed-off-by: Marc Zyngier <maz@kernel.org>
19
Message-id: 20191122135833.28953-1-maz@kernel.org
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
8
---
24
target/arm/helper.c | 7 +++++--
9
target/arm/ptw.c | 28 ++++++++++++++--------------
25
1 file changed, 5 insertions(+), 2 deletions(-)
10
1 file changed, 14 insertions(+), 14 deletions(-)
26
11
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
28
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
14
--- a/target/arm/ptw.c
30
+++ b/target/arm/helper.c
15
+++ b/target/arm/ptw.c
31
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
16
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
32
CPUState *cs = env_cpu(env);
17
33
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
18
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
34
uint64_t ret = 0;
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
35
+ bool allow_virt = (arm_current_el(env) == 1 &&
20
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
36
+ (!arm_is_secure_below_el3(env) ||
21
- int *prot, target_ulong *page_size,
37
+ (env->cp15.scr_el3 & SCR_EEL2)));
22
+ GetPhysAddrResult *result,
38
23
ARMMMUFaultInfo *fi)
39
- if (hcr_el2 & HCR_IMO) {
24
{
40
+ if (allow_virt && (hcr_el2 & HCR_IMO)) {
25
uint32_t secure = regime_is_secure(env, mmu_idx);
41
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
26
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
42
ret |= CPSR_I;
27
} else {
43
}
28
fi->type = ARMFault_QEMU_SFault;
44
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
29
}
30
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
31
- *phys_ptr = address;
32
- *prot = 0;
33
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
34
+ result->phys = address;
35
+ result->prot = 0;
36
return true;
37
}
38
} else {
39
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
40
* might downgrade a secure access to nonsecure.
41
*/
42
if (sattrs.ns) {
43
- txattrs->secure = false;
44
+ result->attrs.secure = false;
45
} else if (!secure) {
46
/*
47
* NS access to S memory must fault.
48
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
49
* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
50
*/
51
fi->type = ARMFault_QEMU_SFault;
52
- *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
53
- *phys_ptr = address;
54
- *prot = 0;
55
+ result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
56
+ result->phys = address;
57
+ result->prot = 0;
58
return true;
59
}
45
}
60
}
46
}
61
}
47
62
48
- if (hcr_el2 & HCR_FMO) {
63
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
49
+ if (allow_virt && (hcr_el2 & HCR_FMO)) {
64
- txattrs, prot, &mpu_is_subpage, fi, NULL);
50
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
65
- *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
51
ret |= CPSR_F;
66
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
52
}
67
+ &result->phys, &result->attrs, &result->prot,
68
+ &mpu_is_subpage, fi, NULL);
69
+ result->page_size =
70
+ sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
71
return ret;
72
}
73
74
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
75
if (arm_feature(env, ARM_FEATURE_V8)) {
76
/* PMSAv8 */
77
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
78
- &result->phys, &result->attrs,
79
- &result->prot, &result->page_size, fi);
80
+ result, fi);
81
} else if (arm_feature(env, ARM_FEATURE_V7)) {
82
/* PMSAv7 */
83
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
53
--
84
--
54
2.20.1
85
2.25.1
55
86
56
87
diff view generated by jsdifflib
New patch
[PULL 10/39] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220822152741.1617527-10-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/internals.h | 11 +++++------
10
target/arm/m_helper.c | 16 +++++++---------
11
target/arm/ptw.c | 20 +++++++++-----------
12
3 files changed, 21 insertions(+), 26 deletions(-)
13
14
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/internals.h
17
+++ b/target/arm/internals.h
18
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
V8M_SAttributes *sattrs);
21
22
-bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
23
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
24
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
25
- int *prot, bool *is_subpage,
26
- ARMMMUFaultInfo *fi, uint32_t *mregion);
27
-
28
/* Cacheability and shareability attributes for a memory access */
29
typedef struct ARMCacheAttrs {
30
/*
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
32
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
33
__attribute__((nonnull));
34
35
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
36
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
37
+ GetPhysAddrResult *result, bool *is_subpage,
38
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
39
+
40
void arm_log_exception(CPUState *cs);
41
42
#endif /* !CONFIG_USER_ONLY */
43
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/m_helper.c
46
+++ b/target/arm/m_helper.c
47
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
48
V8M_SAttributes sattrs = {};
49
uint32_t tt_resp;
50
bool r, rw, nsr, nsrw, mrvalid;
51
- int prot;
52
- ARMMMUFaultInfo fi = {};
53
- MemTxAttrs attrs = {};
54
- hwaddr phys_addr;
55
ARMMMUIdx mmu_idx;
56
uint32_t mregion;
57
bool targetpriv;
58
bool targetsec = env->v7m.secure;
59
- bool is_subpage;
60
61
/*
62
* Work out what the security state and privilege level we're
63
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
64
* inspecting the other MPU state.
65
*/
66
if (arm_current_el(env) != 0 || alt) {
67
+ GetPhysAddrResult res = {};
68
+ ARMMMUFaultInfo fi = {};
69
+ bool is_subpage;
70
+
71
/* We can ignore the return value as prot is always set */
72
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
73
- &phys_addr, &attrs, &prot, &is_subpage,
74
- &fi, &mregion);
75
+ &res, &is_subpage, &fi, &mregion);
76
if (mregion == -1) {
77
mrvalid = false;
78
mregion = 0;
79
} else {
80
mrvalid = true;
81
}
82
- r = prot & PAGE_READ;
83
- rw = prot & PAGE_WRITE;
84
+ r = res.prot & PAGE_READ;
85
+ rw = res.prot & PAGE_WRITE;
86
} else {
87
r = false;
88
rw = false;
89
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/ptw.c
92
+++ b/target/arm/ptw.c
93
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
94
95
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
96
MMUAccessType access_type, ARMMMUIdx mmu_idx,
97
- hwaddr *phys_ptr, MemTxAttrs *txattrs,
98
- int *prot, bool *is_subpage,
99
+ GetPhysAddrResult *result, bool *is_subpage,
100
ARMMMUFaultInfo *fi, uint32_t *mregion)
101
{
102
/*
103
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
104
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
105
106
*is_subpage = false;
107
- *phys_ptr = address;
108
- *prot = 0;
109
+ result->phys = address;
110
+ result->prot = 0;
111
if (mregion) {
112
*mregion = -1;
113
}
114
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
115
116
if (matchregion == -1) {
117
/* hit using the background region */
118
- get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
119
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
120
} else {
121
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
122
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
123
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
124
xn = 1;
125
}
126
127
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
128
- if (*prot && !xn && !(pxn && !is_user)) {
129
- *prot |= PAGE_EXEC;
130
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
131
+ if (result->prot && !xn && !(pxn && !is_user)) {
132
+ result->prot |= PAGE_EXEC;
133
}
134
/*
135
* We don't need to look the attribute up in the MAIR0/MAIR1
136
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
137
138
fi->type = ARMFault_Permission;
139
fi->level = 1;
140
- return !(*prot & (1 << access_type));
141
+ return !(result->prot & (1 << access_type));
142
}
143
144
static bool v8m_is_sau_exempt(CPUARMState *env,
145
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
146
}
147
148
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
149
- &result->phys, &result->attrs, &result->prot,
150
- &mpu_is_subpage, fi, NULL);
151
+ result, &mpu_is_subpage, fi, NULL);
152
result->page_size =
153
sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
154
return ret;
155
--
156
2.25.1
157
158
diff view generated by jsdifflib
New patch
[PULL 11/39] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This can be made redundant with result->page_size, by moving the basic
4
set of page_size from get_phys_addr_pmsav8. We still need to overwrite
5
page_size when v8m_security_lookup signals a subpage.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-11-richard.henderson@linaro.org
9
[PMM: Update a comment that used to refer to is_subpage]
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/internals.h | 4 ++--
14
target/arm/m_helper.c | 3 +--
15
target/arm/ptw.c | 23 ++++++++++++-----------
16
3 files changed, 15 insertions(+), 15 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
21
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
23
24
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
25
MMUAccessType access_type, ARMMMUIdx mmu_idx,
26
- GetPhysAddrResult *result, bool *is_subpage,
27
- ARMMMUFaultInfo *fi, uint32_t *mregion);
28
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
29
+ uint32_t *mregion);
30
31
void arm_log_exception(CPUState *cs);
32
33
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/m_helper.c
36
+++ b/target/arm/m_helper.c
37
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
38
if (arm_current_el(env) != 0 || alt) {
39
GetPhysAddrResult res = {};
40
ARMMMUFaultInfo fi = {};
41
- bool is_subpage;
42
43
/* We can ignore the return value as prot is always set */
44
pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
45
- &res, &is_subpage, &fi, &mregion);
46
+ &res, &fi, &mregion);
47
if (mregion == -1) {
48
mrvalid = false;
49
mregion = 0;
50
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/ptw.c
53
+++ b/target/arm/ptw.c
54
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
55
56
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
57
MMUAccessType access_type, ARMMMUIdx mmu_idx,
58
- GetPhysAddrResult *result, bool *is_subpage,
59
- ARMMMUFaultInfo *fi, uint32_t *mregion)
60
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
61
+ uint32_t *mregion)
62
{
63
/*
64
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
65
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
66
* mregion is (if not NULL) set to the region number which matched,
67
* or -1 if no region number is returned (MPU off, address did not
68
* hit a region, address hit in multiple regions).
69
- * We set is_subpage to true if the region hit doesn't cover the
70
- * entire TARGET_PAGE the address is within.
71
+ * If the region hit doesn't cover the entire TARGET_PAGE the address
72
+ * is within, then we set the result page_size to 1 to force the
73
+ * memory system to use a subpage.
74
*/
75
ARMCPU *cpu = env_archcpu(env);
76
bool is_user = regime_is_user(env, mmu_idx);
77
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
78
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
79
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
80
81
- *is_subpage = false;
82
+ result->page_size = TARGET_PAGE_SIZE;
83
result->phys = address;
84
result->prot = 0;
85
if (mregion) {
86
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
87
ranges_overlap(base, limit - base + 1,
88
addr_page_base,
89
TARGET_PAGE_SIZE)) {
90
- *is_subpage = true;
91
+ result->page_size = 1;
92
}
93
continue;
94
}
95
96
if (base > addr_page_base || limit < addr_page_limit) {
97
- *is_subpage = true;
98
+ result->page_size = 1;
99
}
100
101
if (matchregion != -1) {
102
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
103
uint32_t secure = regime_is_secure(env, mmu_idx);
104
V8M_SAttributes sattrs = {};
105
bool ret;
106
- bool mpu_is_subpage;
107
108
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
109
v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
110
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
111
}
112
113
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
114
- result, &mpu_is_subpage, fi, NULL);
115
- result->page_size =
116
- sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
117
+ result, fi, NULL);
118
+ if (sattrs.subpage) {
119
+ result->page_size = 1;
120
+ }
121
return ret;
122
}
123
124
--
125
2.25.1
diff view generated by jsdifflib
New patch
[PULL 12/39] target/arm: Add is_secure parameter to v8m_security_lookup
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the use of regime_is_secure from v8m_security_lookup,
4
passing the new parameter to the lookup instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-12-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 2 +-
13
target/arm/m_helper.c | 9 ++++++---
14
target/arm/ptw.c | 9 +++++----
15
3 files changed, 12 insertions(+), 8 deletions(-)
16
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
20
+++ b/target/arm/internals.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
22
23
void v8m_security_lookup(CPUARMState *env, uint32_t address,
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
25
- V8M_SAttributes *sattrs);
26
+ bool secure, V8M_SAttributes *sattrs);
27
28
/* Cacheability and shareability attributes for a memory access */
29
typedef struct ARMCacheAttrs {
30
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/m_helper.c
33
+++ b/target/arm/m_helper.c
34
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
35
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
36
V8M_SAttributes sattrs = {};
37
38
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
39
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
40
+ targets_secure, &sattrs);
41
if (sattrs.ns) {
42
attrs.secure = false;
43
} else if (!targets_secure) {
44
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
45
ARMMMUFaultInfo fi = {};
46
MemTxResult txres;
47
48
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
49
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
50
+ regime_is_secure(env, mmu_idx), &sattrs);
51
if (!sattrs.nsc || sattrs.ns) {
52
/*
53
* This must be the second half of the insn, and it straddles a
54
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
55
}
56
57
if (env->v7m.secure) {
58
- v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
59
+ v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
60
+ targetsec, &sattrs);
61
nsr = sattrs.ns && r;
62
nsrw = sattrs.ns && rw;
63
} else {
64
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/ptw.c
67
+++ b/target/arm/ptw.c
68
@@ -XXX,XX +XXX,XX @@ static bool v8m_is_sau_exempt(CPUARMState *env,
69
}
70
71
void v8m_security_lookup(CPUARMState *env, uint32_t address,
72
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
73
- V8M_SAttributes *sattrs)
74
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
75
+ bool is_secure, V8M_SAttributes *sattrs)
76
{
77
/*
78
* Look up the security attributes for this address. Compare the
79
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
80
}
81
82
if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
83
- sattrs->ns = !regime_is_secure(env, mmu_idx);
84
+ sattrs->ns = !is_secure;
85
return;
86
}
87
88
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
89
bool ret;
90
91
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
92
- v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
93
+ v8m_security_lookup(env, address, access_type, mmu_idx,
94
+ secure, &sattrs);
95
if (access_type == MMU_INST_FETCH) {
96
/*
97
* Instruction fetches always use the MMU bank and the
98
--
99
2.25.1
100
101
diff view generated by jsdifflib
[PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
[PULL 13/39] target/arm: Add secure parameter to pmsav8_mpu_lookup
1
From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
According to the PushStack() pseudocode in the armv7m RM,
3
Remove the use of regime_is_secure from pmsav8_mpu_lookup,
4
bit 4 of the LR should be set to NOT(CONTROL.PFCA) when
4
passing the new parameter to the lookup instead.
5
an FPU is present. Current implementation is doing it for
6
armv8, but not for armv7. This patch makes the existing
7
logic applicable to both code paths.
8
5
9
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-13-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/m_helper.c | 7 +++----
12
target/arm/internals.h | 4 ++--
14
1 file changed, 3 insertions(+), 4 deletions(-)
13
target/arm/m_helper.c | 2 +-
14
target/arm/ptw.c | 7 +++----
15
3 files changed, 6 insertions(+), 7 deletions(-)
15
16
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
20
+++ b/target/arm/internals.h
21
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
22
23
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
26
- uint32_t *mregion);
27
+ bool is_secure, GetPhysAddrResult *result,
28
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
29
30
void arm_log_exception(CPUState *cs);
31
16
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
32
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
17
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/m_helper.c
34
--- a/target/arm/m_helper.c
19
+++ b/target/arm/m_helper.c
35
+++ b/target/arm/m_helper.c
20
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
36
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
21
if (env->v7m.secure) {
37
ARMMMUFaultInfo fi = {};
22
lr |= R_V7M_EXCRET_S_MASK;
38
23
}
39
/* We can ignore the return value as prot is always set */
24
- if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
40
- pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
25
- lr |= R_V7M_EXCRET_FTYPE_MASK;
41
+ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec,
26
- }
42
&res, &fi, &mregion);
27
} else {
43
if (mregion == -1) {
28
lr = R_V7M_EXCRET_RES1_MASK |
44
mrvalid = false;
29
R_V7M_EXCRET_S_MASK |
45
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
30
R_V7M_EXCRET_DCRS_MASK |
46
index XXXXXXX..XXXXXXX 100644
31
- R_V7M_EXCRET_FTYPE_MASK |
47
--- a/target/arm/ptw.c
32
R_V7M_EXCRET_ES_MASK;
48
+++ b/target/arm/ptw.c
33
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
49
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
34
lr |= R_V7M_EXCRET_SPSEL_MASK;
50
51
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
52
MMUAccessType access_type, ARMMMUIdx mmu_idx,
53
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi,
54
- uint32_t *mregion)
55
+ bool secure, GetPhysAddrResult *result,
56
+ ARMMMUFaultInfo *fi, uint32_t *mregion)
57
{
58
/*
59
* Perform a PMSAv8 MPU lookup (without also doing the SAU check
60
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
61
*/
62
ARMCPU *cpu = env_archcpu(env);
63
bool is_user = regime_is_user(env, mmu_idx);
64
- uint32_t secure = regime_is_secure(env, mmu_idx);
65
int n;
66
int matchregion = -1;
67
bool hit = false;
68
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
35
}
69
}
36
}
70
}
37
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
71
38
+ lr |= R_V7M_EXCRET_FTYPE_MASK;
72
- ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
39
+ }
73
+ ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
40
if (!arm_v7m_is_handler_mode(env)) {
74
result, fi, NULL);
41
lr |= R_V7M_EXCRET_MODE_MASK;
75
if (sattrs.subpage) {
42
}
76
result->page_size = 1;
43
--
77
--
44
2.20.1
78
2.25.1
45
79
46
80
diff view generated by jsdifflib
New patch
[PULL 14/39] target/arm: Add is_secure parameter to get_phys_addr_v5
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the use of regime_is_secure from get_phys_addr_v5,
4
passing the new parameter to the lookup instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
[PMM: Folded in definition of local is_secure in get_phys_addr(),
9
since I dropped the earlier patch that would have provided it]
10
Message-id: 20220822152741.1617527-14-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/ptw.c | 14 +++++++-------
15
1 file changed, 7 insertions(+), 7 deletions(-)
16
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/ptw.c
20
+++ b/target/arm/ptw.c
21
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
22
23
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
24
MMUAccessType access_type, ARMMMUIdx mmu_idx,
25
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
26
+ bool is_secure, GetPhysAddrResult *result,
27
+ ARMMMUFaultInfo *fi)
28
{
29
int level = 1;
30
uint32_t table;
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
32
fi->type = ARMFault_Translation;
33
goto do_fault;
34
}
35
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
36
- mmu_idx, fi);
37
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
38
if (fi->type != ARMFault_None) {
39
goto do_fault;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
42
/* Fine pagetable. */
43
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
44
}
45
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
46
- mmu_idx, fi);
47
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
48
if (fi->type != ARMFault_None) {
49
goto do_fault;
50
}
51
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
52
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
53
{
54
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
55
+ bool is_secure = regime_is_secure(env, mmu_idx);
56
57
if (mmu_idx != s1_mmu_idx) {
58
/*
59
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
60
* cannot upgrade an non-secure translation regime's attributes
61
* to secure.
62
*/
63
- result->attrs.secure = regime_is_secure(env, mmu_idx);
64
+ result->attrs.secure = is_secure;
65
result->attrs.user = regime_is_user(env, mmu_idx);
66
67
/*
68
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
69
result, fi);
70
} else {
71
return get_phys_addr_v5(env, address, access_type, mmu_idx,
72
- result, fi);
73
+ is_secure, result, fi);
74
}
75
}
76
77
--
78
2.25.1
79
80
diff view generated by jsdifflib
New patch
[PULL 15/39] target/arm: Add is_secure parameter to get_phys_addr_v6
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the use of regime_is_secure from get_phys_addr_v6,
4
passing the new parameter to the lookup instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-15-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 11 +++++------
13
1 file changed, 5 insertions(+), 6 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ do_fault:
20
21
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
24
+ bool is_secure, GetPhysAddrResult *result,
25
+ ARMMMUFaultInfo *fi)
26
{
27
ARMCPU *cpu = env_archcpu(env);
28
int level = 1;
29
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
30
fi->type = ARMFault_Translation;
31
goto do_fault;
32
}
33
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
34
- mmu_idx, fi);
35
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
36
if (fi->type != ARMFault_None) {
37
goto do_fault;
38
}
39
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
40
ns = extract32(desc, 3, 1);
41
/* Lookup l2 entry. */
42
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
43
- desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx),
44
- mmu_idx, fi);
45
+ desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
46
if (fi->type != ARMFault_None) {
47
goto do_fault;
48
}
49
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
50
result, fi);
51
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
52
return get_phys_addr_v6(env, address, access_type, mmu_idx,
53
- result, fi);
54
+ is_secure, result, fi);
55
} else {
56
return get_phys_addr_v5(env, address, access_type, mmu_idx,
57
is_secure, result, fi);
58
--
59
2.25.1
60
61
diff view generated by jsdifflib
New patch
[PULL 16/39] target/arm: Add secure parameter to get_phys_addr_pmsav8
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the use of regime_is_secure from get_phys_addr_pmsav8.
4
Since we already had a local variable named secure, use that.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-16-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 5 ++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
20
21
static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result,
24
+ bool secure, GetPhysAddrResult *result,
25
ARMMMUFaultInfo *fi)
26
{
27
- uint32_t secure = regime_is_secure(env, mmu_idx);
28
V8M_SAttributes sattrs = {};
29
bool ret;
30
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
32
if (arm_feature(env, ARM_FEATURE_V8)) {
33
/* PMSAv8 */
34
ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
35
- result, fi);
36
+ is_secure, result, fi);
37
} else if (arm_feature(env, ARM_FEATURE_V7)) {
38
/* PMSAv7 */
39
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
New patch
[PULL 17/39] target/arm: Add is_secure parameter to pmsav7_use_background_region
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the use of regime_is_secure from pmsav7_use_background_region,
4
using the new parameter instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-17-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ static bool m_is_system_region(CPUARMState *env, uint32_t address)
20
}
21
22
static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
23
- bool is_user)
24
+ bool is_secure, bool is_user)
25
{
26
/*
27
* Return true if we should use the default memory map as a
28
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
29
}
30
31
if (arm_feature(env, ARM_FEATURE_M)) {
32
- return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
33
- & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
34
+ return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
35
} else {
36
return regime_sctlr(env, mmu_idx) & SCTLR_BR;
37
}
38
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
39
{
40
ARMCPU *cpu = env_archcpu(env);
41
int n;
42
+ bool secure = regime_is_secure(env, mmu_idx);
43
bool is_user = regime_is_user(env, mmu_idx);
44
45
result->phys = address;
46
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
47
}
48
49
if (n == -1) { /* no hits */
50
- if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
51
+ if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
52
/* background fault */
53
fi->type = ARMFault_Background;
54
return true;
55
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
56
} else if (m_is_ppb_region(env, address)) {
57
hit = true;
58
} else {
59
- if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
60
+ if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {
61
hit = true;
62
}
63
64
--
65
2.25.1
66
67
diff view generated by jsdifflib
New patch
[PULL 18/39] target/arm: Add secure parameter to get_phys_addr_pmsav7
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the use of regime_is_secure from get_phys_addr_pmsav7,
4
using the new parameter instead.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220822152741.1617527-19-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 5 ++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
20
21
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
22
MMUAccessType access_type, ARMMMUIdx mmu_idx,
23
- GetPhysAddrResult *result,
24
+ bool secure, GetPhysAddrResult *result,
25
ARMMMUFaultInfo *fi)
26
{
27
ARMCPU *cpu = env_archcpu(env);
28
int n;
29
- bool secure = regime_is_secure(env, mmu_idx);
30
bool is_user = regime_is_user(env, mmu_idx);
31
32
result->phys = address;
33
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
34
} else if (arm_feature(env, ARM_FEATURE_V7)) {
35
/* PMSAv7 */
36
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
37
- result, fi);
38
+ is_secure, result, fi);
39
} else {
40
/* Pre-v7 MPU */
41
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
[PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
[PULL 19/39] target/arm: Add is_secure parameter to get_phys_addr_pmsav5
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add the CRP as unimplemented thus avoiding bus errors when
3
Remove the use of regime_is_secure from get_phys_addr_pmsav5.
4
guests access these registers.
5
4
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Message-id: 20220822152741.1617527-21-richard.henderson@linaro.org
9
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
include/hw/arm/xlnx-versal.h | 3 +++
11
target/arm/ptw.c | 4 ++--
13
hw/arm/xlnx-versal.c | 2 ++
12
1 file changed, 2 insertions(+), 2 deletions(-)
14
2 files changed, 5 insertions(+)
15
13
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
16
--- a/target/arm/ptw.c
19
+++ b/include/hw/arm/xlnx-versal.h
17
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
18
@@ -XXX,XX +XXX,XX @@ do_fault:
21
#define MM_IOU_SCNTRS_SIZE 0x10000
19
22
#define MM_FPD_CRF 0xfd1a0000U
20
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
23
#define MM_FPD_CRF_SIZE 0x140000
21
MMUAccessType access_type, ARMMMUIdx mmu_idx,
24
+
22
- GetPhysAddrResult *result,
25
+#define MM_PMC_CRP 0xf1260000U
23
+ bool is_secure, GetPhysAddrResult *result,
26
+#define MM_PMC_CRP_SIZE 0x10000
24
ARMMMUFaultInfo *fi)
27
#endif
25
{
28
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
26
int n;
29
index XXXXXXX..XXXXXXX 100644
27
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
30
--- a/hw/arm/xlnx-versal.c
28
} else {
31
+++ b/hw/arm/xlnx-versal.c
29
/* Pre-v7 MPU */
32
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
30
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
33
MM_CRL, MM_CRL_SIZE);
31
- result, fi);
34
versal_unimp_area(s, "crf", &s->mr_ps,
32
+ is_secure, result, fi);
35
MM_FPD_CRF, MM_FPD_CRF_SIZE);
33
}
36
+ versal_unimp_area(s, "crp", &s->mr_ps,
34
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
37
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
35
" mmu_idx %u -> %s (prot %c%c%c)\n",
38
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
39
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
40
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
41
--
36
--
42
2.20.1
37
2.25.1
43
38
44
39
diff view generated by jsdifflib
New patch
[PULL 20/39] hw/acpi: Add ospm_status hook implementation for acpi-ged
1
From: Keqian Zhu <zhukeqian1@huawei.com>
1
2
3
Setup an ARM virtual machine of machine virt and execute qmp "query-acpi-ospm-status"
4
causes segmentation fault with following dumpstack:
5
#1 0x0000aaaaab64235c in qmp_query_acpi_ospm_status (errp=errp@entry=0xfffffffff030) at ../monitor/qmp-cmds.c:312
6
#2 0x0000aaaaabfc4e20 in qmp_marshal_query_acpi_ospm_status (args=<optimized out>, ret=0xffffea4ffe90, errp=0xffffea4ffe88) at qapi/qapi-commands-acpi.c:63
7
#3 0x0000aaaaabff8ba0 in do_qmp_dispatch_bh (opaque=0xffffea4ffe98) at ../qapi/qmp-dispatch.c:128
8
#4 0x0000aaaaac02e594 in aio_bh_call (bh=0xffffe0004d80) at ../util/async.c:150
9
#5 aio_bh_poll (ctx=ctx@entry=0xaaaaad0f6040) at ../util/async.c:178
10
#6 0x0000aaaaac00bd40 in aio_dispatch (ctx=ctx@entry=0xaaaaad0f6040) at ../util/aio-posix.c:421
11
#7 0x0000aaaaac02e010 in aio_ctx_dispatch (source=0xaaaaad0f6040, callback=<optimized out>, user_data=<optimized out>) at ../util/async.c:320
12
#8 0x0000fffff76f6884 in g_main_context_dispatch () at /usr/lib64/libglib-2.0.so.0
13
#9 0x0000aaaaac0452d4 in glib_pollfds_poll () at ../util/main-loop.c:297
14
#10 os_host_main_loop_wait (timeout=0) at ../util/main-loop.c:320
15
#11 main_loop_wait (nonblocking=nonblocking@entry=0) at ../util/main-loop.c:596
16
#12 0x0000aaaaab5c9e50 in qemu_main_loop () at ../softmmu/runstate.c:734
17
#13 0x0000aaaaab185370 in qemu_main (argc=argc@entry=47, argv=argv@entry=0xfffffffff518, envp=envp@entry=0x0) at ../softmmu/main.c:38
18
#14 0x0000aaaaab16f99c in main (argc=47, argv=0xfffffffff518) at ../softmmu/main.c:47
19
20
Fixes: ebb62075021a ("hw/acpi: Add ACPI Generic Event Device Support")
21
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
22
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
23
Message-id: 20220816094957.31700-1-zhukeqian1@huawei.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
hw/acpi/generic_event_device.c | 8 ++++++++
27
1 file changed, 8 insertions(+)
28
29
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/acpi/generic_event_device.c
32
+++ b/hw/acpi/generic_event_device.c
33
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
34
}
35
}
36
37
+static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
38
+{
39
+ AcpiGedState *s = ACPI_GED(adev);
40
+
41
+ acpi_memory_ospm_status(&s->memhp_state, list);
42
+}
43
+
44
static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
45
{
46
AcpiGedState *s = ACPI_GED(adev);
47
@@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data)
48
hc->unplug_request = acpi_ged_unplug_request_cb;
49
hc->unplug = acpi_ged_unplug_cb;
50
51
+ adevc->ospm_status = acpi_ged_ospm_status;
52
adevc->send_event = acpi_ged_send_event;
53
}
54
55
--
56
2.25.1
diff view generated by jsdifflib
New patch
[PULL 21/39] hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
1
From: Lucas Dietrich <ld.adecy@gmail.com>
1
2
3
The LAN9118 allows the guest to specify a level for both the TX and
4
RX FIFOs at which an interrupt will be generated. We implement the
5
RSFL_INT interrupt for the RX FIFO but are missing the handling of
6
the equivalent TSFL_INT for the TX FIFO. Add the missing test to set
7
the interrupt if the TX FIFO has exceeded the guest-specified level.
8
9
This flag is required for Micrium lan911x ethernet driver to work.
10
11
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
12
[PMM: Tweaked commit message and comment]
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/net/lan9118.c | 8 ++++++++
17
1 file changed, 8 insertions(+)
18
19
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/lan9118.c
22
+++ b/hw/net/lan9118.c
23
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
24
n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
25
s->tx_status_fifo[n] = status;
26
s->tx_status_fifo_used++;
27
+
28
+ /*
29
+ * Generate TSFL interrupt if TX FIFO level exceeds the level
30
+ * specified in the FIFO_INT TX Status Level field.
31
+ */
32
+ if (s->tx_status_fifo_used > ((s->fifo_int >> 16) & 0xff)) {
33
+ s->int_sts |= TSFL_INT;
34
+ }
35
if (s->tx_status_fifo_used == 512) {
36
s->int_sts |= TSFF_INT;
37
/* TODO: Stop transmission. */
38
--
39
2.25.1
diff view generated by jsdifflib
New patch
[PULL 22/39] chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Replace '84' magic value by the X_MAX definition, and '1' by Y_MAX.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-2-peter.maydell@linaro.org
10
---
11
chardev/baum.c | 11 +++++++----
12
1 file changed, 7 insertions(+), 4 deletions(-)
13
14
diff --git a/chardev/baum.c b/chardev/baum.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/chardev/baum.c
17
+++ b/chardev/baum.c
18
@@ -XXX,XX +XXX,XX @@
19
20
#define BUF_SIZE 256
21
22
+#define X_MAX 84
23
+#define Y_MAX 1
24
+
25
struct BaumChardev {
26
Chardev parent;
27
28
@@ -XXX,XX +XXX,XX @@ static int baum_deferred_init(BaumChardev *baum)
29
brlapi_perror("baum: brlapi__getDisplaySize");
30
return 0;
31
}
32
- if (baum->y > 1) {
33
- baum->y = 1;
34
+ if (baum->y > Y_MAX) {
35
+ baum->y = Y_MAX;
36
}
37
- if (baum->x > 84) {
38
- baum->x = 84;
39
+ if (baum->x > X_MAX) {
40
+ baum->x = X_MAX;
41
}
42
43
con = qemu_console_lookup_by_index(0);
44
--
45
2.25.1
46
47
diff view generated by jsdifflib
New patch
[PULL 23/39] chardev/baum: Use definitions to avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
We know 'x * y' will be at most 'X_MAX * Y_MAX' (which is not
4
a big value, it is actually 84). Instead of having the compiler
5
use variable-length array, declare an array able to hold the
6
maximum 'x * y'.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
10
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20220819153931.3147384-3-peter.maydell@linaro.org
13
---
14
chardev/baum.c | 8 ++++----
15
1 file changed, 4 insertions(+), 4 deletions(-)
16
17
diff --git a/chardev/baum.c b/chardev/baum.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/chardev/baum.c
20
+++ b/chardev/baum.c
21
@@ -XXX,XX +XXX,XX @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
22
switch (req) {
23
case BAUM_REQ_DisplayData:
24
{
25
- uint8_t cells[baum->x * baum->y], c;
26
- uint8_t text[baum->x * baum->y];
27
- uint8_t zero[baum->x * baum->y];
28
+ uint8_t cells[X_MAX * Y_MAX], c;
29
+ uint8_t text[X_MAX * Y_MAX];
30
+ uint8_t zero[X_MAX * Y_MAX];
31
int cursor = BRLAPI_CURSOR_OFF;
32
int i;
33
34
@@ -XXX,XX +XXX,XX @@ static int baum_eat_packet(BaumChardev *baum, const uint8_t *buf, int len)
35
}
36
timer_del(baum->cellCount_timer);
37
38
- memset(zero, 0, sizeof(zero));
39
+ memset(zero, 0, baum->x * baum->y);
40
41
brlapi_writeArguments_t wa = {
42
.displayNumber = BRLAPI_DISPLAY_DEFAULT,
43
--
44
2.25.1
45
46
diff view generated by jsdifflib
New patch
[PULL 24/39] chardev/baum: Avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
8
Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-4-peter.maydell@linaro.org
11
---
12
chardev/baum.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/chardev/baum.c b/chardev/baum.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/chardev/baum.c
18
+++ b/chardev/baum.c
19
@@ -XXX,XX +XXX,XX @@ static void baum_chr_accept_input(struct Chardev *chr)
20
static void baum_write_packet(BaumChardev *baum, const uint8_t *buf, int len)
21
{
22
Chardev *chr = CHARDEV(baum);
23
- uint8_t io_buf[1 + 2 * len], *cur = io_buf;
24
+ g_autofree uint8_t *io_buf = g_malloc(1 + 2 * len);
25
+ uint8_t *cur = io_buf;
26
int room;
27
*cur++ = ESC;
28
while (len--)
29
--
30
2.25.1
31
32
diff view generated by jsdifflib
New patch
[PULL 25/39] io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
The combined_key[... QIO_CHANNEL_WEBSOCK_GUID_LEN ...] array in
4
qio_channel_websock_handshake_send_res_ok() expands to a call
5
to strlen(QIO_CHANNEL_WEBSOCK_GUID), and the compiler doesn't
6
realize the string is const, so consider combined_key[] being
7
a variable-length array.
8
9
To remove the variable-length array, we provide it a hint to
10
the compiler by using sizeof() - 1 instead of strlen().
11
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20220819153931.3147384-5-peter.maydell@linaro.org
16
---
17
io/channel-websock.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/io/channel-websock.c b/io/channel-websock.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/io/channel-websock.c
23
+++ b/io/channel-websock.c
24
@@ -XXX,XX +XXX,XX @@
25
26
#define QIO_CHANNEL_WEBSOCK_CLIENT_KEY_LEN 24
27
#define QIO_CHANNEL_WEBSOCK_GUID "258EAFA5-E914-47DA-95CA-C5AB0DC85B11"
28
-#define QIO_CHANNEL_WEBSOCK_GUID_LEN strlen(QIO_CHANNEL_WEBSOCK_GUID)
29
+#define QIO_CHANNEL_WEBSOCK_GUID_LEN (sizeof(QIO_CHANNEL_WEBSOCK_GUID) - 1)
30
31
#define QIO_CHANNEL_WEBSOCK_HEADER_PROTOCOL "sec-websocket-protocol"
32
#define QIO_CHANNEL_WEBSOCK_HEADER_VERSION "sec-websocket-version"
33
--
34
2.25.1
35
36
diff view generated by jsdifflib
New patch
[PULL 26/39] hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
The compiler isn't clever enough to figure 'min_buf_size'
4
is a constant, so help it by using a definitions instead.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: Jason Wang <jasowang@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-6-peter.maydell@linaro.org
11
---
12
hw/net/e1000e_core.c | 7 ++++---
13
1 file changed, 4 insertions(+), 3 deletions(-)
14
15
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/e1000e_core.c
18
+++ b/hw/net/e1000e_core.c
19
@@ -XXX,XX +XXX,XX @@ e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
20
}
21
}
22
23
+/* Min. octets in an ethernet frame sans FCS */
24
+#define MIN_BUF_SIZE 60
25
+
26
ssize_t
27
e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
28
{
29
static const int maximum_ethernet_hdr_len = (14 + 4);
30
- /* Min. octets in an ethernet frame sans FCS */
31
- static const int min_buf_size = 60;
32
33
uint32_t n = 0;
34
- uint8_t min_buf[min_buf_size];
35
+ uint8_t min_buf[MIN_BUF_SIZE];
36
struct iovec min_iov;
37
uint8_t *filter_buf;
38
size_t size, orig_size;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
New patch
[PULL 27/39] hw/ppc/pnv: Avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: David Gibson <david@gibson.dropbear.id.au>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
11
Message-id: 20220819153931.3147384-7-peter.maydell@linaro.org
12
---
13
hw/ppc/pnv.c | 4 ++--
14
hw/ppc/spapr.c | 8 ++++----
15
hw/ppc/spapr_pci_nvlink2.c | 2 +-
16
3 files changed, 7 insertions(+), 7 deletions(-)
17
18
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ppc/pnv.c
21
+++ b/hw/ppc/pnv.c
22
@@ -XXX,XX +XXX,XX @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
23
int smt_threads = CPU_CORE(pc)->nr_threads;
24
CPUPPCState *env = &cpu->env;
25
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
26
- uint32_t servers_prop[smt_threads];
27
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
28
int i;
29
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
30
0xffffffff, 0xffffffff};
31
@@ -XXX,XX +XXX,XX @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
32
servers_prop[i] = cpu_to_be32(pc->pir + i);
33
}
34
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
35
- servers_prop, sizeof(servers_prop))));
36
+ servers_prop, sizeof(*servers_prop) * smt_threads)));
37
}
38
39
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
40
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/ppc/spapr.c
43
+++ b/hw/ppc/spapr.c
44
@@ -XXX,XX +XXX,XX @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
45
int smt_threads)
46
{
47
int i, ret = 0;
48
- uint32_t servers_prop[smt_threads];
49
- uint32_t gservers_prop[smt_threads * 2];
50
+ g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
51
+ g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2);
52
int index = spapr_get_vcpu_id(cpu);
53
54
if (cpu->compat_pvr) {
55
@@ -XXX,XX +XXX,XX @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
56
gservers_prop[i*2 + 1] = 0;
57
}
58
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
59
- servers_prop, sizeof(servers_prop));
60
+ servers_prop, sizeof(*servers_prop) * smt_threads);
61
if (ret < 0) {
62
return ret;
63
}
64
ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
65
- gservers_prop, sizeof(gservers_prop));
66
+ gservers_prop, sizeof(*gservers_prop) * smt_threads * 2);
67
68
return ret;
69
}
70
diff --git a/hw/ppc/spapr_pci_nvlink2.c b/hw/ppc/spapr_pci_nvlink2.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/ppc/spapr_pci_nvlink2.c
73
+++ b/hw/ppc/spapr_pci_nvlink2.c
74
@@ -XXX,XX +XXX,XX @@ void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
75
continue;
76
}
77
if (dev == nvslot->gpdev) {
78
- uint32_t npus[nvslot->linknum];
79
+ g_autofree uint32_t *npus = g_new(uint32_t, nvslot->linknum);
80
81
for (j = 0; j < nvslot->linknum; ++j) {
82
PCIDevice *npdev = nvslot->links[j].npdev;
83
--
84
2.25.1
85
86
diff view generated by jsdifflib
New patch
[PULL 28/39] hw/intc/xics: Avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: David Gibson <david@gibson.dropbear.id.au>
8
Reviewed-by: Greg Kurz <groug@kaod.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220819153931.3147384-8-peter.maydell@linaro.org
11
---
12
hw/intc/xics.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/xics.c
18
+++ b/hw/intc/xics.c
19
@@ -XXX,XX +XXX,XX @@ static void ics_reset_irq(ICSIRQState *irq)
20
static void ics_reset(DeviceState *dev)
21
{
22
ICSState *ics = ICS(dev);
23
+ g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
24
int i;
25
- uint8_t flags[ics->nr_irqs];
26
27
for (i = 0; i < ics->nr_irqs; i++) {
28
flags[i] = ics->irqs[i].flags;
29
--
30
2.25.1
31
32
diff view generated by jsdifflib
New patch
[PULL 29/39] hw/i386/multiboot: Avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use autofree heap allocation instead of variable-length array on
4
the stack. Replace the snprintf() call by g_strdup_printf().
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-9-peter.maydell@linaro.org
10
---
11
hw/i386/multiboot.c | 5 ++---
12
1 file changed, 2 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/i386/multiboot.c
17
+++ b/hw/i386/multiboot.c
18
@@ -XXX,XX +XXX,XX @@ int load_multiboot(X86MachineState *x86ms,
19
uint8_t *mb_bootinfo_data;
20
uint32_t cmdline_len;
21
GList *mods = NULL;
22
+ g_autofree char *kcmdline = NULL;
23
24
/* Ok, let's see if it is a multiboot image.
25
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
26
@@ -XXX,XX +XXX,XX @@ int load_multiboot(X86MachineState *x86ms,
27
}
28
29
/* Commandline support */
30
- char kcmdline[strlen(kernel_filename) + strlen(kernel_cmdline) + 2];
31
- snprintf(kcmdline, sizeof(kcmdline), "%s %s",
32
- kernel_filename, kernel_cmdline);
33
+ kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline);
34
stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline));
35
36
stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name));
37
--
38
2.25.1
39
40
diff view generated by jsdifflib
New patch
[PULL 30/39] hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
The compiler isn't clever enough to figure 'width' is a constant,
4
so help it by using a definitions instead.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-10-peter.maydell@linaro.org
10
---
11
hw/usb/hcd-ohci.c | 7 ++++---
12
1 file changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/usb/hcd-ohci.c
17
+++ b/hw/usb/hcd-ohci.c
18
@@ -XXX,XX +XXX,XX @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
19
return 1;
20
}
21
22
+#define HEX_CHAR_PER_LINE 16
23
+
24
static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
25
{
26
bool print16;
27
bool printall;
28
- const int width = 16;
29
int i;
30
- char tmp[3 * width + 1];
31
+ char tmp[3 * HEX_CHAR_PER_LINE + 1];
32
char *p = tmp;
33
34
print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
35
@@ -XXX,XX +XXX,XX @@ static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
36
}
37
38
for (i = 0; ; i++) {
39
- if (i && (!(i % width) || (i == len))) {
40
+ if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) {
41
if (!printall) {
42
trace_usb_ohci_td_pkt_short(msg, tmp);
43
break;
44
--
45
2.25.1
46
47
diff view generated by jsdifflib
New patch
[PULL 31/39] ui/curses: Avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-11-peter.maydell@linaro.org
10
---
11
ui/curses.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/ui/curses.c b/ui/curses.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/ui/curses.c
17
+++ b/ui/curses.c
18
@@ -XXX,XX +XXX,XX @@ static void curses_update(DisplayChangeListener *dcl,
19
int x, int y, int w, int h)
20
{
21
console_ch_t *line;
22
- cchar_t curses_line[width];
23
+ g_autofree cchar_t *curses_line = g_new(cchar_t, width);
24
wchar_t wch[CCHARW_MAX];
25
attr_t attrs;
26
short colors;
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
New patch
[PULL 32/39] tests/unit/test-vmstate: Avoid dynamic stack allocation
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use autofree heap allocation instead of variable-length
4
array on the stack.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220819153931.3147384-12-peter.maydell@linaro.org
10
---
11
tests/unit/test-vmstate.c | 7 +++----
12
1 file changed, 3 insertions(+), 4 deletions(-)
13
14
diff --git a/tests/unit/test-vmstate.c b/tests/unit/test-vmstate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/unit/test-vmstate.c
17
+++ b/tests/unit/test-vmstate.c
18
@@ -XXX,XX +XXX,XX @@ static void save_buffer(const uint8_t *buf, size_t buf_size)
19
static void compare_vmstate(const uint8_t *wire, size_t size)
20
{
21
QEMUFile *f = open_test_file(false);
22
- uint8_t result[size];
23
+ g_autofree uint8_t *result = g_malloc(size);
24
25
/* read back as binary */
26
27
- g_assert_cmpint(qemu_get_buffer(f, result, sizeof(result)), ==,
28
- sizeof(result));
29
+ g_assert_cmpint(qemu_get_buffer(f, result, size), ==, size);
30
g_assert(!qemu_file_get_error(f));
31
32
/* Compare that what is on the file is the same that what we
33
expected to be there */
34
- SUCCESS(memcmp(result, wire, sizeof(result)));
35
+ SUCCESS(memcmp(result, wire, size));
36
37
/* Must reach EOF */
38
qemu_get_byte(f);
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
New patch
[PULL 33/39] configure: Remove unused python_version variable
1
Shellcheck correctly reports that we set python_version and never use
2
it. This is a leftover from commit f9332757898a7: we used to use
3
python_version purely to as part of the summary information printed
4
at the end of a configure run, and that commit changed to printing
5
the information from meson (which looks up the python version
6
itself). Remove the unused variable.
1
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20220825150703.4074125-2-peter.maydell@linaro.org
12
---
13
configure | 3 ---
14
1 file changed, 3 deletions(-)
15
16
diff --git a/configure b/configure
17
index XXXXXXX..XXXXXXX 100755
18
--- a/configure
19
+++ b/configure
20
@@ -XXX,XX +XXX,XX @@ if ! $python -c 'import sys; sys.exit(sys.version_info < (3,6))'; then
21
"Use --python=/path/to/python to specify a supported Python."
22
fi
23
24
-# Preserve python version since some functionality is dependent on it
25
-python_version=$($python -c 'import sys; print("%d.%d.%d" % (sys.version_info[0], sys.version_info[1], sys.version_info[2]))' 2>/dev/null)
26
-
27
# Suppress writing compiled files
28
python="$python -B"
29
30
--
31
2.25.1
32
33
diff view generated by jsdifflib
New patch
[PULL 34/39] configure: Remove unused meson_args variable
1
The meson_args variable was added in commit 3b4da13293482134b, but
2
was not used in that commit and isn't used today. Delete the
3
unnecessary assignment.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220825150703.4074125-3-peter.maydell@linaro.org
9
---
10
configure | 1 -
11
1 file changed, 1 deletion(-)
12
13
diff --git a/configure b/configure
14
index XXXXXXX..XXXXXXX 100755
15
--- a/configure
16
+++ b/configure
17
@@ -XXX,XX +XXX,XX @@ pie=""
18
coroutine=""
19
plugins="$default_feature"
20
meson=""
21
-meson_args=""
22
ninja=""
23
bindir="bin"
24
skip_meson=no
25
--
26
2.25.1
27
28
diff view generated by jsdifflib
New patch
[PULL 35/39] configure: Add missing quoting for some easy cases
1
1
This commit adds quotes in some places which:
2
* are spotted by shellcheck
3
* are obviously incorrect
4
* are easy to fix just by adding the quotes
5
6
It doesn't attempt fix all of the places shellcheck finds errors,
7
or even all the ones which are easy to fix. It's just a random
8
sampling which is hopefully easy to review and which cuts
9
down the size of the problem for next time somebody wants to
10
try to look at shellcheck errors.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20220825150703.4074125-4-peter.maydell@linaro.org
16
---
17
configure | 64 +++++++++++++++++++++++++++----------------------------
18
1 file changed, 32 insertions(+), 32 deletions(-)
19
20
diff --git a/configure b/configure
21
index XXXXXXX..XXXXXXX 100755
22
--- a/configure
23
+++ b/configure
24
@@ -XXX,XX +XXX,XX @@ GNUmakefile: ;
25
26
EOF
27
cd build
28
- exec $source_path/configure "$@"
29
+ exec "$source_path/configure" "$@"
30
fi
31
32
# Temporary directory used for files created while
33
@@ -XXX,XX +XXX,XX @@ meson_option_build_array() {
34
printf ']\n'
35
}
36
37
-. $source_path/scripts/meson-buildoptions.sh
38
+. "$source_path/scripts/meson-buildoptions.sh"
39
40
meson_options=
41
meson_option_add() {
42
@@ -XXX,XX +XXX,XX @@ for opt do
43
case "$opt" in
44
--help|-h) show_help=yes
45
;;
46
- --version|-V) exec cat $source_path/VERSION
47
+ --version|-V) exec cat "$source_path/VERSION"
48
;;
49
--prefix=*) prefix="$optarg"
50
;;
51
@@ -XXX,XX +XXX,XX @@ default_target_list=""
52
mak_wilds=""
53
54
if [ "$linux_user" != no ]; then
55
- if [ "$targetos" = linux ] && [ -d $source_path/linux-user/include/host/$cpu ]; then
56
+ if [ "$targetos" = linux ] && [ -d "$source_path/linux-user/include/host/$cpu" ]; then
57
linux_user=yes
58
elif [ "$linux_user" = yes ]; then
59
error_exit "linux-user not supported on this architecture"
60
@@ -XXX,XX +XXX,XX @@ if [ "$bsd_user" != no ]; then
61
if [ "$bsd_user" = "" ]; then
62
test $targetos = freebsd && bsd_user=yes
63
fi
64
- if [ "$bsd_user" = yes ] && ! [ -d $source_path/bsd-user/$targetos ]; then
65
+ if [ "$bsd_user" = yes ] && ! [ -d "$source_path/bsd-user/$targetos" ]; then
66
error_exit "bsd-user not supported on this host OS"
67
fi
68
fi
69
@@ -XXX,XX +XXX,XX @@ python="$python -B"
70
if test -z "$meson"; then
71
if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.59.3; then
72
meson=meson
73
- elif test $git_submodules_action != 'ignore' ; then
74
+ elif test "$git_submodules_action" != 'ignore' ; then
75
meson=git
76
elif test -e "${source_path}/meson/meson.py" ; then
77
meson=internal
78
@@ -XXX,XX +XXX,XX @@ esac
79
container="no"
80
if test $use_containers = "yes"; then
81
if has "docker" || has "podman"; then
82
- container=$($python $source_path/tests/docker/docker.py probe)
83
+ container=$($python "$source_path"/tests/docker/docker.py probe)
84
fi
85
fi
86
87
@@ -XXX,XX +XXX,XX @@ if test "$QEMU_GA_DISTRO" = ""; then
88
QEMU_GA_DISTRO=Linux
89
fi
90
if test "$QEMU_GA_VERSION" = ""; then
91
- QEMU_GA_VERSION=$(cat $source_path/VERSION)
92
+ QEMU_GA_VERSION=$(cat "$source_path"/VERSION)
93
fi
94
95
96
@@ -XXX,XX +XXX,XX @@ fi
97
for target in $target_list; do
98
target_dir="$target"
99
target_name=$(echo $target | cut -d '-' -f 1)$EXESUF
100
- mkdir -p $target_dir
101
+ mkdir -p "$target_dir"
102
case $target in
103
*-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" ;;
104
*) symlink "../qemu-system-$target_name" "$target_dir/qemu-system-$target_name" ;;
105
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
106
config_target_mak=tests/tcg/config-$target.mak
107
108
echo "# Automatically generated by configure - do not modify" > $config_target_mak
109
- echo "TARGET_NAME=$arch" >> $config_target_mak
110
+ echo "TARGET_NAME=$arch" >> "$config_target_mak"
111
case $target in
112
xtensa*-linux-user)
113
# the toolchain is not complete with headers, only build softmmu tests
114
continue
115
;;
116
*-softmmu)
117
- test -f $source_path/tests/tcg/$arch/Makefile.softmmu-target || continue
118
+ test -f "$source_path/tests/tcg/$arch/Makefile.softmmu-target" || continue
119
qemu="qemu-system-$arch"
120
;;
121
*-linux-user|*-bsd-user)
122
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
123
# compilers is a requirememt for adding a new test that needs a
124
# compiler feature.
125
126
- echo "BUILD_STATIC=$build_static" >> $config_target_mak
127
- write_target_makefile >> $config_target_mak
128
+ echo "BUILD_STATIC=$build_static" >> "$config_target_mak"
129
+ write_target_makefile >> "$config_target_mak"
130
case $target in
131
aarch64-*)
132
if do_compiler "$target_cc" $target_cflags \
133
-march=armv8.1-a+sve -o $TMPE $TMPC; then
134
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
135
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
136
fi
137
if do_compiler "$target_cc" $target_cflags \
138
-march=armv8.1-a+sve2 -o $TMPE $TMPC; then
139
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
140
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
141
fi
142
if do_compiler "$target_cc" $target_cflags \
143
-march=armv8.3-a -o $TMPE $TMPC; then
144
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
145
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
146
fi
147
if do_compiler "$target_cc" $target_cflags \
148
-mbranch-protection=standard -o $TMPE $TMPC; then
149
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
150
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
151
fi
152
if do_compiler "$target_cc" $target_cflags \
153
-march=armv8.5-a+memtag -o $TMPE $TMPC; then
154
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
155
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
156
fi
157
;;
158
ppc*)
159
if do_compiler "$target_cc" $target_cflags \
160
-mpower8-vector -o $TMPE $TMPC; then
161
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
162
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
163
fi
164
if do_compiler "$target_cc" $target_cflags \
165
-mpower10 -o $TMPE $TMPC; then
166
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
167
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
168
fi
169
;;
170
i386-linux-user)
171
if do_compiler "$target_cc" $target_cflags \
172
-Werror -fno-pie -o $TMPE $TMPC; then
173
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
174
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
175
fi
176
;;
177
esac
178
elif test -n "$container_image"; then
179
echo "build-tcg-tests-$target: docker-image-$container_image" >> $makefile
180
- echo "BUILD_STATIC=y" >> $config_target_mak
181
- write_container_target_makefile >> $config_target_mak
182
+ echo "BUILD_STATIC=y" >> "$config_target_mak"
183
+ write_container_target_makefile >> "$config_target_mak"
184
case $target in
185
aarch64-*)
186
- echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
187
- echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
188
- echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
189
- echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
190
- echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
191
+ echo "CROSS_CC_HAS_SVE=y" >> "$config_target_mak"
192
+ echo "CROSS_CC_HAS_SVE2=y" >> "$config_target_mak"
193
+ echo "CROSS_CC_HAS_ARMV8_3=y" >> "$config_target_mak"
194
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> "$config_target_mak"
195
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> "$config_target_mak"
196
;;
197
ppc*)
198
- echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> $config_target_mak
199
- echo "CROSS_CC_HAS_POWER10=y" >> $config_target_mak
200
+ echo "CROSS_CC_HAS_POWER8_VECTOR=y" >> "$config_target_mak"
201
+ echo "CROSS_CC_HAS_POWER10=y" >> "$config_target_mak"
202
;;
203
i386-linux-user)
204
- echo "CROSS_CC_HAS_I386_NOPIE=y" >> $config_target_mak
205
+ echo "CROSS_CC_HAS_I386_NOPIE=y" >> "$config_target_mak"
206
;;
207
esac
208
got_cross_cc=yes
209
fi
210
if test $got_cross_cc = yes; then
211
mkdir -p tests/tcg/$target
212
- echo "QEMU=$PWD/$qemu" >> $config_target_mak
213
+ echo "QEMU=$PWD/$qemu" >> "$config_target_mak"
214
echo "run-tcg-tests-$target: $qemu\$(EXESUF)" >> $makefile
215
tcg_tests_targets="$tcg_tests_targets $target"
216
fi
217
--
218
2.25.1
219
220
diff view generated by jsdifflib
New patch
[PULL 36/39] configure: Add './' on front of glob of */config-devices.mak.d
1
Shellcheck warns that in
2
rm -f */config-devices.mak.d
3
the glob might expand to something with a '-' in it, which would
4
then be misinterpreted as an option to rm. Fix this by adding './'.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20220825150703.4074125-5-peter.maydell@linaro.org
10
---
11
configure | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/configure b/configure
15
index XXXXXXX..XXXXXXX 100755
16
--- a/configure
17
+++ b/configure
18
@@ -XXX,XX +XXX,XX @@ exit 0
19
fi
20
21
# Remove old dependency files to make sure that they get properly regenerated
22
-rm -f */config-devices.mak.d
23
+rm -f ./*/config-devices.mak.d
24
25
if test -z "$python"
26
then
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
New patch
[PULL 37/39] configure: Remove use of backtick `...` syntax
1
There's only one place in configure where we use `...` to execute a
2
command and capture the result. Switch to $() to match the rest of
3
the script. This silences a shellcheck warning.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220825150703.4074125-6-peter.maydell@linaro.org
9
---
10
configure | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/configure b/configure
14
index XXXXXXX..XXXXXXX 100755
15
--- a/configure
16
+++ b/configure
17
@@ -XXX,XX +XXX,XX @@ LINKS="$LINKS python"
18
LINKS="$LINKS contrib/plugins/Makefile "
19
for f in $LINKS ; do
20
if [ -e "$source_path/$f" ]; then
21
- mkdir -p `dirname ./$f`
22
+ mkdir -p "$(dirname ./"$f")"
23
symlink "$source_path/$f" "$f"
24
fi
25
done
26
--
27
2.25.1
28
29
diff view generated by jsdifflib
New patch
[PULL 38/39] configure: Check mkdir result directly, not via $?
1
Shellcheck warns that we have one place where we run a command and
2
then check if it failed using $?; this is better written to simply
3
check the command in the 'if' statement directly.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220825150703.4074125-7-peter.maydell@linaro.org
9
---
10
configure | 3 +--
11
1 file changed, 1 insertion(+), 2 deletions(-)
12
13
diff --git a/configure b/configure
14
index XXXXXXX..XXXXXXX 100755
15
--- a/configure
16
+++ b/configure
17
@@ -XXX,XX +XXX,XX @@ fi
18
# it when configure exits.)
19
TMPDIR1="config-temp"
20
rm -rf "${TMPDIR1}"
21
-mkdir -p "${TMPDIR1}"
22
-if [ $? -ne 0 ]; then
23
+if ! mkdir -p "${TMPDIR1}"; then
24
echo "ERROR: failed to create temporary directory"
25
exit 1
26
fi
27
--
28
2.25.1
29
30
diff view generated by jsdifflib
New patch
[PULL 39/39] configure: Avoid use of 'local' as it is non-POSIX
1
We use the non-POSIX 'local' keyword in just two places in configure;
2
rewrite to avoid it.
1
3
4
In do_compiler(), just drop the 'local' keyword. The variable
5
'compiler' is only used elsewhere in the do_compiler_werror()
6
function, which already uses the variable as a normal non-local one.
7
8
In probe_target_compiler(), $try and $t are both local; make them
9
normal variables and use a more obviously distinct variable name
10
for $t.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20220825150703.4074125-8-peter.maydell@linaro.org
16
---
17
configure | 7 +++----
18
1 file changed, 3 insertions(+), 4 deletions(-)
19
20
diff --git a/configure b/configure
21
index XXXXXXX..XXXXXXX 100755
22
--- a/configure
23
+++ b/configure
24
@@ -XXX,XX +XXX,XX @@ error_exit() {
25
do_compiler() {
26
# Run the compiler, capturing its output to the log. First argument
27
# is compiler binary to execute.
28
- local compiler="$1"
29
+ compiler="$1"
30
shift
31
if test -n "$BASH_VERSION"; then eval '
32
echo >>config.log "
33
@@ -XXX,XX +XXX,XX @@ probe_target_compiler() {
34
: ${container_cross_strip:=${container_cross_prefix}strip}
35
done
36
37
- local t try
38
try=cross
39
case "$target_arch:$cpu" in
40
aarch64_be:aarch64 | \
41
@@ -XXX,XX +XXX,XX @@ probe_target_compiler() {
42
try='native cross' ;;
43
esac
44
eval "target_cflags=\${cross_cc_cflags_$target_arch}"
45
- for t in $try; do
46
- case $t in
47
+ for thistry in $try; do
48
+ case $thistry in
49
native)
50
target_cc=$cc
51
target_ccas=$ccas
52
--
53
2.25.1
54
55
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.